mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MTB_ADV_WISE_1530/core_cm3.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:: Anna Bridge
Date:: Fri Jun 22 15:38:59 2018 +0100
Revision:: 169:a7c7b631e539
Parent:: 167:84c0a372a020

mbed library. Release version 162

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	167:84c0a372a020	1	/************************************************************************//
AnnaBridge	167:84c0a372a020	2	* @file core_cm3.h
AnnaBridge	167:84c0a372a020	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
Anna Bridge	169:a7c7b631e539	4	* @version V5.0.5
Anna Bridge	169:a7c7b631e539	5	* @date 08. January 2018
AnnaBridge	167:84c0a372a020	6	******************************************************************************/
AnnaBridge	167:84c0a372a020	7	/*
AnnaBridge	167:84c0a372a020	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge	167:84c0a372a020	9	*
AnnaBridge	167:84c0a372a020	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	167:84c0a372a020	11	*
AnnaBridge	167:84c0a372a020	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	167:84c0a372a020	13	* not use this file except in compliance with the License.
AnnaBridge	167:84c0a372a020	14	* You may obtain a copy of the License at
AnnaBridge	167:84c0a372a020	15	*
AnnaBridge	167:84c0a372a020	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	167:84c0a372a020	17	*
AnnaBridge	167:84c0a372a020	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	167:84c0a372a020	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	167:84c0a372a020	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	167:84c0a372a020	21	* See the License for the specific language governing permissions and
AnnaBridge	167:84c0a372a020	22	* limitations under the License.
AnnaBridge	167:84c0a372a020	23	*/
AnnaBridge	167:84c0a372a020	24
AnnaBridge	167:84c0a372a020	25	#if defined ( __ICCARM__ )
Anna Bridge	169:a7c7b631e539	26	#pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge	169:a7c7b631e539	27	#elif defined (__clang__)
AnnaBridge	167:84c0a372a020	28	#pragma clang system_header /* treat file as system include file */
AnnaBridge	167:84c0a372a020	29	#endif
AnnaBridge	167:84c0a372a020	30
AnnaBridge	167:84c0a372a020	31	#ifndef __CORE_CM3_H_GENERIC
AnnaBridge	167:84c0a372a020	32	#define __CORE_CM3_H_GENERIC
AnnaBridge	167:84c0a372a020	33
AnnaBridge	167:84c0a372a020	34	#include <stdint.h>
AnnaBridge	167:84c0a372a020	35
AnnaBridge	167:84c0a372a020	36	#ifdef __cplusplus
AnnaBridge	167:84c0a372a020	37	extern "C" {
AnnaBridge	167:84c0a372a020	38	#endif
AnnaBridge	167:84c0a372a020	39
AnnaBridge	167:84c0a372a020	40	/**
AnnaBridge	167:84c0a372a020	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge	167:84c0a372a020	42	CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge	167:84c0a372a020	43
AnnaBridge	167:84c0a372a020	44	\li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge	167:84c0a372a020	45	Function definitions in header files are used to allow 'inlining'.
AnnaBridge	167:84c0a372a020	46
AnnaBridge	167:84c0a372a020	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge	167:84c0a372a020	48	Unions are used for effective representation of core registers.
AnnaBridge	167:84c0a372a020	49
AnnaBridge	167:84c0a372a020	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge	167:84c0a372a020	51	Function-like macros are used to allow more efficient code.
AnnaBridge	167:84c0a372a020	52	*/
AnnaBridge	167:84c0a372a020	53
AnnaBridge	167:84c0a372a020	54
AnnaBridge	167:84c0a372a020	55	/*******************************************************************************
AnnaBridge	167:84c0a372a020	56	* CMSIS definitions
AnnaBridge	167:84c0a372a020	57	******************************************************************************/
AnnaBridge	167:84c0a372a020	58	/**
AnnaBridge	167:84c0a372a020	59	\ingroup Cortex_M3
AnnaBridge	167:84c0a372a020	60	@{
AnnaBridge	167:84c0a372a020	61	*/
AnnaBridge	167:84c0a372a020	62
AnnaBridge	167:84c0a372a020	63	#include "cmsis_version.h"
AnnaBridge	167:84c0a372a020	64
AnnaBridge	167:84c0a372a020	65	/* CMSIS CM3 definitions */
AnnaBridge	167:84c0a372a020	66	#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
AnnaBridge	167:84c0a372a020	67	#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
AnnaBridge	167:84c0a372a020	68	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) \| \
AnnaBridge	167:84c0a372a020	69	__CM3_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
AnnaBridge	167:84c0a372a020	70
AnnaBridge	167:84c0a372a020	71	#define __CORTEX_M (3U) /!< Cortex-M Core /
AnnaBridge	167:84c0a372a020	72
AnnaBridge	167:84c0a372a020	73	/** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge	167:84c0a372a020	74	This core does not support an FPU at all
AnnaBridge	167:84c0a372a020	75	*/
AnnaBridge	167:84c0a372a020	76	#define __FPU_USED 0U
AnnaBridge	167:84c0a372a020	77
AnnaBridge	167:84c0a372a020	78	#if defined ( __CC_ARM )
AnnaBridge	167:84c0a372a020	79	#if defined __TARGET_FPU_VFP
AnnaBridge	167:84c0a372a020	80	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:84c0a372a020	81	#endif
AnnaBridge	167:84c0a372a020	82
AnnaBridge	167:84c0a372a020	83	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	167:84c0a372a020	84	#if defined __ARM_PCS_VFP
AnnaBridge	167:84c0a372a020	85	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:84c0a372a020	86	#endif
AnnaBridge	167:84c0a372a020	87
AnnaBridge	167:84c0a372a020	88	#elif defined ( __GNUC__ )
AnnaBridge	167:84c0a372a020	89	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge	167:84c0a372a020	90	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:84c0a372a020	91	#endif
AnnaBridge	167:84c0a372a020	92
AnnaBridge	167:84c0a372a020	93	#elif defined ( __ICCARM__ )
AnnaBridge	167:84c0a372a020	94	#if defined __ARMVFP__
AnnaBridge	167:84c0a372a020	95	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:84c0a372a020	96	#endif
AnnaBridge	167:84c0a372a020	97
AnnaBridge	167:84c0a372a020	98	#elif defined ( __TI_ARM__ )
AnnaBridge	167:84c0a372a020	99	#if defined __TI_VFP_SUPPORT__
AnnaBridge	167:84c0a372a020	100	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:84c0a372a020	101	#endif
AnnaBridge	167:84c0a372a020	102
AnnaBridge	167:84c0a372a020	103	#elif defined ( __TASKING__ )
AnnaBridge	167:84c0a372a020	104	#if defined __FPU_VFP__
AnnaBridge	167:84c0a372a020	105	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:84c0a372a020	106	#endif
AnnaBridge	167:84c0a372a020	107
AnnaBridge	167:84c0a372a020	108	#elif defined ( __CSMC__ )
AnnaBridge	167:84c0a372a020	109	#if ( __CSMC__ & 0x400U)
AnnaBridge	167:84c0a372a020	110	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:84c0a372a020	111	#endif
AnnaBridge	167:84c0a372a020	112
AnnaBridge	167:84c0a372a020	113	#endif
AnnaBridge	167:84c0a372a020	114
AnnaBridge	167:84c0a372a020	115	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge	167:84c0a372a020	116
AnnaBridge	167:84c0a372a020	117
AnnaBridge	167:84c0a372a020	118	#ifdef __cplusplus
AnnaBridge	167:84c0a372a020	119	}
AnnaBridge	167:84c0a372a020	120	#endif
AnnaBridge	167:84c0a372a020	121
AnnaBridge	167:84c0a372a020	122	#endif /* __CORE_CM3_H_GENERIC */
AnnaBridge	167:84c0a372a020	123
AnnaBridge	167:84c0a372a020	124	#ifndef __CMSIS_GENERIC
AnnaBridge	167:84c0a372a020	125
AnnaBridge	167:84c0a372a020	126	#ifndef __CORE_CM3_H_DEPENDANT
AnnaBridge	167:84c0a372a020	127	#define __CORE_CM3_H_DEPENDANT
AnnaBridge	167:84c0a372a020	128
AnnaBridge	167:84c0a372a020	129	#ifdef __cplusplus
AnnaBridge	167:84c0a372a020	130	extern "C" {
AnnaBridge	167:84c0a372a020	131	#endif
AnnaBridge	167:84c0a372a020	132
AnnaBridge	167:84c0a372a020	133	/* check device defines and use defaults */
AnnaBridge	167:84c0a372a020	134	#if defined __CHECK_DEVICE_DEFINES
AnnaBridge	167:84c0a372a020	135	#ifndef __CM3_REV
AnnaBridge	167:84c0a372a020	136	#define __CM3_REV 0x0200U
AnnaBridge	167:84c0a372a020	137	#warning "__CM3_REV not defined in device header file; using default!"
AnnaBridge	167:84c0a372a020	138	#endif
AnnaBridge	167:84c0a372a020	139
AnnaBridge	167:84c0a372a020	140	#ifndef __MPU_PRESENT
AnnaBridge	167:84c0a372a020	141	#define __MPU_PRESENT 0U
AnnaBridge	167:84c0a372a020	142	#warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge	167:84c0a372a020	143	#endif
AnnaBridge	167:84c0a372a020	144
AnnaBridge	167:84c0a372a020	145	#ifndef __NVIC_PRIO_BITS
AnnaBridge	167:84c0a372a020	146	#define __NVIC_PRIO_BITS 3U
AnnaBridge	167:84c0a372a020	147	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge	167:84c0a372a020	148	#endif
AnnaBridge	167:84c0a372a020	149
AnnaBridge	167:84c0a372a020	150	#ifndef __Vendor_SysTickConfig
AnnaBridge	167:84c0a372a020	151	#define __Vendor_SysTickConfig 0U
AnnaBridge	167:84c0a372a020	152	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge	167:84c0a372a020	153	#endif
AnnaBridge	167:84c0a372a020	154	#endif
AnnaBridge	167:84c0a372a020	155
AnnaBridge	167:84c0a372a020	156	/* IO definitions (access restrictions to peripheral registers) */
AnnaBridge	167:84c0a372a020	157	/**
AnnaBridge	167:84c0a372a020	158	\defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge	167:84c0a372a020	159
AnnaBridge	167:84c0a372a020	160	<strong>IO Type Qualifiers</strong> are used
AnnaBridge	167:84c0a372a020	161	\li to specify the access to peripheral variables.
AnnaBridge	167:84c0a372a020	162	\li for automatic generation of peripheral register debug information.
AnnaBridge	167:84c0a372a020	163	*/
AnnaBridge	167:84c0a372a020	164	#ifdef __cplusplus
AnnaBridge	167:84c0a372a020	165	#define __I volatile /!< Defines 'read only' permissions /
AnnaBridge	167:84c0a372a020	166	#else
AnnaBridge	167:84c0a372a020	167	#define __I volatile const /!< Defines 'read only' permissions /
AnnaBridge	167:84c0a372a020	168	#endif
AnnaBridge	167:84c0a372a020	169	#define __O volatile /!< Defines 'write only' permissions /
AnnaBridge	167:84c0a372a020	170	#define __IO volatile /!< Defines 'read / write' permissions /
AnnaBridge	167:84c0a372a020	171
AnnaBridge	167:84c0a372a020	172	/* following defines should be used for structure members */
AnnaBridge	167:84c0a372a020	173	#define __IM volatile const /! Defines 'read only' structure member permissions /
AnnaBridge	167:84c0a372a020	174	#define __OM volatile /! Defines 'write only' structure member permissions /
AnnaBridge	167:84c0a372a020	175	#define __IOM volatile /! Defines 'read / write' structure member permissions /
AnnaBridge	167:84c0a372a020	176
AnnaBridge	167:84c0a372a020	177	/@} end of group Cortex_M3 /
AnnaBridge	167:84c0a372a020	178
AnnaBridge	167:84c0a372a020	179
AnnaBridge	167:84c0a372a020	180
AnnaBridge	167:84c0a372a020	181	/*******************************************************************************
AnnaBridge	167:84c0a372a020	182	* Register Abstraction
AnnaBridge	167:84c0a372a020	183	Core Register contain:
AnnaBridge	167:84c0a372a020	184	- Core Register
AnnaBridge	167:84c0a372a020	185	- Core NVIC Register
AnnaBridge	167:84c0a372a020	186	- Core SCB Register
AnnaBridge	167:84c0a372a020	187	- Core SysTick Register
AnnaBridge	167:84c0a372a020	188	- Core Debug Register
AnnaBridge	167:84c0a372a020	189	- Core MPU Register
AnnaBridge	167:84c0a372a020	190	******************************************************************************/
AnnaBridge	167:84c0a372a020	191	/**
AnnaBridge	167:84c0a372a020	192	\defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge	167:84c0a372a020	193	\brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge	167:84c0a372a020	194	*/
AnnaBridge	167:84c0a372a020	195
AnnaBridge	167:84c0a372a020	196	/**
AnnaBridge	167:84c0a372a020	197	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	198	\defgroup CMSIS_CORE Status and Control Registers
AnnaBridge	167:84c0a372a020	199	\brief Core Register type definitions.
AnnaBridge	167:84c0a372a020	200	@{
AnnaBridge	167:84c0a372a020	201	*/
AnnaBridge	167:84c0a372a020	202
AnnaBridge	167:84c0a372a020	203	/**
AnnaBridge	167:84c0a372a020	204	\brief Union type to access the Application Program Status Register (APSR).
AnnaBridge	167:84c0a372a020	205	*/
AnnaBridge	167:84c0a372a020	206	typedef union
AnnaBridge	167:84c0a372a020	207	{
AnnaBridge	167:84c0a372a020	208	struct
AnnaBridge	167:84c0a372a020	209	{
AnnaBridge	167:84c0a372a020	210	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
AnnaBridge	167:84c0a372a020	211	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	167:84c0a372a020	212	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	167:84c0a372a020	213	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	167:84c0a372a020	214	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	167:84c0a372a020	215	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	167:84c0a372a020	216	} b; /!< Structure used for bit access /
AnnaBridge	167:84c0a372a020	217	uint32_t w; /!< Type used for word access /
AnnaBridge	167:84c0a372a020	218	} APSR_Type;
AnnaBridge	167:84c0a372a020	219
AnnaBridge	167:84c0a372a020	220	/* APSR Register Definitions */
AnnaBridge	167:84c0a372a020	221	#define APSR_N_Pos 31U /!< APSR: N Position /
AnnaBridge	167:84c0a372a020	222	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
AnnaBridge	167:84c0a372a020	223
AnnaBridge	167:84c0a372a020	224	#define APSR_Z_Pos 30U /!< APSR: Z Position /
AnnaBridge	167:84c0a372a020	225	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
AnnaBridge	167:84c0a372a020	226
AnnaBridge	167:84c0a372a020	227	#define APSR_C_Pos 29U /!< APSR: C Position /
AnnaBridge	167:84c0a372a020	228	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
AnnaBridge	167:84c0a372a020	229
AnnaBridge	167:84c0a372a020	230	#define APSR_V_Pos 28U /!< APSR: V Position /
AnnaBridge	167:84c0a372a020	231	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
AnnaBridge	167:84c0a372a020	232
AnnaBridge	167:84c0a372a020	233	#define APSR_Q_Pos 27U /!< APSR: Q Position /
AnnaBridge	167:84c0a372a020	234	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
AnnaBridge	167:84c0a372a020	235
AnnaBridge	167:84c0a372a020	236
AnnaBridge	167:84c0a372a020	237	/**
AnnaBridge	167:84c0a372a020	238	\brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge	167:84c0a372a020	239	*/
AnnaBridge	167:84c0a372a020	240	typedef union
AnnaBridge	167:84c0a372a020	241	{
AnnaBridge	167:84c0a372a020	242	struct
AnnaBridge	167:84c0a372a020	243	{
AnnaBridge	167:84c0a372a020	244	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	167:84c0a372a020	245	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
AnnaBridge	167:84c0a372a020	246	} b; /!< Structure used for bit access /
AnnaBridge	167:84c0a372a020	247	uint32_t w; /!< Type used for word access /
AnnaBridge	167:84c0a372a020	248	} IPSR_Type;
AnnaBridge	167:84c0a372a020	249
AnnaBridge	167:84c0a372a020	250	/* IPSR Register Definitions */
AnnaBridge	167:84c0a372a020	251	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
AnnaBridge	167:84c0a372a020	252	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
AnnaBridge	167:84c0a372a020	253
AnnaBridge	167:84c0a372a020	254
AnnaBridge	167:84c0a372a020	255	/**
AnnaBridge	167:84c0a372a020	256	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge	167:84c0a372a020	257	*/
AnnaBridge	167:84c0a372a020	258	typedef union
AnnaBridge	167:84c0a372a020	259	{
AnnaBridge	167:84c0a372a020	260	struct
AnnaBridge	167:84c0a372a020	261	{
AnnaBridge	167:84c0a372a020	262	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	167:84c0a372a020	263	uint32_t _reserved0:1; /!< bit: 9 Reserved /
AnnaBridge	167:84c0a372a020	264	uint32_t ICI_IT_1:6; /!< bit: 10..15 ICI/IT part 1 /
AnnaBridge	167:84c0a372a020	265	uint32_t _reserved1:8; /!< bit: 16..23 Reserved /
AnnaBridge	167:84c0a372a020	266	uint32_t T:1; /!< bit: 24 Thumb bit /
AnnaBridge	167:84c0a372a020	267	uint32_t ICI_IT_2:2; /!< bit: 25..26 ICI/IT part 2 /
AnnaBridge	167:84c0a372a020	268	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	167:84c0a372a020	269	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	167:84c0a372a020	270	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	167:84c0a372a020	271	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	167:84c0a372a020	272	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	167:84c0a372a020	273	} b; /!< Structure used for bit access /
AnnaBridge	167:84c0a372a020	274	uint32_t w; /!< Type used for word access /
AnnaBridge	167:84c0a372a020	275	} xPSR_Type;
AnnaBridge	167:84c0a372a020	276
AnnaBridge	167:84c0a372a020	277	/* xPSR Register Definitions */
AnnaBridge	167:84c0a372a020	278	#define xPSR_N_Pos 31U /!< xPSR: N Position /
AnnaBridge	167:84c0a372a020	279	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
AnnaBridge	167:84c0a372a020	280
AnnaBridge	167:84c0a372a020	281	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
AnnaBridge	167:84c0a372a020	282	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
AnnaBridge	167:84c0a372a020	283
AnnaBridge	167:84c0a372a020	284	#define xPSR_C_Pos 29U /!< xPSR: C Position /
AnnaBridge	167:84c0a372a020	285	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
AnnaBridge	167:84c0a372a020	286
AnnaBridge	167:84c0a372a020	287	#define xPSR_V_Pos 28U /!< xPSR: V Position /
AnnaBridge	167:84c0a372a020	288	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
AnnaBridge	167:84c0a372a020	289
AnnaBridge	167:84c0a372a020	290	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
AnnaBridge	167:84c0a372a020	291	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
AnnaBridge	167:84c0a372a020	292
AnnaBridge	167:84c0a372a020	293	#define xPSR_ICI_IT_2_Pos 25U /!< xPSR: ICI/IT part 2 Position /
AnnaBridge	167:84c0a372a020	294	#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /!< xPSR: ICI/IT part 2 Mask /
AnnaBridge	167:84c0a372a020	295
AnnaBridge	167:84c0a372a020	296	#define xPSR_T_Pos 24U /!< xPSR: T Position /
AnnaBridge	167:84c0a372a020	297	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
AnnaBridge	167:84c0a372a020	298
AnnaBridge	167:84c0a372a020	299	#define xPSR_ICI_IT_1_Pos 10U /!< xPSR: ICI/IT part 1 Position /
AnnaBridge	167:84c0a372a020	300	#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /!< xPSR: ICI/IT part 1 Mask /
AnnaBridge	167:84c0a372a020	301
AnnaBridge	167:84c0a372a020	302	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
AnnaBridge	167:84c0a372a020	303	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
AnnaBridge	167:84c0a372a020	304
AnnaBridge	167:84c0a372a020	305
AnnaBridge	167:84c0a372a020	306	/**
AnnaBridge	167:84c0a372a020	307	\brief Union type to access the Control Registers (CONTROL).
AnnaBridge	167:84c0a372a020	308	*/
AnnaBridge	167:84c0a372a020	309	typedef union
AnnaBridge	167:84c0a372a020	310	{
AnnaBridge	167:84c0a372a020	311	struct
AnnaBridge	167:84c0a372a020	312	{
AnnaBridge	167:84c0a372a020	313	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
AnnaBridge	167:84c0a372a020	314	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
AnnaBridge	167:84c0a372a020	315	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
AnnaBridge	167:84c0a372a020	316	} b; /!< Structure used for bit access /
AnnaBridge	167:84c0a372a020	317	uint32_t w; /!< Type used for word access /
AnnaBridge	167:84c0a372a020	318	} CONTROL_Type;
AnnaBridge	167:84c0a372a020	319
AnnaBridge	167:84c0a372a020	320	/* CONTROL Register Definitions */
AnnaBridge	167:84c0a372a020	321	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
AnnaBridge	167:84c0a372a020	322	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
AnnaBridge	167:84c0a372a020	323
AnnaBridge	167:84c0a372a020	324	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
AnnaBridge	167:84c0a372a020	325	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
AnnaBridge	167:84c0a372a020	326
AnnaBridge	167:84c0a372a020	327	/@} end of group CMSIS_CORE /
AnnaBridge	167:84c0a372a020	328
AnnaBridge	167:84c0a372a020	329
AnnaBridge	167:84c0a372a020	330	/**
AnnaBridge	167:84c0a372a020	331	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	332	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge	167:84c0a372a020	333	\brief Type definitions for the NVIC Registers
AnnaBridge	167:84c0a372a020	334	@{
AnnaBridge	167:84c0a372a020	335	*/
AnnaBridge	167:84c0a372a020	336
AnnaBridge	167:84c0a372a020	337	/**
AnnaBridge	167:84c0a372a020	338	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge	167:84c0a372a020	339	*/
AnnaBridge	167:84c0a372a020	340	typedef struct
AnnaBridge	167:84c0a372a020	341	{
AnnaBridge	167:84c0a372a020	342	__IOM uint32_t ISER[8U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
AnnaBridge	167:84c0a372a020	343	uint32_t RESERVED0[24U];
AnnaBridge	167:84c0a372a020	344	__IOM uint32_t ICER[8U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
AnnaBridge	167:84c0a372a020	345	uint32_t RSERVED1[24U];
AnnaBridge	167:84c0a372a020	346	__IOM uint32_t ISPR[8U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
AnnaBridge	167:84c0a372a020	347	uint32_t RESERVED2[24U];
AnnaBridge	167:84c0a372a020	348	__IOM uint32_t ICPR[8U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
AnnaBridge	167:84c0a372a020	349	uint32_t RESERVED3[24U];
AnnaBridge	167:84c0a372a020	350	__IOM uint32_t IABR[8U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
AnnaBridge	167:84c0a372a020	351	uint32_t RESERVED4[56U];
AnnaBridge	167:84c0a372a020	352	__IOM uint8_t IP[240U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
AnnaBridge	167:84c0a372a020	353	uint32_t RESERVED5[644U];
AnnaBridge	167:84c0a372a020	354	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
AnnaBridge	167:84c0a372a020	355	} NVIC_Type;
AnnaBridge	167:84c0a372a020	356
AnnaBridge	167:84c0a372a020	357	/* Software Triggered Interrupt Register Definitions */
AnnaBridge	167:84c0a372a020	358	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
AnnaBridge	167:84c0a372a020	359	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
AnnaBridge	167:84c0a372a020	360
AnnaBridge	167:84c0a372a020	361	/@} end of group CMSIS_NVIC /
AnnaBridge	167:84c0a372a020	362
AnnaBridge	167:84c0a372a020	363
AnnaBridge	167:84c0a372a020	364	/**
AnnaBridge	167:84c0a372a020	365	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	366	\defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge	167:84c0a372a020	367	\brief Type definitions for the System Control Block Registers
AnnaBridge	167:84c0a372a020	368	@{
AnnaBridge	167:84c0a372a020	369	*/
AnnaBridge	167:84c0a372a020	370
AnnaBridge	167:84c0a372a020	371	/**
AnnaBridge	167:84c0a372a020	372	\brief Structure type to access the System Control Block (SCB).
AnnaBridge	167:84c0a372a020	373	*/
AnnaBridge	167:84c0a372a020	374	typedef struct
AnnaBridge	167:84c0a372a020	375	{
AnnaBridge	167:84c0a372a020	376	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
AnnaBridge	167:84c0a372a020	377	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
AnnaBridge	167:84c0a372a020	378	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
AnnaBridge	167:84c0a372a020	379	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
AnnaBridge	167:84c0a372a020	380	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
AnnaBridge	167:84c0a372a020	381	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
AnnaBridge	167:84c0a372a020	382	__IOM uint8_t SHP[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
AnnaBridge	167:84c0a372a020	383	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
AnnaBridge	167:84c0a372a020	384	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
AnnaBridge	167:84c0a372a020	385	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
AnnaBridge	167:84c0a372a020	386	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
AnnaBridge	167:84c0a372a020	387	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
AnnaBridge	167:84c0a372a020	388	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
AnnaBridge	167:84c0a372a020	389	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
AnnaBridge	167:84c0a372a020	390	__IM uint32_t PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
AnnaBridge	167:84c0a372a020	391	__IM uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
AnnaBridge	167:84c0a372a020	392	__IM uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
AnnaBridge	167:84c0a372a020	393	__IM uint32_t MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
AnnaBridge	167:84c0a372a020	394	__IM uint32_t ISAR[5U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
AnnaBridge	167:84c0a372a020	395	uint32_t RESERVED0[5U];
AnnaBridge	167:84c0a372a020	396	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
AnnaBridge	167:84c0a372a020	397	} SCB_Type;
AnnaBridge	167:84c0a372a020	398
AnnaBridge	167:84c0a372a020	399	/* SCB CPUID Register Definitions */
AnnaBridge	167:84c0a372a020	400	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
AnnaBridge	167:84c0a372a020	401	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
AnnaBridge	167:84c0a372a020	402
AnnaBridge	167:84c0a372a020	403	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
AnnaBridge	167:84c0a372a020	404	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
AnnaBridge	167:84c0a372a020	405
AnnaBridge	167:84c0a372a020	406	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
AnnaBridge	167:84c0a372a020	407	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
AnnaBridge	167:84c0a372a020	408
AnnaBridge	167:84c0a372a020	409	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
AnnaBridge	167:84c0a372a020	410	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
AnnaBridge	167:84c0a372a020	411
AnnaBridge	167:84c0a372a020	412	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
AnnaBridge	167:84c0a372a020	413	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
AnnaBridge	167:84c0a372a020	414
AnnaBridge	167:84c0a372a020	415	/* SCB Interrupt Control State Register Definitions */
AnnaBridge	167:84c0a372a020	416	#define SCB_ICSR_NMIPENDSET_Pos 31U /!< SCB ICSR: NMIPENDSET Position /
AnnaBridge	167:84c0a372a020	417	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
AnnaBridge	167:84c0a372a020	418
AnnaBridge	167:84c0a372a020	419	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
AnnaBridge	167:84c0a372a020	420	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
AnnaBridge	167:84c0a372a020	421
AnnaBridge	167:84c0a372a020	422	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
AnnaBridge	167:84c0a372a020	423	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
AnnaBridge	167:84c0a372a020	424
AnnaBridge	167:84c0a372a020	425	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
AnnaBridge	167:84c0a372a020	426	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
AnnaBridge	167:84c0a372a020	427
AnnaBridge	167:84c0a372a020	428	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
AnnaBridge	167:84c0a372a020	429	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
AnnaBridge	167:84c0a372a020	430
AnnaBridge	167:84c0a372a020	431	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
AnnaBridge	167:84c0a372a020	432	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
AnnaBridge	167:84c0a372a020	433
AnnaBridge	167:84c0a372a020	434	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
AnnaBridge	167:84c0a372a020	435	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
AnnaBridge	167:84c0a372a020	436
AnnaBridge	167:84c0a372a020	437	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
AnnaBridge	167:84c0a372a020	438	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
AnnaBridge	167:84c0a372a020	439
AnnaBridge	167:84c0a372a020	440	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
AnnaBridge	167:84c0a372a020	441	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
AnnaBridge	167:84c0a372a020	442
AnnaBridge	167:84c0a372a020	443	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
AnnaBridge	167:84c0a372a020	444	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
AnnaBridge	167:84c0a372a020	445
AnnaBridge	167:84c0a372a020	446	/* SCB Vector Table Offset Register Definitions */
AnnaBridge	167:84c0a372a020	447	#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
AnnaBridge	167:84c0a372a020	448	#define SCB_VTOR_TBLBASE_Pos 29U /!< SCB VTOR: TBLBASE Position /
AnnaBridge	167:84c0a372a020	449	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
AnnaBridge	167:84c0a372a020	450
AnnaBridge	167:84c0a372a020	451	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
AnnaBridge	167:84c0a372a020	452	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
AnnaBridge	167:84c0a372a020	453	#else
AnnaBridge	167:84c0a372a020	454	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
AnnaBridge	167:84c0a372a020	455	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
AnnaBridge	167:84c0a372a020	456	#endif
AnnaBridge	167:84c0a372a020	457
AnnaBridge	167:84c0a372a020	458	/* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge	167:84c0a372a020	459	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
AnnaBridge	167:84c0a372a020	460	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
AnnaBridge	167:84c0a372a020	461
AnnaBridge	167:84c0a372a020	462	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
AnnaBridge	167:84c0a372a020	463	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
AnnaBridge	167:84c0a372a020	464
AnnaBridge	167:84c0a372a020	465	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
AnnaBridge	167:84c0a372a020	466	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
AnnaBridge	167:84c0a372a020	467
AnnaBridge	167:84c0a372a020	468	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
AnnaBridge	167:84c0a372a020	469	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
AnnaBridge	167:84c0a372a020	470
AnnaBridge	167:84c0a372a020	471	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
AnnaBridge	167:84c0a372a020	472	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
AnnaBridge	167:84c0a372a020	473
AnnaBridge	167:84c0a372a020	474	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
AnnaBridge	167:84c0a372a020	475	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
AnnaBridge	167:84c0a372a020	476
AnnaBridge	167:84c0a372a020	477	#define SCB_AIRCR_VECTRESET_Pos 0U /!< SCB AIRCR: VECTRESET Position /
AnnaBridge	167:84c0a372a020	478	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
AnnaBridge	167:84c0a372a020	479
AnnaBridge	167:84c0a372a020	480	/* SCB System Control Register Definitions */
AnnaBridge	167:84c0a372a020	481	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
AnnaBridge	167:84c0a372a020	482	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
AnnaBridge	167:84c0a372a020	483
AnnaBridge	167:84c0a372a020	484	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
AnnaBridge	167:84c0a372a020	485	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
AnnaBridge	167:84c0a372a020	486
AnnaBridge	167:84c0a372a020	487	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
AnnaBridge	167:84c0a372a020	488	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
AnnaBridge	167:84c0a372a020	489
AnnaBridge	167:84c0a372a020	490	/* SCB Configuration Control Register Definitions */
AnnaBridge	167:84c0a372a020	491	#define SCB_CCR_STKALIGN_Pos 9U /!< SCB CCR: STKALIGN Position /
AnnaBridge	167:84c0a372a020	492	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
AnnaBridge	167:84c0a372a020	493
AnnaBridge	167:84c0a372a020	494	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
AnnaBridge	167:84c0a372a020	495	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
AnnaBridge	167:84c0a372a020	496
AnnaBridge	167:84c0a372a020	497	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
AnnaBridge	167:84c0a372a020	498	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
AnnaBridge	167:84c0a372a020	499
AnnaBridge	167:84c0a372a020	500	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
AnnaBridge	167:84c0a372a020	501	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
AnnaBridge	167:84c0a372a020	502
AnnaBridge	167:84c0a372a020	503	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
AnnaBridge	167:84c0a372a020	504	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
AnnaBridge	167:84c0a372a020	505
AnnaBridge	167:84c0a372a020	506	#define SCB_CCR_NONBASETHRDENA_Pos 0U /!< SCB CCR: NONBASETHRDENA Position /
AnnaBridge	167:84c0a372a020	507	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
AnnaBridge	167:84c0a372a020	508
AnnaBridge	167:84c0a372a020	509	/* SCB System Handler Control and State Register Definitions */
AnnaBridge	167:84c0a372a020	510	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
AnnaBridge	167:84c0a372a020	511	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
AnnaBridge	167:84c0a372a020	512
AnnaBridge	167:84c0a372a020	513	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
AnnaBridge	167:84c0a372a020	514	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
AnnaBridge	167:84c0a372a020	515
AnnaBridge	167:84c0a372a020	516	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
AnnaBridge	167:84c0a372a020	517	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
AnnaBridge	167:84c0a372a020	518
AnnaBridge	167:84c0a372a020	519	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
AnnaBridge	167:84c0a372a020	520	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
AnnaBridge	167:84c0a372a020	521
AnnaBridge	167:84c0a372a020	522	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
AnnaBridge	167:84c0a372a020	523	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
AnnaBridge	167:84c0a372a020	524
AnnaBridge	167:84c0a372a020	525	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
AnnaBridge	167:84c0a372a020	526	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
AnnaBridge	167:84c0a372a020	527
AnnaBridge	167:84c0a372a020	528	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
AnnaBridge	167:84c0a372a020	529	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
AnnaBridge	167:84c0a372a020	530
AnnaBridge	167:84c0a372a020	531	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
AnnaBridge	167:84c0a372a020	532	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
AnnaBridge	167:84c0a372a020	533
AnnaBridge	167:84c0a372a020	534	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
AnnaBridge	167:84c0a372a020	535	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
AnnaBridge	167:84c0a372a020	536
AnnaBridge	167:84c0a372a020	537	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
AnnaBridge	167:84c0a372a020	538	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
AnnaBridge	167:84c0a372a020	539
AnnaBridge	167:84c0a372a020	540	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
AnnaBridge	167:84c0a372a020	541	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
AnnaBridge	167:84c0a372a020	542
AnnaBridge	167:84c0a372a020	543	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
AnnaBridge	167:84c0a372a020	544	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
AnnaBridge	167:84c0a372a020	545
AnnaBridge	167:84c0a372a020	546	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
AnnaBridge	167:84c0a372a020	547	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
AnnaBridge	167:84c0a372a020	548
AnnaBridge	167:84c0a372a020	549	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
AnnaBridge	167:84c0a372a020	550	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
AnnaBridge	167:84c0a372a020	551
AnnaBridge	167:84c0a372a020	552	/* SCB Configurable Fault Status Register Definitions */
AnnaBridge	167:84c0a372a020	553	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
AnnaBridge	167:84c0a372a020	554	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
AnnaBridge	167:84c0a372a020	555
AnnaBridge	167:84c0a372a020	556	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
AnnaBridge	167:84c0a372a020	557	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
AnnaBridge	167:84c0a372a020	558
AnnaBridge	167:84c0a372a020	559	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
AnnaBridge	167:84c0a372a020	560	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
AnnaBridge	167:84c0a372a020	561
AnnaBridge	167:84c0a372a020	562	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	167:84c0a372a020	563	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
AnnaBridge	167:84c0a372a020	564	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
AnnaBridge	167:84c0a372a020	565
AnnaBridge	167:84c0a372a020	566	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
AnnaBridge	167:84c0a372a020	567	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
AnnaBridge	167:84c0a372a020	568
AnnaBridge	167:84c0a372a020	569	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
AnnaBridge	167:84c0a372a020	570	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
AnnaBridge	167:84c0a372a020	571
AnnaBridge	167:84c0a372a020	572	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
AnnaBridge	167:84c0a372a020	573	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
AnnaBridge	167:84c0a372a020	574
AnnaBridge	167:84c0a372a020	575	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
AnnaBridge	167:84c0a372a020	576	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
AnnaBridge	167:84c0a372a020	577
AnnaBridge	167:84c0a372a020	578	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	167:84c0a372a020	579	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
AnnaBridge	167:84c0a372a020	580	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
AnnaBridge	167:84c0a372a020	581
AnnaBridge	167:84c0a372a020	582	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
AnnaBridge	167:84c0a372a020	583	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
AnnaBridge	167:84c0a372a020	584
AnnaBridge	167:84c0a372a020	585	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
AnnaBridge	167:84c0a372a020	586	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
AnnaBridge	167:84c0a372a020	587
AnnaBridge	167:84c0a372a020	588	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
AnnaBridge	167:84c0a372a020	589	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
AnnaBridge	167:84c0a372a020	590
AnnaBridge	167:84c0a372a020	591	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
AnnaBridge	167:84c0a372a020	592	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
AnnaBridge	167:84c0a372a020	593
AnnaBridge	167:84c0a372a020	594	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
AnnaBridge	167:84c0a372a020	595	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
AnnaBridge	167:84c0a372a020	596
AnnaBridge	167:84c0a372a020	597	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	167:84c0a372a020	598	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
AnnaBridge	167:84c0a372a020	599	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
AnnaBridge	167:84c0a372a020	600
AnnaBridge	167:84c0a372a020	601	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
AnnaBridge	167:84c0a372a020	602	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
AnnaBridge	167:84c0a372a020	603
AnnaBridge	167:84c0a372a020	604	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
AnnaBridge	167:84c0a372a020	605	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
AnnaBridge	167:84c0a372a020	606
AnnaBridge	167:84c0a372a020	607	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
AnnaBridge	167:84c0a372a020	608	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
AnnaBridge	167:84c0a372a020	609
AnnaBridge	167:84c0a372a020	610	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
AnnaBridge	167:84c0a372a020	611	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
AnnaBridge	167:84c0a372a020	612
AnnaBridge	167:84c0a372a020	613	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
AnnaBridge	167:84c0a372a020	614	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
AnnaBridge	167:84c0a372a020	615
AnnaBridge	167:84c0a372a020	616	/* SCB Hard Fault Status Register Definitions */
AnnaBridge	167:84c0a372a020	617	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
AnnaBridge	167:84c0a372a020	618	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
AnnaBridge	167:84c0a372a020	619
AnnaBridge	167:84c0a372a020	620	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
AnnaBridge	167:84c0a372a020	621	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
AnnaBridge	167:84c0a372a020	622
AnnaBridge	167:84c0a372a020	623	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
AnnaBridge	167:84c0a372a020	624	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
AnnaBridge	167:84c0a372a020	625
AnnaBridge	167:84c0a372a020	626	/* SCB Debug Fault Status Register Definitions */
AnnaBridge	167:84c0a372a020	627	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
AnnaBridge	167:84c0a372a020	628	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
AnnaBridge	167:84c0a372a020	629
AnnaBridge	167:84c0a372a020	630	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
AnnaBridge	167:84c0a372a020	631	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
AnnaBridge	167:84c0a372a020	632
AnnaBridge	167:84c0a372a020	633	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
AnnaBridge	167:84c0a372a020	634	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
AnnaBridge	167:84c0a372a020	635
AnnaBridge	167:84c0a372a020	636	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
AnnaBridge	167:84c0a372a020	637	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
AnnaBridge	167:84c0a372a020	638
AnnaBridge	167:84c0a372a020	639	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
AnnaBridge	167:84c0a372a020	640	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
AnnaBridge	167:84c0a372a020	641
AnnaBridge	167:84c0a372a020	642	/@} end of group CMSIS_SCB /
AnnaBridge	167:84c0a372a020	643
AnnaBridge	167:84c0a372a020	644
AnnaBridge	167:84c0a372a020	645	/**
AnnaBridge	167:84c0a372a020	646	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	647	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge	167:84c0a372a020	648	\brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge	167:84c0a372a020	649	@{
AnnaBridge	167:84c0a372a020	650	*/
AnnaBridge	167:84c0a372a020	651
AnnaBridge	167:84c0a372a020	652	/**
AnnaBridge	167:84c0a372a020	653	\brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge	167:84c0a372a020	654	*/
AnnaBridge	167:84c0a372a020	655	typedef struct
AnnaBridge	167:84c0a372a020	656	{
AnnaBridge	167:84c0a372a020	657	uint32_t RESERVED0[1U];
AnnaBridge	167:84c0a372a020	658	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
AnnaBridge	167:84c0a372a020	659	#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
AnnaBridge	167:84c0a372a020	660	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
AnnaBridge	167:84c0a372a020	661	#else
AnnaBridge	167:84c0a372a020	662	uint32_t RESERVED1[1U];
AnnaBridge	167:84c0a372a020	663	#endif
AnnaBridge	167:84c0a372a020	664	} SCnSCB_Type;
AnnaBridge	167:84c0a372a020	665
AnnaBridge	167:84c0a372a020	666	/* Interrupt Controller Type Register Definitions */
AnnaBridge	167:84c0a372a020	667	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
AnnaBridge	167:84c0a372a020	668	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
AnnaBridge	167:84c0a372a020	669
AnnaBridge	167:84c0a372a020	670	/* Auxiliary Control Register Definitions */
AnnaBridge	167:84c0a372a020	671
AnnaBridge	167:84c0a372a020	672	#define SCnSCB_ACTLR_DISFOLD_Pos 2U /!< ACTLR: DISFOLD Position /
AnnaBridge	167:84c0a372a020	673	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
AnnaBridge	167:84c0a372a020	674
AnnaBridge	167:84c0a372a020	675	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /!< ACTLR: DISDEFWBUF Position /
AnnaBridge	167:84c0a372a020	676	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
AnnaBridge	167:84c0a372a020	677
AnnaBridge	167:84c0a372a020	678	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /!< ACTLR: DISMCYCINT Position /
AnnaBridge	167:84c0a372a020	679	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
AnnaBridge	167:84c0a372a020	680
AnnaBridge	167:84c0a372a020	681	/@} end of group CMSIS_SCnotSCB /
AnnaBridge	167:84c0a372a020	682
AnnaBridge	167:84c0a372a020	683
AnnaBridge	167:84c0a372a020	684	/**
AnnaBridge	167:84c0a372a020	685	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	686	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge	167:84c0a372a020	687	\brief Type definitions for the System Timer Registers.
AnnaBridge	167:84c0a372a020	688	@{
AnnaBridge	167:84c0a372a020	689	*/
AnnaBridge	167:84c0a372a020	690
AnnaBridge	167:84c0a372a020	691	/**
AnnaBridge	167:84c0a372a020	692	\brief Structure type to access the System Timer (SysTick).
AnnaBridge	167:84c0a372a020	693	*/
AnnaBridge	167:84c0a372a020	694	typedef struct
AnnaBridge	167:84c0a372a020	695	{
AnnaBridge	167:84c0a372a020	696	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
AnnaBridge	167:84c0a372a020	697	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
AnnaBridge	167:84c0a372a020	698	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
AnnaBridge	167:84c0a372a020	699	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
AnnaBridge	167:84c0a372a020	700	} SysTick_Type;
AnnaBridge	167:84c0a372a020	701
AnnaBridge	167:84c0a372a020	702	/* SysTick Control / Status Register Definitions */
AnnaBridge	167:84c0a372a020	703	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
AnnaBridge	167:84c0a372a020	704	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
AnnaBridge	167:84c0a372a020	705
AnnaBridge	167:84c0a372a020	706	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
AnnaBridge	167:84c0a372a020	707	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
AnnaBridge	167:84c0a372a020	708
AnnaBridge	167:84c0a372a020	709	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
AnnaBridge	167:84c0a372a020	710	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
AnnaBridge	167:84c0a372a020	711
AnnaBridge	167:84c0a372a020	712	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
AnnaBridge	167:84c0a372a020	713	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
AnnaBridge	167:84c0a372a020	714
AnnaBridge	167:84c0a372a020	715	/* SysTick Reload Register Definitions */
AnnaBridge	167:84c0a372a020	716	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
AnnaBridge	167:84c0a372a020	717	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
AnnaBridge	167:84c0a372a020	718
AnnaBridge	167:84c0a372a020	719	/* SysTick Current Register Definitions */
AnnaBridge	167:84c0a372a020	720	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
AnnaBridge	167:84c0a372a020	721	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
AnnaBridge	167:84c0a372a020	722
AnnaBridge	167:84c0a372a020	723	/* SysTick Calibration Register Definitions */
AnnaBridge	167:84c0a372a020	724	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
AnnaBridge	167:84c0a372a020	725	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
AnnaBridge	167:84c0a372a020	726
AnnaBridge	167:84c0a372a020	727	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
AnnaBridge	167:84c0a372a020	728	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
AnnaBridge	167:84c0a372a020	729
AnnaBridge	167:84c0a372a020	730	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
AnnaBridge	167:84c0a372a020	731	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
AnnaBridge	167:84c0a372a020	732
AnnaBridge	167:84c0a372a020	733	/@} end of group CMSIS_SysTick /
AnnaBridge	167:84c0a372a020	734
AnnaBridge	167:84c0a372a020	735
AnnaBridge	167:84c0a372a020	736	/**
AnnaBridge	167:84c0a372a020	737	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	738	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge	167:84c0a372a020	739	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
AnnaBridge	167:84c0a372a020	740	@{
AnnaBridge	167:84c0a372a020	741	*/
AnnaBridge	167:84c0a372a020	742
AnnaBridge	167:84c0a372a020	743	/**
AnnaBridge	167:84c0a372a020	744	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
AnnaBridge	167:84c0a372a020	745	*/
AnnaBridge	167:84c0a372a020	746	typedef struct
AnnaBridge	167:84c0a372a020	747	{
AnnaBridge	167:84c0a372a020	748	__OM union
AnnaBridge	167:84c0a372a020	749	{
AnnaBridge	167:84c0a372a020	750	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
AnnaBridge	167:84c0a372a020	751	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
AnnaBridge	167:84c0a372a020	752	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
AnnaBridge	167:84c0a372a020	753	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
AnnaBridge	167:84c0a372a020	754	uint32_t RESERVED0[864U];
AnnaBridge	167:84c0a372a020	755	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
AnnaBridge	167:84c0a372a020	756	uint32_t RESERVED1[15U];
AnnaBridge	167:84c0a372a020	757	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
AnnaBridge	167:84c0a372a020	758	uint32_t RESERVED2[15U];
AnnaBridge	167:84c0a372a020	759	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
AnnaBridge	167:84c0a372a020	760	uint32_t RESERVED3[29U];
AnnaBridge	167:84c0a372a020	761	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
AnnaBridge	167:84c0a372a020	762	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
AnnaBridge	167:84c0a372a020	763	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
AnnaBridge	167:84c0a372a020	764	uint32_t RESERVED4[43U];
AnnaBridge	167:84c0a372a020	765	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
AnnaBridge	167:84c0a372a020	766	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
AnnaBridge	167:84c0a372a020	767	uint32_t RESERVED5[6U];
AnnaBridge	167:84c0a372a020	768	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
AnnaBridge	167:84c0a372a020	769	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
AnnaBridge	167:84c0a372a020	770	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
AnnaBridge	167:84c0a372a020	771	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
AnnaBridge	167:84c0a372a020	772	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
AnnaBridge	167:84c0a372a020	773	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
AnnaBridge	167:84c0a372a020	774	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
AnnaBridge	167:84c0a372a020	775	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
AnnaBridge	167:84c0a372a020	776	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
AnnaBridge	167:84c0a372a020	777	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
AnnaBridge	167:84c0a372a020	778	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
AnnaBridge	167:84c0a372a020	779	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
AnnaBridge	167:84c0a372a020	780	} ITM_Type;
AnnaBridge	167:84c0a372a020	781
AnnaBridge	167:84c0a372a020	782	/* ITM Trace Privilege Register Definitions */
AnnaBridge	167:84c0a372a020	783	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
Anna Bridge	169:a7c7b631e539	784	#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
AnnaBridge	167:84c0a372a020	785
AnnaBridge	167:84c0a372a020	786	/* ITM Trace Control Register Definitions */
AnnaBridge	167:84c0a372a020	787	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
AnnaBridge	167:84c0a372a020	788	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
AnnaBridge	167:84c0a372a020	789
AnnaBridge	167:84c0a372a020	790	#define ITM_TCR_TraceBusID_Pos 16U /!< ITM TCR: ATBID Position /
AnnaBridge	167:84c0a372a020	791	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
AnnaBridge	167:84c0a372a020	792
AnnaBridge	167:84c0a372a020	793	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
AnnaBridge	167:84c0a372a020	794	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
AnnaBridge	167:84c0a372a020	795
AnnaBridge	167:84c0a372a020	796	#define ITM_TCR_TSPrescale_Pos 8U /!< ITM TCR: TSPrescale Position /
AnnaBridge	167:84c0a372a020	797	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
AnnaBridge	167:84c0a372a020	798
AnnaBridge	167:84c0a372a020	799	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
AnnaBridge	167:84c0a372a020	800	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
AnnaBridge	167:84c0a372a020	801
AnnaBridge	167:84c0a372a020	802	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
AnnaBridge	167:84c0a372a020	803	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
AnnaBridge	167:84c0a372a020	804
AnnaBridge	167:84c0a372a020	805	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
AnnaBridge	167:84c0a372a020	806	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
AnnaBridge	167:84c0a372a020	807
AnnaBridge	167:84c0a372a020	808	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
AnnaBridge	167:84c0a372a020	809	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
AnnaBridge	167:84c0a372a020	810
AnnaBridge	167:84c0a372a020	811	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
AnnaBridge	167:84c0a372a020	812	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
AnnaBridge	167:84c0a372a020	813
AnnaBridge	167:84c0a372a020	814	/* ITM Integration Write Register Definitions */
AnnaBridge	167:84c0a372a020	815	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
AnnaBridge	167:84c0a372a020	816	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
AnnaBridge	167:84c0a372a020	817
AnnaBridge	167:84c0a372a020	818	/* ITM Integration Read Register Definitions */
AnnaBridge	167:84c0a372a020	819	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
AnnaBridge	167:84c0a372a020	820	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
AnnaBridge	167:84c0a372a020	821
AnnaBridge	167:84c0a372a020	822	/* ITM Integration Mode Control Register Definitions */
AnnaBridge	167:84c0a372a020	823	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
AnnaBridge	167:84c0a372a020	824	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
AnnaBridge	167:84c0a372a020	825
AnnaBridge	167:84c0a372a020	826	/* ITM Lock Status Register Definitions */
AnnaBridge	167:84c0a372a020	827	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
AnnaBridge	167:84c0a372a020	828	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
AnnaBridge	167:84c0a372a020	829
AnnaBridge	167:84c0a372a020	830	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
AnnaBridge	167:84c0a372a020	831	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
AnnaBridge	167:84c0a372a020	832
AnnaBridge	167:84c0a372a020	833	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
AnnaBridge	167:84c0a372a020	834	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
AnnaBridge	167:84c0a372a020	835
AnnaBridge	167:84c0a372a020	836	/@}/ /* end of group CMSIS_ITM */
AnnaBridge	167:84c0a372a020	837
AnnaBridge	167:84c0a372a020	838
AnnaBridge	167:84c0a372a020	839	/**
AnnaBridge	167:84c0a372a020	840	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	841	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge	167:84c0a372a020	842	\brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge	167:84c0a372a020	843	@{
AnnaBridge	167:84c0a372a020	844	*/
AnnaBridge	167:84c0a372a020	845
AnnaBridge	167:84c0a372a020	846	/**
AnnaBridge	167:84c0a372a020	847	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge	167:84c0a372a020	848	*/
AnnaBridge	167:84c0a372a020	849	typedef struct
AnnaBridge	167:84c0a372a020	850	{
AnnaBridge	167:84c0a372a020	851	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
AnnaBridge	167:84c0a372a020	852	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
AnnaBridge	167:84c0a372a020	853	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
AnnaBridge	167:84c0a372a020	854	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
AnnaBridge	167:84c0a372a020	855	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
AnnaBridge	167:84c0a372a020	856	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
AnnaBridge	167:84c0a372a020	857	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
AnnaBridge	167:84c0a372a020	858	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
AnnaBridge	167:84c0a372a020	859	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
AnnaBridge	167:84c0a372a020	860	__IOM uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
AnnaBridge	167:84c0a372a020	861	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
AnnaBridge	167:84c0a372a020	862	uint32_t RESERVED0[1U];
AnnaBridge	167:84c0a372a020	863	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
AnnaBridge	167:84c0a372a020	864	__IOM uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
AnnaBridge	167:84c0a372a020	865	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
AnnaBridge	167:84c0a372a020	866	uint32_t RESERVED1[1U];
AnnaBridge	167:84c0a372a020	867	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
AnnaBridge	167:84c0a372a020	868	__IOM uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
AnnaBridge	167:84c0a372a020	869	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
AnnaBridge	167:84c0a372a020	870	uint32_t RESERVED2[1U];
AnnaBridge	167:84c0a372a020	871	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
AnnaBridge	167:84c0a372a020	872	__IOM uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
AnnaBridge	167:84c0a372a020	873	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
AnnaBridge	167:84c0a372a020	874	} DWT_Type;
AnnaBridge	167:84c0a372a020	875
AnnaBridge	167:84c0a372a020	876	/* DWT Control Register Definitions */
AnnaBridge	167:84c0a372a020	877	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
AnnaBridge	167:84c0a372a020	878	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
AnnaBridge	167:84c0a372a020	879
AnnaBridge	167:84c0a372a020	880	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
AnnaBridge	167:84c0a372a020	881	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
AnnaBridge	167:84c0a372a020	882
AnnaBridge	167:84c0a372a020	883	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
AnnaBridge	167:84c0a372a020	884	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
AnnaBridge	167:84c0a372a020	885
AnnaBridge	167:84c0a372a020	886	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
AnnaBridge	167:84c0a372a020	887	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
AnnaBridge	167:84c0a372a020	888
AnnaBridge	167:84c0a372a020	889	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
AnnaBridge	167:84c0a372a020	890	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
AnnaBridge	167:84c0a372a020	891
AnnaBridge	167:84c0a372a020	892	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
AnnaBridge	167:84c0a372a020	893	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
AnnaBridge	167:84c0a372a020	894
AnnaBridge	167:84c0a372a020	895	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
AnnaBridge	167:84c0a372a020	896	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
AnnaBridge	167:84c0a372a020	897
AnnaBridge	167:84c0a372a020	898	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
AnnaBridge	167:84c0a372a020	899	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
AnnaBridge	167:84c0a372a020	900
AnnaBridge	167:84c0a372a020	901	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
AnnaBridge	167:84c0a372a020	902	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
AnnaBridge	167:84c0a372a020	903
AnnaBridge	167:84c0a372a020	904	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
AnnaBridge	167:84c0a372a020	905	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
AnnaBridge	167:84c0a372a020	906
AnnaBridge	167:84c0a372a020	907	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
AnnaBridge	167:84c0a372a020	908	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
AnnaBridge	167:84c0a372a020	909
AnnaBridge	167:84c0a372a020	910	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
AnnaBridge	167:84c0a372a020	911	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
AnnaBridge	167:84c0a372a020	912
AnnaBridge	167:84c0a372a020	913	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
AnnaBridge	167:84c0a372a020	914	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
AnnaBridge	167:84c0a372a020	915
AnnaBridge	167:84c0a372a020	916	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
AnnaBridge	167:84c0a372a020	917	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
AnnaBridge	167:84c0a372a020	918
AnnaBridge	167:84c0a372a020	919	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
AnnaBridge	167:84c0a372a020	920	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
AnnaBridge	167:84c0a372a020	921
AnnaBridge	167:84c0a372a020	922	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
AnnaBridge	167:84c0a372a020	923	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
AnnaBridge	167:84c0a372a020	924
AnnaBridge	167:84c0a372a020	925	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
AnnaBridge	167:84c0a372a020	926	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
AnnaBridge	167:84c0a372a020	927
AnnaBridge	167:84c0a372a020	928	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
AnnaBridge	167:84c0a372a020	929	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
AnnaBridge	167:84c0a372a020	930
AnnaBridge	167:84c0a372a020	931	/* DWT CPI Count Register Definitions */
AnnaBridge	167:84c0a372a020	932	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
AnnaBridge	167:84c0a372a020	933	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
AnnaBridge	167:84c0a372a020	934
AnnaBridge	167:84c0a372a020	935	/* DWT Exception Overhead Count Register Definitions */
AnnaBridge	167:84c0a372a020	936	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
AnnaBridge	167:84c0a372a020	937	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
AnnaBridge	167:84c0a372a020	938
AnnaBridge	167:84c0a372a020	939	/* DWT Sleep Count Register Definitions */
AnnaBridge	167:84c0a372a020	940	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
AnnaBridge	167:84c0a372a020	941	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
AnnaBridge	167:84c0a372a020	942
AnnaBridge	167:84c0a372a020	943	/* DWT LSU Count Register Definitions */
AnnaBridge	167:84c0a372a020	944	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
AnnaBridge	167:84c0a372a020	945	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
AnnaBridge	167:84c0a372a020	946
AnnaBridge	167:84c0a372a020	947	/* DWT Folded-instruction Count Register Definitions */
AnnaBridge	167:84c0a372a020	948	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
AnnaBridge	167:84c0a372a020	949	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
AnnaBridge	167:84c0a372a020	950
AnnaBridge	167:84c0a372a020	951	/* DWT Comparator Mask Register Definitions */
AnnaBridge	167:84c0a372a020	952	#define DWT_MASK_MASK_Pos 0U /!< DWT MASK: MASK Position /
AnnaBridge	167:84c0a372a020	953	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
AnnaBridge	167:84c0a372a020	954
AnnaBridge	167:84c0a372a020	955	/* DWT Comparator Function Register Definitions */
AnnaBridge	167:84c0a372a020	956	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
AnnaBridge	167:84c0a372a020	957	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
AnnaBridge	167:84c0a372a020	958
AnnaBridge	167:84c0a372a020	959	#define DWT_FUNCTION_DATAVADDR1_Pos 16U /!< DWT FUNCTION: DATAVADDR1 Position /
AnnaBridge	167:84c0a372a020	960	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
AnnaBridge	167:84c0a372a020	961
AnnaBridge	167:84c0a372a020	962	#define DWT_FUNCTION_DATAVADDR0_Pos 12U /!< DWT FUNCTION: DATAVADDR0 Position /
AnnaBridge	167:84c0a372a020	963	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
AnnaBridge	167:84c0a372a020	964
AnnaBridge	167:84c0a372a020	965	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
AnnaBridge	167:84c0a372a020	966	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
AnnaBridge	167:84c0a372a020	967
AnnaBridge	167:84c0a372a020	968	#define DWT_FUNCTION_LNK1ENA_Pos 9U /!< DWT FUNCTION: LNK1ENA Position /
AnnaBridge	167:84c0a372a020	969	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
AnnaBridge	167:84c0a372a020	970
AnnaBridge	167:84c0a372a020	971	#define DWT_FUNCTION_DATAVMATCH_Pos 8U /!< DWT FUNCTION: DATAVMATCH Position /
AnnaBridge	167:84c0a372a020	972	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
AnnaBridge	167:84c0a372a020	973
AnnaBridge	167:84c0a372a020	974	#define DWT_FUNCTION_CYCMATCH_Pos 7U /!< DWT FUNCTION: CYCMATCH Position /
AnnaBridge	167:84c0a372a020	975	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
AnnaBridge	167:84c0a372a020	976
AnnaBridge	167:84c0a372a020	977	#define DWT_FUNCTION_EMITRANGE_Pos 5U /!< DWT FUNCTION: EMITRANGE Position /
AnnaBridge	167:84c0a372a020	978	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
AnnaBridge	167:84c0a372a020	979
AnnaBridge	167:84c0a372a020	980	#define DWT_FUNCTION_FUNCTION_Pos 0U /!< DWT FUNCTION: FUNCTION Position /
AnnaBridge	167:84c0a372a020	981	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
AnnaBridge	167:84c0a372a020	982
AnnaBridge	167:84c0a372a020	983	/@}/ /* end of group CMSIS_DWT */
AnnaBridge	167:84c0a372a020	984
AnnaBridge	167:84c0a372a020	985
AnnaBridge	167:84c0a372a020	986	/**
AnnaBridge	167:84c0a372a020	987	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	988	\defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge	167:84c0a372a020	989	\brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge	167:84c0a372a020	990	@{
AnnaBridge	167:84c0a372a020	991	*/
AnnaBridge	167:84c0a372a020	992
AnnaBridge	167:84c0a372a020	993	/**
AnnaBridge	167:84c0a372a020	994	\brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge	167:84c0a372a020	995	*/
AnnaBridge	167:84c0a372a020	996	typedef struct
AnnaBridge	167:84c0a372a020	997	{
AnnaBridge	167:84c0a372a020	998	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
AnnaBridge	167:84c0a372a020	999	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
AnnaBridge	167:84c0a372a020	1000	uint32_t RESERVED0[2U];
AnnaBridge	167:84c0a372a020	1001	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
AnnaBridge	167:84c0a372a020	1002	uint32_t RESERVED1[55U];
AnnaBridge	167:84c0a372a020	1003	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
AnnaBridge	167:84c0a372a020	1004	uint32_t RESERVED2[131U];
AnnaBridge	167:84c0a372a020	1005	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
AnnaBridge	167:84c0a372a020	1006	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
AnnaBridge	167:84c0a372a020	1007	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
AnnaBridge	167:84c0a372a020	1008	uint32_t RESERVED3[759U];
AnnaBridge	167:84c0a372a020	1009	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
AnnaBridge	167:84c0a372a020	1010	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
AnnaBridge	167:84c0a372a020	1011	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
AnnaBridge	167:84c0a372a020	1012	uint32_t RESERVED4[1U];
AnnaBridge	167:84c0a372a020	1013	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
AnnaBridge	167:84c0a372a020	1014	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
AnnaBridge	167:84c0a372a020	1015	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
AnnaBridge	167:84c0a372a020	1016	uint32_t RESERVED5[39U];
AnnaBridge	167:84c0a372a020	1017	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
AnnaBridge	167:84c0a372a020	1018	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
AnnaBridge	167:84c0a372a020	1019	uint32_t RESERVED7[8U];
AnnaBridge	167:84c0a372a020	1020	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
AnnaBridge	167:84c0a372a020	1021	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
AnnaBridge	167:84c0a372a020	1022	} TPI_Type;
AnnaBridge	167:84c0a372a020	1023
AnnaBridge	167:84c0a372a020	1024	/* TPI Asynchronous Clock Prescaler Register Definitions */
Anna Bridge	169:a7c7b631e539	1025	#define TPI_ACPR_PRESCALER_Pos 0U /!< @Deprecated TPI ACPR: PRESCALER Position /
Anna Bridge	169:a7c7b631e539	1026	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< @Deprecated TPI ACPR: PRESCALER Mask /
Anna Bridge	169:a7c7b631e539	1027
Anna Bridge	169:a7c7b631e539	1028	#define TPI_ACPR_SWOSCALER_Pos 0U /!< TPI ACPR: SWOSCALER Position /
Anna Bridge	169:a7c7b631e539	1029	#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/) /!< TPI ACPR: SWOSCALER Mask /
AnnaBridge	167:84c0a372a020	1030
AnnaBridge	167:84c0a372a020	1031	/* TPI Selected Pin Protocol Register Definitions */
AnnaBridge	167:84c0a372a020	1032	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
AnnaBridge	167:84c0a372a020	1033	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
AnnaBridge	167:84c0a372a020	1034
AnnaBridge	167:84c0a372a020	1035	/* TPI Formatter and Flush Status Register Definitions */
AnnaBridge	167:84c0a372a020	1036	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
AnnaBridge	167:84c0a372a020	1037	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
AnnaBridge	167:84c0a372a020	1038
AnnaBridge	167:84c0a372a020	1039	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
AnnaBridge	167:84c0a372a020	1040	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
AnnaBridge	167:84c0a372a020	1041
AnnaBridge	167:84c0a372a020	1042	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
AnnaBridge	167:84c0a372a020	1043	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
AnnaBridge	167:84c0a372a020	1044
AnnaBridge	167:84c0a372a020	1045	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
AnnaBridge	167:84c0a372a020	1046	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
AnnaBridge	167:84c0a372a020	1047
AnnaBridge	167:84c0a372a020	1048	/* TPI Formatter and Flush Control Register Definitions */
AnnaBridge	167:84c0a372a020	1049	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
AnnaBridge	167:84c0a372a020	1050	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
AnnaBridge	167:84c0a372a020	1051
AnnaBridge	167:84c0a372a020	1052	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
AnnaBridge	167:84c0a372a020	1053	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
AnnaBridge	167:84c0a372a020	1054
AnnaBridge	167:84c0a372a020	1055	/* TPI TRIGGER Register Definitions */
AnnaBridge	167:84c0a372a020	1056	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
AnnaBridge	167:84c0a372a020	1057	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
AnnaBridge	167:84c0a372a020	1058
AnnaBridge	167:84c0a372a020	1059	/* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge	167:84c0a372a020	1060	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
AnnaBridge	167:84c0a372a020	1061	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
AnnaBridge	167:84c0a372a020	1062
AnnaBridge	167:84c0a372a020	1063	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
AnnaBridge	167:84c0a372a020	1064	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
AnnaBridge	167:84c0a372a020	1065
AnnaBridge	167:84c0a372a020	1066	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
AnnaBridge	167:84c0a372a020	1067	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
AnnaBridge	167:84c0a372a020	1068
AnnaBridge	167:84c0a372a020	1069	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
AnnaBridge	167:84c0a372a020	1070	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
AnnaBridge	167:84c0a372a020	1071
AnnaBridge	167:84c0a372a020	1072	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
AnnaBridge	167:84c0a372a020	1073	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
AnnaBridge	167:84c0a372a020	1074
AnnaBridge	167:84c0a372a020	1075	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
AnnaBridge	167:84c0a372a020	1076	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
AnnaBridge	167:84c0a372a020	1077
AnnaBridge	167:84c0a372a020	1078	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
AnnaBridge	167:84c0a372a020	1079	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
AnnaBridge	167:84c0a372a020	1080
AnnaBridge	167:84c0a372a020	1081	/* TPI ITATBCTR2 Register Definitions */
AnnaBridge	167:84c0a372a020	1082	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
AnnaBridge	167:84c0a372a020	1083	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
AnnaBridge	167:84c0a372a020	1084
AnnaBridge	167:84c0a372a020	1085	/* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge	167:84c0a372a020	1086	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
AnnaBridge	167:84c0a372a020	1087	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
AnnaBridge	167:84c0a372a020	1088
AnnaBridge	167:84c0a372a020	1089	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
AnnaBridge	167:84c0a372a020	1090	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
AnnaBridge	167:84c0a372a020	1091
AnnaBridge	167:84c0a372a020	1092	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
AnnaBridge	167:84c0a372a020	1093	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
AnnaBridge	167:84c0a372a020	1094
AnnaBridge	167:84c0a372a020	1095	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
AnnaBridge	167:84c0a372a020	1096	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
AnnaBridge	167:84c0a372a020	1097
AnnaBridge	167:84c0a372a020	1098	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
AnnaBridge	167:84c0a372a020	1099	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
AnnaBridge	167:84c0a372a020	1100
AnnaBridge	167:84c0a372a020	1101	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
AnnaBridge	167:84c0a372a020	1102	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
AnnaBridge	167:84c0a372a020	1103
AnnaBridge	167:84c0a372a020	1104	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
AnnaBridge	167:84c0a372a020	1105	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
AnnaBridge	167:84c0a372a020	1106
AnnaBridge	167:84c0a372a020	1107	/* TPI ITATBCTR0 Register Definitions */
AnnaBridge	167:84c0a372a020	1108	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
AnnaBridge	167:84c0a372a020	1109	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
AnnaBridge	167:84c0a372a020	1110
AnnaBridge	167:84c0a372a020	1111	/* TPI Integration Mode Control Register Definitions */
AnnaBridge	167:84c0a372a020	1112	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
AnnaBridge	167:84c0a372a020	1113	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
AnnaBridge	167:84c0a372a020	1114
AnnaBridge	167:84c0a372a020	1115	/* TPI DEVID Register Definitions */
AnnaBridge	167:84c0a372a020	1116	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
AnnaBridge	167:84c0a372a020	1117	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
AnnaBridge	167:84c0a372a020	1118
AnnaBridge	167:84c0a372a020	1119	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
AnnaBridge	167:84c0a372a020	1120	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
AnnaBridge	167:84c0a372a020	1121
AnnaBridge	167:84c0a372a020	1122	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
AnnaBridge	167:84c0a372a020	1123	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
AnnaBridge	167:84c0a372a020	1124
AnnaBridge	167:84c0a372a020	1125	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
AnnaBridge	167:84c0a372a020	1126	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
AnnaBridge	167:84c0a372a020	1127
AnnaBridge	167:84c0a372a020	1128	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
AnnaBridge	167:84c0a372a020	1129	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
AnnaBridge	167:84c0a372a020	1130
AnnaBridge	167:84c0a372a020	1131	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
AnnaBridge	167:84c0a372a020	1132	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
AnnaBridge	167:84c0a372a020	1133
AnnaBridge	167:84c0a372a020	1134	/* TPI DEVTYPE Register Definitions */
AnnaBridge	167:84c0a372a020	1135	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
AnnaBridge	167:84c0a372a020	1136	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
AnnaBridge	167:84c0a372a020	1137
AnnaBridge	167:84c0a372a020	1138	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
AnnaBridge	167:84c0a372a020	1139	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
AnnaBridge	167:84c0a372a020	1140
AnnaBridge	167:84c0a372a020	1141	/@}/ /* end of group CMSIS_TPI */
AnnaBridge	167:84c0a372a020	1142
AnnaBridge	167:84c0a372a020	1143
AnnaBridge	167:84c0a372a020	1144	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	167:84c0a372a020	1145	/**
AnnaBridge	167:84c0a372a020	1146	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	1147	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge	167:84c0a372a020	1148	\brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge	167:84c0a372a020	1149	@{
AnnaBridge	167:84c0a372a020	1150	*/
AnnaBridge	167:84c0a372a020	1151
AnnaBridge	167:84c0a372a020	1152	/**
AnnaBridge	167:84c0a372a020	1153	\brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge	167:84c0a372a020	1154	*/
AnnaBridge	167:84c0a372a020	1155	typedef struct
AnnaBridge	167:84c0a372a020	1156	{
AnnaBridge	167:84c0a372a020	1157	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
AnnaBridge	167:84c0a372a020	1158	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
AnnaBridge	167:84c0a372a020	1159	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
AnnaBridge	167:84c0a372a020	1160	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
AnnaBridge	167:84c0a372a020	1161	__IOM uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
AnnaBridge	167:84c0a372a020	1162	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
AnnaBridge	167:84c0a372a020	1163	__IOM uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
AnnaBridge	167:84c0a372a020	1164	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
AnnaBridge	167:84c0a372a020	1165	__IOM uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
AnnaBridge	167:84c0a372a020	1166	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
AnnaBridge	167:84c0a372a020	1167	__IOM uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
AnnaBridge	167:84c0a372a020	1168	} MPU_Type;
AnnaBridge	167:84c0a372a020	1169
AnnaBridge	167:84c0a372a020	1170	#define MPU_TYPE_RALIASES 4U
AnnaBridge	167:84c0a372a020	1171
AnnaBridge	167:84c0a372a020	1172	/* MPU Type Register Definitions */
AnnaBridge	167:84c0a372a020	1173	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
AnnaBridge	167:84c0a372a020	1174	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
AnnaBridge	167:84c0a372a020	1175
AnnaBridge	167:84c0a372a020	1176	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
AnnaBridge	167:84c0a372a020	1177	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
AnnaBridge	167:84c0a372a020	1178
AnnaBridge	167:84c0a372a020	1179	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
AnnaBridge	167:84c0a372a020	1180	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
AnnaBridge	167:84c0a372a020	1181
AnnaBridge	167:84c0a372a020	1182	/* MPU Control Register Definitions */
AnnaBridge	167:84c0a372a020	1183	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
AnnaBridge	167:84c0a372a020	1184	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
AnnaBridge	167:84c0a372a020	1185
AnnaBridge	167:84c0a372a020	1186	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
AnnaBridge	167:84c0a372a020	1187	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
AnnaBridge	167:84c0a372a020	1188
AnnaBridge	167:84c0a372a020	1189	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
AnnaBridge	167:84c0a372a020	1190	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
AnnaBridge	167:84c0a372a020	1191
AnnaBridge	167:84c0a372a020	1192	/* MPU Region Number Register Definitions */
AnnaBridge	167:84c0a372a020	1193	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
AnnaBridge	167:84c0a372a020	1194	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
AnnaBridge	167:84c0a372a020	1195
AnnaBridge	167:84c0a372a020	1196	/* MPU Region Base Address Register Definitions */
AnnaBridge	167:84c0a372a020	1197	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
AnnaBridge	167:84c0a372a020	1198	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
AnnaBridge	167:84c0a372a020	1199
AnnaBridge	167:84c0a372a020	1200	#define MPU_RBAR_VALID_Pos 4U /!< MPU RBAR: VALID Position /
AnnaBridge	167:84c0a372a020	1201	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
AnnaBridge	167:84c0a372a020	1202
AnnaBridge	167:84c0a372a020	1203	#define MPU_RBAR_REGION_Pos 0U /!< MPU RBAR: REGION Position /
AnnaBridge	167:84c0a372a020	1204	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
AnnaBridge	167:84c0a372a020	1205
AnnaBridge	167:84c0a372a020	1206	/* MPU Region Attribute and Size Register Definitions */
AnnaBridge	167:84c0a372a020	1207	#define MPU_RASR_ATTRS_Pos 16U /!< MPU RASR: MPU Region Attribute field Position /
AnnaBridge	167:84c0a372a020	1208	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
AnnaBridge	167:84c0a372a020	1209
AnnaBridge	167:84c0a372a020	1210	#define MPU_RASR_XN_Pos 28U /!< MPU RASR: ATTRS.XN Position /
AnnaBridge	167:84c0a372a020	1211	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
AnnaBridge	167:84c0a372a020	1212
AnnaBridge	167:84c0a372a020	1213	#define MPU_RASR_AP_Pos 24U /!< MPU RASR: ATTRS.AP Position /
AnnaBridge	167:84c0a372a020	1214	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
AnnaBridge	167:84c0a372a020	1215
AnnaBridge	167:84c0a372a020	1216	#define MPU_RASR_TEX_Pos 19U /!< MPU RASR: ATTRS.TEX Position /
AnnaBridge	167:84c0a372a020	1217	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
AnnaBridge	167:84c0a372a020	1218
AnnaBridge	167:84c0a372a020	1219	#define MPU_RASR_S_Pos 18U /!< MPU RASR: ATTRS.S Position /
AnnaBridge	167:84c0a372a020	1220	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
AnnaBridge	167:84c0a372a020	1221
AnnaBridge	167:84c0a372a020	1222	#define MPU_RASR_C_Pos 17U /!< MPU RASR: ATTRS.C Position /
AnnaBridge	167:84c0a372a020	1223	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
AnnaBridge	167:84c0a372a020	1224
AnnaBridge	167:84c0a372a020	1225	#define MPU_RASR_B_Pos 16U /!< MPU RASR: ATTRS.B Position /
AnnaBridge	167:84c0a372a020	1226	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
AnnaBridge	167:84c0a372a020	1227
AnnaBridge	167:84c0a372a020	1228	#define MPU_RASR_SRD_Pos 8U /!< MPU RASR: Sub-Region Disable Position /
AnnaBridge	167:84c0a372a020	1229	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
AnnaBridge	167:84c0a372a020	1230
AnnaBridge	167:84c0a372a020	1231	#define MPU_RASR_SIZE_Pos 1U /!< MPU RASR: Region Size Field Position /
AnnaBridge	167:84c0a372a020	1232	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
AnnaBridge	167:84c0a372a020	1233
AnnaBridge	167:84c0a372a020	1234	#define MPU_RASR_ENABLE_Pos 0U /!< MPU RASR: Region enable bit Position /
AnnaBridge	167:84c0a372a020	1235	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
AnnaBridge	167:84c0a372a020	1236
AnnaBridge	167:84c0a372a020	1237	/@} end of group CMSIS_MPU /
AnnaBridge	167:84c0a372a020	1238	#endif
AnnaBridge	167:84c0a372a020	1239
AnnaBridge	167:84c0a372a020	1240
AnnaBridge	167:84c0a372a020	1241	/**
AnnaBridge	167:84c0a372a020	1242	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	1243	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge	167:84c0a372a020	1244	\brief Type definitions for the Core Debug Registers
AnnaBridge	167:84c0a372a020	1245	@{
AnnaBridge	167:84c0a372a020	1246	*/
AnnaBridge	167:84c0a372a020	1247
AnnaBridge	167:84c0a372a020	1248	/**
AnnaBridge	167:84c0a372a020	1249	\brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge	167:84c0a372a020	1250	*/
AnnaBridge	167:84c0a372a020	1251	typedef struct
AnnaBridge	167:84c0a372a020	1252	{
AnnaBridge	167:84c0a372a020	1253	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
AnnaBridge	167:84c0a372a020	1254	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
AnnaBridge	167:84c0a372a020	1255	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
AnnaBridge	167:84c0a372a020	1256	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
AnnaBridge	167:84c0a372a020	1257	} CoreDebug_Type;
AnnaBridge	167:84c0a372a020	1258
AnnaBridge	167:84c0a372a020	1259	/* Debug Halting Control and Status Register Definitions */
AnnaBridge	167:84c0a372a020	1260	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
AnnaBridge	167:84c0a372a020	1261	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
AnnaBridge	167:84c0a372a020	1262
AnnaBridge	167:84c0a372a020	1263	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
AnnaBridge	167:84c0a372a020	1264	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
AnnaBridge	167:84c0a372a020	1265
AnnaBridge	167:84c0a372a020	1266	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
AnnaBridge	167:84c0a372a020	1267	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
AnnaBridge	167:84c0a372a020	1268
AnnaBridge	167:84c0a372a020	1269	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
AnnaBridge	167:84c0a372a020	1270	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
AnnaBridge	167:84c0a372a020	1271
AnnaBridge	167:84c0a372a020	1272	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
AnnaBridge	167:84c0a372a020	1273	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
AnnaBridge	167:84c0a372a020	1274
AnnaBridge	167:84c0a372a020	1275	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
AnnaBridge	167:84c0a372a020	1276	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
AnnaBridge	167:84c0a372a020	1277
AnnaBridge	167:84c0a372a020	1278	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
AnnaBridge	167:84c0a372a020	1279	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
AnnaBridge	167:84c0a372a020	1280
AnnaBridge	167:84c0a372a020	1281	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
AnnaBridge	167:84c0a372a020	1282	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
AnnaBridge	167:84c0a372a020	1283
AnnaBridge	167:84c0a372a020	1284	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
AnnaBridge	167:84c0a372a020	1285	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
AnnaBridge	167:84c0a372a020	1286
AnnaBridge	167:84c0a372a020	1287	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
AnnaBridge	167:84c0a372a020	1288	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
AnnaBridge	167:84c0a372a020	1289
AnnaBridge	167:84c0a372a020	1290	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
AnnaBridge	167:84c0a372a020	1291	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
AnnaBridge	167:84c0a372a020	1292
AnnaBridge	167:84c0a372a020	1293	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
AnnaBridge	167:84c0a372a020	1294	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
AnnaBridge	167:84c0a372a020	1295
AnnaBridge	167:84c0a372a020	1296	/* Debug Core Register Selector Register Definitions */
AnnaBridge	167:84c0a372a020	1297	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
AnnaBridge	167:84c0a372a020	1298	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
AnnaBridge	167:84c0a372a020	1299
AnnaBridge	167:84c0a372a020	1300	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
AnnaBridge	167:84c0a372a020	1301	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
AnnaBridge	167:84c0a372a020	1302
AnnaBridge	167:84c0a372a020	1303	/* Debug Exception and Monitor Control Register Definitions */
AnnaBridge	167:84c0a372a020	1304	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
AnnaBridge	167:84c0a372a020	1305	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
AnnaBridge	167:84c0a372a020	1306
AnnaBridge	167:84c0a372a020	1307	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
AnnaBridge	167:84c0a372a020	1308	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
AnnaBridge	167:84c0a372a020	1309
AnnaBridge	167:84c0a372a020	1310	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
AnnaBridge	167:84c0a372a020	1311	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
AnnaBridge	167:84c0a372a020	1312
AnnaBridge	167:84c0a372a020	1313	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
AnnaBridge	167:84c0a372a020	1314	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
AnnaBridge	167:84c0a372a020	1315
AnnaBridge	167:84c0a372a020	1316	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
AnnaBridge	167:84c0a372a020	1317	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
AnnaBridge	167:84c0a372a020	1318
AnnaBridge	167:84c0a372a020	1319	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
AnnaBridge	167:84c0a372a020	1320	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
AnnaBridge	167:84c0a372a020	1321
AnnaBridge	167:84c0a372a020	1322	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
AnnaBridge	167:84c0a372a020	1323	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
AnnaBridge	167:84c0a372a020	1324
AnnaBridge	167:84c0a372a020	1325	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
AnnaBridge	167:84c0a372a020	1326	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
AnnaBridge	167:84c0a372a020	1327
AnnaBridge	167:84c0a372a020	1328	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
AnnaBridge	167:84c0a372a020	1329	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
AnnaBridge	167:84c0a372a020	1330
AnnaBridge	167:84c0a372a020	1331	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
AnnaBridge	167:84c0a372a020	1332	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
AnnaBridge	167:84c0a372a020	1333
AnnaBridge	167:84c0a372a020	1334	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
AnnaBridge	167:84c0a372a020	1335	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
AnnaBridge	167:84c0a372a020	1336
AnnaBridge	167:84c0a372a020	1337	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
AnnaBridge	167:84c0a372a020	1338	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
AnnaBridge	167:84c0a372a020	1339
AnnaBridge	167:84c0a372a020	1340	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
AnnaBridge	167:84c0a372a020	1341	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
AnnaBridge	167:84c0a372a020	1342
AnnaBridge	167:84c0a372a020	1343	/@} end of group CMSIS_CoreDebug /
AnnaBridge	167:84c0a372a020	1344
AnnaBridge	167:84c0a372a020	1345
AnnaBridge	167:84c0a372a020	1346	/**
AnnaBridge	167:84c0a372a020	1347	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	1348	\defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge	167:84c0a372a020	1349	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge	167:84c0a372a020	1350	@{
AnnaBridge	167:84c0a372a020	1351	*/
AnnaBridge	167:84c0a372a020	1352
AnnaBridge	167:84c0a372a020	1353	/**
AnnaBridge	167:84c0a372a020	1354	\brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge	167:84c0a372a020	1355	\param[in] field Name of the register bit field.
AnnaBridge	167:84c0a372a020	1356	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge	167:84c0a372a020	1357	\return Masked and shifted value.
AnnaBridge	167:84c0a372a020	1358	*/
AnnaBridge	167:84c0a372a020	1359	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge	167:84c0a372a020	1360
AnnaBridge	167:84c0a372a020	1361	/**
AnnaBridge	167:84c0a372a020	1362	\brief Mask and shift a register value to extract a bit filed value.
AnnaBridge	167:84c0a372a020	1363	\param[in] field Name of the register bit field.
AnnaBridge	167:84c0a372a020	1364	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge	167:84c0a372a020	1365	\return Masked and shifted bit field value.
AnnaBridge	167:84c0a372a020	1366	*/
AnnaBridge	167:84c0a372a020	1367	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge	167:84c0a372a020	1368
AnnaBridge	167:84c0a372a020	1369	/@} end of group CMSIS_core_bitfield /
AnnaBridge	167:84c0a372a020	1370
AnnaBridge	167:84c0a372a020	1371
AnnaBridge	167:84c0a372a020	1372	/**
AnnaBridge	167:84c0a372a020	1373	\ingroup CMSIS_core_register
AnnaBridge	167:84c0a372a020	1374	\defgroup CMSIS_core_base Core Definitions
AnnaBridge	167:84c0a372a020	1375	\brief Definitions for base addresses, unions, and structures.
AnnaBridge	167:84c0a372a020	1376	@{
AnnaBridge	167:84c0a372a020	1377	*/
AnnaBridge	167:84c0a372a020	1378
AnnaBridge	167:84c0a372a020	1379	/* Memory mapping of Core Hardware */
AnnaBridge	167:84c0a372a020	1380	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
AnnaBridge	167:84c0a372a020	1381	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
AnnaBridge	167:84c0a372a020	1382	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
AnnaBridge	167:84c0a372a020	1383	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
AnnaBridge	167:84c0a372a020	1384	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
AnnaBridge	167:84c0a372a020	1385	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
AnnaBridge	167:84c0a372a020	1386	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
AnnaBridge	167:84c0a372a020	1387	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
AnnaBridge	167:84c0a372a020	1388
AnnaBridge	167:84c0a372a020	1389	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
AnnaBridge	167:84c0a372a020	1390	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
AnnaBridge	167:84c0a372a020	1391	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
AnnaBridge	167:84c0a372a020	1392	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
AnnaBridge	167:84c0a372a020	1393	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
AnnaBridge	167:84c0a372a020	1394	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
AnnaBridge	167:84c0a372a020	1395	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
AnnaBridge	167:84c0a372a020	1396	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
AnnaBridge	167:84c0a372a020	1397
AnnaBridge	167:84c0a372a020	1398	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	167:84c0a372a020	1399	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
AnnaBridge	167:84c0a372a020	1400	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
AnnaBridge	167:84c0a372a020	1401	#endif
AnnaBridge	167:84c0a372a020	1402
AnnaBridge	167:84c0a372a020	1403	/@} /
AnnaBridge	167:84c0a372a020	1404
AnnaBridge	167:84c0a372a020	1405
AnnaBridge	167:84c0a372a020	1406
AnnaBridge	167:84c0a372a020	1407	/*******************************************************************************
AnnaBridge	167:84c0a372a020	1408	* Hardware Abstraction Layer
AnnaBridge	167:84c0a372a020	1409	Core Function Interface contains:
AnnaBridge	167:84c0a372a020	1410	- Core NVIC Functions
AnnaBridge	167:84c0a372a020	1411	- Core SysTick Functions
AnnaBridge	167:84c0a372a020	1412	- Core Debug Functions
AnnaBridge	167:84c0a372a020	1413	- Core Register Access Functions
AnnaBridge	167:84c0a372a020	1414	******************************************************************************/
AnnaBridge	167:84c0a372a020	1415	/**
AnnaBridge	167:84c0a372a020	1416	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge	167:84c0a372a020	1417	*/
AnnaBridge	167:84c0a372a020	1418
AnnaBridge	167:84c0a372a020	1419
AnnaBridge	167:84c0a372a020	1420
AnnaBridge	167:84c0a372a020	1421	/* ########################## NVIC functions #################################### */
AnnaBridge	167:84c0a372a020	1422	/**
AnnaBridge	167:84c0a372a020	1423	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:84c0a372a020	1424	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge	167:84c0a372a020	1425	\brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge	167:84c0a372a020	1426	@{
AnnaBridge	167:84c0a372a020	1427	*/
AnnaBridge	167:84c0a372a020	1428
AnnaBridge	167:84c0a372a020	1429	#ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge	167:84c0a372a020	1430	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	167:84c0a372a020	1431	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge	167:84c0a372a020	1432	#endif
AnnaBridge	167:84c0a372a020	1433	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	167:84c0a372a020	1434	#else
AnnaBridge	167:84c0a372a020	1435	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
AnnaBridge	167:84c0a372a020	1436	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
AnnaBridge	167:84c0a372a020	1437	#define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge	167:84c0a372a020	1438	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge	167:84c0a372a020	1439	#define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge	167:84c0a372a020	1440	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge	167:84c0a372a020	1441	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge	167:84c0a372a020	1442	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge	167:84c0a372a020	1443	#define NVIC_GetActive __NVIC_GetActive
AnnaBridge	167:84c0a372a020	1444	#define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge	167:84c0a372a020	1445	#define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge	167:84c0a372a020	1446	#define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge	167:84c0a372a020	1447	#endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge	167:84c0a372a020	1448
AnnaBridge	167:84c0a372a020	1449	#ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge	167:84c0a372a020	1450	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	167:84c0a372a020	1451	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge	167:84c0a372a020	1452	#endif
AnnaBridge	167:84c0a372a020	1453	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	167:84c0a372a020	1454	#else
AnnaBridge	167:84c0a372a020	1455	#define NVIC_SetVector __NVIC_SetVector
AnnaBridge	167:84c0a372a020	1456	#define NVIC_GetVector __NVIC_GetVector
AnnaBridge	167:84c0a372a020	1457	#endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge	167:84c0a372a020	1458
AnnaBridge	167:84c0a372a020	1459	#define NVIC_USER_IRQ_OFFSET 16
AnnaBridge	167:84c0a372a020	1460
AnnaBridge	167:84c0a372a020	1461
AnnaBridge	167:84c0a372a020	1462
AnnaBridge	167:84c0a372a020	1463	/**
AnnaBridge	167:84c0a372a020	1464	\brief Set Priority Grouping
AnnaBridge	167:84c0a372a020	1465	\details Sets the priority grouping field using the required unlock sequence.
AnnaBridge	167:84c0a372a020	1466	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge	167:84c0a372a020	1467	Only values from 0..7 are used.
AnnaBridge	167:84c0a372a020	1468	In case of a conflict between priority grouping and available
AnnaBridge	167:84c0a372a020	1469	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	167:84c0a372a020	1470	\param [in] PriorityGroup Priority grouping field.
AnnaBridge	167:84c0a372a020	1471	*/
AnnaBridge	167:84c0a372a020	1472	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
AnnaBridge	167:84c0a372a020	1473	{
AnnaBridge	167:84c0a372a020	1474	uint32_t reg_value;
AnnaBridge	167:84c0a372a020	1475	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	167:84c0a372a020	1476
AnnaBridge	167:84c0a372a020	1477	reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge	167:84c0a372a020	1478	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge	167:84c0a372a020	1479	reg_value = (reg_value \|
AnnaBridge	167:84c0a372a020	1480	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Anna Bridge	169:a7c7b631e539	1481	(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
AnnaBridge	167:84c0a372a020	1482	SCB->AIRCR = reg_value;
AnnaBridge	167:84c0a372a020	1483	}
AnnaBridge	167:84c0a372a020	1484
AnnaBridge	167:84c0a372a020	1485
AnnaBridge	167:84c0a372a020	1486	/**
AnnaBridge	167:84c0a372a020	1487	\brief Get Priority Grouping
AnnaBridge	167:84c0a372a020	1488	\details Reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge	167:84c0a372a020	1489	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge	167:84c0a372a020	1490	*/
AnnaBridge	167:84c0a372a020	1491	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
AnnaBridge	167:84c0a372a020	1492	{
AnnaBridge	167:84c0a372a020	1493	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge	167:84c0a372a020	1494	}
AnnaBridge	167:84c0a372a020	1495
AnnaBridge	167:84c0a372a020	1496
AnnaBridge	167:84c0a372a020	1497	/**
AnnaBridge	167:84c0a372a020	1498	\brief Enable Interrupt
AnnaBridge	167:84c0a372a020	1499	\details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	167:84c0a372a020	1500	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	1501	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	1502	*/
AnnaBridge	167:84c0a372a020	1503	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	1504	{
AnnaBridge	167:84c0a372a020	1505	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	1506	{
Anna Bridge	169:a7c7b631e539	1507	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	167:84c0a372a020	1508	}
AnnaBridge	167:84c0a372a020	1509	}
AnnaBridge	167:84c0a372a020	1510
AnnaBridge	167:84c0a372a020	1511
AnnaBridge	167:84c0a372a020	1512	/**
AnnaBridge	167:84c0a372a020	1513	\brief Get Interrupt Enable status
AnnaBridge	167:84c0a372a020	1514	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge	167:84c0a372a020	1515	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	1516	\return 0 Interrupt is not enabled.
AnnaBridge	167:84c0a372a020	1517	\return 1 Interrupt is enabled.
AnnaBridge	167:84c0a372a020	1518	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	1519	*/
AnnaBridge	167:84c0a372a020	1520	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	1521	{
AnnaBridge	167:84c0a372a020	1522	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	1523	{
Anna Bridge	169:a7c7b631e539	1524	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:84c0a372a020	1525	}
AnnaBridge	167:84c0a372a020	1526	else
AnnaBridge	167:84c0a372a020	1527	{
AnnaBridge	167:84c0a372a020	1528	return(0U);
AnnaBridge	167:84c0a372a020	1529	}
AnnaBridge	167:84c0a372a020	1530	}
AnnaBridge	167:84c0a372a020	1531
AnnaBridge	167:84c0a372a020	1532
AnnaBridge	167:84c0a372a020	1533	/**
AnnaBridge	167:84c0a372a020	1534	\brief Disable Interrupt
AnnaBridge	167:84c0a372a020	1535	\details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	167:84c0a372a020	1536	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	1537	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	1538	*/
AnnaBridge	167:84c0a372a020	1539	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	1540	{
AnnaBridge	167:84c0a372a020	1541	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	1542	{
Anna Bridge	169:a7c7b631e539	1543	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	167:84c0a372a020	1544	__DSB();
AnnaBridge	167:84c0a372a020	1545	__ISB();
AnnaBridge	167:84c0a372a020	1546	}
AnnaBridge	167:84c0a372a020	1547	}
AnnaBridge	167:84c0a372a020	1548
AnnaBridge	167:84c0a372a020	1549
AnnaBridge	167:84c0a372a020	1550	/**
AnnaBridge	167:84c0a372a020	1551	\brief Get Pending Interrupt
AnnaBridge	167:84c0a372a020	1552	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge	167:84c0a372a020	1553	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	1554	\return 0 Interrupt status is not pending.
AnnaBridge	167:84c0a372a020	1555	\return 1 Interrupt status is pending.
AnnaBridge	167:84c0a372a020	1556	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	1557	*/
AnnaBridge	167:84c0a372a020	1558	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	1559	{
AnnaBridge	167:84c0a372a020	1560	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	1561	{
Anna Bridge	169:a7c7b631e539	1562	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:84c0a372a020	1563	}
AnnaBridge	167:84c0a372a020	1564	else
AnnaBridge	167:84c0a372a020	1565	{
AnnaBridge	167:84c0a372a020	1566	return(0U);
AnnaBridge	167:84c0a372a020	1567	}
AnnaBridge	167:84c0a372a020	1568	}
AnnaBridge	167:84c0a372a020	1569
AnnaBridge	167:84c0a372a020	1570
AnnaBridge	167:84c0a372a020	1571	/**
AnnaBridge	167:84c0a372a020	1572	\brief Set Pending Interrupt
AnnaBridge	167:84c0a372a020	1573	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	167:84c0a372a020	1574	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	1575	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	1576	*/
AnnaBridge	167:84c0a372a020	1577	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	1578	{
AnnaBridge	167:84c0a372a020	1579	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	1580	{
Anna Bridge	169:a7c7b631e539	1581	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	167:84c0a372a020	1582	}
AnnaBridge	167:84c0a372a020	1583	}
AnnaBridge	167:84c0a372a020	1584
AnnaBridge	167:84c0a372a020	1585
AnnaBridge	167:84c0a372a020	1586	/**
AnnaBridge	167:84c0a372a020	1587	\brief Clear Pending Interrupt
AnnaBridge	167:84c0a372a020	1588	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	167:84c0a372a020	1589	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	1590	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	1591	*/
AnnaBridge	167:84c0a372a020	1592	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	1593	{
AnnaBridge	167:84c0a372a020	1594	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	1595	{
Anna Bridge	169:a7c7b631e539	1596	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	167:84c0a372a020	1597	}
AnnaBridge	167:84c0a372a020	1598	}
AnnaBridge	167:84c0a372a020	1599
AnnaBridge	167:84c0a372a020	1600
AnnaBridge	167:84c0a372a020	1601	/**
AnnaBridge	167:84c0a372a020	1602	\brief Get Active Interrupt
AnnaBridge	167:84c0a372a020	1603	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge	167:84c0a372a020	1604	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:84c0a372a020	1605	\return 0 Interrupt status is not active.
AnnaBridge	167:84c0a372a020	1606	\return 1 Interrupt status is active.
AnnaBridge	167:84c0a372a020	1607	\note IRQn must not be negative.
AnnaBridge	167:84c0a372a020	1608	*/
AnnaBridge	167:84c0a372a020	1609	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	1610	{
AnnaBridge	167:84c0a372a020	1611	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	1612	{
Anna Bridge	169:a7c7b631e539	1613	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:84c0a372a020	1614	}
AnnaBridge	167:84c0a372a020	1615	else
AnnaBridge	167:84c0a372a020	1616	{
AnnaBridge	167:84c0a372a020	1617	return(0U);
AnnaBridge	167:84c0a372a020	1618	}
AnnaBridge	167:84c0a372a020	1619	}
AnnaBridge	167:84c0a372a020	1620
AnnaBridge	167:84c0a372a020	1621
AnnaBridge	167:84c0a372a020	1622	/**
AnnaBridge	167:84c0a372a020	1623	\brief Set Interrupt Priority
AnnaBridge	167:84c0a372a020	1624	\details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge	167:84c0a372a020	1625	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:84c0a372a020	1626	or negative to specify a processor exception.
AnnaBridge	167:84c0a372a020	1627	\param [in] IRQn Interrupt number.
AnnaBridge	167:84c0a372a020	1628	\param [in] priority Priority to set.
AnnaBridge	167:84c0a372a020	1629	\note The priority cannot be set for every processor exception.
AnnaBridge	167:84c0a372a020	1630	*/
AnnaBridge	167:84c0a372a020	1631	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	167:84c0a372a020	1632	{
AnnaBridge	167:84c0a372a020	1633	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	1634	{
Anna Bridge	169:a7c7b631e539	1635	NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	167:84c0a372a020	1636	}
AnnaBridge	167:84c0a372a020	1637	else
AnnaBridge	167:84c0a372a020	1638	{
Anna Bridge	169:a7c7b631e539	1639	SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	167:84c0a372a020	1640	}
AnnaBridge	167:84c0a372a020	1641	}
AnnaBridge	167:84c0a372a020	1642
AnnaBridge	167:84c0a372a020	1643
AnnaBridge	167:84c0a372a020	1644	/**
AnnaBridge	167:84c0a372a020	1645	\brief Get Interrupt Priority
AnnaBridge	167:84c0a372a020	1646	\details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge	167:84c0a372a020	1647	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:84c0a372a020	1648	or negative to specify a processor exception.
AnnaBridge	167:84c0a372a020	1649	\param [in] IRQn Interrupt number.
AnnaBridge	167:84c0a372a020	1650	\return Interrupt Priority.
AnnaBridge	167:84c0a372a020	1651	Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	167:84c0a372a020	1652	*/
AnnaBridge	167:84c0a372a020	1653	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	1654	{
AnnaBridge	167:84c0a372a020	1655
AnnaBridge	167:84c0a372a020	1656	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:84c0a372a020	1657	{
Anna Bridge	169:a7c7b631e539	1658	return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	167:84c0a372a020	1659	}
AnnaBridge	167:84c0a372a020	1660	else
AnnaBridge	167:84c0a372a020	1661	{
Anna Bridge	169:a7c7b631e539	1662	return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	167:84c0a372a020	1663	}
AnnaBridge	167:84c0a372a020	1664	}
AnnaBridge	167:84c0a372a020	1665
AnnaBridge	167:84c0a372a020	1666
AnnaBridge	167:84c0a372a020	1667	/**
AnnaBridge	167:84c0a372a020	1668	\brief Encode Priority
AnnaBridge	167:84c0a372a020	1669	\details Encodes the priority for an interrupt with the given priority group,
AnnaBridge	167:84c0a372a020	1670	preemptive priority value, and subpriority value.
AnnaBridge	167:84c0a372a020	1671	In case of a conflict between priority grouping and available
AnnaBridge	167:84c0a372a020	1672	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	167:84c0a372a020	1673	\param [in] PriorityGroup Used priority group.
AnnaBridge	167:84c0a372a020	1674	\param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	167:84c0a372a020	1675	\param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge	167:84c0a372a020	1676	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge	167:84c0a372a020	1677	*/
AnnaBridge	167:84c0a372a020	1678	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge	167:84c0a372a020	1679	{
AnnaBridge	167:84c0a372a020	1680	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	167:84c0a372a020	1681	uint32_t PreemptPriorityBits;
AnnaBridge	167:84c0a372a020	1682	uint32_t SubPriorityBits;
AnnaBridge	167:84c0a372a020	1683
AnnaBridge	167:84c0a372a020	1684	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	167:84c0a372a020	1685	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	167:84c0a372a020	1686
AnnaBridge	167:84c0a372a020	1687	return (
AnnaBridge	167:84c0a372a020	1688	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
AnnaBridge	167:84c0a372a020	1689	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge	167:84c0a372a020	1690	);
AnnaBridge	167:84c0a372a020	1691	}
AnnaBridge	167:84c0a372a020	1692
AnnaBridge	167:84c0a372a020	1693
AnnaBridge	167:84c0a372a020	1694	/**
AnnaBridge	167:84c0a372a020	1695	\brief Decode Priority
AnnaBridge	167:84c0a372a020	1696	\details Decodes an interrupt priority value with a given priority group to
AnnaBridge	167:84c0a372a020	1697	preemptive priority value and subpriority value.
AnnaBridge	167:84c0a372a020	1698	In case of a conflict between priority grouping and available
AnnaBridge	167:84c0a372a020	1699	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge	167:84c0a372a020	1700	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge	167:84c0a372a020	1701	\param [in] PriorityGroup Used priority group.
AnnaBridge	167:84c0a372a020	1702	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	167:84c0a372a020	1703	\param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge	167:84c0a372a020	1704	*/
AnnaBridge	167:84c0a372a020	1705	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
AnnaBridge	167:84c0a372a020	1706	{
AnnaBridge	167:84c0a372a020	1707	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	167:84c0a372a020	1708	uint32_t PreemptPriorityBits;
AnnaBridge	167:84c0a372a020	1709	uint32_t SubPriorityBits;
AnnaBridge	167:84c0a372a020	1710
AnnaBridge	167:84c0a372a020	1711	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	167:84c0a372a020	1712	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	167:84c0a372a020	1713
AnnaBridge	167:84c0a372a020	1714	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge	167:84c0a372a020	1715	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge	167:84c0a372a020	1716	}
AnnaBridge	167:84c0a372a020	1717
AnnaBridge	167:84c0a372a020	1718
AnnaBridge	167:84c0a372a020	1719	/**
AnnaBridge	167:84c0a372a020	1720	\brief Set Interrupt Vector
AnnaBridge	167:84c0a372a020	1721	\details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge	167:84c0a372a020	1722	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:84c0a372a020	1723	or negative to specify a processor exception.
AnnaBridge	167:84c0a372a020	1724	VTOR must been relocated to SRAM before.
AnnaBridge	167:84c0a372a020	1725	\param [in] IRQn Interrupt number
AnnaBridge	167:84c0a372a020	1726	\param [in] vector Address of interrupt handler function
AnnaBridge	167:84c0a372a020	1727	*/
AnnaBridge	167:84c0a372a020	1728	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge	167:84c0a372a020	1729	{
AnnaBridge	167:84c0a372a020	1730	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	167:84c0a372a020	1731	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge	167:84c0a372a020	1732	}
AnnaBridge	167:84c0a372a020	1733
AnnaBridge	167:84c0a372a020	1734
AnnaBridge	167:84c0a372a020	1735	/**
AnnaBridge	167:84c0a372a020	1736	\brief Get Interrupt Vector
AnnaBridge	167:84c0a372a020	1737	\details Reads an interrupt vector from interrupt vector table.
AnnaBridge	167:84c0a372a020	1738	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:84c0a372a020	1739	or negative to specify a processor exception.
AnnaBridge	167:84c0a372a020	1740	\param [in] IRQn Interrupt number.
AnnaBridge	167:84c0a372a020	1741	\return Address of interrupt handler function
AnnaBridge	167:84c0a372a020	1742	*/
AnnaBridge	167:84c0a372a020	1743	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge	167:84c0a372a020	1744	{
AnnaBridge	167:84c0a372a020	1745	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	167:84c0a372a020	1746	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge	167:84c0a372a020	1747	}
AnnaBridge	167:84c0a372a020	1748
AnnaBridge	167:84c0a372a020	1749
AnnaBridge	167:84c0a372a020	1750	/**
AnnaBridge	167:84c0a372a020	1751	\brief System Reset
AnnaBridge	167:84c0a372a020	1752	\details Initiates a system reset request to reset the MCU.
AnnaBridge	167:84c0a372a020	1753	*/
AnnaBridge	167:84c0a372a020	1754	__STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge	167:84c0a372a020	1755	{
AnnaBridge	167:84c0a372a020	1756	__DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge	167:84c0a372a020	1757	buffered write are completed before reset */
AnnaBridge	167:84c0a372a020	1758	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	167:84c0a372a020	1759	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
AnnaBridge	167:84c0a372a020	1760	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
AnnaBridge	167:84c0a372a020	1761	__DSB(); /* Ensure completion of memory access */
AnnaBridge	167:84c0a372a020	1762
AnnaBridge	167:84c0a372a020	1763	for(;;) /* wait until reset */
AnnaBridge	167:84c0a372a020	1764	{
AnnaBridge	167:84c0a372a020	1765	__NOP();
AnnaBridge	167:84c0a372a020	1766	}
AnnaBridge	167:84c0a372a020	1767	}
AnnaBridge	167:84c0a372a020	1768
AnnaBridge	167:84c0a372a020	1769	/@} end of CMSIS_Core_NVICFunctions /
AnnaBridge	167:84c0a372a020	1770
AnnaBridge	167:84c0a372a020	1771	/* ########################## MPU functions #################################### */
AnnaBridge	167:84c0a372a020	1772
AnnaBridge	167:84c0a372a020	1773	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	167:84c0a372a020	1774
AnnaBridge	167:84c0a372a020	1775	#include "mpu_armv7.h"
AnnaBridge	167:84c0a372a020	1776
AnnaBridge	167:84c0a372a020	1777	#endif
AnnaBridge	167:84c0a372a020	1778
AnnaBridge	167:84c0a372a020	1779	/* ########################## FPU functions #################################### */
AnnaBridge	167:84c0a372a020	1780	/**
AnnaBridge	167:84c0a372a020	1781	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:84c0a372a020	1782	\defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge	167:84c0a372a020	1783	\brief Function that provides FPU type.
AnnaBridge	167:84c0a372a020	1784	@{
AnnaBridge	167:84c0a372a020	1785	*/
AnnaBridge	167:84c0a372a020	1786
AnnaBridge	167:84c0a372a020	1787	/**
AnnaBridge	167:84c0a372a020	1788	\brief get FPU type
AnnaBridge	167:84c0a372a020	1789	\details returns the FPU type
AnnaBridge	167:84c0a372a020	1790	\returns
AnnaBridge	167:84c0a372a020	1791	- \b 0: No FPU
AnnaBridge	167:84c0a372a020	1792	- \b 1: Single precision FPU
AnnaBridge	167:84c0a372a020	1793	- \b 2: Double + Single precision FPU
AnnaBridge	167:84c0a372a020	1794	*/
AnnaBridge	167:84c0a372a020	1795	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge	167:84c0a372a020	1796	{
AnnaBridge	167:84c0a372a020	1797	return 0U; /* No FPU */
AnnaBridge	167:84c0a372a020	1798	}
AnnaBridge	167:84c0a372a020	1799
AnnaBridge	167:84c0a372a020	1800
AnnaBridge	167:84c0a372a020	1801	/@} end of CMSIS_Core_FpuFunctions /
AnnaBridge	167:84c0a372a020	1802
AnnaBridge	167:84c0a372a020	1803
AnnaBridge	167:84c0a372a020	1804
AnnaBridge	167:84c0a372a020	1805	/* ################################## SysTick function ############################################ */
AnnaBridge	167:84c0a372a020	1806	/**
AnnaBridge	167:84c0a372a020	1807	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:84c0a372a020	1808	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge	167:84c0a372a020	1809	\brief Functions that configure the System.
AnnaBridge	167:84c0a372a020	1810	@{
AnnaBridge	167:84c0a372a020	1811	*/
AnnaBridge	167:84c0a372a020	1812
AnnaBridge	167:84c0a372a020	1813	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge	167:84c0a372a020	1814
AnnaBridge	167:84c0a372a020	1815	/**
AnnaBridge	167:84c0a372a020	1816	\brief System Tick Configuration
AnnaBridge	167:84c0a372a020	1817	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge	167:84c0a372a020	1818	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	167:84c0a372a020	1819	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	167:84c0a372a020	1820	\return 0 Function succeeded.
AnnaBridge	167:84c0a372a020	1821	\return 1 Function failed.
AnnaBridge	167:84c0a372a020	1822	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	167:84c0a372a020	1823	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	167:84c0a372a020	1824	must contain a vendor-specific implementation of this function.
AnnaBridge	167:84c0a372a020	1825	*/
AnnaBridge	167:84c0a372a020	1826	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge	167:84c0a372a020	1827	{
AnnaBridge	167:84c0a372a020	1828	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	167:84c0a372a020	1829	{
AnnaBridge	167:84c0a372a020	1830	return (1UL); /* Reload value impossible */
AnnaBridge	167:84c0a372a020	1831	}
AnnaBridge	167:84c0a372a020	1832
AnnaBridge	167:84c0a372a020	1833	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	167:84c0a372a020	1834	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	167:84c0a372a020	1835	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	167:84c0a372a020	1836	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	167:84c0a372a020	1837	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	167:84c0a372a020	1838	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	167:84c0a372a020	1839	return (0UL); /* Function successful */
AnnaBridge	167:84c0a372a020	1840	}
AnnaBridge	167:84c0a372a020	1841
AnnaBridge	167:84c0a372a020	1842	#endif
AnnaBridge	167:84c0a372a020	1843
AnnaBridge	167:84c0a372a020	1844	/@} end of CMSIS_Core_SysTickFunctions /
AnnaBridge	167:84c0a372a020	1845
AnnaBridge	167:84c0a372a020	1846
AnnaBridge	167:84c0a372a020	1847
AnnaBridge	167:84c0a372a020	1848	/* ##################################### Debug In/Output function ########################################### */
AnnaBridge	167:84c0a372a020	1849	/**
AnnaBridge	167:84c0a372a020	1850	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:84c0a372a020	1851	\defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge	167:84c0a372a020	1852	\brief Functions that access the ITM debug interface.
AnnaBridge	167:84c0a372a020	1853	@{
AnnaBridge	167:84c0a372a020	1854	*/
AnnaBridge	167:84c0a372a020	1855
AnnaBridge	167:84c0a372a020	1856	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
AnnaBridge	167:84c0a372a020	1857	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
AnnaBridge	167:84c0a372a020	1858
AnnaBridge	167:84c0a372a020	1859
AnnaBridge	167:84c0a372a020	1860	/**
AnnaBridge	167:84c0a372a020	1861	\brief ITM Send Character
AnnaBridge	167:84c0a372a020	1862	\details Transmits a character via the ITM channel 0, and
AnnaBridge	167:84c0a372a020	1863	\li Just returns when no debugger is connected that has booked the output.
AnnaBridge	167:84c0a372a020	1864	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge	167:84c0a372a020	1865	\param [in] ch Character to transmit.
AnnaBridge	167:84c0a372a020	1866	\returns Character to transmit.
AnnaBridge	167:84c0a372a020	1867	*/
AnnaBridge	167:84c0a372a020	1868	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
AnnaBridge	167:84c0a372a020	1869	{
AnnaBridge	167:84c0a372a020	1870	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
AnnaBridge	167:84c0a372a020	1871	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
AnnaBridge	167:84c0a372a020	1872	{
AnnaBridge	167:84c0a372a020	1873	while (ITM->PORT[0U].u32 == 0UL)
AnnaBridge	167:84c0a372a020	1874	{
AnnaBridge	167:84c0a372a020	1875	__NOP();
AnnaBridge	167:84c0a372a020	1876	}
AnnaBridge	167:84c0a372a020	1877	ITM->PORT[0U].u8 = (uint8_t)ch;
AnnaBridge	167:84c0a372a020	1878	}
AnnaBridge	167:84c0a372a020	1879	return (ch);
AnnaBridge	167:84c0a372a020	1880	}
AnnaBridge	167:84c0a372a020	1881
AnnaBridge	167:84c0a372a020	1882
AnnaBridge	167:84c0a372a020	1883	/**
AnnaBridge	167:84c0a372a020	1884	\brief ITM Receive Character
AnnaBridge	167:84c0a372a020	1885	\details Inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge	167:84c0a372a020	1886	\return Received character.
AnnaBridge	167:84c0a372a020	1887	\return -1 No character pending.
AnnaBridge	167:84c0a372a020	1888	*/
AnnaBridge	167:84c0a372a020	1889	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
AnnaBridge	167:84c0a372a020	1890	{
AnnaBridge	167:84c0a372a020	1891	int32_t ch = -1; /* no character available */
AnnaBridge	167:84c0a372a020	1892
AnnaBridge	167:84c0a372a020	1893	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
AnnaBridge	167:84c0a372a020	1894	{
AnnaBridge	167:84c0a372a020	1895	ch = ITM_RxBuffer;
AnnaBridge	167:84c0a372a020	1896	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
AnnaBridge	167:84c0a372a020	1897	}
AnnaBridge	167:84c0a372a020	1898
AnnaBridge	167:84c0a372a020	1899	return (ch);
AnnaBridge	167:84c0a372a020	1900	}
AnnaBridge	167:84c0a372a020	1901
AnnaBridge	167:84c0a372a020	1902
AnnaBridge	167:84c0a372a020	1903	/**
AnnaBridge	167:84c0a372a020	1904	\brief ITM Check Character
AnnaBridge	167:84c0a372a020	1905	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge	167:84c0a372a020	1906	\return 0 No character available.
AnnaBridge	167:84c0a372a020	1907	\return 1 Character available.
AnnaBridge	167:84c0a372a020	1908	*/
AnnaBridge	167:84c0a372a020	1909	__STATIC_INLINE int32_t ITM_CheckChar (void)
AnnaBridge	167:84c0a372a020	1910	{
AnnaBridge	167:84c0a372a020	1911
AnnaBridge	167:84c0a372a020	1912	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
AnnaBridge	167:84c0a372a020	1913	{
AnnaBridge	167:84c0a372a020	1914	return (0); /* no character available */
AnnaBridge	167:84c0a372a020	1915	}
AnnaBridge	167:84c0a372a020	1916	else
AnnaBridge	167:84c0a372a020	1917	{
AnnaBridge	167:84c0a372a020	1918	return (1); /* character available */
AnnaBridge	167:84c0a372a020	1919	}
AnnaBridge	167:84c0a372a020	1920	}
AnnaBridge	167:84c0a372a020	1921
AnnaBridge	167:84c0a372a020	1922	/@} end of CMSIS_core_DebugFunctions /
AnnaBridge	167:84c0a372a020	1923
AnnaBridge	167:84c0a372a020	1924
AnnaBridge	167:84c0a372a020	1925
AnnaBridge	167:84c0a372a020	1926
AnnaBridge	167:84c0a372a020	1927	#ifdef __cplusplus
AnnaBridge	167:84c0a372a020	1928	}
AnnaBridge	167:84c0a372a020	1929	#endif
AnnaBridge	167:84c0a372a020	1930
AnnaBridge	167:84c0a372a020	1931	#endif /* __CORE_CM3_H_DEPENDANT */
AnnaBridge	167:84c0a372a020	1932
AnnaBridge	167:84c0a372a020	1933	#endif /* __CMSIS_GENERIC */