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TARGET_MTB_ADV_WISE_1530/cmsis_armclang.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:: Anna Bridge
Date:: Fri Jun 22 15:38:59 2018 +0100
Revision:: 169:a7c7b631e539
Parent:: 167:84c0a372a020

mbed library. Release version 162

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	167:84c0a372a020	1	/************************************************************************//
AnnaBridge	167:84c0a372a020	2	* @file cmsis_armclang.h
Anna Bridge	169:a7c7b631e539	3	* @brief CMSIS compiler armclang (Arm Compiler 6) header file
Anna Bridge	169:a7c7b631e539	4	* @version V5.0.4
Anna Bridge	169:a7c7b631e539	5	* @date 10. January 2018
AnnaBridge	167:84c0a372a020	6	******************************************************************************/
AnnaBridge	167:84c0a372a020	7	/*
Anna Bridge	169:a7c7b631e539	8	* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
AnnaBridge	167:84c0a372a020	9	*
AnnaBridge	167:84c0a372a020	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	167:84c0a372a020	11	*
AnnaBridge	167:84c0a372a020	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	167:84c0a372a020	13	* not use this file except in compliance with the License.
AnnaBridge	167:84c0a372a020	14	* You may obtain a copy of the License at
AnnaBridge	167:84c0a372a020	15	*
AnnaBridge	167:84c0a372a020	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	167:84c0a372a020	17	*
AnnaBridge	167:84c0a372a020	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	167:84c0a372a020	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	167:84c0a372a020	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	167:84c0a372a020	21	* See the License for the specific language governing permissions and
AnnaBridge	167:84c0a372a020	22	* limitations under the License.
AnnaBridge	167:84c0a372a020	23	*/
AnnaBridge	167:84c0a372a020	24
AnnaBridge	167:84c0a372a020	25	/lint -esym(9058, IRQn)/ /* disable MISRA 2012 Rule 2.4 for IRQn */
AnnaBridge	167:84c0a372a020	26
AnnaBridge	167:84c0a372a020	27	#ifndef __CMSIS_ARMCLANG_H
AnnaBridge	167:84c0a372a020	28	#define __CMSIS_ARMCLANG_H
AnnaBridge	167:84c0a372a020	29
Anna Bridge	169:a7c7b631e539	30	#pragma clang system_header /* treat file as system include file */
Anna Bridge	169:a7c7b631e539	31
AnnaBridge	167:84c0a372a020	32	#ifndef __ARM_COMPAT_H
Anna Bridge	169:a7c7b631e539	33	#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
AnnaBridge	167:84c0a372a020	34	#endif
AnnaBridge	167:84c0a372a020	35
AnnaBridge	167:84c0a372a020	36	/* CMSIS compiler specific defines */
AnnaBridge	167:84c0a372a020	37	#ifndef __ASM
AnnaBridge	167:84c0a372a020	38	#define __ASM __asm
AnnaBridge	167:84c0a372a020	39	#endif
AnnaBridge	167:84c0a372a020	40	#ifndef __INLINE
AnnaBridge	167:84c0a372a020	41	#define __INLINE __inline
AnnaBridge	167:84c0a372a020	42	#endif
AnnaBridge	167:84c0a372a020	43	#ifndef __STATIC_INLINE
AnnaBridge	167:84c0a372a020	44	#define __STATIC_INLINE static __inline
AnnaBridge	167:84c0a372a020	45	#endif
Anna Bridge	169:a7c7b631e539	46	#ifndef __STATIC_FORCEINLINE
Anna Bridge	169:a7c7b631e539	47	#define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
Anna Bridge	169:a7c7b631e539	48	#endif
AnnaBridge	167:84c0a372a020	49	#ifndef __NO_RETURN
Anna Bridge	169:a7c7b631e539	50	#define __NO_RETURN __attribute__((__noreturn__))
AnnaBridge	167:84c0a372a020	51	#endif
AnnaBridge	167:84c0a372a020	52	#ifndef __USED
AnnaBridge	167:84c0a372a020	53	#define __USED __attribute__((used))
AnnaBridge	167:84c0a372a020	54	#endif
AnnaBridge	167:84c0a372a020	55	#ifndef __WEAK
AnnaBridge	167:84c0a372a020	56	#define __WEAK __attribute__((weak))
AnnaBridge	167:84c0a372a020	57	#endif
AnnaBridge	167:84c0a372a020	58	#ifndef __PACKED
AnnaBridge	167:84c0a372a020	59	#define __PACKED __attribute__((packed, aligned(1)))
AnnaBridge	167:84c0a372a020	60	#endif
AnnaBridge	167:84c0a372a020	61	#ifndef __PACKED_STRUCT
AnnaBridge	167:84c0a372a020	62	#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
AnnaBridge	167:84c0a372a020	63	#endif
AnnaBridge	167:84c0a372a020	64	#ifndef __PACKED_UNION
AnnaBridge	167:84c0a372a020	65	#define __PACKED_UNION union __attribute__((packed, aligned(1)))
AnnaBridge	167:84c0a372a020	66	#endif
AnnaBridge	167:84c0a372a020	67	#ifndef __UNALIGNED_UINT32 /* deprecated */
AnnaBridge	167:84c0a372a020	68	#pragma clang diagnostic push
AnnaBridge	167:84c0a372a020	69	#pragma clang diagnostic ignored "-Wpacked"
AnnaBridge	167:84c0a372a020	70	/lint -esym(9058, T_UINT32)/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
AnnaBridge	167:84c0a372a020	71	struct __attribute__((packed)) T_UINT32 { uint32_t v; };
AnnaBridge	167:84c0a372a020	72	#pragma clang diagnostic pop
AnnaBridge	167:84c0a372a020	73	#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
AnnaBridge	167:84c0a372a020	74	#endif
AnnaBridge	167:84c0a372a020	75	#ifndef __UNALIGNED_UINT16_WRITE
AnnaBridge	167:84c0a372a020	76	#pragma clang diagnostic push
AnnaBridge	167:84c0a372a020	77	#pragma clang diagnostic ignored "-Wpacked"
AnnaBridge	167:84c0a372a020	78	/lint -esym(9058, T_UINT16_WRITE)/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
AnnaBridge	167:84c0a372a020	79	__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
AnnaBridge	167:84c0a372a020	80	#pragma clang diagnostic pop
AnnaBridge	167:84c0a372a020	81	#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE )(void )(addr))->v) = (val))
AnnaBridge	167:84c0a372a020	82	#endif
AnnaBridge	167:84c0a372a020	83	#ifndef __UNALIGNED_UINT16_READ
AnnaBridge	167:84c0a372a020	84	#pragma clang diagnostic push
AnnaBridge	167:84c0a372a020	85	#pragma clang diagnostic ignored "-Wpacked"
AnnaBridge	167:84c0a372a020	86	/lint -esym(9058, T_UINT16_READ)/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
AnnaBridge	167:84c0a372a020	87	__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
AnnaBridge	167:84c0a372a020	88	#pragma clang diagnostic pop
AnnaBridge	167:84c0a372a020	89	#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ )(const void )(addr))->v)
AnnaBridge	167:84c0a372a020	90	#endif
AnnaBridge	167:84c0a372a020	91	#ifndef __UNALIGNED_UINT32_WRITE
AnnaBridge	167:84c0a372a020	92	#pragma clang diagnostic push
AnnaBridge	167:84c0a372a020	93	#pragma clang diagnostic ignored "-Wpacked"
AnnaBridge	167:84c0a372a020	94	/lint -esym(9058, T_UINT32_WRITE)/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
AnnaBridge	167:84c0a372a020	95	__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
AnnaBridge	167:84c0a372a020	96	#pragma clang diagnostic pop
AnnaBridge	167:84c0a372a020	97	#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE )(void )(addr))->v) = (val))
AnnaBridge	167:84c0a372a020	98	#endif
AnnaBridge	167:84c0a372a020	99	#ifndef __UNALIGNED_UINT32_READ
AnnaBridge	167:84c0a372a020	100	#pragma clang diagnostic push
AnnaBridge	167:84c0a372a020	101	#pragma clang diagnostic ignored "-Wpacked"
AnnaBridge	167:84c0a372a020	102	/lint -esym(9058, T_UINT32_READ)/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
AnnaBridge	167:84c0a372a020	103	__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
AnnaBridge	167:84c0a372a020	104	#pragma clang diagnostic pop
AnnaBridge	167:84c0a372a020	105	#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ )(const void )(addr))->v)
AnnaBridge	167:84c0a372a020	106	#endif
AnnaBridge	167:84c0a372a020	107	#ifndef __ALIGNED
AnnaBridge	167:84c0a372a020	108	#define __ALIGNED(x) __attribute__((aligned(x)))
AnnaBridge	167:84c0a372a020	109	#endif
AnnaBridge	167:84c0a372a020	110	#ifndef __RESTRICT
AnnaBridge	167:84c0a372a020	111	#define __RESTRICT __restrict
AnnaBridge	167:84c0a372a020	112	#endif
AnnaBridge	167:84c0a372a020	113
AnnaBridge	167:84c0a372a020	114
AnnaBridge	167:84c0a372a020	115	/* ########################### Core Function Access ########################### */
AnnaBridge	167:84c0a372a020	116	/** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:84c0a372a020	117	\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
AnnaBridge	167:84c0a372a020	118	@{
AnnaBridge	167:84c0a372a020	119	*/
AnnaBridge	167:84c0a372a020	120
AnnaBridge	167:84c0a372a020	121	/**
AnnaBridge	167:84c0a372a020	122	\brief Enable IRQ Interrupts
AnnaBridge	167:84c0a372a020	123	\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
AnnaBridge	167:84c0a372a020	124	Can only be executed in Privileged modes.
AnnaBridge	167:84c0a372a020	125	*/
AnnaBridge	167:84c0a372a020	126	/* intrinsic void __enable_irq(); see arm_compat.h */
AnnaBridge	167:84c0a372a020	127
AnnaBridge	167:84c0a372a020	128
AnnaBridge	167:84c0a372a020	129	/**
AnnaBridge	167:84c0a372a020	130	\brief Disable IRQ Interrupts
AnnaBridge	167:84c0a372a020	131	\details Disables IRQ interrupts by setting the I-bit in the CPSR.
AnnaBridge	167:84c0a372a020	132	Can only be executed in Privileged modes.
AnnaBridge	167:84c0a372a020	133	*/
AnnaBridge	167:84c0a372a020	134	/* intrinsic void __disable_irq(); see arm_compat.h */
AnnaBridge	167:84c0a372a020	135
AnnaBridge	167:84c0a372a020	136
AnnaBridge	167:84c0a372a020	137	/**
AnnaBridge	167:84c0a372a020	138	\brief Get Control Register
AnnaBridge	167:84c0a372a020	139	\details Returns the content of the Control Register.
AnnaBridge	167:84c0a372a020	140	\return Control Register value
AnnaBridge	167:84c0a372a020	141	*/
Anna Bridge	169:a7c7b631e539	142	__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
AnnaBridge	167:84c0a372a020	143	{
AnnaBridge	167:84c0a372a020	144	uint32_t result;
AnnaBridge	167:84c0a372a020	145
AnnaBridge	167:84c0a372a020	146	__ASM volatile ("MRS %0, control" : "=r" (result) );
AnnaBridge	167:84c0a372a020	147	return(result);
AnnaBridge	167:84c0a372a020	148	}
AnnaBridge	167:84c0a372a020	149
AnnaBridge	167:84c0a372a020	150
AnnaBridge	167:84c0a372a020	151	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	152	/**
AnnaBridge	167:84c0a372a020	153	\brief Get Control Register (non-secure)
AnnaBridge	167:84c0a372a020	154	\details Returns the content of the non-secure Control Register when in secure mode.
AnnaBridge	167:84c0a372a020	155	\return non-secure Control Register value
AnnaBridge	167:84c0a372a020	156	*/
Anna Bridge	169:a7c7b631e539	157	__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
AnnaBridge	167:84c0a372a020	158	{
AnnaBridge	167:84c0a372a020	159	uint32_t result;
AnnaBridge	167:84c0a372a020	160
AnnaBridge	167:84c0a372a020	161	__ASM volatile ("MRS %0, control_ns" : "=r" (result) );
AnnaBridge	167:84c0a372a020	162	return(result);
AnnaBridge	167:84c0a372a020	163	}
AnnaBridge	167:84c0a372a020	164	#endif
AnnaBridge	167:84c0a372a020	165
AnnaBridge	167:84c0a372a020	166
AnnaBridge	167:84c0a372a020	167	/**
AnnaBridge	167:84c0a372a020	168	\brief Set Control Register
AnnaBridge	167:84c0a372a020	169	\details Writes the given value to the Control Register.
AnnaBridge	167:84c0a372a020	170	\param [in] control Control Register value to set
AnnaBridge	167:84c0a372a020	171	*/
Anna Bridge	169:a7c7b631e539	172	__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
AnnaBridge	167:84c0a372a020	173	{
AnnaBridge	167:84c0a372a020	174	__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
AnnaBridge	167:84c0a372a020	175	}
AnnaBridge	167:84c0a372a020	176
AnnaBridge	167:84c0a372a020	177
AnnaBridge	167:84c0a372a020	178	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	179	/**
AnnaBridge	167:84c0a372a020	180	\brief Set Control Register (non-secure)
AnnaBridge	167:84c0a372a020	181	\details Writes the given value to the non-secure Control Register when in secure state.
AnnaBridge	167:84c0a372a020	182	\param [in] control Control Register value to set
AnnaBridge	167:84c0a372a020	183	*/
Anna Bridge	169:a7c7b631e539	184	__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
AnnaBridge	167:84c0a372a020	185	{
AnnaBridge	167:84c0a372a020	186	__ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
AnnaBridge	167:84c0a372a020	187	}
AnnaBridge	167:84c0a372a020	188	#endif
AnnaBridge	167:84c0a372a020	189
AnnaBridge	167:84c0a372a020	190
AnnaBridge	167:84c0a372a020	191	/**
AnnaBridge	167:84c0a372a020	192	\brief Get IPSR Register
AnnaBridge	167:84c0a372a020	193	\details Returns the content of the IPSR Register.
AnnaBridge	167:84c0a372a020	194	\return IPSR Register value
AnnaBridge	167:84c0a372a020	195	*/
Anna Bridge	169:a7c7b631e539	196	__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
AnnaBridge	167:84c0a372a020	197	{
AnnaBridge	167:84c0a372a020	198	uint32_t result;
AnnaBridge	167:84c0a372a020	199
AnnaBridge	167:84c0a372a020	200	__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
AnnaBridge	167:84c0a372a020	201	return(result);
AnnaBridge	167:84c0a372a020	202	}
AnnaBridge	167:84c0a372a020	203
AnnaBridge	167:84c0a372a020	204
AnnaBridge	167:84c0a372a020	205	/**
AnnaBridge	167:84c0a372a020	206	\brief Get APSR Register
AnnaBridge	167:84c0a372a020	207	\details Returns the content of the APSR Register.
AnnaBridge	167:84c0a372a020	208	\return APSR Register value
AnnaBridge	167:84c0a372a020	209	*/
Anna Bridge	169:a7c7b631e539	210	__STATIC_FORCEINLINE uint32_t __get_APSR(void)
AnnaBridge	167:84c0a372a020	211	{
AnnaBridge	167:84c0a372a020	212	uint32_t result;
AnnaBridge	167:84c0a372a020	213
AnnaBridge	167:84c0a372a020	214	__ASM volatile ("MRS %0, apsr" : "=r" (result) );
AnnaBridge	167:84c0a372a020	215	return(result);
AnnaBridge	167:84c0a372a020	216	}
AnnaBridge	167:84c0a372a020	217
AnnaBridge	167:84c0a372a020	218
AnnaBridge	167:84c0a372a020	219	/**
AnnaBridge	167:84c0a372a020	220	\brief Get xPSR Register
AnnaBridge	167:84c0a372a020	221	\details Returns the content of the xPSR Register.
AnnaBridge	167:84c0a372a020	222	\return xPSR Register value
AnnaBridge	167:84c0a372a020	223	*/
Anna Bridge	169:a7c7b631e539	224	__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
AnnaBridge	167:84c0a372a020	225	{
AnnaBridge	167:84c0a372a020	226	uint32_t result;
AnnaBridge	167:84c0a372a020	227
AnnaBridge	167:84c0a372a020	228	__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
AnnaBridge	167:84c0a372a020	229	return(result);
AnnaBridge	167:84c0a372a020	230	}
AnnaBridge	167:84c0a372a020	231
AnnaBridge	167:84c0a372a020	232
AnnaBridge	167:84c0a372a020	233	/**
AnnaBridge	167:84c0a372a020	234	\brief Get Process Stack Pointer
AnnaBridge	167:84c0a372a020	235	\details Returns the current value of the Process Stack Pointer (PSP).
AnnaBridge	167:84c0a372a020	236	\return PSP Register value
AnnaBridge	167:84c0a372a020	237	*/
Anna Bridge	169:a7c7b631e539	238	__STATIC_FORCEINLINE uint32_t __get_PSP(void)
AnnaBridge	167:84c0a372a020	239	{
AnnaBridge	167:84c0a372a020	240	register uint32_t result;
AnnaBridge	167:84c0a372a020	241
AnnaBridge	167:84c0a372a020	242	__ASM volatile ("MRS %0, psp" : "=r" (result) );
AnnaBridge	167:84c0a372a020	243	return(result);
AnnaBridge	167:84c0a372a020	244	}
AnnaBridge	167:84c0a372a020	245
AnnaBridge	167:84c0a372a020	246
AnnaBridge	167:84c0a372a020	247	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	248	/**
AnnaBridge	167:84c0a372a020	249	\brief Get Process Stack Pointer (non-secure)
AnnaBridge	167:84c0a372a020	250	\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge	167:84c0a372a020	251	\return PSP Register value
AnnaBridge	167:84c0a372a020	252	*/
Anna Bridge	169:a7c7b631e539	253	__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
AnnaBridge	167:84c0a372a020	254	{
AnnaBridge	167:84c0a372a020	255	register uint32_t result;
AnnaBridge	167:84c0a372a020	256
AnnaBridge	167:84c0a372a020	257	__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
AnnaBridge	167:84c0a372a020	258	return(result);
AnnaBridge	167:84c0a372a020	259	}
AnnaBridge	167:84c0a372a020	260	#endif
AnnaBridge	167:84c0a372a020	261
AnnaBridge	167:84c0a372a020	262
AnnaBridge	167:84c0a372a020	263	/**
AnnaBridge	167:84c0a372a020	264	\brief Set Process Stack Pointer
AnnaBridge	167:84c0a372a020	265	\details Assigns the given value to the Process Stack Pointer (PSP).
AnnaBridge	167:84c0a372a020	266	\param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge	167:84c0a372a020	267	*/
Anna Bridge	169:a7c7b631e539	268	__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
AnnaBridge	167:84c0a372a020	269	{
AnnaBridge	167:84c0a372a020	270	__ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
AnnaBridge	167:84c0a372a020	271	}
AnnaBridge	167:84c0a372a020	272
AnnaBridge	167:84c0a372a020	273
AnnaBridge	167:84c0a372a020	274	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	275	/**
AnnaBridge	167:84c0a372a020	276	\brief Set Process Stack Pointer (non-secure)
AnnaBridge	167:84c0a372a020	277	\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge	167:84c0a372a020	278	\param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge	167:84c0a372a020	279	*/
Anna Bridge	169:a7c7b631e539	280	__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
AnnaBridge	167:84c0a372a020	281	{
AnnaBridge	167:84c0a372a020	282	__ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
AnnaBridge	167:84c0a372a020	283	}
AnnaBridge	167:84c0a372a020	284	#endif
AnnaBridge	167:84c0a372a020	285
AnnaBridge	167:84c0a372a020	286
AnnaBridge	167:84c0a372a020	287	/**
AnnaBridge	167:84c0a372a020	288	\brief Get Main Stack Pointer
AnnaBridge	167:84c0a372a020	289	\details Returns the current value of the Main Stack Pointer (MSP).
AnnaBridge	167:84c0a372a020	290	\return MSP Register value
AnnaBridge	167:84c0a372a020	291	*/
Anna Bridge	169:a7c7b631e539	292	__STATIC_FORCEINLINE uint32_t __get_MSP(void)
AnnaBridge	167:84c0a372a020	293	{
AnnaBridge	167:84c0a372a020	294	register uint32_t result;
AnnaBridge	167:84c0a372a020	295
AnnaBridge	167:84c0a372a020	296	__ASM volatile ("MRS %0, msp" : "=r" (result) );
AnnaBridge	167:84c0a372a020	297	return(result);
AnnaBridge	167:84c0a372a020	298	}
AnnaBridge	167:84c0a372a020	299
AnnaBridge	167:84c0a372a020	300
AnnaBridge	167:84c0a372a020	301	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	302	/**
AnnaBridge	167:84c0a372a020	303	\brief Get Main Stack Pointer (non-secure)
AnnaBridge	167:84c0a372a020	304	\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge	167:84c0a372a020	305	\return MSP Register value
AnnaBridge	167:84c0a372a020	306	*/
Anna Bridge	169:a7c7b631e539	307	__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
AnnaBridge	167:84c0a372a020	308	{
AnnaBridge	167:84c0a372a020	309	register uint32_t result;
AnnaBridge	167:84c0a372a020	310
AnnaBridge	167:84c0a372a020	311	__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
AnnaBridge	167:84c0a372a020	312	return(result);
AnnaBridge	167:84c0a372a020	313	}
AnnaBridge	167:84c0a372a020	314	#endif
AnnaBridge	167:84c0a372a020	315
AnnaBridge	167:84c0a372a020	316
AnnaBridge	167:84c0a372a020	317	/**
AnnaBridge	167:84c0a372a020	318	\brief Set Main Stack Pointer
AnnaBridge	167:84c0a372a020	319	\details Assigns the given value to the Main Stack Pointer (MSP).
AnnaBridge	167:84c0a372a020	320	\param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge	167:84c0a372a020	321	*/
Anna Bridge	169:a7c7b631e539	322	__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
AnnaBridge	167:84c0a372a020	323	{
AnnaBridge	167:84c0a372a020	324	__ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
AnnaBridge	167:84c0a372a020	325	}
AnnaBridge	167:84c0a372a020	326
AnnaBridge	167:84c0a372a020	327
AnnaBridge	167:84c0a372a020	328	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	329	/**
AnnaBridge	167:84c0a372a020	330	\brief Set Main Stack Pointer (non-secure)
AnnaBridge	167:84c0a372a020	331	\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge	167:84c0a372a020	332	\param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge	167:84c0a372a020	333	*/
Anna Bridge	169:a7c7b631e539	334	__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
AnnaBridge	167:84c0a372a020	335	{
AnnaBridge	167:84c0a372a020	336	__ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
AnnaBridge	167:84c0a372a020	337	}
AnnaBridge	167:84c0a372a020	338	#endif
AnnaBridge	167:84c0a372a020	339
AnnaBridge	167:84c0a372a020	340
AnnaBridge	167:84c0a372a020	341	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	342	/**
AnnaBridge	167:84c0a372a020	343	\brief Get Stack Pointer (non-secure)
AnnaBridge	167:84c0a372a020	344	\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge	167:84c0a372a020	345	\return SP Register value
AnnaBridge	167:84c0a372a020	346	*/
Anna Bridge	169:a7c7b631e539	347	__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
AnnaBridge	167:84c0a372a020	348	{
AnnaBridge	167:84c0a372a020	349	register uint32_t result;
AnnaBridge	167:84c0a372a020	350
AnnaBridge	167:84c0a372a020	351	__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
AnnaBridge	167:84c0a372a020	352	return(result);
AnnaBridge	167:84c0a372a020	353	}
AnnaBridge	167:84c0a372a020	354
AnnaBridge	167:84c0a372a020	355
AnnaBridge	167:84c0a372a020	356	/**
AnnaBridge	167:84c0a372a020	357	\brief Set Stack Pointer (non-secure)
AnnaBridge	167:84c0a372a020	358	\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge	167:84c0a372a020	359	\param [in] topOfStack Stack Pointer value to set
AnnaBridge	167:84c0a372a020	360	*/
Anna Bridge	169:a7c7b631e539	361	__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
AnnaBridge	167:84c0a372a020	362	{
AnnaBridge	167:84c0a372a020	363	__ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
AnnaBridge	167:84c0a372a020	364	}
AnnaBridge	167:84c0a372a020	365	#endif
AnnaBridge	167:84c0a372a020	366
AnnaBridge	167:84c0a372a020	367
AnnaBridge	167:84c0a372a020	368	/**
AnnaBridge	167:84c0a372a020	369	\brief Get Priority Mask
AnnaBridge	167:84c0a372a020	370	\details Returns the current state of the priority mask bit from the Priority Mask Register.
AnnaBridge	167:84c0a372a020	371	\return Priority Mask value
AnnaBridge	167:84c0a372a020	372	*/
Anna Bridge	169:a7c7b631e539	373	__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
AnnaBridge	167:84c0a372a020	374	{
AnnaBridge	167:84c0a372a020	375	uint32_t result;
AnnaBridge	167:84c0a372a020	376
AnnaBridge	167:84c0a372a020	377	__ASM volatile ("MRS %0, primask" : "=r" (result) );
AnnaBridge	167:84c0a372a020	378	return(result);
AnnaBridge	167:84c0a372a020	379	}
AnnaBridge	167:84c0a372a020	380
AnnaBridge	167:84c0a372a020	381
AnnaBridge	167:84c0a372a020	382	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	383	/**
AnnaBridge	167:84c0a372a020	384	\brief Get Priority Mask (non-secure)
AnnaBridge	167:84c0a372a020	385	\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
AnnaBridge	167:84c0a372a020	386	\return Priority Mask value
AnnaBridge	167:84c0a372a020	387	*/
Anna Bridge	169:a7c7b631e539	388	__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
AnnaBridge	167:84c0a372a020	389	{
AnnaBridge	167:84c0a372a020	390	uint32_t result;
AnnaBridge	167:84c0a372a020	391
AnnaBridge	167:84c0a372a020	392	__ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
AnnaBridge	167:84c0a372a020	393	return(result);
AnnaBridge	167:84c0a372a020	394	}
AnnaBridge	167:84c0a372a020	395	#endif
AnnaBridge	167:84c0a372a020	396
AnnaBridge	167:84c0a372a020	397
AnnaBridge	167:84c0a372a020	398	/**
AnnaBridge	167:84c0a372a020	399	\brief Set Priority Mask
AnnaBridge	167:84c0a372a020	400	\details Assigns the given value to the Priority Mask Register.
AnnaBridge	167:84c0a372a020	401	\param [in] priMask Priority Mask
AnnaBridge	167:84c0a372a020	402	*/
Anna Bridge	169:a7c7b631e539	403	__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
AnnaBridge	167:84c0a372a020	404	{
AnnaBridge	167:84c0a372a020	405	__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
AnnaBridge	167:84c0a372a020	406	}
AnnaBridge	167:84c0a372a020	407
AnnaBridge	167:84c0a372a020	408
AnnaBridge	167:84c0a372a020	409	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	410	/**
AnnaBridge	167:84c0a372a020	411	\brief Set Priority Mask (non-secure)
AnnaBridge	167:84c0a372a020	412	\details Assigns the given value to the non-secure Priority Mask Register when in secure state.
AnnaBridge	167:84c0a372a020	413	\param [in] priMask Priority Mask
AnnaBridge	167:84c0a372a020	414	*/
Anna Bridge	169:a7c7b631e539	415	__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
AnnaBridge	167:84c0a372a020	416	{
AnnaBridge	167:84c0a372a020	417	__ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
AnnaBridge	167:84c0a372a020	418	}
AnnaBridge	167:84c0a372a020	419	#endif
AnnaBridge	167:84c0a372a020	420
AnnaBridge	167:84c0a372a020	421
AnnaBridge	167:84c0a372a020	422	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	423	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	424	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	167:84c0a372a020	425	/**
AnnaBridge	167:84c0a372a020	426	\brief Enable FIQ
AnnaBridge	167:84c0a372a020	427	\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
AnnaBridge	167:84c0a372a020	428	Can only be executed in Privileged modes.
AnnaBridge	167:84c0a372a020	429	*/
AnnaBridge	167:84c0a372a020	430	#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
AnnaBridge	167:84c0a372a020	431
AnnaBridge	167:84c0a372a020	432
AnnaBridge	167:84c0a372a020	433	/**
AnnaBridge	167:84c0a372a020	434	\brief Disable FIQ
AnnaBridge	167:84c0a372a020	435	\details Disables FIQ interrupts by setting the F-bit in the CPSR.
AnnaBridge	167:84c0a372a020	436	Can only be executed in Privileged modes.
AnnaBridge	167:84c0a372a020	437	*/
AnnaBridge	167:84c0a372a020	438	#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
AnnaBridge	167:84c0a372a020	439
AnnaBridge	167:84c0a372a020	440
AnnaBridge	167:84c0a372a020	441	/**
AnnaBridge	167:84c0a372a020	442	\brief Get Base Priority
AnnaBridge	167:84c0a372a020	443	\details Returns the current value of the Base Priority register.
AnnaBridge	167:84c0a372a020	444	\return Base Priority register value
AnnaBridge	167:84c0a372a020	445	*/
Anna Bridge	169:a7c7b631e539	446	__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
AnnaBridge	167:84c0a372a020	447	{
AnnaBridge	167:84c0a372a020	448	uint32_t result;
AnnaBridge	167:84c0a372a020	449
AnnaBridge	167:84c0a372a020	450	__ASM volatile ("MRS %0, basepri" : "=r" (result) );
AnnaBridge	167:84c0a372a020	451	return(result);
AnnaBridge	167:84c0a372a020	452	}
AnnaBridge	167:84c0a372a020	453
AnnaBridge	167:84c0a372a020	454
AnnaBridge	167:84c0a372a020	455	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	456	/**
AnnaBridge	167:84c0a372a020	457	\brief Get Base Priority (non-secure)
AnnaBridge	167:84c0a372a020	458	\details Returns the current value of the non-secure Base Priority register when in secure state.
AnnaBridge	167:84c0a372a020	459	\return Base Priority register value
AnnaBridge	167:84c0a372a020	460	*/
Anna Bridge	169:a7c7b631e539	461	__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
AnnaBridge	167:84c0a372a020	462	{
AnnaBridge	167:84c0a372a020	463	uint32_t result;
AnnaBridge	167:84c0a372a020	464
AnnaBridge	167:84c0a372a020	465	__ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
AnnaBridge	167:84c0a372a020	466	return(result);
AnnaBridge	167:84c0a372a020	467	}
AnnaBridge	167:84c0a372a020	468	#endif
AnnaBridge	167:84c0a372a020	469
AnnaBridge	167:84c0a372a020	470
AnnaBridge	167:84c0a372a020	471	/**
AnnaBridge	167:84c0a372a020	472	\brief Set Base Priority
AnnaBridge	167:84c0a372a020	473	\details Assigns the given value to the Base Priority register.
AnnaBridge	167:84c0a372a020	474	\param [in] basePri Base Priority value to set
AnnaBridge	167:84c0a372a020	475	*/
Anna Bridge	169:a7c7b631e539	476	__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
AnnaBridge	167:84c0a372a020	477	{
AnnaBridge	167:84c0a372a020	478	__ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
AnnaBridge	167:84c0a372a020	479	}
AnnaBridge	167:84c0a372a020	480
AnnaBridge	167:84c0a372a020	481
AnnaBridge	167:84c0a372a020	482	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	483	/**
AnnaBridge	167:84c0a372a020	484	\brief Set Base Priority (non-secure)
AnnaBridge	167:84c0a372a020	485	\details Assigns the given value to the non-secure Base Priority register when in secure state.
AnnaBridge	167:84c0a372a020	486	\param [in] basePri Base Priority value to set
AnnaBridge	167:84c0a372a020	487	*/
Anna Bridge	169:a7c7b631e539	488	__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
AnnaBridge	167:84c0a372a020	489	{
AnnaBridge	167:84c0a372a020	490	__ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
AnnaBridge	167:84c0a372a020	491	}
AnnaBridge	167:84c0a372a020	492	#endif
AnnaBridge	167:84c0a372a020	493
AnnaBridge	167:84c0a372a020	494
AnnaBridge	167:84c0a372a020	495	/**
AnnaBridge	167:84c0a372a020	496	\brief Set Base Priority with condition
AnnaBridge	167:84c0a372a020	497	\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
AnnaBridge	167:84c0a372a020	498	or the new value increases the BASEPRI priority level.
AnnaBridge	167:84c0a372a020	499	\param [in] basePri Base Priority value to set
AnnaBridge	167:84c0a372a020	500	*/
Anna Bridge	169:a7c7b631e539	501	__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
AnnaBridge	167:84c0a372a020	502	{
AnnaBridge	167:84c0a372a020	503	__ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
AnnaBridge	167:84c0a372a020	504	}
AnnaBridge	167:84c0a372a020	505
AnnaBridge	167:84c0a372a020	506
AnnaBridge	167:84c0a372a020	507	/**
AnnaBridge	167:84c0a372a020	508	\brief Get Fault Mask
AnnaBridge	167:84c0a372a020	509	\details Returns the current value of the Fault Mask register.
AnnaBridge	167:84c0a372a020	510	\return Fault Mask register value
AnnaBridge	167:84c0a372a020	511	*/
Anna Bridge	169:a7c7b631e539	512	__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
AnnaBridge	167:84c0a372a020	513	{
AnnaBridge	167:84c0a372a020	514	uint32_t result;
AnnaBridge	167:84c0a372a020	515
AnnaBridge	167:84c0a372a020	516	__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
AnnaBridge	167:84c0a372a020	517	return(result);
AnnaBridge	167:84c0a372a020	518	}
AnnaBridge	167:84c0a372a020	519
AnnaBridge	167:84c0a372a020	520
AnnaBridge	167:84c0a372a020	521	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	522	/**
AnnaBridge	167:84c0a372a020	523	\brief Get Fault Mask (non-secure)
AnnaBridge	167:84c0a372a020	524	\details Returns the current value of the non-secure Fault Mask register when in secure state.
AnnaBridge	167:84c0a372a020	525	\return Fault Mask register value
AnnaBridge	167:84c0a372a020	526	*/
Anna Bridge	169:a7c7b631e539	527	__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
AnnaBridge	167:84c0a372a020	528	{
AnnaBridge	167:84c0a372a020	529	uint32_t result;
AnnaBridge	167:84c0a372a020	530
AnnaBridge	167:84c0a372a020	531	__ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
AnnaBridge	167:84c0a372a020	532	return(result);
AnnaBridge	167:84c0a372a020	533	}
AnnaBridge	167:84c0a372a020	534	#endif
AnnaBridge	167:84c0a372a020	535
AnnaBridge	167:84c0a372a020	536
AnnaBridge	167:84c0a372a020	537	/**
AnnaBridge	167:84c0a372a020	538	\brief Set Fault Mask
AnnaBridge	167:84c0a372a020	539	\details Assigns the given value to the Fault Mask register.
AnnaBridge	167:84c0a372a020	540	\param [in] faultMask Fault Mask value to set
AnnaBridge	167:84c0a372a020	541	*/
Anna Bridge	169:a7c7b631e539	542	__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
AnnaBridge	167:84c0a372a020	543	{
AnnaBridge	167:84c0a372a020	544	__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
AnnaBridge	167:84c0a372a020	545	}
AnnaBridge	167:84c0a372a020	546
AnnaBridge	167:84c0a372a020	547
AnnaBridge	167:84c0a372a020	548	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	549	/**
AnnaBridge	167:84c0a372a020	550	\brief Set Fault Mask (non-secure)
AnnaBridge	167:84c0a372a020	551	\details Assigns the given value to the non-secure Fault Mask register when in secure state.
AnnaBridge	167:84c0a372a020	552	\param [in] faultMask Fault Mask value to set
AnnaBridge	167:84c0a372a020	553	*/
Anna Bridge	169:a7c7b631e539	554	__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
AnnaBridge	167:84c0a372a020	555	{
AnnaBridge	167:84c0a372a020	556	__ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
AnnaBridge	167:84c0a372a020	557	}
AnnaBridge	167:84c0a372a020	558	#endif
AnnaBridge	167:84c0a372a020	559
AnnaBridge	167:84c0a372a020	560	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	561	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	562	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge	167:84c0a372a020	563
AnnaBridge	167:84c0a372a020	564
AnnaBridge	167:84c0a372a020	565	#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	566	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge	167:84c0a372a020	567
AnnaBridge	167:84c0a372a020	568	/**
AnnaBridge	167:84c0a372a020	569	\brief Get Process Stack Pointer Limit
Anna Bridge	169:a7c7b631e539	570	Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Anna Bridge	169:a7c7b631e539	571	Stack Pointer Limit register hence zero is returned always in non-secure
Anna Bridge	169:a7c7b631e539	572	mode.
Anna Bridge	169:a7c7b631e539	573
AnnaBridge	167:84c0a372a020	574	\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
AnnaBridge	167:84c0a372a020	575	\return PSPLIM Register value
AnnaBridge	167:84c0a372a020	576	*/
Anna Bridge	169:a7c7b631e539	577	__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
AnnaBridge	167:84c0a372a020	578	{
Anna Bridge	169:a7c7b631e539	579	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
Anna Bridge	169:a7c7b631e539	580	(!defined (__ARM_FEATURE_CMSE) \|\| (__ARM_FEATURE_CMSE < 3)))
Anna Bridge	169:a7c7b631e539	581	// without main extensions, the non-secure PSPLIM is RAZ/WI
Anna Bridge	169:a7c7b631e539	582	return 0U;
Anna Bridge	169:a7c7b631e539	583	#else
AnnaBridge	167:84c0a372a020	584	register uint32_t result;
AnnaBridge	167:84c0a372a020	585	__ASM volatile ("MRS %0, psplim" : "=r" (result) );
Anna Bridge	169:a7c7b631e539	586	return result;
Anna Bridge	169:a7c7b631e539	587	#endif
AnnaBridge	167:84c0a372a020	588	}
AnnaBridge	167:84c0a372a020	589
Anna Bridge	169:a7c7b631e539	590	#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	591	/**
AnnaBridge	167:84c0a372a020	592	\brief Get Process Stack Pointer Limit (non-secure)
Anna Bridge	169:a7c7b631e539	593	Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Anna Bridge	169:a7c7b631e539	594	Stack Pointer Limit register hence zero is returned always in non-secure
Anna Bridge	169:a7c7b631e539	595	mode.
Anna Bridge	169:a7c7b631e539	596
AnnaBridge	167:84c0a372a020	597	\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge	167:84c0a372a020	598	\return PSPLIM Register value
AnnaBridge	167:84c0a372a020	599	*/
Anna Bridge	169:a7c7b631e539	600	__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
AnnaBridge	167:84c0a372a020	601	{
Anna Bridge	169:a7c7b631e539	602	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
Anna Bridge	169:a7c7b631e539	603	// without main extensions, the non-secure PSPLIM is RAZ/WI
Anna Bridge	169:a7c7b631e539	604	return 0U;
Anna Bridge	169:a7c7b631e539	605	#else
AnnaBridge	167:84c0a372a020	606	register uint32_t result;
AnnaBridge	167:84c0a372a020	607	__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
Anna Bridge	169:a7c7b631e539	608	return result;
Anna Bridge	169:a7c7b631e539	609	#endif
AnnaBridge	167:84c0a372a020	610	}
AnnaBridge	167:84c0a372a020	611	#endif
AnnaBridge	167:84c0a372a020	612
AnnaBridge	167:84c0a372a020	613
AnnaBridge	167:84c0a372a020	614	/**
AnnaBridge	167:84c0a372a020	615	\brief Set Process Stack Pointer Limit
Anna Bridge	169:a7c7b631e539	616	Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Anna Bridge	169:a7c7b631e539	617	Stack Pointer Limit register hence the write is silently ignored in non-secure
Anna Bridge	169:a7c7b631e539	618	mode.
Anna Bridge	169:a7c7b631e539	619
AnnaBridge	167:84c0a372a020	620	\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
AnnaBridge	167:84c0a372a020	621	\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge	167:84c0a372a020	622	*/
Anna Bridge	169:a7c7b631e539	623	__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
AnnaBridge	167:84c0a372a020	624	{
Anna Bridge	169:a7c7b631e539	625	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
Anna Bridge	169:a7c7b631e539	626	(!defined (__ARM_FEATURE_CMSE) \|\| (__ARM_FEATURE_CMSE < 3)))
Anna Bridge	169:a7c7b631e539	627	// without main extensions, the non-secure PSPLIM is RAZ/WI
Anna Bridge	169:a7c7b631e539	628	(void)ProcStackPtrLimit;
Anna Bridge	169:a7c7b631e539	629	#else
AnnaBridge	167:84c0a372a020	630	__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
Anna Bridge	169:a7c7b631e539	631	#endif
AnnaBridge	167:84c0a372a020	632	}
AnnaBridge	167:84c0a372a020	633
AnnaBridge	167:84c0a372a020	634
Anna Bridge	169:a7c7b631e539	635	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	636	/**
AnnaBridge	167:84c0a372a020	637	\brief Set Process Stack Pointer (non-secure)
Anna Bridge	169:a7c7b631e539	638	Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Anna Bridge	169:a7c7b631e539	639	Stack Pointer Limit register hence the write is silently ignored in non-secure
Anna Bridge	169:a7c7b631e539	640	mode.
Anna Bridge	169:a7c7b631e539	641
AnnaBridge	167:84c0a372a020	642	\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge	167:84c0a372a020	643	\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge	167:84c0a372a020	644	*/
Anna Bridge	169:a7c7b631e539	645	__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
AnnaBridge	167:84c0a372a020	646	{
Anna Bridge	169:a7c7b631e539	647	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
Anna Bridge	169:a7c7b631e539	648	// without main extensions, the non-secure PSPLIM is RAZ/WI
Anna Bridge	169:a7c7b631e539	649	(void)ProcStackPtrLimit;
Anna Bridge	169:a7c7b631e539	650	#else
AnnaBridge	167:84c0a372a020	651	__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
Anna Bridge	169:a7c7b631e539	652	#endif
AnnaBridge	167:84c0a372a020	653	}
AnnaBridge	167:84c0a372a020	654	#endif
AnnaBridge	167:84c0a372a020	655
AnnaBridge	167:84c0a372a020	656
AnnaBridge	167:84c0a372a020	657	/**
AnnaBridge	167:84c0a372a020	658	\brief Get Main Stack Pointer Limit
Anna Bridge	169:a7c7b631e539	659	Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Anna Bridge	169:a7c7b631e539	660	Stack Pointer Limit register hence zero is returned always.
Anna Bridge	169:a7c7b631e539	661
AnnaBridge	167:84c0a372a020	662	\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
AnnaBridge	167:84c0a372a020	663	\return MSPLIM Register value
AnnaBridge	167:84c0a372a020	664	*/
Anna Bridge	169:a7c7b631e539	665	__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
AnnaBridge	167:84c0a372a020	666	{
Anna Bridge	169:a7c7b631e539	667	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
Anna Bridge	169:a7c7b631e539	668	(!defined (__ARM_FEATURE_CMSE) \|\| (__ARM_FEATURE_CMSE < 3)))
Anna Bridge	169:a7c7b631e539	669	// without main extensions, the non-secure MSPLIM is RAZ/WI
Anna Bridge	169:a7c7b631e539	670	return 0U;
Anna Bridge	169:a7c7b631e539	671	#else
AnnaBridge	167:84c0a372a020	672	register uint32_t result;
AnnaBridge	167:84c0a372a020	673	__ASM volatile ("MRS %0, msplim" : "=r" (result) );
Anna Bridge	169:a7c7b631e539	674	return result;
Anna Bridge	169:a7c7b631e539	675	#endif
AnnaBridge	167:84c0a372a020	676	}
AnnaBridge	167:84c0a372a020	677
AnnaBridge	167:84c0a372a020	678
Anna Bridge	169:a7c7b631e539	679	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	680	/**
AnnaBridge	167:84c0a372a020	681	\brief Get Main Stack Pointer Limit (non-secure)
Anna Bridge	169:a7c7b631e539	682	Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Anna Bridge	169:a7c7b631e539	683	Stack Pointer Limit register hence zero is returned always.
Anna Bridge	169:a7c7b631e539	684
AnnaBridge	167:84c0a372a020	685	\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
AnnaBridge	167:84c0a372a020	686	\return MSPLIM Register value
AnnaBridge	167:84c0a372a020	687	*/
Anna Bridge	169:a7c7b631e539	688	__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
AnnaBridge	167:84c0a372a020	689	{
Anna Bridge	169:a7c7b631e539	690	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
Anna Bridge	169:a7c7b631e539	691	// without main extensions, the non-secure MSPLIM is RAZ/WI
Anna Bridge	169:a7c7b631e539	692	return 0U;
Anna Bridge	169:a7c7b631e539	693	#else
AnnaBridge	167:84c0a372a020	694	register uint32_t result;
AnnaBridge	167:84c0a372a020	695	__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
Anna Bridge	169:a7c7b631e539	696	return result;
Anna Bridge	169:a7c7b631e539	697	#endif
AnnaBridge	167:84c0a372a020	698	}
AnnaBridge	167:84c0a372a020	699	#endif
AnnaBridge	167:84c0a372a020	700
AnnaBridge	167:84c0a372a020	701
AnnaBridge	167:84c0a372a020	702	/**
AnnaBridge	167:84c0a372a020	703	\brief Set Main Stack Pointer Limit
Anna Bridge	169:a7c7b631e539	704	Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Anna Bridge	169:a7c7b631e539	705	Stack Pointer Limit register hence the write is silently ignored.
Anna Bridge	169:a7c7b631e539	706
AnnaBridge	167:84c0a372a020	707	\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
AnnaBridge	167:84c0a372a020	708	\param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
AnnaBridge	167:84c0a372a020	709	*/
Anna Bridge	169:a7c7b631e539	710	__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
AnnaBridge	167:84c0a372a020	711	{
Anna Bridge	169:a7c7b631e539	712	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
Anna Bridge	169:a7c7b631e539	713	(!defined (__ARM_FEATURE_CMSE) \|\| (__ARM_FEATURE_CMSE < 3)))
Anna Bridge	169:a7c7b631e539	714	// without main extensions, the non-secure MSPLIM is RAZ/WI
Anna Bridge	169:a7c7b631e539	715	(void)MainStackPtrLimit;
Anna Bridge	169:a7c7b631e539	716	#else
AnnaBridge	167:84c0a372a020	717	__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
Anna Bridge	169:a7c7b631e539	718	#endif
AnnaBridge	167:84c0a372a020	719	}
AnnaBridge	167:84c0a372a020	720
AnnaBridge	167:84c0a372a020	721
Anna Bridge	169:a7c7b631e539	722	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	723	/**
AnnaBridge	167:84c0a372a020	724	\brief Set Main Stack Pointer Limit (non-secure)
Anna Bridge	169:a7c7b631e539	725	Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Anna Bridge	169:a7c7b631e539	726	Stack Pointer Limit register hence the write is silently ignored.
Anna Bridge	169:a7c7b631e539	727
AnnaBridge	167:84c0a372a020	728	\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
AnnaBridge	167:84c0a372a020	729	\param [in] MainStackPtrLimit Main Stack Pointer value to set
AnnaBridge	167:84c0a372a020	730	*/
Anna Bridge	169:a7c7b631e539	731	__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
AnnaBridge	167:84c0a372a020	732	{
Anna Bridge	169:a7c7b631e539	733	#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
Anna Bridge	169:a7c7b631e539	734	// without main extensions, the non-secure MSPLIM is RAZ/WI
Anna Bridge	169:a7c7b631e539	735	(void)MainStackPtrLimit;
Anna Bridge	169:a7c7b631e539	736	#else
AnnaBridge	167:84c0a372a020	737	__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
Anna Bridge	169:a7c7b631e539	738	#endif
AnnaBridge	167:84c0a372a020	739	}
AnnaBridge	167:84c0a372a020	740	#endif
AnnaBridge	167:84c0a372a020	741
AnnaBridge	167:84c0a372a020	742	#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	743	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge	167:84c0a372a020	744
AnnaBridge	167:84c0a372a020	745
AnnaBridge	167:84c0a372a020	746	#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	747	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	167:84c0a372a020	748
AnnaBridge	167:84c0a372a020	749	/**
AnnaBridge	167:84c0a372a020	750	\brief Get FPSCR
AnnaBridge	167:84c0a372a020	751	\details Returns the current value of the Floating Point Status/Control register.
AnnaBridge	167:84c0a372a020	752	\return Floating Point Status/Control register value
AnnaBridge	167:84c0a372a020	753	*/
AnnaBridge	167:84c0a372a020	754	#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge	167:84c0a372a020	755	(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge	167:84c0a372a020	756	#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
AnnaBridge	167:84c0a372a020	757	#else
AnnaBridge	167:84c0a372a020	758	#define __get_FPSCR() ((uint32_t)0U)
AnnaBridge	167:84c0a372a020	759	#endif
AnnaBridge	167:84c0a372a020	760
AnnaBridge	167:84c0a372a020	761	/**
AnnaBridge	167:84c0a372a020	762	\brief Set FPSCR
AnnaBridge	167:84c0a372a020	763	\details Assigns the given value to the Floating Point Status/Control register.
AnnaBridge	167:84c0a372a020	764	\param [in] fpscr Floating Point Status/Control value to set
AnnaBridge	167:84c0a372a020	765	*/
AnnaBridge	167:84c0a372a020	766	#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge	167:84c0a372a020	767	(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge	167:84c0a372a020	768	#define __set_FPSCR __builtin_arm_set_fpscr
AnnaBridge	167:84c0a372a020	769	#else
AnnaBridge	167:84c0a372a020	770	#define __set_FPSCR(x) ((void)(x))
AnnaBridge	167:84c0a372a020	771	#endif
AnnaBridge	167:84c0a372a020	772
AnnaBridge	167:84c0a372a020	773	#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	774	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge	167:84c0a372a020	775
AnnaBridge	167:84c0a372a020	776
AnnaBridge	167:84c0a372a020	777
AnnaBridge	167:84c0a372a020	778	/@} end of CMSIS_Core_RegAccFunctions /
AnnaBridge	167:84c0a372a020	779
AnnaBridge	167:84c0a372a020	780
AnnaBridge	167:84c0a372a020	781	/* ########################## Core Instruction Access ######################### */
AnnaBridge	167:84c0a372a020	782	/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
AnnaBridge	167:84c0a372a020	783	Access to dedicated instructions
AnnaBridge	167:84c0a372a020	784	@{
AnnaBridge	167:84c0a372a020	785	*/
AnnaBridge	167:84c0a372a020	786
AnnaBridge	167:84c0a372a020	787	/* Define macros for porting to both thumb1 and thumb2.
AnnaBridge	167:84c0a372a020	788	* For thumb1, use low register (r0-r7), specified by constraint "l"
AnnaBridge	167:84c0a372a020	789	* Otherwise, use general registers, specified by constraint "r" */
AnnaBridge	167:84c0a372a020	790	#if defined (__thumb__) && !defined (__thumb2__)
AnnaBridge	167:84c0a372a020	791	#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
AnnaBridge	167:84c0a372a020	792	#define __CMSIS_GCC_USE_REG(r) "l" (r)
AnnaBridge	167:84c0a372a020	793	#else
AnnaBridge	167:84c0a372a020	794	#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
AnnaBridge	167:84c0a372a020	795	#define __CMSIS_GCC_USE_REG(r) "r" (r)
AnnaBridge	167:84c0a372a020	796	#endif
AnnaBridge	167:84c0a372a020	797
AnnaBridge	167:84c0a372a020	798	/**
AnnaBridge	167:84c0a372a020	799	\brief No Operation
AnnaBridge	167:84c0a372a020	800	\details No Operation does nothing. This instruction can be used for code alignment purposes.
AnnaBridge	167:84c0a372a020	801	*/
AnnaBridge	167:84c0a372a020	802	#define __NOP __builtin_arm_nop
AnnaBridge	167:84c0a372a020	803
AnnaBridge	167:84c0a372a020	804	/**
AnnaBridge	167:84c0a372a020	805	\brief Wait For Interrupt
AnnaBridge	167:84c0a372a020	806	\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
AnnaBridge	167:84c0a372a020	807	*/
AnnaBridge	167:84c0a372a020	808	#define __WFI __builtin_arm_wfi
AnnaBridge	167:84c0a372a020	809
AnnaBridge	167:84c0a372a020	810
AnnaBridge	167:84c0a372a020	811	/**
AnnaBridge	167:84c0a372a020	812	\brief Wait For Event
AnnaBridge	167:84c0a372a020	813	\details Wait For Event is a hint instruction that permits the processor to enter
AnnaBridge	167:84c0a372a020	814	a low-power state until one of a number of events occurs.
AnnaBridge	167:84c0a372a020	815	*/
AnnaBridge	167:84c0a372a020	816	#define __WFE __builtin_arm_wfe
AnnaBridge	167:84c0a372a020	817
AnnaBridge	167:84c0a372a020	818
AnnaBridge	167:84c0a372a020	819	/**
AnnaBridge	167:84c0a372a020	820	\brief Send Event
AnnaBridge	167:84c0a372a020	821	\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
AnnaBridge	167:84c0a372a020	822	*/
AnnaBridge	167:84c0a372a020	823	#define __SEV __builtin_arm_sev
AnnaBridge	167:84c0a372a020	824
AnnaBridge	167:84c0a372a020	825
AnnaBridge	167:84c0a372a020	826	/**
AnnaBridge	167:84c0a372a020	827	\brief Instruction Synchronization Barrier
AnnaBridge	167:84c0a372a020	828	\details Instruction Synchronization Barrier flushes the pipeline in the processor,
AnnaBridge	167:84c0a372a020	829	so that all instructions following the ISB are fetched from cache or memory,
AnnaBridge	167:84c0a372a020	830	after the instruction has been completed.
AnnaBridge	167:84c0a372a020	831	*/
AnnaBridge	167:84c0a372a020	832	#define __ISB() __builtin_arm_isb(0xF);
AnnaBridge	167:84c0a372a020	833
AnnaBridge	167:84c0a372a020	834	/**
AnnaBridge	167:84c0a372a020	835	\brief Data Synchronization Barrier
AnnaBridge	167:84c0a372a020	836	\details Acts as a special kind of Data Memory Barrier.
AnnaBridge	167:84c0a372a020	837	It completes when all explicit memory accesses before this instruction complete.
AnnaBridge	167:84c0a372a020	838	*/
AnnaBridge	167:84c0a372a020	839	#define __DSB() __builtin_arm_dsb(0xF);
AnnaBridge	167:84c0a372a020	840
AnnaBridge	167:84c0a372a020	841
AnnaBridge	167:84c0a372a020	842	/**
AnnaBridge	167:84c0a372a020	843	\brief Data Memory Barrier
AnnaBridge	167:84c0a372a020	844	\details Ensures the apparent order of the explicit memory operations before
AnnaBridge	167:84c0a372a020	845	and after the instruction, without ensuring their completion.
AnnaBridge	167:84c0a372a020	846	*/
AnnaBridge	167:84c0a372a020	847	#define __DMB() __builtin_arm_dmb(0xF);
AnnaBridge	167:84c0a372a020	848
AnnaBridge	167:84c0a372a020	849
AnnaBridge	167:84c0a372a020	850	/**
AnnaBridge	167:84c0a372a020	851	\brief Reverse byte order (32 bit)
Anna Bridge	169:a7c7b631e539	852	\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
AnnaBridge	167:84c0a372a020	853	\param [in] value Value to reverse
AnnaBridge	167:84c0a372a020	854	\return Reversed value
AnnaBridge	167:84c0a372a020	855	*/
Anna Bridge	169:a7c7b631e539	856	#define __REV(value) __builtin_bswap32(value)
AnnaBridge	167:84c0a372a020	857
AnnaBridge	167:84c0a372a020	858
AnnaBridge	167:84c0a372a020	859	/**
AnnaBridge	167:84c0a372a020	860	\brief Reverse byte order (16 bit)
Anna Bridge	169:a7c7b631e539	861	\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
AnnaBridge	167:84c0a372a020	862	\param [in] value Value to reverse
AnnaBridge	167:84c0a372a020	863	\return Reversed value
AnnaBridge	167:84c0a372a020	864	*/
Anna Bridge	169:a7c7b631e539	865	#define __REV16(value) __ROR(__REV(value), 16)
AnnaBridge	167:84c0a372a020	866
AnnaBridge	167:84c0a372a020	867
AnnaBridge	167:84c0a372a020	868	/**
Anna Bridge	169:a7c7b631e539	869	\brief Reverse byte order (16 bit)
Anna Bridge	169:a7c7b631e539	870	\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
AnnaBridge	167:84c0a372a020	871	\param [in] value Value to reverse
AnnaBridge	167:84c0a372a020	872	\return Reversed value
AnnaBridge	167:84c0a372a020	873	*/
Anna Bridge	169:a7c7b631e539	874	#define __REVSH(value) (int16_t)__builtin_bswap16(value)
AnnaBridge	167:84c0a372a020	875
AnnaBridge	167:84c0a372a020	876
AnnaBridge	167:84c0a372a020	877	/**
AnnaBridge	167:84c0a372a020	878	\brief Rotate Right in unsigned value (32 bit)
AnnaBridge	167:84c0a372a020	879	\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
AnnaBridge	167:84c0a372a020	880	\param [in] op1 Value to rotate
AnnaBridge	167:84c0a372a020	881	\param [in] op2 Number of Bits to rotate
AnnaBridge	167:84c0a372a020	882	\return Rotated value
AnnaBridge	167:84c0a372a020	883	*/
Anna Bridge	169:a7c7b631e539	884	__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	885	{
Anna Bridge	169:a7c7b631e539	886	op2 %= 32U;
Anna Bridge	169:a7c7b631e539	887	if (op2 == 0U)
Anna Bridge	169:a7c7b631e539	888	{
Anna Bridge	169:a7c7b631e539	889	return op1;
Anna Bridge	169:a7c7b631e539	890	}
AnnaBridge	167:84c0a372a020	891	return (op1 >> op2) \| (op1 << (32U - op2));
AnnaBridge	167:84c0a372a020	892	}
AnnaBridge	167:84c0a372a020	893
AnnaBridge	167:84c0a372a020	894
AnnaBridge	167:84c0a372a020	895	/**
AnnaBridge	167:84c0a372a020	896	\brief Breakpoint
AnnaBridge	167:84c0a372a020	897	\details Causes the processor to enter Debug state.
AnnaBridge	167:84c0a372a020	898	Debug tools can use this to investigate system state when the instruction at a particular address is reached.
AnnaBridge	167:84c0a372a020	899	\param [in] value is ignored by the processor.
AnnaBridge	167:84c0a372a020	900	If required, a debugger can use it to store additional information about the breakpoint.
AnnaBridge	167:84c0a372a020	901	*/
AnnaBridge	167:84c0a372a020	902	#define __BKPT(value) __ASM volatile ("bkpt "#value)
AnnaBridge	167:84c0a372a020	903
AnnaBridge	167:84c0a372a020	904
AnnaBridge	167:84c0a372a020	905	/**
AnnaBridge	167:84c0a372a020	906	\brief Reverse bit order of value
AnnaBridge	167:84c0a372a020	907	\details Reverses the bit order of the given value.
AnnaBridge	167:84c0a372a020	908	\param [in] value Value to reverse
AnnaBridge	167:84c0a372a020	909	\return Reversed value
AnnaBridge	167:84c0a372a020	910	*/
Anna Bridge	169:a7c7b631e539	911	#define __RBIT __builtin_arm_rbit
AnnaBridge	167:84c0a372a020	912
AnnaBridge	167:84c0a372a020	913	/**
AnnaBridge	167:84c0a372a020	914	\brief Count leading zeros
AnnaBridge	167:84c0a372a020	915	\details Counts the number of leading zeros of a data value.
AnnaBridge	167:84c0a372a020	916	\param [in] value Value to count the leading zeros
AnnaBridge	167:84c0a372a020	917	\return number of leading zeros in value
AnnaBridge	167:84c0a372a020	918	*/
Anna Bridge	169:a7c7b631e539	919	#define __CLZ (uint8_t)__builtin_clz
AnnaBridge	167:84c0a372a020	920
AnnaBridge	167:84c0a372a020	921
AnnaBridge	167:84c0a372a020	922	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	923	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	924	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	925	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge	167:84c0a372a020	926	/**
AnnaBridge	167:84c0a372a020	927	\brief LDR Exclusive (8 bit)
AnnaBridge	167:84c0a372a020	928	\details Executes a exclusive LDR instruction for 8 bit value.
AnnaBridge	167:84c0a372a020	929	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	930	\return value of type uint8_t at (*ptr)
AnnaBridge	167:84c0a372a020	931	*/
AnnaBridge	167:84c0a372a020	932	#define __LDREXB (uint8_t)__builtin_arm_ldrex
AnnaBridge	167:84c0a372a020	933
AnnaBridge	167:84c0a372a020	934
AnnaBridge	167:84c0a372a020	935	/**
AnnaBridge	167:84c0a372a020	936	\brief LDR Exclusive (16 bit)
AnnaBridge	167:84c0a372a020	937	\details Executes a exclusive LDR instruction for 16 bit values.
AnnaBridge	167:84c0a372a020	938	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	939	\return value of type uint16_t at (*ptr)
AnnaBridge	167:84c0a372a020	940	*/
AnnaBridge	167:84c0a372a020	941	#define __LDREXH (uint16_t)__builtin_arm_ldrex
AnnaBridge	167:84c0a372a020	942
AnnaBridge	167:84c0a372a020	943
AnnaBridge	167:84c0a372a020	944	/**
AnnaBridge	167:84c0a372a020	945	\brief LDR Exclusive (32 bit)
AnnaBridge	167:84c0a372a020	946	\details Executes a exclusive LDR instruction for 32 bit values.
AnnaBridge	167:84c0a372a020	947	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	948	\return value of type uint32_t at (*ptr)
AnnaBridge	167:84c0a372a020	949	*/
AnnaBridge	167:84c0a372a020	950	#define __LDREXW (uint32_t)__builtin_arm_ldrex
AnnaBridge	167:84c0a372a020	951
AnnaBridge	167:84c0a372a020	952
AnnaBridge	167:84c0a372a020	953	/**
AnnaBridge	167:84c0a372a020	954	\brief STR Exclusive (8 bit)
AnnaBridge	167:84c0a372a020	955	\details Executes a exclusive STR instruction for 8 bit values.
AnnaBridge	167:84c0a372a020	956	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	957	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	958	\return 0 Function succeeded
AnnaBridge	167:84c0a372a020	959	\return 1 Function failed
AnnaBridge	167:84c0a372a020	960	*/
AnnaBridge	167:84c0a372a020	961	#define __STREXB (uint32_t)__builtin_arm_strex
AnnaBridge	167:84c0a372a020	962
AnnaBridge	167:84c0a372a020	963
AnnaBridge	167:84c0a372a020	964	/**
AnnaBridge	167:84c0a372a020	965	\brief STR Exclusive (16 bit)
AnnaBridge	167:84c0a372a020	966	\details Executes a exclusive STR instruction for 16 bit values.
AnnaBridge	167:84c0a372a020	967	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	968	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	969	\return 0 Function succeeded
AnnaBridge	167:84c0a372a020	970	\return 1 Function failed
AnnaBridge	167:84c0a372a020	971	*/
AnnaBridge	167:84c0a372a020	972	#define __STREXH (uint32_t)__builtin_arm_strex
AnnaBridge	167:84c0a372a020	973
AnnaBridge	167:84c0a372a020	974
AnnaBridge	167:84c0a372a020	975	/**
AnnaBridge	167:84c0a372a020	976	\brief STR Exclusive (32 bit)
AnnaBridge	167:84c0a372a020	977	\details Executes a exclusive STR instruction for 32 bit values.
AnnaBridge	167:84c0a372a020	978	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	979	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	980	\return 0 Function succeeded
AnnaBridge	167:84c0a372a020	981	\return 1 Function failed
AnnaBridge	167:84c0a372a020	982	*/
AnnaBridge	167:84c0a372a020	983	#define __STREXW (uint32_t)__builtin_arm_strex
AnnaBridge	167:84c0a372a020	984
AnnaBridge	167:84c0a372a020	985
AnnaBridge	167:84c0a372a020	986	/**
AnnaBridge	167:84c0a372a020	987	\brief Remove the exclusive lock
AnnaBridge	167:84c0a372a020	988	\details Removes the exclusive lock which is created by LDREX.
AnnaBridge	167:84c0a372a020	989	*/
AnnaBridge	167:84c0a372a020	990	#define __CLREX __builtin_arm_clrex
AnnaBridge	167:84c0a372a020	991
AnnaBridge	167:84c0a372a020	992	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	993	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	994	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	995	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge	167:84c0a372a020	996
AnnaBridge	167:84c0a372a020	997
AnnaBridge	167:84c0a372a020	998	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	999	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	1000	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	167:84c0a372a020	1001
AnnaBridge	167:84c0a372a020	1002	/**
AnnaBridge	167:84c0a372a020	1003	\brief Signed Saturate
AnnaBridge	167:84c0a372a020	1004	\details Saturates a signed value.
AnnaBridge	167:84c0a372a020	1005	\param [in] value Value to be saturated
AnnaBridge	167:84c0a372a020	1006	\param [in] sat Bit position to saturate to (1..32)
AnnaBridge	167:84c0a372a020	1007	\return Saturated value
AnnaBridge	167:84c0a372a020	1008	*/
AnnaBridge	167:84c0a372a020	1009	#define __SSAT __builtin_arm_ssat
AnnaBridge	167:84c0a372a020	1010
AnnaBridge	167:84c0a372a020	1011
AnnaBridge	167:84c0a372a020	1012	/**
AnnaBridge	167:84c0a372a020	1013	\brief Unsigned Saturate
AnnaBridge	167:84c0a372a020	1014	\details Saturates an unsigned value.
AnnaBridge	167:84c0a372a020	1015	\param [in] value Value to be saturated
AnnaBridge	167:84c0a372a020	1016	\param [in] sat Bit position to saturate to (0..31)
AnnaBridge	167:84c0a372a020	1017	\return Saturated value
AnnaBridge	167:84c0a372a020	1018	*/
AnnaBridge	167:84c0a372a020	1019	#define __USAT __builtin_arm_usat
AnnaBridge	167:84c0a372a020	1020
AnnaBridge	167:84c0a372a020	1021
AnnaBridge	167:84c0a372a020	1022	/**
AnnaBridge	167:84c0a372a020	1023	\brief Rotate Right with Extend (32 bit)
AnnaBridge	167:84c0a372a020	1024	\details Moves each bit of a bitstring right by one bit.
AnnaBridge	167:84c0a372a020	1025	The carry input is shifted in at the left end of the bitstring.
AnnaBridge	167:84c0a372a020	1026	\param [in] value Value to rotate
AnnaBridge	167:84c0a372a020	1027	\return Rotated value
AnnaBridge	167:84c0a372a020	1028	*/
Anna Bridge	169:a7c7b631e539	1029	__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
AnnaBridge	167:84c0a372a020	1030	{
AnnaBridge	167:84c0a372a020	1031	uint32_t result;
AnnaBridge	167:84c0a372a020	1032
AnnaBridge	167:84c0a372a020	1033	__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge	167:84c0a372a020	1034	return(result);
AnnaBridge	167:84c0a372a020	1035	}
AnnaBridge	167:84c0a372a020	1036
AnnaBridge	167:84c0a372a020	1037
AnnaBridge	167:84c0a372a020	1038	/**
AnnaBridge	167:84c0a372a020	1039	\brief LDRT Unprivileged (8 bit)
AnnaBridge	167:84c0a372a020	1040	\details Executes a Unprivileged LDRT instruction for 8 bit value.
AnnaBridge	167:84c0a372a020	1041	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	1042	\return value of type uint8_t at (*ptr)
AnnaBridge	167:84c0a372a020	1043	*/
Anna Bridge	169:a7c7b631e539	1044	__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
AnnaBridge	167:84c0a372a020	1045	{
AnnaBridge	167:84c0a372a020	1046	uint32_t result;
AnnaBridge	167:84c0a372a020	1047
AnnaBridge	167:84c0a372a020	1048	__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	167:84c0a372a020	1049	return ((uint8_t) result); /* Add explicit type cast here */
AnnaBridge	167:84c0a372a020	1050	}
AnnaBridge	167:84c0a372a020	1051
AnnaBridge	167:84c0a372a020	1052
AnnaBridge	167:84c0a372a020	1053	/**
AnnaBridge	167:84c0a372a020	1054	\brief LDRT Unprivileged (16 bit)
AnnaBridge	167:84c0a372a020	1055	\details Executes a Unprivileged LDRT instruction for 16 bit values.
AnnaBridge	167:84c0a372a020	1056	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	1057	\return value of type uint16_t at (*ptr)
AnnaBridge	167:84c0a372a020	1058	*/
Anna Bridge	169:a7c7b631e539	1059	__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
AnnaBridge	167:84c0a372a020	1060	{
AnnaBridge	167:84c0a372a020	1061	uint32_t result;
AnnaBridge	167:84c0a372a020	1062
AnnaBridge	167:84c0a372a020	1063	__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	167:84c0a372a020	1064	return ((uint16_t) result); /* Add explicit type cast here */
AnnaBridge	167:84c0a372a020	1065	}
AnnaBridge	167:84c0a372a020	1066
AnnaBridge	167:84c0a372a020	1067
AnnaBridge	167:84c0a372a020	1068	/**
AnnaBridge	167:84c0a372a020	1069	\brief LDRT Unprivileged (32 bit)
AnnaBridge	167:84c0a372a020	1070	\details Executes a Unprivileged LDRT instruction for 32 bit values.
AnnaBridge	167:84c0a372a020	1071	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	1072	\return value of type uint32_t at (*ptr)
AnnaBridge	167:84c0a372a020	1073	*/
Anna Bridge	169:a7c7b631e539	1074	__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
AnnaBridge	167:84c0a372a020	1075	{
AnnaBridge	167:84c0a372a020	1076	uint32_t result;
AnnaBridge	167:84c0a372a020	1077
AnnaBridge	167:84c0a372a020	1078	__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	167:84c0a372a020	1079	return(result);
AnnaBridge	167:84c0a372a020	1080	}
AnnaBridge	167:84c0a372a020	1081
AnnaBridge	167:84c0a372a020	1082
AnnaBridge	167:84c0a372a020	1083	/**
AnnaBridge	167:84c0a372a020	1084	\brief STRT Unprivileged (8 bit)
AnnaBridge	167:84c0a372a020	1085	\details Executes a Unprivileged STRT instruction for 8 bit values.
AnnaBridge	167:84c0a372a020	1086	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	1087	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	1088	*/
Anna Bridge	169:a7c7b631e539	1089	__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
AnnaBridge	167:84c0a372a020	1090	{
AnnaBridge	167:84c0a372a020	1091	__ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	167:84c0a372a020	1092	}
AnnaBridge	167:84c0a372a020	1093
AnnaBridge	167:84c0a372a020	1094
AnnaBridge	167:84c0a372a020	1095	/**
AnnaBridge	167:84c0a372a020	1096	\brief STRT Unprivileged (16 bit)
AnnaBridge	167:84c0a372a020	1097	\details Executes a Unprivileged STRT instruction for 16 bit values.
AnnaBridge	167:84c0a372a020	1098	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	1099	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	1100	*/
Anna Bridge	169:a7c7b631e539	1101	__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
AnnaBridge	167:84c0a372a020	1102	{
AnnaBridge	167:84c0a372a020	1103	__ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	167:84c0a372a020	1104	}
AnnaBridge	167:84c0a372a020	1105
AnnaBridge	167:84c0a372a020	1106
AnnaBridge	167:84c0a372a020	1107	/**
AnnaBridge	167:84c0a372a020	1108	\brief STRT Unprivileged (32 bit)
AnnaBridge	167:84c0a372a020	1109	\details Executes a Unprivileged STRT instruction for 32 bit values.
AnnaBridge	167:84c0a372a020	1110	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	1111	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	1112	*/
Anna Bridge	169:a7c7b631e539	1113	__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
AnnaBridge	167:84c0a372a020	1114	{
AnnaBridge	167:84c0a372a020	1115	__ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
AnnaBridge	167:84c0a372a020	1116	}
AnnaBridge	167:84c0a372a020	1117
AnnaBridge	167:84c0a372a020	1118	#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	1119	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	1120	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge	167:84c0a372a020	1121
AnnaBridge	167:84c0a372a020	1122	/**
AnnaBridge	167:84c0a372a020	1123	\brief Signed Saturate
AnnaBridge	167:84c0a372a020	1124	\details Saturates a signed value.
AnnaBridge	167:84c0a372a020	1125	\param [in] value Value to be saturated
AnnaBridge	167:84c0a372a020	1126	\param [in] sat Bit position to saturate to (1..32)
AnnaBridge	167:84c0a372a020	1127	\return Saturated value
AnnaBridge	167:84c0a372a020	1128	*/
Anna Bridge	169:a7c7b631e539	1129	__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
AnnaBridge	167:84c0a372a020	1130	{
Anna Bridge	169:a7c7b631e539	1131	if ((sat >= 1U) && (sat <= 32U))
Anna Bridge	169:a7c7b631e539	1132	{
AnnaBridge	167:84c0a372a020	1133	const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
AnnaBridge	167:84c0a372a020	1134	const int32_t min = -1 - max ;
Anna Bridge	169:a7c7b631e539	1135	if (val > max)
Anna Bridge	169:a7c7b631e539	1136	{
AnnaBridge	167:84c0a372a020	1137	return max;
Anna Bridge	169:a7c7b631e539	1138	}
Anna Bridge	169:a7c7b631e539	1139	else if (val < min)
Anna Bridge	169:a7c7b631e539	1140	{
AnnaBridge	167:84c0a372a020	1141	return min;
AnnaBridge	167:84c0a372a020	1142	}
AnnaBridge	167:84c0a372a020	1143	}
AnnaBridge	167:84c0a372a020	1144	return val;
AnnaBridge	167:84c0a372a020	1145	}
AnnaBridge	167:84c0a372a020	1146
AnnaBridge	167:84c0a372a020	1147	/**
AnnaBridge	167:84c0a372a020	1148	\brief Unsigned Saturate
AnnaBridge	167:84c0a372a020	1149	\details Saturates an unsigned value.
AnnaBridge	167:84c0a372a020	1150	\param [in] value Value to be saturated
AnnaBridge	167:84c0a372a020	1151	\param [in] sat Bit position to saturate to (0..31)
AnnaBridge	167:84c0a372a020	1152	\return Saturated value
AnnaBridge	167:84c0a372a020	1153	*/
Anna Bridge	169:a7c7b631e539	1154	__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
AnnaBridge	167:84c0a372a020	1155	{
Anna Bridge	169:a7c7b631e539	1156	if (sat <= 31U)
Anna Bridge	169:a7c7b631e539	1157	{
AnnaBridge	167:84c0a372a020	1158	const uint32_t max = ((1U << sat) - 1U);
Anna Bridge	169:a7c7b631e539	1159	if (val > (int32_t)max)
Anna Bridge	169:a7c7b631e539	1160	{
AnnaBridge	167:84c0a372a020	1161	return max;
Anna Bridge	169:a7c7b631e539	1162	}
Anna Bridge	169:a7c7b631e539	1163	else if (val < 0)
Anna Bridge	169:a7c7b631e539	1164	{
AnnaBridge	167:84c0a372a020	1165	return 0U;
AnnaBridge	167:84c0a372a020	1166	}
AnnaBridge	167:84c0a372a020	1167	}
AnnaBridge	167:84c0a372a020	1168	return (uint32_t)val;
AnnaBridge	167:84c0a372a020	1169	}
AnnaBridge	167:84c0a372a020	1170
AnnaBridge	167:84c0a372a020	1171	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	1172	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	1173	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge	167:84c0a372a020	1174
AnnaBridge	167:84c0a372a020	1175
AnnaBridge	167:84c0a372a020	1176	#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	1177	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge	167:84c0a372a020	1178	/**
AnnaBridge	167:84c0a372a020	1179	\brief Load-Acquire (8 bit)
AnnaBridge	167:84c0a372a020	1180	\details Executes a LDAB instruction for 8 bit value.
AnnaBridge	167:84c0a372a020	1181	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	1182	\return value of type uint8_t at (*ptr)
AnnaBridge	167:84c0a372a020	1183	*/
Anna Bridge	169:a7c7b631e539	1184	__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
AnnaBridge	167:84c0a372a020	1185	{
AnnaBridge	167:84c0a372a020	1186	uint32_t result;
AnnaBridge	167:84c0a372a020	1187
AnnaBridge	167:84c0a372a020	1188	__ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	167:84c0a372a020	1189	return ((uint8_t) result);
AnnaBridge	167:84c0a372a020	1190	}
AnnaBridge	167:84c0a372a020	1191
AnnaBridge	167:84c0a372a020	1192
AnnaBridge	167:84c0a372a020	1193	/**
AnnaBridge	167:84c0a372a020	1194	\brief Load-Acquire (16 bit)
AnnaBridge	167:84c0a372a020	1195	\details Executes a LDAH instruction for 16 bit values.
AnnaBridge	167:84c0a372a020	1196	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	1197	\return value of type uint16_t at (*ptr)
AnnaBridge	167:84c0a372a020	1198	*/
Anna Bridge	169:a7c7b631e539	1199	__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
AnnaBridge	167:84c0a372a020	1200	{
AnnaBridge	167:84c0a372a020	1201	uint32_t result;
AnnaBridge	167:84c0a372a020	1202
AnnaBridge	167:84c0a372a020	1203	__ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	167:84c0a372a020	1204	return ((uint16_t) result);
AnnaBridge	167:84c0a372a020	1205	}
AnnaBridge	167:84c0a372a020	1206
AnnaBridge	167:84c0a372a020	1207
AnnaBridge	167:84c0a372a020	1208	/**
AnnaBridge	167:84c0a372a020	1209	\brief Load-Acquire (32 bit)
AnnaBridge	167:84c0a372a020	1210	\details Executes a LDA instruction for 32 bit values.
AnnaBridge	167:84c0a372a020	1211	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	1212	\return value of type uint32_t at (*ptr)
AnnaBridge	167:84c0a372a020	1213	*/
Anna Bridge	169:a7c7b631e539	1214	__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
AnnaBridge	167:84c0a372a020	1215	{
AnnaBridge	167:84c0a372a020	1216	uint32_t result;
AnnaBridge	167:84c0a372a020	1217
AnnaBridge	167:84c0a372a020	1218	__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	167:84c0a372a020	1219	return(result);
AnnaBridge	167:84c0a372a020	1220	}
AnnaBridge	167:84c0a372a020	1221
AnnaBridge	167:84c0a372a020	1222
AnnaBridge	167:84c0a372a020	1223	/**
AnnaBridge	167:84c0a372a020	1224	\brief Store-Release (8 bit)
AnnaBridge	167:84c0a372a020	1225	\details Executes a STLB instruction for 8 bit values.
AnnaBridge	167:84c0a372a020	1226	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	1227	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	1228	*/
Anna Bridge	169:a7c7b631e539	1229	__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
AnnaBridge	167:84c0a372a020	1230	{
AnnaBridge	167:84c0a372a020	1231	__ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	167:84c0a372a020	1232	}
AnnaBridge	167:84c0a372a020	1233
AnnaBridge	167:84c0a372a020	1234
AnnaBridge	167:84c0a372a020	1235	/**
AnnaBridge	167:84c0a372a020	1236	\brief Store-Release (16 bit)
AnnaBridge	167:84c0a372a020	1237	\details Executes a STLH instruction for 16 bit values.
AnnaBridge	167:84c0a372a020	1238	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	1239	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	1240	*/
Anna Bridge	169:a7c7b631e539	1241	__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
AnnaBridge	167:84c0a372a020	1242	{
AnnaBridge	167:84c0a372a020	1243	__ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	167:84c0a372a020	1244	}
AnnaBridge	167:84c0a372a020	1245
AnnaBridge	167:84c0a372a020	1246
AnnaBridge	167:84c0a372a020	1247	/**
AnnaBridge	167:84c0a372a020	1248	\brief Store-Release (32 bit)
AnnaBridge	167:84c0a372a020	1249	\details Executes a STL instruction for 32 bit values.
AnnaBridge	167:84c0a372a020	1250	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	1251	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	1252	*/
Anna Bridge	169:a7c7b631e539	1253	__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
AnnaBridge	167:84c0a372a020	1254	{
AnnaBridge	167:84c0a372a020	1255	__ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	167:84c0a372a020	1256	}
AnnaBridge	167:84c0a372a020	1257
AnnaBridge	167:84c0a372a020	1258
AnnaBridge	167:84c0a372a020	1259	/**
AnnaBridge	167:84c0a372a020	1260	\brief Load-Acquire Exclusive (8 bit)
AnnaBridge	167:84c0a372a020	1261	\details Executes a LDAB exclusive instruction for 8 bit value.
AnnaBridge	167:84c0a372a020	1262	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	1263	\return value of type uint8_t at (*ptr)
AnnaBridge	167:84c0a372a020	1264	*/
AnnaBridge	167:84c0a372a020	1265	#define __LDAEXB (uint8_t)__builtin_arm_ldaex
AnnaBridge	167:84c0a372a020	1266
AnnaBridge	167:84c0a372a020	1267
AnnaBridge	167:84c0a372a020	1268	/**
AnnaBridge	167:84c0a372a020	1269	\brief Load-Acquire Exclusive (16 bit)
AnnaBridge	167:84c0a372a020	1270	\details Executes a LDAH exclusive instruction for 16 bit values.
AnnaBridge	167:84c0a372a020	1271	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	1272	\return value of type uint16_t at (*ptr)
AnnaBridge	167:84c0a372a020	1273	*/
AnnaBridge	167:84c0a372a020	1274	#define __LDAEXH (uint16_t)__builtin_arm_ldaex
AnnaBridge	167:84c0a372a020	1275
AnnaBridge	167:84c0a372a020	1276
AnnaBridge	167:84c0a372a020	1277	/**
AnnaBridge	167:84c0a372a020	1278	\brief Load-Acquire Exclusive (32 bit)
AnnaBridge	167:84c0a372a020	1279	\details Executes a LDA exclusive instruction for 32 bit values.
AnnaBridge	167:84c0a372a020	1280	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	1281	\return value of type uint32_t at (*ptr)
AnnaBridge	167:84c0a372a020	1282	*/
AnnaBridge	167:84c0a372a020	1283	#define __LDAEX (uint32_t)__builtin_arm_ldaex
AnnaBridge	167:84c0a372a020	1284
AnnaBridge	167:84c0a372a020	1285
AnnaBridge	167:84c0a372a020	1286	/**
AnnaBridge	167:84c0a372a020	1287	\brief Store-Release Exclusive (8 bit)
AnnaBridge	167:84c0a372a020	1288	\details Executes a STLB exclusive instruction for 8 bit values.
AnnaBridge	167:84c0a372a020	1289	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	1290	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	1291	\return 0 Function succeeded
AnnaBridge	167:84c0a372a020	1292	\return 1 Function failed
AnnaBridge	167:84c0a372a020	1293	*/
AnnaBridge	167:84c0a372a020	1294	#define __STLEXB (uint32_t)__builtin_arm_stlex
AnnaBridge	167:84c0a372a020	1295
AnnaBridge	167:84c0a372a020	1296
AnnaBridge	167:84c0a372a020	1297	/**
AnnaBridge	167:84c0a372a020	1298	\brief Store-Release Exclusive (16 bit)
AnnaBridge	167:84c0a372a020	1299	\details Executes a STLH exclusive instruction for 16 bit values.
AnnaBridge	167:84c0a372a020	1300	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	1301	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	1302	\return 0 Function succeeded
AnnaBridge	167:84c0a372a020	1303	\return 1 Function failed
AnnaBridge	167:84c0a372a020	1304	*/
AnnaBridge	167:84c0a372a020	1305	#define __STLEXH (uint32_t)__builtin_arm_stlex
AnnaBridge	167:84c0a372a020	1306
AnnaBridge	167:84c0a372a020	1307
AnnaBridge	167:84c0a372a020	1308	/**
AnnaBridge	167:84c0a372a020	1309	\brief Store-Release Exclusive (32 bit)
AnnaBridge	167:84c0a372a020	1310	\details Executes a STL exclusive instruction for 32 bit values.
AnnaBridge	167:84c0a372a020	1311	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	1312	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	1313	\return 0 Function succeeded
AnnaBridge	167:84c0a372a020	1314	\return 1 Function failed
AnnaBridge	167:84c0a372a020	1315	*/
AnnaBridge	167:84c0a372a020	1316	#define __STLEX (uint32_t)__builtin_arm_stlex
AnnaBridge	167:84c0a372a020	1317
AnnaBridge	167:84c0a372a020	1318	#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	1319	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge	167:84c0a372a020	1320
AnnaBridge	167:84c0a372a020	1321	/@}/ /* end of group CMSIS_Core_InstructionInterface */
AnnaBridge	167:84c0a372a020	1322
AnnaBridge	167:84c0a372a020	1323
AnnaBridge	167:84c0a372a020	1324	/* ################### Compiler specific Intrinsics ########################### */
AnnaBridge	167:84c0a372a020	1325	/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
AnnaBridge	167:84c0a372a020	1326	Access to dedicated SIMD instructions
AnnaBridge	167:84c0a372a020	1327	@{
AnnaBridge	167:84c0a372a020	1328	*/
AnnaBridge	167:84c0a372a020	1329
AnnaBridge	167:84c0a372a020	1330	#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
AnnaBridge	167:84c0a372a020	1331
Anna Bridge	169:a7c7b631e539	1332	__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1333	{
AnnaBridge	167:84c0a372a020	1334	uint32_t result;
AnnaBridge	167:84c0a372a020	1335
AnnaBridge	167:84c0a372a020	1336	__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1337	return(result);
AnnaBridge	167:84c0a372a020	1338	}
AnnaBridge	167:84c0a372a020	1339
Anna Bridge	169:a7c7b631e539	1340	__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1341	{
AnnaBridge	167:84c0a372a020	1342	uint32_t result;
AnnaBridge	167:84c0a372a020	1343
AnnaBridge	167:84c0a372a020	1344	__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1345	return(result);
AnnaBridge	167:84c0a372a020	1346	}
AnnaBridge	167:84c0a372a020	1347
Anna Bridge	169:a7c7b631e539	1348	__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1349	{
AnnaBridge	167:84c0a372a020	1350	uint32_t result;
AnnaBridge	167:84c0a372a020	1351
AnnaBridge	167:84c0a372a020	1352	__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1353	return(result);
AnnaBridge	167:84c0a372a020	1354	}
AnnaBridge	167:84c0a372a020	1355
Anna Bridge	169:a7c7b631e539	1356	__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1357	{
AnnaBridge	167:84c0a372a020	1358	uint32_t result;
AnnaBridge	167:84c0a372a020	1359
AnnaBridge	167:84c0a372a020	1360	__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1361	return(result);
AnnaBridge	167:84c0a372a020	1362	}
AnnaBridge	167:84c0a372a020	1363
Anna Bridge	169:a7c7b631e539	1364	__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1365	{
AnnaBridge	167:84c0a372a020	1366	uint32_t result;
AnnaBridge	167:84c0a372a020	1367
AnnaBridge	167:84c0a372a020	1368	__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1369	return(result);
AnnaBridge	167:84c0a372a020	1370	}
AnnaBridge	167:84c0a372a020	1371
Anna Bridge	169:a7c7b631e539	1372	__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1373	{
AnnaBridge	167:84c0a372a020	1374	uint32_t result;
AnnaBridge	167:84c0a372a020	1375
AnnaBridge	167:84c0a372a020	1376	__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1377	return(result);
AnnaBridge	167:84c0a372a020	1378	}
AnnaBridge	167:84c0a372a020	1379
AnnaBridge	167:84c0a372a020	1380
Anna Bridge	169:a7c7b631e539	1381	__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1382	{
AnnaBridge	167:84c0a372a020	1383	uint32_t result;
AnnaBridge	167:84c0a372a020	1384
AnnaBridge	167:84c0a372a020	1385	__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1386	return(result);
AnnaBridge	167:84c0a372a020	1387	}
AnnaBridge	167:84c0a372a020	1388
Anna Bridge	169:a7c7b631e539	1389	__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1390	{
AnnaBridge	167:84c0a372a020	1391	uint32_t result;
AnnaBridge	167:84c0a372a020	1392
AnnaBridge	167:84c0a372a020	1393	__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1394	return(result);
AnnaBridge	167:84c0a372a020	1395	}
AnnaBridge	167:84c0a372a020	1396
Anna Bridge	169:a7c7b631e539	1397	__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1398	{
AnnaBridge	167:84c0a372a020	1399	uint32_t result;
AnnaBridge	167:84c0a372a020	1400
AnnaBridge	167:84c0a372a020	1401	__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1402	return(result);
AnnaBridge	167:84c0a372a020	1403	}
AnnaBridge	167:84c0a372a020	1404
Anna Bridge	169:a7c7b631e539	1405	__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1406	{
AnnaBridge	167:84c0a372a020	1407	uint32_t result;
AnnaBridge	167:84c0a372a020	1408
AnnaBridge	167:84c0a372a020	1409	__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1410	return(result);
AnnaBridge	167:84c0a372a020	1411	}
AnnaBridge	167:84c0a372a020	1412
Anna Bridge	169:a7c7b631e539	1413	__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1414	{
AnnaBridge	167:84c0a372a020	1415	uint32_t result;
AnnaBridge	167:84c0a372a020	1416
AnnaBridge	167:84c0a372a020	1417	__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1418	return(result);
AnnaBridge	167:84c0a372a020	1419	}
AnnaBridge	167:84c0a372a020	1420
Anna Bridge	169:a7c7b631e539	1421	__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1422	{
AnnaBridge	167:84c0a372a020	1423	uint32_t result;
AnnaBridge	167:84c0a372a020	1424
AnnaBridge	167:84c0a372a020	1425	__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1426	return(result);
AnnaBridge	167:84c0a372a020	1427	}
AnnaBridge	167:84c0a372a020	1428
AnnaBridge	167:84c0a372a020	1429
Anna Bridge	169:a7c7b631e539	1430	__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1431	{
AnnaBridge	167:84c0a372a020	1432	uint32_t result;
AnnaBridge	167:84c0a372a020	1433
AnnaBridge	167:84c0a372a020	1434	__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1435	return(result);
AnnaBridge	167:84c0a372a020	1436	}
AnnaBridge	167:84c0a372a020	1437
Anna Bridge	169:a7c7b631e539	1438	__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1439	{
AnnaBridge	167:84c0a372a020	1440	uint32_t result;
AnnaBridge	167:84c0a372a020	1441
AnnaBridge	167:84c0a372a020	1442	__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1443	return(result);
AnnaBridge	167:84c0a372a020	1444	}
AnnaBridge	167:84c0a372a020	1445
Anna Bridge	169:a7c7b631e539	1446	__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1447	{
AnnaBridge	167:84c0a372a020	1448	uint32_t result;
AnnaBridge	167:84c0a372a020	1449
AnnaBridge	167:84c0a372a020	1450	__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1451	return(result);
AnnaBridge	167:84c0a372a020	1452	}
AnnaBridge	167:84c0a372a020	1453
Anna Bridge	169:a7c7b631e539	1454	__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1455	{
AnnaBridge	167:84c0a372a020	1456	uint32_t result;
AnnaBridge	167:84c0a372a020	1457
AnnaBridge	167:84c0a372a020	1458	__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1459	return(result);
AnnaBridge	167:84c0a372a020	1460	}
AnnaBridge	167:84c0a372a020	1461
Anna Bridge	169:a7c7b631e539	1462	__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1463	{
AnnaBridge	167:84c0a372a020	1464	uint32_t result;
AnnaBridge	167:84c0a372a020	1465
AnnaBridge	167:84c0a372a020	1466	__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1467	return(result);
AnnaBridge	167:84c0a372a020	1468	}
AnnaBridge	167:84c0a372a020	1469
Anna Bridge	169:a7c7b631e539	1470	__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1471	{
AnnaBridge	167:84c0a372a020	1472	uint32_t result;
AnnaBridge	167:84c0a372a020	1473
AnnaBridge	167:84c0a372a020	1474	__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1475	return(result);
AnnaBridge	167:84c0a372a020	1476	}
AnnaBridge	167:84c0a372a020	1477
Anna Bridge	169:a7c7b631e539	1478	__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1479	{
AnnaBridge	167:84c0a372a020	1480	uint32_t result;
AnnaBridge	167:84c0a372a020	1481
AnnaBridge	167:84c0a372a020	1482	__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1483	return(result);
AnnaBridge	167:84c0a372a020	1484	}
AnnaBridge	167:84c0a372a020	1485
Anna Bridge	169:a7c7b631e539	1486	__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1487	{
AnnaBridge	167:84c0a372a020	1488	uint32_t result;
AnnaBridge	167:84c0a372a020	1489
AnnaBridge	167:84c0a372a020	1490	__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1491	return(result);
AnnaBridge	167:84c0a372a020	1492	}
AnnaBridge	167:84c0a372a020	1493
Anna Bridge	169:a7c7b631e539	1494	__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1495	{
AnnaBridge	167:84c0a372a020	1496	uint32_t result;
AnnaBridge	167:84c0a372a020	1497
AnnaBridge	167:84c0a372a020	1498	__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1499	return(result);
AnnaBridge	167:84c0a372a020	1500	}
AnnaBridge	167:84c0a372a020	1501
Anna Bridge	169:a7c7b631e539	1502	__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1503	{
AnnaBridge	167:84c0a372a020	1504	uint32_t result;
AnnaBridge	167:84c0a372a020	1505
AnnaBridge	167:84c0a372a020	1506	__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1507	return(result);
AnnaBridge	167:84c0a372a020	1508	}
AnnaBridge	167:84c0a372a020	1509
Anna Bridge	169:a7c7b631e539	1510	__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1511	{
AnnaBridge	167:84c0a372a020	1512	uint32_t result;
AnnaBridge	167:84c0a372a020	1513
AnnaBridge	167:84c0a372a020	1514	__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1515	return(result);
AnnaBridge	167:84c0a372a020	1516	}
AnnaBridge	167:84c0a372a020	1517
Anna Bridge	169:a7c7b631e539	1518	__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1519	{
AnnaBridge	167:84c0a372a020	1520	uint32_t result;
AnnaBridge	167:84c0a372a020	1521
AnnaBridge	167:84c0a372a020	1522	__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1523	return(result);
AnnaBridge	167:84c0a372a020	1524	}
AnnaBridge	167:84c0a372a020	1525
Anna Bridge	169:a7c7b631e539	1526	__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1527	{
AnnaBridge	167:84c0a372a020	1528	uint32_t result;
AnnaBridge	167:84c0a372a020	1529
AnnaBridge	167:84c0a372a020	1530	__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1531	return(result);
AnnaBridge	167:84c0a372a020	1532	}
AnnaBridge	167:84c0a372a020	1533
Anna Bridge	169:a7c7b631e539	1534	__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1535	{
AnnaBridge	167:84c0a372a020	1536	uint32_t result;
AnnaBridge	167:84c0a372a020	1537
AnnaBridge	167:84c0a372a020	1538	__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1539	return(result);
AnnaBridge	167:84c0a372a020	1540	}
AnnaBridge	167:84c0a372a020	1541
Anna Bridge	169:a7c7b631e539	1542	__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1543	{
AnnaBridge	167:84c0a372a020	1544	uint32_t result;
AnnaBridge	167:84c0a372a020	1545
AnnaBridge	167:84c0a372a020	1546	__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1547	return(result);
AnnaBridge	167:84c0a372a020	1548	}
AnnaBridge	167:84c0a372a020	1549
Anna Bridge	169:a7c7b631e539	1550	__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1551	{
AnnaBridge	167:84c0a372a020	1552	uint32_t result;
AnnaBridge	167:84c0a372a020	1553
AnnaBridge	167:84c0a372a020	1554	__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1555	return(result);
AnnaBridge	167:84c0a372a020	1556	}
AnnaBridge	167:84c0a372a020	1557
Anna Bridge	169:a7c7b631e539	1558	__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1559	{
AnnaBridge	167:84c0a372a020	1560	uint32_t result;
AnnaBridge	167:84c0a372a020	1561
AnnaBridge	167:84c0a372a020	1562	__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1563	return(result);
AnnaBridge	167:84c0a372a020	1564	}
AnnaBridge	167:84c0a372a020	1565
Anna Bridge	169:a7c7b631e539	1566	__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1567	{
AnnaBridge	167:84c0a372a020	1568	uint32_t result;
AnnaBridge	167:84c0a372a020	1569
AnnaBridge	167:84c0a372a020	1570	__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1571	return(result);
AnnaBridge	167:84c0a372a020	1572	}
AnnaBridge	167:84c0a372a020	1573
Anna Bridge	169:a7c7b631e539	1574	__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1575	{
AnnaBridge	167:84c0a372a020	1576	uint32_t result;
AnnaBridge	167:84c0a372a020	1577
AnnaBridge	167:84c0a372a020	1578	__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1579	return(result);
AnnaBridge	167:84c0a372a020	1580	}
AnnaBridge	167:84c0a372a020	1581
Anna Bridge	169:a7c7b631e539	1582	__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1583	{
AnnaBridge	167:84c0a372a020	1584	uint32_t result;
AnnaBridge	167:84c0a372a020	1585
AnnaBridge	167:84c0a372a020	1586	__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1587	return(result);
AnnaBridge	167:84c0a372a020	1588	}
AnnaBridge	167:84c0a372a020	1589
Anna Bridge	169:a7c7b631e539	1590	__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1591	{
AnnaBridge	167:84c0a372a020	1592	uint32_t result;
AnnaBridge	167:84c0a372a020	1593
AnnaBridge	167:84c0a372a020	1594	__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1595	return(result);
AnnaBridge	167:84c0a372a020	1596	}
AnnaBridge	167:84c0a372a020	1597
Anna Bridge	169:a7c7b631e539	1598	__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1599	{
AnnaBridge	167:84c0a372a020	1600	uint32_t result;
AnnaBridge	167:84c0a372a020	1601
AnnaBridge	167:84c0a372a020	1602	__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1603	return(result);
AnnaBridge	167:84c0a372a020	1604	}
AnnaBridge	167:84c0a372a020	1605
Anna Bridge	169:a7c7b631e539	1606	__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1607	{
AnnaBridge	167:84c0a372a020	1608	uint32_t result;
AnnaBridge	167:84c0a372a020	1609
AnnaBridge	167:84c0a372a020	1610	__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1611	return(result);
AnnaBridge	167:84c0a372a020	1612	}
AnnaBridge	167:84c0a372a020	1613
Anna Bridge	169:a7c7b631e539	1614	__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1615	{
AnnaBridge	167:84c0a372a020	1616	uint32_t result;
AnnaBridge	167:84c0a372a020	1617
AnnaBridge	167:84c0a372a020	1618	__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1619	return(result);
AnnaBridge	167:84c0a372a020	1620	}
AnnaBridge	167:84c0a372a020	1621
Anna Bridge	169:a7c7b631e539	1622	__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1623	{
AnnaBridge	167:84c0a372a020	1624	uint32_t result;
AnnaBridge	167:84c0a372a020	1625
AnnaBridge	167:84c0a372a020	1626	__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1627	return(result);
AnnaBridge	167:84c0a372a020	1628	}
AnnaBridge	167:84c0a372a020	1629
Anna Bridge	169:a7c7b631e539	1630	__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	167:84c0a372a020	1631	{
AnnaBridge	167:84c0a372a020	1632	uint32_t result;
AnnaBridge	167:84c0a372a020	1633
AnnaBridge	167:84c0a372a020	1634	__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	167:84c0a372a020	1635	return(result);
AnnaBridge	167:84c0a372a020	1636	}
AnnaBridge	167:84c0a372a020	1637
AnnaBridge	167:84c0a372a020	1638	#define __SSAT16(ARG1,ARG2) \
AnnaBridge	167:84c0a372a020	1639	({ \
AnnaBridge	167:84c0a372a020	1640	int32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	167:84c0a372a020	1641	__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	167:84c0a372a020	1642	__RES; \
AnnaBridge	167:84c0a372a020	1643	})
AnnaBridge	167:84c0a372a020	1644
AnnaBridge	167:84c0a372a020	1645	#define __USAT16(ARG1,ARG2) \
AnnaBridge	167:84c0a372a020	1646	({ \
AnnaBridge	167:84c0a372a020	1647	uint32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	167:84c0a372a020	1648	__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	167:84c0a372a020	1649	__RES; \
AnnaBridge	167:84c0a372a020	1650	})
AnnaBridge	167:84c0a372a020	1651
Anna Bridge	169:a7c7b631e539	1652	__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
AnnaBridge	167:84c0a372a020	1653	{
AnnaBridge	167:84c0a372a020	1654	uint32_t result;
AnnaBridge	167:84c0a372a020	1655
AnnaBridge	167:84c0a372a020	1656	__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge	167:84c0a372a020	1657	return(result);
AnnaBridge	167:84c0a372a020	1658	}
AnnaBridge	167:84c0a372a020	1659
Anna Bridge	169:a7c7b631e539	1660	__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1661	{
AnnaBridge	167:84c0a372a020	1662	uint32_t result;
AnnaBridge	167:84c0a372a020	1663
AnnaBridge	167:84c0a372a020	1664	__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1665	return(result);
AnnaBridge	167:84c0a372a020	1666	}
AnnaBridge	167:84c0a372a020	1667
Anna Bridge	169:a7c7b631e539	1668	__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
AnnaBridge	167:84c0a372a020	1669	{
AnnaBridge	167:84c0a372a020	1670	uint32_t result;
AnnaBridge	167:84c0a372a020	1671
AnnaBridge	167:84c0a372a020	1672	__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge	167:84c0a372a020	1673	return(result);
AnnaBridge	167:84c0a372a020	1674	}
AnnaBridge	167:84c0a372a020	1675
Anna Bridge	169:a7c7b631e539	1676	__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1677	{
AnnaBridge	167:84c0a372a020	1678	uint32_t result;
AnnaBridge	167:84c0a372a020	1679
AnnaBridge	167:84c0a372a020	1680	__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1681	return(result);
AnnaBridge	167:84c0a372a020	1682	}
AnnaBridge	167:84c0a372a020	1683
Anna Bridge	169:a7c7b631e539	1684	__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1685	{
AnnaBridge	167:84c0a372a020	1686	uint32_t result;
AnnaBridge	167:84c0a372a020	1687
AnnaBridge	167:84c0a372a020	1688	__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1689	return(result);
AnnaBridge	167:84c0a372a020	1690	}
AnnaBridge	167:84c0a372a020	1691
Anna Bridge	169:a7c7b631e539	1692	__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1693	{
AnnaBridge	167:84c0a372a020	1694	uint32_t result;
AnnaBridge	167:84c0a372a020	1695
AnnaBridge	167:84c0a372a020	1696	__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1697	return(result);
AnnaBridge	167:84c0a372a020	1698	}
AnnaBridge	167:84c0a372a020	1699
Anna Bridge	169:a7c7b631e539	1700	__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	167:84c0a372a020	1701	{
AnnaBridge	167:84c0a372a020	1702	uint32_t result;
AnnaBridge	167:84c0a372a020	1703
AnnaBridge	167:84c0a372a020	1704	__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	167:84c0a372a020	1705	return(result);
AnnaBridge	167:84c0a372a020	1706	}
AnnaBridge	167:84c0a372a020	1707
Anna Bridge	169:a7c7b631e539	1708	__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	167:84c0a372a020	1709	{
AnnaBridge	167:84c0a372a020	1710	uint32_t result;
AnnaBridge	167:84c0a372a020	1711
AnnaBridge	167:84c0a372a020	1712	__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	167:84c0a372a020	1713	return(result);
AnnaBridge	167:84c0a372a020	1714	}
AnnaBridge	167:84c0a372a020	1715
Anna Bridge	169:a7c7b631e539	1716	__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	167:84c0a372a020	1717	{
AnnaBridge	167:84c0a372a020	1718	union llreg_u{
AnnaBridge	167:84c0a372a020	1719	uint32_t w32[2];
AnnaBridge	167:84c0a372a020	1720	uint64_t w64;
AnnaBridge	167:84c0a372a020	1721	} llr;
AnnaBridge	167:84c0a372a020	1722	llr.w64 = acc;
AnnaBridge	167:84c0a372a020	1723
AnnaBridge	167:84c0a372a020	1724	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	167:84c0a372a020	1725	__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	167:84c0a372a020	1726	#else /* Big endian */
AnnaBridge	167:84c0a372a020	1727	__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	167:84c0a372a020	1728	#endif
AnnaBridge	167:84c0a372a020	1729
AnnaBridge	167:84c0a372a020	1730	return(llr.w64);
AnnaBridge	167:84c0a372a020	1731	}
AnnaBridge	167:84c0a372a020	1732
Anna Bridge	169:a7c7b631e539	1733	__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	167:84c0a372a020	1734	{
AnnaBridge	167:84c0a372a020	1735	union llreg_u{
AnnaBridge	167:84c0a372a020	1736	uint32_t w32[2];
AnnaBridge	167:84c0a372a020	1737	uint64_t w64;
AnnaBridge	167:84c0a372a020	1738	} llr;
AnnaBridge	167:84c0a372a020	1739	llr.w64 = acc;
AnnaBridge	167:84c0a372a020	1740
AnnaBridge	167:84c0a372a020	1741	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	167:84c0a372a020	1742	__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	167:84c0a372a020	1743	#else /* Big endian */
AnnaBridge	167:84c0a372a020	1744	__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	167:84c0a372a020	1745	#endif
AnnaBridge	167:84c0a372a020	1746
AnnaBridge	167:84c0a372a020	1747	return(llr.w64);
AnnaBridge	167:84c0a372a020	1748	}
AnnaBridge	167:84c0a372a020	1749
Anna Bridge	169:a7c7b631e539	1750	__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1751	{
AnnaBridge	167:84c0a372a020	1752	uint32_t result;
AnnaBridge	167:84c0a372a020	1753
AnnaBridge	167:84c0a372a020	1754	__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1755	return(result);
AnnaBridge	167:84c0a372a020	1756	}
AnnaBridge	167:84c0a372a020	1757
Anna Bridge	169:a7c7b631e539	1758	__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1759	{
AnnaBridge	167:84c0a372a020	1760	uint32_t result;
AnnaBridge	167:84c0a372a020	1761
AnnaBridge	167:84c0a372a020	1762	__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1763	return(result);
AnnaBridge	167:84c0a372a020	1764	}
AnnaBridge	167:84c0a372a020	1765
Anna Bridge	169:a7c7b631e539	1766	__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	167:84c0a372a020	1767	{
AnnaBridge	167:84c0a372a020	1768	uint32_t result;
AnnaBridge	167:84c0a372a020	1769
AnnaBridge	167:84c0a372a020	1770	__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	167:84c0a372a020	1771	return(result);
AnnaBridge	167:84c0a372a020	1772	}
AnnaBridge	167:84c0a372a020	1773
Anna Bridge	169:a7c7b631e539	1774	__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	167:84c0a372a020	1775	{
AnnaBridge	167:84c0a372a020	1776	uint32_t result;
AnnaBridge	167:84c0a372a020	1777
AnnaBridge	167:84c0a372a020	1778	__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	167:84c0a372a020	1779	return(result);
AnnaBridge	167:84c0a372a020	1780	}
AnnaBridge	167:84c0a372a020	1781
Anna Bridge	169:a7c7b631e539	1782	__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	167:84c0a372a020	1783	{
AnnaBridge	167:84c0a372a020	1784	union llreg_u{
AnnaBridge	167:84c0a372a020	1785	uint32_t w32[2];
AnnaBridge	167:84c0a372a020	1786	uint64_t w64;
AnnaBridge	167:84c0a372a020	1787	} llr;
AnnaBridge	167:84c0a372a020	1788	llr.w64 = acc;
AnnaBridge	167:84c0a372a020	1789
AnnaBridge	167:84c0a372a020	1790	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	167:84c0a372a020	1791	__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	167:84c0a372a020	1792	#else /* Big endian */
AnnaBridge	167:84c0a372a020	1793	__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	167:84c0a372a020	1794	#endif
AnnaBridge	167:84c0a372a020	1795
AnnaBridge	167:84c0a372a020	1796	return(llr.w64);
AnnaBridge	167:84c0a372a020	1797	}
AnnaBridge	167:84c0a372a020	1798
Anna Bridge	169:a7c7b631e539	1799	__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	167:84c0a372a020	1800	{
AnnaBridge	167:84c0a372a020	1801	union llreg_u{
AnnaBridge	167:84c0a372a020	1802	uint32_t w32[2];
AnnaBridge	167:84c0a372a020	1803	uint64_t w64;
AnnaBridge	167:84c0a372a020	1804	} llr;
AnnaBridge	167:84c0a372a020	1805	llr.w64 = acc;
AnnaBridge	167:84c0a372a020	1806
AnnaBridge	167:84c0a372a020	1807	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	167:84c0a372a020	1808	__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	167:84c0a372a020	1809	#else /* Big endian */
AnnaBridge	167:84c0a372a020	1810	__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	167:84c0a372a020	1811	#endif
AnnaBridge	167:84c0a372a020	1812
AnnaBridge	167:84c0a372a020	1813	return(llr.w64);
AnnaBridge	167:84c0a372a020	1814	}
AnnaBridge	167:84c0a372a020	1815
Anna Bridge	169:a7c7b631e539	1816	__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1817	{
AnnaBridge	167:84c0a372a020	1818	uint32_t result;
AnnaBridge	167:84c0a372a020	1819
AnnaBridge	167:84c0a372a020	1820	__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1821	return(result);
AnnaBridge	167:84c0a372a020	1822	}
AnnaBridge	167:84c0a372a020	1823
Anna Bridge	169:a7c7b631e539	1824	__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
AnnaBridge	167:84c0a372a020	1825	{
AnnaBridge	167:84c0a372a020	1826	int32_t result;
AnnaBridge	167:84c0a372a020	1827
AnnaBridge	167:84c0a372a020	1828	__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1829	return(result);
AnnaBridge	167:84c0a372a020	1830	}
AnnaBridge	167:84c0a372a020	1831
Anna Bridge	169:a7c7b631e539	1832	__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
AnnaBridge	167:84c0a372a020	1833	{
AnnaBridge	167:84c0a372a020	1834	int32_t result;
AnnaBridge	167:84c0a372a020	1835
AnnaBridge	167:84c0a372a020	1836	__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1837	return(result);
AnnaBridge	167:84c0a372a020	1838	}
AnnaBridge	167:84c0a372a020	1839
AnnaBridge	167:84c0a372a020	1840	#if 0
AnnaBridge	167:84c0a372a020	1841	#define __PKHBT(ARG1,ARG2,ARG3) \
AnnaBridge	167:84c0a372a020	1842	({ \
AnnaBridge	167:84c0a372a020	1843	uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge	167:84c0a372a020	1844	__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge	167:84c0a372a020	1845	__RES; \
AnnaBridge	167:84c0a372a020	1846	})
AnnaBridge	167:84c0a372a020	1847
AnnaBridge	167:84c0a372a020	1848	#define __PKHTB(ARG1,ARG2,ARG3) \
AnnaBridge	167:84c0a372a020	1849	({ \
AnnaBridge	167:84c0a372a020	1850	uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge	167:84c0a372a020	1851	if (ARG3 == 0) \
AnnaBridge	167:84c0a372a020	1852	__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
AnnaBridge	167:84c0a372a020	1853	else \
AnnaBridge	167:84c0a372a020	1854	__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge	167:84c0a372a020	1855	__RES; \
AnnaBridge	167:84c0a372a020	1856	})
AnnaBridge	167:84c0a372a020	1857	#endif
AnnaBridge	167:84c0a372a020	1858
AnnaBridge	167:84c0a372a020	1859	#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) \| \
AnnaBridge	167:84c0a372a020	1860	((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
AnnaBridge	167:84c0a372a020	1861
AnnaBridge	167:84c0a372a020	1862	#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) \| \
AnnaBridge	167:84c0a372a020	1863	((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
AnnaBridge	167:84c0a372a020	1864
Anna Bridge	169:a7c7b631e539	1865	__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
AnnaBridge	167:84c0a372a020	1866	{
AnnaBridge	167:84c0a372a020	1867	int32_t result;
AnnaBridge	167:84c0a372a020	1868
AnnaBridge	167:84c0a372a020	1869	__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	167:84c0a372a020	1870	return(result);
AnnaBridge	167:84c0a372a020	1871	}
AnnaBridge	167:84c0a372a020	1872
AnnaBridge	167:84c0a372a020	1873	#endif /* (__ARM_FEATURE_DSP == 1) */
AnnaBridge	167:84c0a372a020	1874	/@} end of group CMSIS_SIMD_intrinsics /
AnnaBridge	167:84c0a372a020	1875
AnnaBridge	167:84c0a372a020	1876
AnnaBridge	167:84c0a372a020	1877	#endif /* __CMSIS_ARMCLANG_H */