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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

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TARGET_MAX32625PICO_NO_BOOT/core_cm4.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 15:38:59 2018 +0100
Revision:
169:a7c7b631e539
mbed library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 169:a7c7b631e539 1 /**************************************************************************//**
Anna Bridge 169:a7c7b631e539 2 * @file core_cm4.h
Anna Bridge 169:a7c7b631e539 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
Anna Bridge 169:a7c7b631e539 4 * @version V5.0.5
Anna Bridge 169:a7c7b631e539 5 * @date 08. January 2018
Anna Bridge 169:a7c7b631e539 6 ******************************************************************************/
Anna Bridge 169:a7c7b631e539 7 /*
Anna Bridge 169:a7c7b631e539 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
Anna Bridge 169:a7c7b631e539 9 *
Anna Bridge 169:a7c7b631e539 10 * SPDX-License-Identifier: Apache-2.0
Anna Bridge 169:a7c7b631e539 11 *
Anna Bridge 169:a7c7b631e539 12 * Licensed under the Apache License, Version 2.0 (the License); you may
Anna Bridge 169:a7c7b631e539 13 * not use this file except in compliance with the License.
Anna Bridge 169:a7c7b631e539 14 * You may obtain a copy of the License at
Anna Bridge 169:a7c7b631e539 15 *
Anna Bridge 169:a7c7b631e539 16 * www.apache.org/licenses/LICENSE-2.0
Anna Bridge 169:a7c7b631e539 17 *
Anna Bridge 169:a7c7b631e539 18 * Unless required by applicable law or agreed to in writing, software
Anna Bridge 169:a7c7b631e539 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Anna Bridge 169:a7c7b631e539 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Anna Bridge 169:a7c7b631e539 21 * See the License for the specific language governing permissions and
Anna Bridge 169:a7c7b631e539 22 * limitations under the License.
Anna Bridge 169:a7c7b631e539 23 */
Anna Bridge 169:a7c7b631e539 24
Anna Bridge 169:a7c7b631e539 25 #if defined ( __ICCARM__ )
Anna Bridge 169:a7c7b631e539 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 169:a7c7b631e539 27 #elif defined (__clang__)
Anna Bridge 169:a7c7b631e539 28 #pragma clang system_header /* treat file as system include file */
Anna Bridge 169:a7c7b631e539 29 #endif
Anna Bridge 169:a7c7b631e539 30
Anna Bridge 169:a7c7b631e539 31 #ifndef __CORE_CM4_H_GENERIC
Anna Bridge 169:a7c7b631e539 32 #define __CORE_CM4_H_GENERIC
Anna Bridge 169:a7c7b631e539 33
Anna Bridge 169:a7c7b631e539 34 #include <stdint.h>
Anna Bridge 169:a7c7b631e539 35
Anna Bridge 169:a7c7b631e539 36 #ifdef __cplusplus
Anna Bridge 169:a7c7b631e539 37 extern "C" {
Anna Bridge 169:a7c7b631e539 38 #endif
Anna Bridge 169:a7c7b631e539 39
Anna Bridge 169:a7c7b631e539 40 /**
Anna Bridge 169:a7c7b631e539 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Anna Bridge 169:a7c7b631e539 42 CMSIS violates the following MISRA-C:2004 rules:
Anna Bridge 169:a7c7b631e539 43
Anna Bridge 169:a7c7b631e539 44 \li Required Rule 8.5, object/function definition in header file.<br>
Anna Bridge 169:a7c7b631e539 45 Function definitions in header files are used to allow 'inlining'.
Anna Bridge 169:a7c7b631e539 46
Anna Bridge 169:a7c7b631e539 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Anna Bridge 169:a7c7b631e539 48 Unions are used for effective representation of core registers.
Anna Bridge 169:a7c7b631e539 49
Anna Bridge 169:a7c7b631e539 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
Anna Bridge 169:a7c7b631e539 51 Function-like macros are used to allow more efficient code.
Anna Bridge 169:a7c7b631e539 52 */
Anna Bridge 169:a7c7b631e539 53
Anna Bridge 169:a7c7b631e539 54
Anna Bridge 169:a7c7b631e539 55 /*******************************************************************************
Anna Bridge 169:a7c7b631e539 56 * CMSIS definitions
Anna Bridge 169:a7c7b631e539 57 ******************************************************************************/
Anna Bridge 169:a7c7b631e539 58 /**
Anna Bridge 169:a7c7b631e539 59 \ingroup Cortex_M4
Anna Bridge 169:a7c7b631e539 60 @{
Anna Bridge 169:a7c7b631e539 61 */
Anna Bridge 169:a7c7b631e539 62
Anna Bridge 169:a7c7b631e539 63 #include "cmsis_version.h"
Anna Bridge 169:a7c7b631e539 64
Anna Bridge 169:a7c7b631e539 65 /* CMSIS CM4 definitions */
Anna Bridge 169:a7c7b631e539 66 #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
Anna Bridge 169:a7c7b631e539 67 #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
Anna Bridge 169:a7c7b631e539 68 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
Anna Bridge 169:a7c7b631e539 69 __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
Anna Bridge 169:a7c7b631e539 70
Anna Bridge 169:a7c7b631e539 71 #define __CORTEX_M (4U) /*!< Cortex-M Core */
Anna Bridge 169:a7c7b631e539 72
Anna Bridge 169:a7c7b631e539 73 /** __FPU_USED indicates whether an FPU is used or not.
Anna Bridge 169:a7c7b631e539 74 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
Anna Bridge 169:a7c7b631e539 75 */
Anna Bridge 169:a7c7b631e539 76 #if defined ( __CC_ARM )
Anna Bridge 169:a7c7b631e539 77 #if defined __TARGET_FPU_VFP
Anna Bridge 169:a7c7b631e539 78 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 79 #define __FPU_USED 1U
Anna Bridge 169:a7c7b631e539 80 #else
Anna Bridge 169:a7c7b631e539 81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 169:a7c7b631e539 82 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 83 #endif
Anna Bridge 169:a7c7b631e539 84 #else
Anna Bridge 169:a7c7b631e539 85 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 86 #endif
Anna Bridge 169:a7c7b631e539 87
Anna Bridge 169:a7c7b631e539 88 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
Anna Bridge 169:a7c7b631e539 89 #if defined __ARM_PCS_VFP
Anna Bridge 169:a7c7b631e539 90 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 91 #define __FPU_USED 1U
Anna Bridge 169:a7c7b631e539 92 #else
Anna Bridge 169:a7c7b631e539 93 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 169:a7c7b631e539 94 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 95 #endif
Anna Bridge 169:a7c7b631e539 96 #else
Anna Bridge 169:a7c7b631e539 97 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 98 #endif
Anna Bridge 169:a7c7b631e539 99
Anna Bridge 169:a7c7b631e539 100 #elif defined ( __GNUC__ )
Anna Bridge 169:a7c7b631e539 101 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Anna Bridge 169:a7c7b631e539 102 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 103 #define __FPU_USED 1U
Anna Bridge 169:a7c7b631e539 104 #else
Anna Bridge 169:a7c7b631e539 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 169:a7c7b631e539 106 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 107 #endif
Anna Bridge 169:a7c7b631e539 108 #else
Anna Bridge 169:a7c7b631e539 109 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 110 #endif
Anna Bridge 169:a7c7b631e539 111
Anna Bridge 169:a7c7b631e539 112 #elif defined ( __ICCARM__ )
Anna Bridge 169:a7c7b631e539 113 #if defined __ARMVFP__
Anna Bridge 169:a7c7b631e539 114 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 115 #define __FPU_USED 1U
Anna Bridge 169:a7c7b631e539 116 #else
Anna Bridge 169:a7c7b631e539 117 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 169:a7c7b631e539 118 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 119 #endif
Anna Bridge 169:a7c7b631e539 120 #else
Anna Bridge 169:a7c7b631e539 121 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 122 #endif
Anna Bridge 169:a7c7b631e539 123
Anna Bridge 169:a7c7b631e539 124 #elif defined ( __TI_ARM__ )
Anna Bridge 169:a7c7b631e539 125 #if defined __TI_VFP_SUPPORT__
Anna Bridge 169:a7c7b631e539 126 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 127 #define __FPU_USED 1U
Anna Bridge 169:a7c7b631e539 128 #else
Anna Bridge 169:a7c7b631e539 129 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 169:a7c7b631e539 130 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 131 #endif
Anna Bridge 169:a7c7b631e539 132 #else
Anna Bridge 169:a7c7b631e539 133 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 134 #endif
Anna Bridge 169:a7c7b631e539 135
Anna Bridge 169:a7c7b631e539 136 #elif defined ( __TASKING__ )
Anna Bridge 169:a7c7b631e539 137 #if defined __FPU_VFP__
Anna Bridge 169:a7c7b631e539 138 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 139 #define __FPU_USED 1U
Anna Bridge 169:a7c7b631e539 140 #else
Anna Bridge 169:a7c7b631e539 141 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 169:a7c7b631e539 142 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 143 #endif
Anna Bridge 169:a7c7b631e539 144 #else
Anna Bridge 169:a7c7b631e539 145 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 146 #endif
Anna Bridge 169:a7c7b631e539 147
Anna Bridge 169:a7c7b631e539 148 #elif defined ( __CSMC__ )
Anna Bridge 169:a7c7b631e539 149 #if ( __CSMC__ & 0x400U)
Anna Bridge 169:a7c7b631e539 150 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 151 #define __FPU_USED 1U
Anna Bridge 169:a7c7b631e539 152 #else
Anna Bridge 169:a7c7b631e539 153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 169:a7c7b631e539 154 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 155 #endif
Anna Bridge 169:a7c7b631e539 156 #else
Anna Bridge 169:a7c7b631e539 157 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 158 #endif
Anna Bridge 169:a7c7b631e539 159
Anna Bridge 169:a7c7b631e539 160 #endif
Anna Bridge 169:a7c7b631e539 161
Anna Bridge 169:a7c7b631e539 162 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
Anna Bridge 169:a7c7b631e539 163
Anna Bridge 169:a7c7b631e539 164
Anna Bridge 169:a7c7b631e539 165 #ifdef __cplusplus
Anna Bridge 169:a7c7b631e539 166 }
Anna Bridge 169:a7c7b631e539 167 #endif
Anna Bridge 169:a7c7b631e539 168
Anna Bridge 169:a7c7b631e539 169 #endif /* __CORE_CM4_H_GENERIC */
Anna Bridge 169:a7c7b631e539 170
Anna Bridge 169:a7c7b631e539 171 #ifndef __CMSIS_GENERIC
Anna Bridge 169:a7c7b631e539 172
Anna Bridge 169:a7c7b631e539 173 #ifndef __CORE_CM4_H_DEPENDANT
Anna Bridge 169:a7c7b631e539 174 #define __CORE_CM4_H_DEPENDANT
Anna Bridge 169:a7c7b631e539 175
Anna Bridge 169:a7c7b631e539 176 #ifdef __cplusplus
Anna Bridge 169:a7c7b631e539 177 extern "C" {
Anna Bridge 169:a7c7b631e539 178 #endif
Anna Bridge 169:a7c7b631e539 179
Anna Bridge 169:a7c7b631e539 180 /* check device defines and use defaults */
Anna Bridge 169:a7c7b631e539 181 #if defined __CHECK_DEVICE_DEFINES
Anna Bridge 169:a7c7b631e539 182 #ifndef __CM4_REV
Anna Bridge 169:a7c7b631e539 183 #define __CM4_REV 0x0000U
Anna Bridge 169:a7c7b631e539 184 #warning "__CM4_REV not defined in device header file; using default!"
Anna Bridge 169:a7c7b631e539 185 #endif
Anna Bridge 169:a7c7b631e539 186
Anna Bridge 169:a7c7b631e539 187 #ifndef __FPU_PRESENT
Anna Bridge 169:a7c7b631e539 188 #define __FPU_PRESENT 0U
Anna Bridge 169:a7c7b631e539 189 #warning "__FPU_PRESENT not defined in device header file; using default!"
Anna Bridge 169:a7c7b631e539 190 #endif
Anna Bridge 169:a7c7b631e539 191
Anna Bridge 169:a7c7b631e539 192 #ifndef __MPU_PRESENT
Anna Bridge 169:a7c7b631e539 193 #define __MPU_PRESENT 0U
Anna Bridge 169:a7c7b631e539 194 #warning "__MPU_PRESENT not defined in device header file; using default!"
Anna Bridge 169:a7c7b631e539 195 #endif
Anna Bridge 169:a7c7b631e539 196
Anna Bridge 169:a7c7b631e539 197 #ifndef __NVIC_PRIO_BITS
Anna Bridge 169:a7c7b631e539 198 #define __NVIC_PRIO_BITS 3U
Anna Bridge 169:a7c7b631e539 199 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Anna Bridge 169:a7c7b631e539 200 #endif
Anna Bridge 169:a7c7b631e539 201
Anna Bridge 169:a7c7b631e539 202 #ifndef __Vendor_SysTickConfig
Anna Bridge 169:a7c7b631e539 203 #define __Vendor_SysTickConfig 0U
Anna Bridge 169:a7c7b631e539 204 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Anna Bridge 169:a7c7b631e539 205 #endif
Anna Bridge 169:a7c7b631e539 206 #endif
Anna Bridge 169:a7c7b631e539 207
Anna Bridge 169:a7c7b631e539 208 /* IO definitions (access restrictions to peripheral registers) */
Anna Bridge 169:a7c7b631e539 209 /**
Anna Bridge 169:a7c7b631e539 210 \defgroup CMSIS_glob_defs CMSIS Global Defines
Anna Bridge 169:a7c7b631e539 211
Anna Bridge 169:a7c7b631e539 212 <strong>IO Type Qualifiers</strong> are used
Anna Bridge 169:a7c7b631e539 213 \li to specify the access to peripheral variables.
Anna Bridge 169:a7c7b631e539 214 \li for automatic generation of peripheral register debug information.
Anna Bridge 169:a7c7b631e539 215 */
Anna Bridge 169:a7c7b631e539 216 #ifdef __cplusplus
Anna Bridge 169:a7c7b631e539 217 #define __I volatile /*!< Defines 'read only' permissions */
Anna Bridge 169:a7c7b631e539 218 #else
Anna Bridge 169:a7c7b631e539 219 #define __I volatile const /*!< Defines 'read only' permissions */
Anna Bridge 169:a7c7b631e539 220 #endif
Anna Bridge 169:a7c7b631e539 221 #define __O volatile /*!< Defines 'write only' permissions */
Anna Bridge 169:a7c7b631e539 222 #define __IO volatile /*!< Defines 'read / write' permissions */
Anna Bridge 169:a7c7b631e539 223
Anna Bridge 169:a7c7b631e539 224 /* following defines should be used for structure members */
Anna Bridge 169:a7c7b631e539 225 #define __IM volatile const /*! Defines 'read only' structure member permissions */
Anna Bridge 169:a7c7b631e539 226 #define __OM volatile /*! Defines 'write only' structure member permissions */
Anna Bridge 169:a7c7b631e539 227 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
Anna Bridge 169:a7c7b631e539 228
Anna Bridge 169:a7c7b631e539 229 /*@} end of group Cortex_M4 */
Anna Bridge 169:a7c7b631e539 230
Anna Bridge 169:a7c7b631e539 231
Anna Bridge 169:a7c7b631e539 232
Anna Bridge 169:a7c7b631e539 233 /*******************************************************************************
Anna Bridge 169:a7c7b631e539 234 * Register Abstraction
Anna Bridge 169:a7c7b631e539 235 Core Register contain:
Anna Bridge 169:a7c7b631e539 236 - Core Register
Anna Bridge 169:a7c7b631e539 237 - Core NVIC Register
Anna Bridge 169:a7c7b631e539 238 - Core SCB Register
Anna Bridge 169:a7c7b631e539 239 - Core SysTick Register
Anna Bridge 169:a7c7b631e539 240 - Core Debug Register
Anna Bridge 169:a7c7b631e539 241 - Core MPU Register
Anna Bridge 169:a7c7b631e539 242 - Core FPU Register
Anna Bridge 169:a7c7b631e539 243 ******************************************************************************/
Anna Bridge 169:a7c7b631e539 244 /**
Anna Bridge 169:a7c7b631e539 245 \defgroup CMSIS_core_register Defines and Type Definitions
Anna Bridge 169:a7c7b631e539 246 \brief Type definitions and defines for Cortex-M processor based devices.
Anna Bridge 169:a7c7b631e539 247 */
Anna Bridge 169:a7c7b631e539 248
Anna Bridge 169:a7c7b631e539 249 /**
Anna Bridge 169:a7c7b631e539 250 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 251 \defgroup CMSIS_CORE Status and Control Registers
Anna Bridge 169:a7c7b631e539 252 \brief Core Register type definitions.
Anna Bridge 169:a7c7b631e539 253 @{
Anna Bridge 169:a7c7b631e539 254 */
Anna Bridge 169:a7c7b631e539 255
Anna Bridge 169:a7c7b631e539 256 /**
Anna Bridge 169:a7c7b631e539 257 \brief Union type to access the Application Program Status Register (APSR).
Anna Bridge 169:a7c7b631e539 258 */
Anna Bridge 169:a7c7b631e539 259 typedef union
Anna Bridge 169:a7c7b631e539 260 {
Anna Bridge 169:a7c7b631e539 261 struct
Anna Bridge 169:a7c7b631e539 262 {
Anna Bridge 169:a7c7b631e539 263 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
Anna Bridge 169:a7c7b631e539 264 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Anna Bridge 169:a7c7b631e539 265 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
Anna Bridge 169:a7c7b631e539 266 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Anna Bridge 169:a7c7b631e539 267 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Anna Bridge 169:a7c7b631e539 268 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Anna Bridge 169:a7c7b631e539 269 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Anna Bridge 169:a7c7b631e539 270 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Anna Bridge 169:a7c7b631e539 271 } b; /*!< Structure used for bit access */
Anna Bridge 169:a7c7b631e539 272 uint32_t w; /*!< Type used for word access */
Anna Bridge 169:a7c7b631e539 273 } APSR_Type;
Anna Bridge 169:a7c7b631e539 274
Anna Bridge 169:a7c7b631e539 275 /* APSR Register Definitions */
Anna Bridge 169:a7c7b631e539 276 #define APSR_N_Pos 31U /*!< APSR: N Position */
Anna Bridge 169:a7c7b631e539 277 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Anna Bridge 169:a7c7b631e539 278
Anna Bridge 169:a7c7b631e539 279 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
Anna Bridge 169:a7c7b631e539 280 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Anna Bridge 169:a7c7b631e539 281
Anna Bridge 169:a7c7b631e539 282 #define APSR_C_Pos 29U /*!< APSR: C Position */
Anna Bridge 169:a7c7b631e539 283 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Anna Bridge 169:a7c7b631e539 284
Anna Bridge 169:a7c7b631e539 285 #define APSR_V_Pos 28U /*!< APSR: V Position */
Anna Bridge 169:a7c7b631e539 286 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Anna Bridge 169:a7c7b631e539 287
Anna Bridge 169:a7c7b631e539 288 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
Anna Bridge 169:a7c7b631e539 289 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
Anna Bridge 169:a7c7b631e539 290
Anna Bridge 169:a7c7b631e539 291 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
Anna Bridge 169:a7c7b631e539 292 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
Anna Bridge 169:a7c7b631e539 293
Anna Bridge 169:a7c7b631e539 294
Anna Bridge 169:a7c7b631e539 295 /**
Anna Bridge 169:a7c7b631e539 296 \brief Union type to access the Interrupt Program Status Register (IPSR).
Anna Bridge 169:a7c7b631e539 297 */
Anna Bridge 169:a7c7b631e539 298 typedef union
Anna Bridge 169:a7c7b631e539 299 {
Anna Bridge 169:a7c7b631e539 300 struct
Anna Bridge 169:a7c7b631e539 301 {
Anna Bridge 169:a7c7b631e539 302 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Anna Bridge 169:a7c7b631e539 303 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Anna Bridge 169:a7c7b631e539 304 } b; /*!< Structure used for bit access */
Anna Bridge 169:a7c7b631e539 305 uint32_t w; /*!< Type used for word access */
Anna Bridge 169:a7c7b631e539 306 } IPSR_Type;
Anna Bridge 169:a7c7b631e539 307
Anna Bridge 169:a7c7b631e539 308 /* IPSR Register Definitions */
Anna Bridge 169:a7c7b631e539 309 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
Anna Bridge 169:a7c7b631e539 310 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Anna Bridge 169:a7c7b631e539 311
Anna Bridge 169:a7c7b631e539 312
Anna Bridge 169:a7c7b631e539 313 /**
Anna Bridge 169:a7c7b631e539 314 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Anna Bridge 169:a7c7b631e539 315 */
Anna Bridge 169:a7c7b631e539 316 typedef union
Anna Bridge 169:a7c7b631e539 317 {
Anna Bridge 169:a7c7b631e539 318 struct
Anna Bridge 169:a7c7b631e539 319 {
Anna Bridge 169:a7c7b631e539 320 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Anna Bridge 169:a7c7b631e539 321 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
Anna Bridge 169:a7c7b631e539 322 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
Anna Bridge 169:a7c7b631e539 323 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Anna Bridge 169:a7c7b631e539 324 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
Anna Bridge 169:a7c7b631e539 325 uint32_t T:1; /*!< bit: 24 Thumb bit */
Anna Bridge 169:a7c7b631e539 326 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
Anna Bridge 169:a7c7b631e539 327 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Anna Bridge 169:a7c7b631e539 328 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Anna Bridge 169:a7c7b631e539 329 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Anna Bridge 169:a7c7b631e539 330 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Anna Bridge 169:a7c7b631e539 331 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Anna Bridge 169:a7c7b631e539 332 } b; /*!< Structure used for bit access */
Anna Bridge 169:a7c7b631e539 333 uint32_t w; /*!< Type used for word access */
Anna Bridge 169:a7c7b631e539 334 } xPSR_Type;
Anna Bridge 169:a7c7b631e539 335
Anna Bridge 169:a7c7b631e539 336 /* xPSR Register Definitions */
Anna Bridge 169:a7c7b631e539 337 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
Anna Bridge 169:a7c7b631e539 338 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Anna Bridge 169:a7c7b631e539 339
Anna Bridge 169:a7c7b631e539 340 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
Anna Bridge 169:a7c7b631e539 341 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Anna Bridge 169:a7c7b631e539 342
Anna Bridge 169:a7c7b631e539 343 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
Anna Bridge 169:a7c7b631e539 344 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Anna Bridge 169:a7c7b631e539 345
Anna Bridge 169:a7c7b631e539 346 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
Anna Bridge 169:a7c7b631e539 347 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Anna Bridge 169:a7c7b631e539 348
Anna Bridge 169:a7c7b631e539 349 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
Anna Bridge 169:a7c7b631e539 350 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
Anna Bridge 169:a7c7b631e539 351
Anna Bridge 169:a7c7b631e539 352 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
Anna Bridge 169:a7c7b631e539 353 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
Anna Bridge 169:a7c7b631e539 354
Anna Bridge 169:a7c7b631e539 355 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
Anna Bridge 169:a7c7b631e539 356 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Anna Bridge 169:a7c7b631e539 357
Anna Bridge 169:a7c7b631e539 358 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
Anna Bridge 169:a7c7b631e539 359 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
Anna Bridge 169:a7c7b631e539 360
Anna Bridge 169:a7c7b631e539 361 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
Anna Bridge 169:a7c7b631e539 362 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
Anna Bridge 169:a7c7b631e539 363
Anna Bridge 169:a7c7b631e539 364 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
Anna Bridge 169:a7c7b631e539 365 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Anna Bridge 169:a7c7b631e539 366
Anna Bridge 169:a7c7b631e539 367
Anna Bridge 169:a7c7b631e539 368 /**
Anna Bridge 169:a7c7b631e539 369 \brief Union type to access the Control Registers (CONTROL).
Anna Bridge 169:a7c7b631e539 370 */
Anna Bridge 169:a7c7b631e539 371 typedef union
Anna Bridge 169:a7c7b631e539 372 {
Anna Bridge 169:a7c7b631e539 373 struct
Anna Bridge 169:a7c7b631e539 374 {
Anna Bridge 169:a7c7b631e539 375 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Anna Bridge 169:a7c7b631e539 376 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Anna Bridge 169:a7c7b631e539 377 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
Anna Bridge 169:a7c7b631e539 378 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
Anna Bridge 169:a7c7b631e539 379 } b; /*!< Structure used for bit access */
Anna Bridge 169:a7c7b631e539 380 uint32_t w; /*!< Type used for word access */
Anna Bridge 169:a7c7b631e539 381 } CONTROL_Type;
Anna Bridge 169:a7c7b631e539 382
Anna Bridge 169:a7c7b631e539 383 /* CONTROL Register Definitions */
Anna Bridge 169:a7c7b631e539 384 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
Anna Bridge 169:a7c7b631e539 385 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
Anna Bridge 169:a7c7b631e539 386
Anna Bridge 169:a7c7b631e539 387 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
Anna Bridge 169:a7c7b631e539 388 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Anna Bridge 169:a7c7b631e539 389
Anna Bridge 169:a7c7b631e539 390 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
Anna Bridge 169:a7c7b631e539 391 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Anna Bridge 169:a7c7b631e539 392
Anna Bridge 169:a7c7b631e539 393 /*@} end of group CMSIS_CORE */
Anna Bridge 169:a7c7b631e539 394
Anna Bridge 169:a7c7b631e539 395
Anna Bridge 169:a7c7b631e539 396 /**
Anna Bridge 169:a7c7b631e539 397 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 398 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Anna Bridge 169:a7c7b631e539 399 \brief Type definitions for the NVIC Registers
Anna Bridge 169:a7c7b631e539 400 @{
Anna Bridge 169:a7c7b631e539 401 */
Anna Bridge 169:a7c7b631e539 402
Anna Bridge 169:a7c7b631e539 403 /**
Anna Bridge 169:a7c7b631e539 404 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Anna Bridge 169:a7c7b631e539 405 */
Anna Bridge 169:a7c7b631e539 406 typedef struct
Anna Bridge 169:a7c7b631e539 407 {
Anna Bridge 169:a7c7b631e539 408 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Anna Bridge 169:a7c7b631e539 409 uint32_t RESERVED0[24U];
Anna Bridge 169:a7c7b631e539 410 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Anna Bridge 169:a7c7b631e539 411 uint32_t RSERVED1[24U];
Anna Bridge 169:a7c7b631e539 412 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Anna Bridge 169:a7c7b631e539 413 uint32_t RESERVED2[24U];
Anna Bridge 169:a7c7b631e539 414 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Anna Bridge 169:a7c7b631e539 415 uint32_t RESERVED3[24U];
Anna Bridge 169:a7c7b631e539 416 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
Anna Bridge 169:a7c7b631e539 417 uint32_t RESERVED4[56U];
Anna Bridge 169:a7c7b631e539 418 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
Anna Bridge 169:a7c7b631e539 419 uint32_t RESERVED5[644U];
Anna Bridge 169:a7c7b631e539 420 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
Anna Bridge 169:a7c7b631e539 421 } NVIC_Type;
Anna Bridge 169:a7c7b631e539 422
Anna Bridge 169:a7c7b631e539 423 /* Software Triggered Interrupt Register Definitions */
Anna Bridge 169:a7c7b631e539 424 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
Anna Bridge 169:a7c7b631e539 425 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
Anna Bridge 169:a7c7b631e539 426
Anna Bridge 169:a7c7b631e539 427 /*@} end of group CMSIS_NVIC */
Anna Bridge 169:a7c7b631e539 428
Anna Bridge 169:a7c7b631e539 429
Anna Bridge 169:a7c7b631e539 430 /**
Anna Bridge 169:a7c7b631e539 431 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 432 \defgroup CMSIS_SCB System Control Block (SCB)
Anna Bridge 169:a7c7b631e539 433 \brief Type definitions for the System Control Block Registers
Anna Bridge 169:a7c7b631e539 434 @{
Anna Bridge 169:a7c7b631e539 435 */
Anna Bridge 169:a7c7b631e539 436
Anna Bridge 169:a7c7b631e539 437 /**
Anna Bridge 169:a7c7b631e539 438 \brief Structure type to access the System Control Block (SCB).
Anna Bridge 169:a7c7b631e539 439 */
Anna Bridge 169:a7c7b631e539 440 typedef struct
Anna Bridge 169:a7c7b631e539 441 {
Anna Bridge 169:a7c7b631e539 442 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Anna Bridge 169:a7c7b631e539 443 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Anna Bridge 169:a7c7b631e539 444 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Anna Bridge 169:a7c7b631e539 445 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Anna Bridge 169:a7c7b631e539 446 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Anna Bridge 169:a7c7b631e539 447 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Anna Bridge 169:a7c7b631e539 448 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
Anna Bridge 169:a7c7b631e539 449 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Anna Bridge 169:a7c7b631e539 450 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
Anna Bridge 169:a7c7b631e539 451 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
Anna Bridge 169:a7c7b631e539 452 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
Anna Bridge 169:a7c7b631e539 453 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
Anna Bridge 169:a7c7b631e539 454 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
Anna Bridge 169:a7c7b631e539 455 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
Anna Bridge 169:a7c7b631e539 456 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
Anna Bridge 169:a7c7b631e539 457 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
Anna Bridge 169:a7c7b631e539 458 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
Anna Bridge 169:a7c7b631e539 459 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
Anna Bridge 169:a7c7b631e539 460 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
Anna Bridge 169:a7c7b631e539 461 uint32_t RESERVED0[5U];
Anna Bridge 169:a7c7b631e539 462 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
Anna Bridge 169:a7c7b631e539 463 } SCB_Type;
Anna Bridge 169:a7c7b631e539 464
Anna Bridge 169:a7c7b631e539 465 /* SCB CPUID Register Definitions */
Anna Bridge 169:a7c7b631e539 466 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
Anna Bridge 169:a7c7b631e539 467 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Anna Bridge 169:a7c7b631e539 468
Anna Bridge 169:a7c7b631e539 469 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
Anna Bridge 169:a7c7b631e539 470 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Anna Bridge 169:a7c7b631e539 471
Anna Bridge 169:a7c7b631e539 472 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
Anna Bridge 169:a7c7b631e539 473 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Anna Bridge 169:a7c7b631e539 474
Anna Bridge 169:a7c7b631e539 475 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
Anna Bridge 169:a7c7b631e539 476 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Anna Bridge 169:a7c7b631e539 477
Anna Bridge 169:a7c7b631e539 478 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
Anna Bridge 169:a7c7b631e539 479 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Anna Bridge 169:a7c7b631e539 480
Anna Bridge 169:a7c7b631e539 481 /* SCB Interrupt Control State Register Definitions */
Anna Bridge 169:a7c7b631e539 482 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
Anna Bridge 169:a7c7b631e539 483 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Anna Bridge 169:a7c7b631e539 484
Anna Bridge 169:a7c7b631e539 485 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
Anna Bridge 169:a7c7b631e539 486 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Anna Bridge 169:a7c7b631e539 487
Anna Bridge 169:a7c7b631e539 488 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
Anna Bridge 169:a7c7b631e539 489 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Anna Bridge 169:a7c7b631e539 490
Anna Bridge 169:a7c7b631e539 491 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
Anna Bridge 169:a7c7b631e539 492 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Anna Bridge 169:a7c7b631e539 493
Anna Bridge 169:a7c7b631e539 494 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
Anna Bridge 169:a7c7b631e539 495 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Anna Bridge 169:a7c7b631e539 496
Anna Bridge 169:a7c7b631e539 497 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
Anna Bridge 169:a7c7b631e539 498 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Anna Bridge 169:a7c7b631e539 499
Anna Bridge 169:a7c7b631e539 500 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
Anna Bridge 169:a7c7b631e539 501 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Anna Bridge 169:a7c7b631e539 502
Anna Bridge 169:a7c7b631e539 503 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
Anna Bridge 169:a7c7b631e539 504 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Anna Bridge 169:a7c7b631e539 505
Anna Bridge 169:a7c7b631e539 506 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
Anna Bridge 169:a7c7b631e539 507 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
Anna Bridge 169:a7c7b631e539 508
Anna Bridge 169:a7c7b631e539 509 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
Anna Bridge 169:a7c7b631e539 510 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Anna Bridge 169:a7c7b631e539 511
Anna Bridge 169:a7c7b631e539 512 /* SCB Vector Table Offset Register Definitions */
Anna Bridge 169:a7c7b631e539 513 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
Anna Bridge 169:a7c7b631e539 514 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Anna Bridge 169:a7c7b631e539 515
Anna Bridge 169:a7c7b631e539 516 /* SCB Application Interrupt and Reset Control Register Definitions */
Anna Bridge 169:a7c7b631e539 517 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
Anna Bridge 169:a7c7b631e539 518 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Anna Bridge 169:a7c7b631e539 519
Anna Bridge 169:a7c7b631e539 520 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
Anna Bridge 169:a7c7b631e539 521 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Anna Bridge 169:a7c7b631e539 522
Anna Bridge 169:a7c7b631e539 523 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
Anna Bridge 169:a7c7b631e539 524 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Anna Bridge 169:a7c7b631e539 525
Anna Bridge 169:a7c7b631e539 526 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
Anna Bridge 169:a7c7b631e539 527 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
Anna Bridge 169:a7c7b631e539 528
Anna Bridge 169:a7c7b631e539 529 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
Anna Bridge 169:a7c7b631e539 530 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Anna Bridge 169:a7c7b631e539 531
Anna Bridge 169:a7c7b631e539 532 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
Anna Bridge 169:a7c7b631e539 533 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Anna Bridge 169:a7c7b631e539 534
Anna Bridge 169:a7c7b631e539 535 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
Anna Bridge 169:a7c7b631e539 536 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
Anna Bridge 169:a7c7b631e539 537
Anna Bridge 169:a7c7b631e539 538 /* SCB System Control Register Definitions */
Anna Bridge 169:a7c7b631e539 539 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
Anna Bridge 169:a7c7b631e539 540 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Anna Bridge 169:a7c7b631e539 541
Anna Bridge 169:a7c7b631e539 542 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
Anna Bridge 169:a7c7b631e539 543 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Anna Bridge 169:a7c7b631e539 544
Anna Bridge 169:a7c7b631e539 545 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
Anna Bridge 169:a7c7b631e539 546 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Anna Bridge 169:a7c7b631e539 547
Anna Bridge 169:a7c7b631e539 548 /* SCB Configuration Control Register Definitions */
Anna Bridge 169:a7c7b631e539 549 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
Anna Bridge 169:a7c7b631e539 550 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Anna Bridge 169:a7c7b631e539 551
Anna Bridge 169:a7c7b631e539 552 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
Anna Bridge 169:a7c7b631e539 553 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
Anna Bridge 169:a7c7b631e539 554
Anna Bridge 169:a7c7b631e539 555 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
Anna Bridge 169:a7c7b631e539 556 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
Anna Bridge 169:a7c7b631e539 557
Anna Bridge 169:a7c7b631e539 558 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
Anna Bridge 169:a7c7b631e539 559 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Anna Bridge 169:a7c7b631e539 560
Anna Bridge 169:a7c7b631e539 561 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
Anna Bridge 169:a7c7b631e539 562 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
Anna Bridge 169:a7c7b631e539 563
Anna Bridge 169:a7c7b631e539 564 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
Anna Bridge 169:a7c7b631e539 565 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
Anna Bridge 169:a7c7b631e539 566
Anna Bridge 169:a7c7b631e539 567 /* SCB System Handler Control and State Register Definitions */
Anna Bridge 169:a7c7b631e539 568 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
Anna Bridge 169:a7c7b631e539 569 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
Anna Bridge 169:a7c7b631e539 570
Anna Bridge 169:a7c7b631e539 571 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
Anna Bridge 169:a7c7b631e539 572 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
Anna Bridge 169:a7c7b631e539 573
Anna Bridge 169:a7c7b631e539 574 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
Anna Bridge 169:a7c7b631e539 575 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
Anna Bridge 169:a7c7b631e539 576
Anna Bridge 169:a7c7b631e539 577 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
Anna Bridge 169:a7c7b631e539 578 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Anna Bridge 169:a7c7b631e539 579
Anna Bridge 169:a7c7b631e539 580 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
Anna Bridge 169:a7c7b631e539 581 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
Anna Bridge 169:a7c7b631e539 582
Anna Bridge 169:a7c7b631e539 583 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
Anna Bridge 169:a7c7b631e539 584 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
Anna Bridge 169:a7c7b631e539 585
Anna Bridge 169:a7c7b631e539 586 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
Anna Bridge 169:a7c7b631e539 587 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
Anna Bridge 169:a7c7b631e539 588
Anna Bridge 169:a7c7b631e539 589 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
Anna Bridge 169:a7c7b631e539 590 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
Anna Bridge 169:a7c7b631e539 591
Anna Bridge 169:a7c7b631e539 592 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
Anna Bridge 169:a7c7b631e539 593 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
Anna Bridge 169:a7c7b631e539 594
Anna Bridge 169:a7c7b631e539 595 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
Anna Bridge 169:a7c7b631e539 596 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
Anna Bridge 169:a7c7b631e539 597
Anna Bridge 169:a7c7b631e539 598 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
Anna Bridge 169:a7c7b631e539 599 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
Anna Bridge 169:a7c7b631e539 600
Anna Bridge 169:a7c7b631e539 601 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
Anna Bridge 169:a7c7b631e539 602 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
Anna Bridge 169:a7c7b631e539 603
Anna Bridge 169:a7c7b631e539 604 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
Anna Bridge 169:a7c7b631e539 605 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
Anna Bridge 169:a7c7b631e539 606
Anna Bridge 169:a7c7b631e539 607 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
Anna Bridge 169:a7c7b631e539 608 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
Anna Bridge 169:a7c7b631e539 609
Anna Bridge 169:a7c7b631e539 610 /* SCB Configurable Fault Status Register Definitions */
Anna Bridge 169:a7c7b631e539 611 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
Anna Bridge 169:a7c7b631e539 612 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
Anna Bridge 169:a7c7b631e539 613
Anna Bridge 169:a7c7b631e539 614 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
Anna Bridge 169:a7c7b631e539 615 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
Anna Bridge 169:a7c7b631e539 616
Anna Bridge 169:a7c7b631e539 617 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
Anna Bridge 169:a7c7b631e539 618 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
Anna Bridge 169:a7c7b631e539 619
Anna Bridge 169:a7c7b631e539 620 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
Anna Bridge 169:a7c7b631e539 621 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
Anna Bridge 169:a7c7b631e539 622 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
Anna Bridge 169:a7c7b631e539 623
Anna Bridge 169:a7c7b631e539 624 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
Anna Bridge 169:a7c7b631e539 625 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
Anna Bridge 169:a7c7b631e539 626
Anna Bridge 169:a7c7b631e539 627 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
Anna Bridge 169:a7c7b631e539 628 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
Anna Bridge 169:a7c7b631e539 629
Anna Bridge 169:a7c7b631e539 630 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
Anna Bridge 169:a7c7b631e539 631 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
Anna Bridge 169:a7c7b631e539 632
Anna Bridge 169:a7c7b631e539 633 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
Anna Bridge 169:a7c7b631e539 634 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
Anna Bridge 169:a7c7b631e539 635
Anna Bridge 169:a7c7b631e539 636 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
Anna Bridge 169:a7c7b631e539 637 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
Anna Bridge 169:a7c7b631e539 638
Anna Bridge 169:a7c7b631e539 639 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
Anna Bridge 169:a7c7b631e539 640 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
Anna Bridge 169:a7c7b631e539 641 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
Anna Bridge 169:a7c7b631e539 642
Anna Bridge 169:a7c7b631e539 643 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
Anna Bridge 169:a7c7b631e539 644 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
Anna Bridge 169:a7c7b631e539 645
Anna Bridge 169:a7c7b631e539 646 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
Anna Bridge 169:a7c7b631e539 647 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
Anna Bridge 169:a7c7b631e539 648
Anna Bridge 169:a7c7b631e539 649 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
Anna Bridge 169:a7c7b631e539 650 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
Anna Bridge 169:a7c7b631e539 651
Anna Bridge 169:a7c7b631e539 652 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
Anna Bridge 169:a7c7b631e539 653 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
Anna Bridge 169:a7c7b631e539 654
Anna Bridge 169:a7c7b631e539 655 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
Anna Bridge 169:a7c7b631e539 656 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
Anna Bridge 169:a7c7b631e539 657
Anna Bridge 169:a7c7b631e539 658 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
Anna Bridge 169:a7c7b631e539 659 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
Anna Bridge 169:a7c7b631e539 660
Anna Bridge 169:a7c7b631e539 661 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
Anna Bridge 169:a7c7b631e539 662 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
Anna Bridge 169:a7c7b631e539 663 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
Anna Bridge 169:a7c7b631e539 664
Anna Bridge 169:a7c7b631e539 665 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
Anna Bridge 169:a7c7b631e539 666 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
Anna Bridge 169:a7c7b631e539 667
Anna Bridge 169:a7c7b631e539 668 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
Anna Bridge 169:a7c7b631e539 669 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
Anna Bridge 169:a7c7b631e539 670
Anna Bridge 169:a7c7b631e539 671 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
Anna Bridge 169:a7c7b631e539 672 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
Anna Bridge 169:a7c7b631e539 673
Anna Bridge 169:a7c7b631e539 674 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
Anna Bridge 169:a7c7b631e539 675 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
Anna Bridge 169:a7c7b631e539 676
Anna Bridge 169:a7c7b631e539 677 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
Anna Bridge 169:a7c7b631e539 678 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
Anna Bridge 169:a7c7b631e539 679
Anna Bridge 169:a7c7b631e539 680 /* SCB Hard Fault Status Register Definitions */
Anna Bridge 169:a7c7b631e539 681 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
Anna Bridge 169:a7c7b631e539 682 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
Anna Bridge 169:a7c7b631e539 683
Anna Bridge 169:a7c7b631e539 684 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
Anna Bridge 169:a7c7b631e539 685 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
Anna Bridge 169:a7c7b631e539 686
Anna Bridge 169:a7c7b631e539 687 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
Anna Bridge 169:a7c7b631e539 688 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
Anna Bridge 169:a7c7b631e539 689
Anna Bridge 169:a7c7b631e539 690 /* SCB Debug Fault Status Register Definitions */
Anna Bridge 169:a7c7b631e539 691 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
Anna Bridge 169:a7c7b631e539 692 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
Anna Bridge 169:a7c7b631e539 693
Anna Bridge 169:a7c7b631e539 694 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
Anna Bridge 169:a7c7b631e539 695 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
Anna Bridge 169:a7c7b631e539 696
Anna Bridge 169:a7c7b631e539 697 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
Anna Bridge 169:a7c7b631e539 698 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
Anna Bridge 169:a7c7b631e539 699
Anna Bridge 169:a7c7b631e539 700 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
Anna Bridge 169:a7c7b631e539 701 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
Anna Bridge 169:a7c7b631e539 702
Anna Bridge 169:a7c7b631e539 703 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
Anna Bridge 169:a7c7b631e539 704 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
Anna Bridge 169:a7c7b631e539 705
Anna Bridge 169:a7c7b631e539 706 /*@} end of group CMSIS_SCB */
Anna Bridge 169:a7c7b631e539 707
Anna Bridge 169:a7c7b631e539 708
Anna Bridge 169:a7c7b631e539 709 /**
Anna Bridge 169:a7c7b631e539 710 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 711 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Anna Bridge 169:a7c7b631e539 712 \brief Type definitions for the System Control and ID Register not in the SCB
Anna Bridge 169:a7c7b631e539 713 @{
Anna Bridge 169:a7c7b631e539 714 */
Anna Bridge 169:a7c7b631e539 715
Anna Bridge 169:a7c7b631e539 716 /**
Anna Bridge 169:a7c7b631e539 717 \brief Structure type to access the System Control and ID Register not in the SCB.
Anna Bridge 169:a7c7b631e539 718 */
Anna Bridge 169:a7c7b631e539 719 typedef struct
Anna Bridge 169:a7c7b631e539 720 {
Anna Bridge 169:a7c7b631e539 721 uint32_t RESERVED0[1U];
Anna Bridge 169:a7c7b631e539 722 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
Anna Bridge 169:a7c7b631e539 723 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
Anna Bridge 169:a7c7b631e539 724 } SCnSCB_Type;
Anna Bridge 169:a7c7b631e539 725
Anna Bridge 169:a7c7b631e539 726 /* Interrupt Controller Type Register Definitions */
Anna Bridge 169:a7c7b631e539 727 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
Anna Bridge 169:a7c7b631e539 728 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
Anna Bridge 169:a7c7b631e539 729
Anna Bridge 169:a7c7b631e539 730 /* Auxiliary Control Register Definitions */
Anna Bridge 169:a7c7b631e539 731 #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
Anna Bridge 169:a7c7b631e539 732 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
Anna Bridge 169:a7c7b631e539 733
Anna Bridge 169:a7c7b631e539 734 #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
Anna Bridge 169:a7c7b631e539 735 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
Anna Bridge 169:a7c7b631e539 736
Anna Bridge 169:a7c7b631e539 737 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
Anna Bridge 169:a7c7b631e539 738 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
Anna Bridge 169:a7c7b631e539 739
Anna Bridge 169:a7c7b631e539 740 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
Anna Bridge 169:a7c7b631e539 741 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
Anna Bridge 169:a7c7b631e539 742
Anna Bridge 169:a7c7b631e539 743 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
Anna Bridge 169:a7c7b631e539 744 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
Anna Bridge 169:a7c7b631e539 745
Anna Bridge 169:a7c7b631e539 746 /*@} end of group CMSIS_SCnotSCB */
Anna Bridge 169:a7c7b631e539 747
Anna Bridge 169:a7c7b631e539 748
Anna Bridge 169:a7c7b631e539 749 /**
Anna Bridge 169:a7c7b631e539 750 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 751 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Anna Bridge 169:a7c7b631e539 752 \brief Type definitions for the System Timer Registers.
Anna Bridge 169:a7c7b631e539 753 @{
Anna Bridge 169:a7c7b631e539 754 */
Anna Bridge 169:a7c7b631e539 755
Anna Bridge 169:a7c7b631e539 756 /**
Anna Bridge 169:a7c7b631e539 757 \brief Structure type to access the System Timer (SysTick).
Anna Bridge 169:a7c7b631e539 758 */
Anna Bridge 169:a7c7b631e539 759 typedef struct
Anna Bridge 169:a7c7b631e539 760 {
Anna Bridge 169:a7c7b631e539 761 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Anna Bridge 169:a7c7b631e539 762 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Anna Bridge 169:a7c7b631e539 763 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Anna Bridge 169:a7c7b631e539 764 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Anna Bridge 169:a7c7b631e539 765 } SysTick_Type;
Anna Bridge 169:a7c7b631e539 766
Anna Bridge 169:a7c7b631e539 767 /* SysTick Control / Status Register Definitions */
Anna Bridge 169:a7c7b631e539 768 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
Anna Bridge 169:a7c7b631e539 769 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Anna Bridge 169:a7c7b631e539 770
Anna Bridge 169:a7c7b631e539 771 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
Anna Bridge 169:a7c7b631e539 772 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Anna Bridge 169:a7c7b631e539 773
Anna Bridge 169:a7c7b631e539 774 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
Anna Bridge 169:a7c7b631e539 775 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Anna Bridge 169:a7c7b631e539 776
Anna Bridge 169:a7c7b631e539 777 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
Anna Bridge 169:a7c7b631e539 778 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Anna Bridge 169:a7c7b631e539 779
Anna Bridge 169:a7c7b631e539 780 /* SysTick Reload Register Definitions */
Anna Bridge 169:a7c7b631e539 781 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
Anna Bridge 169:a7c7b631e539 782 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Anna Bridge 169:a7c7b631e539 783
Anna Bridge 169:a7c7b631e539 784 /* SysTick Current Register Definitions */
Anna Bridge 169:a7c7b631e539 785 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
Anna Bridge 169:a7c7b631e539 786 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Anna Bridge 169:a7c7b631e539 787
Anna Bridge 169:a7c7b631e539 788 /* SysTick Calibration Register Definitions */
Anna Bridge 169:a7c7b631e539 789 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
Anna Bridge 169:a7c7b631e539 790 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Anna Bridge 169:a7c7b631e539 791
Anna Bridge 169:a7c7b631e539 792 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
Anna Bridge 169:a7c7b631e539 793 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Anna Bridge 169:a7c7b631e539 794
Anna Bridge 169:a7c7b631e539 795 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
Anna Bridge 169:a7c7b631e539 796 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Anna Bridge 169:a7c7b631e539 797
Anna Bridge 169:a7c7b631e539 798 /*@} end of group CMSIS_SysTick */
Anna Bridge 169:a7c7b631e539 799
Anna Bridge 169:a7c7b631e539 800
Anna Bridge 169:a7c7b631e539 801 /**
Anna Bridge 169:a7c7b631e539 802 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 803 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Anna Bridge 169:a7c7b631e539 804 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Anna Bridge 169:a7c7b631e539 805 @{
Anna Bridge 169:a7c7b631e539 806 */
Anna Bridge 169:a7c7b631e539 807
Anna Bridge 169:a7c7b631e539 808 /**
Anna Bridge 169:a7c7b631e539 809 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Anna Bridge 169:a7c7b631e539 810 */
Anna Bridge 169:a7c7b631e539 811 typedef struct
Anna Bridge 169:a7c7b631e539 812 {
Anna Bridge 169:a7c7b631e539 813 __OM union
Anna Bridge 169:a7c7b631e539 814 {
Anna Bridge 169:a7c7b631e539 815 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
Anna Bridge 169:a7c7b631e539 816 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
Anna Bridge 169:a7c7b631e539 817 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
Anna Bridge 169:a7c7b631e539 818 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
Anna Bridge 169:a7c7b631e539 819 uint32_t RESERVED0[864U];
Anna Bridge 169:a7c7b631e539 820 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
Anna Bridge 169:a7c7b631e539 821 uint32_t RESERVED1[15U];
Anna Bridge 169:a7c7b631e539 822 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
Anna Bridge 169:a7c7b631e539 823 uint32_t RESERVED2[15U];
Anna Bridge 169:a7c7b631e539 824 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
Anna Bridge 169:a7c7b631e539 825 uint32_t RESERVED3[29U];
Anna Bridge 169:a7c7b631e539 826 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
Anna Bridge 169:a7c7b631e539 827 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
Anna Bridge 169:a7c7b631e539 828 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
Anna Bridge 169:a7c7b631e539 829 uint32_t RESERVED4[43U];
Anna Bridge 169:a7c7b631e539 830 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
Anna Bridge 169:a7c7b631e539 831 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
Anna Bridge 169:a7c7b631e539 832 uint32_t RESERVED5[6U];
Anna Bridge 169:a7c7b631e539 833 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
Anna Bridge 169:a7c7b631e539 834 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
Anna Bridge 169:a7c7b631e539 835 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
Anna Bridge 169:a7c7b631e539 836 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
Anna Bridge 169:a7c7b631e539 837 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
Anna Bridge 169:a7c7b631e539 838 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
Anna Bridge 169:a7c7b631e539 839 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
Anna Bridge 169:a7c7b631e539 840 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
Anna Bridge 169:a7c7b631e539 841 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
Anna Bridge 169:a7c7b631e539 842 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
Anna Bridge 169:a7c7b631e539 843 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
Anna Bridge 169:a7c7b631e539 844 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
Anna Bridge 169:a7c7b631e539 845 } ITM_Type;
Anna Bridge 169:a7c7b631e539 846
Anna Bridge 169:a7c7b631e539 847 /* ITM Trace Privilege Register Definitions */
Anna Bridge 169:a7c7b631e539 848 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
Anna Bridge 169:a7c7b631e539 849 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
Anna Bridge 169:a7c7b631e539 850
Anna Bridge 169:a7c7b631e539 851 /* ITM Trace Control Register Definitions */
Anna Bridge 169:a7c7b631e539 852 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
Anna Bridge 169:a7c7b631e539 853 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
Anna Bridge 169:a7c7b631e539 854
Anna Bridge 169:a7c7b631e539 855 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
Anna Bridge 169:a7c7b631e539 856 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
Anna Bridge 169:a7c7b631e539 857
Anna Bridge 169:a7c7b631e539 858 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
Anna Bridge 169:a7c7b631e539 859 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
Anna Bridge 169:a7c7b631e539 860
Anna Bridge 169:a7c7b631e539 861 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
Anna Bridge 169:a7c7b631e539 862 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
Anna Bridge 169:a7c7b631e539 863
Anna Bridge 169:a7c7b631e539 864 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
Anna Bridge 169:a7c7b631e539 865 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
Anna Bridge 169:a7c7b631e539 866
Anna Bridge 169:a7c7b631e539 867 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
Anna Bridge 169:a7c7b631e539 868 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
Anna Bridge 169:a7c7b631e539 869
Anna Bridge 169:a7c7b631e539 870 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
Anna Bridge 169:a7c7b631e539 871 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
Anna Bridge 169:a7c7b631e539 872
Anna Bridge 169:a7c7b631e539 873 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
Anna Bridge 169:a7c7b631e539 874 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
Anna Bridge 169:a7c7b631e539 875
Anna Bridge 169:a7c7b631e539 876 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
Anna Bridge 169:a7c7b631e539 877 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
Anna Bridge 169:a7c7b631e539 878
Anna Bridge 169:a7c7b631e539 879 /* ITM Integration Write Register Definitions */
Anna Bridge 169:a7c7b631e539 880 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
Anna Bridge 169:a7c7b631e539 881 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
Anna Bridge 169:a7c7b631e539 882
Anna Bridge 169:a7c7b631e539 883 /* ITM Integration Read Register Definitions */
Anna Bridge 169:a7c7b631e539 884 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
Anna Bridge 169:a7c7b631e539 885 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
Anna Bridge 169:a7c7b631e539 886
Anna Bridge 169:a7c7b631e539 887 /* ITM Integration Mode Control Register Definitions */
Anna Bridge 169:a7c7b631e539 888 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
Anna Bridge 169:a7c7b631e539 889 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
Anna Bridge 169:a7c7b631e539 890
Anna Bridge 169:a7c7b631e539 891 /* ITM Lock Status Register Definitions */
Anna Bridge 169:a7c7b631e539 892 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
Anna Bridge 169:a7c7b631e539 893 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
Anna Bridge 169:a7c7b631e539 894
Anna Bridge 169:a7c7b631e539 895 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
Anna Bridge 169:a7c7b631e539 896 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
Anna Bridge 169:a7c7b631e539 897
Anna Bridge 169:a7c7b631e539 898 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
Anna Bridge 169:a7c7b631e539 899 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
Anna Bridge 169:a7c7b631e539 900
Anna Bridge 169:a7c7b631e539 901 /*@}*/ /* end of group CMSIS_ITM */
Anna Bridge 169:a7c7b631e539 902
Anna Bridge 169:a7c7b631e539 903
Anna Bridge 169:a7c7b631e539 904 /**
Anna Bridge 169:a7c7b631e539 905 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 906 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Anna Bridge 169:a7c7b631e539 907 \brief Type definitions for the Data Watchpoint and Trace (DWT)
Anna Bridge 169:a7c7b631e539 908 @{
Anna Bridge 169:a7c7b631e539 909 */
Anna Bridge 169:a7c7b631e539 910
Anna Bridge 169:a7c7b631e539 911 /**
Anna Bridge 169:a7c7b631e539 912 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Anna Bridge 169:a7c7b631e539 913 */
Anna Bridge 169:a7c7b631e539 914 typedef struct
Anna Bridge 169:a7c7b631e539 915 {
Anna Bridge 169:a7c7b631e539 916 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
Anna Bridge 169:a7c7b631e539 917 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
Anna Bridge 169:a7c7b631e539 918 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
Anna Bridge 169:a7c7b631e539 919 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
Anna Bridge 169:a7c7b631e539 920 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
Anna Bridge 169:a7c7b631e539 921 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
Anna Bridge 169:a7c7b631e539 922 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
Anna Bridge 169:a7c7b631e539 923 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
Anna Bridge 169:a7c7b631e539 924 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
Anna Bridge 169:a7c7b631e539 925 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
Anna Bridge 169:a7c7b631e539 926 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
Anna Bridge 169:a7c7b631e539 927 uint32_t RESERVED0[1U];
Anna Bridge 169:a7c7b631e539 928 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
Anna Bridge 169:a7c7b631e539 929 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
Anna Bridge 169:a7c7b631e539 930 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
Anna Bridge 169:a7c7b631e539 931 uint32_t RESERVED1[1U];
Anna Bridge 169:a7c7b631e539 932 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
Anna Bridge 169:a7c7b631e539 933 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
Anna Bridge 169:a7c7b631e539 934 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
Anna Bridge 169:a7c7b631e539 935 uint32_t RESERVED2[1U];
Anna Bridge 169:a7c7b631e539 936 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
Anna Bridge 169:a7c7b631e539 937 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
Anna Bridge 169:a7c7b631e539 938 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
Anna Bridge 169:a7c7b631e539 939 } DWT_Type;
Anna Bridge 169:a7c7b631e539 940
Anna Bridge 169:a7c7b631e539 941 /* DWT Control Register Definitions */
Anna Bridge 169:a7c7b631e539 942 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
Anna Bridge 169:a7c7b631e539 943 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
Anna Bridge 169:a7c7b631e539 944
Anna Bridge 169:a7c7b631e539 945 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
Anna Bridge 169:a7c7b631e539 946 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
Anna Bridge 169:a7c7b631e539 947
Anna Bridge 169:a7c7b631e539 948 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
Anna Bridge 169:a7c7b631e539 949 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
Anna Bridge 169:a7c7b631e539 950
Anna Bridge 169:a7c7b631e539 951 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
Anna Bridge 169:a7c7b631e539 952 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
Anna Bridge 169:a7c7b631e539 953
Anna Bridge 169:a7c7b631e539 954 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
Anna Bridge 169:a7c7b631e539 955 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
Anna Bridge 169:a7c7b631e539 956
Anna Bridge 169:a7c7b631e539 957 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
Anna Bridge 169:a7c7b631e539 958 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
Anna Bridge 169:a7c7b631e539 959
Anna Bridge 169:a7c7b631e539 960 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
Anna Bridge 169:a7c7b631e539 961 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
Anna Bridge 169:a7c7b631e539 962
Anna Bridge 169:a7c7b631e539 963 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
Anna Bridge 169:a7c7b631e539 964 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
Anna Bridge 169:a7c7b631e539 965
Anna Bridge 169:a7c7b631e539 966 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
Anna Bridge 169:a7c7b631e539 967 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
Anna Bridge 169:a7c7b631e539 968
Anna Bridge 169:a7c7b631e539 969 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
Anna Bridge 169:a7c7b631e539 970 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
Anna Bridge 169:a7c7b631e539 971
Anna Bridge 169:a7c7b631e539 972 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
Anna Bridge 169:a7c7b631e539 973 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
Anna Bridge 169:a7c7b631e539 974
Anna Bridge 169:a7c7b631e539 975 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
Anna Bridge 169:a7c7b631e539 976 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
Anna Bridge 169:a7c7b631e539 977
Anna Bridge 169:a7c7b631e539 978 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
Anna Bridge 169:a7c7b631e539 979 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
Anna Bridge 169:a7c7b631e539 980
Anna Bridge 169:a7c7b631e539 981 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
Anna Bridge 169:a7c7b631e539 982 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
Anna Bridge 169:a7c7b631e539 983
Anna Bridge 169:a7c7b631e539 984 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
Anna Bridge 169:a7c7b631e539 985 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
Anna Bridge 169:a7c7b631e539 986
Anna Bridge 169:a7c7b631e539 987 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
Anna Bridge 169:a7c7b631e539 988 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
Anna Bridge 169:a7c7b631e539 989
Anna Bridge 169:a7c7b631e539 990 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
Anna Bridge 169:a7c7b631e539 991 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
Anna Bridge 169:a7c7b631e539 992
Anna Bridge 169:a7c7b631e539 993 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
Anna Bridge 169:a7c7b631e539 994 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
Anna Bridge 169:a7c7b631e539 995
Anna Bridge 169:a7c7b631e539 996 /* DWT CPI Count Register Definitions */
Anna Bridge 169:a7c7b631e539 997 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
Anna Bridge 169:a7c7b631e539 998 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
Anna Bridge 169:a7c7b631e539 999
Anna Bridge 169:a7c7b631e539 1000 /* DWT Exception Overhead Count Register Definitions */
Anna Bridge 169:a7c7b631e539 1001 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
Anna Bridge 169:a7c7b631e539 1002 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
Anna Bridge 169:a7c7b631e539 1003
Anna Bridge 169:a7c7b631e539 1004 /* DWT Sleep Count Register Definitions */
Anna Bridge 169:a7c7b631e539 1005 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
Anna Bridge 169:a7c7b631e539 1006 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
Anna Bridge 169:a7c7b631e539 1007
Anna Bridge 169:a7c7b631e539 1008 /* DWT LSU Count Register Definitions */
Anna Bridge 169:a7c7b631e539 1009 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
Anna Bridge 169:a7c7b631e539 1010 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
Anna Bridge 169:a7c7b631e539 1011
Anna Bridge 169:a7c7b631e539 1012 /* DWT Folded-instruction Count Register Definitions */
Anna Bridge 169:a7c7b631e539 1013 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
Anna Bridge 169:a7c7b631e539 1014 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
Anna Bridge 169:a7c7b631e539 1015
Anna Bridge 169:a7c7b631e539 1016 /* DWT Comparator Mask Register Definitions */
Anna Bridge 169:a7c7b631e539 1017 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
Anna Bridge 169:a7c7b631e539 1018 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
Anna Bridge 169:a7c7b631e539 1019
Anna Bridge 169:a7c7b631e539 1020 /* DWT Comparator Function Register Definitions */
Anna Bridge 169:a7c7b631e539 1021 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
Anna Bridge 169:a7c7b631e539 1022 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
Anna Bridge 169:a7c7b631e539 1023
Anna Bridge 169:a7c7b631e539 1024 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
Anna Bridge 169:a7c7b631e539 1025 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
Anna Bridge 169:a7c7b631e539 1026
Anna Bridge 169:a7c7b631e539 1027 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
Anna Bridge 169:a7c7b631e539 1028 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
Anna Bridge 169:a7c7b631e539 1029
Anna Bridge 169:a7c7b631e539 1030 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
Anna Bridge 169:a7c7b631e539 1031 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
Anna Bridge 169:a7c7b631e539 1032
Anna Bridge 169:a7c7b631e539 1033 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
Anna Bridge 169:a7c7b631e539 1034 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
Anna Bridge 169:a7c7b631e539 1035
Anna Bridge 169:a7c7b631e539 1036 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
Anna Bridge 169:a7c7b631e539 1037 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
Anna Bridge 169:a7c7b631e539 1038
Anna Bridge 169:a7c7b631e539 1039 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
Anna Bridge 169:a7c7b631e539 1040 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
Anna Bridge 169:a7c7b631e539 1041
Anna Bridge 169:a7c7b631e539 1042 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
Anna Bridge 169:a7c7b631e539 1043 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
Anna Bridge 169:a7c7b631e539 1044
Anna Bridge 169:a7c7b631e539 1045 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
Anna Bridge 169:a7c7b631e539 1046 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
Anna Bridge 169:a7c7b631e539 1047
Anna Bridge 169:a7c7b631e539 1048 /*@}*/ /* end of group CMSIS_DWT */
Anna Bridge 169:a7c7b631e539 1049
Anna Bridge 169:a7c7b631e539 1050
Anna Bridge 169:a7c7b631e539 1051 /**
Anna Bridge 169:a7c7b631e539 1052 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 1053 \defgroup CMSIS_TPI Trace Port Interface (TPI)
Anna Bridge 169:a7c7b631e539 1054 \brief Type definitions for the Trace Port Interface (TPI)
Anna Bridge 169:a7c7b631e539 1055 @{
Anna Bridge 169:a7c7b631e539 1056 */
Anna Bridge 169:a7c7b631e539 1057
Anna Bridge 169:a7c7b631e539 1058 /**
Anna Bridge 169:a7c7b631e539 1059 \brief Structure type to access the Trace Port Interface Register (TPI).
Anna Bridge 169:a7c7b631e539 1060 */
Anna Bridge 169:a7c7b631e539 1061 typedef struct
Anna Bridge 169:a7c7b631e539 1062 {
Anna Bridge 169:a7c7b631e539 1063 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
Anna Bridge 169:a7c7b631e539 1064 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
Anna Bridge 169:a7c7b631e539 1065 uint32_t RESERVED0[2U];
Anna Bridge 169:a7c7b631e539 1066 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
Anna Bridge 169:a7c7b631e539 1067 uint32_t RESERVED1[55U];
Anna Bridge 169:a7c7b631e539 1068 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
Anna Bridge 169:a7c7b631e539 1069 uint32_t RESERVED2[131U];
Anna Bridge 169:a7c7b631e539 1070 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
Anna Bridge 169:a7c7b631e539 1071 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
Anna Bridge 169:a7c7b631e539 1072 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
Anna Bridge 169:a7c7b631e539 1073 uint32_t RESERVED3[759U];
Anna Bridge 169:a7c7b631e539 1074 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
Anna Bridge 169:a7c7b631e539 1075 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
Anna Bridge 169:a7c7b631e539 1076 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
Anna Bridge 169:a7c7b631e539 1077 uint32_t RESERVED4[1U];
Anna Bridge 169:a7c7b631e539 1078 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
Anna Bridge 169:a7c7b631e539 1079 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
Anna Bridge 169:a7c7b631e539 1080 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
Anna Bridge 169:a7c7b631e539 1081 uint32_t RESERVED5[39U];
Anna Bridge 169:a7c7b631e539 1082 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
Anna Bridge 169:a7c7b631e539 1083 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
Anna Bridge 169:a7c7b631e539 1084 uint32_t RESERVED7[8U];
Anna Bridge 169:a7c7b631e539 1085 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
Anna Bridge 169:a7c7b631e539 1086 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
Anna Bridge 169:a7c7b631e539 1087 } TPI_Type;
Anna Bridge 169:a7c7b631e539 1088
Anna Bridge 169:a7c7b631e539 1089 /* TPI Asynchronous Clock Prescaler Register Definitions */
Anna Bridge 169:a7c7b631e539 1090 #define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */
Anna Bridge 169:a7c7b631e539 1091 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */
Anna Bridge 169:a7c7b631e539 1092
Anna Bridge 169:a7c7b631e539 1093 #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
Anna Bridge 169:a7c7b631e539 1094 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
Anna Bridge 169:a7c7b631e539 1095
Anna Bridge 169:a7c7b631e539 1096 /* TPI Selected Pin Protocol Register Definitions */
Anna Bridge 169:a7c7b631e539 1097 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
Anna Bridge 169:a7c7b631e539 1098 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
Anna Bridge 169:a7c7b631e539 1099
Anna Bridge 169:a7c7b631e539 1100 /* TPI Formatter and Flush Status Register Definitions */
Anna Bridge 169:a7c7b631e539 1101 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
Anna Bridge 169:a7c7b631e539 1102 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
Anna Bridge 169:a7c7b631e539 1103
Anna Bridge 169:a7c7b631e539 1104 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
Anna Bridge 169:a7c7b631e539 1105 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
Anna Bridge 169:a7c7b631e539 1106
Anna Bridge 169:a7c7b631e539 1107 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
Anna Bridge 169:a7c7b631e539 1108 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
Anna Bridge 169:a7c7b631e539 1109
Anna Bridge 169:a7c7b631e539 1110 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
Anna Bridge 169:a7c7b631e539 1111 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
Anna Bridge 169:a7c7b631e539 1112
Anna Bridge 169:a7c7b631e539 1113 /* TPI Formatter and Flush Control Register Definitions */
Anna Bridge 169:a7c7b631e539 1114 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
Anna Bridge 169:a7c7b631e539 1115 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
Anna Bridge 169:a7c7b631e539 1116
Anna Bridge 169:a7c7b631e539 1117 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
Anna Bridge 169:a7c7b631e539 1118 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
Anna Bridge 169:a7c7b631e539 1119
Anna Bridge 169:a7c7b631e539 1120 /* TPI TRIGGER Register Definitions */
Anna Bridge 169:a7c7b631e539 1121 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
Anna Bridge 169:a7c7b631e539 1122 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
Anna Bridge 169:a7c7b631e539 1123
Anna Bridge 169:a7c7b631e539 1124 /* TPI Integration ETM Data Register Definitions (FIFO0) */
Anna Bridge 169:a7c7b631e539 1125 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
Anna Bridge 169:a7c7b631e539 1126 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
Anna Bridge 169:a7c7b631e539 1127
Anna Bridge 169:a7c7b631e539 1128 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
Anna Bridge 169:a7c7b631e539 1129 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
Anna Bridge 169:a7c7b631e539 1130
Anna Bridge 169:a7c7b631e539 1131 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
Anna Bridge 169:a7c7b631e539 1132 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
Anna Bridge 169:a7c7b631e539 1133
Anna Bridge 169:a7c7b631e539 1134 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
Anna Bridge 169:a7c7b631e539 1135 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
Anna Bridge 169:a7c7b631e539 1136
Anna Bridge 169:a7c7b631e539 1137 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
Anna Bridge 169:a7c7b631e539 1138 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
Anna Bridge 169:a7c7b631e539 1139
Anna Bridge 169:a7c7b631e539 1140 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
Anna Bridge 169:a7c7b631e539 1141 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
Anna Bridge 169:a7c7b631e539 1142
Anna Bridge 169:a7c7b631e539 1143 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
Anna Bridge 169:a7c7b631e539 1144 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
Anna Bridge 169:a7c7b631e539 1145
Anna Bridge 169:a7c7b631e539 1146 /* TPI ITATBCTR2 Register Definitions */
Anna Bridge 169:a7c7b631e539 1147 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
Anna Bridge 169:a7c7b631e539 1148 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
Anna Bridge 169:a7c7b631e539 1149
Anna Bridge 169:a7c7b631e539 1150 /* TPI Integration ITM Data Register Definitions (FIFO1) */
Anna Bridge 169:a7c7b631e539 1151 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
Anna Bridge 169:a7c7b631e539 1152 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
Anna Bridge 169:a7c7b631e539 1153
Anna Bridge 169:a7c7b631e539 1154 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
Anna Bridge 169:a7c7b631e539 1155 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
Anna Bridge 169:a7c7b631e539 1156
Anna Bridge 169:a7c7b631e539 1157 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
Anna Bridge 169:a7c7b631e539 1158 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
Anna Bridge 169:a7c7b631e539 1159
Anna Bridge 169:a7c7b631e539 1160 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
Anna Bridge 169:a7c7b631e539 1161 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
Anna Bridge 169:a7c7b631e539 1162
Anna Bridge 169:a7c7b631e539 1163 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
Anna Bridge 169:a7c7b631e539 1164 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
Anna Bridge 169:a7c7b631e539 1165
Anna Bridge 169:a7c7b631e539 1166 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
Anna Bridge 169:a7c7b631e539 1167 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
Anna Bridge 169:a7c7b631e539 1168
Anna Bridge 169:a7c7b631e539 1169 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
Anna Bridge 169:a7c7b631e539 1170 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
Anna Bridge 169:a7c7b631e539 1171
Anna Bridge 169:a7c7b631e539 1172 /* TPI ITATBCTR0 Register Definitions */
Anna Bridge 169:a7c7b631e539 1173 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
Anna Bridge 169:a7c7b631e539 1174 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
Anna Bridge 169:a7c7b631e539 1175
Anna Bridge 169:a7c7b631e539 1176 /* TPI Integration Mode Control Register Definitions */
Anna Bridge 169:a7c7b631e539 1177 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
Anna Bridge 169:a7c7b631e539 1178 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
Anna Bridge 169:a7c7b631e539 1179
Anna Bridge 169:a7c7b631e539 1180 /* TPI DEVID Register Definitions */
Anna Bridge 169:a7c7b631e539 1181 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
Anna Bridge 169:a7c7b631e539 1182 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
Anna Bridge 169:a7c7b631e539 1183
Anna Bridge 169:a7c7b631e539 1184 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
Anna Bridge 169:a7c7b631e539 1185 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
Anna Bridge 169:a7c7b631e539 1186
Anna Bridge 169:a7c7b631e539 1187 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
Anna Bridge 169:a7c7b631e539 1188 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
Anna Bridge 169:a7c7b631e539 1189
Anna Bridge 169:a7c7b631e539 1190 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
Anna Bridge 169:a7c7b631e539 1191 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
Anna Bridge 169:a7c7b631e539 1192
Anna Bridge 169:a7c7b631e539 1193 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
Anna Bridge 169:a7c7b631e539 1194 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
Anna Bridge 169:a7c7b631e539 1195
Anna Bridge 169:a7c7b631e539 1196 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
Anna Bridge 169:a7c7b631e539 1197 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
Anna Bridge 169:a7c7b631e539 1198
Anna Bridge 169:a7c7b631e539 1199 /* TPI DEVTYPE Register Definitions */
Anna Bridge 169:a7c7b631e539 1200 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
Anna Bridge 169:a7c7b631e539 1201 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
Anna Bridge 169:a7c7b631e539 1202
Anna Bridge 169:a7c7b631e539 1203 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
Anna Bridge 169:a7c7b631e539 1204 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
Anna Bridge 169:a7c7b631e539 1205
Anna Bridge 169:a7c7b631e539 1206 /*@}*/ /* end of group CMSIS_TPI */
Anna Bridge 169:a7c7b631e539 1207
Anna Bridge 169:a7c7b631e539 1208
Anna Bridge 169:a7c7b631e539 1209 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 1210 /**
Anna Bridge 169:a7c7b631e539 1211 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 1212 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Anna Bridge 169:a7c7b631e539 1213 \brief Type definitions for the Memory Protection Unit (MPU)
Anna Bridge 169:a7c7b631e539 1214 @{
Anna Bridge 169:a7c7b631e539 1215 */
Anna Bridge 169:a7c7b631e539 1216
Anna Bridge 169:a7c7b631e539 1217 /**
Anna Bridge 169:a7c7b631e539 1218 \brief Structure type to access the Memory Protection Unit (MPU).
Anna Bridge 169:a7c7b631e539 1219 */
Anna Bridge 169:a7c7b631e539 1220 typedef struct
Anna Bridge 169:a7c7b631e539 1221 {
Anna Bridge 169:a7c7b631e539 1222 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Anna Bridge 169:a7c7b631e539 1223 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Anna Bridge 169:a7c7b631e539 1224 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Anna Bridge 169:a7c7b631e539 1225 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Anna Bridge 169:a7c7b631e539 1226 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Anna Bridge 169:a7c7b631e539 1227 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
Anna Bridge 169:a7c7b631e539 1228 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
Anna Bridge 169:a7c7b631e539 1229 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
Anna Bridge 169:a7c7b631e539 1230 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
Anna Bridge 169:a7c7b631e539 1231 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
Anna Bridge 169:a7c7b631e539 1232 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
Anna Bridge 169:a7c7b631e539 1233 } MPU_Type;
Anna Bridge 169:a7c7b631e539 1234
Anna Bridge 169:a7c7b631e539 1235 #define MPU_TYPE_RALIASES 4U
Anna Bridge 169:a7c7b631e539 1236
Anna Bridge 169:a7c7b631e539 1237 /* MPU Type Register Definitions */
Anna Bridge 169:a7c7b631e539 1238 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
Anna Bridge 169:a7c7b631e539 1239 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Anna Bridge 169:a7c7b631e539 1240
Anna Bridge 169:a7c7b631e539 1241 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
Anna Bridge 169:a7c7b631e539 1242 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Anna Bridge 169:a7c7b631e539 1243
Anna Bridge 169:a7c7b631e539 1244 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
Anna Bridge 169:a7c7b631e539 1245 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Anna Bridge 169:a7c7b631e539 1246
Anna Bridge 169:a7c7b631e539 1247 /* MPU Control Register Definitions */
Anna Bridge 169:a7c7b631e539 1248 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
Anna Bridge 169:a7c7b631e539 1249 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Anna Bridge 169:a7c7b631e539 1250
Anna Bridge 169:a7c7b631e539 1251 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
Anna Bridge 169:a7c7b631e539 1252 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Anna Bridge 169:a7c7b631e539 1253
Anna Bridge 169:a7c7b631e539 1254 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
Anna Bridge 169:a7c7b631e539 1255 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Anna Bridge 169:a7c7b631e539 1256
Anna Bridge 169:a7c7b631e539 1257 /* MPU Region Number Register Definitions */
Anna Bridge 169:a7c7b631e539 1258 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
Anna Bridge 169:a7c7b631e539 1259 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Anna Bridge 169:a7c7b631e539 1260
Anna Bridge 169:a7c7b631e539 1261 /* MPU Region Base Address Register Definitions */
Anna Bridge 169:a7c7b631e539 1262 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
Anna Bridge 169:a7c7b631e539 1263 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Anna Bridge 169:a7c7b631e539 1264
Anna Bridge 169:a7c7b631e539 1265 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
Anna Bridge 169:a7c7b631e539 1266 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Anna Bridge 169:a7c7b631e539 1267
Anna Bridge 169:a7c7b631e539 1268 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
Anna Bridge 169:a7c7b631e539 1269 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Anna Bridge 169:a7c7b631e539 1270
Anna Bridge 169:a7c7b631e539 1271 /* MPU Region Attribute and Size Register Definitions */
Anna Bridge 169:a7c7b631e539 1272 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
Anna Bridge 169:a7c7b631e539 1273 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Anna Bridge 169:a7c7b631e539 1274
Anna Bridge 169:a7c7b631e539 1275 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
Anna Bridge 169:a7c7b631e539 1276 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Anna Bridge 169:a7c7b631e539 1277
Anna Bridge 169:a7c7b631e539 1278 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
Anna Bridge 169:a7c7b631e539 1279 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Anna Bridge 169:a7c7b631e539 1280
Anna Bridge 169:a7c7b631e539 1281 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
Anna Bridge 169:a7c7b631e539 1282 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Anna Bridge 169:a7c7b631e539 1283
Anna Bridge 169:a7c7b631e539 1284 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
Anna Bridge 169:a7c7b631e539 1285 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Anna Bridge 169:a7c7b631e539 1286
Anna Bridge 169:a7c7b631e539 1287 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
Anna Bridge 169:a7c7b631e539 1288 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Anna Bridge 169:a7c7b631e539 1289
Anna Bridge 169:a7c7b631e539 1290 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
Anna Bridge 169:a7c7b631e539 1291 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Anna Bridge 169:a7c7b631e539 1292
Anna Bridge 169:a7c7b631e539 1293 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
Anna Bridge 169:a7c7b631e539 1294 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Anna Bridge 169:a7c7b631e539 1295
Anna Bridge 169:a7c7b631e539 1296 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
Anna Bridge 169:a7c7b631e539 1297 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Anna Bridge 169:a7c7b631e539 1298
Anna Bridge 169:a7c7b631e539 1299 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
Anna Bridge 169:a7c7b631e539 1300 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Anna Bridge 169:a7c7b631e539 1301
Anna Bridge 169:a7c7b631e539 1302 /*@} end of group CMSIS_MPU */
Anna Bridge 169:a7c7b631e539 1303 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
Anna Bridge 169:a7c7b631e539 1304
Anna Bridge 169:a7c7b631e539 1305
Anna Bridge 169:a7c7b631e539 1306 /**
Anna Bridge 169:a7c7b631e539 1307 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 1308 \defgroup CMSIS_FPU Floating Point Unit (FPU)
Anna Bridge 169:a7c7b631e539 1309 \brief Type definitions for the Floating Point Unit (FPU)
Anna Bridge 169:a7c7b631e539 1310 @{
Anna Bridge 169:a7c7b631e539 1311 */
Anna Bridge 169:a7c7b631e539 1312
Anna Bridge 169:a7c7b631e539 1313 /**
Anna Bridge 169:a7c7b631e539 1314 \brief Structure type to access the Floating Point Unit (FPU).
Anna Bridge 169:a7c7b631e539 1315 */
Anna Bridge 169:a7c7b631e539 1316 typedef struct
Anna Bridge 169:a7c7b631e539 1317 {
Anna Bridge 169:a7c7b631e539 1318 uint32_t RESERVED0[1U];
Anna Bridge 169:a7c7b631e539 1319 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
Anna Bridge 169:a7c7b631e539 1320 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
Anna Bridge 169:a7c7b631e539 1321 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
Anna Bridge 169:a7c7b631e539 1322 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
Anna Bridge 169:a7c7b631e539 1323 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
Anna Bridge 169:a7c7b631e539 1324 } FPU_Type;
Anna Bridge 169:a7c7b631e539 1325
Anna Bridge 169:a7c7b631e539 1326 /* Floating-Point Context Control Register Definitions */
Anna Bridge 169:a7c7b631e539 1327 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
Anna Bridge 169:a7c7b631e539 1328 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
Anna Bridge 169:a7c7b631e539 1329
Anna Bridge 169:a7c7b631e539 1330 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
Anna Bridge 169:a7c7b631e539 1331 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
Anna Bridge 169:a7c7b631e539 1332
Anna Bridge 169:a7c7b631e539 1333 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
Anna Bridge 169:a7c7b631e539 1334 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
Anna Bridge 169:a7c7b631e539 1335
Anna Bridge 169:a7c7b631e539 1336 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
Anna Bridge 169:a7c7b631e539 1337 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
Anna Bridge 169:a7c7b631e539 1338
Anna Bridge 169:a7c7b631e539 1339 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
Anna Bridge 169:a7c7b631e539 1340 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
Anna Bridge 169:a7c7b631e539 1341
Anna Bridge 169:a7c7b631e539 1342 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
Anna Bridge 169:a7c7b631e539 1343 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
Anna Bridge 169:a7c7b631e539 1344
Anna Bridge 169:a7c7b631e539 1345 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
Anna Bridge 169:a7c7b631e539 1346 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
Anna Bridge 169:a7c7b631e539 1347
Anna Bridge 169:a7c7b631e539 1348 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
Anna Bridge 169:a7c7b631e539 1349 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
Anna Bridge 169:a7c7b631e539 1350
Anna Bridge 169:a7c7b631e539 1351 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
Anna Bridge 169:a7c7b631e539 1352 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
Anna Bridge 169:a7c7b631e539 1353
Anna Bridge 169:a7c7b631e539 1354 /* Floating-Point Context Address Register Definitions */
Anna Bridge 169:a7c7b631e539 1355 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
Anna Bridge 169:a7c7b631e539 1356 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
Anna Bridge 169:a7c7b631e539 1357
Anna Bridge 169:a7c7b631e539 1358 /* Floating-Point Default Status Control Register Definitions */
Anna Bridge 169:a7c7b631e539 1359 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
Anna Bridge 169:a7c7b631e539 1360 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
Anna Bridge 169:a7c7b631e539 1361
Anna Bridge 169:a7c7b631e539 1362 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
Anna Bridge 169:a7c7b631e539 1363 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
Anna Bridge 169:a7c7b631e539 1364
Anna Bridge 169:a7c7b631e539 1365 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
Anna Bridge 169:a7c7b631e539 1366 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
Anna Bridge 169:a7c7b631e539 1367
Anna Bridge 169:a7c7b631e539 1368 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
Anna Bridge 169:a7c7b631e539 1369 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
Anna Bridge 169:a7c7b631e539 1370
Anna Bridge 169:a7c7b631e539 1371 /* Media and FP Feature Register 0 Definitions */
Anna Bridge 169:a7c7b631e539 1372 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
Anna Bridge 169:a7c7b631e539 1373 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
Anna Bridge 169:a7c7b631e539 1374
Anna Bridge 169:a7c7b631e539 1375 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
Anna Bridge 169:a7c7b631e539 1376 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
Anna Bridge 169:a7c7b631e539 1377
Anna Bridge 169:a7c7b631e539 1378 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
Anna Bridge 169:a7c7b631e539 1379 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
Anna Bridge 169:a7c7b631e539 1380
Anna Bridge 169:a7c7b631e539 1381 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
Anna Bridge 169:a7c7b631e539 1382 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
Anna Bridge 169:a7c7b631e539 1383
Anna Bridge 169:a7c7b631e539 1384 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
Anna Bridge 169:a7c7b631e539 1385 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
Anna Bridge 169:a7c7b631e539 1386
Anna Bridge 169:a7c7b631e539 1387 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
Anna Bridge 169:a7c7b631e539 1388 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
Anna Bridge 169:a7c7b631e539 1389
Anna Bridge 169:a7c7b631e539 1390 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
Anna Bridge 169:a7c7b631e539 1391 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
Anna Bridge 169:a7c7b631e539 1392
Anna Bridge 169:a7c7b631e539 1393 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
Anna Bridge 169:a7c7b631e539 1394 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
Anna Bridge 169:a7c7b631e539 1395
Anna Bridge 169:a7c7b631e539 1396 /* Media and FP Feature Register 1 Definitions */
Anna Bridge 169:a7c7b631e539 1397 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
Anna Bridge 169:a7c7b631e539 1398 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
Anna Bridge 169:a7c7b631e539 1399
Anna Bridge 169:a7c7b631e539 1400 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
Anna Bridge 169:a7c7b631e539 1401 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
Anna Bridge 169:a7c7b631e539 1402
Anna Bridge 169:a7c7b631e539 1403 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
Anna Bridge 169:a7c7b631e539 1404 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
Anna Bridge 169:a7c7b631e539 1405
Anna Bridge 169:a7c7b631e539 1406 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
Anna Bridge 169:a7c7b631e539 1407 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
Anna Bridge 169:a7c7b631e539 1408
Anna Bridge 169:a7c7b631e539 1409 /*@} end of group CMSIS_FPU */
Anna Bridge 169:a7c7b631e539 1410
Anna Bridge 169:a7c7b631e539 1411
Anna Bridge 169:a7c7b631e539 1412 /**
Anna Bridge 169:a7c7b631e539 1413 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 1414 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Anna Bridge 169:a7c7b631e539 1415 \brief Type definitions for the Core Debug Registers
Anna Bridge 169:a7c7b631e539 1416 @{
Anna Bridge 169:a7c7b631e539 1417 */
Anna Bridge 169:a7c7b631e539 1418
Anna Bridge 169:a7c7b631e539 1419 /**
Anna Bridge 169:a7c7b631e539 1420 \brief Structure type to access the Core Debug Register (CoreDebug).
Anna Bridge 169:a7c7b631e539 1421 */
Anna Bridge 169:a7c7b631e539 1422 typedef struct
Anna Bridge 169:a7c7b631e539 1423 {
Anna Bridge 169:a7c7b631e539 1424 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
Anna Bridge 169:a7c7b631e539 1425 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
Anna Bridge 169:a7c7b631e539 1426 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
Anna Bridge 169:a7c7b631e539 1427 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
Anna Bridge 169:a7c7b631e539 1428 } CoreDebug_Type;
Anna Bridge 169:a7c7b631e539 1429
Anna Bridge 169:a7c7b631e539 1430 /* Debug Halting Control and Status Register Definitions */
Anna Bridge 169:a7c7b631e539 1431 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
Anna Bridge 169:a7c7b631e539 1432 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
Anna Bridge 169:a7c7b631e539 1433
Anna Bridge 169:a7c7b631e539 1434 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
Anna Bridge 169:a7c7b631e539 1435 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
Anna Bridge 169:a7c7b631e539 1436
Anna Bridge 169:a7c7b631e539 1437 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
Anna Bridge 169:a7c7b631e539 1438 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
Anna Bridge 169:a7c7b631e539 1439
Anna Bridge 169:a7c7b631e539 1440 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
Anna Bridge 169:a7c7b631e539 1441 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
Anna Bridge 169:a7c7b631e539 1442
Anna Bridge 169:a7c7b631e539 1443 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
Anna Bridge 169:a7c7b631e539 1444 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
Anna Bridge 169:a7c7b631e539 1445
Anna Bridge 169:a7c7b631e539 1446 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
Anna Bridge 169:a7c7b631e539 1447 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
Anna Bridge 169:a7c7b631e539 1448
Anna Bridge 169:a7c7b631e539 1449 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
Anna Bridge 169:a7c7b631e539 1450 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
Anna Bridge 169:a7c7b631e539 1451
Anna Bridge 169:a7c7b631e539 1452 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
Anna Bridge 169:a7c7b631e539 1453 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
Anna Bridge 169:a7c7b631e539 1454
Anna Bridge 169:a7c7b631e539 1455 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
Anna Bridge 169:a7c7b631e539 1456 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
Anna Bridge 169:a7c7b631e539 1457
Anna Bridge 169:a7c7b631e539 1458 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
Anna Bridge 169:a7c7b631e539 1459 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
Anna Bridge 169:a7c7b631e539 1460
Anna Bridge 169:a7c7b631e539 1461 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
Anna Bridge 169:a7c7b631e539 1462 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
Anna Bridge 169:a7c7b631e539 1463
Anna Bridge 169:a7c7b631e539 1464 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Anna Bridge 169:a7c7b631e539 1465 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
Anna Bridge 169:a7c7b631e539 1466
Anna Bridge 169:a7c7b631e539 1467 /* Debug Core Register Selector Register Definitions */
Anna Bridge 169:a7c7b631e539 1468 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
Anna Bridge 169:a7c7b631e539 1469 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
Anna Bridge 169:a7c7b631e539 1470
Anna Bridge 169:a7c7b631e539 1471 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
Anna Bridge 169:a7c7b631e539 1472 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
Anna Bridge 169:a7c7b631e539 1473
Anna Bridge 169:a7c7b631e539 1474 /* Debug Exception and Monitor Control Register Definitions */
Anna Bridge 169:a7c7b631e539 1475 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
Anna Bridge 169:a7c7b631e539 1476 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
Anna Bridge 169:a7c7b631e539 1477
Anna Bridge 169:a7c7b631e539 1478 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
Anna Bridge 169:a7c7b631e539 1479 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
Anna Bridge 169:a7c7b631e539 1480
Anna Bridge 169:a7c7b631e539 1481 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
Anna Bridge 169:a7c7b631e539 1482 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
Anna Bridge 169:a7c7b631e539 1483
Anna Bridge 169:a7c7b631e539 1484 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
Anna Bridge 169:a7c7b631e539 1485 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
Anna Bridge 169:a7c7b631e539 1486
Anna Bridge 169:a7c7b631e539 1487 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
Anna Bridge 169:a7c7b631e539 1488 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
Anna Bridge 169:a7c7b631e539 1489
Anna Bridge 169:a7c7b631e539 1490 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
Anna Bridge 169:a7c7b631e539 1491 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
Anna Bridge 169:a7c7b631e539 1492
Anna Bridge 169:a7c7b631e539 1493 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
Anna Bridge 169:a7c7b631e539 1494 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
Anna Bridge 169:a7c7b631e539 1495
Anna Bridge 169:a7c7b631e539 1496 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
Anna Bridge 169:a7c7b631e539 1497 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
Anna Bridge 169:a7c7b631e539 1498
Anna Bridge 169:a7c7b631e539 1499 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
Anna Bridge 169:a7c7b631e539 1500 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
Anna Bridge 169:a7c7b631e539 1501
Anna Bridge 169:a7c7b631e539 1502 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
Anna Bridge 169:a7c7b631e539 1503 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
Anna Bridge 169:a7c7b631e539 1504
Anna Bridge 169:a7c7b631e539 1505 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
Anna Bridge 169:a7c7b631e539 1506 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
Anna Bridge 169:a7c7b631e539 1507
Anna Bridge 169:a7c7b631e539 1508 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
Anna Bridge 169:a7c7b631e539 1509 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
Anna Bridge 169:a7c7b631e539 1510
Anna Bridge 169:a7c7b631e539 1511 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
Anna Bridge 169:a7c7b631e539 1512 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
Anna Bridge 169:a7c7b631e539 1513
Anna Bridge 169:a7c7b631e539 1514 /*@} end of group CMSIS_CoreDebug */
Anna Bridge 169:a7c7b631e539 1515
Anna Bridge 169:a7c7b631e539 1516
Anna Bridge 169:a7c7b631e539 1517 /**
Anna Bridge 169:a7c7b631e539 1518 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 1519 \defgroup CMSIS_core_bitfield Core register bit field macros
Anna Bridge 169:a7c7b631e539 1520 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
Anna Bridge 169:a7c7b631e539 1521 @{
Anna Bridge 169:a7c7b631e539 1522 */
Anna Bridge 169:a7c7b631e539 1523
Anna Bridge 169:a7c7b631e539 1524 /**
Anna Bridge 169:a7c7b631e539 1525 \brief Mask and shift a bit field value for use in a register bit range.
Anna Bridge 169:a7c7b631e539 1526 \param[in] field Name of the register bit field.
Anna Bridge 169:a7c7b631e539 1527 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
Anna Bridge 169:a7c7b631e539 1528 \return Masked and shifted value.
Anna Bridge 169:a7c7b631e539 1529 */
Anna Bridge 169:a7c7b631e539 1530 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Anna Bridge 169:a7c7b631e539 1531
Anna Bridge 169:a7c7b631e539 1532 /**
Anna Bridge 169:a7c7b631e539 1533 \brief Mask and shift a register value to extract a bit filed value.
Anna Bridge 169:a7c7b631e539 1534 \param[in] field Name of the register bit field.
Anna Bridge 169:a7c7b631e539 1535 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
Anna Bridge 169:a7c7b631e539 1536 \return Masked and shifted bit field value.
Anna Bridge 169:a7c7b631e539 1537 */
Anna Bridge 169:a7c7b631e539 1538 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
Anna Bridge 169:a7c7b631e539 1539
Anna Bridge 169:a7c7b631e539 1540 /*@} end of group CMSIS_core_bitfield */
Anna Bridge 169:a7c7b631e539 1541
Anna Bridge 169:a7c7b631e539 1542
Anna Bridge 169:a7c7b631e539 1543 /**
Anna Bridge 169:a7c7b631e539 1544 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 1545 \defgroup CMSIS_core_base Core Definitions
Anna Bridge 169:a7c7b631e539 1546 \brief Definitions for base addresses, unions, and structures.
Anna Bridge 169:a7c7b631e539 1547 @{
Anna Bridge 169:a7c7b631e539 1548 */
Anna Bridge 169:a7c7b631e539 1549
Anna Bridge 169:a7c7b631e539 1550 /* Memory mapping of Core Hardware */
Anna Bridge 169:a7c7b631e539 1551 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Anna Bridge 169:a7c7b631e539 1552 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
Anna Bridge 169:a7c7b631e539 1553 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
Anna Bridge 169:a7c7b631e539 1554 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
Anna Bridge 169:a7c7b631e539 1555 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
Anna Bridge 169:a7c7b631e539 1556 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Anna Bridge 169:a7c7b631e539 1557 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Anna Bridge 169:a7c7b631e539 1558 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Anna Bridge 169:a7c7b631e539 1559
Anna Bridge 169:a7c7b631e539 1560 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
Anna Bridge 169:a7c7b631e539 1561 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Anna Bridge 169:a7c7b631e539 1562 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Anna Bridge 169:a7c7b631e539 1563 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Anna Bridge 169:a7c7b631e539 1564 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
Anna Bridge 169:a7c7b631e539 1565 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
Anna Bridge 169:a7c7b631e539 1566 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
Anna Bridge 169:a7c7b631e539 1567 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
Anna Bridge 169:a7c7b631e539 1568
Anna Bridge 169:a7c7b631e539 1569 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 1570 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Anna Bridge 169:a7c7b631e539 1571 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Anna Bridge 169:a7c7b631e539 1572 #endif
Anna Bridge 169:a7c7b631e539 1573
Anna Bridge 169:a7c7b631e539 1574 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
Anna Bridge 169:a7c7b631e539 1575 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
Anna Bridge 169:a7c7b631e539 1576
Anna Bridge 169:a7c7b631e539 1577 /*@} */
Anna Bridge 169:a7c7b631e539 1578
Anna Bridge 169:a7c7b631e539 1579
Anna Bridge 169:a7c7b631e539 1580
Anna Bridge 169:a7c7b631e539 1581 /*******************************************************************************
Anna Bridge 169:a7c7b631e539 1582 * Hardware Abstraction Layer
Anna Bridge 169:a7c7b631e539 1583 Core Function Interface contains:
Anna Bridge 169:a7c7b631e539 1584 - Core NVIC Functions
Anna Bridge 169:a7c7b631e539 1585 - Core SysTick Functions
Anna Bridge 169:a7c7b631e539 1586 - Core Debug Functions
Anna Bridge 169:a7c7b631e539 1587 - Core Register Access Functions
Anna Bridge 169:a7c7b631e539 1588 ******************************************************************************/
Anna Bridge 169:a7c7b631e539 1589 /**
Anna Bridge 169:a7c7b631e539 1590 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Anna Bridge 169:a7c7b631e539 1591 */
Anna Bridge 169:a7c7b631e539 1592
Anna Bridge 169:a7c7b631e539 1593
Anna Bridge 169:a7c7b631e539 1594
Anna Bridge 169:a7c7b631e539 1595 /* ########################## NVIC functions #################################### */
Anna Bridge 169:a7c7b631e539 1596 /**
Anna Bridge 169:a7c7b631e539 1597 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 169:a7c7b631e539 1598 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Anna Bridge 169:a7c7b631e539 1599 \brief Functions that manage interrupts and exceptions via the NVIC.
Anna Bridge 169:a7c7b631e539 1600 @{
Anna Bridge 169:a7c7b631e539 1601 */
Anna Bridge 169:a7c7b631e539 1602
Anna Bridge 169:a7c7b631e539 1603 #ifdef CMSIS_NVIC_VIRTUAL
Anna Bridge 169:a7c7b631e539 1604 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge 169:a7c7b631e539 1605 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Anna Bridge 169:a7c7b631e539 1606 #endif
Anna Bridge 169:a7c7b631e539 1607 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge 169:a7c7b631e539 1608 #else
Anna Bridge 169:a7c7b631e539 1609 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
Anna Bridge 169:a7c7b631e539 1610 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
Anna Bridge 169:a7c7b631e539 1611 #define NVIC_EnableIRQ __NVIC_EnableIRQ
Anna Bridge 169:a7c7b631e539 1612 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
Anna Bridge 169:a7c7b631e539 1613 #define NVIC_DisableIRQ __NVIC_DisableIRQ
Anna Bridge 169:a7c7b631e539 1614 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Anna Bridge 169:a7c7b631e539 1615 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Anna Bridge 169:a7c7b631e539 1616 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Anna Bridge 169:a7c7b631e539 1617 #define NVIC_GetActive __NVIC_GetActive
Anna Bridge 169:a7c7b631e539 1618 #define NVIC_SetPriority __NVIC_SetPriority
Anna Bridge 169:a7c7b631e539 1619 #define NVIC_GetPriority __NVIC_GetPriority
Anna Bridge 169:a7c7b631e539 1620 #define NVIC_SystemReset __NVIC_SystemReset
Anna Bridge 169:a7c7b631e539 1621 #endif /* CMSIS_NVIC_VIRTUAL */
Anna Bridge 169:a7c7b631e539 1622
Anna Bridge 169:a7c7b631e539 1623 #ifdef CMSIS_VECTAB_VIRTUAL
Anna Bridge 169:a7c7b631e539 1624 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge 169:a7c7b631e539 1625 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Anna Bridge 169:a7c7b631e539 1626 #endif
Anna Bridge 169:a7c7b631e539 1627 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge 169:a7c7b631e539 1628 #else
Anna Bridge 169:a7c7b631e539 1629 #define NVIC_SetVector __NVIC_SetVector
Anna Bridge 169:a7c7b631e539 1630 #define NVIC_GetVector __NVIC_GetVector
Anna Bridge 169:a7c7b631e539 1631 #endif /* (CMSIS_VECTAB_VIRTUAL) */
Anna Bridge 169:a7c7b631e539 1632
Anna Bridge 169:a7c7b631e539 1633 #define NVIC_USER_IRQ_OFFSET 16
Anna Bridge 169:a7c7b631e539 1634
Anna Bridge 169:a7c7b631e539 1635
Anna Bridge 169:a7c7b631e539 1636
Anna Bridge 169:a7c7b631e539 1637 /**
Anna Bridge 169:a7c7b631e539 1638 \brief Set Priority Grouping
Anna Bridge 169:a7c7b631e539 1639 \details Sets the priority grouping field using the required unlock sequence.
Anna Bridge 169:a7c7b631e539 1640 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Anna Bridge 169:a7c7b631e539 1641 Only values from 0..7 are used.
Anna Bridge 169:a7c7b631e539 1642 In case of a conflict between priority grouping and available
Anna Bridge 169:a7c7b631e539 1643 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Anna Bridge 169:a7c7b631e539 1644 \param [in] PriorityGroup Priority grouping field.
Anna Bridge 169:a7c7b631e539 1645 */
Anna Bridge 169:a7c7b631e539 1646 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Anna Bridge 169:a7c7b631e539 1647 {
Anna Bridge 169:a7c7b631e539 1648 uint32_t reg_value;
Anna Bridge 169:a7c7b631e539 1649 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge 169:a7c7b631e539 1650
Anna Bridge 169:a7c7b631e539 1651 reg_value = SCB->AIRCR; /* read old register configuration */
Anna Bridge 169:a7c7b631e539 1652 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Anna Bridge 169:a7c7b631e539 1653 reg_value = (reg_value |
Anna Bridge 169:a7c7b631e539 1654 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Anna Bridge 169:a7c7b631e539 1655 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
Anna Bridge 169:a7c7b631e539 1656 SCB->AIRCR = reg_value;
Anna Bridge 169:a7c7b631e539 1657 }
Anna Bridge 169:a7c7b631e539 1658
Anna Bridge 169:a7c7b631e539 1659
Anna Bridge 169:a7c7b631e539 1660 /**
Anna Bridge 169:a7c7b631e539 1661 \brief Get Priority Grouping
Anna Bridge 169:a7c7b631e539 1662 \details Reads the priority grouping field from the NVIC Interrupt Controller.
Anna Bridge 169:a7c7b631e539 1663 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Anna Bridge 169:a7c7b631e539 1664 */
Anna Bridge 169:a7c7b631e539 1665 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Anna Bridge 169:a7c7b631e539 1666 {
Anna Bridge 169:a7c7b631e539 1667 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Anna Bridge 169:a7c7b631e539 1668 }
Anna Bridge 169:a7c7b631e539 1669
Anna Bridge 169:a7c7b631e539 1670
Anna Bridge 169:a7c7b631e539 1671 /**
Anna Bridge 169:a7c7b631e539 1672 \brief Enable Interrupt
Anna Bridge 169:a7c7b631e539 1673 \details Enables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge 169:a7c7b631e539 1674 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 1675 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 1676 */
Anna Bridge 169:a7c7b631e539 1677 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 1678 {
Anna Bridge 169:a7c7b631e539 1679 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 1680 {
Anna Bridge 169:a7c7b631e539 1681 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 169:a7c7b631e539 1682 }
Anna Bridge 169:a7c7b631e539 1683 }
Anna Bridge 169:a7c7b631e539 1684
Anna Bridge 169:a7c7b631e539 1685
Anna Bridge 169:a7c7b631e539 1686 /**
Anna Bridge 169:a7c7b631e539 1687 \brief Get Interrupt Enable status
Anna Bridge 169:a7c7b631e539 1688 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
Anna Bridge 169:a7c7b631e539 1689 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 1690 \return 0 Interrupt is not enabled.
Anna Bridge 169:a7c7b631e539 1691 \return 1 Interrupt is enabled.
Anna Bridge 169:a7c7b631e539 1692 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 1693 */
Anna Bridge 169:a7c7b631e539 1694 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 1695 {
Anna Bridge 169:a7c7b631e539 1696 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 1697 {
Anna Bridge 169:a7c7b631e539 1698 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 169:a7c7b631e539 1699 }
Anna Bridge 169:a7c7b631e539 1700 else
Anna Bridge 169:a7c7b631e539 1701 {
Anna Bridge 169:a7c7b631e539 1702 return(0U);
Anna Bridge 169:a7c7b631e539 1703 }
Anna Bridge 169:a7c7b631e539 1704 }
Anna Bridge 169:a7c7b631e539 1705
Anna Bridge 169:a7c7b631e539 1706
Anna Bridge 169:a7c7b631e539 1707 /**
Anna Bridge 169:a7c7b631e539 1708 \brief Disable Interrupt
Anna Bridge 169:a7c7b631e539 1709 \details Disables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge 169:a7c7b631e539 1710 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 1711 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 1712 */
Anna Bridge 169:a7c7b631e539 1713 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 1714 {
Anna Bridge 169:a7c7b631e539 1715 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 1716 {
Anna Bridge 169:a7c7b631e539 1717 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 169:a7c7b631e539 1718 __DSB();
Anna Bridge 169:a7c7b631e539 1719 __ISB();
Anna Bridge 169:a7c7b631e539 1720 }
Anna Bridge 169:a7c7b631e539 1721 }
Anna Bridge 169:a7c7b631e539 1722
Anna Bridge 169:a7c7b631e539 1723
Anna Bridge 169:a7c7b631e539 1724 /**
Anna Bridge 169:a7c7b631e539 1725 \brief Get Pending Interrupt
Anna Bridge 169:a7c7b631e539 1726 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
Anna Bridge 169:a7c7b631e539 1727 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 1728 \return 0 Interrupt status is not pending.
Anna Bridge 169:a7c7b631e539 1729 \return 1 Interrupt status is pending.
Anna Bridge 169:a7c7b631e539 1730 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 1731 */
Anna Bridge 169:a7c7b631e539 1732 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 1733 {
Anna Bridge 169:a7c7b631e539 1734 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 1735 {
Anna Bridge 169:a7c7b631e539 1736 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 169:a7c7b631e539 1737 }
Anna Bridge 169:a7c7b631e539 1738 else
Anna Bridge 169:a7c7b631e539 1739 {
Anna Bridge 169:a7c7b631e539 1740 return(0U);
Anna Bridge 169:a7c7b631e539 1741 }
Anna Bridge 169:a7c7b631e539 1742 }
Anna Bridge 169:a7c7b631e539 1743
Anna Bridge 169:a7c7b631e539 1744
Anna Bridge 169:a7c7b631e539 1745 /**
Anna Bridge 169:a7c7b631e539 1746 \brief Set Pending Interrupt
Anna Bridge 169:a7c7b631e539 1747 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge 169:a7c7b631e539 1748 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 1749 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 1750 */
Anna Bridge 169:a7c7b631e539 1751 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 1752 {
Anna Bridge 169:a7c7b631e539 1753 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 1754 {
Anna Bridge 169:a7c7b631e539 1755 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 169:a7c7b631e539 1756 }
Anna Bridge 169:a7c7b631e539 1757 }
Anna Bridge 169:a7c7b631e539 1758
Anna Bridge 169:a7c7b631e539 1759
Anna Bridge 169:a7c7b631e539 1760 /**
Anna Bridge 169:a7c7b631e539 1761 \brief Clear Pending Interrupt
Anna Bridge 169:a7c7b631e539 1762 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge 169:a7c7b631e539 1763 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 1764 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 1765 */
Anna Bridge 169:a7c7b631e539 1766 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 1767 {
Anna Bridge 169:a7c7b631e539 1768 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 1769 {
Anna Bridge 169:a7c7b631e539 1770 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 169:a7c7b631e539 1771 }
Anna Bridge 169:a7c7b631e539 1772 }
Anna Bridge 169:a7c7b631e539 1773
Anna Bridge 169:a7c7b631e539 1774
Anna Bridge 169:a7c7b631e539 1775 /**
Anna Bridge 169:a7c7b631e539 1776 \brief Get Active Interrupt
Anna Bridge 169:a7c7b631e539 1777 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
Anna Bridge 169:a7c7b631e539 1778 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 1779 \return 0 Interrupt status is not active.
Anna Bridge 169:a7c7b631e539 1780 \return 1 Interrupt status is active.
Anna Bridge 169:a7c7b631e539 1781 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 1782 */
Anna Bridge 169:a7c7b631e539 1783 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 1784 {
Anna Bridge 169:a7c7b631e539 1785 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 1786 {
Anna Bridge 169:a7c7b631e539 1787 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 169:a7c7b631e539 1788 }
Anna Bridge 169:a7c7b631e539 1789 else
Anna Bridge 169:a7c7b631e539 1790 {
Anna Bridge 169:a7c7b631e539 1791 return(0U);
Anna Bridge 169:a7c7b631e539 1792 }
Anna Bridge 169:a7c7b631e539 1793 }
Anna Bridge 169:a7c7b631e539 1794
Anna Bridge 169:a7c7b631e539 1795
Anna Bridge 169:a7c7b631e539 1796 /**
Anna Bridge 169:a7c7b631e539 1797 \brief Set Interrupt Priority
Anna Bridge 169:a7c7b631e539 1798 \details Sets the priority of a device specific interrupt or a processor exception.
Anna Bridge 169:a7c7b631e539 1799 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 169:a7c7b631e539 1800 or negative to specify a processor exception.
Anna Bridge 169:a7c7b631e539 1801 \param [in] IRQn Interrupt number.
Anna Bridge 169:a7c7b631e539 1802 \param [in] priority Priority to set.
Anna Bridge 169:a7c7b631e539 1803 \note The priority cannot be set for every processor exception.
Anna Bridge 169:a7c7b631e539 1804 */
Anna Bridge 169:a7c7b631e539 1805 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Anna Bridge 169:a7c7b631e539 1806 {
Anna Bridge 169:a7c7b631e539 1807 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 1808 {
Anna Bridge 169:a7c7b631e539 1809 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Anna Bridge 169:a7c7b631e539 1810 }
Anna Bridge 169:a7c7b631e539 1811 else
Anna Bridge 169:a7c7b631e539 1812 {
Anna Bridge 169:a7c7b631e539 1813 SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Anna Bridge 169:a7c7b631e539 1814 }
Anna Bridge 169:a7c7b631e539 1815 }
Anna Bridge 169:a7c7b631e539 1816
Anna Bridge 169:a7c7b631e539 1817
Anna Bridge 169:a7c7b631e539 1818 /**
Anna Bridge 169:a7c7b631e539 1819 \brief Get Interrupt Priority
Anna Bridge 169:a7c7b631e539 1820 \details Reads the priority of a device specific interrupt or a processor exception.
Anna Bridge 169:a7c7b631e539 1821 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 169:a7c7b631e539 1822 or negative to specify a processor exception.
Anna Bridge 169:a7c7b631e539 1823 \param [in] IRQn Interrupt number.
Anna Bridge 169:a7c7b631e539 1824 \return Interrupt Priority.
Anna Bridge 169:a7c7b631e539 1825 Value is aligned automatically to the implemented priority bits of the microcontroller.
Anna Bridge 169:a7c7b631e539 1826 */
Anna Bridge 169:a7c7b631e539 1827 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 1828 {
Anna Bridge 169:a7c7b631e539 1829
Anna Bridge 169:a7c7b631e539 1830 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 1831 {
Anna Bridge 169:a7c7b631e539 1832 return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 169:a7c7b631e539 1833 }
Anna Bridge 169:a7c7b631e539 1834 else
Anna Bridge 169:a7c7b631e539 1835 {
Anna Bridge 169:a7c7b631e539 1836 return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 169:a7c7b631e539 1837 }
Anna Bridge 169:a7c7b631e539 1838 }
Anna Bridge 169:a7c7b631e539 1839
Anna Bridge 169:a7c7b631e539 1840
Anna Bridge 169:a7c7b631e539 1841 /**
Anna Bridge 169:a7c7b631e539 1842 \brief Encode Priority
Anna Bridge 169:a7c7b631e539 1843 \details Encodes the priority for an interrupt with the given priority group,
Anna Bridge 169:a7c7b631e539 1844 preemptive priority value, and subpriority value.
Anna Bridge 169:a7c7b631e539 1845 In case of a conflict between priority grouping and available
Anna Bridge 169:a7c7b631e539 1846 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Anna Bridge 169:a7c7b631e539 1847 \param [in] PriorityGroup Used priority group.
Anna Bridge 169:a7c7b631e539 1848 \param [in] PreemptPriority Preemptive priority value (starting from 0).
Anna Bridge 169:a7c7b631e539 1849 \param [in] SubPriority Subpriority value (starting from 0).
Anna Bridge 169:a7c7b631e539 1850 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Anna Bridge 169:a7c7b631e539 1851 */
Anna Bridge 169:a7c7b631e539 1852 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Anna Bridge 169:a7c7b631e539 1853 {
Anna Bridge 169:a7c7b631e539 1854 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge 169:a7c7b631e539 1855 uint32_t PreemptPriorityBits;
Anna Bridge 169:a7c7b631e539 1856 uint32_t SubPriorityBits;
Anna Bridge 169:a7c7b631e539 1857
Anna Bridge 169:a7c7b631e539 1858 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Anna Bridge 169:a7c7b631e539 1859 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Anna Bridge 169:a7c7b631e539 1860
Anna Bridge 169:a7c7b631e539 1861 return (
Anna Bridge 169:a7c7b631e539 1862 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
Anna Bridge 169:a7c7b631e539 1863 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Anna Bridge 169:a7c7b631e539 1864 );
Anna Bridge 169:a7c7b631e539 1865 }
Anna Bridge 169:a7c7b631e539 1866
Anna Bridge 169:a7c7b631e539 1867
Anna Bridge 169:a7c7b631e539 1868 /**
Anna Bridge 169:a7c7b631e539 1869 \brief Decode Priority
Anna Bridge 169:a7c7b631e539 1870 \details Decodes an interrupt priority value with a given priority group to
Anna Bridge 169:a7c7b631e539 1871 preemptive priority value and subpriority value.
Anna Bridge 169:a7c7b631e539 1872 In case of a conflict between priority grouping and available
Anna Bridge 169:a7c7b631e539 1873 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Anna Bridge 169:a7c7b631e539 1874 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Anna Bridge 169:a7c7b631e539 1875 \param [in] PriorityGroup Used priority group.
Anna Bridge 169:a7c7b631e539 1876 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
Anna Bridge 169:a7c7b631e539 1877 \param [out] pSubPriority Subpriority value (starting from 0).
Anna Bridge 169:a7c7b631e539 1878 */
Anna Bridge 169:a7c7b631e539 1879 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
Anna Bridge 169:a7c7b631e539 1880 {
Anna Bridge 169:a7c7b631e539 1881 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge 169:a7c7b631e539 1882 uint32_t PreemptPriorityBits;
Anna Bridge 169:a7c7b631e539 1883 uint32_t SubPriorityBits;
Anna Bridge 169:a7c7b631e539 1884
Anna Bridge 169:a7c7b631e539 1885 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Anna Bridge 169:a7c7b631e539 1886 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Anna Bridge 169:a7c7b631e539 1887
Anna Bridge 169:a7c7b631e539 1888 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Anna Bridge 169:a7c7b631e539 1889 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Anna Bridge 169:a7c7b631e539 1890 }
Anna Bridge 169:a7c7b631e539 1891
Anna Bridge 169:a7c7b631e539 1892
Anna Bridge 169:a7c7b631e539 1893 /**
Anna Bridge 169:a7c7b631e539 1894 \brief Set Interrupt Vector
Anna Bridge 169:a7c7b631e539 1895 \details Sets an interrupt vector in SRAM based interrupt vector table.
Anna Bridge 169:a7c7b631e539 1896 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 169:a7c7b631e539 1897 or negative to specify a processor exception.
Anna Bridge 169:a7c7b631e539 1898 VTOR must been relocated to SRAM before.
Anna Bridge 169:a7c7b631e539 1899 \param [in] IRQn Interrupt number
Anna Bridge 169:a7c7b631e539 1900 \param [in] vector Address of interrupt handler function
Anna Bridge 169:a7c7b631e539 1901 */
Anna Bridge 169:a7c7b631e539 1902 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Anna Bridge 169:a7c7b631e539 1903 {
Anna Bridge 169:a7c7b631e539 1904 uint32_t *vectors = (uint32_t *)SCB->VTOR;
Anna Bridge 169:a7c7b631e539 1905 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
Anna Bridge 169:a7c7b631e539 1906 }
Anna Bridge 169:a7c7b631e539 1907
Anna Bridge 169:a7c7b631e539 1908
Anna Bridge 169:a7c7b631e539 1909 /**
Anna Bridge 169:a7c7b631e539 1910 \brief Get Interrupt Vector
Anna Bridge 169:a7c7b631e539 1911 \details Reads an interrupt vector from interrupt vector table.
Anna Bridge 169:a7c7b631e539 1912 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 169:a7c7b631e539 1913 or negative to specify a processor exception.
Anna Bridge 169:a7c7b631e539 1914 \param [in] IRQn Interrupt number.
Anna Bridge 169:a7c7b631e539 1915 \return Address of interrupt handler function
Anna Bridge 169:a7c7b631e539 1916 */
Anna Bridge 169:a7c7b631e539 1917 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 1918 {
Anna Bridge 169:a7c7b631e539 1919 uint32_t *vectors = (uint32_t *)SCB->VTOR;
Anna Bridge 169:a7c7b631e539 1920 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
Anna Bridge 169:a7c7b631e539 1921 }
Anna Bridge 169:a7c7b631e539 1922
Anna Bridge 169:a7c7b631e539 1923
Anna Bridge 169:a7c7b631e539 1924 /**
Anna Bridge 169:a7c7b631e539 1925 \brief System Reset
Anna Bridge 169:a7c7b631e539 1926 \details Initiates a system reset request to reset the MCU.
Anna Bridge 169:a7c7b631e539 1927 */
Anna Bridge 169:a7c7b631e539 1928 __STATIC_INLINE void __NVIC_SystemReset(void)
Anna Bridge 169:a7c7b631e539 1929 {
Anna Bridge 169:a7c7b631e539 1930 __DSB(); /* Ensure all outstanding memory accesses included
Anna Bridge 169:a7c7b631e539 1931 buffered write are completed before reset */
Anna Bridge 169:a7c7b631e539 1932 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Anna Bridge 169:a7c7b631e539 1933 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
Anna Bridge 169:a7c7b631e539 1934 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Anna Bridge 169:a7c7b631e539 1935 __DSB(); /* Ensure completion of memory access */
Anna Bridge 169:a7c7b631e539 1936
Anna Bridge 169:a7c7b631e539 1937 for(;;) /* wait until reset */
Anna Bridge 169:a7c7b631e539 1938 {
Anna Bridge 169:a7c7b631e539 1939 __NOP();
Anna Bridge 169:a7c7b631e539 1940 }
Anna Bridge 169:a7c7b631e539 1941 }
Anna Bridge 169:a7c7b631e539 1942
Anna Bridge 169:a7c7b631e539 1943 /*@} end of CMSIS_Core_NVICFunctions */
Anna Bridge 169:a7c7b631e539 1944
Anna Bridge 169:a7c7b631e539 1945 /* ########################## MPU functions #################################### */
Anna Bridge 169:a7c7b631e539 1946
Anna Bridge 169:a7c7b631e539 1947 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 1948
Anna Bridge 169:a7c7b631e539 1949 #include "mpu_armv7.h"
Anna Bridge 169:a7c7b631e539 1950
Anna Bridge 169:a7c7b631e539 1951 #endif
Anna Bridge 169:a7c7b631e539 1952
Anna Bridge 169:a7c7b631e539 1953
Anna Bridge 169:a7c7b631e539 1954 /* ########################## FPU functions #################################### */
Anna Bridge 169:a7c7b631e539 1955 /**
Anna Bridge 169:a7c7b631e539 1956 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 169:a7c7b631e539 1957 \defgroup CMSIS_Core_FpuFunctions FPU Functions
Anna Bridge 169:a7c7b631e539 1958 \brief Function that provides FPU type.
Anna Bridge 169:a7c7b631e539 1959 @{
Anna Bridge 169:a7c7b631e539 1960 */
Anna Bridge 169:a7c7b631e539 1961
Anna Bridge 169:a7c7b631e539 1962 /**
Anna Bridge 169:a7c7b631e539 1963 \brief get FPU type
Anna Bridge 169:a7c7b631e539 1964 \details returns the FPU type
Anna Bridge 169:a7c7b631e539 1965 \returns
Anna Bridge 169:a7c7b631e539 1966 - \b 0: No FPU
Anna Bridge 169:a7c7b631e539 1967 - \b 1: Single precision FPU
Anna Bridge 169:a7c7b631e539 1968 - \b 2: Double + Single precision FPU
Anna Bridge 169:a7c7b631e539 1969 */
Anna Bridge 169:a7c7b631e539 1970 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
Anna Bridge 169:a7c7b631e539 1971 {
Anna Bridge 169:a7c7b631e539 1972 uint32_t mvfr0;
Anna Bridge 169:a7c7b631e539 1973
Anna Bridge 169:a7c7b631e539 1974 mvfr0 = FPU->MVFR0;
Anna Bridge 169:a7c7b631e539 1975 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
Anna Bridge 169:a7c7b631e539 1976 {
Anna Bridge 169:a7c7b631e539 1977 return 1U; /* Single precision FPU */
Anna Bridge 169:a7c7b631e539 1978 }
Anna Bridge 169:a7c7b631e539 1979 else
Anna Bridge 169:a7c7b631e539 1980 {
Anna Bridge 169:a7c7b631e539 1981 return 0U; /* No FPU */
Anna Bridge 169:a7c7b631e539 1982 }
Anna Bridge 169:a7c7b631e539 1983 }
Anna Bridge 169:a7c7b631e539 1984
Anna Bridge 169:a7c7b631e539 1985
Anna Bridge 169:a7c7b631e539 1986 /*@} end of CMSIS_Core_FpuFunctions */
Anna Bridge 169:a7c7b631e539 1987
Anna Bridge 169:a7c7b631e539 1988
Anna Bridge 169:a7c7b631e539 1989
Anna Bridge 169:a7c7b631e539 1990 /* ################################## SysTick function ############################################ */
Anna Bridge 169:a7c7b631e539 1991 /**
Anna Bridge 169:a7c7b631e539 1992 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 169:a7c7b631e539 1993 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Anna Bridge 169:a7c7b631e539 1994 \brief Functions that configure the System.
Anna Bridge 169:a7c7b631e539 1995 @{
Anna Bridge 169:a7c7b631e539 1996 */
Anna Bridge 169:a7c7b631e539 1997
Anna Bridge 169:a7c7b631e539 1998 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
Anna Bridge 169:a7c7b631e539 1999
Anna Bridge 169:a7c7b631e539 2000 /**
Anna Bridge 169:a7c7b631e539 2001 \brief System Tick Configuration
Anna Bridge 169:a7c7b631e539 2002 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Anna Bridge 169:a7c7b631e539 2003 Counter is in free running mode to generate periodic interrupts.
Anna Bridge 169:a7c7b631e539 2004 \param [in] ticks Number of ticks between two interrupts.
Anna Bridge 169:a7c7b631e539 2005 \return 0 Function succeeded.
Anna Bridge 169:a7c7b631e539 2006 \return 1 Function failed.
Anna Bridge 169:a7c7b631e539 2007 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Anna Bridge 169:a7c7b631e539 2008 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Anna Bridge 169:a7c7b631e539 2009 must contain a vendor-specific implementation of this function.
Anna Bridge 169:a7c7b631e539 2010 */
Anna Bridge 169:a7c7b631e539 2011 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Anna Bridge 169:a7c7b631e539 2012 {
Anna Bridge 169:a7c7b631e539 2013 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Anna Bridge 169:a7c7b631e539 2014 {
Anna Bridge 169:a7c7b631e539 2015 return (1UL); /* Reload value impossible */
Anna Bridge 169:a7c7b631e539 2016 }
Anna Bridge 169:a7c7b631e539 2017
Anna Bridge 169:a7c7b631e539 2018 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Anna Bridge 169:a7c7b631e539 2019 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Anna Bridge 169:a7c7b631e539 2020 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Anna Bridge 169:a7c7b631e539 2021 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Anna Bridge 169:a7c7b631e539 2022 SysTick_CTRL_TICKINT_Msk |
Anna Bridge 169:a7c7b631e539 2023 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Anna Bridge 169:a7c7b631e539 2024 return (0UL); /* Function successful */
Anna Bridge 169:a7c7b631e539 2025 }
Anna Bridge 169:a7c7b631e539 2026
Anna Bridge 169:a7c7b631e539 2027 #endif
Anna Bridge 169:a7c7b631e539 2028
Anna Bridge 169:a7c7b631e539 2029 /*@} end of CMSIS_Core_SysTickFunctions */
Anna Bridge 169:a7c7b631e539 2030
Anna Bridge 169:a7c7b631e539 2031
Anna Bridge 169:a7c7b631e539 2032
Anna Bridge 169:a7c7b631e539 2033 /* ##################################### Debug In/Output function ########################################### */
Anna Bridge 169:a7c7b631e539 2034 /**
Anna Bridge 169:a7c7b631e539 2035 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 169:a7c7b631e539 2036 \defgroup CMSIS_core_DebugFunctions ITM Functions
Anna Bridge 169:a7c7b631e539 2037 \brief Functions that access the ITM debug interface.
Anna Bridge 169:a7c7b631e539 2038 @{
Anna Bridge 169:a7c7b631e539 2039 */
Anna Bridge 169:a7c7b631e539 2040
Anna Bridge 169:a7c7b631e539 2041 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
Anna Bridge 169:a7c7b631e539 2042 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
Anna Bridge 169:a7c7b631e539 2043
Anna Bridge 169:a7c7b631e539 2044
Anna Bridge 169:a7c7b631e539 2045 /**
Anna Bridge 169:a7c7b631e539 2046 \brief ITM Send Character
Anna Bridge 169:a7c7b631e539 2047 \details Transmits a character via the ITM channel 0, and
Anna Bridge 169:a7c7b631e539 2048 \li Just returns when no debugger is connected that has booked the output.
Anna Bridge 169:a7c7b631e539 2049 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Anna Bridge 169:a7c7b631e539 2050 \param [in] ch Character to transmit.
Anna Bridge 169:a7c7b631e539 2051 \returns Character to transmit.
Anna Bridge 169:a7c7b631e539 2052 */
Anna Bridge 169:a7c7b631e539 2053 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Anna Bridge 169:a7c7b631e539 2054 {
Anna Bridge 169:a7c7b631e539 2055 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Anna Bridge 169:a7c7b631e539 2056 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Anna Bridge 169:a7c7b631e539 2057 {
Anna Bridge 169:a7c7b631e539 2058 while (ITM->PORT[0U].u32 == 0UL)
Anna Bridge 169:a7c7b631e539 2059 {
Anna Bridge 169:a7c7b631e539 2060 __NOP();
Anna Bridge 169:a7c7b631e539 2061 }
Anna Bridge 169:a7c7b631e539 2062 ITM->PORT[0U].u8 = (uint8_t)ch;
Anna Bridge 169:a7c7b631e539 2063 }
Anna Bridge 169:a7c7b631e539 2064 return (ch);
Anna Bridge 169:a7c7b631e539 2065 }
Anna Bridge 169:a7c7b631e539 2066
Anna Bridge 169:a7c7b631e539 2067
Anna Bridge 169:a7c7b631e539 2068 /**
Anna Bridge 169:a7c7b631e539 2069 \brief ITM Receive Character
Anna Bridge 169:a7c7b631e539 2070 \details Inputs a character via the external variable \ref ITM_RxBuffer.
Anna Bridge 169:a7c7b631e539 2071 \return Received character.
Anna Bridge 169:a7c7b631e539 2072 \return -1 No character pending.
Anna Bridge 169:a7c7b631e539 2073 */
Anna Bridge 169:a7c7b631e539 2074 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
Anna Bridge 169:a7c7b631e539 2075 {
Anna Bridge 169:a7c7b631e539 2076 int32_t ch = -1; /* no character available */
Anna Bridge 169:a7c7b631e539 2077
Anna Bridge 169:a7c7b631e539 2078 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
Anna Bridge 169:a7c7b631e539 2079 {
Anna Bridge 169:a7c7b631e539 2080 ch = ITM_RxBuffer;
Anna Bridge 169:a7c7b631e539 2081 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Anna Bridge 169:a7c7b631e539 2082 }
Anna Bridge 169:a7c7b631e539 2083
Anna Bridge 169:a7c7b631e539 2084 return (ch);
Anna Bridge 169:a7c7b631e539 2085 }
Anna Bridge 169:a7c7b631e539 2086
Anna Bridge 169:a7c7b631e539 2087
Anna Bridge 169:a7c7b631e539 2088 /**
Anna Bridge 169:a7c7b631e539 2089 \brief ITM Check Character
Anna Bridge 169:a7c7b631e539 2090 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Anna Bridge 169:a7c7b631e539 2091 \return 0 No character available.
Anna Bridge 169:a7c7b631e539 2092 \return 1 Character available.
Anna Bridge 169:a7c7b631e539 2093 */
Anna Bridge 169:a7c7b631e539 2094 __STATIC_INLINE int32_t ITM_CheckChar (void)
Anna Bridge 169:a7c7b631e539 2095 {
Anna Bridge 169:a7c7b631e539 2096
Anna Bridge 169:a7c7b631e539 2097 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
Anna Bridge 169:a7c7b631e539 2098 {
Anna Bridge 169:a7c7b631e539 2099 return (0); /* no character available */
Anna Bridge 169:a7c7b631e539 2100 }
Anna Bridge 169:a7c7b631e539 2101 else
Anna Bridge 169:a7c7b631e539 2102 {
Anna Bridge 169:a7c7b631e539 2103 return (1); /* character available */
Anna Bridge 169:a7c7b631e539 2104 }
Anna Bridge 169:a7c7b631e539 2105 }
Anna Bridge 169:a7c7b631e539 2106
Anna Bridge 169:a7c7b631e539 2107 /*@} end of CMSIS_core_DebugFunctions */
Anna Bridge 169:a7c7b631e539 2108
Anna Bridge 169:a7c7b631e539 2109
Anna Bridge 169:a7c7b631e539 2110
Anna Bridge 169:a7c7b631e539 2111
Anna Bridge 169:a7c7b631e539 2112 #ifdef __cplusplus
Anna Bridge 169:a7c7b631e539 2113 }
Anna Bridge 169:a7c7b631e539 2114 #endif
Anna Bridge 169:a7c7b631e539 2115
Anna Bridge 169:a7c7b631e539 2116 #endif /* __CORE_CM4_H_DEPENDANT */
Anna Bridge 169:a7c7b631e539 2117
Anna Bridge 169:a7c7b631e539 2118 #endif /* __CMSIS_GENERIC */