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TARGET_MAX32625PICO_NO_BOOT/core_cm0plus.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 15:38:59 2018 +0100
Revision:
169:a7c7b631e539
mbed library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 169:a7c7b631e539 1 /**************************************************************************//**
Anna Bridge 169:a7c7b631e539 2 * @file core_cm0plus.h
Anna Bridge 169:a7c7b631e539 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Anna Bridge 169:a7c7b631e539 4 * @version V5.0.4
Anna Bridge 169:a7c7b631e539 5 * @date 10. January 2018
Anna Bridge 169:a7c7b631e539 6 ******************************************************************************/
Anna Bridge 169:a7c7b631e539 7 /*
Anna Bridge 169:a7c7b631e539 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
Anna Bridge 169:a7c7b631e539 9 *
Anna Bridge 169:a7c7b631e539 10 * SPDX-License-Identifier: Apache-2.0
Anna Bridge 169:a7c7b631e539 11 *
Anna Bridge 169:a7c7b631e539 12 * Licensed under the Apache License, Version 2.0 (the License); you may
Anna Bridge 169:a7c7b631e539 13 * not use this file except in compliance with the License.
Anna Bridge 169:a7c7b631e539 14 * You may obtain a copy of the License at
Anna Bridge 169:a7c7b631e539 15 *
Anna Bridge 169:a7c7b631e539 16 * www.apache.org/licenses/LICENSE-2.0
Anna Bridge 169:a7c7b631e539 17 *
Anna Bridge 169:a7c7b631e539 18 * Unless required by applicable law or agreed to in writing, software
Anna Bridge 169:a7c7b631e539 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Anna Bridge 169:a7c7b631e539 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Anna Bridge 169:a7c7b631e539 21 * See the License for the specific language governing permissions and
Anna Bridge 169:a7c7b631e539 22 * limitations under the License.
Anna Bridge 169:a7c7b631e539 23 */
Anna Bridge 169:a7c7b631e539 24
Anna Bridge 169:a7c7b631e539 25 #if defined ( __ICCARM__ )
Anna Bridge 169:a7c7b631e539 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 169:a7c7b631e539 27 #elif defined (__clang__)
Anna Bridge 169:a7c7b631e539 28 #pragma clang system_header /* treat file as system include file */
Anna Bridge 169:a7c7b631e539 29 #endif
Anna Bridge 169:a7c7b631e539 30
Anna Bridge 169:a7c7b631e539 31 #ifndef __CORE_CM0PLUS_H_GENERIC
Anna Bridge 169:a7c7b631e539 32 #define __CORE_CM0PLUS_H_GENERIC
Anna Bridge 169:a7c7b631e539 33
Anna Bridge 169:a7c7b631e539 34 #include <stdint.h>
Anna Bridge 169:a7c7b631e539 35
Anna Bridge 169:a7c7b631e539 36 #ifdef __cplusplus
Anna Bridge 169:a7c7b631e539 37 extern "C" {
Anna Bridge 169:a7c7b631e539 38 #endif
Anna Bridge 169:a7c7b631e539 39
Anna Bridge 169:a7c7b631e539 40 /**
Anna Bridge 169:a7c7b631e539 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Anna Bridge 169:a7c7b631e539 42 CMSIS violates the following MISRA-C:2004 rules:
Anna Bridge 169:a7c7b631e539 43
Anna Bridge 169:a7c7b631e539 44 \li Required Rule 8.5, object/function definition in header file.<br>
Anna Bridge 169:a7c7b631e539 45 Function definitions in header files are used to allow 'inlining'.
Anna Bridge 169:a7c7b631e539 46
Anna Bridge 169:a7c7b631e539 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Anna Bridge 169:a7c7b631e539 48 Unions are used for effective representation of core registers.
Anna Bridge 169:a7c7b631e539 49
Anna Bridge 169:a7c7b631e539 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
Anna Bridge 169:a7c7b631e539 51 Function-like macros are used to allow more efficient code.
Anna Bridge 169:a7c7b631e539 52 */
Anna Bridge 169:a7c7b631e539 53
Anna Bridge 169:a7c7b631e539 54
Anna Bridge 169:a7c7b631e539 55 /*******************************************************************************
Anna Bridge 169:a7c7b631e539 56 * CMSIS definitions
Anna Bridge 169:a7c7b631e539 57 ******************************************************************************/
Anna Bridge 169:a7c7b631e539 58 /**
Anna Bridge 169:a7c7b631e539 59 \ingroup Cortex-M0+
Anna Bridge 169:a7c7b631e539 60 @{
Anna Bridge 169:a7c7b631e539 61 */
Anna Bridge 169:a7c7b631e539 62
Anna Bridge 169:a7c7b631e539 63 #include "cmsis_version.h"
Anna Bridge 169:a7c7b631e539 64
Anna Bridge 169:a7c7b631e539 65 /* CMSIS CM0+ definitions */
Anna Bridge 169:a7c7b631e539 66 #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
Anna Bridge 169:a7c7b631e539 67 #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
Anna Bridge 169:a7c7b631e539 68 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
Anna Bridge 169:a7c7b631e539 69 __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
Anna Bridge 169:a7c7b631e539 70
Anna Bridge 169:a7c7b631e539 71 #define __CORTEX_M (0U) /*!< Cortex-M Core */
Anna Bridge 169:a7c7b631e539 72
Anna Bridge 169:a7c7b631e539 73 /** __FPU_USED indicates whether an FPU is used or not.
Anna Bridge 169:a7c7b631e539 74 This core does not support an FPU at all
Anna Bridge 169:a7c7b631e539 75 */
Anna Bridge 169:a7c7b631e539 76 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 77
Anna Bridge 169:a7c7b631e539 78 #if defined ( __CC_ARM )
Anna Bridge 169:a7c7b631e539 79 #if defined __TARGET_FPU_VFP
Anna Bridge 169:a7c7b631e539 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 169:a7c7b631e539 81 #endif
Anna Bridge 169:a7c7b631e539 82
Anna Bridge 169:a7c7b631e539 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
Anna Bridge 169:a7c7b631e539 84 #if defined __ARM_PCS_VFP
Anna Bridge 169:a7c7b631e539 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 169:a7c7b631e539 86 #endif
Anna Bridge 169:a7c7b631e539 87
Anna Bridge 169:a7c7b631e539 88 #elif defined ( __GNUC__ )
Anna Bridge 169:a7c7b631e539 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Anna Bridge 169:a7c7b631e539 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 169:a7c7b631e539 91 #endif
Anna Bridge 169:a7c7b631e539 92
Anna Bridge 169:a7c7b631e539 93 #elif defined ( __ICCARM__ )
Anna Bridge 169:a7c7b631e539 94 #if defined __ARMVFP__
Anna Bridge 169:a7c7b631e539 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 169:a7c7b631e539 96 #endif
Anna Bridge 169:a7c7b631e539 97
Anna Bridge 169:a7c7b631e539 98 #elif defined ( __TI_ARM__ )
Anna Bridge 169:a7c7b631e539 99 #if defined __TI_VFP_SUPPORT__
Anna Bridge 169:a7c7b631e539 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 169:a7c7b631e539 101 #endif
Anna Bridge 169:a7c7b631e539 102
Anna Bridge 169:a7c7b631e539 103 #elif defined ( __TASKING__ )
Anna Bridge 169:a7c7b631e539 104 #if defined __FPU_VFP__
Anna Bridge 169:a7c7b631e539 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 169:a7c7b631e539 106 #endif
Anna Bridge 169:a7c7b631e539 107
Anna Bridge 169:a7c7b631e539 108 #elif defined ( __CSMC__ )
Anna Bridge 169:a7c7b631e539 109 #if ( __CSMC__ & 0x400U)
Anna Bridge 169:a7c7b631e539 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 169:a7c7b631e539 111 #endif
Anna Bridge 169:a7c7b631e539 112
Anna Bridge 169:a7c7b631e539 113 #endif
Anna Bridge 169:a7c7b631e539 114
Anna Bridge 169:a7c7b631e539 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
Anna Bridge 169:a7c7b631e539 116
Anna Bridge 169:a7c7b631e539 117
Anna Bridge 169:a7c7b631e539 118 #ifdef __cplusplus
Anna Bridge 169:a7c7b631e539 119 }
Anna Bridge 169:a7c7b631e539 120 #endif
Anna Bridge 169:a7c7b631e539 121
Anna Bridge 169:a7c7b631e539 122 #endif /* __CORE_CM0PLUS_H_GENERIC */
Anna Bridge 169:a7c7b631e539 123
Anna Bridge 169:a7c7b631e539 124 #ifndef __CMSIS_GENERIC
Anna Bridge 169:a7c7b631e539 125
Anna Bridge 169:a7c7b631e539 126 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Anna Bridge 169:a7c7b631e539 127 #define __CORE_CM0PLUS_H_DEPENDANT
Anna Bridge 169:a7c7b631e539 128
Anna Bridge 169:a7c7b631e539 129 #ifdef __cplusplus
Anna Bridge 169:a7c7b631e539 130 extern "C" {
Anna Bridge 169:a7c7b631e539 131 #endif
Anna Bridge 169:a7c7b631e539 132
Anna Bridge 169:a7c7b631e539 133 /* check device defines and use defaults */
Anna Bridge 169:a7c7b631e539 134 #if defined __CHECK_DEVICE_DEFINES
Anna Bridge 169:a7c7b631e539 135 #ifndef __CM0PLUS_REV
Anna Bridge 169:a7c7b631e539 136 #define __CM0PLUS_REV 0x0000U
Anna Bridge 169:a7c7b631e539 137 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Anna Bridge 169:a7c7b631e539 138 #endif
Anna Bridge 169:a7c7b631e539 139
Anna Bridge 169:a7c7b631e539 140 #ifndef __MPU_PRESENT
Anna Bridge 169:a7c7b631e539 141 #define __MPU_PRESENT 0U
Anna Bridge 169:a7c7b631e539 142 #warning "__MPU_PRESENT not defined in device header file; using default!"
Anna Bridge 169:a7c7b631e539 143 #endif
Anna Bridge 169:a7c7b631e539 144
Anna Bridge 169:a7c7b631e539 145 #ifndef __VTOR_PRESENT
Anna Bridge 169:a7c7b631e539 146 #define __VTOR_PRESENT 0U
Anna Bridge 169:a7c7b631e539 147 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Anna Bridge 169:a7c7b631e539 148 #endif
Anna Bridge 169:a7c7b631e539 149
Anna Bridge 169:a7c7b631e539 150 #ifndef __NVIC_PRIO_BITS
Anna Bridge 169:a7c7b631e539 151 #define __NVIC_PRIO_BITS 2U
Anna Bridge 169:a7c7b631e539 152 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Anna Bridge 169:a7c7b631e539 153 #endif
Anna Bridge 169:a7c7b631e539 154
Anna Bridge 169:a7c7b631e539 155 #ifndef __Vendor_SysTickConfig
Anna Bridge 169:a7c7b631e539 156 #define __Vendor_SysTickConfig 0U
Anna Bridge 169:a7c7b631e539 157 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Anna Bridge 169:a7c7b631e539 158 #endif
Anna Bridge 169:a7c7b631e539 159 #endif
Anna Bridge 169:a7c7b631e539 160
Anna Bridge 169:a7c7b631e539 161 /* IO definitions (access restrictions to peripheral registers) */
Anna Bridge 169:a7c7b631e539 162 /**
Anna Bridge 169:a7c7b631e539 163 \defgroup CMSIS_glob_defs CMSIS Global Defines
Anna Bridge 169:a7c7b631e539 164
Anna Bridge 169:a7c7b631e539 165 <strong>IO Type Qualifiers</strong> are used
Anna Bridge 169:a7c7b631e539 166 \li to specify the access to peripheral variables.
Anna Bridge 169:a7c7b631e539 167 \li for automatic generation of peripheral register debug information.
Anna Bridge 169:a7c7b631e539 168 */
Anna Bridge 169:a7c7b631e539 169 #ifdef __cplusplus
Anna Bridge 169:a7c7b631e539 170 #define __I volatile /*!< Defines 'read only' permissions */
Anna Bridge 169:a7c7b631e539 171 #else
Anna Bridge 169:a7c7b631e539 172 #define __I volatile const /*!< Defines 'read only' permissions */
Anna Bridge 169:a7c7b631e539 173 #endif
Anna Bridge 169:a7c7b631e539 174 #define __O volatile /*!< Defines 'write only' permissions */
Anna Bridge 169:a7c7b631e539 175 #define __IO volatile /*!< Defines 'read / write' permissions */
Anna Bridge 169:a7c7b631e539 176
Anna Bridge 169:a7c7b631e539 177 /* following defines should be used for structure members */
Anna Bridge 169:a7c7b631e539 178 #define __IM volatile const /*! Defines 'read only' structure member permissions */
Anna Bridge 169:a7c7b631e539 179 #define __OM volatile /*! Defines 'write only' structure member permissions */
Anna Bridge 169:a7c7b631e539 180 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
Anna Bridge 169:a7c7b631e539 181
Anna Bridge 169:a7c7b631e539 182 /*@} end of group Cortex-M0+ */
Anna Bridge 169:a7c7b631e539 183
Anna Bridge 169:a7c7b631e539 184
Anna Bridge 169:a7c7b631e539 185
Anna Bridge 169:a7c7b631e539 186 /*******************************************************************************
Anna Bridge 169:a7c7b631e539 187 * Register Abstraction
Anna Bridge 169:a7c7b631e539 188 Core Register contain:
Anna Bridge 169:a7c7b631e539 189 - Core Register
Anna Bridge 169:a7c7b631e539 190 - Core NVIC Register
Anna Bridge 169:a7c7b631e539 191 - Core SCB Register
Anna Bridge 169:a7c7b631e539 192 - Core SysTick Register
Anna Bridge 169:a7c7b631e539 193 - Core MPU Register
Anna Bridge 169:a7c7b631e539 194 ******************************************************************************/
Anna Bridge 169:a7c7b631e539 195 /**
Anna Bridge 169:a7c7b631e539 196 \defgroup CMSIS_core_register Defines and Type Definitions
Anna Bridge 169:a7c7b631e539 197 \brief Type definitions and defines for Cortex-M processor based devices.
Anna Bridge 169:a7c7b631e539 198 */
Anna Bridge 169:a7c7b631e539 199
Anna Bridge 169:a7c7b631e539 200 /**
Anna Bridge 169:a7c7b631e539 201 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 202 \defgroup CMSIS_CORE Status and Control Registers
Anna Bridge 169:a7c7b631e539 203 \brief Core Register type definitions.
Anna Bridge 169:a7c7b631e539 204 @{
Anna Bridge 169:a7c7b631e539 205 */
Anna Bridge 169:a7c7b631e539 206
Anna Bridge 169:a7c7b631e539 207 /**
Anna Bridge 169:a7c7b631e539 208 \brief Union type to access the Application Program Status Register (APSR).
Anna Bridge 169:a7c7b631e539 209 */
Anna Bridge 169:a7c7b631e539 210 typedef union
Anna Bridge 169:a7c7b631e539 211 {
Anna Bridge 169:a7c7b631e539 212 struct
Anna Bridge 169:a7c7b631e539 213 {
Anna Bridge 169:a7c7b631e539 214 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Anna Bridge 169:a7c7b631e539 215 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Anna Bridge 169:a7c7b631e539 216 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Anna Bridge 169:a7c7b631e539 217 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Anna Bridge 169:a7c7b631e539 218 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Anna Bridge 169:a7c7b631e539 219 } b; /*!< Structure used for bit access */
Anna Bridge 169:a7c7b631e539 220 uint32_t w; /*!< Type used for word access */
Anna Bridge 169:a7c7b631e539 221 } APSR_Type;
Anna Bridge 169:a7c7b631e539 222
Anna Bridge 169:a7c7b631e539 223 /* APSR Register Definitions */
Anna Bridge 169:a7c7b631e539 224 #define APSR_N_Pos 31U /*!< APSR: N Position */
Anna Bridge 169:a7c7b631e539 225 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Anna Bridge 169:a7c7b631e539 226
Anna Bridge 169:a7c7b631e539 227 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
Anna Bridge 169:a7c7b631e539 228 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Anna Bridge 169:a7c7b631e539 229
Anna Bridge 169:a7c7b631e539 230 #define APSR_C_Pos 29U /*!< APSR: C Position */
Anna Bridge 169:a7c7b631e539 231 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Anna Bridge 169:a7c7b631e539 232
Anna Bridge 169:a7c7b631e539 233 #define APSR_V_Pos 28U /*!< APSR: V Position */
Anna Bridge 169:a7c7b631e539 234 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Anna Bridge 169:a7c7b631e539 235
Anna Bridge 169:a7c7b631e539 236
Anna Bridge 169:a7c7b631e539 237 /**
Anna Bridge 169:a7c7b631e539 238 \brief Union type to access the Interrupt Program Status Register (IPSR).
Anna Bridge 169:a7c7b631e539 239 */
Anna Bridge 169:a7c7b631e539 240 typedef union
Anna Bridge 169:a7c7b631e539 241 {
Anna Bridge 169:a7c7b631e539 242 struct
Anna Bridge 169:a7c7b631e539 243 {
Anna Bridge 169:a7c7b631e539 244 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Anna Bridge 169:a7c7b631e539 245 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Anna Bridge 169:a7c7b631e539 246 } b; /*!< Structure used for bit access */
Anna Bridge 169:a7c7b631e539 247 uint32_t w; /*!< Type used for word access */
Anna Bridge 169:a7c7b631e539 248 } IPSR_Type;
Anna Bridge 169:a7c7b631e539 249
Anna Bridge 169:a7c7b631e539 250 /* IPSR Register Definitions */
Anna Bridge 169:a7c7b631e539 251 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
Anna Bridge 169:a7c7b631e539 252 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Anna Bridge 169:a7c7b631e539 253
Anna Bridge 169:a7c7b631e539 254
Anna Bridge 169:a7c7b631e539 255 /**
Anna Bridge 169:a7c7b631e539 256 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Anna Bridge 169:a7c7b631e539 257 */
Anna Bridge 169:a7c7b631e539 258 typedef union
Anna Bridge 169:a7c7b631e539 259 {
Anna Bridge 169:a7c7b631e539 260 struct
Anna Bridge 169:a7c7b631e539 261 {
Anna Bridge 169:a7c7b631e539 262 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Anna Bridge 169:a7c7b631e539 263 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Anna Bridge 169:a7c7b631e539 264 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Anna Bridge 169:a7c7b631e539 265 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Anna Bridge 169:a7c7b631e539 266 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Anna Bridge 169:a7c7b631e539 267 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Anna Bridge 169:a7c7b631e539 268 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Anna Bridge 169:a7c7b631e539 269 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Anna Bridge 169:a7c7b631e539 270 } b; /*!< Structure used for bit access */
Anna Bridge 169:a7c7b631e539 271 uint32_t w; /*!< Type used for word access */
Anna Bridge 169:a7c7b631e539 272 } xPSR_Type;
Anna Bridge 169:a7c7b631e539 273
Anna Bridge 169:a7c7b631e539 274 /* xPSR Register Definitions */
Anna Bridge 169:a7c7b631e539 275 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
Anna Bridge 169:a7c7b631e539 276 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Anna Bridge 169:a7c7b631e539 277
Anna Bridge 169:a7c7b631e539 278 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
Anna Bridge 169:a7c7b631e539 279 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Anna Bridge 169:a7c7b631e539 280
Anna Bridge 169:a7c7b631e539 281 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
Anna Bridge 169:a7c7b631e539 282 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Anna Bridge 169:a7c7b631e539 283
Anna Bridge 169:a7c7b631e539 284 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
Anna Bridge 169:a7c7b631e539 285 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Anna Bridge 169:a7c7b631e539 286
Anna Bridge 169:a7c7b631e539 287 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
Anna Bridge 169:a7c7b631e539 288 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Anna Bridge 169:a7c7b631e539 289
Anna Bridge 169:a7c7b631e539 290 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
Anna Bridge 169:a7c7b631e539 291 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Anna Bridge 169:a7c7b631e539 292
Anna Bridge 169:a7c7b631e539 293
Anna Bridge 169:a7c7b631e539 294 /**
Anna Bridge 169:a7c7b631e539 295 \brief Union type to access the Control Registers (CONTROL).
Anna Bridge 169:a7c7b631e539 296 */
Anna Bridge 169:a7c7b631e539 297 typedef union
Anna Bridge 169:a7c7b631e539 298 {
Anna Bridge 169:a7c7b631e539 299 struct
Anna Bridge 169:a7c7b631e539 300 {
Anna Bridge 169:a7c7b631e539 301 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Anna Bridge 169:a7c7b631e539 302 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Anna Bridge 169:a7c7b631e539 303 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Anna Bridge 169:a7c7b631e539 304 } b; /*!< Structure used for bit access */
Anna Bridge 169:a7c7b631e539 305 uint32_t w; /*!< Type used for word access */
Anna Bridge 169:a7c7b631e539 306 } CONTROL_Type;
Anna Bridge 169:a7c7b631e539 307
Anna Bridge 169:a7c7b631e539 308 /* CONTROL Register Definitions */
Anna Bridge 169:a7c7b631e539 309 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
Anna Bridge 169:a7c7b631e539 310 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Anna Bridge 169:a7c7b631e539 311
Anna Bridge 169:a7c7b631e539 312 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
Anna Bridge 169:a7c7b631e539 313 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Anna Bridge 169:a7c7b631e539 314
Anna Bridge 169:a7c7b631e539 315 /*@} end of group CMSIS_CORE */
Anna Bridge 169:a7c7b631e539 316
Anna Bridge 169:a7c7b631e539 317
Anna Bridge 169:a7c7b631e539 318 /**
Anna Bridge 169:a7c7b631e539 319 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 320 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Anna Bridge 169:a7c7b631e539 321 \brief Type definitions for the NVIC Registers
Anna Bridge 169:a7c7b631e539 322 @{
Anna Bridge 169:a7c7b631e539 323 */
Anna Bridge 169:a7c7b631e539 324
Anna Bridge 169:a7c7b631e539 325 /**
Anna Bridge 169:a7c7b631e539 326 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Anna Bridge 169:a7c7b631e539 327 */
Anna Bridge 169:a7c7b631e539 328 typedef struct
Anna Bridge 169:a7c7b631e539 329 {
Anna Bridge 169:a7c7b631e539 330 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Anna Bridge 169:a7c7b631e539 331 uint32_t RESERVED0[31U];
Anna Bridge 169:a7c7b631e539 332 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Anna Bridge 169:a7c7b631e539 333 uint32_t RSERVED1[31U];
Anna Bridge 169:a7c7b631e539 334 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Anna Bridge 169:a7c7b631e539 335 uint32_t RESERVED2[31U];
Anna Bridge 169:a7c7b631e539 336 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Anna Bridge 169:a7c7b631e539 337 uint32_t RESERVED3[31U];
Anna Bridge 169:a7c7b631e539 338 uint32_t RESERVED4[64U];
Anna Bridge 169:a7c7b631e539 339 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Anna Bridge 169:a7c7b631e539 340 } NVIC_Type;
Anna Bridge 169:a7c7b631e539 341
Anna Bridge 169:a7c7b631e539 342 /*@} end of group CMSIS_NVIC */
Anna Bridge 169:a7c7b631e539 343
Anna Bridge 169:a7c7b631e539 344
Anna Bridge 169:a7c7b631e539 345 /**
Anna Bridge 169:a7c7b631e539 346 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 347 \defgroup CMSIS_SCB System Control Block (SCB)
Anna Bridge 169:a7c7b631e539 348 \brief Type definitions for the System Control Block Registers
Anna Bridge 169:a7c7b631e539 349 @{
Anna Bridge 169:a7c7b631e539 350 */
Anna Bridge 169:a7c7b631e539 351
Anna Bridge 169:a7c7b631e539 352 /**
Anna Bridge 169:a7c7b631e539 353 \brief Structure type to access the System Control Block (SCB).
Anna Bridge 169:a7c7b631e539 354 */
Anna Bridge 169:a7c7b631e539 355 typedef struct
Anna Bridge 169:a7c7b631e539 356 {
Anna Bridge 169:a7c7b631e539 357 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Anna Bridge 169:a7c7b631e539 358 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Anna Bridge 169:a7c7b631e539 359 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 360 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Anna Bridge 169:a7c7b631e539 361 #else
Anna Bridge 169:a7c7b631e539 362 uint32_t RESERVED0;
Anna Bridge 169:a7c7b631e539 363 #endif
Anna Bridge 169:a7c7b631e539 364 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Anna Bridge 169:a7c7b631e539 365 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Anna Bridge 169:a7c7b631e539 366 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Anna Bridge 169:a7c7b631e539 367 uint32_t RESERVED1;
Anna Bridge 169:a7c7b631e539 368 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Anna Bridge 169:a7c7b631e539 369 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Anna Bridge 169:a7c7b631e539 370 } SCB_Type;
Anna Bridge 169:a7c7b631e539 371
Anna Bridge 169:a7c7b631e539 372 /* SCB CPUID Register Definitions */
Anna Bridge 169:a7c7b631e539 373 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
Anna Bridge 169:a7c7b631e539 374 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Anna Bridge 169:a7c7b631e539 375
Anna Bridge 169:a7c7b631e539 376 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
Anna Bridge 169:a7c7b631e539 377 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Anna Bridge 169:a7c7b631e539 378
Anna Bridge 169:a7c7b631e539 379 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
Anna Bridge 169:a7c7b631e539 380 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Anna Bridge 169:a7c7b631e539 381
Anna Bridge 169:a7c7b631e539 382 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
Anna Bridge 169:a7c7b631e539 383 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Anna Bridge 169:a7c7b631e539 384
Anna Bridge 169:a7c7b631e539 385 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
Anna Bridge 169:a7c7b631e539 386 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Anna Bridge 169:a7c7b631e539 387
Anna Bridge 169:a7c7b631e539 388 /* SCB Interrupt Control State Register Definitions */
Anna Bridge 169:a7c7b631e539 389 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
Anna Bridge 169:a7c7b631e539 390 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Anna Bridge 169:a7c7b631e539 391
Anna Bridge 169:a7c7b631e539 392 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
Anna Bridge 169:a7c7b631e539 393 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Anna Bridge 169:a7c7b631e539 394
Anna Bridge 169:a7c7b631e539 395 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
Anna Bridge 169:a7c7b631e539 396 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Anna Bridge 169:a7c7b631e539 397
Anna Bridge 169:a7c7b631e539 398 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
Anna Bridge 169:a7c7b631e539 399 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Anna Bridge 169:a7c7b631e539 400
Anna Bridge 169:a7c7b631e539 401 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
Anna Bridge 169:a7c7b631e539 402 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Anna Bridge 169:a7c7b631e539 403
Anna Bridge 169:a7c7b631e539 404 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
Anna Bridge 169:a7c7b631e539 405 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Anna Bridge 169:a7c7b631e539 406
Anna Bridge 169:a7c7b631e539 407 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
Anna Bridge 169:a7c7b631e539 408 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Anna Bridge 169:a7c7b631e539 409
Anna Bridge 169:a7c7b631e539 410 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
Anna Bridge 169:a7c7b631e539 411 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Anna Bridge 169:a7c7b631e539 412
Anna Bridge 169:a7c7b631e539 413 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
Anna Bridge 169:a7c7b631e539 414 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Anna Bridge 169:a7c7b631e539 415
Anna Bridge 169:a7c7b631e539 416 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 417 /* SCB Interrupt Control State Register Definitions */
Anna Bridge 169:a7c7b631e539 418 #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
Anna Bridge 169:a7c7b631e539 419 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Anna Bridge 169:a7c7b631e539 420 #endif
Anna Bridge 169:a7c7b631e539 421
Anna Bridge 169:a7c7b631e539 422 /* SCB Application Interrupt and Reset Control Register Definitions */
Anna Bridge 169:a7c7b631e539 423 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
Anna Bridge 169:a7c7b631e539 424 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Anna Bridge 169:a7c7b631e539 425
Anna Bridge 169:a7c7b631e539 426 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
Anna Bridge 169:a7c7b631e539 427 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Anna Bridge 169:a7c7b631e539 428
Anna Bridge 169:a7c7b631e539 429 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
Anna Bridge 169:a7c7b631e539 430 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Anna Bridge 169:a7c7b631e539 431
Anna Bridge 169:a7c7b631e539 432 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
Anna Bridge 169:a7c7b631e539 433 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Anna Bridge 169:a7c7b631e539 434
Anna Bridge 169:a7c7b631e539 435 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
Anna Bridge 169:a7c7b631e539 436 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Anna Bridge 169:a7c7b631e539 437
Anna Bridge 169:a7c7b631e539 438 /* SCB System Control Register Definitions */
Anna Bridge 169:a7c7b631e539 439 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
Anna Bridge 169:a7c7b631e539 440 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Anna Bridge 169:a7c7b631e539 441
Anna Bridge 169:a7c7b631e539 442 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
Anna Bridge 169:a7c7b631e539 443 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Anna Bridge 169:a7c7b631e539 444
Anna Bridge 169:a7c7b631e539 445 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
Anna Bridge 169:a7c7b631e539 446 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Anna Bridge 169:a7c7b631e539 447
Anna Bridge 169:a7c7b631e539 448 /* SCB Configuration Control Register Definitions */
Anna Bridge 169:a7c7b631e539 449 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
Anna Bridge 169:a7c7b631e539 450 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Anna Bridge 169:a7c7b631e539 451
Anna Bridge 169:a7c7b631e539 452 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
Anna Bridge 169:a7c7b631e539 453 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Anna Bridge 169:a7c7b631e539 454
Anna Bridge 169:a7c7b631e539 455 /* SCB System Handler Control and State Register Definitions */
Anna Bridge 169:a7c7b631e539 456 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
Anna Bridge 169:a7c7b631e539 457 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Anna Bridge 169:a7c7b631e539 458
Anna Bridge 169:a7c7b631e539 459 /*@} end of group CMSIS_SCB */
Anna Bridge 169:a7c7b631e539 460
Anna Bridge 169:a7c7b631e539 461
Anna Bridge 169:a7c7b631e539 462 /**
Anna Bridge 169:a7c7b631e539 463 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 464 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Anna Bridge 169:a7c7b631e539 465 \brief Type definitions for the System Timer Registers.
Anna Bridge 169:a7c7b631e539 466 @{
Anna Bridge 169:a7c7b631e539 467 */
Anna Bridge 169:a7c7b631e539 468
Anna Bridge 169:a7c7b631e539 469 /**
Anna Bridge 169:a7c7b631e539 470 \brief Structure type to access the System Timer (SysTick).
Anna Bridge 169:a7c7b631e539 471 */
Anna Bridge 169:a7c7b631e539 472 typedef struct
Anna Bridge 169:a7c7b631e539 473 {
Anna Bridge 169:a7c7b631e539 474 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Anna Bridge 169:a7c7b631e539 475 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Anna Bridge 169:a7c7b631e539 476 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Anna Bridge 169:a7c7b631e539 477 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Anna Bridge 169:a7c7b631e539 478 } SysTick_Type;
Anna Bridge 169:a7c7b631e539 479
Anna Bridge 169:a7c7b631e539 480 /* SysTick Control / Status Register Definitions */
Anna Bridge 169:a7c7b631e539 481 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
Anna Bridge 169:a7c7b631e539 482 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Anna Bridge 169:a7c7b631e539 483
Anna Bridge 169:a7c7b631e539 484 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
Anna Bridge 169:a7c7b631e539 485 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Anna Bridge 169:a7c7b631e539 486
Anna Bridge 169:a7c7b631e539 487 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
Anna Bridge 169:a7c7b631e539 488 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Anna Bridge 169:a7c7b631e539 489
Anna Bridge 169:a7c7b631e539 490 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
Anna Bridge 169:a7c7b631e539 491 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Anna Bridge 169:a7c7b631e539 492
Anna Bridge 169:a7c7b631e539 493 /* SysTick Reload Register Definitions */
Anna Bridge 169:a7c7b631e539 494 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
Anna Bridge 169:a7c7b631e539 495 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Anna Bridge 169:a7c7b631e539 496
Anna Bridge 169:a7c7b631e539 497 /* SysTick Current Register Definitions */
Anna Bridge 169:a7c7b631e539 498 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
Anna Bridge 169:a7c7b631e539 499 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Anna Bridge 169:a7c7b631e539 500
Anna Bridge 169:a7c7b631e539 501 /* SysTick Calibration Register Definitions */
Anna Bridge 169:a7c7b631e539 502 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
Anna Bridge 169:a7c7b631e539 503 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Anna Bridge 169:a7c7b631e539 504
Anna Bridge 169:a7c7b631e539 505 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
Anna Bridge 169:a7c7b631e539 506 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Anna Bridge 169:a7c7b631e539 507
Anna Bridge 169:a7c7b631e539 508 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
Anna Bridge 169:a7c7b631e539 509 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Anna Bridge 169:a7c7b631e539 510
Anna Bridge 169:a7c7b631e539 511 /*@} end of group CMSIS_SysTick */
Anna Bridge 169:a7c7b631e539 512
Anna Bridge 169:a7c7b631e539 513 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 514 /**
Anna Bridge 169:a7c7b631e539 515 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 516 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Anna Bridge 169:a7c7b631e539 517 \brief Type definitions for the Memory Protection Unit (MPU)
Anna Bridge 169:a7c7b631e539 518 @{
Anna Bridge 169:a7c7b631e539 519 */
Anna Bridge 169:a7c7b631e539 520
Anna Bridge 169:a7c7b631e539 521 /**
Anna Bridge 169:a7c7b631e539 522 \brief Structure type to access the Memory Protection Unit (MPU).
Anna Bridge 169:a7c7b631e539 523 */
Anna Bridge 169:a7c7b631e539 524 typedef struct
Anna Bridge 169:a7c7b631e539 525 {
Anna Bridge 169:a7c7b631e539 526 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Anna Bridge 169:a7c7b631e539 527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Anna Bridge 169:a7c7b631e539 528 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Anna Bridge 169:a7c7b631e539 529 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Anna Bridge 169:a7c7b631e539 530 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Anna Bridge 169:a7c7b631e539 531 } MPU_Type;
Anna Bridge 169:a7c7b631e539 532
Anna Bridge 169:a7c7b631e539 533 #define MPU_TYPE_RALIASES 1U
Anna Bridge 169:a7c7b631e539 534
Anna Bridge 169:a7c7b631e539 535 /* MPU Type Register Definitions */
Anna Bridge 169:a7c7b631e539 536 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
Anna Bridge 169:a7c7b631e539 537 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Anna Bridge 169:a7c7b631e539 538
Anna Bridge 169:a7c7b631e539 539 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
Anna Bridge 169:a7c7b631e539 540 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Anna Bridge 169:a7c7b631e539 541
Anna Bridge 169:a7c7b631e539 542 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
Anna Bridge 169:a7c7b631e539 543 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Anna Bridge 169:a7c7b631e539 544
Anna Bridge 169:a7c7b631e539 545 /* MPU Control Register Definitions */
Anna Bridge 169:a7c7b631e539 546 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
Anna Bridge 169:a7c7b631e539 547 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Anna Bridge 169:a7c7b631e539 548
Anna Bridge 169:a7c7b631e539 549 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
Anna Bridge 169:a7c7b631e539 550 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Anna Bridge 169:a7c7b631e539 551
Anna Bridge 169:a7c7b631e539 552 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
Anna Bridge 169:a7c7b631e539 553 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Anna Bridge 169:a7c7b631e539 554
Anna Bridge 169:a7c7b631e539 555 /* MPU Region Number Register Definitions */
Anna Bridge 169:a7c7b631e539 556 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
Anna Bridge 169:a7c7b631e539 557 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Anna Bridge 169:a7c7b631e539 558
Anna Bridge 169:a7c7b631e539 559 /* MPU Region Base Address Register Definitions */
Anna Bridge 169:a7c7b631e539 560 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
Anna Bridge 169:a7c7b631e539 561 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Anna Bridge 169:a7c7b631e539 562
Anna Bridge 169:a7c7b631e539 563 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
Anna Bridge 169:a7c7b631e539 564 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Anna Bridge 169:a7c7b631e539 565
Anna Bridge 169:a7c7b631e539 566 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
Anna Bridge 169:a7c7b631e539 567 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Anna Bridge 169:a7c7b631e539 568
Anna Bridge 169:a7c7b631e539 569 /* MPU Region Attribute and Size Register Definitions */
Anna Bridge 169:a7c7b631e539 570 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
Anna Bridge 169:a7c7b631e539 571 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Anna Bridge 169:a7c7b631e539 572
Anna Bridge 169:a7c7b631e539 573 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
Anna Bridge 169:a7c7b631e539 574 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Anna Bridge 169:a7c7b631e539 575
Anna Bridge 169:a7c7b631e539 576 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
Anna Bridge 169:a7c7b631e539 577 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Anna Bridge 169:a7c7b631e539 578
Anna Bridge 169:a7c7b631e539 579 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
Anna Bridge 169:a7c7b631e539 580 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Anna Bridge 169:a7c7b631e539 581
Anna Bridge 169:a7c7b631e539 582 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
Anna Bridge 169:a7c7b631e539 583 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Anna Bridge 169:a7c7b631e539 584
Anna Bridge 169:a7c7b631e539 585 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
Anna Bridge 169:a7c7b631e539 586 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Anna Bridge 169:a7c7b631e539 587
Anna Bridge 169:a7c7b631e539 588 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
Anna Bridge 169:a7c7b631e539 589 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Anna Bridge 169:a7c7b631e539 590
Anna Bridge 169:a7c7b631e539 591 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
Anna Bridge 169:a7c7b631e539 592 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Anna Bridge 169:a7c7b631e539 593
Anna Bridge 169:a7c7b631e539 594 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
Anna Bridge 169:a7c7b631e539 595 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Anna Bridge 169:a7c7b631e539 596
Anna Bridge 169:a7c7b631e539 597 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
Anna Bridge 169:a7c7b631e539 598 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Anna Bridge 169:a7c7b631e539 599
Anna Bridge 169:a7c7b631e539 600 /*@} end of group CMSIS_MPU */
Anna Bridge 169:a7c7b631e539 601 #endif
Anna Bridge 169:a7c7b631e539 602
Anna Bridge 169:a7c7b631e539 603
Anna Bridge 169:a7c7b631e539 604 /**
Anna Bridge 169:a7c7b631e539 605 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 606 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Anna Bridge 169:a7c7b631e539 607 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Anna Bridge 169:a7c7b631e539 608 Therefore they are not covered by the Cortex-M0+ header file.
Anna Bridge 169:a7c7b631e539 609 @{
Anna Bridge 169:a7c7b631e539 610 */
Anna Bridge 169:a7c7b631e539 611 /*@} end of group CMSIS_CoreDebug */
Anna Bridge 169:a7c7b631e539 612
Anna Bridge 169:a7c7b631e539 613
Anna Bridge 169:a7c7b631e539 614 /**
Anna Bridge 169:a7c7b631e539 615 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 616 \defgroup CMSIS_core_bitfield Core register bit field macros
Anna Bridge 169:a7c7b631e539 617 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
Anna Bridge 169:a7c7b631e539 618 @{
Anna Bridge 169:a7c7b631e539 619 */
Anna Bridge 169:a7c7b631e539 620
Anna Bridge 169:a7c7b631e539 621 /**
Anna Bridge 169:a7c7b631e539 622 \brief Mask and shift a bit field value for use in a register bit range.
Anna Bridge 169:a7c7b631e539 623 \param[in] field Name of the register bit field.
Anna Bridge 169:a7c7b631e539 624 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
Anna Bridge 169:a7c7b631e539 625 \return Masked and shifted value.
Anna Bridge 169:a7c7b631e539 626 */
Anna Bridge 169:a7c7b631e539 627 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Anna Bridge 169:a7c7b631e539 628
Anna Bridge 169:a7c7b631e539 629 /**
Anna Bridge 169:a7c7b631e539 630 \brief Mask and shift a register value to extract a bit filed value.
Anna Bridge 169:a7c7b631e539 631 \param[in] field Name of the register bit field.
Anna Bridge 169:a7c7b631e539 632 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
Anna Bridge 169:a7c7b631e539 633 \return Masked and shifted bit field value.
Anna Bridge 169:a7c7b631e539 634 */
Anna Bridge 169:a7c7b631e539 635 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
Anna Bridge 169:a7c7b631e539 636
Anna Bridge 169:a7c7b631e539 637 /*@} end of group CMSIS_core_bitfield */
Anna Bridge 169:a7c7b631e539 638
Anna Bridge 169:a7c7b631e539 639
Anna Bridge 169:a7c7b631e539 640 /**
Anna Bridge 169:a7c7b631e539 641 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 642 \defgroup CMSIS_core_base Core Definitions
Anna Bridge 169:a7c7b631e539 643 \brief Definitions for base addresses, unions, and structures.
Anna Bridge 169:a7c7b631e539 644 @{
Anna Bridge 169:a7c7b631e539 645 */
Anna Bridge 169:a7c7b631e539 646
Anna Bridge 169:a7c7b631e539 647 /* Memory mapping of Core Hardware */
Anna Bridge 169:a7c7b631e539 648 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Anna Bridge 169:a7c7b631e539 649 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Anna Bridge 169:a7c7b631e539 650 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Anna Bridge 169:a7c7b631e539 651 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Anna Bridge 169:a7c7b631e539 652
Anna Bridge 169:a7c7b631e539 653 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Anna Bridge 169:a7c7b631e539 654 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Anna Bridge 169:a7c7b631e539 655 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Anna Bridge 169:a7c7b631e539 656
Anna Bridge 169:a7c7b631e539 657 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 658 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Anna Bridge 169:a7c7b631e539 659 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Anna Bridge 169:a7c7b631e539 660 #endif
Anna Bridge 169:a7c7b631e539 661
Anna Bridge 169:a7c7b631e539 662 /*@} */
Anna Bridge 169:a7c7b631e539 663
Anna Bridge 169:a7c7b631e539 664
Anna Bridge 169:a7c7b631e539 665
Anna Bridge 169:a7c7b631e539 666 /*******************************************************************************
Anna Bridge 169:a7c7b631e539 667 * Hardware Abstraction Layer
Anna Bridge 169:a7c7b631e539 668 Core Function Interface contains:
Anna Bridge 169:a7c7b631e539 669 - Core NVIC Functions
Anna Bridge 169:a7c7b631e539 670 - Core SysTick Functions
Anna Bridge 169:a7c7b631e539 671 - Core Register Access Functions
Anna Bridge 169:a7c7b631e539 672 ******************************************************************************/
Anna Bridge 169:a7c7b631e539 673 /**
Anna Bridge 169:a7c7b631e539 674 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Anna Bridge 169:a7c7b631e539 675 */
Anna Bridge 169:a7c7b631e539 676
Anna Bridge 169:a7c7b631e539 677
Anna Bridge 169:a7c7b631e539 678
Anna Bridge 169:a7c7b631e539 679 /* ########################## NVIC functions #################################### */
Anna Bridge 169:a7c7b631e539 680 /**
Anna Bridge 169:a7c7b631e539 681 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 169:a7c7b631e539 682 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Anna Bridge 169:a7c7b631e539 683 \brief Functions that manage interrupts and exceptions via the NVIC.
Anna Bridge 169:a7c7b631e539 684 @{
Anna Bridge 169:a7c7b631e539 685 */
Anna Bridge 169:a7c7b631e539 686
Anna Bridge 169:a7c7b631e539 687 #ifdef CMSIS_NVIC_VIRTUAL
Anna Bridge 169:a7c7b631e539 688 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge 169:a7c7b631e539 689 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Anna Bridge 169:a7c7b631e539 690 #endif
Anna Bridge 169:a7c7b631e539 691 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge 169:a7c7b631e539 692 #else
Anna Bridge 169:a7c7b631e539 693 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */
Anna Bridge 169:a7c7b631e539 694 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */
Anna Bridge 169:a7c7b631e539 695 #define NVIC_EnableIRQ __NVIC_EnableIRQ
Anna Bridge 169:a7c7b631e539 696 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
Anna Bridge 169:a7c7b631e539 697 #define NVIC_DisableIRQ __NVIC_DisableIRQ
Anna Bridge 169:a7c7b631e539 698 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Anna Bridge 169:a7c7b631e539 699 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Anna Bridge 169:a7c7b631e539 700 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Anna Bridge 169:a7c7b631e539 701 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
Anna Bridge 169:a7c7b631e539 702 #define NVIC_SetPriority __NVIC_SetPriority
Anna Bridge 169:a7c7b631e539 703 #define NVIC_GetPriority __NVIC_GetPriority
Anna Bridge 169:a7c7b631e539 704 #define NVIC_SystemReset __NVIC_SystemReset
Anna Bridge 169:a7c7b631e539 705 #endif /* CMSIS_NVIC_VIRTUAL */
Anna Bridge 169:a7c7b631e539 706
Anna Bridge 169:a7c7b631e539 707 #ifdef CMSIS_VECTAB_VIRTUAL
Anna Bridge 169:a7c7b631e539 708 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge 169:a7c7b631e539 709 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Anna Bridge 169:a7c7b631e539 710 #endif
Anna Bridge 169:a7c7b631e539 711 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge 169:a7c7b631e539 712 #else
Anna Bridge 169:a7c7b631e539 713 #define NVIC_SetVector __NVIC_SetVector
Anna Bridge 169:a7c7b631e539 714 #define NVIC_GetVector __NVIC_GetVector
Anna Bridge 169:a7c7b631e539 715 #endif /* (CMSIS_VECTAB_VIRTUAL) */
Anna Bridge 169:a7c7b631e539 716
Anna Bridge 169:a7c7b631e539 717 #define NVIC_USER_IRQ_OFFSET 16
Anna Bridge 169:a7c7b631e539 718
Anna Bridge 169:a7c7b631e539 719
Anna Bridge 169:a7c7b631e539 720 /* Interrupt Priorities are WORD accessible only under Armv6-M */
Anna Bridge 169:a7c7b631e539 721 /* The following MACROS handle generation of the register offset and byte masks */
Anna Bridge 169:a7c7b631e539 722 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Anna Bridge 169:a7c7b631e539 723 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Anna Bridge 169:a7c7b631e539 724 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Anna Bridge 169:a7c7b631e539 725
Anna Bridge 169:a7c7b631e539 726
Anna Bridge 169:a7c7b631e539 727 /**
Anna Bridge 169:a7c7b631e539 728 \brief Enable Interrupt
Anna Bridge 169:a7c7b631e539 729 \details Enables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge 169:a7c7b631e539 730 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 731 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 732 */
Anna Bridge 169:a7c7b631e539 733 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 734 {
Anna Bridge 169:a7c7b631e539 735 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 736 {
Anna Bridge 169:a7c7b631e539 737 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 169:a7c7b631e539 738 }
Anna Bridge 169:a7c7b631e539 739 }
Anna Bridge 169:a7c7b631e539 740
Anna Bridge 169:a7c7b631e539 741
Anna Bridge 169:a7c7b631e539 742 /**
Anna Bridge 169:a7c7b631e539 743 \brief Get Interrupt Enable status
Anna Bridge 169:a7c7b631e539 744 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
Anna Bridge 169:a7c7b631e539 745 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 746 \return 0 Interrupt is not enabled.
Anna Bridge 169:a7c7b631e539 747 \return 1 Interrupt is enabled.
Anna Bridge 169:a7c7b631e539 748 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 749 */
Anna Bridge 169:a7c7b631e539 750 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 751 {
Anna Bridge 169:a7c7b631e539 752 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 753 {
Anna Bridge 169:a7c7b631e539 754 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 169:a7c7b631e539 755 }
Anna Bridge 169:a7c7b631e539 756 else
Anna Bridge 169:a7c7b631e539 757 {
Anna Bridge 169:a7c7b631e539 758 return(0U);
Anna Bridge 169:a7c7b631e539 759 }
Anna Bridge 169:a7c7b631e539 760 }
Anna Bridge 169:a7c7b631e539 761
Anna Bridge 169:a7c7b631e539 762
Anna Bridge 169:a7c7b631e539 763 /**
Anna Bridge 169:a7c7b631e539 764 \brief Disable Interrupt
Anna Bridge 169:a7c7b631e539 765 \details Disables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge 169:a7c7b631e539 766 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 767 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 768 */
Anna Bridge 169:a7c7b631e539 769 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 770 {
Anna Bridge 169:a7c7b631e539 771 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 772 {
Anna Bridge 169:a7c7b631e539 773 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 169:a7c7b631e539 774 __DSB();
Anna Bridge 169:a7c7b631e539 775 __ISB();
Anna Bridge 169:a7c7b631e539 776 }
Anna Bridge 169:a7c7b631e539 777 }
Anna Bridge 169:a7c7b631e539 778
Anna Bridge 169:a7c7b631e539 779
Anna Bridge 169:a7c7b631e539 780 /**
Anna Bridge 169:a7c7b631e539 781 \brief Get Pending Interrupt
Anna Bridge 169:a7c7b631e539 782 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
Anna Bridge 169:a7c7b631e539 783 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 784 \return 0 Interrupt status is not pending.
Anna Bridge 169:a7c7b631e539 785 \return 1 Interrupt status is pending.
Anna Bridge 169:a7c7b631e539 786 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 787 */
Anna Bridge 169:a7c7b631e539 788 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 789 {
Anna Bridge 169:a7c7b631e539 790 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 791 {
Anna Bridge 169:a7c7b631e539 792 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 169:a7c7b631e539 793 }
Anna Bridge 169:a7c7b631e539 794 else
Anna Bridge 169:a7c7b631e539 795 {
Anna Bridge 169:a7c7b631e539 796 return(0U);
Anna Bridge 169:a7c7b631e539 797 }
Anna Bridge 169:a7c7b631e539 798 }
Anna Bridge 169:a7c7b631e539 799
Anna Bridge 169:a7c7b631e539 800
Anna Bridge 169:a7c7b631e539 801 /**
Anna Bridge 169:a7c7b631e539 802 \brief Set Pending Interrupt
Anna Bridge 169:a7c7b631e539 803 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge 169:a7c7b631e539 804 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 805 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 806 */
Anna Bridge 169:a7c7b631e539 807 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 808 {
Anna Bridge 169:a7c7b631e539 809 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 810 {
Anna Bridge 169:a7c7b631e539 811 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 169:a7c7b631e539 812 }
Anna Bridge 169:a7c7b631e539 813 }
Anna Bridge 169:a7c7b631e539 814
Anna Bridge 169:a7c7b631e539 815
Anna Bridge 169:a7c7b631e539 816 /**
Anna Bridge 169:a7c7b631e539 817 \brief Clear Pending Interrupt
Anna Bridge 169:a7c7b631e539 818 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge 169:a7c7b631e539 819 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 820 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 821 */
Anna Bridge 169:a7c7b631e539 822 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 823 {
Anna Bridge 169:a7c7b631e539 824 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 825 {
Anna Bridge 169:a7c7b631e539 826 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 169:a7c7b631e539 827 }
Anna Bridge 169:a7c7b631e539 828 }
Anna Bridge 169:a7c7b631e539 829
Anna Bridge 169:a7c7b631e539 830
Anna Bridge 169:a7c7b631e539 831 /**
Anna Bridge 169:a7c7b631e539 832 \brief Set Interrupt Priority
Anna Bridge 169:a7c7b631e539 833 \details Sets the priority of a device specific interrupt or a processor exception.
Anna Bridge 169:a7c7b631e539 834 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 169:a7c7b631e539 835 or negative to specify a processor exception.
Anna Bridge 169:a7c7b631e539 836 \param [in] IRQn Interrupt number.
Anna Bridge 169:a7c7b631e539 837 \param [in] priority Priority to set.
Anna Bridge 169:a7c7b631e539 838 \note The priority cannot be set for every processor exception.
Anna Bridge 169:a7c7b631e539 839 */
Anna Bridge 169:a7c7b631e539 840 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Anna Bridge 169:a7c7b631e539 841 {
Anna Bridge 169:a7c7b631e539 842 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 843 {
Anna Bridge 169:a7c7b631e539 844 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Anna Bridge 169:a7c7b631e539 845 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Anna Bridge 169:a7c7b631e539 846 }
Anna Bridge 169:a7c7b631e539 847 else
Anna Bridge 169:a7c7b631e539 848 {
Anna Bridge 169:a7c7b631e539 849 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Anna Bridge 169:a7c7b631e539 850 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Anna Bridge 169:a7c7b631e539 851 }
Anna Bridge 169:a7c7b631e539 852 }
Anna Bridge 169:a7c7b631e539 853
Anna Bridge 169:a7c7b631e539 854
Anna Bridge 169:a7c7b631e539 855 /**
Anna Bridge 169:a7c7b631e539 856 \brief Get Interrupt Priority
Anna Bridge 169:a7c7b631e539 857 \details Reads the priority of a device specific interrupt or a processor exception.
Anna Bridge 169:a7c7b631e539 858 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 169:a7c7b631e539 859 or negative to specify a processor exception.
Anna Bridge 169:a7c7b631e539 860 \param [in] IRQn Interrupt number.
Anna Bridge 169:a7c7b631e539 861 \return Interrupt Priority.
Anna Bridge 169:a7c7b631e539 862 Value is aligned automatically to the implemented priority bits of the microcontroller.
Anna Bridge 169:a7c7b631e539 863 */
Anna Bridge 169:a7c7b631e539 864 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 865 {
Anna Bridge 169:a7c7b631e539 866
Anna Bridge 169:a7c7b631e539 867 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 868 {
Anna Bridge 169:a7c7b631e539 869 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 169:a7c7b631e539 870 }
Anna Bridge 169:a7c7b631e539 871 else
Anna Bridge 169:a7c7b631e539 872 {
Anna Bridge 169:a7c7b631e539 873 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 169:a7c7b631e539 874 }
Anna Bridge 169:a7c7b631e539 875 }
Anna Bridge 169:a7c7b631e539 876
Anna Bridge 169:a7c7b631e539 877
Anna Bridge 169:a7c7b631e539 878 /**
Anna Bridge 169:a7c7b631e539 879 \brief Set Interrupt Vector
Anna Bridge 169:a7c7b631e539 880 \details Sets an interrupt vector in SRAM based interrupt vector table.
Anna Bridge 169:a7c7b631e539 881 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 169:a7c7b631e539 882 or negative to specify a processor exception.
Anna Bridge 169:a7c7b631e539 883 VTOR must been relocated to SRAM before.
Anna Bridge 169:a7c7b631e539 884 If VTOR is not present address 0 must be mapped to SRAM.
Anna Bridge 169:a7c7b631e539 885 \param [in] IRQn Interrupt number
Anna Bridge 169:a7c7b631e539 886 \param [in] vector Address of interrupt handler function
Anna Bridge 169:a7c7b631e539 887 */
Anna Bridge 169:a7c7b631e539 888 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Anna Bridge 169:a7c7b631e539 889 {
Anna Bridge 169:a7c7b631e539 890 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 891 uint32_t *vectors = (uint32_t *)SCB->VTOR;
Anna Bridge 169:a7c7b631e539 892 #else
Anna Bridge 169:a7c7b631e539 893 uint32_t *vectors = (uint32_t *)0x0U;
Anna Bridge 169:a7c7b631e539 894 #endif
Anna Bridge 169:a7c7b631e539 895 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
Anna Bridge 169:a7c7b631e539 896 }
Anna Bridge 169:a7c7b631e539 897
Anna Bridge 169:a7c7b631e539 898
Anna Bridge 169:a7c7b631e539 899 /**
Anna Bridge 169:a7c7b631e539 900 \brief Get Interrupt Vector
Anna Bridge 169:a7c7b631e539 901 \details Reads an interrupt vector from interrupt vector table.
Anna Bridge 169:a7c7b631e539 902 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 169:a7c7b631e539 903 or negative to specify a processor exception.
Anna Bridge 169:a7c7b631e539 904 \param [in] IRQn Interrupt number.
Anna Bridge 169:a7c7b631e539 905 \return Address of interrupt handler function
Anna Bridge 169:a7c7b631e539 906 */
Anna Bridge 169:a7c7b631e539 907 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 908 {
Anna Bridge 169:a7c7b631e539 909 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 910 uint32_t *vectors = (uint32_t *)SCB->VTOR;
Anna Bridge 169:a7c7b631e539 911 #else
Anna Bridge 169:a7c7b631e539 912 uint32_t *vectors = (uint32_t *)0x0U;
Anna Bridge 169:a7c7b631e539 913 #endif
Anna Bridge 169:a7c7b631e539 914 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
Anna Bridge 169:a7c7b631e539 915
Anna Bridge 169:a7c7b631e539 916 }
Anna Bridge 169:a7c7b631e539 917
Anna Bridge 169:a7c7b631e539 918
Anna Bridge 169:a7c7b631e539 919 /**
Anna Bridge 169:a7c7b631e539 920 \brief System Reset
Anna Bridge 169:a7c7b631e539 921 \details Initiates a system reset request to reset the MCU.
Anna Bridge 169:a7c7b631e539 922 */
Anna Bridge 169:a7c7b631e539 923 __STATIC_INLINE void __NVIC_SystemReset(void)
Anna Bridge 169:a7c7b631e539 924 {
Anna Bridge 169:a7c7b631e539 925 __DSB(); /* Ensure all outstanding memory accesses included
Anna Bridge 169:a7c7b631e539 926 buffered write are completed before reset */
Anna Bridge 169:a7c7b631e539 927 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Anna Bridge 169:a7c7b631e539 928 SCB_AIRCR_SYSRESETREQ_Msk);
Anna Bridge 169:a7c7b631e539 929 __DSB(); /* Ensure completion of memory access */
Anna Bridge 169:a7c7b631e539 930
Anna Bridge 169:a7c7b631e539 931 for(;;) /* wait until reset */
Anna Bridge 169:a7c7b631e539 932 {
Anna Bridge 169:a7c7b631e539 933 __NOP();
Anna Bridge 169:a7c7b631e539 934 }
Anna Bridge 169:a7c7b631e539 935 }
Anna Bridge 169:a7c7b631e539 936
Anna Bridge 169:a7c7b631e539 937 /*@} end of CMSIS_Core_NVICFunctions */
Anna Bridge 169:a7c7b631e539 938
Anna Bridge 169:a7c7b631e539 939 /* ########################## MPU functions #################################### */
Anna Bridge 169:a7c7b631e539 940
Anna Bridge 169:a7c7b631e539 941 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 942
Anna Bridge 169:a7c7b631e539 943 #include "mpu_armv7.h"
Anna Bridge 169:a7c7b631e539 944
Anna Bridge 169:a7c7b631e539 945 #endif
Anna Bridge 169:a7c7b631e539 946
Anna Bridge 169:a7c7b631e539 947 /* ########################## FPU functions #################################### */
Anna Bridge 169:a7c7b631e539 948 /**
Anna Bridge 169:a7c7b631e539 949 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 169:a7c7b631e539 950 \defgroup CMSIS_Core_FpuFunctions FPU Functions
Anna Bridge 169:a7c7b631e539 951 \brief Function that provides FPU type.
Anna Bridge 169:a7c7b631e539 952 @{
Anna Bridge 169:a7c7b631e539 953 */
Anna Bridge 169:a7c7b631e539 954
Anna Bridge 169:a7c7b631e539 955 /**
Anna Bridge 169:a7c7b631e539 956 \brief get FPU type
Anna Bridge 169:a7c7b631e539 957 \details returns the FPU type
Anna Bridge 169:a7c7b631e539 958 \returns
Anna Bridge 169:a7c7b631e539 959 - \b 0: No FPU
Anna Bridge 169:a7c7b631e539 960 - \b 1: Single precision FPU
Anna Bridge 169:a7c7b631e539 961 - \b 2: Double + Single precision FPU
Anna Bridge 169:a7c7b631e539 962 */
Anna Bridge 169:a7c7b631e539 963 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
Anna Bridge 169:a7c7b631e539 964 {
Anna Bridge 169:a7c7b631e539 965 return 0U; /* No FPU */
Anna Bridge 169:a7c7b631e539 966 }
Anna Bridge 169:a7c7b631e539 967
Anna Bridge 169:a7c7b631e539 968
Anna Bridge 169:a7c7b631e539 969 /*@} end of CMSIS_Core_FpuFunctions */
Anna Bridge 169:a7c7b631e539 970
Anna Bridge 169:a7c7b631e539 971
Anna Bridge 169:a7c7b631e539 972
Anna Bridge 169:a7c7b631e539 973 /* ################################## SysTick function ############################################ */
Anna Bridge 169:a7c7b631e539 974 /**
Anna Bridge 169:a7c7b631e539 975 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 169:a7c7b631e539 976 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Anna Bridge 169:a7c7b631e539 977 \brief Functions that configure the System.
Anna Bridge 169:a7c7b631e539 978 @{
Anna Bridge 169:a7c7b631e539 979 */
Anna Bridge 169:a7c7b631e539 980
Anna Bridge 169:a7c7b631e539 981 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
Anna Bridge 169:a7c7b631e539 982
Anna Bridge 169:a7c7b631e539 983 /**
Anna Bridge 169:a7c7b631e539 984 \brief System Tick Configuration
Anna Bridge 169:a7c7b631e539 985 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Anna Bridge 169:a7c7b631e539 986 Counter is in free running mode to generate periodic interrupts.
Anna Bridge 169:a7c7b631e539 987 \param [in] ticks Number of ticks between two interrupts.
Anna Bridge 169:a7c7b631e539 988 \return 0 Function succeeded.
Anna Bridge 169:a7c7b631e539 989 \return 1 Function failed.
Anna Bridge 169:a7c7b631e539 990 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Anna Bridge 169:a7c7b631e539 991 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Anna Bridge 169:a7c7b631e539 992 must contain a vendor-specific implementation of this function.
Anna Bridge 169:a7c7b631e539 993 */
Anna Bridge 169:a7c7b631e539 994 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Anna Bridge 169:a7c7b631e539 995 {
Anna Bridge 169:a7c7b631e539 996 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Anna Bridge 169:a7c7b631e539 997 {
Anna Bridge 169:a7c7b631e539 998 return (1UL); /* Reload value impossible */
Anna Bridge 169:a7c7b631e539 999 }
Anna Bridge 169:a7c7b631e539 1000
Anna Bridge 169:a7c7b631e539 1001 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Anna Bridge 169:a7c7b631e539 1002 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Anna Bridge 169:a7c7b631e539 1003 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Anna Bridge 169:a7c7b631e539 1004 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Anna Bridge 169:a7c7b631e539 1005 SysTick_CTRL_TICKINT_Msk |
Anna Bridge 169:a7c7b631e539 1006 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Anna Bridge 169:a7c7b631e539 1007 return (0UL); /* Function successful */
Anna Bridge 169:a7c7b631e539 1008 }
Anna Bridge 169:a7c7b631e539 1009
Anna Bridge 169:a7c7b631e539 1010 #endif
Anna Bridge 169:a7c7b631e539 1011
Anna Bridge 169:a7c7b631e539 1012 /*@} end of CMSIS_Core_SysTickFunctions */
Anna Bridge 169:a7c7b631e539 1013
Anna Bridge 169:a7c7b631e539 1014
Anna Bridge 169:a7c7b631e539 1015
Anna Bridge 169:a7c7b631e539 1016
Anna Bridge 169:a7c7b631e539 1017 #ifdef __cplusplus
Anna Bridge 169:a7c7b631e539 1018 }
Anna Bridge 169:a7c7b631e539 1019 #endif
Anna Bridge 169:a7c7b631e539 1020
Anna Bridge 169:a7c7b631e539 1021 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Anna Bridge 169:a7c7b631e539 1022
Anna Bridge 169:a7c7b631e539 1023 #endif /* __CMSIS_GENERIC */