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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32625PICO_NO_BOOT/core_armv8mml.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 15:38:59 2018 +0100
Revision:
169:a7c7b631e539
mbed library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 169:a7c7b631e539 1 /**************************************************************************//**
Anna Bridge 169:a7c7b631e539 2 * @file core_armv8mml.h
Anna Bridge 169:a7c7b631e539 3 * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
Anna Bridge 169:a7c7b631e539 4 * @version V5.0.4
Anna Bridge 169:a7c7b631e539 5 * @date 10. January 2018
Anna Bridge 169:a7c7b631e539 6 ******************************************************************************/
Anna Bridge 169:a7c7b631e539 7 /*
Anna Bridge 169:a7c7b631e539 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
Anna Bridge 169:a7c7b631e539 9 *
Anna Bridge 169:a7c7b631e539 10 * SPDX-License-Identifier: Apache-2.0
Anna Bridge 169:a7c7b631e539 11 *
Anna Bridge 169:a7c7b631e539 12 * Licensed under the Apache License, Version 2.0 (the License); you may
Anna Bridge 169:a7c7b631e539 13 * not use this file except in compliance with the License.
Anna Bridge 169:a7c7b631e539 14 * You may obtain a copy of the License at
Anna Bridge 169:a7c7b631e539 15 *
Anna Bridge 169:a7c7b631e539 16 * www.apache.org/licenses/LICENSE-2.0
Anna Bridge 169:a7c7b631e539 17 *
Anna Bridge 169:a7c7b631e539 18 * Unless required by applicable law or agreed to in writing, software
Anna Bridge 169:a7c7b631e539 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Anna Bridge 169:a7c7b631e539 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Anna Bridge 169:a7c7b631e539 21 * See the License for the specific language governing permissions and
Anna Bridge 169:a7c7b631e539 22 * limitations under the License.
Anna Bridge 169:a7c7b631e539 23 */
Anna Bridge 169:a7c7b631e539 24
Anna Bridge 169:a7c7b631e539 25 #if defined ( __ICCARM__ )
Anna Bridge 169:a7c7b631e539 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 169:a7c7b631e539 27 #elif defined (__clang__)
Anna Bridge 169:a7c7b631e539 28 #pragma clang system_header /* treat file as system include file */
Anna Bridge 169:a7c7b631e539 29 #endif
Anna Bridge 169:a7c7b631e539 30
Anna Bridge 169:a7c7b631e539 31 #ifndef __CORE_ARMV8MML_H_GENERIC
Anna Bridge 169:a7c7b631e539 32 #define __CORE_ARMV8MML_H_GENERIC
Anna Bridge 169:a7c7b631e539 33
Anna Bridge 169:a7c7b631e539 34 #include <stdint.h>
Anna Bridge 169:a7c7b631e539 35
Anna Bridge 169:a7c7b631e539 36 #ifdef __cplusplus
Anna Bridge 169:a7c7b631e539 37 extern "C" {
Anna Bridge 169:a7c7b631e539 38 #endif
Anna Bridge 169:a7c7b631e539 39
Anna Bridge 169:a7c7b631e539 40 /**
Anna Bridge 169:a7c7b631e539 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Anna Bridge 169:a7c7b631e539 42 CMSIS violates the following MISRA-C:2004 rules:
Anna Bridge 169:a7c7b631e539 43
Anna Bridge 169:a7c7b631e539 44 \li Required Rule 8.5, object/function definition in header file.<br>
Anna Bridge 169:a7c7b631e539 45 Function definitions in header files are used to allow 'inlining'.
Anna Bridge 169:a7c7b631e539 46
Anna Bridge 169:a7c7b631e539 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Anna Bridge 169:a7c7b631e539 48 Unions are used for effective representation of core registers.
Anna Bridge 169:a7c7b631e539 49
Anna Bridge 169:a7c7b631e539 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
Anna Bridge 169:a7c7b631e539 51 Function-like macros are used to allow more efficient code.
Anna Bridge 169:a7c7b631e539 52 */
Anna Bridge 169:a7c7b631e539 53
Anna Bridge 169:a7c7b631e539 54
Anna Bridge 169:a7c7b631e539 55 /*******************************************************************************
Anna Bridge 169:a7c7b631e539 56 * CMSIS definitions
Anna Bridge 169:a7c7b631e539 57 ******************************************************************************/
Anna Bridge 169:a7c7b631e539 58 /**
Anna Bridge 169:a7c7b631e539 59 \ingroup Cortex_ARMv8MML
Anna Bridge 169:a7c7b631e539 60 @{
Anna Bridge 169:a7c7b631e539 61 */
Anna Bridge 169:a7c7b631e539 62
Anna Bridge 169:a7c7b631e539 63 #include "cmsis_version.h"
Anna Bridge 169:a7c7b631e539 64
Anna Bridge 169:a7c7b631e539 65 /* CMSIS Armv8MML definitions */
Anna Bridge 169:a7c7b631e539 66 #define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
Anna Bridge 169:a7c7b631e539 67 #define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
Anna Bridge 169:a7c7b631e539 68 #define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
Anna Bridge 169:a7c7b631e539 69 __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
Anna Bridge 169:a7c7b631e539 70
Anna Bridge 169:a7c7b631e539 71 #define __CORTEX_M (81U) /*!< Cortex-M Core */
Anna Bridge 169:a7c7b631e539 72
Anna Bridge 169:a7c7b631e539 73 /** __FPU_USED indicates whether an FPU is used or not.
Anna Bridge 169:a7c7b631e539 74 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
Anna Bridge 169:a7c7b631e539 75 */
Anna Bridge 169:a7c7b631e539 76 #if defined ( __CC_ARM )
Anna Bridge 169:a7c7b631e539 77 #if defined __TARGET_FPU_VFP
Anna Bridge 169:a7c7b631e539 78 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 79 #define __FPU_USED 1U
Anna Bridge 169:a7c7b631e539 80 #else
Anna Bridge 169:a7c7b631e539 81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 169:a7c7b631e539 82 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 83 #endif
Anna Bridge 169:a7c7b631e539 84 #else
Anna Bridge 169:a7c7b631e539 85 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 86 #endif
Anna Bridge 169:a7c7b631e539 87
Anna Bridge 169:a7c7b631e539 88 #if defined(__ARM_FEATURE_DSP)
Anna Bridge 169:a7c7b631e539 89 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 90 #define __DSP_USED 1U
Anna Bridge 169:a7c7b631e539 91 #else
Anna Bridge 169:a7c7b631e539 92 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
Anna Bridge 169:a7c7b631e539 93 #define __DSP_USED 0U
Anna Bridge 169:a7c7b631e539 94 #endif
Anna Bridge 169:a7c7b631e539 95 #else
Anna Bridge 169:a7c7b631e539 96 #define __DSP_USED 0U
Anna Bridge 169:a7c7b631e539 97 #endif
Anna Bridge 169:a7c7b631e539 98
Anna Bridge 169:a7c7b631e539 99 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
Anna Bridge 169:a7c7b631e539 100 #if defined __ARM_PCS_VFP
Anna Bridge 169:a7c7b631e539 101 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 102 #define __FPU_USED 1U
Anna Bridge 169:a7c7b631e539 103 #else
Anna Bridge 169:a7c7b631e539 104 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 169:a7c7b631e539 105 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 106 #endif
Anna Bridge 169:a7c7b631e539 107 #else
Anna Bridge 169:a7c7b631e539 108 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 109 #endif
Anna Bridge 169:a7c7b631e539 110
Anna Bridge 169:a7c7b631e539 111 #if defined(__ARM_FEATURE_DSP)
Anna Bridge 169:a7c7b631e539 112 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 113 #define __DSP_USED 1U
Anna Bridge 169:a7c7b631e539 114 #else
Anna Bridge 169:a7c7b631e539 115 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
Anna Bridge 169:a7c7b631e539 116 #define __DSP_USED 0U
Anna Bridge 169:a7c7b631e539 117 #endif
Anna Bridge 169:a7c7b631e539 118 #else
Anna Bridge 169:a7c7b631e539 119 #define __DSP_USED 0U
Anna Bridge 169:a7c7b631e539 120 #endif
Anna Bridge 169:a7c7b631e539 121
Anna Bridge 169:a7c7b631e539 122 #elif defined ( __GNUC__ )
Anna Bridge 169:a7c7b631e539 123 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Anna Bridge 169:a7c7b631e539 124 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 125 #define __FPU_USED 1U
Anna Bridge 169:a7c7b631e539 126 #else
Anna Bridge 169:a7c7b631e539 127 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 169:a7c7b631e539 128 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 129 #endif
Anna Bridge 169:a7c7b631e539 130 #else
Anna Bridge 169:a7c7b631e539 131 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 132 #endif
Anna Bridge 169:a7c7b631e539 133
Anna Bridge 169:a7c7b631e539 134 #if defined(__ARM_FEATURE_DSP)
Anna Bridge 169:a7c7b631e539 135 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 136 #define __DSP_USED 1U
Anna Bridge 169:a7c7b631e539 137 #else
Anna Bridge 169:a7c7b631e539 138 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
Anna Bridge 169:a7c7b631e539 139 #define __DSP_USED 0U
Anna Bridge 169:a7c7b631e539 140 #endif
Anna Bridge 169:a7c7b631e539 141 #else
Anna Bridge 169:a7c7b631e539 142 #define __DSP_USED 0U
Anna Bridge 169:a7c7b631e539 143 #endif
Anna Bridge 169:a7c7b631e539 144
Anna Bridge 169:a7c7b631e539 145 #elif defined ( __ICCARM__ )
Anna Bridge 169:a7c7b631e539 146 #if defined __ARMVFP__
Anna Bridge 169:a7c7b631e539 147 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 148 #define __FPU_USED 1U
Anna Bridge 169:a7c7b631e539 149 #else
Anna Bridge 169:a7c7b631e539 150 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 169:a7c7b631e539 151 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 152 #endif
Anna Bridge 169:a7c7b631e539 153 #else
Anna Bridge 169:a7c7b631e539 154 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 155 #endif
Anna Bridge 169:a7c7b631e539 156
Anna Bridge 169:a7c7b631e539 157 #if defined(__ARM_FEATURE_DSP)
Anna Bridge 169:a7c7b631e539 158 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 159 #define __DSP_USED 1U
Anna Bridge 169:a7c7b631e539 160 #else
Anna Bridge 169:a7c7b631e539 161 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
Anna Bridge 169:a7c7b631e539 162 #define __DSP_USED 0U
Anna Bridge 169:a7c7b631e539 163 #endif
Anna Bridge 169:a7c7b631e539 164 #else
Anna Bridge 169:a7c7b631e539 165 #define __DSP_USED 0U
Anna Bridge 169:a7c7b631e539 166 #endif
Anna Bridge 169:a7c7b631e539 167
Anna Bridge 169:a7c7b631e539 168 #elif defined ( __TI_ARM__ )
Anna Bridge 169:a7c7b631e539 169 #if defined __TI_VFP_SUPPORT__
Anna Bridge 169:a7c7b631e539 170 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 171 #define __FPU_USED 1U
Anna Bridge 169:a7c7b631e539 172 #else
Anna Bridge 169:a7c7b631e539 173 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 169:a7c7b631e539 174 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 175 #endif
Anna Bridge 169:a7c7b631e539 176 #else
Anna Bridge 169:a7c7b631e539 177 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 178 #endif
Anna Bridge 169:a7c7b631e539 179
Anna Bridge 169:a7c7b631e539 180 #elif defined ( __TASKING__ )
Anna Bridge 169:a7c7b631e539 181 #if defined __FPU_VFP__
Anna Bridge 169:a7c7b631e539 182 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 183 #define __FPU_USED 1U
Anna Bridge 169:a7c7b631e539 184 #else
Anna Bridge 169:a7c7b631e539 185 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 169:a7c7b631e539 186 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 187 #endif
Anna Bridge 169:a7c7b631e539 188 #else
Anna Bridge 169:a7c7b631e539 189 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 190 #endif
Anna Bridge 169:a7c7b631e539 191
Anna Bridge 169:a7c7b631e539 192 #elif defined ( __CSMC__ )
Anna Bridge 169:a7c7b631e539 193 #if ( __CSMC__ & 0x400U)
Anna Bridge 169:a7c7b631e539 194 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 195 #define __FPU_USED 1U
Anna Bridge 169:a7c7b631e539 196 #else
Anna Bridge 169:a7c7b631e539 197 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 169:a7c7b631e539 198 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 199 #endif
Anna Bridge 169:a7c7b631e539 200 #else
Anna Bridge 169:a7c7b631e539 201 #define __FPU_USED 0U
Anna Bridge 169:a7c7b631e539 202 #endif
Anna Bridge 169:a7c7b631e539 203
Anna Bridge 169:a7c7b631e539 204 #endif
Anna Bridge 169:a7c7b631e539 205
Anna Bridge 169:a7c7b631e539 206 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
Anna Bridge 169:a7c7b631e539 207
Anna Bridge 169:a7c7b631e539 208
Anna Bridge 169:a7c7b631e539 209 #ifdef __cplusplus
Anna Bridge 169:a7c7b631e539 210 }
Anna Bridge 169:a7c7b631e539 211 #endif
Anna Bridge 169:a7c7b631e539 212
Anna Bridge 169:a7c7b631e539 213 #endif /* __CORE_ARMV8MML_H_GENERIC */
Anna Bridge 169:a7c7b631e539 214
Anna Bridge 169:a7c7b631e539 215 #ifndef __CMSIS_GENERIC
Anna Bridge 169:a7c7b631e539 216
Anna Bridge 169:a7c7b631e539 217 #ifndef __CORE_ARMV8MML_H_DEPENDANT
Anna Bridge 169:a7c7b631e539 218 #define __CORE_ARMV8MML_H_DEPENDANT
Anna Bridge 169:a7c7b631e539 219
Anna Bridge 169:a7c7b631e539 220 #ifdef __cplusplus
Anna Bridge 169:a7c7b631e539 221 extern "C" {
Anna Bridge 169:a7c7b631e539 222 #endif
Anna Bridge 169:a7c7b631e539 223
Anna Bridge 169:a7c7b631e539 224 /* check device defines and use defaults */
Anna Bridge 169:a7c7b631e539 225 #if defined __CHECK_DEVICE_DEFINES
Anna Bridge 169:a7c7b631e539 226 #ifndef __ARMv8MML_REV
Anna Bridge 169:a7c7b631e539 227 #define __ARMv8MML_REV 0x0000U
Anna Bridge 169:a7c7b631e539 228 #warning "__ARMv8MML_REV not defined in device header file; using default!"
Anna Bridge 169:a7c7b631e539 229 #endif
Anna Bridge 169:a7c7b631e539 230
Anna Bridge 169:a7c7b631e539 231 #ifndef __FPU_PRESENT
Anna Bridge 169:a7c7b631e539 232 #define __FPU_PRESENT 0U
Anna Bridge 169:a7c7b631e539 233 #warning "__FPU_PRESENT not defined in device header file; using default!"
Anna Bridge 169:a7c7b631e539 234 #endif
Anna Bridge 169:a7c7b631e539 235
Anna Bridge 169:a7c7b631e539 236 #ifndef __MPU_PRESENT
Anna Bridge 169:a7c7b631e539 237 #define __MPU_PRESENT 0U
Anna Bridge 169:a7c7b631e539 238 #warning "__MPU_PRESENT not defined in device header file; using default!"
Anna Bridge 169:a7c7b631e539 239 #endif
Anna Bridge 169:a7c7b631e539 240
Anna Bridge 169:a7c7b631e539 241 #ifndef __SAUREGION_PRESENT
Anna Bridge 169:a7c7b631e539 242 #define __SAUREGION_PRESENT 0U
Anna Bridge 169:a7c7b631e539 243 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
Anna Bridge 169:a7c7b631e539 244 #endif
Anna Bridge 169:a7c7b631e539 245
Anna Bridge 169:a7c7b631e539 246 #ifndef __DSP_PRESENT
Anna Bridge 169:a7c7b631e539 247 #define __DSP_PRESENT 0U
Anna Bridge 169:a7c7b631e539 248 #warning "__DSP_PRESENT not defined in device header file; using default!"
Anna Bridge 169:a7c7b631e539 249 #endif
Anna Bridge 169:a7c7b631e539 250
Anna Bridge 169:a7c7b631e539 251 #ifndef __NVIC_PRIO_BITS
Anna Bridge 169:a7c7b631e539 252 #define __NVIC_PRIO_BITS 3U
Anna Bridge 169:a7c7b631e539 253 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Anna Bridge 169:a7c7b631e539 254 #endif
Anna Bridge 169:a7c7b631e539 255
Anna Bridge 169:a7c7b631e539 256 #ifndef __Vendor_SysTickConfig
Anna Bridge 169:a7c7b631e539 257 #define __Vendor_SysTickConfig 0U
Anna Bridge 169:a7c7b631e539 258 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Anna Bridge 169:a7c7b631e539 259 #endif
Anna Bridge 169:a7c7b631e539 260 #endif
Anna Bridge 169:a7c7b631e539 261
Anna Bridge 169:a7c7b631e539 262 /* IO definitions (access restrictions to peripheral registers) */
Anna Bridge 169:a7c7b631e539 263 /**
Anna Bridge 169:a7c7b631e539 264 \defgroup CMSIS_glob_defs CMSIS Global Defines
Anna Bridge 169:a7c7b631e539 265
Anna Bridge 169:a7c7b631e539 266 <strong>IO Type Qualifiers</strong> are used
Anna Bridge 169:a7c7b631e539 267 \li to specify the access to peripheral variables.
Anna Bridge 169:a7c7b631e539 268 \li for automatic generation of peripheral register debug information.
Anna Bridge 169:a7c7b631e539 269 */
Anna Bridge 169:a7c7b631e539 270 #ifdef __cplusplus
Anna Bridge 169:a7c7b631e539 271 #define __I volatile /*!< Defines 'read only' permissions */
Anna Bridge 169:a7c7b631e539 272 #else
Anna Bridge 169:a7c7b631e539 273 #define __I volatile const /*!< Defines 'read only' permissions */
Anna Bridge 169:a7c7b631e539 274 #endif
Anna Bridge 169:a7c7b631e539 275 #define __O volatile /*!< Defines 'write only' permissions */
Anna Bridge 169:a7c7b631e539 276 #define __IO volatile /*!< Defines 'read / write' permissions */
Anna Bridge 169:a7c7b631e539 277
Anna Bridge 169:a7c7b631e539 278 /* following defines should be used for structure members */
Anna Bridge 169:a7c7b631e539 279 #define __IM volatile const /*! Defines 'read only' structure member permissions */
Anna Bridge 169:a7c7b631e539 280 #define __OM volatile /*! Defines 'write only' structure member permissions */
Anna Bridge 169:a7c7b631e539 281 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
Anna Bridge 169:a7c7b631e539 282
Anna Bridge 169:a7c7b631e539 283 /*@} end of group ARMv8MML */
Anna Bridge 169:a7c7b631e539 284
Anna Bridge 169:a7c7b631e539 285
Anna Bridge 169:a7c7b631e539 286
Anna Bridge 169:a7c7b631e539 287 /*******************************************************************************
Anna Bridge 169:a7c7b631e539 288 * Register Abstraction
Anna Bridge 169:a7c7b631e539 289 Core Register contain:
Anna Bridge 169:a7c7b631e539 290 - Core Register
Anna Bridge 169:a7c7b631e539 291 - Core NVIC Register
Anna Bridge 169:a7c7b631e539 292 - Core SCB Register
Anna Bridge 169:a7c7b631e539 293 - Core SysTick Register
Anna Bridge 169:a7c7b631e539 294 - Core Debug Register
Anna Bridge 169:a7c7b631e539 295 - Core MPU Register
Anna Bridge 169:a7c7b631e539 296 - Core SAU Register
Anna Bridge 169:a7c7b631e539 297 - Core FPU Register
Anna Bridge 169:a7c7b631e539 298 ******************************************************************************/
Anna Bridge 169:a7c7b631e539 299 /**
Anna Bridge 169:a7c7b631e539 300 \defgroup CMSIS_core_register Defines and Type Definitions
Anna Bridge 169:a7c7b631e539 301 \brief Type definitions and defines for Cortex-M processor based devices.
Anna Bridge 169:a7c7b631e539 302 */
Anna Bridge 169:a7c7b631e539 303
Anna Bridge 169:a7c7b631e539 304 /**
Anna Bridge 169:a7c7b631e539 305 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 306 \defgroup CMSIS_CORE Status and Control Registers
Anna Bridge 169:a7c7b631e539 307 \brief Core Register type definitions.
Anna Bridge 169:a7c7b631e539 308 @{
Anna Bridge 169:a7c7b631e539 309 */
Anna Bridge 169:a7c7b631e539 310
Anna Bridge 169:a7c7b631e539 311 /**
Anna Bridge 169:a7c7b631e539 312 \brief Union type to access the Application Program Status Register (APSR).
Anna Bridge 169:a7c7b631e539 313 */
Anna Bridge 169:a7c7b631e539 314 typedef union
Anna Bridge 169:a7c7b631e539 315 {
Anna Bridge 169:a7c7b631e539 316 struct
Anna Bridge 169:a7c7b631e539 317 {
Anna Bridge 169:a7c7b631e539 318 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
Anna Bridge 169:a7c7b631e539 319 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Anna Bridge 169:a7c7b631e539 320 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
Anna Bridge 169:a7c7b631e539 321 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Anna Bridge 169:a7c7b631e539 322 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Anna Bridge 169:a7c7b631e539 323 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Anna Bridge 169:a7c7b631e539 324 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Anna Bridge 169:a7c7b631e539 325 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Anna Bridge 169:a7c7b631e539 326 } b; /*!< Structure used for bit access */
Anna Bridge 169:a7c7b631e539 327 uint32_t w; /*!< Type used for word access */
Anna Bridge 169:a7c7b631e539 328 } APSR_Type;
Anna Bridge 169:a7c7b631e539 329
Anna Bridge 169:a7c7b631e539 330 /* APSR Register Definitions */
Anna Bridge 169:a7c7b631e539 331 #define APSR_N_Pos 31U /*!< APSR: N Position */
Anna Bridge 169:a7c7b631e539 332 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Anna Bridge 169:a7c7b631e539 333
Anna Bridge 169:a7c7b631e539 334 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
Anna Bridge 169:a7c7b631e539 335 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Anna Bridge 169:a7c7b631e539 336
Anna Bridge 169:a7c7b631e539 337 #define APSR_C_Pos 29U /*!< APSR: C Position */
Anna Bridge 169:a7c7b631e539 338 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Anna Bridge 169:a7c7b631e539 339
Anna Bridge 169:a7c7b631e539 340 #define APSR_V_Pos 28U /*!< APSR: V Position */
Anna Bridge 169:a7c7b631e539 341 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Anna Bridge 169:a7c7b631e539 342
Anna Bridge 169:a7c7b631e539 343 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
Anna Bridge 169:a7c7b631e539 344 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
Anna Bridge 169:a7c7b631e539 345
Anna Bridge 169:a7c7b631e539 346 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
Anna Bridge 169:a7c7b631e539 347 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
Anna Bridge 169:a7c7b631e539 348
Anna Bridge 169:a7c7b631e539 349
Anna Bridge 169:a7c7b631e539 350 /**
Anna Bridge 169:a7c7b631e539 351 \brief Union type to access the Interrupt Program Status Register (IPSR).
Anna Bridge 169:a7c7b631e539 352 */
Anna Bridge 169:a7c7b631e539 353 typedef union
Anna Bridge 169:a7c7b631e539 354 {
Anna Bridge 169:a7c7b631e539 355 struct
Anna Bridge 169:a7c7b631e539 356 {
Anna Bridge 169:a7c7b631e539 357 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Anna Bridge 169:a7c7b631e539 358 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Anna Bridge 169:a7c7b631e539 359 } b; /*!< Structure used for bit access */
Anna Bridge 169:a7c7b631e539 360 uint32_t w; /*!< Type used for word access */
Anna Bridge 169:a7c7b631e539 361 } IPSR_Type;
Anna Bridge 169:a7c7b631e539 362
Anna Bridge 169:a7c7b631e539 363 /* IPSR Register Definitions */
Anna Bridge 169:a7c7b631e539 364 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
Anna Bridge 169:a7c7b631e539 365 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Anna Bridge 169:a7c7b631e539 366
Anna Bridge 169:a7c7b631e539 367
Anna Bridge 169:a7c7b631e539 368 /**
Anna Bridge 169:a7c7b631e539 369 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Anna Bridge 169:a7c7b631e539 370 */
Anna Bridge 169:a7c7b631e539 371 typedef union
Anna Bridge 169:a7c7b631e539 372 {
Anna Bridge 169:a7c7b631e539 373 struct
Anna Bridge 169:a7c7b631e539 374 {
Anna Bridge 169:a7c7b631e539 375 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Anna Bridge 169:a7c7b631e539 376 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
Anna Bridge 169:a7c7b631e539 377 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Anna Bridge 169:a7c7b631e539 378 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
Anna Bridge 169:a7c7b631e539 379 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Anna Bridge 169:a7c7b631e539 380 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Anna Bridge 169:a7c7b631e539 381 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Anna Bridge 169:a7c7b631e539 382 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Anna Bridge 169:a7c7b631e539 383 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Anna Bridge 169:a7c7b631e539 384 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Anna Bridge 169:a7c7b631e539 385 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Anna Bridge 169:a7c7b631e539 386 } b; /*!< Structure used for bit access */
Anna Bridge 169:a7c7b631e539 387 uint32_t w; /*!< Type used for word access */
Anna Bridge 169:a7c7b631e539 388 } xPSR_Type;
Anna Bridge 169:a7c7b631e539 389
Anna Bridge 169:a7c7b631e539 390 /* xPSR Register Definitions */
Anna Bridge 169:a7c7b631e539 391 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
Anna Bridge 169:a7c7b631e539 392 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Anna Bridge 169:a7c7b631e539 393
Anna Bridge 169:a7c7b631e539 394 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
Anna Bridge 169:a7c7b631e539 395 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Anna Bridge 169:a7c7b631e539 396
Anna Bridge 169:a7c7b631e539 397 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
Anna Bridge 169:a7c7b631e539 398 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Anna Bridge 169:a7c7b631e539 399
Anna Bridge 169:a7c7b631e539 400 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
Anna Bridge 169:a7c7b631e539 401 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Anna Bridge 169:a7c7b631e539 402
Anna Bridge 169:a7c7b631e539 403 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
Anna Bridge 169:a7c7b631e539 404 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
Anna Bridge 169:a7c7b631e539 405
Anna Bridge 169:a7c7b631e539 406 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
Anna Bridge 169:a7c7b631e539 407 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
Anna Bridge 169:a7c7b631e539 408
Anna Bridge 169:a7c7b631e539 409 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
Anna Bridge 169:a7c7b631e539 410 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Anna Bridge 169:a7c7b631e539 411
Anna Bridge 169:a7c7b631e539 412 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
Anna Bridge 169:a7c7b631e539 413 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
Anna Bridge 169:a7c7b631e539 414
Anna Bridge 169:a7c7b631e539 415 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
Anna Bridge 169:a7c7b631e539 416 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Anna Bridge 169:a7c7b631e539 417
Anna Bridge 169:a7c7b631e539 418
Anna Bridge 169:a7c7b631e539 419 /**
Anna Bridge 169:a7c7b631e539 420 \brief Union type to access the Control Registers (CONTROL).
Anna Bridge 169:a7c7b631e539 421 */
Anna Bridge 169:a7c7b631e539 422 typedef union
Anna Bridge 169:a7c7b631e539 423 {
Anna Bridge 169:a7c7b631e539 424 struct
Anna Bridge 169:a7c7b631e539 425 {
Anna Bridge 169:a7c7b631e539 426 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Anna Bridge 169:a7c7b631e539 427 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
Anna Bridge 169:a7c7b631e539 428 uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
Anna Bridge 169:a7c7b631e539 429 uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
Anna Bridge 169:a7c7b631e539 430 uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
Anna Bridge 169:a7c7b631e539 431 } b; /*!< Structure used for bit access */
Anna Bridge 169:a7c7b631e539 432 uint32_t w; /*!< Type used for word access */
Anna Bridge 169:a7c7b631e539 433 } CONTROL_Type;
Anna Bridge 169:a7c7b631e539 434
Anna Bridge 169:a7c7b631e539 435 /* CONTROL Register Definitions */
Anna Bridge 169:a7c7b631e539 436 #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
Anna Bridge 169:a7c7b631e539 437 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
Anna Bridge 169:a7c7b631e539 438
Anna Bridge 169:a7c7b631e539 439 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
Anna Bridge 169:a7c7b631e539 440 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
Anna Bridge 169:a7c7b631e539 441
Anna Bridge 169:a7c7b631e539 442 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
Anna Bridge 169:a7c7b631e539 443 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Anna Bridge 169:a7c7b631e539 444
Anna Bridge 169:a7c7b631e539 445 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
Anna Bridge 169:a7c7b631e539 446 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Anna Bridge 169:a7c7b631e539 447
Anna Bridge 169:a7c7b631e539 448 /*@} end of group CMSIS_CORE */
Anna Bridge 169:a7c7b631e539 449
Anna Bridge 169:a7c7b631e539 450
Anna Bridge 169:a7c7b631e539 451 /**
Anna Bridge 169:a7c7b631e539 452 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 453 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Anna Bridge 169:a7c7b631e539 454 \brief Type definitions for the NVIC Registers
Anna Bridge 169:a7c7b631e539 455 @{
Anna Bridge 169:a7c7b631e539 456 */
Anna Bridge 169:a7c7b631e539 457
Anna Bridge 169:a7c7b631e539 458 /**
Anna Bridge 169:a7c7b631e539 459 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Anna Bridge 169:a7c7b631e539 460 */
Anna Bridge 169:a7c7b631e539 461 typedef struct
Anna Bridge 169:a7c7b631e539 462 {
Anna Bridge 169:a7c7b631e539 463 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Anna Bridge 169:a7c7b631e539 464 uint32_t RESERVED0[16U];
Anna Bridge 169:a7c7b631e539 465 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Anna Bridge 169:a7c7b631e539 466 uint32_t RSERVED1[16U];
Anna Bridge 169:a7c7b631e539 467 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Anna Bridge 169:a7c7b631e539 468 uint32_t RESERVED2[16U];
Anna Bridge 169:a7c7b631e539 469 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Anna Bridge 169:a7c7b631e539 470 uint32_t RESERVED3[16U];
Anna Bridge 169:a7c7b631e539 471 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
Anna Bridge 169:a7c7b631e539 472 uint32_t RESERVED4[16U];
Anna Bridge 169:a7c7b631e539 473 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
Anna Bridge 169:a7c7b631e539 474 uint32_t RESERVED5[16U];
Anna Bridge 169:a7c7b631e539 475 __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
Anna Bridge 169:a7c7b631e539 476 uint32_t RESERVED6[580U];
Anna Bridge 169:a7c7b631e539 477 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
Anna Bridge 169:a7c7b631e539 478 } NVIC_Type;
Anna Bridge 169:a7c7b631e539 479
Anna Bridge 169:a7c7b631e539 480 /* Software Triggered Interrupt Register Definitions */
Anna Bridge 169:a7c7b631e539 481 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
Anna Bridge 169:a7c7b631e539 482 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
Anna Bridge 169:a7c7b631e539 483
Anna Bridge 169:a7c7b631e539 484 /*@} end of group CMSIS_NVIC */
Anna Bridge 169:a7c7b631e539 485
Anna Bridge 169:a7c7b631e539 486
Anna Bridge 169:a7c7b631e539 487 /**
Anna Bridge 169:a7c7b631e539 488 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 489 \defgroup CMSIS_SCB System Control Block (SCB)
Anna Bridge 169:a7c7b631e539 490 \brief Type definitions for the System Control Block Registers
Anna Bridge 169:a7c7b631e539 491 @{
Anna Bridge 169:a7c7b631e539 492 */
Anna Bridge 169:a7c7b631e539 493
Anna Bridge 169:a7c7b631e539 494 /**
Anna Bridge 169:a7c7b631e539 495 \brief Structure type to access the System Control Block (SCB).
Anna Bridge 169:a7c7b631e539 496 */
Anna Bridge 169:a7c7b631e539 497 typedef struct
Anna Bridge 169:a7c7b631e539 498 {
Anna Bridge 169:a7c7b631e539 499 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Anna Bridge 169:a7c7b631e539 500 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Anna Bridge 169:a7c7b631e539 501 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Anna Bridge 169:a7c7b631e539 502 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Anna Bridge 169:a7c7b631e539 503 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Anna Bridge 169:a7c7b631e539 504 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Anna Bridge 169:a7c7b631e539 505 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
Anna Bridge 169:a7c7b631e539 506 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Anna Bridge 169:a7c7b631e539 507 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
Anna Bridge 169:a7c7b631e539 508 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
Anna Bridge 169:a7c7b631e539 509 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
Anna Bridge 169:a7c7b631e539 510 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
Anna Bridge 169:a7c7b631e539 511 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
Anna Bridge 169:a7c7b631e539 512 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
Anna Bridge 169:a7c7b631e539 513 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
Anna Bridge 169:a7c7b631e539 514 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
Anna Bridge 169:a7c7b631e539 515 __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
Anna Bridge 169:a7c7b631e539 516 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
Anna Bridge 169:a7c7b631e539 517 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
Anna Bridge 169:a7c7b631e539 518 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
Anna Bridge 169:a7c7b631e539 519 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
Anna Bridge 169:a7c7b631e539 520 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
Anna Bridge 169:a7c7b631e539 521 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
Anna Bridge 169:a7c7b631e539 522 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
Anna Bridge 169:a7c7b631e539 523 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
Anna Bridge 169:a7c7b631e539 524 uint32_t RESERVED3[92U];
Anna Bridge 169:a7c7b631e539 525 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
Anna Bridge 169:a7c7b631e539 526 uint32_t RESERVED4[15U];
Anna Bridge 169:a7c7b631e539 527 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
Anna Bridge 169:a7c7b631e539 528 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
Anna Bridge 169:a7c7b631e539 529 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
Anna Bridge 169:a7c7b631e539 530 uint32_t RESERVED5[1U];
Anna Bridge 169:a7c7b631e539 531 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
Anna Bridge 169:a7c7b631e539 532 uint32_t RESERVED6[1U];
Anna Bridge 169:a7c7b631e539 533 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
Anna Bridge 169:a7c7b631e539 534 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
Anna Bridge 169:a7c7b631e539 535 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
Anna Bridge 169:a7c7b631e539 536 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
Anna Bridge 169:a7c7b631e539 537 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
Anna Bridge 169:a7c7b631e539 538 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
Anna Bridge 169:a7c7b631e539 539 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
Anna Bridge 169:a7c7b631e539 540 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
Anna Bridge 169:a7c7b631e539 541 uint32_t RESERVED7[6U];
Anna Bridge 169:a7c7b631e539 542 __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
Anna Bridge 169:a7c7b631e539 543 __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
Anna Bridge 169:a7c7b631e539 544 __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
Anna Bridge 169:a7c7b631e539 545 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
Anna Bridge 169:a7c7b631e539 546 __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
Anna Bridge 169:a7c7b631e539 547 uint32_t RESERVED8[1U];
Anna Bridge 169:a7c7b631e539 548 __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
Anna Bridge 169:a7c7b631e539 549 } SCB_Type;
Anna Bridge 169:a7c7b631e539 550
Anna Bridge 169:a7c7b631e539 551 /* SCB CPUID Register Definitions */
Anna Bridge 169:a7c7b631e539 552 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
Anna Bridge 169:a7c7b631e539 553 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Anna Bridge 169:a7c7b631e539 554
Anna Bridge 169:a7c7b631e539 555 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
Anna Bridge 169:a7c7b631e539 556 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Anna Bridge 169:a7c7b631e539 557
Anna Bridge 169:a7c7b631e539 558 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
Anna Bridge 169:a7c7b631e539 559 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Anna Bridge 169:a7c7b631e539 560
Anna Bridge 169:a7c7b631e539 561 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
Anna Bridge 169:a7c7b631e539 562 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Anna Bridge 169:a7c7b631e539 563
Anna Bridge 169:a7c7b631e539 564 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
Anna Bridge 169:a7c7b631e539 565 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Anna Bridge 169:a7c7b631e539 566
Anna Bridge 169:a7c7b631e539 567 /* SCB Interrupt Control State Register Definitions */
Anna Bridge 169:a7c7b631e539 568 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
Anna Bridge 169:a7c7b631e539 569 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
Anna Bridge 169:a7c7b631e539 570
Anna Bridge 169:a7c7b631e539 571 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
Anna Bridge 169:a7c7b631e539 572 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
Anna Bridge 169:a7c7b631e539 573
Anna Bridge 169:a7c7b631e539 574 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
Anna Bridge 169:a7c7b631e539 575 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Anna Bridge 169:a7c7b631e539 576
Anna Bridge 169:a7c7b631e539 577 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
Anna Bridge 169:a7c7b631e539 578 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Anna Bridge 169:a7c7b631e539 579
Anna Bridge 169:a7c7b631e539 580 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
Anna Bridge 169:a7c7b631e539 581 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Anna Bridge 169:a7c7b631e539 582
Anna Bridge 169:a7c7b631e539 583 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
Anna Bridge 169:a7c7b631e539 584 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Anna Bridge 169:a7c7b631e539 585
Anna Bridge 169:a7c7b631e539 586 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
Anna Bridge 169:a7c7b631e539 587 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
Anna Bridge 169:a7c7b631e539 588
Anna Bridge 169:a7c7b631e539 589 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
Anna Bridge 169:a7c7b631e539 590 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Anna Bridge 169:a7c7b631e539 591
Anna Bridge 169:a7c7b631e539 592 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
Anna Bridge 169:a7c7b631e539 593 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Anna Bridge 169:a7c7b631e539 594
Anna Bridge 169:a7c7b631e539 595 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
Anna Bridge 169:a7c7b631e539 596 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Anna Bridge 169:a7c7b631e539 597
Anna Bridge 169:a7c7b631e539 598 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
Anna Bridge 169:a7c7b631e539 599 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
Anna Bridge 169:a7c7b631e539 600
Anna Bridge 169:a7c7b631e539 601 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
Anna Bridge 169:a7c7b631e539 602 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Anna Bridge 169:a7c7b631e539 603
Anna Bridge 169:a7c7b631e539 604 /* SCB Vector Table Offset Register Definitions */
Anna Bridge 169:a7c7b631e539 605 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
Anna Bridge 169:a7c7b631e539 606 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Anna Bridge 169:a7c7b631e539 607
Anna Bridge 169:a7c7b631e539 608 /* SCB Application Interrupt and Reset Control Register Definitions */
Anna Bridge 169:a7c7b631e539 609 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
Anna Bridge 169:a7c7b631e539 610 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Anna Bridge 169:a7c7b631e539 611
Anna Bridge 169:a7c7b631e539 612 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
Anna Bridge 169:a7c7b631e539 613 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Anna Bridge 169:a7c7b631e539 614
Anna Bridge 169:a7c7b631e539 615 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
Anna Bridge 169:a7c7b631e539 616 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Anna Bridge 169:a7c7b631e539 617
Anna Bridge 169:a7c7b631e539 618 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
Anna Bridge 169:a7c7b631e539 619 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
Anna Bridge 169:a7c7b631e539 620
Anna Bridge 169:a7c7b631e539 621 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
Anna Bridge 169:a7c7b631e539 622 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
Anna Bridge 169:a7c7b631e539 623
Anna Bridge 169:a7c7b631e539 624 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
Anna Bridge 169:a7c7b631e539 625 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
Anna Bridge 169:a7c7b631e539 626
Anna Bridge 169:a7c7b631e539 627 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
Anna Bridge 169:a7c7b631e539 628 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
Anna Bridge 169:a7c7b631e539 629
Anna Bridge 169:a7c7b631e539 630 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
Anna Bridge 169:a7c7b631e539 631 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Anna Bridge 169:a7c7b631e539 632
Anna Bridge 169:a7c7b631e539 633 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
Anna Bridge 169:a7c7b631e539 634 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Anna Bridge 169:a7c7b631e539 635
Anna Bridge 169:a7c7b631e539 636 /* SCB System Control Register Definitions */
Anna Bridge 169:a7c7b631e539 637 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
Anna Bridge 169:a7c7b631e539 638 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Anna Bridge 169:a7c7b631e539 639
Anna Bridge 169:a7c7b631e539 640 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
Anna Bridge 169:a7c7b631e539 641 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
Anna Bridge 169:a7c7b631e539 642
Anna Bridge 169:a7c7b631e539 643 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
Anna Bridge 169:a7c7b631e539 644 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Anna Bridge 169:a7c7b631e539 645
Anna Bridge 169:a7c7b631e539 646 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
Anna Bridge 169:a7c7b631e539 647 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Anna Bridge 169:a7c7b631e539 648
Anna Bridge 169:a7c7b631e539 649 /* SCB Configuration Control Register Definitions */
Anna Bridge 169:a7c7b631e539 650 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
Anna Bridge 169:a7c7b631e539 651 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
Anna Bridge 169:a7c7b631e539 652
Anna Bridge 169:a7c7b631e539 653 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
Anna Bridge 169:a7c7b631e539 654 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
Anna Bridge 169:a7c7b631e539 655
Anna Bridge 169:a7c7b631e539 656 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
Anna Bridge 169:a7c7b631e539 657 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
Anna Bridge 169:a7c7b631e539 658
Anna Bridge 169:a7c7b631e539 659 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
Anna Bridge 169:a7c7b631e539 660 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
Anna Bridge 169:a7c7b631e539 661
Anna Bridge 169:a7c7b631e539 662 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
Anna Bridge 169:a7c7b631e539 663 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
Anna Bridge 169:a7c7b631e539 664
Anna Bridge 169:a7c7b631e539 665 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
Anna Bridge 169:a7c7b631e539 666 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
Anna Bridge 169:a7c7b631e539 667
Anna Bridge 169:a7c7b631e539 668 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
Anna Bridge 169:a7c7b631e539 669 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Anna Bridge 169:a7c7b631e539 670
Anna Bridge 169:a7c7b631e539 671 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
Anna Bridge 169:a7c7b631e539 672 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
Anna Bridge 169:a7c7b631e539 673
Anna Bridge 169:a7c7b631e539 674 /* SCB System Handler Control and State Register Definitions */
Anna Bridge 169:a7c7b631e539 675 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
Anna Bridge 169:a7c7b631e539 676 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
Anna Bridge 169:a7c7b631e539 677
Anna Bridge 169:a7c7b631e539 678 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
Anna Bridge 169:a7c7b631e539 679 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
Anna Bridge 169:a7c7b631e539 680
Anna Bridge 169:a7c7b631e539 681 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
Anna Bridge 169:a7c7b631e539 682 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
Anna Bridge 169:a7c7b631e539 683
Anna Bridge 169:a7c7b631e539 684 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
Anna Bridge 169:a7c7b631e539 685 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
Anna Bridge 169:a7c7b631e539 686
Anna Bridge 169:a7c7b631e539 687 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
Anna Bridge 169:a7c7b631e539 688 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
Anna Bridge 169:a7c7b631e539 689
Anna Bridge 169:a7c7b631e539 690 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
Anna Bridge 169:a7c7b631e539 691 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
Anna Bridge 169:a7c7b631e539 692
Anna Bridge 169:a7c7b631e539 693 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
Anna Bridge 169:a7c7b631e539 694 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Anna Bridge 169:a7c7b631e539 695
Anna Bridge 169:a7c7b631e539 696 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
Anna Bridge 169:a7c7b631e539 697 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
Anna Bridge 169:a7c7b631e539 698
Anna Bridge 169:a7c7b631e539 699 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
Anna Bridge 169:a7c7b631e539 700 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
Anna Bridge 169:a7c7b631e539 701
Anna Bridge 169:a7c7b631e539 702 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
Anna Bridge 169:a7c7b631e539 703 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
Anna Bridge 169:a7c7b631e539 704
Anna Bridge 169:a7c7b631e539 705 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
Anna Bridge 169:a7c7b631e539 706 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
Anna Bridge 169:a7c7b631e539 707
Anna Bridge 169:a7c7b631e539 708 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
Anna Bridge 169:a7c7b631e539 709 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
Anna Bridge 169:a7c7b631e539 710
Anna Bridge 169:a7c7b631e539 711 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
Anna Bridge 169:a7c7b631e539 712 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
Anna Bridge 169:a7c7b631e539 713
Anna Bridge 169:a7c7b631e539 714 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
Anna Bridge 169:a7c7b631e539 715 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
Anna Bridge 169:a7c7b631e539 716
Anna Bridge 169:a7c7b631e539 717 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
Anna Bridge 169:a7c7b631e539 718 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
Anna Bridge 169:a7c7b631e539 719
Anna Bridge 169:a7c7b631e539 720 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
Anna Bridge 169:a7c7b631e539 721 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
Anna Bridge 169:a7c7b631e539 722
Anna Bridge 169:a7c7b631e539 723 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
Anna Bridge 169:a7c7b631e539 724 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
Anna Bridge 169:a7c7b631e539 725
Anna Bridge 169:a7c7b631e539 726 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
Anna Bridge 169:a7c7b631e539 727 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
Anna Bridge 169:a7c7b631e539 728
Anna Bridge 169:a7c7b631e539 729 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
Anna Bridge 169:a7c7b631e539 730 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
Anna Bridge 169:a7c7b631e539 731
Anna Bridge 169:a7c7b631e539 732 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
Anna Bridge 169:a7c7b631e539 733 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
Anna Bridge 169:a7c7b631e539 734
Anna Bridge 169:a7c7b631e539 735 /* SCB Configurable Fault Status Register Definitions */
Anna Bridge 169:a7c7b631e539 736 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
Anna Bridge 169:a7c7b631e539 737 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
Anna Bridge 169:a7c7b631e539 738
Anna Bridge 169:a7c7b631e539 739 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
Anna Bridge 169:a7c7b631e539 740 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
Anna Bridge 169:a7c7b631e539 741
Anna Bridge 169:a7c7b631e539 742 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
Anna Bridge 169:a7c7b631e539 743 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
Anna Bridge 169:a7c7b631e539 744
Anna Bridge 169:a7c7b631e539 745 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
Anna Bridge 169:a7c7b631e539 746 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
Anna Bridge 169:a7c7b631e539 747 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
Anna Bridge 169:a7c7b631e539 748
Anna Bridge 169:a7c7b631e539 749 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
Anna Bridge 169:a7c7b631e539 750 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
Anna Bridge 169:a7c7b631e539 751
Anna Bridge 169:a7c7b631e539 752 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
Anna Bridge 169:a7c7b631e539 753 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
Anna Bridge 169:a7c7b631e539 754
Anna Bridge 169:a7c7b631e539 755 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
Anna Bridge 169:a7c7b631e539 756 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
Anna Bridge 169:a7c7b631e539 757
Anna Bridge 169:a7c7b631e539 758 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
Anna Bridge 169:a7c7b631e539 759 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
Anna Bridge 169:a7c7b631e539 760
Anna Bridge 169:a7c7b631e539 761 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
Anna Bridge 169:a7c7b631e539 762 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
Anna Bridge 169:a7c7b631e539 763
Anna Bridge 169:a7c7b631e539 764 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
Anna Bridge 169:a7c7b631e539 765 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
Anna Bridge 169:a7c7b631e539 766 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
Anna Bridge 169:a7c7b631e539 767
Anna Bridge 169:a7c7b631e539 768 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
Anna Bridge 169:a7c7b631e539 769 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
Anna Bridge 169:a7c7b631e539 770
Anna Bridge 169:a7c7b631e539 771 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
Anna Bridge 169:a7c7b631e539 772 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
Anna Bridge 169:a7c7b631e539 773
Anna Bridge 169:a7c7b631e539 774 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
Anna Bridge 169:a7c7b631e539 775 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
Anna Bridge 169:a7c7b631e539 776
Anna Bridge 169:a7c7b631e539 777 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
Anna Bridge 169:a7c7b631e539 778 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
Anna Bridge 169:a7c7b631e539 779
Anna Bridge 169:a7c7b631e539 780 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
Anna Bridge 169:a7c7b631e539 781 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
Anna Bridge 169:a7c7b631e539 782
Anna Bridge 169:a7c7b631e539 783 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
Anna Bridge 169:a7c7b631e539 784 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
Anna Bridge 169:a7c7b631e539 785
Anna Bridge 169:a7c7b631e539 786 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
Anna Bridge 169:a7c7b631e539 787 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
Anna Bridge 169:a7c7b631e539 788 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
Anna Bridge 169:a7c7b631e539 789
Anna Bridge 169:a7c7b631e539 790 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
Anna Bridge 169:a7c7b631e539 791 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
Anna Bridge 169:a7c7b631e539 792
Anna Bridge 169:a7c7b631e539 793 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
Anna Bridge 169:a7c7b631e539 794 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
Anna Bridge 169:a7c7b631e539 795
Anna Bridge 169:a7c7b631e539 796 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
Anna Bridge 169:a7c7b631e539 797 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
Anna Bridge 169:a7c7b631e539 798
Anna Bridge 169:a7c7b631e539 799 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
Anna Bridge 169:a7c7b631e539 800 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
Anna Bridge 169:a7c7b631e539 801
Anna Bridge 169:a7c7b631e539 802 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
Anna Bridge 169:a7c7b631e539 803 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
Anna Bridge 169:a7c7b631e539 804
Anna Bridge 169:a7c7b631e539 805 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
Anna Bridge 169:a7c7b631e539 806 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
Anna Bridge 169:a7c7b631e539 807
Anna Bridge 169:a7c7b631e539 808 /* SCB Hard Fault Status Register Definitions */
Anna Bridge 169:a7c7b631e539 809 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
Anna Bridge 169:a7c7b631e539 810 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
Anna Bridge 169:a7c7b631e539 811
Anna Bridge 169:a7c7b631e539 812 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
Anna Bridge 169:a7c7b631e539 813 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
Anna Bridge 169:a7c7b631e539 814
Anna Bridge 169:a7c7b631e539 815 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
Anna Bridge 169:a7c7b631e539 816 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
Anna Bridge 169:a7c7b631e539 817
Anna Bridge 169:a7c7b631e539 818 /* SCB Debug Fault Status Register Definitions */
Anna Bridge 169:a7c7b631e539 819 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
Anna Bridge 169:a7c7b631e539 820 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
Anna Bridge 169:a7c7b631e539 821
Anna Bridge 169:a7c7b631e539 822 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
Anna Bridge 169:a7c7b631e539 823 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
Anna Bridge 169:a7c7b631e539 824
Anna Bridge 169:a7c7b631e539 825 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
Anna Bridge 169:a7c7b631e539 826 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
Anna Bridge 169:a7c7b631e539 827
Anna Bridge 169:a7c7b631e539 828 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
Anna Bridge 169:a7c7b631e539 829 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
Anna Bridge 169:a7c7b631e539 830
Anna Bridge 169:a7c7b631e539 831 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
Anna Bridge 169:a7c7b631e539 832 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
Anna Bridge 169:a7c7b631e539 833
Anna Bridge 169:a7c7b631e539 834 /* SCB Non-Secure Access Control Register Definitions */
Anna Bridge 169:a7c7b631e539 835 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
Anna Bridge 169:a7c7b631e539 836 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
Anna Bridge 169:a7c7b631e539 837
Anna Bridge 169:a7c7b631e539 838 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
Anna Bridge 169:a7c7b631e539 839 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
Anna Bridge 169:a7c7b631e539 840
Anna Bridge 169:a7c7b631e539 841 #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
Anna Bridge 169:a7c7b631e539 842 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
Anna Bridge 169:a7c7b631e539 843
Anna Bridge 169:a7c7b631e539 844 /* SCB Cache Level ID Register Definitions */
Anna Bridge 169:a7c7b631e539 845 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
Anna Bridge 169:a7c7b631e539 846 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
Anna Bridge 169:a7c7b631e539 847
Anna Bridge 169:a7c7b631e539 848 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
Anna Bridge 169:a7c7b631e539 849 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
Anna Bridge 169:a7c7b631e539 850
Anna Bridge 169:a7c7b631e539 851 /* SCB Cache Type Register Definitions */
Anna Bridge 169:a7c7b631e539 852 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
Anna Bridge 169:a7c7b631e539 853 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
Anna Bridge 169:a7c7b631e539 854
Anna Bridge 169:a7c7b631e539 855 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
Anna Bridge 169:a7c7b631e539 856 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
Anna Bridge 169:a7c7b631e539 857
Anna Bridge 169:a7c7b631e539 858 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
Anna Bridge 169:a7c7b631e539 859 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
Anna Bridge 169:a7c7b631e539 860
Anna Bridge 169:a7c7b631e539 861 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
Anna Bridge 169:a7c7b631e539 862 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
Anna Bridge 169:a7c7b631e539 863
Anna Bridge 169:a7c7b631e539 864 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
Anna Bridge 169:a7c7b631e539 865 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
Anna Bridge 169:a7c7b631e539 866
Anna Bridge 169:a7c7b631e539 867 /* SCB Cache Size ID Register Definitions */
Anna Bridge 169:a7c7b631e539 868 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
Anna Bridge 169:a7c7b631e539 869 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
Anna Bridge 169:a7c7b631e539 870
Anna Bridge 169:a7c7b631e539 871 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
Anna Bridge 169:a7c7b631e539 872 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
Anna Bridge 169:a7c7b631e539 873
Anna Bridge 169:a7c7b631e539 874 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
Anna Bridge 169:a7c7b631e539 875 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
Anna Bridge 169:a7c7b631e539 876
Anna Bridge 169:a7c7b631e539 877 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
Anna Bridge 169:a7c7b631e539 878 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
Anna Bridge 169:a7c7b631e539 879
Anna Bridge 169:a7c7b631e539 880 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
Anna Bridge 169:a7c7b631e539 881 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
Anna Bridge 169:a7c7b631e539 882
Anna Bridge 169:a7c7b631e539 883 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
Anna Bridge 169:a7c7b631e539 884 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
Anna Bridge 169:a7c7b631e539 885
Anna Bridge 169:a7c7b631e539 886 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
Anna Bridge 169:a7c7b631e539 887 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
Anna Bridge 169:a7c7b631e539 888
Anna Bridge 169:a7c7b631e539 889 /* SCB Cache Size Selection Register Definitions */
Anna Bridge 169:a7c7b631e539 890 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
Anna Bridge 169:a7c7b631e539 891 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
Anna Bridge 169:a7c7b631e539 892
Anna Bridge 169:a7c7b631e539 893 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
Anna Bridge 169:a7c7b631e539 894 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
Anna Bridge 169:a7c7b631e539 895
Anna Bridge 169:a7c7b631e539 896 /* SCB Software Triggered Interrupt Register Definitions */
Anna Bridge 169:a7c7b631e539 897 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
Anna Bridge 169:a7c7b631e539 898 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
Anna Bridge 169:a7c7b631e539 899
Anna Bridge 169:a7c7b631e539 900 /* SCB D-Cache Invalidate by Set-way Register Definitions */
Anna Bridge 169:a7c7b631e539 901 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
Anna Bridge 169:a7c7b631e539 902 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
Anna Bridge 169:a7c7b631e539 903
Anna Bridge 169:a7c7b631e539 904 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
Anna Bridge 169:a7c7b631e539 905 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
Anna Bridge 169:a7c7b631e539 906
Anna Bridge 169:a7c7b631e539 907 /* SCB D-Cache Clean by Set-way Register Definitions */
Anna Bridge 169:a7c7b631e539 908 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
Anna Bridge 169:a7c7b631e539 909 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
Anna Bridge 169:a7c7b631e539 910
Anna Bridge 169:a7c7b631e539 911 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
Anna Bridge 169:a7c7b631e539 912 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
Anna Bridge 169:a7c7b631e539 913
Anna Bridge 169:a7c7b631e539 914 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
Anna Bridge 169:a7c7b631e539 915 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
Anna Bridge 169:a7c7b631e539 916 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
Anna Bridge 169:a7c7b631e539 917
Anna Bridge 169:a7c7b631e539 918 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
Anna Bridge 169:a7c7b631e539 919 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
Anna Bridge 169:a7c7b631e539 920
Anna Bridge 169:a7c7b631e539 921 /* Instruction Tightly-Coupled Memory Control Register Definitions */
Anna Bridge 169:a7c7b631e539 922 #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
Anna Bridge 169:a7c7b631e539 923 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
Anna Bridge 169:a7c7b631e539 924
Anna Bridge 169:a7c7b631e539 925 #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
Anna Bridge 169:a7c7b631e539 926 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
Anna Bridge 169:a7c7b631e539 927
Anna Bridge 169:a7c7b631e539 928 #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
Anna Bridge 169:a7c7b631e539 929 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
Anna Bridge 169:a7c7b631e539 930
Anna Bridge 169:a7c7b631e539 931 #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
Anna Bridge 169:a7c7b631e539 932 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
Anna Bridge 169:a7c7b631e539 933
Anna Bridge 169:a7c7b631e539 934 /* Data Tightly-Coupled Memory Control Register Definitions */
Anna Bridge 169:a7c7b631e539 935 #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
Anna Bridge 169:a7c7b631e539 936 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
Anna Bridge 169:a7c7b631e539 937
Anna Bridge 169:a7c7b631e539 938 #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
Anna Bridge 169:a7c7b631e539 939 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
Anna Bridge 169:a7c7b631e539 940
Anna Bridge 169:a7c7b631e539 941 #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
Anna Bridge 169:a7c7b631e539 942 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
Anna Bridge 169:a7c7b631e539 943
Anna Bridge 169:a7c7b631e539 944 #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
Anna Bridge 169:a7c7b631e539 945 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
Anna Bridge 169:a7c7b631e539 946
Anna Bridge 169:a7c7b631e539 947 /* AHBP Control Register Definitions */
Anna Bridge 169:a7c7b631e539 948 #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
Anna Bridge 169:a7c7b631e539 949 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
Anna Bridge 169:a7c7b631e539 950
Anna Bridge 169:a7c7b631e539 951 #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
Anna Bridge 169:a7c7b631e539 952 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
Anna Bridge 169:a7c7b631e539 953
Anna Bridge 169:a7c7b631e539 954 /* L1 Cache Control Register Definitions */
Anna Bridge 169:a7c7b631e539 955 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
Anna Bridge 169:a7c7b631e539 956 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
Anna Bridge 169:a7c7b631e539 957
Anna Bridge 169:a7c7b631e539 958 #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
Anna Bridge 169:a7c7b631e539 959 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
Anna Bridge 169:a7c7b631e539 960
Anna Bridge 169:a7c7b631e539 961 #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
Anna Bridge 169:a7c7b631e539 962 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
Anna Bridge 169:a7c7b631e539 963
Anna Bridge 169:a7c7b631e539 964 /* AHBS Control Register Definitions */
Anna Bridge 169:a7c7b631e539 965 #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
Anna Bridge 169:a7c7b631e539 966 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
Anna Bridge 169:a7c7b631e539 967
Anna Bridge 169:a7c7b631e539 968 #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
Anna Bridge 169:a7c7b631e539 969 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
Anna Bridge 169:a7c7b631e539 970
Anna Bridge 169:a7c7b631e539 971 #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
Anna Bridge 169:a7c7b631e539 972 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
Anna Bridge 169:a7c7b631e539 973
Anna Bridge 169:a7c7b631e539 974 /* Auxiliary Bus Fault Status Register Definitions */
Anna Bridge 169:a7c7b631e539 975 #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
Anna Bridge 169:a7c7b631e539 976 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
Anna Bridge 169:a7c7b631e539 977
Anna Bridge 169:a7c7b631e539 978 #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
Anna Bridge 169:a7c7b631e539 979 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
Anna Bridge 169:a7c7b631e539 980
Anna Bridge 169:a7c7b631e539 981 #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
Anna Bridge 169:a7c7b631e539 982 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
Anna Bridge 169:a7c7b631e539 983
Anna Bridge 169:a7c7b631e539 984 #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
Anna Bridge 169:a7c7b631e539 985 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
Anna Bridge 169:a7c7b631e539 986
Anna Bridge 169:a7c7b631e539 987 #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
Anna Bridge 169:a7c7b631e539 988 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
Anna Bridge 169:a7c7b631e539 989
Anna Bridge 169:a7c7b631e539 990 #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
Anna Bridge 169:a7c7b631e539 991 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
Anna Bridge 169:a7c7b631e539 992
Anna Bridge 169:a7c7b631e539 993 /*@} end of group CMSIS_SCB */
Anna Bridge 169:a7c7b631e539 994
Anna Bridge 169:a7c7b631e539 995
Anna Bridge 169:a7c7b631e539 996 /**
Anna Bridge 169:a7c7b631e539 997 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 998 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Anna Bridge 169:a7c7b631e539 999 \brief Type definitions for the System Control and ID Register not in the SCB
Anna Bridge 169:a7c7b631e539 1000 @{
Anna Bridge 169:a7c7b631e539 1001 */
Anna Bridge 169:a7c7b631e539 1002
Anna Bridge 169:a7c7b631e539 1003 /**
Anna Bridge 169:a7c7b631e539 1004 \brief Structure type to access the System Control and ID Register not in the SCB.
Anna Bridge 169:a7c7b631e539 1005 */
Anna Bridge 169:a7c7b631e539 1006 typedef struct
Anna Bridge 169:a7c7b631e539 1007 {
Anna Bridge 169:a7c7b631e539 1008 uint32_t RESERVED0[1U];
Anna Bridge 169:a7c7b631e539 1009 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
Anna Bridge 169:a7c7b631e539 1010 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
Anna Bridge 169:a7c7b631e539 1011 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
Anna Bridge 169:a7c7b631e539 1012 } SCnSCB_Type;
Anna Bridge 169:a7c7b631e539 1013
Anna Bridge 169:a7c7b631e539 1014 /* Interrupt Controller Type Register Definitions */
Anna Bridge 169:a7c7b631e539 1015 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
Anna Bridge 169:a7c7b631e539 1016 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
Anna Bridge 169:a7c7b631e539 1017
Anna Bridge 169:a7c7b631e539 1018 /*@} end of group CMSIS_SCnotSCB */
Anna Bridge 169:a7c7b631e539 1019
Anna Bridge 169:a7c7b631e539 1020
Anna Bridge 169:a7c7b631e539 1021 /**
Anna Bridge 169:a7c7b631e539 1022 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 1023 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Anna Bridge 169:a7c7b631e539 1024 \brief Type definitions for the System Timer Registers.
Anna Bridge 169:a7c7b631e539 1025 @{
Anna Bridge 169:a7c7b631e539 1026 */
Anna Bridge 169:a7c7b631e539 1027
Anna Bridge 169:a7c7b631e539 1028 /**
Anna Bridge 169:a7c7b631e539 1029 \brief Structure type to access the System Timer (SysTick).
Anna Bridge 169:a7c7b631e539 1030 */
Anna Bridge 169:a7c7b631e539 1031 typedef struct
Anna Bridge 169:a7c7b631e539 1032 {
Anna Bridge 169:a7c7b631e539 1033 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Anna Bridge 169:a7c7b631e539 1034 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Anna Bridge 169:a7c7b631e539 1035 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Anna Bridge 169:a7c7b631e539 1036 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Anna Bridge 169:a7c7b631e539 1037 } SysTick_Type;
Anna Bridge 169:a7c7b631e539 1038
Anna Bridge 169:a7c7b631e539 1039 /* SysTick Control / Status Register Definitions */
Anna Bridge 169:a7c7b631e539 1040 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
Anna Bridge 169:a7c7b631e539 1041 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Anna Bridge 169:a7c7b631e539 1042
Anna Bridge 169:a7c7b631e539 1043 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
Anna Bridge 169:a7c7b631e539 1044 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Anna Bridge 169:a7c7b631e539 1045
Anna Bridge 169:a7c7b631e539 1046 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
Anna Bridge 169:a7c7b631e539 1047 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Anna Bridge 169:a7c7b631e539 1048
Anna Bridge 169:a7c7b631e539 1049 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
Anna Bridge 169:a7c7b631e539 1050 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Anna Bridge 169:a7c7b631e539 1051
Anna Bridge 169:a7c7b631e539 1052 /* SysTick Reload Register Definitions */
Anna Bridge 169:a7c7b631e539 1053 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
Anna Bridge 169:a7c7b631e539 1054 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Anna Bridge 169:a7c7b631e539 1055
Anna Bridge 169:a7c7b631e539 1056 /* SysTick Current Register Definitions */
Anna Bridge 169:a7c7b631e539 1057 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
Anna Bridge 169:a7c7b631e539 1058 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Anna Bridge 169:a7c7b631e539 1059
Anna Bridge 169:a7c7b631e539 1060 /* SysTick Calibration Register Definitions */
Anna Bridge 169:a7c7b631e539 1061 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
Anna Bridge 169:a7c7b631e539 1062 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Anna Bridge 169:a7c7b631e539 1063
Anna Bridge 169:a7c7b631e539 1064 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
Anna Bridge 169:a7c7b631e539 1065 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Anna Bridge 169:a7c7b631e539 1066
Anna Bridge 169:a7c7b631e539 1067 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
Anna Bridge 169:a7c7b631e539 1068 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Anna Bridge 169:a7c7b631e539 1069
Anna Bridge 169:a7c7b631e539 1070 /*@} end of group CMSIS_SysTick */
Anna Bridge 169:a7c7b631e539 1071
Anna Bridge 169:a7c7b631e539 1072
Anna Bridge 169:a7c7b631e539 1073 /**
Anna Bridge 169:a7c7b631e539 1074 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 1075 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Anna Bridge 169:a7c7b631e539 1076 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Anna Bridge 169:a7c7b631e539 1077 @{
Anna Bridge 169:a7c7b631e539 1078 */
Anna Bridge 169:a7c7b631e539 1079
Anna Bridge 169:a7c7b631e539 1080 /**
Anna Bridge 169:a7c7b631e539 1081 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Anna Bridge 169:a7c7b631e539 1082 */
Anna Bridge 169:a7c7b631e539 1083 typedef struct
Anna Bridge 169:a7c7b631e539 1084 {
Anna Bridge 169:a7c7b631e539 1085 __OM union
Anna Bridge 169:a7c7b631e539 1086 {
Anna Bridge 169:a7c7b631e539 1087 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
Anna Bridge 169:a7c7b631e539 1088 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
Anna Bridge 169:a7c7b631e539 1089 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
Anna Bridge 169:a7c7b631e539 1090 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
Anna Bridge 169:a7c7b631e539 1091 uint32_t RESERVED0[864U];
Anna Bridge 169:a7c7b631e539 1092 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
Anna Bridge 169:a7c7b631e539 1093 uint32_t RESERVED1[15U];
Anna Bridge 169:a7c7b631e539 1094 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
Anna Bridge 169:a7c7b631e539 1095 uint32_t RESERVED2[15U];
Anna Bridge 169:a7c7b631e539 1096 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
Anna Bridge 169:a7c7b631e539 1097 uint32_t RESERVED3[29U];
Anna Bridge 169:a7c7b631e539 1098 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
Anna Bridge 169:a7c7b631e539 1099 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
Anna Bridge 169:a7c7b631e539 1100 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
Anna Bridge 169:a7c7b631e539 1101 uint32_t RESERVED4[43U];
Anna Bridge 169:a7c7b631e539 1102 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
Anna Bridge 169:a7c7b631e539 1103 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
Anna Bridge 169:a7c7b631e539 1104 uint32_t RESERVED5[1U];
Anna Bridge 169:a7c7b631e539 1105 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
Anna Bridge 169:a7c7b631e539 1106 uint32_t RESERVED6[4U];
Anna Bridge 169:a7c7b631e539 1107 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
Anna Bridge 169:a7c7b631e539 1108 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
Anna Bridge 169:a7c7b631e539 1109 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
Anna Bridge 169:a7c7b631e539 1110 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
Anna Bridge 169:a7c7b631e539 1111 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
Anna Bridge 169:a7c7b631e539 1112 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
Anna Bridge 169:a7c7b631e539 1113 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
Anna Bridge 169:a7c7b631e539 1114 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
Anna Bridge 169:a7c7b631e539 1115 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
Anna Bridge 169:a7c7b631e539 1116 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
Anna Bridge 169:a7c7b631e539 1117 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
Anna Bridge 169:a7c7b631e539 1118 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
Anna Bridge 169:a7c7b631e539 1119 } ITM_Type;
Anna Bridge 169:a7c7b631e539 1120
Anna Bridge 169:a7c7b631e539 1121 /* ITM Stimulus Port Register Definitions */
Anna Bridge 169:a7c7b631e539 1122 #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
Anna Bridge 169:a7c7b631e539 1123 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
Anna Bridge 169:a7c7b631e539 1124
Anna Bridge 169:a7c7b631e539 1125 #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
Anna Bridge 169:a7c7b631e539 1126 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
Anna Bridge 169:a7c7b631e539 1127
Anna Bridge 169:a7c7b631e539 1128 /* ITM Trace Privilege Register Definitions */
Anna Bridge 169:a7c7b631e539 1129 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
Anna Bridge 169:a7c7b631e539 1130 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
Anna Bridge 169:a7c7b631e539 1131
Anna Bridge 169:a7c7b631e539 1132 /* ITM Trace Control Register Definitions */
Anna Bridge 169:a7c7b631e539 1133 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
Anna Bridge 169:a7c7b631e539 1134 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
Anna Bridge 169:a7c7b631e539 1135
Anna Bridge 169:a7c7b631e539 1136 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
Anna Bridge 169:a7c7b631e539 1137 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
Anna Bridge 169:a7c7b631e539 1138
Anna Bridge 169:a7c7b631e539 1139 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
Anna Bridge 169:a7c7b631e539 1140 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
Anna Bridge 169:a7c7b631e539 1141
Anna Bridge 169:a7c7b631e539 1142 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
Anna Bridge 169:a7c7b631e539 1143 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
Anna Bridge 169:a7c7b631e539 1144
Anna Bridge 169:a7c7b631e539 1145 #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
Anna Bridge 169:a7c7b631e539 1146 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
Anna Bridge 169:a7c7b631e539 1147
Anna Bridge 169:a7c7b631e539 1148 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
Anna Bridge 169:a7c7b631e539 1149 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
Anna Bridge 169:a7c7b631e539 1150
Anna Bridge 169:a7c7b631e539 1151 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
Anna Bridge 169:a7c7b631e539 1152 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
Anna Bridge 169:a7c7b631e539 1153
Anna Bridge 169:a7c7b631e539 1154 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
Anna Bridge 169:a7c7b631e539 1155 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
Anna Bridge 169:a7c7b631e539 1156
Anna Bridge 169:a7c7b631e539 1157 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
Anna Bridge 169:a7c7b631e539 1158 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
Anna Bridge 169:a7c7b631e539 1159
Anna Bridge 169:a7c7b631e539 1160 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
Anna Bridge 169:a7c7b631e539 1161 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
Anna Bridge 169:a7c7b631e539 1162
Anna Bridge 169:a7c7b631e539 1163 /* ITM Integration Write Register Definitions */
Anna Bridge 169:a7c7b631e539 1164 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
Anna Bridge 169:a7c7b631e539 1165 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
Anna Bridge 169:a7c7b631e539 1166
Anna Bridge 169:a7c7b631e539 1167 /* ITM Integration Read Register Definitions */
Anna Bridge 169:a7c7b631e539 1168 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
Anna Bridge 169:a7c7b631e539 1169 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
Anna Bridge 169:a7c7b631e539 1170
Anna Bridge 169:a7c7b631e539 1171 /* ITM Integration Mode Control Register Definitions */
Anna Bridge 169:a7c7b631e539 1172 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
Anna Bridge 169:a7c7b631e539 1173 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
Anna Bridge 169:a7c7b631e539 1174
Anna Bridge 169:a7c7b631e539 1175 /* ITM Lock Status Register Definitions */
Anna Bridge 169:a7c7b631e539 1176 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
Anna Bridge 169:a7c7b631e539 1177 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
Anna Bridge 169:a7c7b631e539 1178
Anna Bridge 169:a7c7b631e539 1179 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
Anna Bridge 169:a7c7b631e539 1180 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
Anna Bridge 169:a7c7b631e539 1181
Anna Bridge 169:a7c7b631e539 1182 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
Anna Bridge 169:a7c7b631e539 1183 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
Anna Bridge 169:a7c7b631e539 1184
Anna Bridge 169:a7c7b631e539 1185 /*@}*/ /* end of group CMSIS_ITM */
Anna Bridge 169:a7c7b631e539 1186
Anna Bridge 169:a7c7b631e539 1187
Anna Bridge 169:a7c7b631e539 1188 /**
Anna Bridge 169:a7c7b631e539 1189 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 1190 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Anna Bridge 169:a7c7b631e539 1191 \brief Type definitions for the Data Watchpoint and Trace (DWT)
Anna Bridge 169:a7c7b631e539 1192 @{
Anna Bridge 169:a7c7b631e539 1193 */
Anna Bridge 169:a7c7b631e539 1194
Anna Bridge 169:a7c7b631e539 1195 /**
Anna Bridge 169:a7c7b631e539 1196 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Anna Bridge 169:a7c7b631e539 1197 */
Anna Bridge 169:a7c7b631e539 1198 typedef struct
Anna Bridge 169:a7c7b631e539 1199 {
Anna Bridge 169:a7c7b631e539 1200 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
Anna Bridge 169:a7c7b631e539 1201 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
Anna Bridge 169:a7c7b631e539 1202 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
Anna Bridge 169:a7c7b631e539 1203 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
Anna Bridge 169:a7c7b631e539 1204 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
Anna Bridge 169:a7c7b631e539 1205 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
Anna Bridge 169:a7c7b631e539 1206 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
Anna Bridge 169:a7c7b631e539 1207 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
Anna Bridge 169:a7c7b631e539 1208 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
Anna Bridge 169:a7c7b631e539 1209 uint32_t RESERVED1[1U];
Anna Bridge 169:a7c7b631e539 1210 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
Anna Bridge 169:a7c7b631e539 1211 uint32_t RESERVED2[1U];
Anna Bridge 169:a7c7b631e539 1212 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
Anna Bridge 169:a7c7b631e539 1213 uint32_t RESERVED3[1U];
Anna Bridge 169:a7c7b631e539 1214 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
Anna Bridge 169:a7c7b631e539 1215 uint32_t RESERVED4[1U];
Anna Bridge 169:a7c7b631e539 1216 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
Anna Bridge 169:a7c7b631e539 1217 uint32_t RESERVED5[1U];
Anna Bridge 169:a7c7b631e539 1218 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
Anna Bridge 169:a7c7b631e539 1219 uint32_t RESERVED6[1U];
Anna Bridge 169:a7c7b631e539 1220 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
Anna Bridge 169:a7c7b631e539 1221 uint32_t RESERVED7[1U];
Anna Bridge 169:a7c7b631e539 1222 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
Anna Bridge 169:a7c7b631e539 1223 uint32_t RESERVED8[1U];
Anna Bridge 169:a7c7b631e539 1224 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
Anna Bridge 169:a7c7b631e539 1225 uint32_t RESERVED9[1U];
Anna Bridge 169:a7c7b631e539 1226 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
Anna Bridge 169:a7c7b631e539 1227 uint32_t RESERVED10[1U];
Anna Bridge 169:a7c7b631e539 1228 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
Anna Bridge 169:a7c7b631e539 1229 uint32_t RESERVED11[1U];
Anna Bridge 169:a7c7b631e539 1230 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
Anna Bridge 169:a7c7b631e539 1231 uint32_t RESERVED12[1U];
Anna Bridge 169:a7c7b631e539 1232 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
Anna Bridge 169:a7c7b631e539 1233 uint32_t RESERVED13[1U];
Anna Bridge 169:a7c7b631e539 1234 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
Anna Bridge 169:a7c7b631e539 1235 uint32_t RESERVED14[1U];
Anna Bridge 169:a7c7b631e539 1236 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
Anna Bridge 169:a7c7b631e539 1237 uint32_t RESERVED15[1U];
Anna Bridge 169:a7c7b631e539 1238 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
Anna Bridge 169:a7c7b631e539 1239 uint32_t RESERVED16[1U];
Anna Bridge 169:a7c7b631e539 1240 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
Anna Bridge 169:a7c7b631e539 1241 uint32_t RESERVED17[1U];
Anna Bridge 169:a7c7b631e539 1242 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
Anna Bridge 169:a7c7b631e539 1243 uint32_t RESERVED18[1U];
Anna Bridge 169:a7c7b631e539 1244 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
Anna Bridge 169:a7c7b631e539 1245 uint32_t RESERVED19[1U];
Anna Bridge 169:a7c7b631e539 1246 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
Anna Bridge 169:a7c7b631e539 1247 uint32_t RESERVED20[1U];
Anna Bridge 169:a7c7b631e539 1248 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
Anna Bridge 169:a7c7b631e539 1249 uint32_t RESERVED21[1U];
Anna Bridge 169:a7c7b631e539 1250 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
Anna Bridge 169:a7c7b631e539 1251 uint32_t RESERVED22[1U];
Anna Bridge 169:a7c7b631e539 1252 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
Anna Bridge 169:a7c7b631e539 1253 uint32_t RESERVED23[1U];
Anna Bridge 169:a7c7b631e539 1254 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
Anna Bridge 169:a7c7b631e539 1255 uint32_t RESERVED24[1U];
Anna Bridge 169:a7c7b631e539 1256 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
Anna Bridge 169:a7c7b631e539 1257 uint32_t RESERVED25[1U];
Anna Bridge 169:a7c7b631e539 1258 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
Anna Bridge 169:a7c7b631e539 1259 uint32_t RESERVED26[1U];
Anna Bridge 169:a7c7b631e539 1260 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
Anna Bridge 169:a7c7b631e539 1261 uint32_t RESERVED27[1U];
Anna Bridge 169:a7c7b631e539 1262 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
Anna Bridge 169:a7c7b631e539 1263 uint32_t RESERVED28[1U];
Anna Bridge 169:a7c7b631e539 1264 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
Anna Bridge 169:a7c7b631e539 1265 uint32_t RESERVED29[1U];
Anna Bridge 169:a7c7b631e539 1266 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
Anna Bridge 169:a7c7b631e539 1267 uint32_t RESERVED30[1U];
Anna Bridge 169:a7c7b631e539 1268 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
Anna Bridge 169:a7c7b631e539 1269 uint32_t RESERVED31[1U];
Anna Bridge 169:a7c7b631e539 1270 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
Anna Bridge 169:a7c7b631e539 1271 uint32_t RESERVED32[934U];
Anna Bridge 169:a7c7b631e539 1272 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
Anna Bridge 169:a7c7b631e539 1273 uint32_t RESERVED33[1U];
Anna Bridge 169:a7c7b631e539 1274 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
Anna Bridge 169:a7c7b631e539 1275 } DWT_Type;
Anna Bridge 169:a7c7b631e539 1276
Anna Bridge 169:a7c7b631e539 1277 /* DWT Control Register Definitions */
Anna Bridge 169:a7c7b631e539 1278 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
Anna Bridge 169:a7c7b631e539 1279 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
Anna Bridge 169:a7c7b631e539 1280
Anna Bridge 169:a7c7b631e539 1281 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
Anna Bridge 169:a7c7b631e539 1282 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
Anna Bridge 169:a7c7b631e539 1283
Anna Bridge 169:a7c7b631e539 1284 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
Anna Bridge 169:a7c7b631e539 1285 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
Anna Bridge 169:a7c7b631e539 1286
Anna Bridge 169:a7c7b631e539 1287 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
Anna Bridge 169:a7c7b631e539 1288 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
Anna Bridge 169:a7c7b631e539 1289
Anna Bridge 169:a7c7b631e539 1290 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
Anna Bridge 169:a7c7b631e539 1291 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
Anna Bridge 169:a7c7b631e539 1292
Anna Bridge 169:a7c7b631e539 1293 #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
Anna Bridge 169:a7c7b631e539 1294 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
Anna Bridge 169:a7c7b631e539 1295
Anna Bridge 169:a7c7b631e539 1296 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
Anna Bridge 169:a7c7b631e539 1297 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
Anna Bridge 169:a7c7b631e539 1298
Anna Bridge 169:a7c7b631e539 1299 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
Anna Bridge 169:a7c7b631e539 1300 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
Anna Bridge 169:a7c7b631e539 1301
Anna Bridge 169:a7c7b631e539 1302 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
Anna Bridge 169:a7c7b631e539 1303 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
Anna Bridge 169:a7c7b631e539 1304
Anna Bridge 169:a7c7b631e539 1305 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
Anna Bridge 169:a7c7b631e539 1306 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
Anna Bridge 169:a7c7b631e539 1307
Anna Bridge 169:a7c7b631e539 1308 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
Anna Bridge 169:a7c7b631e539 1309 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
Anna Bridge 169:a7c7b631e539 1310
Anna Bridge 169:a7c7b631e539 1311 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
Anna Bridge 169:a7c7b631e539 1312 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
Anna Bridge 169:a7c7b631e539 1313
Anna Bridge 169:a7c7b631e539 1314 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
Anna Bridge 169:a7c7b631e539 1315 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
Anna Bridge 169:a7c7b631e539 1316
Anna Bridge 169:a7c7b631e539 1317 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
Anna Bridge 169:a7c7b631e539 1318 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
Anna Bridge 169:a7c7b631e539 1319
Anna Bridge 169:a7c7b631e539 1320 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
Anna Bridge 169:a7c7b631e539 1321 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
Anna Bridge 169:a7c7b631e539 1322
Anna Bridge 169:a7c7b631e539 1323 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
Anna Bridge 169:a7c7b631e539 1324 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
Anna Bridge 169:a7c7b631e539 1325
Anna Bridge 169:a7c7b631e539 1326 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
Anna Bridge 169:a7c7b631e539 1327 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
Anna Bridge 169:a7c7b631e539 1328
Anna Bridge 169:a7c7b631e539 1329 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
Anna Bridge 169:a7c7b631e539 1330 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
Anna Bridge 169:a7c7b631e539 1331
Anna Bridge 169:a7c7b631e539 1332 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
Anna Bridge 169:a7c7b631e539 1333 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
Anna Bridge 169:a7c7b631e539 1334
Anna Bridge 169:a7c7b631e539 1335 /* DWT CPI Count Register Definitions */
Anna Bridge 169:a7c7b631e539 1336 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
Anna Bridge 169:a7c7b631e539 1337 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
Anna Bridge 169:a7c7b631e539 1338
Anna Bridge 169:a7c7b631e539 1339 /* DWT Exception Overhead Count Register Definitions */
Anna Bridge 169:a7c7b631e539 1340 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
Anna Bridge 169:a7c7b631e539 1341 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
Anna Bridge 169:a7c7b631e539 1342
Anna Bridge 169:a7c7b631e539 1343 /* DWT Sleep Count Register Definitions */
Anna Bridge 169:a7c7b631e539 1344 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
Anna Bridge 169:a7c7b631e539 1345 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
Anna Bridge 169:a7c7b631e539 1346
Anna Bridge 169:a7c7b631e539 1347 /* DWT LSU Count Register Definitions */
Anna Bridge 169:a7c7b631e539 1348 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
Anna Bridge 169:a7c7b631e539 1349 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
Anna Bridge 169:a7c7b631e539 1350
Anna Bridge 169:a7c7b631e539 1351 /* DWT Folded-instruction Count Register Definitions */
Anna Bridge 169:a7c7b631e539 1352 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
Anna Bridge 169:a7c7b631e539 1353 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
Anna Bridge 169:a7c7b631e539 1354
Anna Bridge 169:a7c7b631e539 1355 /* DWT Comparator Function Register Definitions */
Anna Bridge 169:a7c7b631e539 1356 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
Anna Bridge 169:a7c7b631e539 1357 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
Anna Bridge 169:a7c7b631e539 1358
Anna Bridge 169:a7c7b631e539 1359 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
Anna Bridge 169:a7c7b631e539 1360 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
Anna Bridge 169:a7c7b631e539 1361
Anna Bridge 169:a7c7b631e539 1362 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
Anna Bridge 169:a7c7b631e539 1363 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
Anna Bridge 169:a7c7b631e539 1364
Anna Bridge 169:a7c7b631e539 1365 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
Anna Bridge 169:a7c7b631e539 1366 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
Anna Bridge 169:a7c7b631e539 1367
Anna Bridge 169:a7c7b631e539 1368 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
Anna Bridge 169:a7c7b631e539 1369 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
Anna Bridge 169:a7c7b631e539 1370
Anna Bridge 169:a7c7b631e539 1371 /*@}*/ /* end of group CMSIS_DWT */
Anna Bridge 169:a7c7b631e539 1372
Anna Bridge 169:a7c7b631e539 1373
Anna Bridge 169:a7c7b631e539 1374 /**
Anna Bridge 169:a7c7b631e539 1375 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 1376 \defgroup CMSIS_TPI Trace Port Interface (TPI)
Anna Bridge 169:a7c7b631e539 1377 \brief Type definitions for the Trace Port Interface (TPI)
Anna Bridge 169:a7c7b631e539 1378 @{
Anna Bridge 169:a7c7b631e539 1379 */
Anna Bridge 169:a7c7b631e539 1380
Anna Bridge 169:a7c7b631e539 1381 /**
Anna Bridge 169:a7c7b631e539 1382 \brief Structure type to access the Trace Port Interface Register (TPI).
Anna Bridge 169:a7c7b631e539 1383 */
Anna Bridge 169:a7c7b631e539 1384 typedef struct
Anna Bridge 169:a7c7b631e539 1385 {
Anna Bridge 169:a7c7b631e539 1386 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
Anna Bridge 169:a7c7b631e539 1387 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
Anna Bridge 169:a7c7b631e539 1388 uint32_t RESERVED0[2U];
Anna Bridge 169:a7c7b631e539 1389 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
Anna Bridge 169:a7c7b631e539 1390 uint32_t RESERVED1[55U];
Anna Bridge 169:a7c7b631e539 1391 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
Anna Bridge 169:a7c7b631e539 1392 uint32_t RESERVED2[131U];
Anna Bridge 169:a7c7b631e539 1393 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
Anna Bridge 169:a7c7b631e539 1394 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
Anna Bridge 169:a7c7b631e539 1395 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
Anna Bridge 169:a7c7b631e539 1396 uint32_t RESERVED3[759U];
Anna Bridge 169:a7c7b631e539 1397 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
Anna Bridge 169:a7c7b631e539 1398 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
Anna Bridge 169:a7c7b631e539 1399 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
Anna Bridge 169:a7c7b631e539 1400 uint32_t RESERVED4[1U];
Anna Bridge 169:a7c7b631e539 1401 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
Anna Bridge 169:a7c7b631e539 1402 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
Anna Bridge 169:a7c7b631e539 1403 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
Anna Bridge 169:a7c7b631e539 1404 uint32_t RESERVED5[39U];
Anna Bridge 169:a7c7b631e539 1405 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
Anna Bridge 169:a7c7b631e539 1406 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
Anna Bridge 169:a7c7b631e539 1407 uint32_t RESERVED7[8U];
Anna Bridge 169:a7c7b631e539 1408 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
Anna Bridge 169:a7c7b631e539 1409 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
Anna Bridge 169:a7c7b631e539 1410 } TPI_Type;
Anna Bridge 169:a7c7b631e539 1411
Anna Bridge 169:a7c7b631e539 1412 /* TPI Asynchronous Clock Prescaler Register Definitions */
Anna Bridge 169:a7c7b631e539 1413 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
Anna Bridge 169:a7c7b631e539 1414 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
Anna Bridge 169:a7c7b631e539 1415
Anna Bridge 169:a7c7b631e539 1416 /* TPI Selected Pin Protocol Register Definitions */
Anna Bridge 169:a7c7b631e539 1417 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
Anna Bridge 169:a7c7b631e539 1418 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
Anna Bridge 169:a7c7b631e539 1419
Anna Bridge 169:a7c7b631e539 1420 /* TPI Formatter and Flush Status Register Definitions */
Anna Bridge 169:a7c7b631e539 1421 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
Anna Bridge 169:a7c7b631e539 1422 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
Anna Bridge 169:a7c7b631e539 1423
Anna Bridge 169:a7c7b631e539 1424 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
Anna Bridge 169:a7c7b631e539 1425 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
Anna Bridge 169:a7c7b631e539 1426
Anna Bridge 169:a7c7b631e539 1427 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
Anna Bridge 169:a7c7b631e539 1428 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
Anna Bridge 169:a7c7b631e539 1429
Anna Bridge 169:a7c7b631e539 1430 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
Anna Bridge 169:a7c7b631e539 1431 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
Anna Bridge 169:a7c7b631e539 1432
Anna Bridge 169:a7c7b631e539 1433 /* TPI Formatter and Flush Control Register Definitions */
Anna Bridge 169:a7c7b631e539 1434 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
Anna Bridge 169:a7c7b631e539 1435 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
Anna Bridge 169:a7c7b631e539 1436
Anna Bridge 169:a7c7b631e539 1437 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
Anna Bridge 169:a7c7b631e539 1438 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
Anna Bridge 169:a7c7b631e539 1439
Anna Bridge 169:a7c7b631e539 1440 /* TPI TRIGGER Register Definitions */
Anna Bridge 169:a7c7b631e539 1441 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
Anna Bridge 169:a7c7b631e539 1442 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
Anna Bridge 169:a7c7b631e539 1443
Anna Bridge 169:a7c7b631e539 1444 /* TPI Integration ETM Data Register Definitions (FIFO0) */
Anna Bridge 169:a7c7b631e539 1445 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
Anna Bridge 169:a7c7b631e539 1446 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
Anna Bridge 169:a7c7b631e539 1447
Anna Bridge 169:a7c7b631e539 1448 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
Anna Bridge 169:a7c7b631e539 1449 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
Anna Bridge 169:a7c7b631e539 1450
Anna Bridge 169:a7c7b631e539 1451 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
Anna Bridge 169:a7c7b631e539 1452 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
Anna Bridge 169:a7c7b631e539 1453
Anna Bridge 169:a7c7b631e539 1454 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
Anna Bridge 169:a7c7b631e539 1455 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
Anna Bridge 169:a7c7b631e539 1456
Anna Bridge 169:a7c7b631e539 1457 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
Anna Bridge 169:a7c7b631e539 1458 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
Anna Bridge 169:a7c7b631e539 1459
Anna Bridge 169:a7c7b631e539 1460 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
Anna Bridge 169:a7c7b631e539 1461 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
Anna Bridge 169:a7c7b631e539 1462
Anna Bridge 169:a7c7b631e539 1463 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
Anna Bridge 169:a7c7b631e539 1464 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
Anna Bridge 169:a7c7b631e539 1465
Anna Bridge 169:a7c7b631e539 1466 /* TPI ITATBCTR2 Register Definitions */
Anna Bridge 169:a7c7b631e539 1467 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
Anna Bridge 169:a7c7b631e539 1468 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
Anna Bridge 169:a7c7b631e539 1469
Anna Bridge 169:a7c7b631e539 1470 /* TPI Integration ITM Data Register Definitions (FIFO1) */
Anna Bridge 169:a7c7b631e539 1471 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
Anna Bridge 169:a7c7b631e539 1472 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
Anna Bridge 169:a7c7b631e539 1473
Anna Bridge 169:a7c7b631e539 1474 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
Anna Bridge 169:a7c7b631e539 1475 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
Anna Bridge 169:a7c7b631e539 1476
Anna Bridge 169:a7c7b631e539 1477 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
Anna Bridge 169:a7c7b631e539 1478 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
Anna Bridge 169:a7c7b631e539 1479
Anna Bridge 169:a7c7b631e539 1480 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
Anna Bridge 169:a7c7b631e539 1481 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
Anna Bridge 169:a7c7b631e539 1482
Anna Bridge 169:a7c7b631e539 1483 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
Anna Bridge 169:a7c7b631e539 1484 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
Anna Bridge 169:a7c7b631e539 1485
Anna Bridge 169:a7c7b631e539 1486 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
Anna Bridge 169:a7c7b631e539 1487 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
Anna Bridge 169:a7c7b631e539 1488
Anna Bridge 169:a7c7b631e539 1489 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
Anna Bridge 169:a7c7b631e539 1490 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
Anna Bridge 169:a7c7b631e539 1491
Anna Bridge 169:a7c7b631e539 1492 /* TPI ITATBCTR0 Register Definitions */
Anna Bridge 169:a7c7b631e539 1493 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
Anna Bridge 169:a7c7b631e539 1494 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
Anna Bridge 169:a7c7b631e539 1495
Anna Bridge 169:a7c7b631e539 1496 /* TPI Integration Mode Control Register Definitions */
Anna Bridge 169:a7c7b631e539 1497 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
Anna Bridge 169:a7c7b631e539 1498 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
Anna Bridge 169:a7c7b631e539 1499
Anna Bridge 169:a7c7b631e539 1500 /* TPI DEVID Register Definitions */
Anna Bridge 169:a7c7b631e539 1501 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
Anna Bridge 169:a7c7b631e539 1502 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
Anna Bridge 169:a7c7b631e539 1503
Anna Bridge 169:a7c7b631e539 1504 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
Anna Bridge 169:a7c7b631e539 1505 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
Anna Bridge 169:a7c7b631e539 1506
Anna Bridge 169:a7c7b631e539 1507 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
Anna Bridge 169:a7c7b631e539 1508 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
Anna Bridge 169:a7c7b631e539 1509
Anna Bridge 169:a7c7b631e539 1510 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
Anna Bridge 169:a7c7b631e539 1511 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
Anna Bridge 169:a7c7b631e539 1512
Anna Bridge 169:a7c7b631e539 1513 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
Anna Bridge 169:a7c7b631e539 1514 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
Anna Bridge 169:a7c7b631e539 1515
Anna Bridge 169:a7c7b631e539 1516 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
Anna Bridge 169:a7c7b631e539 1517 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
Anna Bridge 169:a7c7b631e539 1518
Anna Bridge 169:a7c7b631e539 1519 /* TPI DEVTYPE Register Definitions */
Anna Bridge 169:a7c7b631e539 1520 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
Anna Bridge 169:a7c7b631e539 1521 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
Anna Bridge 169:a7c7b631e539 1522
Anna Bridge 169:a7c7b631e539 1523 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
Anna Bridge 169:a7c7b631e539 1524 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
Anna Bridge 169:a7c7b631e539 1525
Anna Bridge 169:a7c7b631e539 1526 /*@}*/ /* end of group CMSIS_TPI */
Anna Bridge 169:a7c7b631e539 1527
Anna Bridge 169:a7c7b631e539 1528
Anna Bridge 169:a7c7b631e539 1529 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 1530 /**
Anna Bridge 169:a7c7b631e539 1531 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 1532 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Anna Bridge 169:a7c7b631e539 1533 \brief Type definitions for the Memory Protection Unit (MPU)
Anna Bridge 169:a7c7b631e539 1534 @{
Anna Bridge 169:a7c7b631e539 1535 */
Anna Bridge 169:a7c7b631e539 1536
Anna Bridge 169:a7c7b631e539 1537 /**
Anna Bridge 169:a7c7b631e539 1538 \brief Structure type to access the Memory Protection Unit (MPU).
Anna Bridge 169:a7c7b631e539 1539 */
Anna Bridge 169:a7c7b631e539 1540 typedef struct
Anna Bridge 169:a7c7b631e539 1541 {
Anna Bridge 169:a7c7b631e539 1542 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Anna Bridge 169:a7c7b631e539 1543 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Anna Bridge 169:a7c7b631e539 1544 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
Anna Bridge 169:a7c7b631e539 1545 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Anna Bridge 169:a7c7b631e539 1546 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
Anna Bridge 169:a7c7b631e539 1547 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
Anna Bridge 169:a7c7b631e539 1548 __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
Anna Bridge 169:a7c7b631e539 1549 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
Anna Bridge 169:a7c7b631e539 1550 __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
Anna Bridge 169:a7c7b631e539 1551 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
Anna Bridge 169:a7c7b631e539 1552 __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
Anna Bridge 169:a7c7b631e539 1553 uint32_t RESERVED0[1];
Anna Bridge 169:a7c7b631e539 1554 union {
Anna Bridge 169:a7c7b631e539 1555 __IOM uint32_t MAIR[2];
Anna Bridge 169:a7c7b631e539 1556 struct {
Anna Bridge 169:a7c7b631e539 1557 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
Anna Bridge 169:a7c7b631e539 1558 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
Anna Bridge 169:a7c7b631e539 1559 };
Anna Bridge 169:a7c7b631e539 1560 };
Anna Bridge 169:a7c7b631e539 1561 } MPU_Type;
Anna Bridge 169:a7c7b631e539 1562
Anna Bridge 169:a7c7b631e539 1563 #define MPU_TYPE_RALIASES 4U
Anna Bridge 169:a7c7b631e539 1564
Anna Bridge 169:a7c7b631e539 1565 /* MPU Type Register Definitions */
Anna Bridge 169:a7c7b631e539 1566 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
Anna Bridge 169:a7c7b631e539 1567 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Anna Bridge 169:a7c7b631e539 1568
Anna Bridge 169:a7c7b631e539 1569 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
Anna Bridge 169:a7c7b631e539 1570 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Anna Bridge 169:a7c7b631e539 1571
Anna Bridge 169:a7c7b631e539 1572 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
Anna Bridge 169:a7c7b631e539 1573 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Anna Bridge 169:a7c7b631e539 1574
Anna Bridge 169:a7c7b631e539 1575 /* MPU Control Register Definitions */
Anna Bridge 169:a7c7b631e539 1576 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
Anna Bridge 169:a7c7b631e539 1577 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Anna Bridge 169:a7c7b631e539 1578
Anna Bridge 169:a7c7b631e539 1579 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
Anna Bridge 169:a7c7b631e539 1580 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Anna Bridge 169:a7c7b631e539 1581
Anna Bridge 169:a7c7b631e539 1582 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
Anna Bridge 169:a7c7b631e539 1583 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Anna Bridge 169:a7c7b631e539 1584
Anna Bridge 169:a7c7b631e539 1585 /* MPU Region Number Register Definitions */
Anna Bridge 169:a7c7b631e539 1586 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
Anna Bridge 169:a7c7b631e539 1587 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Anna Bridge 169:a7c7b631e539 1588
Anna Bridge 169:a7c7b631e539 1589 /* MPU Region Base Address Register Definitions */
Anna Bridge 169:a7c7b631e539 1590 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
Anna Bridge 169:a7c7b631e539 1591 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Anna Bridge 169:a7c7b631e539 1592
Anna Bridge 169:a7c7b631e539 1593 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
Anna Bridge 169:a7c7b631e539 1594 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
Anna Bridge 169:a7c7b631e539 1595
Anna Bridge 169:a7c7b631e539 1596 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
Anna Bridge 169:a7c7b631e539 1597 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
Anna Bridge 169:a7c7b631e539 1598
Anna Bridge 169:a7c7b631e539 1599 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
Anna Bridge 169:a7c7b631e539 1600 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
Anna Bridge 169:a7c7b631e539 1601
Anna Bridge 169:a7c7b631e539 1602 /* MPU Region Limit Address Register Definitions */
Anna Bridge 169:a7c7b631e539 1603 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
Anna Bridge 169:a7c7b631e539 1604 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
Anna Bridge 169:a7c7b631e539 1605
Anna Bridge 169:a7c7b631e539 1606 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
Anna Bridge 169:a7c7b631e539 1607 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
Anna Bridge 169:a7c7b631e539 1608
Anna Bridge 169:a7c7b631e539 1609 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
Anna Bridge 169:a7c7b631e539 1610 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
Anna Bridge 169:a7c7b631e539 1611
Anna Bridge 169:a7c7b631e539 1612 /* MPU Memory Attribute Indirection Register 0 Definitions */
Anna Bridge 169:a7c7b631e539 1613 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
Anna Bridge 169:a7c7b631e539 1614 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
Anna Bridge 169:a7c7b631e539 1615
Anna Bridge 169:a7c7b631e539 1616 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
Anna Bridge 169:a7c7b631e539 1617 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
Anna Bridge 169:a7c7b631e539 1618
Anna Bridge 169:a7c7b631e539 1619 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
Anna Bridge 169:a7c7b631e539 1620 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
Anna Bridge 169:a7c7b631e539 1621
Anna Bridge 169:a7c7b631e539 1622 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
Anna Bridge 169:a7c7b631e539 1623 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
Anna Bridge 169:a7c7b631e539 1624
Anna Bridge 169:a7c7b631e539 1625 /* MPU Memory Attribute Indirection Register 1 Definitions */
Anna Bridge 169:a7c7b631e539 1626 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
Anna Bridge 169:a7c7b631e539 1627 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
Anna Bridge 169:a7c7b631e539 1628
Anna Bridge 169:a7c7b631e539 1629 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
Anna Bridge 169:a7c7b631e539 1630 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
Anna Bridge 169:a7c7b631e539 1631
Anna Bridge 169:a7c7b631e539 1632 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
Anna Bridge 169:a7c7b631e539 1633 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
Anna Bridge 169:a7c7b631e539 1634
Anna Bridge 169:a7c7b631e539 1635 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
Anna Bridge 169:a7c7b631e539 1636 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
Anna Bridge 169:a7c7b631e539 1637
Anna Bridge 169:a7c7b631e539 1638 /*@} end of group CMSIS_MPU */
Anna Bridge 169:a7c7b631e539 1639 #endif
Anna Bridge 169:a7c7b631e539 1640
Anna Bridge 169:a7c7b631e539 1641
Anna Bridge 169:a7c7b631e539 1642 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge 169:a7c7b631e539 1643 /**
Anna Bridge 169:a7c7b631e539 1644 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 1645 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
Anna Bridge 169:a7c7b631e539 1646 \brief Type definitions for the Security Attribution Unit (SAU)
Anna Bridge 169:a7c7b631e539 1647 @{
Anna Bridge 169:a7c7b631e539 1648 */
Anna Bridge 169:a7c7b631e539 1649
Anna Bridge 169:a7c7b631e539 1650 /**
Anna Bridge 169:a7c7b631e539 1651 \brief Structure type to access the Security Attribution Unit (SAU).
Anna Bridge 169:a7c7b631e539 1652 */
Anna Bridge 169:a7c7b631e539 1653 typedef struct
Anna Bridge 169:a7c7b631e539 1654 {
Anna Bridge 169:a7c7b631e539 1655 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
Anna Bridge 169:a7c7b631e539 1656 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
Anna Bridge 169:a7c7b631e539 1657 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 1658 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
Anna Bridge 169:a7c7b631e539 1659 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
Anna Bridge 169:a7c7b631e539 1660 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
Anna Bridge 169:a7c7b631e539 1661 #else
Anna Bridge 169:a7c7b631e539 1662 uint32_t RESERVED0[3];
Anna Bridge 169:a7c7b631e539 1663 #endif
Anna Bridge 169:a7c7b631e539 1664 __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
Anna Bridge 169:a7c7b631e539 1665 __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
Anna Bridge 169:a7c7b631e539 1666 } SAU_Type;
Anna Bridge 169:a7c7b631e539 1667
Anna Bridge 169:a7c7b631e539 1668 /* SAU Control Register Definitions */
Anna Bridge 169:a7c7b631e539 1669 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
Anna Bridge 169:a7c7b631e539 1670 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
Anna Bridge 169:a7c7b631e539 1671
Anna Bridge 169:a7c7b631e539 1672 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
Anna Bridge 169:a7c7b631e539 1673 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
Anna Bridge 169:a7c7b631e539 1674
Anna Bridge 169:a7c7b631e539 1675 /* SAU Type Register Definitions */
Anna Bridge 169:a7c7b631e539 1676 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
Anna Bridge 169:a7c7b631e539 1677 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
Anna Bridge 169:a7c7b631e539 1678
Anna Bridge 169:a7c7b631e539 1679 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 1680 /* SAU Region Number Register Definitions */
Anna Bridge 169:a7c7b631e539 1681 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
Anna Bridge 169:a7c7b631e539 1682 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
Anna Bridge 169:a7c7b631e539 1683
Anna Bridge 169:a7c7b631e539 1684 /* SAU Region Base Address Register Definitions */
Anna Bridge 169:a7c7b631e539 1685 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
Anna Bridge 169:a7c7b631e539 1686 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
Anna Bridge 169:a7c7b631e539 1687
Anna Bridge 169:a7c7b631e539 1688 /* SAU Region Limit Address Register Definitions */
Anna Bridge 169:a7c7b631e539 1689 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
Anna Bridge 169:a7c7b631e539 1690 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
Anna Bridge 169:a7c7b631e539 1691
Anna Bridge 169:a7c7b631e539 1692 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
Anna Bridge 169:a7c7b631e539 1693 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
Anna Bridge 169:a7c7b631e539 1694
Anna Bridge 169:a7c7b631e539 1695 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
Anna Bridge 169:a7c7b631e539 1696 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
Anna Bridge 169:a7c7b631e539 1697
Anna Bridge 169:a7c7b631e539 1698 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
Anna Bridge 169:a7c7b631e539 1699
Anna Bridge 169:a7c7b631e539 1700 /* Secure Fault Status Register Definitions */
Anna Bridge 169:a7c7b631e539 1701 #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
Anna Bridge 169:a7c7b631e539 1702 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
Anna Bridge 169:a7c7b631e539 1703
Anna Bridge 169:a7c7b631e539 1704 #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
Anna Bridge 169:a7c7b631e539 1705 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
Anna Bridge 169:a7c7b631e539 1706
Anna Bridge 169:a7c7b631e539 1707 #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
Anna Bridge 169:a7c7b631e539 1708 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
Anna Bridge 169:a7c7b631e539 1709
Anna Bridge 169:a7c7b631e539 1710 #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
Anna Bridge 169:a7c7b631e539 1711 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
Anna Bridge 169:a7c7b631e539 1712
Anna Bridge 169:a7c7b631e539 1713 #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
Anna Bridge 169:a7c7b631e539 1714 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
Anna Bridge 169:a7c7b631e539 1715
Anna Bridge 169:a7c7b631e539 1716 #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
Anna Bridge 169:a7c7b631e539 1717 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
Anna Bridge 169:a7c7b631e539 1718
Anna Bridge 169:a7c7b631e539 1719 #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
Anna Bridge 169:a7c7b631e539 1720 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
Anna Bridge 169:a7c7b631e539 1721
Anna Bridge 169:a7c7b631e539 1722 #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
Anna Bridge 169:a7c7b631e539 1723 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
Anna Bridge 169:a7c7b631e539 1724
Anna Bridge 169:a7c7b631e539 1725 /*@} end of group CMSIS_SAU */
Anna Bridge 169:a7c7b631e539 1726 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge 169:a7c7b631e539 1727
Anna Bridge 169:a7c7b631e539 1728
Anna Bridge 169:a7c7b631e539 1729 /**
Anna Bridge 169:a7c7b631e539 1730 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 1731 \defgroup CMSIS_FPU Floating Point Unit (FPU)
Anna Bridge 169:a7c7b631e539 1732 \brief Type definitions for the Floating Point Unit (FPU)
Anna Bridge 169:a7c7b631e539 1733 @{
Anna Bridge 169:a7c7b631e539 1734 */
Anna Bridge 169:a7c7b631e539 1735
Anna Bridge 169:a7c7b631e539 1736 /**
Anna Bridge 169:a7c7b631e539 1737 \brief Structure type to access the Floating Point Unit (FPU).
Anna Bridge 169:a7c7b631e539 1738 */
Anna Bridge 169:a7c7b631e539 1739 typedef struct
Anna Bridge 169:a7c7b631e539 1740 {
Anna Bridge 169:a7c7b631e539 1741 uint32_t RESERVED0[1U];
Anna Bridge 169:a7c7b631e539 1742 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
Anna Bridge 169:a7c7b631e539 1743 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
Anna Bridge 169:a7c7b631e539 1744 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
Anna Bridge 169:a7c7b631e539 1745 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
Anna Bridge 169:a7c7b631e539 1746 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
Anna Bridge 169:a7c7b631e539 1747 } FPU_Type;
Anna Bridge 169:a7c7b631e539 1748
Anna Bridge 169:a7c7b631e539 1749 /* Floating-Point Context Control Register Definitions */
Anna Bridge 169:a7c7b631e539 1750 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
Anna Bridge 169:a7c7b631e539 1751 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
Anna Bridge 169:a7c7b631e539 1752
Anna Bridge 169:a7c7b631e539 1753 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
Anna Bridge 169:a7c7b631e539 1754 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
Anna Bridge 169:a7c7b631e539 1755
Anna Bridge 169:a7c7b631e539 1756 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
Anna Bridge 169:a7c7b631e539 1757 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
Anna Bridge 169:a7c7b631e539 1758
Anna Bridge 169:a7c7b631e539 1759 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
Anna Bridge 169:a7c7b631e539 1760 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
Anna Bridge 169:a7c7b631e539 1761
Anna Bridge 169:a7c7b631e539 1762 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
Anna Bridge 169:a7c7b631e539 1763 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
Anna Bridge 169:a7c7b631e539 1764
Anna Bridge 169:a7c7b631e539 1765 #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
Anna Bridge 169:a7c7b631e539 1766 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
Anna Bridge 169:a7c7b631e539 1767
Anna Bridge 169:a7c7b631e539 1768 #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
Anna Bridge 169:a7c7b631e539 1769 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
Anna Bridge 169:a7c7b631e539 1770
Anna Bridge 169:a7c7b631e539 1771 #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
Anna Bridge 169:a7c7b631e539 1772 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
Anna Bridge 169:a7c7b631e539 1773
Anna Bridge 169:a7c7b631e539 1774 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
Anna Bridge 169:a7c7b631e539 1775 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
Anna Bridge 169:a7c7b631e539 1776
Anna Bridge 169:a7c7b631e539 1777 #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
Anna Bridge 169:a7c7b631e539 1778 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
Anna Bridge 169:a7c7b631e539 1779
Anna Bridge 169:a7c7b631e539 1780 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
Anna Bridge 169:a7c7b631e539 1781 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
Anna Bridge 169:a7c7b631e539 1782
Anna Bridge 169:a7c7b631e539 1783 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
Anna Bridge 169:a7c7b631e539 1784 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
Anna Bridge 169:a7c7b631e539 1785
Anna Bridge 169:a7c7b631e539 1786 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
Anna Bridge 169:a7c7b631e539 1787 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
Anna Bridge 169:a7c7b631e539 1788
Anna Bridge 169:a7c7b631e539 1789 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
Anna Bridge 169:a7c7b631e539 1790 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
Anna Bridge 169:a7c7b631e539 1791
Anna Bridge 169:a7c7b631e539 1792 #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
Anna Bridge 169:a7c7b631e539 1793 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
Anna Bridge 169:a7c7b631e539 1794
Anna Bridge 169:a7c7b631e539 1795 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
Anna Bridge 169:a7c7b631e539 1796 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
Anna Bridge 169:a7c7b631e539 1797
Anna Bridge 169:a7c7b631e539 1798 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
Anna Bridge 169:a7c7b631e539 1799 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
Anna Bridge 169:a7c7b631e539 1800
Anna Bridge 169:a7c7b631e539 1801 /* Floating-Point Context Address Register Definitions */
Anna Bridge 169:a7c7b631e539 1802 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
Anna Bridge 169:a7c7b631e539 1803 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
Anna Bridge 169:a7c7b631e539 1804
Anna Bridge 169:a7c7b631e539 1805 /* Floating-Point Default Status Control Register Definitions */
Anna Bridge 169:a7c7b631e539 1806 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
Anna Bridge 169:a7c7b631e539 1807 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
Anna Bridge 169:a7c7b631e539 1808
Anna Bridge 169:a7c7b631e539 1809 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
Anna Bridge 169:a7c7b631e539 1810 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
Anna Bridge 169:a7c7b631e539 1811
Anna Bridge 169:a7c7b631e539 1812 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
Anna Bridge 169:a7c7b631e539 1813 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
Anna Bridge 169:a7c7b631e539 1814
Anna Bridge 169:a7c7b631e539 1815 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
Anna Bridge 169:a7c7b631e539 1816 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
Anna Bridge 169:a7c7b631e539 1817
Anna Bridge 169:a7c7b631e539 1818 /* Media and FP Feature Register 0 Definitions */
Anna Bridge 169:a7c7b631e539 1819 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
Anna Bridge 169:a7c7b631e539 1820 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
Anna Bridge 169:a7c7b631e539 1821
Anna Bridge 169:a7c7b631e539 1822 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
Anna Bridge 169:a7c7b631e539 1823 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
Anna Bridge 169:a7c7b631e539 1824
Anna Bridge 169:a7c7b631e539 1825 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
Anna Bridge 169:a7c7b631e539 1826 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
Anna Bridge 169:a7c7b631e539 1827
Anna Bridge 169:a7c7b631e539 1828 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
Anna Bridge 169:a7c7b631e539 1829 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
Anna Bridge 169:a7c7b631e539 1830
Anna Bridge 169:a7c7b631e539 1831 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
Anna Bridge 169:a7c7b631e539 1832 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
Anna Bridge 169:a7c7b631e539 1833
Anna Bridge 169:a7c7b631e539 1834 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
Anna Bridge 169:a7c7b631e539 1835 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
Anna Bridge 169:a7c7b631e539 1836
Anna Bridge 169:a7c7b631e539 1837 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
Anna Bridge 169:a7c7b631e539 1838 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
Anna Bridge 169:a7c7b631e539 1839
Anna Bridge 169:a7c7b631e539 1840 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
Anna Bridge 169:a7c7b631e539 1841 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
Anna Bridge 169:a7c7b631e539 1842
Anna Bridge 169:a7c7b631e539 1843 /* Media and FP Feature Register 1 Definitions */
Anna Bridge 169:a7c7b631e539 1844 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
Anna Bridge 169:a7c7b631e539 1845 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
Anna Bridge 169:a7c7b631e539 1846
Anna Bridge 169:a7c7b631e539 1847 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
Anna Bridge 169:a7c7b631e539 1848 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
Anna Bridge 169:a7c7b631e539 1849
Anna Bridge 169:a7c7b631e539 1850 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
Anna Bridge 169:a7c7b631e539 1851 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
Anna Bridge 169:a7c7b631e539 1852
Anna Bridge 169:a7c7b631e539 1853 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
Anna Bridge 169:a7c7b631e539 1854 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
Anna Bridge 169:a7c7b631e539 1855
Anna Bridge 169:a7c7b631e539 1856 /*@} end of group CMSIS_FPU */
Anna Bridge 169:a7c7b631e539 1857
Anna Bridge 169:a7c7b631e539 1858
Anna Bridge 169:a7c7b631e539 1859 /**
Anna Bridge 169:a7c7b631e539 1860 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 1861 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Anna Bridge 169:a7c7b631e539 1862 \brief Type definitions for the Core Debug Registers
Anna Bridge 169:a7c7b631e539 1863 @{
Anna Bridge 169:a7c7b631e539 1864 */
Anna Bridge 169:a7c7b631e539 1865
Anna Bridge 169:a7c7b631e539 1866 /**
Anna Bridge 169:a7c7b631e539 1867 \brief Structure type to access the Core Debug Register (CoreDebug).
Anna Bridge 169:a7c7b631e539 1868 */
Anna Bridge 169:a7c7b631e539 1869 typedef struct
Anna Bridge 169:a7c7b631e539 1870 {
Anna Bridge 169:a7c7b631e539 1871 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
Anna Bridge 169:a7c7b631e539 1872 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
Anna Bridge 169:a7c7b631e539 1873 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
Anna Bridge 169:a7c7b631e539 1874 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
Anna Bridge 169:a7c7b631e539 1875 uint32_t RESERVED4[1U];
Anna Bridge 169:a7c7b631e539 1876 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
Anna Bridge 169:a7c7b631e539 1877 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
Anna Bridge 169:a7c7b631e539 1878 } CoreDebug_Type;
Anna Bridge 169:a7c7b631e539 1879
Anna Bridge 169:a7c7b631e539 1880 /* Debug Halting Control and Status Register Definitions */
Anna Bridge 169:a7c7b631e539 1881 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
Anna Bridge 169:a7c7b631e539 1882 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
Anna Bridge 169:a7c7b631e539 1883
Anna Bridge 169:a7c7b631e539 1884 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
Anna Bridge 169:a7c7b631e539 1885 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
Anna Bridge 169:a7c7b631e539 1886
Anna Bridge 169:a7c7b631e539 1887 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
Anna Bridge 169:a7c7b631e539 1888 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
Anna Bridge 169:a7c7b631e539 1889
Anna Bridge 169:a7c7b631e539 1890 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
Anna Bridge 169:a7c7b631e539 1891 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
Anna Bridge 169:a7c7b631e539 1892
Anna Bridge 169:a7c7b631e539 1893 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
Anna Bridge 169:a7c7b631e539 1894 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
Anna Bridge 169:a7c7b631e539 1895
Anna Bridge 169:a7c7b631e539 1896 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
Anna Bridge 169:a7c7b631e539 1897 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
Anna Bridge 169:a7c7b631e539 1898
Anna Bridge 169:a7c7b631e539 1899 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
Anna Bridge 169:a7c7b631e539 1900 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
Anna Bridge 169:a7c7b631e539 1901
Anna Bridge 169:a7c7b631e539 1902 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
Anna Bridge 169:a7c7b631e539 1903 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
Anna Bridge 169:a7c7b631e539 1904
Anna Bridge 169:a7c7b631e539 1905 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
Anna Bridge 169:a7c7b631e539 1906 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
Anna Bridge 169:a7c7b631e539 1907
Anna Bridge 169:a7c7b631e539 1908 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
Anna Bridge 169:a7c7b631e539 1909 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
Anna Bridge 169:a7c7b631e539 1910
Anna Bridge 169:a7c7b631e539 1911 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
Anna Bridge 169:a7c7b631e539 1912 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
Anna Bridge 169:a7c7b631e539 1913
Anna Bridge 169:a7c7b631e539 1914 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
Anna Bridge 169:a7c7b631e539 1915 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
Anna Bridge 169:a7c7b631e539 1916
Anna Bridge 169:a7c7b631e539 1917 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Anna Bridge 169:a7c7b631e539 1918 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
Anna Bridge 169:a7c7b631e539 1919
Anna Bridge 169:a7c7b631e539 1920 /* Debug Core Register Selector Register Definitions */
Anna Bridge 169:a7c7b631e539 1921 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
Anna Bridge 169:a7c7b631e539 1922 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
Anna Bridge 169:a7c7b631e539 1923
Anna Bridge 169:a7c7b631e539 1924 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
Anna Bridge 169:a7c7b631e539 1925 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
Anna Bridge 169:a7c7b631e539 1926
Anna Bridge 169:a7c7b631e539 1927 /* Debug Exception and Monitor Control Register Definitions */
Anna Bridge 169:a7c7b631e539 1928 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
Anna Bridge 169:a7c7b631e539 1929 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
Anna Bridge 169:a7c7b631e539 1930
Anna Bridge 169:a7c7b631e539 1931 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
Anna Bridge 169:a7c7b631e539 1932 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
Anna Bridge 169:a7c7b631e539 1933
Anna Bridge 169:a7c7b631e539 1934 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
Anna Bridge 169:a7c7b631e539 1935 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
Anna Bridge 169:a7c7b631e539 1936
Anna Bridge 169:a7c7b631e539 1937 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
Anna Bridge 169:a7c7b631e539 1938 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
Anna Bridge 169:a7c7b631e539 1939
Anna Bridge 169:a7c7b631e539 1940 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
Anna Bridge 169:a7c7b631e539 1941 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
Anna Bridge 169:a7c7b631e539 1942
Anna Bridge 169:a7c7b631e539 1943 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
Anna Bridge 169:a7c7b631e539 1944 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
Anna Bridge 169:a7c7b631e539 1945
Anna Bridge 169:a7c7b631e539 1946 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
Anna Bridge 169:a7c7b631e539 1947 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
Anna Bridge 169:a7c7b631e539 1948
Anna Bridge 169:a7c7b631e539 1949 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
Anna Bridge 169:a7c7b631e539 1950 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
Anna Bridge 169:a7c7b631e539 1951
Anna Bridge 169:a7c7b631e539 1952 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
Anna Bridge 169:a7c7b631e539 1953 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
Anna Bridge 169:a7c7b631e539 1954
Anna Bridge 169:a7c7b631e539 1955 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
Anna Bridge 169:a7c7b631e539 1956 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
Anna Bridge 169:a7c7b631e539 1957
Anna Bridge 169:a7c7b631e539 1958 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
Anna Bridge 169:a7c7b631e539 1959 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
Anna Bridge 169:a7c7b631e539 1960
Anna Bridge 169:a7c7b631e539 1961 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
Anna Bridge 169:a7c7b631e539 1962 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
Anna Bridge 169:a7c7b631e539 1963
Anna Bridge 169:a7c7b631e539 1964 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
Anna Bridge 169:a7c7b631e539 1965 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
Anna Bridge 169:a7c7b631e539 1966
Anna Bridge 169:a7c7b631e539 1967 /* Debug Authentication Control Register Definitions */
Anna Bridge 169:a7c7b631e539 1968 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
Anna Bridge 169:a7c7b631e539 1969 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
Anna Bridge 169:a7c7b631e539 1970
Anna Bridge 169:a7c7b631e539 1971 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
Anna Bridge 169:a7c7b631e539 1972 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
Anna Bridge 169:a7c7b631e539 1973
Anna Bridge 169:a7c7b631e539 1974 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
Anna Bridge 169:a7c7b631e539 1975 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
Anna Bridge 169:a7c7b631e539 1976
Anna Bridge 169:a7c7b631e539 1977 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
Anna Bridge 169:a7c7b631e539 1978 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
Anna Bridge 169:a7c7b631e539 1979
Anna Bridge 169:a7c7b631e539 1980 /* Debug Security Control and Status Register Definitions */
Anna Bridge 169:a7c7b631e539 1981 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
Anna Bridge 169:a7c7b631e539 1982 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
Anna Bridge 169:a7c7b631e539 1983
Anna Bridge 169:a7c7b631e539 1984 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
Anna Bridge 169:a7c7b631e539 1985 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
Anna Bridge 169:a7c7b631e539 1986
Anna Bridge 169:a7c7b631e539 1987 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
Anna Bridge 169:a7c7b631e539 1988 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
Anna Bridge 169:a7c7b631e539 1989
Anna Bridge 169:a7c7b631e539 1990 /*@} end of group CMSIS_CoreDebug */
Anna Bridge 169:a7c7b631e539 1991
Anna Bridge 169:a7c7b631e539 1992
Anna Bridge 169:a7c7b631e539 1993 /**
Anna Bridge 169:a7c7b631e539 1994 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 1995 \defgroup CMSIS_core_bitfield Core register bit field macros
Anna Bridge 169:a7c7b631e539 1996 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
Anna Bridge 169:a7c7b631e539 1997 @{
Anna Bridge 169:a7c7b631e539 1998 */
Anna Bridge 169:a7c7b631e539 1999
Anna Bridge 169:a7c7b631e539 2000 /**
Anna Bridge 169:a7c7b631e539 2001 \brief Mask and shift a bit field value for use in a register bit range.
Anna Bridge 169:a7c7b631e539 2002 \param[in] field Name of the register bit field.
Anna Bridge 169:a7c7b631e539 2003 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
Anna Bridge 169:a7c7b631e539 2004 \return Masked and shifted value.
Anna Bridge 169:a7c7b631e539 2005 */
Anna Bridge 169:a7c7b631e539 2006 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Anna Bridge 169:a7c7b631e539 2007
Anna Bridge 169:a7c7b631e539 2008 /**
Anna Bridge 169:a7c7b631e539 2009 \brief Mask and shift a register value to extract a bit filed value.
Anna Bridge 169:a7c7b631e539 2010 \param[in] field Name of the register bit field.
Anna Bridge 169:a7c7b631e539 2011 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
Anna Bridge 169:a7c7b631e539 2012 \return Masked and shifted bit field value.
Anna Bridge 169:a7c7b631e539 2013 */
Anna Bridge 169:a7c7b631e539 2014 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
Anna Bridge 169:a7c7b631e539 2015
Anna Bridge 169:a7c7b631e539 2016 /*@} end of group CMSIS_core_bitfield */
Anna Bridge 169:a7c7b631e539 2017
Anna Bridge 169:a7c7b631e539 2018
Anna Bridge 169:a7c7b631e539 2019 /**
Anna Bridge 169:a7c7b631e539 2020 \ingroup CMSIS_core_register
Anna Bridge 169:a7c7b631e539 2021 \defgroup CMSIS_core_base Core Definitions
Anna Bridge 169:a7c7b631e539 2022 \brief Definitions for base addresses, unions, and structures.
Anna Bridge 169:a7c7b631e539 2023 @{
Anna Bridge 169:a7c7b631e539 2024 */
Anna Bridge 169:a7c7b631e539 2025
Anna Bridge 169:a7c7b631e539 2026 /* Memory mapping of Core Hardware */
Anna Bridge 169:a7c7b631e539 2027 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Anna Bridge 169:a7c7b631e539 2028 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
Anna Bridge 169:a7c7b631e539 2029 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
Anna Bridge 169:a7c7b631e539 2030 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
Anna Bridge 169:a7c7b631e539 2031 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
Anna Bridge 169:a7c7b631e539 2032 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Anna Bridge 169:a7c7b631e539 2033 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Anna Bridge 169:a7c7b631e539 2034 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Anna Bridge 169:a7c7b631e539 2035
Anna Bridge 169:a7c7b631e539 2036 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
Anna Bridge 169:a7c7b631e539 2037 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Anna Bridge 169:a7c7b631e539 2038 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Anna Bridge 169:a7c7b631e539 2039 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Anna Bridge 169:a7c7b631e539 2040 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
Anna Bridge 169:a7c7b631e539 2041 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
Anna Bridge 169:a7c7b631e539 2042 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
Anna Bridge 169:a7c7b631e539 2043 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
Anna Bridge 169:a7c7b631e539 2044
Anna Bridge 169:a7c7b631e539 2045 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 2046 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Anna Bridge 169:a7c7b631e539 2047 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Anna Bridge 169:a7c7b631e539 2048 #endif
Anna Bridge 169:a7c7b631e539 2049
Anna Bridge 169:a7c7b631e539 2050 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge 169:a7c7b631e539 2051 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
Anna Bridge 169:a7c7b631e539 2052 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
Anna Bridge 169:a7c7b631e539 2053 #endif
Anna Bridge 169:a7c7b631e539 2054
Anna Bridge 169:a7c7b631e539 2055 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
Anna Bridge 169:a7c7b631e539 2056 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
Anna Bridge 169:a7c7b631e539 2057
Anna Bridge 169:a7c7b631e539 2058 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge 169:a7c7b631e539 2059 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
Anna Bridge 169:a7c7b631e539 2060 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
Anna Bridge 169:a7c7b631e539 2061 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
Anna Bridge 169:a7c7b631e539 2062 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
Anna Bridge 169:a7c7b631e539 2063 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
Anna Bridge 169:a7c7b631e539 2064
Anna Bridge 169:a7c7b631e539 2065 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
Anna Bridge 169:a7c7b631e539 2066 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
Anna Bridge 169:a7c7b631e539 2067 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
Anna Bridge 169:a7c7b631e539 2068 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
Anna Bridge 169:a7c7b631e539 2069 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
Anna Bridge 169:a7c7b631e539 2070
Anna Bridge 169:a7c7b631e539 2071 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 2072 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
Anna Bridge 169:a7c7b631e539 2073 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
Anna Bridge 169:a7c7b631e539 2074 #endif
Anna Bridge 169:a7c7b631e539 2075
Anna Bridge 169:a7c7b631e539 2076 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
Anna Bridge 169:a7c7b631e539 2077 #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
Anna Bridge 169:a7c7b631e539 2078
Anna Bridge 169:a7c7b631e539 2079 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge 169:a7c7b631e539 2080 /*@} */
Anna Bridge 169:a7c7b631e539 2081
Anna Bridge 169:a7c7b631e539 2082
Anna Bridge 169:a7c7b631e539 2083
Anna Bridge 169:a7c7b631e539 2084 /*******************************************************************************
Anna Bridge 169:a7c7b631e539 2085 * Hardware Abstraction Layer
Anna Bridge 169:a7c7b631e539 2086 Core Function Interface contains:
Anna Bridge 169:a7c7b631e539 2087 - Core NVIC Functions
Anna Bridge 169:a7c7b631e539 2088 - Core SysTick Functions
Anna Bridge 169:a7c7b631e539 2089 - Core Debug Functions
Anna Bridge 169:a7c7b631e539 2090 - Core Register Access Functions
Anna Bridge 169:a7c7b631e539 2091 ******************************************************************************/
Anna Bridge 169:a7c7b631e539 2092 /**
Anna Bridge 169:a7c7b631e539 2093 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Anna Bridge 169:a7c7b631e539 2094 */
Anna Bridge 169:a7c7b631e539 2095
Anna Bridge 169:a7c7b631e539 2096
Anna Bridge 169:a7c7b631e539 2097
Anna Bridge 169:a7c7b631e539 2098 /* ########################## NVIC functions #################################### */
Anna Bridge 169:a7c7b631e539 2099 /**
Anna Bridge 169:a7c7b631e539 2100 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 169:a7c7b631e539 2101 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Anna Bridge 169:a7c7b631e539 2102 \brief Functions that manage interrupts and exceptions via the NVIC.
Anna Bridge 169:a7c7b631e539 2103 @{
Anna Bridge 169:a7c7b631e539 2104 */
Anna Bridge 169:a7c7b631e539 2105
Anna Bridge 169:a7c7b631e539 2106 #ifdef CMSIS_NVIC_VIRTUAL
Anna Bridge 169:a7c7b631e539 2107 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge 169:a7c7b631e539 2108 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Anna Bridge 169:a7c7b631e539 2109 #endif
Anna Bridge 169:a7c7b631e539 2110 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge 169:a7c7b631e539 2111 #else
Anna Bridge 169:a7c7b631e539 2112 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
Anna Bridge 169:a7c7b631e539 2113 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
Anna Bridge 169:a7c7b631e539 2114 #define NVIC_EnableIRQ __NVIC_EnableIRQ
Anna Bridge 169:a7c7b631e539 2115 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
Anna Bridge 169:a7c7b631e539 2116 #define NVIC_DisableIRQ __NVIC_DisableIRQ
Anna Bridge 169:a7c7b631e539 2117 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Anna Bridge 169:a7c7b631e539 2118 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Anna Bridge 169:a7c7b631e539 2119 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Anna Bridge 169:a7c7b631e539 2120 #define NVIC_GetActive __NVIC_GetActive
Anna Bridge 169:a7c7b631e539 2121 #define NVIC_SetPriority __NVIC_SetPriority
Anna Bridge 169:a7c7b631e539 2122 #define NVIC_GetPriority __NVIC_GetPriority
Anna Bridge 169:a7c7b631e539 2123 #define NVIC_SystemReset __NVIC_SystemReset
Anna Bridge 169:a7c7b631e539 2124 #endif /* CMSIS_NVIC_VIRTUAL */
Anna Bridge 169:a7c7b631e539 2125
Anna Bridge 169:a7c7b631e539 2126 #ifdef CMSIS_VECTAB_VIRTUAL
Anna Bridge 169:a7c7b631e539 2127 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge 169:a7c7b631e539 2128 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Anna Bridge 169:a7c7b631e539 2129 #endif
Anna Bridge 169:a7c7b631e539 2130 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge 169:a7c7b631e539 2131 #else
Anna Bridge 169:a7c7b631e539 2132 #define NVIC_SetVector __NVIC_SetVector
Anna Bridge 169:a7c7b631e539 2133 #define NVIC_GetVector __NVIC_GetVector
Anna Bridge 169:a7c7b631e539 2134 #endif /* (CMSIS_VECTAB_VIRTUAL) */
Anna Bridge 169:a7c7b631e539 2135
Anna Bridge 169:a7c7b631e539 2136 #define NVIC_USER_IRQ_OFFSET 16
Anna Bridge 169:a7c7b631e539 2137
Anna Bridge 169:a7c7b631e539 2138
Anna Bridge 169:a7c7b631e539 2139
Anna Bridge 169:a7c7b631e539 2140 /**
Anna Bridge 169:a7c7b631e539 2141 \brief Set Priority Grouping
Anna Bridge 169:a7c7b631e539 2142 \details Sets the priority grouping field using the required unlock sequence.
Anna Bridge 169:a7c7b631e539 2143 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Anna Bridge 169:a7c7b631e539 2144 Only values from 0..7 are used.
Anna Bridge 169:a7c7b631e539 2145 In case of a conflict between priority grouping and available
Anna Bridge 169:a7c7b631e539 2146 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Anna Bridge 169:a7c7b631e539 2147 \param [in] PriorityGroup Priority grouping field.
Anna Bridge 169:a7c7b631e539 2148 */
Anna Bridge 169:a7c7b631e539 2149 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Anna Bridge 169:a7c7b631e539 2150 {
Anna Bridge 169:a7c7b631e539 2151 uint32_t reg_value;
Anna Bridge 169:a7c7b631e539 2152 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge 169:a7c7b631e539 2153
Anna Bridge 169:a7c7b631e539 2154 reg_value = SCB->AIRCR; /* read old register configuration */
Anna Bridge 169:a7c7b631e539 2155 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Anna Bridge 169:a7c7b631e539 2156 reg_value = (reg_value |
Anna Bridge 169:a7c7b631e539 2157 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Anna Bridge 169:a7c7b631e539 2158 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
Anna Bridge 169:a7c7b631e539 2159 SCB->AIRCR = reg_value;
Anna Bridge 169:a7c7b631e539 2160 }
Anna Bridge 169:a7c7b631e539 2161
Anna Bridge 169:a7c7b631e539 2162
Anna Bridge 169:a7c7b631e539 2163 /**
Anna Bridge 169:a7c7b631e539 2164 \brief Get Priority Grouping
Anna Bridge 169:a7c7b631e539 2165 \details Reads the priority grouping field from the NVIC Interrupt Controller.
Anna Bridge 169:a7c7b631e539 2166 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Anna Bridge 169:a7c7b631e539 2167 */
Anna Bridge 169:a7c7b631e539 2168 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Anna Bridge 169:a7c7b631e539 2169 {
Anna Bridge 169:a7c7b631e539 2170 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Anna Bridge 169:a7c7b631e539 2171 }
Anna Bridge 169:a7c7b631e539 2172
Anna Bridge 169:a7c7b631e539 2173
Anna Bridge 169:a7c7b631e539 2174 /**
Anna Bridge 169:a7c7b631e539 2175 \brief Enable Interrupt
Anna Bridge 169:a7c7b631e539 2176 \details Enables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge 169:a7c7b631e539 2177 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 2178 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 2179 */
Anna Bridge 169:a7c7b631e539 2180 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 2181 {
Anna Bridge 169:a7c7b631e539 2182 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 2183 {
Anna Bridge 169:a7c7b631e539 2184 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 169:a7c7b631e539 2185 }
Anna Bridge 169:a7c7b631e539 2186 }
Anna Bridge 169:a7c7b631e539 2187
Anna Bridge 169:a7c7b631e539 2188
Anna Bridge 169:a7c7b631e539 2189 /**
Anna Bridge 169:a7c7b631e539 2190 \brief Get Interrupt Enable status
Anna Bridge 169:a7c7b631e539 2191 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
Anna Bridge 169:a7c7b631e539 2192 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 2193 \return 0 Interrupt is not enabled.
Anna Bridge 169:a7c7b631e539 2194 \return 1 Interrupt is enabled.
Anna Bridge 169:a7c7b631e539 2195 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 2196 */
Anna Bridge 169:a7c7b631e539 2197 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 2198 {
Anna Bridge 169:a7c7b631e539 2199 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 2200 {
Anna Bridge 169:a7c7b631e539 2201 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 169:a7c7b631e539 2202 }
Anna Bridge 169:a7c7b631e539 2203 else
Anna Bridge 169:a7c7b631e539 2204 {
Anna Bridge 169:a7c7b631e539 2205 return(0U);
Anna Bridge 169:a7c7b631e539 2206 }
Anna Bridge 169:a7c7b631e539 2207 }
Anna Bridge 169:a7c7b631e539 2208
Anna Bridge 169:a7c7b631e539 2209
Anna Bridge 169:a7c7b631e539 2210 /**
Anna Bridge 169:a7c7b631e539 2211 \brief Disable Interrupt
Anna Bridge 169:a7c7b631e539 2212 \details Disables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge 169:a7c7b631e539 2213 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 2214 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 2215 */
Anna Bridge 169:a7c7b631e539 2216 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 2217 {
Anna Bridge 169:a7c7b631e539 2218 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 2219 {
Anna Bridge 169:a7c7b631e539 2220 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 169:a7c7b631e539 2221 __DSB();
Anna Bridge 169:a7c7b631e539 2222 __ISB();
Anna Bridge 169:a7c7b631e539 2223 }
Anna Bridge 169:a7c7b631e539 2224 }
Anna Bridge 169:a7c7b631e539 2225
Anna Bridge 169:a7c7b631e539 2226
Anna Bridge 169:a7c7b631e539 2227 /**
Anna Bridge 169:a7c7b631e539 2228 \brief Get Pending Interrupt
Anna Bridge 169:a7c7b631e539 2229 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
Anna Bridge 169:a7c7b631e539 2230 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 2231 \return 0 Interrupt status is not pending.
Anna Bridge 169:a7c7b631e539 2232 \return 1 Interrupt status is pending.
Anna Bridge 169:a7c7b631e539 2233 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 2234 */
Anna Bridge 169:a7c7b631e539 2235 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 2236 {
Anna Bridge 169:a7c7b631e539 2237 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 2238 {
Anna Bridge 169:a7c7b631e539 2239 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 169:a7c7b631e539 2240 }
Anna Bridge 169:a7c7b631e539 2241 else
Anna Bridge 169:a7c7b631e539 2242 {
Anna Bridge 169:a7c7b631e539 2243 return(0U);
Anna Bridge 169:a7c7b631e539 2244 }
Anna Bridge 169:a7c7b631e539 2245 }
Anna Bridge 169:a7c7b631e539 2246
Anna Bridge 169:a7c7b631e539 2247
Anna Bridge 169:a7c7b631e539 2248 /**
Anna Bridge 169:a7c7b631e539 2249 \brief Set Pending Interrupt
Anna Bridge 169:a7c7b631e539 2250 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge 169:a7c7b631e539 2251 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 2252 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 2253 */
Anna Bridge 169:a7c7b631e539 2254 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 2255 {
Anna Bridge 169:a7c7b631e539 2256 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 2257 {
Anna Bridge 169:a7c7b631e539 2258 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 169:a7c7b631e539 2259 }
Anna Bridge 169:a7c7b631e539 2260 }
Anna Bridge 169:a7c7b631e539 2261
Anna Bridge 169:a7c7b631e539 2262
Anna Bridge 169:a7c7b631e539 2263 /**
Anna Bridge 169:a7c7b631e539 2264 \brief Clear Pending Interrupt
Anna Bridge 169:a7c7b631e539 2265 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge 169:a7c7b631e539 2266 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 2267 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 2268 */
Anna Bridge 169:a7c7b631e539 2269 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 2270 {
Anna Bridge 169:a7c7b631e539 2271 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 2272 {
Anna Bridge 169:a7c7b631e539 2273 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 169:a7c7b631e539 2274 }
Anna Bridge 169:a7c7b631e539 2275 }
Anna Bridge 169:a7c7b631e539 2276
Anna Bridge 169:a7c7b631e539 2277
Anna Bridge 169:a7c7b631e539 2278 /**
Anna Bridge 169:a7c7b631e539 2279 \brief Get Active Interrupt
Anna Bridge 169:a7c7b631e539 2280 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
Anna Bridge 169:a7c7b631e539 2281 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 2282 \return 0 Interrupt status is not active.
Anna Bridge 169:a7c7b631e539 2283 \return 1 Interrupt status is active.
Anna Bridge 169:a7c7b631e539 2284 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 2285 */
Anna Bridge 169:a7c7b631e539 2286 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 2287 {
Anna Bridge 169:a7c7b631e539 2288 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 2289 {
Anna Bridge 169:a7c7b631e539 2290 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 169:a7c7b631e539 2291 }
Anna Bridge 169:a7c7b631e539 2292 else
Anna Bridge 169:a7c7b631e539 2293 {
Anna Bridge 169:a7c7b631e539 2294 return(0U);
Anna Bridge 169:a7c7b631e539 2295 }
Anna Bridge 169:a7c7b631e539 2296 }
Anna Bridge 169:a7c7b631e539 2297
Anna Bridge 169:a7c7b631e539 2298
Anna Bridge 169:a7c7b631e539 2299 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge 169:a7c7b631e539 2300 /**
Anna Bridge 169:a7c7b631e539 2301 \brief Get Interrupt Target State
Anna Bridge 169:a7c7b631e539 2302 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
Anna Bridge 169:a7c7b631e539 2303 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 2304 \return 0 if interrupt is assigned to Secure
Anna Bridge 169:a7c7b631e539 2305 \return 1 if interrupt is assigned to Non Secure
Anna Bridge 169:a7c7b631e539 2306 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 2307 */
Anna Bridge 169:a7c7b631e539 2308 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 2309 {
Anna Bridge 169:a7c7b631e539 2310 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 2311 {
Anna Bridge 169:a7c7b631e539 2312 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 169:a7c7b631e539 2313 }
Anna Bridge 169:a7c7b631e539 2314 else
Anna Bridge 169:a7c7b631e539 2315 {
Anna Bridge 169:a7c7b631e539 2316 return(0U);
Anna Bridge 169:a7c7b631e539 2317 }
Anna Bridge 169:a7c7b631e539 2318 }
Anna Bridge 169:a7c7b631e539 2319
Anna Bridge 169:a7c7b631e539 2320
Anna Bridge 169:a7c7b631e539 2321 /**
Anna Bridge 169:a7c7b631e539 2322 \brief Set Interrupt Target State
Anna Bridge 169:a7c7b631e539 2323 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
Anna Bridge 169:a7c7b631e539 2324 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 2325 \return 0 if interrupt is assigned to Secure
Anna Bridge 169:a7c7b631e539 2326 1 if interrupt is assigned to Non Secure
Anna Bridge 169:a7c7b631e539 2327 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 2328 */
Anna Bridge 169:a7c7b631e539 2329 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 2330 {
Anna Bridge 169:a7c7b631e539 2331 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 2332 {
Anna Bridge 169:a7c7b631e539 2333 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
Anna Bridge 169:a7c7b631e539 2334 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 169:a7c7b631e539 2335 }
Anna Bridge 169:a7c7b631e539 2336 else
Anna Bridge 169:a7c7b631e539 2337 {
Anna Bridge 169:a7c7b631e539 2338 return(0U);
Anna Bridge 169:a7c7b631e539 2339 }
Anna Bridge 169:a7c7b631e539 2340 }
Anna Bridge 169:a7c7b631e539 2341
Anna Bridge 169:a7c7b631e539 2342
Anna Bridge 169:a7c7b631e539 2343 /**
Anna Bridge 169:a7c7b631e539 2344 \brief Clear Interrupt Target State
Anna Bridge 169:a7c7b631e539 2345 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
Anna Bridge 169:a7c7b631e539 2346 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 2347 \return 0 if interrupt is assigned to Secure
Anna Bridge 169:a7c7b631e539 2348 1 if interrupt is assigned to Non Secure
Anna Bridge 169:a7c7b631e539 2349 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 2350 */
Anna Bridge 169:a7c7b631e539 2351 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 2352 {
Anna Bridge 169:a7c7b631e539 2353 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 2354 {
Anna Bridge 169:a7c7b631e539 2355 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
Anna Bridge 169:a7c7b631e539 2356 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 169:a7c7b631e539 2357 }
Anna Bridge 169:a7c7b631e539 2358 else
Anna Bridge 169:a7c7b631e539 2359 {
Anna Bridge 169:a7c7b631e539 2360 return(0U);
Anna Bridge 169:a7c7b631e539 2361 }
Anna Bridge 169:a7c7b631e539 2362 }
Anna Bridge 169:a7c7b631e539 2363 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge 169:a7c7b631e539 2364
Anna Bridge 169:a7c7b631e539 2365
Anna Bridge 169:a7c7b631e539 2366 /**
Anna Bridge 169:a7c7b631e539 2367 \brief Set Interrupt Priority
Anna Bridge 169:a7c7b631e539 2368 \details Sets the priority of a device specific interrupt or a processor exception.
Anna Bridge 169:a7c7b631e539 2369 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 169:a7c7b631e539 2370 or negative to specify a processor exception.
Anna Bridge 169:a7c7b631e539 2371 \param [in] IRQn Interrupt number.
Anna Bridge 169:a7c7b631e539 2372 \param [in] priority Priority to set.
Anna Bridge 169:a7c7b631e539 2373 \note The priority cannot be set for every processor exception.
Anna Bridge 169:a7c7b631e539 2374 */
Anna Bridge 169:a7c7b631e539 2375 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Anna Bridge 169:a7c7b631e539 2376 {
Anna Bridge 169:a7c7b631e539 2377 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 2378 {
Anna Bridge 169:a7c7b631e539 2379 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Anna Bridge 169:a7c7b631e539 2380 }
Anna Bridge 169:a7c7b631e539 2381 else
Anna Bridge 169:a7c7b631e539 2382 {
Anna Bridge 169:a7c7b631e539 2383 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Anna Bridge 169:a7c7b631e539 2384 }
Anna Bridge 169:a7c7b631e539 2385 }
Anna Bridge 169:a7c7b631e539 2386
Anna Bridge 169:a7c7b631e539 2387
Anna Bridge 169:a7c7b631e539 2388 /**
Anna Bridge 169:a7c7b631e539 2389 \brief Get Interrupt Priority
Anna Bridge 169:a7c7b631e539 2390 \details Reads the priority of a device specific interrupt or a processor exception.
Anna Bridge 169:a7c7b631e539 2391 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 169:a7c7b631e539 2392 or negative to specify a processor exception.
Anna Bridge 169:a7c7b631e539 2393 \param [in] IRQn Interrupt number.
Anna Bridge 169:a7c7b631e539 2394 \return Interrupt Priority.
Anna Bridge 169:a7c7b631e539 2395 Value is aligned automatically to the implemented priority bits of the microcontroller.
Anna Bridge 169:a7c7b631e539 2396 */
Anna Bridge 169:a7c7b631e539 2397 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 2398 {
Anna Bridge 169:a7c7b631e539 2399
Anna Bridge 169:a7c7b631e539 2400 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 2401 {
Anna Bridge 169:a7c7b631e539 2402 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 169:a7c7b631e539 2403 }
Anna Bridge 169:a7c7b631e539 2404 else
Anna Bridge 169:a7c7b631e539 2405 {
Anna Bridge 169:a7c7b631e539 2406 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 169:a7c7b631e539 2407 }
Anna Bridge 169:a7c7b631e539 2408 }
Anna Bridge 169:a7c7b631e539 2409
Anna Bridge 169:a7c7b631e539 2410
Anna Bridge 169:a7c7b631e539 2411 /**
Anna Bridge 169:a7c7b631e539 2412 \brief Encode Priority
Anna Bridge 169:a7c7b631e539 2413 \details Encodes the priority for an interrupt with the given priority group,
Anna Bridge 169:a7c7b631e539 2414 preemptive priority value, and subpriority value.
Anna Bridge 169:a7c7b631e539 2415 In case of a conflict between priority grouping and available
Anna Bridge 169:a7c7b631e539 2416 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Anna Bridge 169:a7c7b631e539 2417 \param [in] PriorityGroup Used priority group.
Anna Bridge 169:a7c7b631e539 2418 \param [in] PreemptPriority Preemptive priority value (starting from 0).
Anna Bridge 169:a7c7b631e539 2419 \param [in] SubPriority Subpriority value (starting from 0).
Anna Bridge 169:a7c7b631e539 2420 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Anna Bridge 169:a7c7b631e539 2421 */
Anna Bridge 169:a7c7b631e539 2422 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Anna Bridge 169:a7c7b631e539 2423 {
Anna Bridge 169:a7c7b631e539 2424 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge 169:a7c7b631e539 2425 uint32_t PreemptPriorityBits;
Anna Bridge 169:a7c7b631e539 2426 uint32_t SubPriorityBits;
Anna Bridge 169:a7c7b631e539 2427
Anna Bridge 169:a7c7b631e539 2428 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Anna Bridge 169:a7c7b631e539 2429 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Anna Bridge 169:a7c7b631e539 2430
Anna Bridge 169:a7c7b631e539 2431 return (
Anna Bridge 169:a7c7b631e539 2432 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
Anna Bridge 169:a7c7b631e539 2433 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Anna Bridge 169:a7c7b631e539 2434 );
Anna Bridge 169:a7c7b631e539 2435 }
Anna Bridge 169:a7c7b631e539 2436
Anna Bridge 169:a7c7b631e539 2437
Anna Bridge 169:a7c7b631e539 2438 /**
Anna Bridge 169:a7c7b631e539 2439 \brief Decode Priority
Anna Bridge 169:a7c7b631e539 2440 \details Decodes an interrupt priority value with a given priority group to
Anna Bridge 169:a7c7b631e539 2441 preemptive priority value and subpriority value.
Anna Bridge 169:a7c7b631e539 2442 In case of a conflict between priority grouping and available
Anna Bridge 169:a7c7b631e539 2443 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Anna Bridge 169:a7c7b631e539 2444 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Anna Bridge 169:a7c7b631e539 2445 \param [in] PriorityGroup Used priority group.
Anna Bridge 169:a7c7b631e539 2446 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
Anna Bridge 169:a7c7b631e539 2447 \param [out] pSubPriority Subpriority value (starting from 0).
Anna Bridge 169:a7c7b631e539 2448 */
Anna Bridge 169:a7c7b631e539 2449 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
Anna Bridge 169:a7c7b631e539 2450 {
Anna Bridge 169:a7c7b631e539 2451 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge 169:a7c7b631e539 2452 uint32_t PreemptPriorityBits;
Anna Bridge 169:a7c7b631e539 2453 uint32_t SubPriorityBits;
Anna Bridge 169:a7c7b631e539 2454
Anna Bridge 169:a7c7b631e539 2455 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Anna Bridge 169:a7c7b631e539 2456 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Anna Bridge 169:a7c7b631e539 2457
Anna Bridge 169:a7c7b631e539 2458 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Anna Bridge 169:a7c7b631e539 2459 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Anna Bridge 169:a7c7b631e539 2460 }
Anna Bridge 169:a7c7b631e539 2461
Anna Bridge 169:a7c7b631e539 2462
Anna Bridge 169:a7c7b631e539 2463 /**
Anna Bridge 169:a7c7b631e539 2464 \brief Set Interrupt Vector
Anna Bridge 169:a7c7b631e539 2465 \details Sets an interrupt vector in SRAM based interrupt vector table.
Anna Bridge 169:a7c7b631e539 2466 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 169:a7c7b631e539 2467 or negative to specify a processor exception.
Anna Bridge 169:a7c7b631e539 2468 VTOR must been relocated to SRAM before.
Anna Bridge 169:a7c7b631e539 2469 \param [in] IRQn Interrupt number
Anna Bridge 169:a7c7b631e539 2470 \param [in] vector Address of interrupt handler function
Anna Bridge 169:a7c7b631e539 2471 */
Anna Bridge 169:a7c7b631e539 2472 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Anna Bridge 169:a7c7b631e539 2473 {
Anna Bridge 169:a7c7b631e539 2474 uint32_t *vectors = (uint32_t *)SCB->VTOR;
Anna Bridge 169:a7c7b631e539 2475 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
Anna Bridge 169:a7c7b631e539 2476 }
Anna Bridge 169:a7c7b631e539 2477
Anna Bridge 169:a7c7b631e539 2478
Anna Bridge 169:a7c7b631e539 2479 /**
Anna Bridge 169:a7c7b631e539 2480 \brief Get Interrupt Vector
Anna Bridge 169:a7c7b631e539 2481 \details Reads an interrupt vector from interrupt vector table.
Anna Bridge 169:a7c7b631e539 2482 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 169:a7c7b631e539 2483 or negative to specify a processor exception.
Anna Bridge 169:a7c7b631e539 2484 \param [in] IRQn Interrupt number.
Anna Bridge 169:a7c7b631e539 2485 \return Address of interrupt handler function
Anna Bridge 169:a7c7b631e539 2486 */
Anna Bridge 169:a7c7b631e539 2487 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 2488 {
Anna Bridge 169:a7c7b631e539 2489 uint32_t *vectors = (uint32_t *)SCB->VTOR;
Anna Bridge 169:a7c7b631e539 2490 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
Anna Bridge 169:a7c7b631e539 2491 }
Anna Bridge 169:a7c7b631e539 2492
Anna Bridge 169:a7c7b631e539 2493
Anna Bridge 169:a7c7b631e539 2494 /**
Anna Bridge 169:a7c7b631e539 2495 \brief System Reset
Anna Bridge 169:a7c7b631e539 2496 \details Initiates a system reset request to reset the MCU.
Anna Bridge 169:a7c7b631e539 2497 */
Anna Bridge 169:a7c7b631e539 2498 __STATIC_INLINE void __NVIC_SystemReset(void)
Anna Bridge 169:a7c7b631e539 2499 {
Anna Bridge 169:a7c7b631e539 2500 __DSB(); /* Ensure all outstanding memory accesses included
Anna Bridge 169:a7c7b631e539 2501 buffered write are completed before reset */
Anna Bridge 169:a7c7b631e539 2502 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Anna Bridge 169:a7c7b631e539 2503 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
Anna Bridge 169:a7c7b631e539 2504 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Anna Bridge 169:a7c7b631e539 2505 __DSB(); /* Ensure completion of memory access */
Anna Bridge 169:a7c7b631e539 2506
Anna Bridge 169:a7c7b631e539 2507 for(;;) /* wait until reset */
Anna Bridge 169:a7c7b631e539 2508 {
Anna Bridge 169:a7c7b631e539 2509 __NOP();
Anna Bridge 169:a7c7b631e539 2510 }
Anna Bridge 169:a7c7b631e539 2511 }
Anna Bridge 169:a7c7b631e539 2512
Anna Bridge 169:a7c7b631e539 2513 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge 169:a7c7b631e539 2514 /**
Anna Bridge 169:a7c7b631e539 2515 \brief Set Priority Grouping (non-secure)
Anna Bridge 169:a7c7b631e539 2516 \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
Anna Bridge 169:a7c7b631e539 2517 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Anna Bridge 169:a7c7b631e539 2518 Only values from 0..7 are used.
Anna Bridge 169:a7c7b631e539 2519 In case of a conflict between priority grouping and available
Anna Bridge 169:a7c7b631e539 2520 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Anna Bridge 169:a7c7b631e539 2521 \param [in] PriorityGroup Priority grouping field.
Anna Bridge 169:a7c7b631e539 2522 */
Anna Bridge 169:a7c7b631e539 2523 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
Anna Bridge 169:a7c7b631e539 2524 {
Anna Bridge 169:a7c7b631e539 2525 uint32_t reg_value;
Anna Bridge 169:a7c7b631e539 2526 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Anna Bridge 169:a7c7b631e539 2527
Anna Bridge 169:a7c7b631e539 2528 reg_value = SCB_NS->AIRCR; /* read old register configuration */
Anna Bridge 169:a7c7b631e539 2529 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Anna Bridge 169:a7c7b631e539 2530 reg_value = (reg_value |
Anna Bridge 169:a7c7b631e539 2531 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Anna Bridge 169:a7c7b631e539 2532 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
Anna Bridge 169:a7c7b631e539 2533 SCB_NS->AIRCR = reg_value;
Anna Bridge 169:a7c7b631e539 2534 }
Anna Bridge 169:a7c7b631e539 2535
Anna Bridge 169:a7c7b631e539 2536
Anna Bridge 169:a7c7b631e539 2537 /**
Anna Bridge 169:a7c7b631e539 2538 \brief Get Priority Grouping (non-secure)
Anna Bridge 169:a7c7b631e539 2539 \details Reads the priority grouping field from the non-secure NVIC when in secure state.
Anna Bridge 169:a7c7b631e539 2540 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Anna Bridge 169:a7c7b631e539 2541 */
Anna Bridge 169:a7c7b631e539 2542 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
Anna Bridge 169:a7c7b631e539 2543 {
Anna Bridge 169:a7c7b631e539 2544 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Anna Bridge 169:a7c7b631e539 2545 }
Anna Bridge 169:a7c7b631e539 2546
Anna Bridge 169:a7c7b631e539 2547
Anna Bridge 169:a7c7b631e539 2548 /**
Anna Bridge 169:a7c7b631e539 2549 \brief Enable Interrupt (non-secure)
Anna Bridge 169:a7c7b631e539 2550 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
Anna Bridge 169:a7c7b631e539 2551 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 2552 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 2553 */
Anna Bridge 169:a7c7b631e539 2554 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 2555 {
Anna Bridge 169:a7c7b631e539 2556 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 2557 {
Anna Bridge 169:a7c7b631e539 2558 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 169:a7c7b631e539 2559 }
Anna Bridge 169:a7c7b631e539 2560 }
Anna Bridge 169:a7c7b631e539 2561
Anna Bridge 169:a7c7b631e539 2562
Anna Bridge 169:a7c7b631e539 2563 /**
Anna Bridge 169:a7c7b631e539 2564 \brief Get Interrupt Enable status (non-secure)
Anna Bridge 169:a7c7b631e539 2565 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
Anna Bridge 169:a7c7b631e539 2566 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 2567 \return 0 Interrupt is not enabled.
Anna Bridge 169:a7c7b631e539 2568 \return 1 Interrupt is enabled.
Anna Bridge 169:a7c7b631e539 2569 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 2570 */
Anna Bridge 169:a7c7b631e539 2571 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 2572 {
Anna Bridge 169:a7c7b631e539 2573 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 2574 {
Anna Bridge 169:a7c7b631e539 2575 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 169:a7c7b631e539 2576 }
Anna Bridge 169:a7c7b631e539 2577 else
Anna Bridge 169:a7c7b631e539 2578 {
Anna Bridge 169:a7c7b631e539 2579 return(0U);
Anna Bridge 169:a7c7b631e539 2580 }
Anna Bridge 169:a7c7b631e539 2581 }
Anna Bridge 169:a7c7b631e539 2582
Anna Bridge 169:a7c7b631e539 2583
Anna Bridge 169:a7c7b631e539 2584 /**
Anna Bridge 169:a7c7b631e539 2585 \brief Disable Interrupt (non-secure)
Anna Bridge 169:a7c7b631e539 2586 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
Anna Bridge 169:a7c7b631e539 2587 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 2588 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 2589 */
Anna Bridge 169:a7c7b631e539 2590 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 2591 {
Anna Bridge 169:a7c7b631e539 2592 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 2593 {
Anna Bridge 169:a7c7b631e539 2594 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 169:a7c7b631e539 2595 }
Anna Bridge 169:a7c7b631e539 2596 }
Anna Bridge 169:a7c7b631e539 2597
Anna Bridge 169:a7c7b631e539 2598
Anna Bridge 169:a7c7b631e539 2599 /**
Anna Bridge 169:a7c7b631e539 2600 \brief Get Pending Interrupt (non-secure)
Anna Bridge 169:a7c7b631e539 2601 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
Anna Bridge 169:a7c7b631e539 2602 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 2603 \return 0 Interrupt status is not pending.
Anna Bridge 169:a7c7b631e539 2604 \return 1 Interrupt status is pending.
Anna Bridge 169:a7c7b631e539 2605 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 2606 */
Anna Bridge 169:a7c7b631e539 2607 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 2608 {
Anna Bridge 169:a7c7b631e539 2609 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 2610 {
Anna Bridge 169:a7c7b631e539 2611 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 169:a7c7b631e539 2612 }
Anna Bridge 169:a7c7b631e539 2613 else
Anna Bridge 169:a7c7b631e539 2614 {
Anna Bridge 169:a7c7b631e539 2615 return(0U);
Anna Bridge 169:a7c7b631e539 2616 }
Anna Bridge 169:a7c7b631e539 2617 }
Anna Bridge 169:a7c7b631e539 2618
Anna Bridge 169:a7c7b631e539 2619
Anna Bridge 169:a7c7b631e539 2620 /**
Anna Bridge 169:a7c7b631e539 2621 \brief Set Pending Interrupt (non-secure)
Anna Bridge 169:a7c7b631e539 2622 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
Anna Bridge 169:a7c7b631e539 2623 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 2624 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 2625 */
Anna Bridge 169:a7c7b631e539 2626 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 2627 {
Anna Bridge 169:a7c7b631e539 2628 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 2629 {
Anna Bridge 169:a7c7b631e539 2630 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 169:a7c7b631e539 2631 }
Anna Bridge 169:a7c7b631e539 2632 }
Anna Bridge 169:a7c7b631e539 2633
Anna Bridge 169:a7c7b631e539 2634
Anna Bridge 169:a7c7b631e539 2635 /**
Anna Bridge 169:a7c7b631e539 2636 \brief Clear Pending Interrupt (non-secure)
Anna Bridge 169:a7c7b631e539 2637 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
Anna Bridge 169:a7c7b631e539 2638 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 2639 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 2640 */
Anna Bridge 169:a7c7b631e539 2641 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 2642 {
Anna Bridge 169:a7c7b631e539 2643 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 2644 {
Anna Bridge 169:a7c7b631e539 2645 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 169:a7c7b631e539 2646 }
Anna Bridge 169:a7c7b631e539 2647 }
Anna Bridge 169:a7c7b631e539 2648
Anna Bridge 169:a7c7b631e539 2649
Anna Bridge 169:a7c7b631e539 2650 /**
Anna Bridge 169:a7c7b631e539 2651 \brief Get Active Interrupt (non-secure)
Anna Bridge 169:a7c7b631e539 2652 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
Anna Bridge 169:a7c7b631e539 2653 \param [in] IRQn Device specific interrupt number.
Anna Bridge 169:a7c7b631e539 2654 \return 0 Interrupt status is not active.
Anna Bridge 169:a7c7b631e539 2655 \return 1 Interrupt status is active.
Anna Bridge 169:a7c7b631e539 2656 \note IRQn must not be negative.
Anna Bridge 169:a7c7b631e539 2657 */
Anna Bridge 169:a7c7b631e539 2658 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 2659 {
Anna Bridge 169:a7c7b631e539 2660 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 2661 {
Anna Bridge 169:a7c7b631e539 2662 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 169:a7c7b631e539 2663 }
Anna Bridge 169:a7c7b631e539 2664 else
Anna Bridge 169:a7c7b631e539 2665 {
Anna Bridge 169:a7c7b631e539 2666 return(0U);
Anna Bridge 169:a7c7b631e539 2667 }
Anna Bridge 169:a7c7b631e539 2668 }
Anna Bridge 169:a7c7b631e539 2669
Anna Bridge 169:a7c7b631e539 2670
Anna Bridge 169:a7c7b631e539 2671 /**
Anna Bridge 169:a7c7b631e539 2672 \brief Set Interrupt Priority (non-secure)
Anna Bridge 169:a7c7b631e539 2673 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
Anna Bridge 169:a7c7b631e539 2674 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 169:a7c7b631e539 2675 or negative to specify a processor exception.
Anna Bridge 169:a7c7b631e539 2676 \param [in] IRQn Interrupt number.
Anna Bridge 169:a7c7b631e539 2677 \param [in] priority Priority to set.
Anna Bridge 169:a7c7b631e539 2678 \note The priority cannot be set for every non-secure processor exception.
Anna Bridge 169:a7c7b631e539 2679 */
Anna Bridge 169:a7c7b631e539 2680 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
Anna Bridge 169:a7c7b631e539 2681 {
Anna Bridge 169:a7c7b631e539 2682 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 2683 {
Anna Bridge 169:a7c7b631e539 2684 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Anna Bridge 169:a7c7b631e539 2685 }
Anna Bridge 169:a7c7b631e539 2686 else
Anna Bridge 169:a7c7b631e539 2687 {
Anna Bridge 169:a7c7b631e539 2688 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Anna Bridge 169:a7c7b631e539 2689 }
Anna Bridge 169:a7c7b631e539 2690 }
Anna Bridge 169:a7c7b631e539 2691
Anna Bridge 169:a7c7b631e539 2692
Anna Bridge 169:a7c7b631e539 2693 /**
Anna Bridge 169:a7c7b631e539 2694 \brief Get Interrupt Priority (non-secure)
Anna Bridge 169:a7c7b631e539 2695 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
Anna Bridge 169:a7c7b631e539 2696 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 169:a7c7b631e539 2697 or negative to specify a processor exception.
Anna Bridge 169:a7c7b631e539 2698 \param [in] IRQn Interrupt number.
Anna Bridge 169:a7c7b631e539 2699 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
Anna Bridge 169:a7c7b631e539 2700 */
Anna Bridge 169:a7c7b631e539 2701 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
Anna Bridge 169:a7c7b631e539 2702 {
Anna Bridge 169:a7c7b631e539 2703
Anna Bridge 169:a7c7b631e539 2704 if ((int32_t)(IRQn) >= 0)
Anna Bridge 169:a7c7b631e539 2705 {
Anna Bridge 169:a7c7b631e539 2706 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 169:a7c7b631e539 2707 }
Anna Bridge 169:a7c7b631e539 2708 else
Anna Bridge 169:a7c7b631e539 2709 {
Anna Bridge 169:a7c7b631e539 2710 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 169:a7c7b631e539 2711 }
Anna Bridge 169:a7c7b631e539 2712 }
Anna Bridge 169:a7c7b631e539 2713 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
Anna Bridge 169:a7c7b631e539 2714
Anna Bridge 169:a7c7b631e539 2715 /*@} end of CMSIS_Core_NVICFunctions */
Anna Bridge 169:a7c7b631e539 2716
Anna Bridge 169:a7c7b631e539 2717 /* ########################## MPU functions #################################### */
Anna Bridge 169:a7c7b631e539 2718
Anna Bridge 169:a7c7b631e539 2719 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 169:a7c7b631e539 2720
Anna Bridge 169:a7c7b631e539 2721 #include "mpu_armv8.h"
Anna Bridge 169:a7c7b631e539 2722
Anna Bridge 169:a7c7b631e539 2723 #endif
Anna Bridge 169:a7c7b631e539 2724
Anna Bridge 169:a7c7b631e539 2725 /* ########################## FPU functions #################################### */
Anna Bridge 169:a7c7b631e539 2726 /**
Anna Bridge 169:a7c7b631e539 2727 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 169:a7c7b631e539 2728 \defgroup CMSIS_Core_FpuFunctions FPU Functions
Anna Bridge 169:a7c7b631e539 2729 \brief Function that provides FPU type.
Anna Bridge 169:a7c7b631e539 2730 @{
Anna Bridge 169:a7c7b631e539 2731 */
Anna Bridge 169:a7c7b631e539 2732
Anna Bridge 169:a7c7b631e539 2733 /**
Anna Bridge 169:a7c7b631e539 2734 \brief get FPU type
Anna Bridge 169:a7c7b631e539 2735 \details returns the FPU type
Anna Bridge 169:a7c7b631e539 2736 \returns
Anna Bridge 169:a7c7b631e539 2737 - \b 0: No FPU
Anna Bridge 169:a7c7b631e539 2738 - \b 1: Single precision FPU
Anna Bridge 169:a7c7b631e539 2739 - \b 2: Double + Single precision FPU
Anna Bridge 169:a7c7b631e539 2740 */
Anna Bridge 169:a7c7b631e539 2741 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
Anna Bridge 169:a7c7b631e539 2742 {
Anna Bridge 169:a7c7b631e539 2743 uint32_t mvfr0;
Anna Bridge 169:a7c7b631e539 2744
Anna Bridge 169:a7c7b631e539 2745 mvfr0 = FPU->MVFR0;
Anna Bridge 169:a7c7b631e539 2746 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
Anna Bridge 169:a7c7b631e539 2747 {
Anna Bridge 169:a7c7b631e539 2748 return 2U; /* Double + Single precision FPU */
Anna Bridge 169:a7c7b631e539 2749 }
Anna Bridge 169:a7c7b631e539 2750 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
Anna Bridge 169:a7c7b631e539 2751 {
Anna Bridge 169:a7c7b631e539 2752 return 1U; /* Single precision FPU */
Anna Bridge 169:a7c7b631e539 2753 }
Anna Bridge 169:a7c7b631e539 2754 else
Anna Bridge 169:a7c7b631e539 2755 {
Anna Bridge 169:a7c7b631e539 2756 return 0U; /* No FPU */
Anna Bridge 169:a7c7b631e539 2757 }
Anna Bridge 169:a7c7b631e539 2758 }
Anna Bridge 169:a7c7b631e539 2759
Anna Bridge 169:a7c7b631e539 2760
Anna Bridge 169:a7c7b631e539 2761 /*@} end of CMSIS_Core_FpuFunctions */
Anna Bridge 169:a7c7b631e539 2762
Anna Bridge 169:a7c7b631e539 2763
Anna Bridge 169:a7c7b631e539 2764
Anna Bridge 169:a7c7b631e539 2765 /* ########################## SAU functions #################################### */
Anna Bridge 169:a7c7b631e539 2766 /**
Anna Bridge 169:a7c7b631e539 2767 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 169:a7c7b631e539 2768 \defgroup CMSIS_Core_SAUFunctions SAU Functions
Anna Bridge 169:a7c7b631e539 2769 \brief Functions that configure the SAU.
Anna Bridge 169:a7c7b631e539 2770 @{
Anna Bridge 169:a7c7b631e539 2771 */
Anna Bridge 169:a7c7b631e539 2772
Anna Bridge 169:a7c7b631e539 2773 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge 169:a7c7b631e539 2774
Anna Bridge 169:a7c7b631e539 2775 /**
Anna Bridge 169:a7c7b631e539 2776 \brief Enable SAU
Anna Bridge 169:a7c7b631e539 2777 \details Enables the Security Attribution Unit (SAU).
Anna Bridge 169:a7c7b631e539 2778 */
Anna Bridge 169:a7c7b631e539 2779 __STATIC_INLINE void TZ_SAU_Enable(void)
Anna Bridge 169:a7c7b631e539 2780 {
Anna Bridge 169:a7c7b631e539 2781 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
Anna Bridge 169:a7c7b631e539 2782 }
Anna Bridge 169:a7c7b631e539 2783
Anna Bridge 169:a7c7b631e539 2784
Anna Bridge 169:a7c7b631e539 2785
Anna Bridge 169:a7c7b631e539 2786 /**
Anna Bridge 169:a7c7b631e539 2787 \brief Disable SAU
Anna Bridge 169:a7c7b631e539 2788 \details Disables the Security Attribution Unit (SAU).
Anna Bridge 169:a7c7b631e539 2789 */
Anna Bridge 169:a7c7b631e539 2790 __STATIC_INLINE void TZ_SAU_Disable(void)
Anna Bridge 169:a7c7b631e539 2791 {
Anna Bridge 169:a7c7b631e539 2792 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
Anna Bridge 169:a7c7b631e539 2793 }
Anna Bridge 169:a7c7b631e539 2794
Anna Bridge 169:a7c7b631e539 2795 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge 169:a7c7b631e539 2796
Anna Bridge 169:a7c7b631e539 2797 /*@} end of CMSIS_Core_SAUFunctions */
Anna Bridge 169:a7c7b631e539 2798
Anna Bridge 169:a7c7b631e539 2799
Anna Bridge 169:a7c7b631e539 2800
Anna Bridge 169:a7c7b631e539 2801
Anna Bridge 169:a7c7b631e539 2802 /* ################################## SysTick function ############################################ */
Anna Bridge 169:a7c7b631e539 2803 /**
Anna Bridge 169:a7c7b631e539 2804 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 169:a7c7b631e539 2805 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Anna Bridge 169:a7c7b631e539 2806 \brief Functions that configure the System.
Anna Bridge 169:a7c7b631e539 2807 @{
Anna Bridge 169:a7c7b631e539 2808 */
Anna Bridge 169:a7c7b631e539 2809
Anna Bridge 169:a7c7b631e539 2810 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
Anna Bridge 169:a7c7b631e539 2811
Anna Bridge 169:a7c7b631e539 2812 /**
Anna Bridge 169:a7c7b631e539 2813 \brief System Tick Configuration
Anna Bridge 169:a7c7b631e539 2814 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Anna Bridge 169:a7c7b631e539 2815 Counter is in free running mode to generate periodic interrupts.
Anna Bridge 169:a7c7b631e539 2816 \param [in] ticks Number of ticks between two interrupts.
Anna Bridge 169:a7c7b631e539 2817 \return 0 Function succeeded.
Anna Bridge 169:a7c7b631e539 2818 \return 1 Function failed.
Anna Bridge 169:a7c7b631e539 2819 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Anna Bridge 169:a7c7b631e539 2820 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Anna Bridge 169:a7c7b631e539 2821 must contain a vendor-specific implementation of this function.
Anna Bridge 169:a7c7b631e539 2822 */
Anna Bridge 169:a7c7b631e539 2823 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Anna Bridge 169:a7c7b631e539 2824 {
Anna Bridge 169:a7c7b631e539 2825 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Anna Bridge 169:a7c7b631e539 2826 {
Anna Bridge 169:a7c7b631e539 2827 return (1UL); /* Reload value impossible */
Anna Bridge 169:a7c7b631e539 2828 }
Anna Bridge 169:a7c7b631e539 2829
Anna Bridge 169:a7c7b631e539 2830 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Anna Bridge 169:a7c7b631e539 2831 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Anna Bridge 169:a7c7b631e539 2832 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Anna Bridge 169:a7c7b631e539 2833 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Anna Bridge 169:a7c7b631e539 2834 SysTick_CTRL_TICKINT_Msk |
Anna Bridge 169:a7c7b631e539 2835 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Anna Bridge 169:a7c7b631e539 2836 return (0UL); /* Function successful */
Anna Bridge 169:a7c7b631e539 2837 }
Anna Bridge 169:a7c7b631e539 2838
Anna Bridge 169:a7c7b631e539 2839 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
Anna Bridge 169:a7c7b631e539 2840 /**
Anna Bridge 169:a7c7b631e539 2841 \brief System Tick Configuration (non-secure)
Anna Bridge 169:a7c7b631e539 2842 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
Anna Bridge 169:a7c7b631e539 2843 Counter is in free running mode to generate periodic interrupts.
Anna Bridge 169:a7c7b631e539 2844 \param [in] ticks Number of ticks between two interrupts.
Anna Bridge 169:a7c7b631e539 2845 \return 0 Function succeeded.
Anna Bridge 169:a7c7b631e539 2846 \return 1 Function failed.
Anna Bridge 169:a7c7b631e539 2847 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Anna Bridge 169:a7c7b631e539 2848 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
Anna Bridge 169:a7c7b631e539 2849 must contain a vendor-specific implementation of this function.
Anna Bridge 169:a7c7b631e539 2850
Anna Bridge 169:a7c7b631e539 2851 */
Anna Bridge 169:a7c7b631e539 2852 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
Anna Bridge 169:a7c7b631e539 2853 {
Anna Bridge 169:a7c7b631e539 2854 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Anna Bridge 169:a7c7b631e539 2855 {
Anna Bridge 169:a7c7b631e539 2856 return (1UL); /* Reload value impossible */
Anna Bridge 169:a7c7b631e539 2857 }
Anna Bridge 169:a7c7b631e539 2858
Anna Bridge 169:a7c7b631e539 2859 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Anna Bridge 169:a7c7b631e539 2860 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Anna Bridge 169:a7c7b631e539 2861 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
Anna Bridge 169:a7c7b631e539 2862 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Anna Bridge 169:a7c7b631e539 2863 SysTick_CTRL_TICKINT_Msk |
Anna Bridge 169:a7c7b631e539 2864 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Anna Bridge 169:a7c7b631e539 2865 return (0UL); /* Function successful */
Anna Bridge 169:a7c7b631e539 2866 }
Anna Bridge 169:a7c7b631e539 2867 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
Anna Bridge 169:a7c7b631e539 2868
Anna Bridge 169:a7c7b631e539 2869 #endif
Anna Bridge 169:a7c7b631e539 2870
Anna Bridge 169:a7c7b631e539 2871 /*@} end of CMSIS_Core_SysTickFunctions */
Anna Bridge 169:a7c7b631e539 2872
Anna Bridge 169:a7c7b631e539 2873
Anna Bridge 169:a7c7b631e539 2874
Anna Bridge 169:a7c7b631e539 2875 /* ##################################### Debug In/Output function ########################################### */
Anna Bridge 169:a7c7b631e539 2876 /**
Anna Bridge 169:a7c7b631e539 2877 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 169:a7c7b631e539 2878 \defgroup CMSIS_core_DebugFunctions ITM Functions
Anna Bridge 169:a7c7b631e539 2879 \brief Functions that access the ITM debug interface.
Anna Bridge 169:a7c7b631e539 2880 @{
Anna Bridge 169:a7c7b631e539 2881 */
Anna Bridge 169:a7c7b631e539 2882
Anna Bridge 169:a7c7b631e539 2883 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
Anna Bridge 169:a7c7b631e539 2884 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
Anna Bridge 169:a7c7b631e539 2885
Anna Bridge 169:a7c7b631e539 2886
Anna Bridge 169:a7c7b631e539 2887 /**
Anna Bridge 169:a7c7b631e539 2888 \brief ITM Send Character
Anna Bridge 169:a7c7b631e539 2889 \details Transmits a character via the ITM channel 0, and
Anna Bridge 169:a7c7b631e539 2890 \li Just returns when no debugger is connected that has booked the output.
Anna Bridge 169:a7c7b631e539 2891 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Anna Bridge 169:a7c7b631e539 2892 \param [in] ch Character to transmit.
Anna Bridge 169:a7c7b631e539 2893 \returns Character to transmit.
Anna Bridge 169:a7c7b631e539 2894 */
Anna Bridge 169:a7c7b631e539 2895 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Anna Bridge 169:a7c7b631e539 2896 {
Anna Bridge 169:a7c7b631e539 2897 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Anna Bridge 169:a7c7b631e539 2898 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Anna Bridge 169:a7c7b631e539 2899 {
Anna Bridge 169:a7c7b631e539 2900 while (ITM->PORT[0U].u32 == 0UL)
Anna Bridge 169:a7c7b631e539 2901 {
Anna Bridge 169:a7c7b631e539 2902 __NOP();
Anna Bridge 169:a7c7b631e539 2903 }
Anna Bridge 169:a7c7b631e539 2904 ITM->PORT[0U].u8 = (uint8_t)ch;
Anna Bridge 169:a7c7b631e539 2905 }
Anna Bridge 169:a7c7b631e539 2906 return (ch);
Anna Bridge 169:a7c7b631e539 2907 }
Anna Bridge 169:a7c7b631e539 2908
Anna Bridge 169:a7c7b631e539 2909
Anna Bridge 169:a7c7b631e539 2910 /**
Anna Bridge 169:a7c7b631e539 2911 \brief ITM Receive Character
Anna Bridge 169:a7c7b631e539 2912 \details Inputs a character via the external variable \ref ITM_RxBuffer.
Anna Bridge 169:a7c7b631e539 2913 \return Received character.
Anna Bridge 169:a7c7b631e539 2914 \return -1 No character pending.
Anna Bridge 169:a7c7b631e539 2915 */
Anna Bridge 169:a7c7b631e539 2916 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
Anna Bridge 169:a7c7b631e539 2917 {
Anna Bridge 169:a7c7b631e539 2918 int32_t ch = -1; /* no character available */
Anna Bridge 169:a7c7b631e539 2919
Anna Bridge 169:a7c7b631e539 2920 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
Anna Bridge 169:a7c7b631e539 2921 {
Anna Bridge 169:a7c7b631e539 2922 ch = ITM_RxBuffer;
Anna Bridge 169:a7c7b631e539 2923 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Anna Bridge 169:a7c7b631e539 2924 }
Anna Bridge 169:a7c7b631e539 2925
Anna Bridge 169:a7c7b631e539 2926 return (ch);
Anna Bridge 169:a7c7b631e539 2927 }
Anna Bridge 169:a7c7b631e539 2928
Anna Bridge 169:a7c7b631e539 2929
Anna Bridge 169:a7c7b631e539 2930 /**
Anna Bridge 169:a7c7b631e539 2931 \brief ITM Check Character
Anna Bridge 169:a7c7b631e539 2932 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Anna Bridge 169:a7c7b631e539 2933 \return 0 No character available.
Anna Bridge 169:a7c7b631e539 2934 \return 1 Character available.
Anna Bridge 169:a7c7b631e539 2935 */
Anna Bridge 169:a7c7b631e539 2936 __STATIC_INLINE int32_t ITM_CheckChar (void)
Anna Bridge 169:a7c7b631e539 2937 {
Anna Bridge 169:a7c7b631e539 2938
Anna Bridge 169:a7c7b631e539 2939 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
Anna Bridge 169:a7c7b631e539 2940 {
Anna Bridge 169:a7c7b631e539 2941 return (0); /* no character available */
Anna Bridge 169:a7c7b631e539 2942 }
Anna Bridge 169:a7c7b631e539 2943 else
Anna Bridge 169:a7c7b631e539 2944 {
Anna Bridge 169:a7c7b631e539 2945 return (1); /* character available */
Anna Bridge 169:a7c7b631e539 2946 }
Anna Bridge 169:a7c7b631e539 2947 }
Anna Bridge 169:a7c7b631e539 2948
Anna Bridge 169:a7c7b631e539 2949 /*@} end of CMSIS_core_DebugFunctions */
Anna Bridge 169:a7c7b631e539 2950
Anna Bridge 169:a7c7b631e539 2951
Anna Bridge 169:a7c7b631e539 2952
Anna Bridge 169:a7c7b631e539 2953
Anna Bridge 169:a7c7b631e539 2954 #ifdef __cplusplus
Anna Bridge 169:a7c7b631e539 2955 }
Anna Bridge 169:a7c7b631e539 2956 #endif
Anna Bridge 169:a7c7b631e539 2957
Anna Bridge 169:a7c7b631e539 2958 #endif /* __CORE_ARMV8MML_H_DEPENDANT */
Anna Bridge 169:a7c7b631e539 2959
Anna Bridge 169:a7c7b631e539 2960 #endif /* __CMSIS_GENERIC */