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TARGET_MAX32620FTHR/mpu_armv8.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 15:38:59 2018 +0100
Revision:
169:a7c7b631e539
Parent:
167:84c0a372a020 
mbed library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:84c0a372a020 1 /******************************************************************************
AnnaBridge 167:84c0a372a020 2 * @file mpu_armv8.h
Anna Bridge 169:a7c7b631e539 3 * @brief CMSIS MPU API for Armv8-M MPU
Anna Bridge 169:a7c7b631e539 4 * @version V5.0.4
Anna Bridge 169:a7c7b631e539 5 * @date 10. January 2018
AnnaBridge 167:84c0a372a020 6 ******************************************************************************/
AnnaBridge 167:84c0a372a020 7 /*
Anna Bridge 169:a7c7b631e539 8 * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
AnnaBridge 167:84c0a372a020 9 *
AnnaBridge 167:84c0a372a020 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 167:84c0a372a020 11 *
AnnaBridge 167:84c0a372a020 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 167:84c0a372a020 13 * not use this file except in compliance with the License.
AnnaBridge 167:84c0a372a020 14 * You may obtain a copy of the License at
AnnaBridge 167:84c0a372a020 15 *
AnnaBridge 167:84c0a372a020 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 167:84c0a372a020 17 *
AnnaBridge 167:84c0a372a020 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 167:84c0a372a020 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 167:84c0a372a020 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 167:84c0a372a020 21 * See the License for the specific language governing permissions and
AnnaBridge 167:84c0a372a020 22 * limitations under the License.
AnnaBridge 167:84c0a372a020 23 */
Anna Bridge 169:a7c7b631e539 24
Anna Bridge 169:a7c7b631e539 25 #if defined ( __ICCARM__ )
Anna Bridge 169:a7c7b631e539 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 169:a7c7b631e539 27 #elif defined (__clang__)
Anna Bridge 169:a7c7b631e539 28 #pragma clang system_header /* treat file as system include file */
Anna Bridge 169:a7c7b631e539 29 #endif
Anna Bridge 169:a7c7b631e539 30
AnnaBridge 167:84c0a372a020 31 #ifndef ARM_MPU_ARMV8_H
AnnaBridge 167:84c0a372a020 32 #define ARM_MPU_ARMV8_H
AnnaBridge 167:84c0a372a020 33
AnnaBridge 167:84c0a372a020 34 /** \brief Attribute for device memory (outer only) */
AnnaBridge 167:84c0a372a020 35 #define ARM_MPU_ATTR_DEVICE ( 0U )
AnnaBridge 167:84c0a372a020 36
AnnaBridge 167:84c0a372a020 37 /** \brief Attribute for non-cacheable, normal memory */
AnnaBridge 167:84c0a372a020 38 #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
AnnaBridge 167:84c0a372a020 39
AnnaBridge 167:84c0a372a020 40 /** \brief Attribute for normal memory (outer and inner)
AnnaBridge 167:84c0a372a020 41 * \param NT Non-Transient: Set to 1 for non-transient data.
AnnaBridge 167:84c0a372a020 42 * \param WB Write-Back: Set to 1 to use write-back update policy.
AnnaBridge 167:84c0a372a020 43 * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
AnnaBridge 167:84c0a372a020 44 * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
AnnaBridge 167:84c0a372a020 45 */
AnnaBridge 167:84c0a372a020 46 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
AnnaBridge 167:84c0a372a020 47 (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
AnnaBridge 167:84c0a372a020 48
AnnaBridge 167:84c0a372a020 49 /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
AnnaBridge 167:84c0a372a020 50 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
AnnaBridge 167:84c0a372a020 51
AnnaBridge 167:84c0a372a020 52 /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
AnnaBridge 167:84c0a372a020 53 #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
AnnaBridge 167:84c0a372a020 54
AnnaBridge 167:84c0a372a020 55 /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
AnnaBridge 167:84c0a372a020 56 #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
AnnaBridge 167:84c0a372a020 57
AnnaBridge 167:84c0a372a020 58 /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
AnnaBridge 167:84c0a372a020 59 #define ARM_MPU_ATTR_DEVICE_GRE (3U)
AnnaBridge 167:84c0a372a020 60
AnnaBridge 167:84c0a372a020 61 /** \brief Memory Attribute
AnnaBridge 167:84c0a372a020 62 * \param O Outer memory attributes
AnnaBridge 167:84c0a372a020 63 * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
AnnaBridge 167:84c0a372a020 64 */
AnnaBridge 167:84c0a372a020 65 #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
AnnaBridge 167:84c0a372a020 66
AnnaBridge 167:84c0a372a020 67 /** \brief Normal memory non-shareable */
AnnaBridge 167:84c0a372a020 68 #define ARM_MPU_SH_NON (0U)
AnnaBridge 167:84c0a372a020 69
AnnaBridge 167:84c0a372a020 70 /** \brief Normal memory outer shareable */
AnnaBridge 167:84c0a372a020 71 #define ARM_MPU_SH_OUTER (2U)
AnnaBridge 167:84c0a372a020 72
AnnaBridge 167:84c0a372a020 73 /** \brief Normal memory inner shareable */
AnnaBridge 167:84c0a372a020 74 #define ARM_MPU_SH_INNER (3U)
AnnaBridge 167:84c0a372a020 75
AnnaBridge 167:84c0a372a020 76 /** \brief Memory access permissions
AnnaBridge 167:84c0a372a020 77 * \param RO Read-Only: Set to 1 for read-only memory.
AnnaBridge 167:84c0a372a020 78 * \param NP Non-Privileged: Set to 1 for non-privileged memory.
AnnaBridge 167:84c0a372a020 79 */
AnnaBridge 167:84c0a372a020 80 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
AnnaBridge 167:84c0a372a020 81
AnnaBridge 167:84c0a372a020 82 /** \brief Region Base Address Register value
AnnaBridge 167:84c0a372a020 83 * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
AnnaBridge 167:84c0a372a020 84 * \param SH Defines the Shareability domain for this memory region.
AnnaBridge 167:84c0a372a020 85 * \param RO Read-Only: Set to 1 for a read-only memory region.
AnnaBridge 167:84c0a372a020 86 * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
AnnaBridge 167:84c0a372a020 87 * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
AnnaBridge 167:84c0a372a020 88 */
AnnaBridge 167:84c0a372a020 89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
AnnaBridge 167:84c0a372a020 90 ((BASE & MPU_RBAR_BASE_Pos) | \
AnnaBridge 167:84c0a372a020 91 ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
AnnaBridge 167:84c0a372a020 92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
AnnaBridge 167:84c0a372a020 93 ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
AnnaBridge 167:84c0a372a020 94
AnnaBridge 167:84c0a372a020 95 /** \brief Region Limit Address Register value
AnnaBridge 167:84c0a372a020 96 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
AnnaBridge 167:84c0a372a020 97 * \param IDX The attribute index to be associated with this memory region.
AnnaBridge 167:84c0a372a020 98 */
AnnaBridge 167:84c0a372a020 99 #define ARM_MPU_RLAR(LIMIT, IDX) \
AnnaBridge 167:84c0a372a020 100 ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
AnnaBridge 167:84c0a372a020 101 ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
AnnaBridge 167:84c0a372a020 102 (MPU_RLAR_EN_Msk))
AnnaBridge 167:84c0a372a020 103
AnnaBridge 167:84c0a372a020 104 /**
AnnaBridge 167:84c0a372a020 105 * Struct for a single MPU Region
AnnaBridge 167:84c0a372a020 106 */
Anna Bridge 169:a7c7b631e539 107 typedef struct {
AnnaBridge 167:84c0a372a020 108 uint32_t RBAR; /*!< Region Base Address Register value */
AnnaBridge 167:84c0a372a020 109 uint32_t RLAR; /*!< Region Limit Address Register value */
AnnaBridge 167:84c0a372a020 110 } ARM_MPU_Region_t;
AnnaBridge 167:84c0a372a020 111
AnnaBridge 167:84c0a372a020 112 /** Enable the MPU.
AnnaBridge 167:84c0a372a020 113 * \param MPU_Control Default access permissions for unconfigured regions.
AnnaBridge 167:84c0a372a020 114 */
AnnaBridge 167:84c0a372a020 115 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
AnnaBridge 167:84c0a372a020 116 {
AnnaBridge 167:84c0a372a020 117 __DSB();
AnnaBridge 167:84c0a372a020 118 __ISB();
AnnaBridge 167:84c0a372a020 119 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
AnnaBridge 167:84c0a372a020 120 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 167:84c0a372a020 121 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 167:84c0a372a020 122 #endif
AnnaBridge 167:84c0a372a020 123 }
AnnaBridge 167:84c0a372a020 124
AnnaBridge 167:84c0a372a020 125 /** Disable the MPU.
AnnaBridge 167:84c0a372a020 126 */
AnnaBridge 167:84c0a372a020 127 __STATIC_INLINE void ARM_MPU_Disable(void)
AnnaBridge 167:84c0a372a020 128 {
AnnaBridge 167:84c0a372a020 129 __DSB();
AnnaBridge 167:84c0a372a020 130 __ISB();
AnnaBridge 167:84c0a372a020 131 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 167:84c0a372a020 132 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 167:84c0a372a020 133 #endif
AnnaBridge 167:84c0a372a020 134 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
AnnaBridge 167:84c0a372a020 135 }
AnnaBridge 167:84c0a372a020 136
AnnaBridge 167:84c0a372a020 137 #ifdef MPU_NS
AnnaBridge 167:84c0a372a020 138 /** Enable the Non-secure MPU.
AnnaBridge 167:84c0a372a020 139 * \param MPU_Control Default access permissions for unconfigured regions.
AnnaBridge 167:84c0a372a020 140 */
AnnaBridge 167:84c0a372a020 141 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
AnnaBridge 167:84c0a372a020 142 {
AnnaBridge 167:84c0a372a020 143 __DSB();
AnnaBridge 167:84c0a372a020 144 __ISB();
AnnaBridge 167:84c0a372a020 145 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
AnnaBridge 167:84c0a372a020 146 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 167:84c0a372a020 147 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 167:84c0a372a020 148 #endif
AnnaBridge 167:84c0a372a020 149 }
AnnaBridge 167:84c0a372a020 150
AnnaBridge 167:84c0a372a020 151 /** Disable the Non-secure MPU.
AnnaBridge 167:84c0a372a020 152 */
AnnaBridge 167:84c0a372a020 153 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
AnnaBridge 167:84c0a372a020 154 {
AnnaBridge 167:84c0a372a020 155 __DSB();
AnnaBridge 167:84c0a372a020 156 __ISB();
AnnaBridge 167:84c0a372a020 157 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
AnnaBridge 167:84c0a372a020 158 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 167:84c0a372a020 159 #endif
AnnaBridge 167:84c0a372a020 160 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
AnnaBridge 167:84c0a372a020 161 }
AnnaBridge 167:84c0a372a020 162 #endif
AnnaBridge 167:84c0a372a020 163
AnnaBridge 167:84c0a372a020 164 /** Set the memory attribute encoding to the given MPU.
AnnaBridge 167:84c0a372a020 165 * \param mpu Pointer to the MPU to be configured.
AnnaBridge 167:84c0a372a020 166 * \param idx The attribute index to be set [0-7]
AnnaBridge 167:84c0a372a020 167 * \param attr The attribute value to be set.
AnnaBridge 167:84c0a372a020 168 */
AnnaBridge 167:84c0a372a020 169 __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
AnnaBridge 167:84c0a372a020 170 {
AnnaBridge 167:84c0a372a020 171 const uint8_t reg = idx / 4U;
AnnaBridge 167:84c0a372a020 172 const uint32_t pos = ((idx % 4U) * 8U);
AnnaBridge 167:84c0a372a020 173 const uint32_t mask = 0xFFU << pos;
AnnaBridge 167:84c0a372a020 174
Anna Bridge 169:a7c7b631e539 175 if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
AnnaBridge 167:84c0a372a020 176 return; // invalid index
AnnaBridge 167:84c0a372a020 177 }
AnnaBridge 167:84c0a372a020 178
Anna Bridge 169:a7c7b631e539 179 mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
AnnaBridge 167:84c0a372a020 180 }
AnnaBridge 167:84c0a372a020 181
AnnaBridge 167:84c0a372a020 182 /** Set the memory attribute encoding.
AnnaBridge 167:84c0a372a020 183 * \param idx The attribute index to be set [0-7]
AnnaBridge 167:84c0a372a020 184 * \param attr The attribute value to be set.
AnnaBridge 167:84c0a372a020 185 */
AnnaBridge 167:84c0a372a020 186 __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
AnnaBridge 167:84c0a372a020 187 {
AnnaBridge 167:84c0a372a020 188 ARM_MPU_SetMemAttrEx(MPU, idx, attr);
AnnaBridge 167:84c0a372a020 189 }
AnnaBridge 167:84c0a372a020 190
AnnaBridge 167:84c0a372a020 191 #ifdef MPU_NS
AnnaBridge 167:84c0a372a020 192 /** Set the memory attribute encoding to the Non-secure MPU.
AnnaBridge 167:84c0a372a020 193 * \param idx The attribute index to be set [0-7]
AnnaBridge 167:84c0a372a020 194 * \param attr The attribute value to be set.
AnnaBridge 167:84c0a372a020 195 */
AnnaBridge 167:84c0a372a020 196 __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
AnnaBridge 167:84c0a372a020 197 {
AnnaBridge 167:84c0a372a020 198 ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
AnnaBridge 167:84c0a372a020 199 }
AnnaBridge 167:84c0a372a020 200 #endif
AnnaBridge 167:84c0a372a020 201
AnnaBridge 167:84c0a372a020 202 /** Clear and disable the given MPU region of the given MPU.
AnnaBridge 167:84c0a372a020 203 * \param mpu Pointer to MPU to be used.
AnnaBridge 167:84c0a372a020 204 * \param rnr Region number to be cleared.
AnnaBridge 167:84c0a372a020 205 */
AnnaBridge 167:84c0a372a020 206 __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
AnnaBridge 167:84c0a372a020 207 {
Anna Bridge 169:a7c7b631e539 208 mpu->RNR = rnr;
Anna Bridge 169:a7c7b631e539 209 mpu->RLAR = 0U;
AnnaBridge 167:84c0a372a020 210 }
AnnaBridge 167:84c0a372a020 211
AnnaBridge 167:84c0a372a020 212 /** Clear and disable the given MPU region.
AnnaBridge 167:84c0a372a020 213 * \param rnr Region number to be cleared.
AnnaBridge 167:84c0a372a020 214 */
AnnaBridge 167:84c0a372a020 215 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
AnnaBridge 167:84c0a372a020 216 {
AnnaBridge 167:84c0a372a020 217 ARM_MPU_ClrRegionEx(MPU, rnr);
AnnaBridge 167:84c0a372a020 218 }
AnnaBridge 167:84c0a372a020 219
AnnaBridge 167:84c0a372a020 220 #ifdef MPU_NS
AnnaBridge 167:84c0a372a020 221 /** Clear and disable the given Non-secure MPU region.
AnnaBridge 167:84c0a372a020 222 * \param rnr Region number to be cleared.
AnnaBridge 167:84c0a372a020 223 */
AnnaBridge 167:84c0a372a020 224 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
AnnaBridge 167:84c0a372a020 225 {
AnnaBridge 167:84c0a372a020 226 ARM_MPU_ClrRegionEx(MPU_NS, rnr);
AnnaBridge 167:84c0a372a020 227 }
AnnaBridge 167:84c0a372a020 228 #endif
AnnaBridge 167:84c0a372a020 229
AnnaBridge 167:84c0a372a020 230 /** Configure the given MPU region of the given MPU.
AnnaBridge 167:84c0a372a020 231 * \param mpu Pointer to MPU to be used.
AnnaBridge 167:84c0a372a020 232 * \param rnr Region number to be configured.
AnnaBridge 167:84c0a372a020 233 * \param rbar Value for RBAR register.
AnnaBridge 167:84c0a372a020 234 * \param rlar Value for RLAR register.
AnnaBridge 167:84c0a372a020 235 */
AnnaBridge 167:84c0a372a020 236 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
AnnaBridge 167:84c0a372a020 237 {
Anna Bridge 169:a7c7b631e539 238 mpu->RNR = rnr;
Anna Bridge 169:a7c7b631e539 239 mpu->RBAR = rbar;
Anna Bridge 169:a7c7b631e539 240 mpu->RLAR = rlar;
AnnaBridge 167:84c0a372a020 241 }
AnnaBridge 167:84c0a372a020 242
AnnaBridge 167:84c0a372a020 243 /** Configure the given MPU region.
AnnaBridge 167:84c0a372a020 244 * \param rnr Region number to be configured.
AnnaBridge 167:84c0a372a020 245 * \param rbar Value for RBAR register.
AnnaBridge 167:84c0a372a020 246 * \param rlar Value for RLAR register.
AnnaBridge 167:84c0a372a020 247 */
AnnaBridge 167:84c0a372a020 248 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
AnnaBridge 167:84c0a372a020 249 {
AnnaBridge 167:84c0a372a020 250 ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
AnnaBridge 167:84c0a372a020 251 }
AnnaBridge 167:84c0a372a020 252
AnnaBridge 167:84c0a372a020 253 #ifdef MPU_NS
AnnaBridge 167:84c0a372a020 254 /** Configure the given Non-secure MPU region.
AnnaBridge 167:84c0a372a020 255 * \param rnr Region number to be configured.
AnnaBridge 167:84c0a372a020 256 * \param rbar Value for RBAR register.
AnnaBridge 167:84c0a372a020 257 * \param rlar Value for RLAR register.
AnnaBridge 167:84c0a372a020 258 */
AnnaBridge 167:84c0a372a020 259 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
AnnaBridge 167:84c0a372a020 260 {
AnnaBridge 167:84c0a372a020 261 ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
AnnaBridge 167:84c0a372a020 262 }
AnnaBridge 167:84c0a372a020 263 #endif
AnnaBridge 167:84c0a372a020 264
AnnaBridge 167:84c0a372a020 265 /** Memcopy with strictly ordered memory access, e.g. for register targets.
AnnaBridge 167:84c0a372a020 266 * \param dst Destination data is copied to.
AnnaBridge 167:84c0a372a020 267 * \param src Source data is copied from.
AnnaBridge 167:84c0a372a020 268 * \param len Amount of data words to be copied.
AnnaBridge 167:84c0a372a020 269 */
AnnaBridge 167:84c0a372a020 270 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
AnnaBridge 167:84c0a372a020 271 {
AnnaBridge 167:84c0a372a020 272 uint32_t i;
AnnaBridge 167:84c0a372a020 273 for (i = 0U; i < len; ++i)
AnnaBridge 167:84c0a372a020 274 {
AnnaBridge 167:84c0a372a020 275 dst[i] = src[i];
AnnaBridge 167:84c0a372a020 276 }
AnnaBridge 167:84c0a372a020 277 }
AnnaBridge 167:84c0a372a020 278
AnnaBridge 167:84c0a372a020 279 /** Load the given number of MPU regions from a table to the given MPU.
AnnaBridge 167:84c0a372a020 280 * \param mpu Pointer to the MPU registers to be used.
AnnaBridge 167:84c0a372a020 281 * \param rnr First region number to be configured.
AnnaBridge 167:84c0a372a020 282 * \param table Pointer to the MPU configuration table.
AnnaBridge 167:84c0a372a020 283 * \param cnt Amount of regions to be configured.
AnnaBridge 167:84c0a372a020 284 */
AnnaBridge 167:84c0a372a020 285 __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
AnnaBridge 167:84c0a372a020 286 {
Anna Bridge 169:a7c7b631e539 287 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
AnnaBridge 167:84c0a372a020 288 if (cnt == 1U) {
AnnaBridge 167:84c0a372a020 289 mpu->RNR = rnr;
AnnaBridge 167:84c0a372a020 290 orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
AnnaBridge 167:84c0a372a020 291 } else {
AnnaBridge 167:84c0a372a020 292 uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
AnnaBridge 167:84c0a372a020 293 uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
AnnaBridge 167:84c0a372a020 294
AnnaBridge 167:84c0a372a020 295 mpu->RNR = rnrBase;
Anna Bridge 169:a7c7b631e539 296 while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
AnnaBridge 167:84c0a372a020 297 uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
AnnaBridge 167:84c0a372a020 298 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
Anna Bridge 169:a7c7b631e539 299 table += c;
Anna Bridge 169:a7c7b631e539 300 cnt -= c;
Anna Bridge 169:a7c7b631e539 301 rnrOffset = 0U;
Anna Bridge 169:a7c7b631e539 302 rnrBase += MPU_TYPE_RALIASES;
Anna Bridge 169:a7c7b631e539 303 mpu->RNR = rnrBase;
AnnaBridge 167:84c0a372a020 304 }
Anna Bridge 169:a7c7b631e539 305
Anna Bridge 169:a7c7b631e539 306 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
AnnaBridge 167:84c0a372a020 307 }
AnnaBridge 167:84c0a372a020 308 }
AnnaBridge 167:84c0a372a020 309
AnnaBridge 167:84c0a372a020 310 /** Load the given number of MPU regions from a table.
AnnaBridge 167:84c0a372a020 311 * \param rnr First region number to be configured.
AnnaBridge 167:84c0a372a020 312 * \param table Pointer to the MPU configuration table.
AnnaBridge 167:84c0a372a020 313 * \param cnt Amount of regions to be configured.
AnnaBridge 167:84c0a372a020 314 */
AnnaBridge 167:84c0a372a020 315 __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
AnnaBridge 167:84c0a372a020 316 {
AnnaBridge 167:84c0a372a020 317 ARM_MPU_LoadEx(MPU, rnr, table, cnt);
AnnaBridge 167:84c0a372a020 318 }
AnnaBridge 167:84c0a372a020 319
AnnaBridge 167:84c0a372a020 320 #ifdef MPU_NS
AnnaBridge 167:84c0a372a020 321 /** Load the given number of MPU regions from a table to the Non-secure MPU.
AnnaBridge 167:84c0a372a020 322 * \param rnr First region number to be configured.
AnnaBridge 167:84c0a372a020 323 * \param table Pointer to the MPU configuration table.
AnnaBridge 167:84c0a372a020 324 * \param cnt Amount of regions to be configured.
AnnaBridge 167:84c0a372a020 325 */
AnnaBridge 167:84c0a372a020 326 __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
AnnaBridge 167:84c0a372a020 327 {
AnnaBridge 167:84c0a372a020 328 ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
AnnaBridge 167:84c0a372a020 329 }
AnnaBridge 167:84c0a372a020 330 #endif
AnnaBridge 167:84c0a372a020 331
AnnaBridge 167:84c0a372a020 332 #endif
AnnaBridge 167:84c0a372a020 333