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TARGET_B96B_F446VE/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:: Anna Bridge
Date:: Fri Jun 22 15:38:59 2018 +0100
Revision:: 169:a7c7b631e539
Parent:: 163:e59c8e839560

mbed library. Release version 162

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	156:ff21514d8981	1	/**
AnnaBridge	156:ff21514d8981	2	******************************************************************************
AnnaBridge	156:ff21514d8981	3	* @file stm32f4xx_ll_sdmmc.h
AnnaBridge	156:ff21514d8981	4	* @author MCD Application Team
AnnaBridge	156:ff21514d8981	5	* @brief Header file of SDMMC HAL module.
AnnaBridge	156:ff21514d8981	6	******************************************************************************
AnnaBridge	156:ff21514d8981	7	* @attention
AnnaBridge	156:ff21514d8981	8	*
AnnaBridge	156:ff21514d8981	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	156:ff21514d8981	10	*
AnnaBridge	156:ff21514d8981	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	156:ff21514d8981	12	* are permitted provided that the following conditions are met:
AnnaBridge	156:ff21514d8981	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	156:ff21514d8981	14	* this list of conditions and the following disclaimer.
AnnaBridge	156:ff21514d8981	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	156:ff21514d8981	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	156:ff21514d8981	17	* and/or other materials provided with the distribution.
AnnaBridge	156:ff21514d8981	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	156:ff21514d8981	19	* may be used to endorse or promote products derived from this software
AnnaBridge	156:ff21514d8981	20	* without specific prior written permission.
AnnaBridge	156:ff21514d8981	21	*
AnnaBridge	156:ff21514d8981	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	156:ff21514d8981	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	156:ff21514d8981	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	156:ff21514d8981	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	156:ff21514d8981	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	156:ff21514d8981	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	156:ff21514d8981	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	156:ff21514d8981	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	156:ff21514d8981	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	156:ff21514d8981	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	156:ff21514d8981	32	*
AnnaBridge	156:ff21514d8981	33	******************************************************************************
AnnaBridge	156:ff21514d8981	34	*/
AnnaBridge	156:ff21514d8981	35
AnnaBridge	156:ff21514d8981	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	156:ff21514d8981	37	#ifndef __STM32F4xx_LL_SDMMC_H
AnnaBridge	156:ff21514d8981	38	#define __STM32F4xx_LL_SDMMC_H
AnnaBridge	156:ff21514d8981	39
AnnaBridge	156:ff21514d8981	40	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	41	extern "C" {
AnnaBridge	156:ff21514d8981	42	#endif
AnnaBridge	156:ff21514d8981	43
AnnaBridge	156:ff21514d8981	44	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
AnnaBridge	156:ff21514d8981	45	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
AnnaBridge	156:ff21514d8981	46	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
AnnaBridge	156:ff21514d8981	47	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	156:ff21514d8981	48	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	49
AnnaBridge	156:ff21514d8981	50	/* Includes ------------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	51	#include "stm32f4xx_hal_def.h"
AnnaBridge	156:ff21514d8981	52
AnnaBridge	156:ff21514d8981	53	/** @addtogroup STM32F4xx_Driver
AnnaBridge	156:ff21514d8981	54	* @{
AnnaBridge	156:ff21514d8981	55	*/
AnnaBridge	156:ff21514d8981	56
AnnaBridge	156:ff21514d8981	57	/** @addtogroup SDMMC_LL
AnnaBridge	156:ff21514d8981	58	* @{
AnnaBridge	156:ff21514d8981	59	*/
AnnaBridge	156:ff21514d8981	60
AnnaBridge	156:ff21514d8981	61	/* Exported types ------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	62	/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
AnnaBridge	156:ff21514d8981	63	* @{
AnnaBridge	156:ff21514d8981	64	*/
AnnaBridge	156:ff21514d8981	65
AnnaBridge	156:ff21514d8981	66	/**
AnnaBridge	156:ff21514d8981	67	* @brief SDMMC Configuration Structure definition
AnnaBridge	156:ff21514d8981	68	*/
AnnaBridge	156:ff21514d8981	69	typedef struct
AnnaBridge	156:ff21514d8981	70	{
AnnaBridge	156:ff21514d8981	71	uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
AnnaBridge	156:ff21514d8981	72	This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
AnnaBridge	156:ff21514d8981	73
AnnaBridge	156:ff21514d8981	74	uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
AnnaBridge	156:ff21514d8981	75	enabled or disabled.
AnnaBridge	156:ff21514d8981	76	This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
AnnaBridge	156:ff21514d8981	77
AnnaBridge	156:ff21514d8981	78	uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
AnnaBridge	156:ff21514d8981	79	disabled when the bus is idle.
AnnaBridge	156:ff21514d8981	80	This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
AnnaBridge	156:ff21514d8981	81
AnnaBridge	156:ff21514d8981	82	uint32_t BusWide; /*!< Specifies the SDMMC bus width.
AnnaBridge	156:ff21514d8981	83	This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
AnnaBridge	156:ff21514d8981	84
AnnaBridge	156:ff21514d8981	85	uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
AnnaBridge	156:ff21514d8981	86	This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
AnnaBridge	156:ff21514d8981	87
AnnaBridge	156:ff21514d8981	88	uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
AnnaBridge	156:ff21514d8981	89	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	156:ff21514d8981	90
AnnaBridge	156:ff21514d8981	91	}SDIO_InitTypeDef;
AnnaBridge	156:ff21514d8981	92
AnnaBridge	156:ff21514d8981	93
AnnaBridge	156:ff21514d8981	94	/**
AnnaBridge	156:ff21514d8981	95	* @brief SDMMC Command Control structure
AnnaBridge	156:ff21514d8981	96	*/
AnnaBridge	156:ff21514d8981	97	typedef struct
AnnaBridge	156:ff21514d8981	98	{
AnnaBridge	156:ff21514d8981	99	uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
AnnaBridge	156:ff21514d8981	100	to a card as part of a command message. If a command
AnnaBridge	156:ff21514d8981	101	contains an argument, it must be loaded into this register
AnnaBridge	156:ff21514d8981	102	before writing the command to the command register. */
AnnaBridge	156:ff21514d8981	103
AnnaBridge	156:ff21514d8981	104	uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
AnnaBridge	156:ff21514d8981	105	Max_Data = 64 */
AnnaBridge	156:ff21514d8981	106
AnnaBridge	156:ff21514d8981	107	uint32_t Response; /*!< Specifies the SDMMC response type.
AnnaBridge	156:ff21514d8981	108	This parameter can be a value of @ref SDMMC_LL_Response_Type */
AnnaBridge	156:ff21514d8981	109
AnnaBridge	156:ff21514d8981	110	uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
AnnaBridge	156:ff21514d8981	111	enabled or disabled.
AnnaBridge	156:ff21514d8981	112	This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
AnnaBridge	156:ff21514d8981	113
AnnaBridge	156:ff21514d8981	114	uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
AnnaBridge	156:ff21514d8981	115	is enabled or disabled.
AnnaBridge	156:ff21514d8981	116	This parameter can be a value of @ref SDMMC_LL_CPSM_State */
AnnaBridge	156:ff21514d8981	117	}SDIO_CmdInitTypeDef;
AnnaBridge	156:ff21514d8981	118
AnnaBridge	156:ff21514d8981	119
AnnaBridge	156:ff21514d8981	120	/**
AnnaBridge	156:ff21514d8981	121	* @brief SDMMC Data Control structure
AnnaBridge	156:ff21514d8981	122	*/
AnnaBridge	156:ff21514d8981	123	typedef struct
AnnaBridge	156:ff21514d8981	124	{
AnnaBridge	156:ff21514d8981	125	uint32_t DataTimeOut; /!< Specifies the data timeout period in card bus clock periods. /
AnnaBridge	156:ff21514d8981	126
AnnaBridge	156:ff21514d8981	127	uint32_t DataLength; /!< Specifies the number of data bytes to be transferred. /
AnnaBridge	156:ff21514d8981	128
AnnaBridge	156:ff21514d8981	129	uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
AnnaBridge	156:ff21514d8981	130	This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
AnnaBridge	156:ff21514d8981	131
AnnaBridge	156:ff21514d8981	132	uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
AnnaBridge	156:ff21514d8981	133	is a read or write.
AnnaBridge	156:ff21514d8981	134	This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
AnnaBridge	156:ff21514d8981	135
AnnaBridge	156:ff21514d8981	136	uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
AnnaBridge	156:ff21514d8981	137	This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
AnnaBridge	156:ff21514d8981	138
AnnaBridge	156:ff21514d8981	139	uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
AnnaBridge	156:ff21514d8981	140	is enabled or disabled.
AnnaBridge	156:ff21514d8981	141	This parameter can be a value of @ref SDMMC_LL_DPSM_State */
AnnaBridge	156:ff21514d8981	142	}SDIO_DataInitTypeDef;
AnnaBridge	156:ff21514d8981	143
AnnaBridge	156:ff21514d8981	144	/**
AnnaBridge	156:ff21514d8981	145	* @}
AnnaBridge	156:ff21514d8981	146	*/
AnnaBridge	156:ff21514d8981	147
AnnaBridge	156:ff21514d8981	148	/* Exported constants --------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	149	/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
AnnaBridge	156:ff21514d8981	150	* @{
AnnaBridge	156:ff21514d8981	151	*/
AnnaBridge	156:ff21514d8981	152	#define SDMMC_ERROR_NONE 0x00000000U /!< No error /
AnnaBridge	156:ff21514d8981	153	#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /!< Command response received (but CRC check failed) /
AnnaBridge	156:ff21514d8981	154	#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /!< Data block sent/received (CRC check failed) /
AnnaBridge	156:ff21514d8981	155	#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /!< Command response timeout /
AnnaBridge	156:ff21514d8981	156	#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /!< Data timeout /
AnnaBridge	156:ff21514d8981	157	#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /!< Transmit FIFO underrun /
AnnaBridge	156:ff21514d8981	158	#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /!< Receive FIFO overrun /
AnnaBridge	156:ff21514d8981	159	#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /!< Misaligned address /
AnnaBridge	156:ff21514d8981	160	#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the
AnnaBridge	156:ff21514d8981	161	number of transferred bytes does not match the block length */
AnnaBridge	156:ff21514d8981	162	#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /!< An error in the sequence of erase command occurs /
AnnaBridge	156:ff21514d8981	163	#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /!< An invalid selection for erase groups /
AnnaBridge	156:ff21514d8981	164	#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /!< Attempt to program a write protect block /
AnnaBridge	156:ff21514d8981	165	#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock
AnnaBridge	156:ff21514d8981	166	command or if there was an attempt to access a locked card */
AnnaBridge	156:ff21514d8981	167	#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /!< CRC check of the previous command failed /
AnnaBridge	156:ff21514d8981	168	#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /!< Command is not legal for the card state /
AnnaBridge	156:ff21514d8981	169	#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /!< Card internal ECC was applied but failed to correct the data /
AnnaBridge	156:ff21514d8981	170	#define SDMMC_ERROR_CC_ERR 0x00008000U /!< Internal card controller error /
AnnaBridge	156:ff21514d8981	171	#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /!< General or unknown error /
AnnaBridge	156:ff21514d8981	172	#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /!< The card could not sustain data reading in stream rmode /
AnnaBridge	156:ff21514d8981	173	#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /!< The card could not sustain data programming in stream mode /
AnnaBridge	156:ff21514d8981	174	#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /!< CID/CSD overwrite error /
AnnaBridge	156:ff21514d8981	175	#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /!< Only partial address space was erased /
AnnaBridge	156:ff21514d8981	176	#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /!< Command has been executed without using internal ECC /
AnnaBridge	156:ff21514d8981	177	#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out
AnnaBridge	156:ff21514d8981	178	of erase sequence command was received */
AnnaBridge	156:ff21514d8981	179	#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /!< Error in sequence of authentication /
AnnaBridge	156:ff21514d8981	180	#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /!< Error in case of invalid voltage range /
AnnaBridge	156:ff21514d8981	181	#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /!< Error when addressed block is out of range /
AnnaBridge	156:ff21514d8981	182	#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /!< Error when command request is not applicable /
AnnaBridge	156:ff21514d8981	183	#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /!< the used parameter is not valid /
AnnaBridge	156:ff21514d8981	184	#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /!< Error when feature is not insupported /
AnnaBridge	156:ff21514d8981	185	#define SDMMC_ERROR_BUSY 0x20000000U /!< Error when transfer process is busy /
AnnaBridge	156:ff21514d8981	186	#define SDMMC_ERROR_DMA 0x40000000U /!< Error while DMA transfer /
AnnaBridge	156:ff21514d8981	187	#define SDMMC_ERROR_TIMEOUT 0x80000000U /!< Timeout error /
AnnaBridge	156:ff21514d8981	188
AnnaBridge	156:ff21514d8981	189	/**
AnnaBridge	156:ff21514d8981	190	* @brief SDMMC Commands Index
AnnaBridge	156:ff21514d8981	191	*/
AnnaBridge	156:ff21514d8981	192	#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0) /!< Resets the SD memory card. /
AnnaBridge	156:ff21514d8981	193	#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1) /!< Sends host capacity support information and activates the card's initialization process. /
AnnaBridge	156:ff21514d8981	194	#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2) /!< Asks any card connected to the host to send the CID numbers on the CMD line. /
AnnaBridge	156:ff21514d8981	195	#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3) /!< Asks the card to publish a new relative address (RCA). /
AnnaBridge	156:ff21514d8981	196	#define SDMMC_CMD_SET_DSR ((uint8_t)4) /!< Programs the DSR of all cards. /
AnnaBridge	156:ff21514d8981	197	#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
AnnaBridge	156:ff21514d8981	198	operating condition register (OCR) content in the response on the CMD line. */
AnnaBridge	156:ff21514d8981	199	#define SDMMC_CMD_HS_SWITCH ((uint8_t)6) /!< Checks switchable function (mode 0) and switch card function (mode 1). /
AnnaBridge	156:ff21514d8981	200	#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7) /!< Selects the card by its own relative address and gets deselected by any other address /
AnnaBridge	156:ff21514d8981	201	#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
AnnaBridge	156:ff21514d8981	202	and asks the card whether card supports voltage. */
AnnaBridge	156:ff21514d8981	203	#define SDMMC_CMD_SEND_CSD ((uint8_t)9) /!< Addressed card sends its card specific data (CSD) on the CMD line. /
AnnaBridge	156:ff21514d8981	204	#define SDMMC_CMD_SEND_CID ((uint8_t)10) /!< Addressed card sends its card identification (CID) on the CMD line. /
AnnaBridge	156:ff21514d8981	205	#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /!< SD card doesn't support it. /
AnnaBridge	156:ff21514d8981	206	#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12) /!< Forces the card to stop transmission. /
AnnaBridge	156:ff21514d8981	207	#define SDMMC_CMD_SEND_STATUS ((uint8_t)13) /!< Addressed card sends its status register. /
AnnaBridge	156:ff21514d8981	208	#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14) /!< Reserved /
AnnaBridge	156:ff21514d8981	209	#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15) /!< Sends an addressed card into the inactive state. /
AnnaBridge	156:ff21514d8981	210	#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands
AnnaBridge	156:ff21514d8981	211	(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
AnnaBridge	156:ff21514d8981	212	for SDHS and SDXC. */
AnnaBridge	156:ff21514d8981	213	#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
AnnaBridge	156:ff21514d8981	214	fixed 512 bytes in case of SDHC and SDXC. */
AnnaBridge	156:ff21514d8981	215	#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by
AnnaBridge	156:ff21514d8981	216	STOP_TRANSMISSION command. */
AnnaBridge	156:ff21514d8981	217	#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /!< 64 bytes tuning pattern is sent for SDR50 and SDR104. /
AnnaBridge	156:ff21514d8981	218	#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /!< Speed class control command. /
AnnaBridge	156:ff21514d8981	219	#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23) /!< Specify block count for CMD18 and CMD25. /
AnnaBridge	156:ff21514d8981	220	#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
AnnaBridge	156:ff21514d8981	221	fixed 512 bytes in case of SDHC and SDXC. */
AnnaBridge	156:ff21514d8981	222	#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. /
AnnaBridge	156:ff21514d8981	223	#define SDMMC_CMD_PROG_CID ((uint8_t)26) /!< Reserved for manufacturers. /
AnnaBridge	156:ff21514d8981	224	#define SDMMC_CMD_PROG_CSD ((uint8_t)27) /!< Programming of the programmable bits of the CSD. /
AnnaBridge	156:ff21514d8981	225	#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28) /!< Sets the write protection bit of the addressed group. /
AnnaBridge	156:ff21514d8981	226	#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29) /!< Clears the write protection bit of the addressed group. /
AnnaBridge	156:ff21514d8981	227	#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30) /!< Asks the card to send the status of the write protection bits. /
AnnaBridge	156:ff21514d8981	228	#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32) /!< Sets the address of the first write block to be erased. (For SD card only). /
AnnaBridge	156:ff21514d8981	229	#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33) /!< Sets the address of the last write block of the continuous range to be erased. /
AnnaBridge	156:ff21514d8981	230	#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command
AnnaBridge	156:ff21514d8981	231	system set by switch function command (CMD6). */
AnnaBridge	156:ff21514d8981	232	#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased.
AnnaBridge	156:ff21514d8981	233	Reserved for each command system set by switch function command (CMD6). */
AnnaBridge	156:ff21514d8981	234	#define SDMMC_CMD_ERASE ((uint8_t)38) /!< Reserved for SD security applications. /
AnnaBridge	156:ff21514d8981	235	#define SDMMC_CMD_FAST_IO ((uint8_t)39) /!< SD card doesn't support it (Reserved). /
AnnaBridge	156:ff21514d8981	236	#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40) /!< SD card doesn't support it (Reserved). /
AnnaBridge	156:ff21514d8981	237	#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
AnnaBridge	156:ff21514d8981	238	the SET_BLOCK_LEN command. */
AnnaBridge	156:ff21514d8981	239	#define SDMMC_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather
AnnaBridge	156:ff21514d8981	240	than a standard command. */
AnnaBridge	156:ff21514d8981	241	#define SDMMC_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card
AnnaBridge	156:ff21514d8981	242	for general purpose/application specific commands. */
AnnaBridge	156:ff21514d8981	243	#define SDMMC_CMD_NO_CMD ((uint8_t)64) /!< No command /
AnnaBridge	156:ff21514d8981	244
AnnaBridge	156:ff21514d8981	245	/**
AnnaBridge	156:ff21514d8981	246	* @brief Following commands are SD Card Specific commands.
AnnaBridge	156:ff21514d8981	247	* SDMMC_APP_CMD should be sent before sending these commands.
AnnaBridge	156:ff21514d8981	248	*/
AnnaBridge	156:ff21514d8981	249	#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
AnnaBridge	156:ff21514d8981	250	widths are given in SCR register. */
AnnaBridge	156:ff21514d8981	251	#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13) /!< (ACMD13) Sends the SD status. /
AnnaBridge	156:ff21514d8981	252	#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
AnnaBridge	156:ff21514d8981	253	32bit+CRC data block. */
AnnaBridge	156:ff21514d8981	254	#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
AnnaBridge	156:ff21514d8981	255	send its operating condition register (OCR) content in the response on the CMD line. */
AnnaBridge	156:ff21514d8981	256	#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card /
AnnaBridge	156:ff21514d8981	257	#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51) /!< Reads the SD Configuration Register (SCR). /
AnnaBridge	156:ff21514d8981	258	#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52) /!< For SD I/O card only, reserved for security specification. /
AnnaBridge	156:ff21514d8981	259	#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53) /!< For SD I/O card only, reserved for security specification. /
AnnaBridge	156:ff21514d8981	260
AnnaBridge	156:ff21514d8981	261	/**
AnnaBridge	156:ff21514d8981	262	* @brief Following commands are SD Card Specific security commands.
AnnaBridge	156:ff21514d8981	263	* SDMMC_CMD_APP_CMD should be sent before sending these commands.
AnnaBridge	156:ff21514d8981	264	*/
AnnaBridge	156:ff21514d8981	265	#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43)
AnnaBridge	156:ff21514d8981	266	#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44)
AnnaBridge	156:ff21514d8981	267	#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45)
AnnaBridge	156:ff21514d8981	268	#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46)
AnnaBridge	156:ff21514d8981	269	#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47)
AnnaBridge	156:ff21514d8981	270	#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48)
AnnaBridge	156:ff21514d8981	271	#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18)
AnnaBridge	156:ff21514d8981	272	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25)
AnnaBridge	156:ff21514d8981	273	#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38)
AnnaBridge	156:ff21514d8981	274	#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49)
AnnaBridge	156:ff21514d8981	275	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48)
AnnaBridge	156:ff21514d8981	276
AnnaBridge	156:ff21514d8981	277	/**
AnnaBridge	156:ff21514d8981	278	* @brief Masks for errors Card Status R1 (OCR Register)
AnnaBridge	156:ff21514d8981	279	*/
AnnaBridge	156:ff21514d8981	280	#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U
AnnaBridge	156:ff21514d8981	281	#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U
AnnaBridge	156:ff21514d8981	282	#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U
AnnaBridge	156:ff21514d8981	283	#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U
AnnaBridge	156:ff21514d8981	284	#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U
AnnaBridge	156:ff21514d8981	285	#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U
AnnaBridge	156:ff21514d8981	286	#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U
AnnaBridge	156:ff21514d8981	287	#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U
AnnaBridge	156:ff21514d8981	288	#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U
AnnaBridge	156:ff21514d8981	289	#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U
AnnaBridge	156:ff21514d8981	290	#define SDMMC_OCR_CC_ERROR 0x00100000U
AnnaBridge	156:ff21514d8981	291	#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U
AnnaBridge	156:ff21514d8981	292	#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U
AnnaBridge	156:ff21514d8981	293	#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U
AnnaBridge	156:ff21514d8981	294	#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U
AnnaBridge	156:ff21514d8981	295	#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U
AnnaBridge	156:ff21514d8981	296	#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U
AnnaBridge	156:ff21514d8981	297	#define SDMMC_OCR_ERASE_RESET 0x00002000U
AnnaBridge	156:ff21514d8981	298	#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U
AnnaBridge	156:ff21514d8981	299	#define SDMMC_OCR_ERRORBITS 0xFDFFE008U
AnnaBridge	156:ff21514d8981	300
AnnaBridge	156:ff21514d8981	301	/**
AnnaBridge	156:ff21514d8981	302	* @brief Masks for R6 Response
AnnaBridge	156:ff21514d8981	303	*/
AnnaBridge	156:ff21514d8981	304	#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U
AnnaBridge	156:ff21514d8981	305	#define SDMMC_R6_ILLEGAL_CMD 0x00004000U
AnnaBridge	156:ff21514d8981	306	#define SDMMC_R6_COM_CRC_FAILED 0x00008000U
AnnaBridge	156:ff21514d8981	307
AnnaBridge	156:ff21514d8981	308	#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U
AnnaBridge	156:ff21514d8981	309	#define SDMMC_HIGH_CAPACITY 0x40000000U
AnnaBridge	156:ff21514d8981	310	#define SDMMC_STD_CAPACITY 0x00000000U
AnnaBridge	156:ff21514d8981	311	#define SDMMC_CHECK_PATTERN 0x000001AAU
AnnaBridge	156:ff21514d8981	312
AnnaBridge	156:ff21514d8981	313	#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU
AnnaBridge	156:ff21514d8981	314
AnnaBridge	156:ff21514d8981	315	#define SDMMC_MAX_TRIAL 0x0000FFFFU
AnnaBridge	156:ff21514d8981	316
AnnaBridge	156:ff21514d8981	317	#define SDMMC_ALLZERO 0x00000000U
AnnaBridge	156:ff21514d8981	318
AnnaBridge	156:ff21514d8981	319	#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U
AnnaBridge	156:ff21514d8981	320	#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
AnnaBridge	156:ff21514d8981	321	#define SDMMC_CARD_LOCKED 0x02000000U
AnnaBridge	156:ff21514d8981	322
AnnaBridge	156:ff21514d8981	323	#define SDMMC_DATATIMEOUT 0xFFFFFFFFU
AnnaBridge	156:ff21514d8981	324
AnnaBridge	156:ff21514d8981	325	#define SDMMC_0TO7BITS 0x000000FFU
AnnaBridge	156:ff21514d8981	326	#define SDMMC_8TO15BITS 0x0000FF00U
AnnaBridge	156:ff21514d8981	327	#define SDMMC_16TO23BITS 0x00FF0000U
AnnaBridge	156:ff21514d8981	328	#define SDMMC_24TO31BITS 0xFF000000U
AnnaBridge	156:ff21514d8981	329	#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU
AnnaBridge	156:ff21514d8981	330
AnnaBridge	156:ff21514d8981	331	#define SDMMC_HALFFIFO 0x00000008U
AnnaBridge	156:ff21514d8981	332	#define SDMMC_HALFFIFOBYTES 0x00000020U
AnnaBridge	156:ff21514d8981	333
AnnaBridge	156:ff21514d8981	334	/**
AnnaBridge	156:ff21514d8981	335	* @brief Command Class supported
AnnaBridge	156:ff21514d8981	336	*/
AnnaBridge	156:ff21514d8981	337	#define SDIO_CCCC_ERASE 0x00000020U
AnnaBridge	156:ff21514d8981	338
AnnaBridge	156:ff21514d8981	339	#define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */
AnnaBridge	156:ff21514d8981	340	#define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */
AnnaBridge	156:ff21514d8981	341
AnnaBridge	156:ff21514d8981	342
AnnaBridge	156:ff21514d8981	343	/** @defgroup SDIO_LL_Clock_Edge Clock Edge
AnnaBridge	156:ff21514d8981	344	* @{
AnnaBridge	156:ff21514d8981	345	*/
AnnaBridge	156:ff21514d8981	346	#define SDIO_CLOCK_EDGE_RISING 0x00000000U
AnnaBridge	156:ff21514d8981	347	#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
AnnaBridge	156:ff21514d8981	348
AnnaBridge	156:ff21514d8981	349	#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) \|\| \
AnnaBridge	156:ff21514d8981	350	((EDGE) == SDIO_CLOCK_EDGE_FALLING))
AnnaBridge	156:ff21514d8981	351	/**
AnnaBridge	156:ff21514d8981	352	* @}
AnnaBridge	156:ff21514d8981	353	*/
AnnaBridge	156:ff21514d8981	354
AnnaBridge	156:ff21514d8981	355	/** @defgroup SDIO_LL_Clock_Bypass Clock Bypass
AnnaBridge	156:ff21514d8981	356	* @{
AnnaBridge	156:ff21514d8981	357	*/
AnnaBridge	156:ff21514d8981	358	#define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	359	#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
AnnaBridge	156:ff21514d8981	360
AnnaBridge	156:ff21514d8981	361	#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	362	((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
AnnaBridge	156:ff21514d8981	363	/**
AnnaBridge	156:ff21514d8981	364	* @}
AnnaBridge	156:ff21514d8981	365	*/
AnnaBridge	156:ff21514d8981	366
AnnaBridge	156:ff21514d8981	367	/** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving
AnnaBridge	156:ff21514d8981	368	* @{
AnnaBridge	156:ff21514d8981	369	*/
AnnaBridge	156:ff21514d8981	370	#define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	371	#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
AnnaBridge	156:ff21514d8981	372
AnnaBridge	156:ff21514d8981	373	#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	374	((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
AnnaBridge	156:ff21514d8981	375	/**
AnnaBridge	156:ff21514d8981	376	* @}
AnnaBridge	156:ff21514d8981	377	*/
AnnaBridge	156:ff21514d8981	378
AnnaBridge	156:ff21514d8981	379	/** @defgroup SDIO_LL_Bus_Wide Bus Width
AnnaBridge	156:ff21514d8981	380	* @{
AnnaBridge	156:ff21514d8981	381	*/
AnnaBridge	156:ff21514d8981	382	#define SDIO_BUS_WIDE_1B 0x00000000U
AnnaBridge	156:ff21514d8981	383	#define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
AnnaBridge	156:ff21514d8981	384	#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
AnnaBridge	156:ff21514d8981	385
AnnaBridge	156:ff21514d8981	386	#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) \|\| \
AnnaBridge	156:ff21514d8981	387	((WIDE) == SDIO_BUS_WIDE_4B) \|\| \
AnnaBridge	156:ff21514d8981	388	((WIDE) == SDIO_BUS_WIDE_8B))
AnnaBridge	156:ff21514d8981	389	/**
AnnaBridge	156:ff21514d8981	390	* @}
AnnaBridge	156:ff21514d8981	391	*/
AnnaBridge	156:ff21514d8981	392
AnnaBridge	156:ff21514d8981	393	/** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control
AnnaBridge	156:ff21514d8981	394	* @{
AnnaBridge	156:ff21514d8981	395	*/
AnnaBridge	156:ff21514d8981	396	#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	397	#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
AnnaBridge	156:ff21514d8981	398
AnnaBridge	156:ff21514d8981	399	#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	400	((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
AnnaBridge	156:ff21514d8981	401	/**
AnnaBridge	156:ff21514d8981	402	* @}
AnnaBridge	156:ff21514d8981	403	*/
AnnaBridge	156:ff21514d8981	404
AnnaBridge	156:ff21514d8981	405	/** @defgroup SDIO_LL_Clock_Division Clock Division
AnnaBridge	156:ff21514d8981	406	* @{
AnnaBridge	156:ff21514d8981	407	*/
AnnaBridge	156:ff21514d8981	408	#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU)
AnnaBridge	156:ff21514d8981	409	/**
AnnaBridge	156:ff21514d8981	410	* @}
AnnaBridge	156:ff21514d8981	411	*/
AnnaBridge	156:ff21514d8981	412
AnnaBridge	156:ff21514d8981	413	/** @defgroup SDIO_LL_Command_Index Command Index
AnnaBridge	156:ff21514d8981	414	* @{
AnnaBridge	156:ff21514d8981	415	*/
AnnaBridge	156:ff21514d8981	416	#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
AnnaBridge	156:ff21514d8981	417	/**
AnnaBridge	156:ff21514d8981	418	* @}
AnnaBridge	156:ff21514d8981	419	*/
AnnaBridge	156:ff21514d8981	420
AnnaBridge	156:ff21514d8981	421	/** @defgroup SDIO_LL_Response_Type Response Type
AnnaBridge	156:ff21514d8981	422	* @{
AnnaBridge	156:ff21514d8981	423	*/
AnnaBridge	156:ff21514d8981	424	#define SDIO_RESPONSE_NO 0x00000000U
AnnaBridge	156:ff21514d8981	425	#define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
AnnaBridge	156:ff21514d8981	426	#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
AnnaBridge	156:ff21514d8981	427
AnnaBridge	156:ff21514d8981	428	#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) \|\| \
AnnaBridge	156:ff21514d8981	429	((RESPONSE) == SDIO_RESPONSE_SHORT) \|\| \
AnnaBridge	156:ff21514d8981	430	((RESPONSE) == SDIO_RESPONSE_LONG))
AnnaBridge	156:ff21514d8981	431	/**
AnnaBridge	156:ff21514d8981	432	* @}
AnnaBridge	156:ff21514d8981	433	*/
AnnaBridge	156:ff21514d8981	434
AnnaBridge	156:ff21514d8981	435	/** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt
AnnaBridge	156:ff21514d8981	436	* @{
AnnaBridge	156:ff21514d8981	437	*/
AnnaBridge	156:ff21514d8981	438	#define SDIO_WAIT_NO 0x00000000U
AnnaBridge	156:ff21514d8981	439	#define SDIO_WAIT_IT SDIO_CMD_WAITINT
AnnaBridge	156:ff21514d8981	440	#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
AnnaBridge	156:ff21514d8981	441
AnnaBridge	156:ff21514d8981	442	#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) \|\| \
AnnaBridge	156:ff21514d8981	443	((WAIT) == SDIO_WAIT_IT) \|\| \
AnnaBridge	156:ff21514d8981	444	((WAIT) == SDIO_WAIT_PEND))
AnnaBridge	156:ff21514d8981	445	/**
AnnaBridge	156:ff21514d8981	446	* @}
AnnaBridge	156:ff21514d8981	447	*/
AnnaBridge	156:ff21514d8981	448
AnnaBridge	156:ff21514d8981	449	/** @defgroup SDIO_LL_CPSM_State CPSM State
AnnaBridge	156:ff21514d8981	450	* @{
AnnaBridge	156:ff21514d8981	451	*/
AnnaBridge	156:ff21514d8981	452	#define SDIO_CPSM_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	453	#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
AnnaBridge	156:ff21514d8981	454
AnnaBridge	156:ff21514d8981	455	#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) \|\| \
AnnaBridge	156:ff21514d8981	456	((CPSM) == SDIO_CPSM_ENABLE))
AnnaBridge	156:ff21514d8981	457	/**
AnnaBridge	156:ff21514d8981	458	* @}
AnnaBridge	156:ff21514d8981	459	*/
AnnaBridge	156:ff21514d8981	460
AnnaBridge	156:ff21514d8981	461	/** @defgroup SDIO_LL_Response_Registers Response Register
AnnaBridge	156:ff21514d8981	462	* @{
AnnaBridge	156:ff21514d8981	463	*/
AnnaBridge	156:ff21514d8981	464	#define SDIO_RESP1 0x00000000U
AnnaBridge	156:ff21514d8981	465	#define SDIO_RESP2 0x00000004U
AnnaBridge	156:ff21514d8981	466	#define SDIO_RESP3 0x00000008U
AnnaBridge	156:ff21514d8981	467	#define SDIO_RESP4 0x0000000CU
AnnaBridge	156:ff21514d8981	468
AnnaBridge	156:ff21514d8981	469	#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) \|\| \
AnnaBridge	156:ff21514d8981	470	((RESP) == SDIO_RESP2) \|\| \
AnnaBridge	156:ff21514d8981	471	((RESP) == SDIO_RESP3) \|\| \
AnnaBridge	156:ff21514d8981	472	((RESP) == SDIO_RESP4))
AnnaBridge	156:ff21514d8981	473	/**
AnnaBridge	156:ff21514d8981	474	* @}
AnnaBridge	156:ff21514d8981	475	*/
AnnaBridge	156:ff21514d8981	476
AnnaBridge	156:ff21514d8981	477	/** @defgroup SDIO_LL_Data_Length Data Lenght
AnnaBridge	156:ff21514d8981	478	* @{
AnnaBridge	156:ff21514d8981	479	*/
AnnaBridge	156:ff21514d8981	480	#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
AnnaBridge	156:ff21514d8981	481	/**
AnnaBridge	156:ff21514d8981	482	* @}
AnnaBridge	156:ff21514d8981	483	*/
AnnaBridge	156:ff21514d8981	484
AnnaBridge	156:ff21514d8981	485	/** @defgroup SDIO_LL_Data_Block_Size Data Block Size
AnnaBridge	156:ff21514d8981	486	* @{
AnnaBridge	156:ff21514d8981	487	*/
AnnaBridge	156:ff21514d8981	488	#define SDIO_DATABLOCK_SIZE_1B 0x00000000U
AnnaBridge	156:ff21514d8981	489	#define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
AnnaBridge	156:ff21514d8981	490	#define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
AnnaBridge	156:ff21514d8981	491	#define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_1)
AnnaBridge	156:ff21514d8981	492	#define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
AnnaBridge	156:ff21514d8981	493	#define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_2)
AnnaBridge	156:ff21514d8981	494	#define SDIO_DATABLOCK_SIZE_64B (SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_2)
AnnaBridge	156:ff21514d8981	495	#define SDIO_DATABLOCK_SIZE_128B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_2)
AnnaBridge	156:ff21514d8981	496	#define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
AnnaBridge	156:ff21514d8981	497	#define SDIO_DATABLOCK_SIZE_512B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_3)
AnnaBridge	156:ff21514d8981	498	#define SDIO_DATABLOCK_SIZE_1024B (SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_3)
AnnaBridge	156:ff21514d8981	499	#define SDIO_DATABLOCK_SIZE_2048B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_3)
AnnaBridge	156:ff21514d8981	500	#define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2\|SDIO_DCTRL_DBLOCKSIZE_3)
AnnaBridge	156:ff21514d8981	501	#define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_2\|SDIO_DCTRL_DBLOCKSIZE_3)
AnnaBridge	156:ff21514d8981	502	#define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_2\|SDIO_DCTRL_DBLOCKSIZE_3)
AnnaBridge	156:ff21514d8981	503
AnnaBridge	156:ff21514d8981	504	#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) \|\| \
AnnaBridge	156:ff21514d8981	505	((SIZE) == SDIO_DATABLOCK_SIZE_2B) \|\| \
AnnaBridge	156:ff21514d8981	506	((SIZE) == SDIO_DATABLOCK_SIZE_4B) \|\| \
AnnaBridge	156:ff21514d8981	507	((SIZE) == SDIO_DATABLOCK_SIZE_8B) \|\| \
AnnaBridge	156:ff21514d8981	508	((SIZE) == SDIO_DATABLOCK_SIZE_16B) \|\| \
AnnaBridge	156:ff21514d8981	509	((SIZE) == SDIO_DATABLOCK_SIZE_32B) \|\| \
AnnaBridge	156:ff21514d8981	510	((SIZE) == SDIO_DATABLOCK_SIZE_64B) \|\| \
AnnaBridge	156:ff21514d8981	511	((SIZE) == SDIO_DATABLOCK_SIZE_128B) \|\| \
AnnaBridge	156:ff21514d8981	512	((SIZE) == SDIO_DATABLOCK_SIZE_256B) \|\| \
AnnaBridge	156:ff21514d8981	513	((SIZE) == SDIO_DATABLOCK_SIZE_512B) \|\| \
AnnaBridge	156:ff21514d8981	514	((SIZE) == SDIO_DATABLOCK_SIZE_1024B) \|\| \
AnnaBridge	156:ff21514d8981	515	((SIZE) == SDIO_DATABLOCK_SIZE_2048B) \|\| \
AnnaBridge	156:ff21514d8981	516	((SIZE) == SDIO_DATABLOCK_SIZE_4096B) \|\| \
AnnaBridge	156:ff21514d8981	517	((SIZE) == SDIO_DATABLOCK_SIZE_8192B) \|\| \
AnnaBridge	156:ff21514d8981	518	((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
AnnaBridge	156:ff21514d8981	519	/**
AnnaBridge	156:ff21514d8981	520	* @}
AnnaBridge	156:ff21514d8981	521	*/
AnnaBridge	156:ff21514d8981	522
AnnaBridge	156:ff21514d8981	523	/** @defgroup SDIO_LL_Transfer_Direction Transfer Direction
AnnaBridge	156:ff21514d8981	524	* @{
AnnaBridge	156:ff21514d8981	525	*/
AnnaBridge	156:ff21514d8981	526	#define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U
AnnaBridge	156:ff21514d8981	527	#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
AnnaBridge	156:ff21514d8981	528
AnnaBridge	156:ff21514d8981	529	#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) \|\| \
AnnaBridge	156:ff21514d8981	530	((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
AnnaBridge	156:ff21514d8981	531	/**
AnnaBridge	156:ff21514d8981	532	* @}
AnnaBridge	156:ff21514d8981	533	*/
AnnaBridge	156:ff21514d8981	534
AnnaBridge	156:ff21514d8981	535	/** @defgroup SDIO_LL_Transfer_Type Transfer Type
AnnaBridge	156:ff21514d8981	536	* @{
AnnaBridge	156:ff21514d8981	537	*/
AnnaBridge	156:ff21514d8981	538	#define SDIO_TRANSFER_MODE_BLOCK 0x00000000U
AnnaBridge	156:ff21514d8981	539	#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
AnnaBridge	156:ff21514d8981	540
AnnaBridge	156:ff21514d8981	541	#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) \|\| \
AnnaBridge	156:ff21514d8981	542	((MODE) == SDIO_TRANSFER_MODE_STREAM))
AnnaBridge	156:ff21514d8981	543	/**
AnnaBridge	156:ff21514d8981	544	* @}
AnnaBridge	156:ff21514d8981	545	*/
AnnaBridge	156:ff21514d8981	546
AnnaBridge	156:ff21514d8981	547	/** @defgroup SDIO_LL_DPSM_State DPSM State
AnnaBridge	156:ff21514d8981	548	* @{
AnnaBridge	156:ff21514d8981	549	*/
AnnaBridge	156:ff21514d8981	550	#define SDIO_DPSM_DISABLE 0x00000000U
AnnaBridge	156:ff21514d8981	551	#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
AnnaBridge	156:ff21514d8981	552
AnnaBridge	156:ff21514d8981	553	#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) \|\|\
AnnaBridge	156:ff21514d8981	554	((DPSM) == SDIO_DPSM_ENABLE))
AnnaBridge	156:ff21514d8981	555	/**
AnnaBridge	156:ff21514d8981	556	* @}
AnnaBridge	156:ff21514d8981	557	*/
AnnaBridge	156:ff21514d8981	558
AnnaBridge	156:ff21514d8981	559	/** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode
AnnaBridge	156:ff21514d8981	560	* @{
AnnaBridge	156:ff21514d8981	561	*/
AnnaBridge	156:ff21514d8981	562	#define SDIO_READ_WAIT_MODE_DATA2 0x00000000U
AnnaBridge	156:ff21514d8981	563	#define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD)
AnnaBridge	156:ff21514d8981	564
AnnaBridge	156:ff21514d8981	565	#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) \|\| \
AnnaBridge	156:ff21514d8981	566	((MODE) == SDIO_READ_WAIT_MODE_DATA2))
AnnaBridge	156:ff21514d8981	567	/**
AnnaBridge	156:ff21514d8981	568	* @}
AnnaBridge	156:ff21514d8981	569	*/
AnnaBridge	156:ff21514d8981	570
AnnaBridge	156:ff21514d8981	571	/** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources
AnnaBridge	156:ff21514d8981	572	* @{
AnnaBridge	156:ff21514d8981	573	*/
AnnaBridge	156:ff21514d8981	574	#define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
AnnaBridge	156:ff21514d8981	575	#define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
AnnaBridge	156:ff21514d8981	576	#define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
AnnaBridge	156:ff21514d8981	577	#define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
AnnaBridge	156:ff21514d8981	578	#define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
AnnaBridge	156:ff21514d8981	579	#define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
AnnaBridge	156:ff21514d8981	580	#define SDIO_IT_CMDREND SDIO_STA_CMDREND
AnnaBridge	156:ff21514d8981	581	#define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
AnnaBridge	156:ff21514d8981	582	#define SDIO_IT_DATAEND SDIO_STA_DATAEND
AnnaBridge	156:ff21514d8981	583	#define SDIO_IT_STBITERR SDIO_STA_STBITERR
AnnaBridge	156:ff21514d8981	584	#define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
AnnaBridge	156:ff21514d8981	585	#define SDIO_IT_CMDACT SDIO_STA_CMDACT
AnnaBridge	156:ff21514d8981	586	#define SDIO_IT_TXACT SDIO_STA_TXACT
AnnaBridge	156:ff21514d8981	587	#define SDIO_IT_RXACT SDIO_STA_RXACT
AnnaBridge	156:ff21514d8981	588	#define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
AnnaBridge	156:ff21514d8981	589	#define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
AnnaBridge	156:ff21514d8981	590	#define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
AnnaBridge	156:ff21514d8981	591	#define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
AnnaBridge	156:ff21514d8981	592	#define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
AnnaBridge	156:ff21514d8981	593	#define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
AnnaBridge	156:ff21514d8981	594	#define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
AnnaBridge	156:ff21514d8981	595	#define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
AnnaBridge	156:ff21514d8981	596	#define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
AnnaBridge	156:ff21514d8981	597	#define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
AnnaBridge	156:ff21514d8981	598	/**
AnnaBridge	156:ff21514d8981	599	* @}
AnnaBridge	156:ff21514d8981	600	*/
AnnaBridge	156:ff21514d8981	601
AnnaBridge	156:ff21514d8981	602	/** @defgroup SDIO_LL_Flags Flags
AnnaBridge	156:ff21514d8981	603	* @{
AnnaBridge	156:ff21514d8981	604	*/
AnnaBridge	156:ff21514d8981	605	#define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
AnnaBridge	156:ff21514d8981	606	#define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
AnnaBridge	156:ff21514d8981	607	#define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
AnnaBridge	156:ff21514d8981	608	#define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
AnnaBridge	156:ff21514d8981	609	#define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
AnnaBridge	156:ff21514d8981	610	#define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
AnnaBridge	156:ff21514d8981	611	#define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
AnnaBridge	156:ff21514d8981	612	#define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
AnnaBridge	156:ff21514d8981	613	#define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
AnnaBridge	156:ff21514d8981	614	#define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
AnnaBridge	156:ff21514d8981	615	#define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
AnnaBridge	156:ff21514d8981	616	#define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
AnnaBridge	156:ff21514d8981	617	#define SDIO_FLAG_TXACT SDIO_STA_TXACT
AnnaBridge	156:ff21514d8981	618	#define SDIO_FLAG_RXACT SDIO_STA_RXACT
AnnaBridge	156:ff21514d8981	619	#define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
AnnaBridge	156:ff21514d8981	620	#define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
AnnaBridge	156:ff21514d8981	621	#define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
AnnaBridge	156:ff21514d8981	622	#define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
AnnaBridge	156:ff21514d8981	623	#define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
AnnaBridge	156:ff21514d8981	624	#define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
AnnaBridge	156:ff21514d8981	625	#define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
AnnaBridge	156:ff21514d8981	626	#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
AnnaBridge	156:ff21514d8981	627	#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
AnnaBridge	156:ff21514d8981	628	#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
AnnaBridge	156:ff21514d8981	629	#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL \| SDIO_FLAG_DCRCFAIL \| SDIO_FLAG_CTIMEOUT \|\
AnnaBridge	156:ff21514d8981	630	SDIO_FLAG_DTIMEOUT \| SDIO_FLAG_TXUNDERR \| SDIO_FLAG_RXOVERR \|\
AnnaBridge	156:ff21514d8981	631	SDIO_FLAG_CMDREND \| SDIO_FLAG_CMDSENT \| SDIO_FLAG_DATAEND \|\
AnnaBridge	156:ff21514d8981	632	SDIO_FLAG_DBCKEND))
AnnaBridge	156:ff21514d8981	633	/**
AnnaBridge	156:ff21514d8981	634	* @}
AnnaBridge	156:ff21514d8981	635	*/
AnnaBridge	156:ff21514d8981	636
AnnaBridge	156:ff21514d8981	637	/**
AnnaBridge	156:ff21514d8981	638	* @}
AnnaBridge	156:ff21514d8981	639	*/
AnnaBridge	156:ff21514d8981	640
AnnaBridge	156:ff21514d8981	641	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	642	/** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros
AnnaBridge	156:ff21514d8981	643	* @{
AnnaBridge	156:ff21514d8981	644	*/
AnnaBridge	156:ff21514d8981	645
AnnaBridge	156:ff21514d8981	646	/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
AnnaBridge	156:ff21514d8981	647	* @{
AnnaBridge	156:ff21514d8981	648	*/
AnnaBridge	156:ff21514d8981	649	/* ------------ SDIO registers bit address in the alias region -------------- */
AnnaBridge	156:ff21514d8981	650	#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
AnnaBridge	156:ff21514d8981	651
AnnaBridge	156:ff21514d8981	652	/* --- CLKCR Register ---*/
AnnaBridge	156:ff21514d8981	653	/* Alias word address of CLKEN bit */
AnnaBridge	156:ff21514d8981	654	#define CLKCR_OFFSET (SDIO_OFFSET + 0x04U)
AnnaBridge	156:ff21514d8981	655	#define CLKEN_BITNUMBER 0x08U
AnnaBridge	156:ff21514d8981	656	#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
AnnaBridge	156:ff21514d8981	657
AnnaBridge	156:ff21514d8981	658	/* --- CMD Register ---*/
AnnaBridge	156:ff21514d8981	659	/* Alias word address of SDIOSUSPEND bit */
AnnaBridge	156:ff21514d8981	660	#define CMD_OFFSET (SDIO_OFFSET + 0x0CU)
AnnaBridge	156:ff21514d8981	661	#define SDIOSUSPEND_BITNUMBER 0x0BU
AnnaBridge	156:ff21514d8981	662	#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
AnnaBridge	156:ff21514d8981	663
AnnaBridge	156:ff21514d8981	664	/* Alias word address of ENCMDCOMPL bit */
AnnaBridge	156:ff21514d8981	665	#define ENCMDCOMPL_BITNUMBER 0x0CU
AnnaBridge	156:ff21514d8981	666	#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
AnnaBridge	156:ff21514d8981	667
AnnaBridge	156:ff21514d8981	668	/* Alias word address of NIEN bit */
AnnaBridge	156:ff21514d8981	669	#define NIEN_BITNUMBER 0x0DU
AnnaBridge	156:ff21514d8981	670	#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
AnnaBridge	156:ff21514d8981	671
AnnaBridge	156:ff21514d8981	672	/* Alias word address of ATACMD bit */
AnnaBridge	156:ff21514d8981	673	#define ATACMD_BITNUMBER 0x0EU
AnnaBridge	156:ff21514d8981	674	#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
AnnaBridge	156:ff21514d8981	675
AnnaBridge	156:ff21514d8981	676	/* --- DCTRL Register ---*/
AnnaBridge	156:ff21514d8981	677	/* Alias word address of DMAEN bit */
AnnaBridge	156:ff21514d8981	678	#define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU)
AnnaBridge	156:ff21514d8981	679	#define DMAEN_BITNUMBER 0x03U
AnnaBridge	156:ff21514d8981	680	#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
AnnaBridge	156:ff21514d8981	681
AnnaBridge	156:ff21514d8981	682	/* Alias word address of RWSTART bit */
AnnaBridge	156:ff21514d8981	683	#define RWSTART_BITNUMBER 0x08U
AnnaBridge	156:ff21514d8981	684	#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
AnnaBridge	156:ff21514d8981	685
AnnaBridge	156:ff21514d8981	686	/* Alias word address of RWSTOP bit */
AnnaBridge	156:ff21514d8981	687	#define RWSTOP_BITNUMBER 0x09U
AnnaBridge	156:ff21514d8981	688	#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
AnnaBridge	156:ff21514d8981	689
AnnaBridge	156:ff21514d8981	690	/* Alias word address of RWMOD bit */
AnnaBridge	156:ff21514d8981	691	#define RWMOD_BITNUMBER 0x0AU
AnnaBridge	156:ff21514d8981	692	#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
AnnaBridge	156:ff21514d8981	693
AnnaBridge	156:ff21514d8981	694	/* Alias word address of SDIOEN bit */
AnnaBridge	156:ff21514d8981	695	#define SDIOEN_BITNUMBER 0x0BU
AnnaBridge	156:ff21514d8981	696	#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
AnnaBridge	156:ff21514d8981	697	/**
AnnaBridge	156:ff21514d8981	698	* @}
AnnaBridge	156:ff21514d8981	699	*/
AnnaBridge	156:ff21514d8981	700
AnnaBridge	156:ff21514d8981	701	/** @defgroup SDIO_LL_Register Bits And Addresses Definitions
AnnaBridge	156:ff21514d8981	702	* @brief SDIO_LL registers bit address in the alias region
AnnaBridge	156:ff21514d8981	703	* @{
AnnaBridge	156:ff21514d8981	704	*/
AnnaBridge	156:ff21514d8981	705	/* ---------------------- SDIO registers bit mask --------------------------- */
AnnaBridge	156:ff21514d8981	706	/* --- CLKCR Register ---*/
AnnaBridge	156:ff21514d8981	707	/* CLKCR register clear mask */
AnnaBridge	156:ff21514d8981	708	#define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV \| SDIO_CLKCR_PWRSAV \|\
AnnaBridge	156:ff21514d8981	709	SDIO_CLKCR_BYPASS \| SDIO_CLKCR_WIDBUS \|\
AnnaBridge	156:ff21514d8981	710	SDIO_CLKCR_NEGEDGE \| SDIO_CLKCR_HWFC_EN))
AnnaBridge	156:ff21514d8981	711
AnnaBridge	156:ff21514d8981	712	/* --- DCTRL Register ---*/
AnnaBridge	156:ff21514d8981	713	/* SDIO DCTRL Clear Mask */
AnnaBridge	156:ff21514d8981	714	#define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN \| SDIO_DCTRL_DTDIR \|\
AnnaBridge	156:ff21514d8981	715	SDIO_DCTRL_DTMODE \| SDIO_DCTRL_DBLOCKSIZE))
AnnaBridge	156:ff21514d8981	716
AnnaBridge	156:ff21514d8981	717	/* --- CMD Register ---*/
AnnaBridge	156:ff21514d8981	718	/* CMD Register clear mask */
AnnaBridge	156:ff21514d8981	719	#define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX \| SDIO_CMD_WAITRESP \|\
AnnaBridge	156:ff21514d8981	720	SDIO_CMD_WAITINT \| SDIO_CMD_WAITPEND \|\
AnnaBridge	156:ff21514d8981	721	SDIO_CMD_CPSMEN \| SDIO_CMD_SDIOSUSPEND))
AnnaBridge	156:ff21514d8981	722
AnnaBridge	156:ff21514d8981	723	/* SDIO Initialization Frequency (400KHz max) */
AnnaBridge	156:ff21514d8981	724	#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
AnnaBridge	156:ff21514d8981	725
AnnaBridge	156:ff21514d8981	726	/* SDIO Data Transfer Frequency (25MHz max) */
AnnaBridge	156:ff21514d8981	727	#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
AnnaBridge	156:ff21514d8981	728
AnnaBridge	156:ff21514d8981	729	/**
AnnaBridge	156:ff21514d8981	730	* @}
AnnaBridge	156:ff21514d8981	731	*/
AnnaBridge	156:ff21514d8981	732
AnnaBridge	156:ff21514d8981	733	/** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration
AnnaBridge	156:ff21514d8981	734	* @brief macros to handle interrupts and specific clock configurations
AnnaBridge	156:ff21514d8981	735	* @{
AnnaBridge	156:ff21514d8981	736	*/
AnnaBridge	156:ff21514d8981	737
AnnaBridge	156:ff21514d8981	738	/**
AnnaBridge	156:ff21514d8981	739	* @brief Enable the SDIO device.
AnnaBridge	163:e59c8e839560	740	* @param __INSTANCE__ SDIO Instance
AnnaBridge	156:ff21514d8981	741	* @retval None
AnnaBridge	156:ff21514d8981	742	*/
AnnaBridge	156:ff21514d8981	743	#define __SDIO_ENABLE(__INSTANCE__) ((__IO uint32_t )CLKCR_CLKEN_BB = ENABLE)
AnnaBridge	156:ff21514d8981	744
AnnaBridge	156:ff21514d8981	745	/**
AnnaBridge	156:ff21514d8981	746	* @brief Disable the SDIO device.
AnnaBridge	163:e59c8e839560	747	* @param __INSTANCE__ SDIO Instance
AnnaBridge	156:ff21514d8981	748	* @retval None
AnnaBridge	156:ff21514d8981	749	*/
AnnaBridge	156:ff21514d8981	750	#define __SDIO_DISABLE(__INSTANCE__) ((__IO uint32_t )CLKCR_CLKEN_BB = DISABLE)
AnnaBridge	156:ff21514d8981	751
AnnaBridge	156:ff21514d8981	752	/**
AnnaBridge	156:ff21514d8981	753	* @brief Enable the SDIO DMA transfer.
AnnaBridge	163:e59c8e839560	754	* @param __INSTANCE__ SDIO Instance
AnnaBridge	156:ff21514d8981	755	* @retval None
AnnaBridge	156:ff21514d8981	756	*/
AnnaBridge	156:ff21514d8981	757	#define __SDIO_DMA_ENABLE(__INSTANCE__) ((__IO uint32_t )DCTRL_DMAEN_BB = ENABLE)
AnnaBridge	156:ff21514d8981	758	/**
AnnaBridge	156:ff21514d8981	759	* @brief Disable the SDIO DMA transfer.
AnnaBridge	163:e59c8e839560	760	* @param __INSTANCE__ SDIO Instance
AnnaBridge	156:ff21514d8981	761	* @retval None
AnnaBridge	156:ff21514d8981	762	*/
AnnaBridge	156:ff21514d8981	763	#define __SDIO_DMA_DISABLE(__INSTANCE__) ((__IO uint32_t )DCTRL_DMAEN_BB = DISABLE)
AnnaBridge	156:ff21514d8981	764
AnnaBridge	156:ff21514d8981	765	/**
AnnaBridge	156:ff21514d8981	766	* @brief Enable the SDIO device interrupt.
AnnaBridge	163:e59c8e839560	767	* @param __INSTANCE__ Pointer to SDIO register base
AnnaBridge	163:e59c8e839560	768	* @param __INTERRUPT__ specifies the SDIO interrupt sources to be enabled.
AnnaBridge	156:ff21514d8981	769	* This parameter can be one or a combination of the following values:
AnnaBridge	156:ff21514d8981	770	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	156:ff21514d8981	771	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	156:ff21514d8981	772	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	156:ff21514d8981	773	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	156:ff21514d8981	774	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	156:ff21514d8981	775	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	156:ff21514d8981	776	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	156:ff21514d8981	777	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	156:ff21514d8981	778	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
AnnaBridge	156:ff21514d8981	779	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	156:ff21514d8981	780	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
AnnaBridge	156:ff21514d8981	781	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
AnnaBridge	156:ff21514d8981	782	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
AnnaBridge	156:ff21514d8981	783	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge	156:ff21514d8981	784	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge	156:ff21514d8981	785	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge	156:ff21514d8981	786	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge	156:ff21514d8981	787	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge	156:ff21514d8981	788	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge	156:ff21514d8981	789	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge	156:ff21514d8981	790	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge	156:ff21514d8981	791	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	156:ff21514d8981	792	* @retval None
AnnaBridge	156:ff21514d8981	793	*/
AnnaBridge	156:ff21514d8981	794	#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__))
AnnaBridge	156:ff21514d8981	795
AnnaBridge	156:ff21514d8981	796	/**
AnnaBridge	156:ff21514d8981	797	* @brief Disable the SDIO device interrupt.
AnnaBridge	163:e59c8e839560	798	* @param __INSTANCE__ Pointer to SDIO register base
AnnaBridge	163:e59c8e839560	799	* @param __INTERRUPT__ specifies the SDIO interrupt sources to be disabled.
AnnaBridge	156:ff21514d8981	800	* This parameter can be one or a combination of the following values:
AnnaBridge	156:ff21514d8981	801	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	156:ff21514d8981	802	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	156:ff21514d8981	803	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	156:ff21514d8981	804	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	156:ff21514d8981	805	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	156:ff21514d8981	806	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	156:ff21514d8981	807	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	156:ff21514d8981	808	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	156:ff21514d8981	809	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
AnnaBridge	156:ff21514d8981	810	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	156:ff21514d8981	811	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
AnnaBridge	156:ff21514d8981	812	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
AnnaBridge	156:ff21514d8981	813	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
AnnaBridge	156:ff21514d8981	814	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge	156:ff21514d8981	815	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge	156:ff21514d8981	816	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge	156:ff21514d8981	817	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge	156:ff21514d8981	818	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge	156:ff21514d8981	819	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge	156:ff21514d8981	820	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge	156:ff21514d8981	821	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge	156:ff21514d8981	822	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	156:ff21514d8981	823	* @retval None
AnnaBridge	156:ff21514d8981	824	*/
AnnaBridge	156:ff21514d8981	825	#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
AnnaBridge	156:ff21514d8981	826
AnnaBridge	156:ff21514d8981	827	/**
AnnaBridge	156:ff21514d8981	828	* @brief Checks whether the specified SDIO flag is set or not.
AnnaBridge	163:e59c8e839560	829	* @param __INSTANCE__ Pointer to SDIO register base
AnnaBridge	163:e59c8e839560	830	* @param __FLAG__ specifies the flag to check.
AnnaBridge	156:ff21514d8981	831	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	832	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
AnnaBridge	156:ff21514d8981	833	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
AnnaBridge	156:ff21514d8981	834	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
AnnaBridge	156:ff21514d8981	835	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
AnnaBridge	156:ff21514d8981	836	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
AnnaBridge	156:ff21514d8981	837	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
AnnaBridge	156:ff21514d8981	838	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
AnnaBridge	156:ff21514d8981	839	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
AnnaBridge	156:ff21514d8981	840	* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
AnnaBridge	156:ff21514d8981	841	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
AnnaBridge	156:ff21514d8981	842	* @arg SDIO_FLAG_CMDACT: Command transfer in progress
AnnaBridge	156:ff21514d8981	843	* @arg SDIO_FLAG_TXACT: Data transmit in progress
AnnaBridge	156:ff21514d8981	844	* @arg SDIO_FLAG_RXACT: Data receive in progress
AnnaBridge	156:ff21514d8981	845	* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
AnnaBridge	156:ff21514d8981	846	* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
AnnaBridge	156:ff21514d8981	847	* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
AnnaBridge	156:ff21514d8981	848	* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
AnnaBridge	156:ff21514d8981	849	* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
AnnaBridge	156:ff21514d8981	850	* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
AnnaBridge	156:ff21514d8981	851	* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
AnnaBridge	156:ff21514d8981	852	* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
AnnaBridge	156:ff21514d8981	853	* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
AnnaBridge	156:ff21514d8981	854	* @retval The new state of SDIO_FLAG (SET or RESET).
AnnaBridge	156:ff21514d8981	855	*/
AnnaBridge	156:ff21514d8981	856	#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
AnnaBridge	156:ff21514d8981	857
AnnaBridge	156:ff21514d8981	858
AnnaBridge	156:ff21514d8981	859	/**
AnnaBridge	156:ff21514d8981	860	* @brief Clears the SDIO pending flags.
AnnaBridge	163:e59c8e839560	861	* @param __INSTANCE__ Pointer to SDIO register base
AnnaBridge	163:e59c8e839560	862	* @param __FLAG__ specifies the flag to clear.
AnnaBridge	156:ff21514d8981	863	* This parameter can be one or a combination of the following values:
AnnaBridge	156:ff21514d8981	864	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
AnnaBridge	156:ff21514d8981	865	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
AnnaBridge	156:ff21514d8981	866	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
AnnaBridge	156:ff21514d8981	867	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
AnnaBridge	156:ff21514d8981	868	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
AnnaBridge	156:ff21514d8981	869	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
AnnaBridge	156:ff21514d8981	870	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
AnnaBridge	156:ff21514d8981	871	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
AnnaBridge	156:ff21514d8981	872	* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
AnnaBridge	156:ff21514d8981	873	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
AnnaBridge	156:ff21514d8981	874	* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
AnnaBridge	156:ff21514d8981	875	* @retval None
AnnaBridge	156:ff21514d8981	876	*/
AnnaBridge	156:ff21514d8981	877	#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
AnnaBridge	156:ff21514d8981	878
AnnaBridge	156:ff21514d8981	879	/**
AnnaBridge	156:ff21514d8981	880	* @brief Checks whether the specified SDIO interrupt has occurred or not.
AnnaBridge	163:e59c8e839560	881	* @param __INSTANCE__ Pointer to SDIO register base
AnnaBridge	163:e59c8e839560	882	* @param __INTERRUPT__ specifies the SDIO interrupt source to check.
AnnaBridge	156:ff21514d8981	883	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	884	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	156:ff21514d8981	885	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	156:ff21514d8981	886	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	156:ff21514d8981	887	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	156:ff21514d8981	888	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	156:ff21514d8981	889	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	156:ff21514d8981	890	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	156:ff21514d8981	891	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	156:ff21514d8981	892	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
AnnaBridge	156:ff21514d8981	893	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	156:ff21514d8981	894	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
AnnaBridge	156:ff21514d8981	895	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
AnnaBridge	156:ff21514d8981	896	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
AnnaBridge	156:ff21514d8981	897	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge	156:ff21514d8981	898	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge	156:ff21514d8981	899	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge	156:ff21514d8981	900	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge	156:ff21514d8981	901	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge	156:ff21514d8981	902	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge	156:ff21514d8981	903	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge	156:ff21514d8981	904	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge	156:ff21514d8981	905	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	156:ff21514d8981	906	* @retval The new state of SDIO_IT (SET or RESET).
AnnaBridge	156:ff21514d8981	907	*/
AnnaBridge	156:ff21514d8981	908	#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge	156:ff21514d8981	909
AnnaBridge	156:ff21514d8981	910	/**
AnnaBridge	156:ff21514d8981	911	* @brief Clears the SDIO's interrupt pending bits.
AnnaBridge	163:e59c8e839560	912	* @param __INSTANCE__ Pointer to SDIO register base
AnnaBridge	163:e59c8e839560	913	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge	156:ff21514d8981	914	* This parameter can be one or a combination of the following values:
AnnaBridge	156:ff21514d8981	915	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	156:ff21514d8981	916	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	156:ff21514d8981	917	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	156:ff21514d8981	918	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	156:ff21514d8981	919	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	156:ff21514d8981	920	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	156:ff21514d8981	921	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	156:ff21514d8981	922	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	156:ff21514d8981	923	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
AnnaBridge	156:ff21514d8981	924	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	156:ff21514d8981	925	* @retval None
AnnaBridge	156:ff21514d8981	926	*/
AnnaBridge	156:ff21514d8981	927	#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
AnnaBridge	156:ff21514d8981	928
AnnaBridge	156:ff21514d8981	929	/**
AnnaBridge	156:ff21514d8981	930	* @brief Enable Start the SD I/O Read Wait operation.
AnnaBridge	163:e59c8e839560	931	* @param __INSTANCE__ Pointer to SDIO register base
AnnaBridge	156:ff21514d8981	932	* @retval None
AnnaBridge	156:ff21514d8981	933	*/
AnnaBridge	156:ff21514d8981	934	#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTART_BB = ENABLE)
AnnaBridge	156:ff21514d8981	935
AnnaBridge	156:ff21514d8981	936	/**
AnnaBridge	156:ff21514d8981	937	* @brief Disable Start the SD I/O Read Wait operations.
AnnaBridge	163:e59c8e839560	938	* @param __INSTANCE__ Pointer to SDIO register base
AnnaBridge	156:ff21514d8981	939	* @retval None
AnnaBridge	156:ff21514d8981	940	*/
AnnaBridge	156:ff21514d8981	941	#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTART_BB = DISABLE)
AnnaBridge	156:ff21514d8981	942
AnnaBridge	156:ff21514d8981	943	/**
AnnaBridge	156:ff21514d8981	944	* @brief Enable Start the SD I/O Read Wait operation.
AnnaBridge	163:e59c8e839560	945	* @param __INSTANCE__ Pointer to SDIO register base
AnnaBridge	156:ff21514d8981	946	* @retval None
AnnaBridge	156:ff21514d8981	947	*/
AnnaBridge	156:ff21514d8981	948	#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTOP_BB = ENABLE)
AnnaBridge	156:ff21514d8981	949
AnnaBridge	156:ff21514d8981	950	/**
AnnaBridge	156:ff21514d8981	951	* @brief Disable Stop the SD I/O Read Wait operations.
AnnaBridge	163:e59c8e839560	952	* @param __INSTANCE__ Pointer to SDIO register base
AnnaBridge	156:ff21514d8981	953	* @retval None
AnnaBridge	156:ff21514d8981	954	*/
AnnaBridge	156:ff21514d8981	955	#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTOP_BB = DISABLE)
AnnaBridge	156:ff21514d8981	956
AnnaBridge	156:ff21514d8981	957	/**
AnnaBridge	156:ff21514d8981	958	* @brief Enable the SD I/O Mode Operation.
AnnaBridge	163:e59c8e839560	959	* @param __INSTANCE__ Pointer to SDIO register base
AnnaBridge	156:ff21514d8981	960	* @retval None
AnnaBridge	156:ff21514d8981	961	*/
AnnaBridge	156:ff21514d8981	962	#define __SDIO_OPERATION_ENABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_SDIOEN_BB = ENABLE)
AnnaBridge	156:ff21514d8981	963
AnnaBridge	156:ff21514d8981	964	/**
AnnaBridge	156:ff21514d8981	965	* @brief Disable the SD I/O Mode Operation.
AnnaBridge	163:e59c8e839560	966	* @param __INSTANCE__ Pointer to SDIO register base
AnnaBridge	156:ff21514d8981	967	* @retval None
AnnaBridge	156:ff21514d8981	968	*/
AnnaBridge	156:ff21514d8981	969	#define __SDIO_OPERATION_DISABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_SDIOEN_BB = DISABLE)
AnnaBridge	156:ff21514d8981	970
AnnaBridge	156:ff21514d8981	971	/**
AnnaBridge	156:ff21514d8981	972	* @brief Enable the SD I/O Suspend command sending.
AnnaBridge	163:e59c8e839560	973	* @param __INSTANCE__ Pointer to SDIO register base
AnnaBridge	156:ff21514d8981	974	* @retval None
AnnaBridge	156:ff21514d8981	975	*/
AnnaBridge	156:ff21514d8981	976	#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = ENABLE)
AnnaBridge	156:ff21514d8981	977
AnnaBridge	156:ff21514d8981	978	/**
AnnaBridge	156:ff21514d8981	979	* @brief Disable the SD I/O Suspend command sending.
AnnaBridge	163:e59c8e839560	980	* @param __INSTANCE__ Pointer to SDIO register base
AnnaBridge	156:ff21514d8981	981	* @retval None
AnnaBridge	156:ff21514d8981	982	*/
AnnaBridge	156:ff21514d8981	983	#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = DISABLE)
AnnaBridge	156:ff21514d8981	984
AnnaBridge	156:ff21514d8981	985	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
AnnaBridge	156:ff21514d8981	986	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
AnnaBridge	156:ff21514d8981	987	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
AnnaBridge	156:ff21514d8981	988	/**
AnnaBridge	156:ff21514d8981	989	* @brief Enable the command completion signal.
AnnaBridge	156:ff21514d8981	990	* @retval None
AnnaBridge	156:ff21514d8981	991	*/
AnnaBridge	156:ff21514d8981	992	#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = ENABLE)
AnnaBridge	156:ff21514d8981	993
AnnaBridge	156:ff21514d8981	994	/**
AnnaBridge	156:ff21514d8981	995	* @brief Disable the command completion signal.
AnnaBridge	156:ff21514d8981	996	* @retval None
AnnaBridge	156:ff21514d8981	997	*/
AnnaBridge	156:ff21514d8981	998	#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = DISABLE)
AnnaBridge	156:ff21514d8981	999
AnnaBridge	156:ff21514d8981	1000	/**
AnnaBridge	156:ff21514d8981	1001	* @brief Enable the CE-ATA interrupt.
AnnaBridge	156:ff21514d8981	1002	* @retval None
AnnaBridge	156:ff21514d8981	1003	*/
AnnaBridge	156:ff21514d8981	1004	#define __SDIO_CEATA_ENABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)0U)
AnnaBridge	156:ff21514d8981	1005
AnnaBridge	156:ff21514d8981	1006	/**
AnnaBridge	156:ff21514d8981	1007	* @brief Disable the CE-ATA interrupt.
AnnaBridge	156:ff21514d8981	1008	* @retval None
AnnaBridge	156:ff21514d8981	1009	*/
AnnaBridge	156:ff21514d8981	1010	#define __SDIO_CEATA_DISABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)1U)
AnnaBridge	156:ff21514d8981	1011
AnnaBridge	156:ff21514d8981	1012	/**
AnnaBridge	156:ff21514d8981	1013	* @brief Enable send CE-ATA command (CMD61).
AnnaBridge	156:ff21514d8981	1014	* @retval None
AnnaBridge	156:ff21514d8981	1015	*/
AnnaBridge	156:ff21514d8981	1016	#define __SDIO_CEATA_SENDCMD_ENABLE() ((__IO uint32_t ) CMD_ATACMD_BB = ENABLE)
AnnaBridge	156:ff21514d8981	1017
AnnaBridge	156:ff21514d8981	1018	/**
AnnaBridge	156:ff21514d8981	1019	* @brief Disable send CE-ATA command (CMD61).
AnnaBridge	156:ff21514d8981	1020	* @retval None
AnnaBridge	156:ff21514d8981	1021	*/
AnnaBridge	156:ff21514d8981	1022	#define __SDIO_CEATA_SENDCMD_DISABLE() ((__IO uint32_t ) CMD_ATACMD_BB = DISABLE)
AnnaBridge	156:ff21514d8981	1023	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\|\
AnnaBridge	156:ff21514d8981	1024	STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
AnnaBridge	156:ff21514d8981	1025
AnnaBridge	156:ff21514d8981	1026	/**
AnnaBridge	156:ff21514d8981	1027	* @}
AnnaBridge	156:ff21514d8981	1028	*/
AnnaBridge	156:ff21514d8981	1029
AnnaBridge	156:ff21514d8981	1030	/**
AnnaBridge	156:ff21514d8981	1031	* @}
AnnaBridge	156:ff21514d8981	1032	*/
AnnaBridge	156:ff21514d8981	1033
AnnaBridge	156:ff21514d8981	1034	/* Exported functions --------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	1035	/** @addtogroup SDMMC_LL_Exported_Functions
AnnaBridge	156:ff21514d8981	1036	* @{
AnnaBridge	156:ff21514d8981	1037	*/
AnnaBridge	156:ff21514d8981	1038
AnnaBridge	156:ff21514d8981	1039	/* Initialization/de-initialization functions **********************************/
AnnaBridge	156:ff21514d8981	1040	/** @addtogroup HAL_SDMMC_LL_Group1
AnnaBridge	156:ff21514d8981	1041	* @{
AnnaBridge	156:ff21514d8981	1042	*/
AnnaBridge	156:ff21514d8981	1043	HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
AnnaBridge	156:ff21514d8981	1044	/**
AnnaBridge	156:ff21514d8981	1045	* @}
AnnaBridge	156:ff21514d8981	1046	*/
AnnaBridge	156:ff21514d8981	1047
AnnaBridge	156:ff21514d8981	1048	/* I/O operation functions *****************************************************/
AnnaBridge	156:ff21514d8981	1049	/** @addtogroup HAL_SDMMC_LL_Group2
AnnaBridge	156:ff21514d8981	1050	* @{
AnnaBridge	156:ff21514d8981	1051	*/
AnnaBridge	156:ff21514d8981	1052	uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
AnnaBridge	156:ff21514d8981	1053	HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef SDIOx, uint32_t pWriteData);
AnnaBridge	156:ff21514d8981	1054	/**
AnnaBridge	156:ff21514d8981	1055	* @}
AnnaBridge	156:ff21514d8981	1056	*/
AnnaBridge	156:ff21514d8981	1057
AnnaBridge	156:ff21514d8981	1058	/* Peripheral Control functions ************************************************/
AnnaBridge	156:ff21514d8981	1059	/** @addtogroup HAL_SDMMC_LL_Group3
AnnaBridge	156:ff21514d8981	1060	* @{
AnnaBridge	156:ff21514d8981	1061	*/
AnnaBridge	156:ff21514d8981	1062	HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
AnnaBridge	156:ff21514d8981	1063	HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
AnnaBridge	156:ff21514d8981	1064	uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
AnnaBridge	156:ff21514d8981	1065
AnnaBridge	156:ff21514d8981	1066	/* Command path state machine (CPSM) management functions */
AnnaBridge	156:ff21514d8981	1067	HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef SDIOx, SDIO_CmdInitTypeDef Command);
AnnaBridge	156:ff21514d8981	1068	uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
AnnaBridge	156:ff21514d8981	1069	uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
AnnaBridge	156:ff21514d8981	1070
AnnaBridge	156:ff21514d8981	1071	/* Data path state machine (DPSM) management functions */
AnnaBridge	156:ff21514d8981	1072	HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef SDIOx, SDIO_DataInitTypeDef Data);
AnnaBridge	156:ff21514d8981	1073	uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
AnnaBridge	156:ff21514d8981	1074	uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
AnnaBridge	156:ff21514d8981	1075
AnnaBridge	156:ff21514d8981	1076	/* SDMMC Cards mode management functions */
AnnaBridge	156:ff21514d8981	1077	HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
AnnaBridge	156:ff21514d8981	1078
AnnaBridge	156:ff21514d8981	1079	/* SDMMC Commands management functions */
AnnaBridge	156:ff21514d8981	1080	uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize);
AnnaBridge	156:ff21514d8981	1081	uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
AnnaBridge	156:ff21514d8981	1082	uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
AnnaBridge	156:ff21514d8981	1083	uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
AnnaBridge	156:ff21514d8981	1084	uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
AnnaBridge	156:ff21514d8981	1085	uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
AnnaBridge	156:ff21514d8981	1086	uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
AnnaBridge	156:ff21514d8981	1087	uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
AnnaBridge	156:ff21514d8981	1088	uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
AnnaBridge	156:ff21514d8981	1089	uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);
AnnaBridge	156:ff21514d8981	1090	uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
AnnaBridge	156:ff21514d8981	1091	uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
AnnaBridge	156:ff21514d8981	1092	uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
AnnaBridge	156:ff21514d8981	1093	uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType);
AnnaBridge	156:ff21514d8981	1094	uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
AnnaBridge	156:ff21514d8981	1095	uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
AnnaBridge	156:ff21514d8981	1096	uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
AnnaBridge	156:ff21514d8981	1097	uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
AnnaBridge	156:ff21514d8981	1098	uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef SDIOx, uint16_t pRCA);
AnnaBridge	156:ff21514d8981	1099	uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
AnnaBridge	156:ff21514d8981	1100	uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
AnnaBridge	156:ff21514d8981	1101
AnnaBridge	156:ff21514d8981	1102	uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
AnnaBridge	156:ff21514d8981	1103	uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
AnnaBridge	156:ff21514d8981	1104	uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
AnnaBridge	156:ff21514d8981	1105	uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
AnnaBridge	156:ff21514d8981	1106
AnnaBridge	156:ff21514d8981	1107	/**
AnnaBridge	156:ff21514d8981	1108	* @}
AnnaBridge	156:ff21514d8981	1109	*/
AnnaBridge	156:ff21514d8981	1110
AnnaBridge	156:ff21514d8981	1111	/**
AnnaBridge	156:ff21514d8981	1112	* @}
AnnaBridge	156:ff21514d8981	1113	*/
AnnaBridge	156:ff21514d8981	1114
AnnaBridge	156:ff21514d8981	1115	/**
AnnaBridge	156:ff21514d8981	1116	* @}
AnnaBridge	156:ff21514d8981	1117	*/
AnnaBridge	156:ff21514d8981	1118
AnnaBridge	156:ff21514d8981	1119	/**
AnnaBridge	156:ff21514d8981	1120	* @}
AnnaBridge	156:ff21514d8981	1121	*/
AnnaBridge	156:ff21514d8981	1122
AnnaBridge	156:ff21514d8981	1123	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
AnnaBridge	156:ff21514d8981	1124	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
AnnaBridge	156:ff21514d8981	1125	STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	1126
AnnaBridge	156:ff21514d8981	1127	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	1128	}
AnnaBridge	156:ff21514d8981	1129	#endif
AnnaBridge	156:ff21514d8981	1130
AnnaBridge	156:ff21514d8981	1131	#endif /* __STM32F4xx_LL_SDMMC_H */
AnnaBridge	156:ff21514d8981	1132
AnnaBridge	156:ff21514d8981	1133	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/