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TARGET_B96B_F446VE/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:: Anna Bridge
Date:: Fri Jun 22 15:38:59 2018 +0100
Revision:: 169:a7c7b631e539
Parent:: 163:e59c8e839560

mbed library. Release version 162

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	156:ff21514d8981	1	/**
AnnaBridge	156:ff21514d8981	2	******************************************************************************
AnnaBridge	156:ff21514d8981	3	* @file stm32f4xx_hal_rcc_ex.h
AnnaBridge	156:ff21514d8981	4	* @author MCD Application Team
AnnaBridge	156:ff21514d8981	5	* @brief Header file of RCC HAL Extension module.
AnnaBridge	156:ff21514d8981	6	******************************************************************************
AnnaBridge	156:ff21514d8981	7	* @attention
AnnaBridge	156:ff21514d8981	8	*
AnnaBridge	156:ff21514d8981	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	156:ff21514d8981	10	*
AnnaBridge	156:ff21514d8981	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	156:ff21514d8981	12	* are permitted provided that the following conditions are met:
AnnaBridge	156:ff21514d8981	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	156:ff21514d8981	14	* this list of conditions and the following disclaimer.
AnnaBridge	156:ff21514d8981	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	156:ff21514d8981	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	156:ff21514d8981	17	* and/or other materials provided with the distribution.
AnnaBridge	156:ff21514d8981	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	156:ff21514d8981	19	* may be used to endorse or promote products derived from this software
AnnaBridge	156:ff21514d8981	20	* without specific prior written permission.
AnnaBridge	156:ff21514d8981	21	*
AnnaBridge	156:ff21514d8981	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	156:ff21514d8981	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	156:ff21514d8981	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	156:ff21514d8981	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	156:ff21514d8981	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	156:ff21514d8981	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	156:ff21514d8981	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	156:ff21514d8981	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	156:ff21514d8981	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	156:ff21514d8981	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	156:ff21514d8981	32	*
AnnaBridge	156:ff21514d8981	33	******************************************************************************
AnnaBridge	156:ff21514d8981	34	*/
AnnaBridge	156:ff21514d8981	35
AnnaBridge	156:ff21514d8981	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	156:ff21514d8981	37	#ifndef __STM32F4xx_HAL_RCC_EX_H
AnnaBridge	156:ff21514d8981	38	#define __STM32F4xx_HAL_RCC_EX_H
AnnaBridge	156:ff21514d8981	39
AnnaBridge	156:ff21514d8981	40	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	41	extern "C" {
AnnaBridge	156:ff21514d8981	42	#endif
AnnaBridge	156:ff21514d8981	43
AnnaBridge	156:ff21514d8981	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	45	#include "stm32f4xx_hal_def.h"
AnnaBridge	156:ff21514d8981	46
AnnaBridge	156:ff21514d8981	47	/** @addtogroup STM32F4xx_HAL_Driver
AnnaBridge	156:ff21514d8981	48	* @{
AnnaBridge	156:ff21514d8981	49	*/
AnnaBridge	156:ff21514d8981	50
AnnaBridge	156:ff21514d8981	51	/** @addtogroup RCCEx
AnnaBridge	156:ff21514d8981	52	* @{
AnnaBridge	156:ff21514d8981	53	*/
AnnaBridge	156:ff21514d8981	54
AnnaBridge	156:ff21514d8981	55	/* Exported types ------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	56	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
AnnaBridge	156:ff21514d8981	57	* @{
AnnaBridge	156:ff21514d8981	58	*/
AnnaBridge	156:ff21514d8981	59
AnnaBridge	156:ff21514d8981	60	/**
AnnaBridge	156:ff21514d8981	61	* @brief RCC PLL configuration structure definition
AnnaBridge	156:ff21514d8981	62	*/
AnnaBridge	156:ff21514d8981	63	typedef struct
AnnaBridge	156:ff21514d8981	64	{
AnnaBridge	156:ff21514d8981	65	uint32_t PLLState; /*!< The new state of the PLL.
AnnaBridge	156:ff21514d8981	66	This parameter can be a value of @ref RCC_PLL_Config */
AnnaBridge	156:ff21514d8981	67
AnnaBridge	156:ff21514d8981	68	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
AnnaBridge	156:ff21514d8981	69	This parameter must be a value of @ref RCC_PLL_Clock_Source */
AnnaBridge	156:ff21514d8981	70
AnnaBridge	156:ff21514d8981	71	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
AnnaBridge	156:ff21514d8981	72	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
AnnaBridge	156:ff21514d8981	73
AnnaBridge	156:ff21514d8981	74	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
AnnaBridge	156:ff21514d8981	75	This parameter must be a number between Min_Data = 50 and Max_Data = 432
AnnaBridge	156:ff21514d8981	76	except for STM32F411xE devices where the Min_Data = 192 */
AnnaBridge	156:ff21514d8981	77
AnnaBridge	156:ff21514d8981	78	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
AnnaBridge	156:ff21514d8981	79	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
AnnaBridge	156:ff21514d8981	80
AnnaBridge	156:ff21514d8981	81	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
AnnaBridge	156:ff21514d8981	82	This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
AnnaBridge	156:ff21514d8981	83	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
AnnaBridge	156:ff21514d8981	84	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
AnnaBridge	156:ff21514d8981	85	defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	86	uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
AnnaBridge	156:ff21514d8981	87	This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx
AnnaBridge	156:ff21514d8981	88	and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.
AnnaBridge	156:ff21514d8981	89	This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
AnnaBridge	156:ff21514d8981	90	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	91	}RCC_PLLInitTypeDef;
AnnaBridge	156:ff21514d8981	92
AnnaBridge	156:ff21514d8981	93	#if defined(STM32F446xx)
AnnaBridge	156:ff21514d8981	94	/**
AnnaBridge	156:ff21514d8981	95	* @brief PLLI2S Clock structure definition
AnnaBridge	156:ff21514d8981	96	*/
AnnaBridge	156:ff21514d8981	97	typedef struct
AnnaBridge	156:ff21514d8981	98	{
AnnaBridge	156:ff21514d8981	99	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
AnnaBridge	156:ff21514d8981	100	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
AnnaBridge	156:ff21514d8981	101
AnnaBridge	156:ff21514d8981	102	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
AnnaBridge	156:ff21514d8981	103	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
AnnaBridge	156:ff21514d8981	104
AnnaBridge	156:ff21514d8981	105	uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock.
AnnaBridge	156:ff21514d8981	106	This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */
AnnaBridge	156:ff21514d8981	107
AnnaBridge	156:ff21514d8981	108	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
AnnaBridge	156:ff21514d8981	109	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	156:ff21514d8981	110	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
AnnaBridge	156:ff21514d8981	111
AnnaBridge	156:ff21514d8981	112	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
AnnaBridge	156:ff21514d8981	113	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	156:ff21514d8981	114	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
AnnaBridge	156:ff21514d8981	115	}RCC_PLLI2SInitTypeDef;
AnnaBridge	156:ff21514d8981	116
AnnaBridge	156:ff21514d8981	117	/**
AnnaBridge	156:ff21514d8981	118	* @brief PLLSAI Clock structure definition
AnnaBridge	156:ff21514d8981	119	*/
AnnaBridge	156:ff21514d8981	120	typedef struct
AnnaBridge	156:ff21514d8981	121	{
AnnaBridge	156:ff21514d8981	122	uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
AnnaBridge	156:ff21514d8981	123	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
AnnaBridge	156:ff21514d8981	124
AnnaBridge	156:ff21514d8981	125	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
AnnaBridge	156:ff21514d8981	126	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
AnnaBridge	156:ff21514d8981	127
AnnaBridge	156:ff21514d8981	128	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
AnnaBridge	156:ff21514d8981	129	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
AnnaBridge	156:ff21514d8981	130
AnnaBridge	156:ff21514d8981	131	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock.
AnnaBridge	156:ff21514d8981	132	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	156:ff21514d8981	133	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
AnnaBridge	156:ff21514d8981	134	}RCC_PLLSAIInitTypeDef;
AnnaBridge	156:ff21514d8981	135
AnnaBridge	156:ff21514d8981	136	/**
AnnaBridge	156:ff21514d8981	137	* @brief RCC extended clocks structure definition
AnnaBridge	156:ff21514d8981	138	*/
AnnaBridge	156:ff21514d8981	139	typedef struct
AnnaBridge	156:ff21514d8981	140	{
AnnaBridge	156:ff21514d8981	141	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	156:ff21514d8981	142	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	156:ff21514d8981	143
AnnaBridge	156:ff21514d8981	144	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
AnnaBridge	156:ff21514d8981	145	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
AnnaBridge	156:ff21514d8981	146
AnnaBridge	156:ff21514d8981	147	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
AnnaBridge	156:ff21514d8981	148	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
AnnaBridge	156:ff21514d8981	149
AnnaBridge	156:ff21514d8981	150	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
AnnaBridge	156:ff21514d8981	151	This parameter must be a number between Min_Data = 1 and Max_Data = 32
AnnaBridge	156:ff21514d8981	152	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
AnnaBridge	156:ff21514d8981	153
AnnaBridge	156:ff21514d8981	154	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
AnnaBridge	156:ff21514d8981	155	This parameter must be a number between Min_Data = 1 and Max_Data = 32
AnnaBridge	156:ff21514d8981	156	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
AnnaBridge	156:ff21514d8981	157
AnnaBridge	156:ff21514d8981	158	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection.
AnnaBridge	156:ff21514d8981	159	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
AnnaBridge	156:ff21514d8981	160
AnnaBridge	156:ff21514d8981	161	uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection.
AnnaBridge	156:ff21514d8981	162	This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
AnnaBridge	156:ff21514d8981	163
AnnaBridge	156:ff21514d8981	164	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
AnnaBridge	156:ff21514d8981	165	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
AnnaBridge	156:ff21514d8981	166
AnnaBridge	156:ff21514d8981	167	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
AnnaBridge	156:ff21514d8981	168	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
AnnaBridge	156:ff21514d8981	169
AnnaBridge	156:ff21514d8981	170	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
AnnaBridge	156:ff21514d8981	171	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	156:ff21514d8981	172
AnnaBridge	156:ff21514d8981	173	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
AnnaBridge	156:ff21514d8981	174	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
AnnaBridge	156:ff21514d8981	175
AnnaBridge	156:ff21514d8981	176	uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection.
AnnaBridge	156:ff21514d8981	177	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
AnnaBridge	156:ff21514d8981	178
AnnaBridge	156:ff21514d8981	179	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
AnnaBridge	156:ff21514d8981	180	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
AnnaBridge	156:ff21514d8981	181
AnnaBridge	156:ff21514d8981	182	uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection.
AnnaBridge	156:ff21514d8981	183	This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
AnnaBridge	156:ff21514d8981	184
AnnaBridge	156:ff21514d8981	185	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
AnnaBridge	156:ff21514d8981	186	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
AnnaBridge	156:ff21514d8981	187
AnnaBridge	156:ff21514d8981	188	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
AnnaBridge	156:ff21514d8981	189	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
AnnaBridge	156:ff21514d8981	190	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	156:ff21514d8981	191	#endif /* STM32F446xx */
AnnaBridge	156:ff21514d8981	192
AnnaBridge	156:ff21514d8981	193	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	156:ff21514d8981	194	/**
AnnaBridge	156:ff21514d8981	195	* @brief RCC extended clocks structure definition
AnnaBridge	156:ff21514d8981	196	*/
AnnaBridge	156:ff21514d8981	197	typedef struct
AnnaBridge	156:ff21514d8981	198	{
AnnaBridge	156:ff21514d8981	199	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	156:ff21514d8981	200	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	156:ff21514d8981	201
AnnaBridge	156:ff21514d8981	202	uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection.
AnnaBridge	156:ff21514d8981	203	This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */
AnnaBridge	156:ff21514d8981	204
AnnaBridge	156:ff21514d8981	205	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
AnnaBridge	156:ff21514d8981	206	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	156:ff21514d8981	207
AnnaBridge	156:ff21514d8981	208	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
AnnaBridge	156:ff21514d8981	209	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
AnnaBridge	156:ff21514d8981	210
AnnaBridge	156:ff21514d8981	211	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
AnnaBridge	156:ff21514d8981	212	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
AnnaBridge	156:ff21514d8981	213
AnnaBridge	156:ff21514d8981	214	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
AnnaBridge	156:ff21514d8981	215	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
AnnaBridge	156:ff21514d8981	216	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	156:ff21514d8981	217	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	156:ff21514d8981	218
AnnaBridge	156:ff21514d8981	219	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	220	/**
AnnaBridge	156:ff21514d8981	221	* @brief PLLI2S Clock structure definition
AnnaBridge	156:ff21514d8981	222	*/
AnnaBridge	156:ff21514d8981	223	typedef struct
AnnaBridge	156:ff21514d8981	224	{
AnnaBridge	156:ff21514d8981	225	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
AnnaBridge	156:ff21514d8981	226	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
AnnaBridge	156:ff21514d8981	227
AnnaBridge	156:ff21514d8981	228	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
AnnaBridge	156:ff21514d8981	229	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
AnnaBridge	156:ff21514d8981	230
AnnaBridge	156:ff21514d8981	231	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
AnnaBridge	156:ff21514d8981	232	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	156:ff21514d8981	233	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
AnnaBridge	156:ff21514d8981	234
AnnaBridge	156:ff21514d8981	235	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
AnnaBridge	156:ff21514d8981	236	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	156:ff21514d8981	237	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
AnnaBridge	156:ff21514d8981	238	}RCC_PLLI2SInitTypeDef;
AnnaBridge	156:ff21514d8981	239
AnnaBridge	156:ff21514d8981	240	/**
AnnaBridge	156:ff21514d8981	241	* @brief RCC extended clocks structure definition
AnnaBridge	156:ff21514d8981	242	*/
AnnaBridge	156:ff21514d8981	243	typedef struct
AnnaBridge	156:ff21514d8981	244	{
AnnaBridge	156:ff21514d8981	245	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	156:ff21514d8981	246	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	156:ff21514d8981	247
AnnaBridge	156:ff21514d8981	248	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
AnnaBridge	156:ff21514d8981	249	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
AnnaBridge	156:ff21514d8981	250
AnnaBridge	156:ff21514d8981	251	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	252	uint32_t PLLDivR; /*!< Specifies the PLL division factor for SAI1 clock.
AnnaBridge	156:ff21514d8981	253	This parameter must be a number between Min_Data = 1 and Max_Data = 32
AnnaBridge	156:ff21514d8981	254	This parameter will be used only when PLL is selected as Clock Source SAI */
AnnaBridge	156:ff21514d8981	255
AnnaBridge	156:ff21514d8981	256	uint32_t PLLI2SDivR; /*!< Specifies the PLLI2S division factor for SAI1 clock.
AnnaBridge	156:ff21514d8981	257	This parameter must be a number between Min_Data = 1 and Max_Data = 32
AnnaBridge	156:ff21514d8981	258	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
AnnaBridge	156:ff21514d8981	259	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	260
AnnaBridge	156:ff21514d8981	261	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
AnnaBridge	156:ff21514d8981	262	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
AnnaBridge	156:ff21514d8981	263
AnnaBridge	156:ff21514d8981	264	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
AnnaBridge	156:ff21514d8981	265	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
AnnaBridge	156:ff21514d8981	266
AnnaBridge	156:ff21514d8981	267	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
AnnaBridge	156:ff21514d8981	268	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	156:ff21514d8981	269
AnnaBridge	156:ff21514d8981	270	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
AnnaBridge	156:ff21514d8981	271	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
AnnaBridge	156:ff21514d8981	272
AnnaBridge	156:ff21514d8981	273	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
AnnaBridge	156:ff21514d8981	274	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
AnnaBridge	156:ff21514d8981	275
AnnaBridge	156:ff21514d8981	276	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
AnnaBridge	156:ff21514d8981	277	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
AnnaBridge	156:ff21514d8981	278
AnnaBridge	156:ff21514d8981	279	uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock Selection.
AnnaBridge	156:ff21514d8981	280	This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
AnnaBridge	156:ff21514d8981	281
AnnaBridge	156:ff21514d8981	282	uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection.
AnnaBridge	156:ff21514d8981	283	This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */
AnnaBridge	156:ff21514d8981	284
AnnaBridge	156:ff21514d8981	285	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	286	uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock Selection.
AnnaBridge	156:ff21514d8981	287	This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */
AnnaBridge	156:ff21514d8981	288
AnnaBridge	156:ff21514d8981	289	uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection.
AnnaBridge	156:ff21514d8981	290	This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */
AnnaBridge	156:ff21514d8981	291
AnnaBridge	156:ff21514d8981	292	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
AnnaBridge	156:ff21514d8981	293	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
AnnaBridge	156:ff21514d8981	294
AnnaBridge	156:ff21514d8981	295	uint32_t SaiAClockSelection; /*!< Specifies SAI1_A Clock Prescalers Selection
AnnaBridge	156:ff21514d8981	296	This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */
AnnaBridge	156:ff21514d8981	297
AnnaBridge	156:ff21514d8981	298	uint32_t SaiBClockSelection; /*!< Specifies SAI1_B Clock Prescalers Selection
AnnaBridge	156:ff21514d8981	299	This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */
AnnaBridge	156:ff21514d8981	300	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	301
AnnaBridge	156:ff21514d8981	302	uint32_t PLLI2SSelection; /*!< Specifies PLL I2S Clock Source Selection.
AnnaBridge	156:ff21514d8981	303	This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */
AnnaBridge	156:ff21514d8981	304
AnnaBridge	156:ff21514d8981	305	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
AnnaBridge	156:ff21514d8981	306	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
AnnaBridge	156:ff21514d8981	307	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	156:ff21514d8981	308	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	309
AnnaBridge	156:ff21514d8981	310	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	163:e59c8e839560	311
AnnaBridge	156:ff21514d8981	312	/**
AnnaBridge	156:ff21514d8981	313	* @brief PLLI2S Clock structure definition
AnnaBridge	156:ff21514d8981	314	*/
AnnaBridge	156:ff21514d8981	315	typedef struct
AnnaBridge	156:ff21514d8981	316	{
AnnaBridge	156:ff21514d8981	317	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
AnnaBridge	156:ff21514d8981	318	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	156:ff21514d8981	319	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
AnnaBridge	156:ff21514d8981	320
AnnaBridge	156:ff21514d8981	321	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
AnnaBridge	156:ff21514d8981	322	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	156:ff21514d8981	323	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
AnnaBridge	156:ff21514d8981	324
AnnaBridge	156:ff21514d8981	325	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
AnnaBridge	156:ff21514d8981	326	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	156:ff21514d8981	327	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
AnnaBridge	156:ff21514d8981	328	}RCC_PLLI2SInitTypeDef;
AnnaBridge	156:ff21514d8981	329
AnnaBridge	156:ff21514d8981	330	/**
AnnaBridge	156:ff21514d8981	331	* @brief PLLSAI Clock structure definition
AnnaBridge	156:ff21514d8981	332	*/
AnnaBridge	156:ff21514d8981	333	typedef struct
AnnaBridge	156:ff21514d8981	334	{
AnnaBridge	156:ff21514d8981	335	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
AnnaBridge	156:ff21514d8981	336	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	156:ff21514d8981	337	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
AnnaBridge	156:ff21514d8981	338	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	339	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks.
AnnaBridge	156:ff21514d8981	340	This parameter is only available in STM32F469xx/STM32F479xx devices.
AnnaBridge	156:ff21514d8981	341	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
AnnaBridge	156:ff21514d8981	342	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	343
AnnaBridge	156:ff21514d8981	344	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
AnnaBridge	156:ff21514d8981	345	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	156:ff21514d8981	346	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
AnnaBridge	156:ff21514d8981	347
AnnaBridge	156:ff21514d8981	348	uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
AnnaBridge	156:ff21514d8981	349	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	156:ff21514d8981	350	This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
AnnaBridge	156:ff21514d8981	351
AnnaBridge	156:ff21514d8981	352	}RCC_PLLSAIInitTypeDef;
AnnaBridge	156:ff21514d8981	353
AnnaBridge	156:ff21514d8981	354	/**
AnnaBridge	156:ff21514d8981	355	* @brief RCC extended clocks structure definition
AnnaBridge	156:ff21514d8981	356	*/
AnnaBridge	156:ff21514d8981	357	typedef struct
AnnaBridge	156:ff21514d8981	358	{
AnnaBridge	156:ff21514d8981	359	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	156:ff21514d8981	360	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	156:ff21514d8981	361
AnnaBridge	156:ff21514d8981	362	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
AnnaBridge	156:ff21514d8981	363	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
AnnaBridge	156:ff21514d8981	364
AnnaBridge	156:ff21514d8981	365	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
AnnaBridge	156:ff21514d8981	366	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
AnnaBridge	156:ff21514d8981	367
AnnaBridge	156:ff21514d8981	368	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
AnnaBridge	156:ff21514d8981	369	This parameter must be a number between Min_Data = 1 and Max_Data = 32
AnnaBridge	156:ff21514d8981	370	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
AnnaBridge	156:ff21514d8981	371
AnnaBridge	156:ff21514d8981	372	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
AnnaBridge	156:ff21514d8981	373	This parameter must be a number between Min_Data = 1 and Max_Data = 32
AnnaBridge	156:ff21514d8981	374	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
AnnaBridge	156:ff21514d8981	375
AnnaBridge	156:ff21514d8981	376	uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
AnnaBridge	156:ff21514d8981	377	This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
AnnaBridge	156:ff21514d8981	378
AnnaBridge	156:ff21514d8981	379	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
AnnaBridge	156:ff21514d8981	380	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	156:ff21514d8981	381
AnnaBridge	156:ff21514d8981	382	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
AnnaBridge	156:ff21514d8981	383	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
AnnaBridge	156:ff21514d8981	384	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	385	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
AnnaBridge	156:ff21514d8981	386	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
AnnaBridge	156:ff21514d8981	387
AnnaBridge	156:ff21514d8981	388	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
AnnaBridge	156:ff21514d8981	389	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
AnnaBridge	156:ff21514d8981	390	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	391	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	156:ff21514d8981	392
AnnaBridge	156:ff21514d8981	393	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	394
AnnaBridge	156:ff21514d8981	395	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
AnnaBridge	156:ff21514d8981	396	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
AnnaBridge	156:ff21514d8981	397	/**
AnnaBridge	156:ff21514d8981	398	* @brief PLLI2S Clock structure definition
AnnaBridge	156:ff21514d8981	399	*/
AnnaBridge	156:ff21514d8981	400	typedef struct
AnnaBridge	156:ff21514d8981	401	{
AnnaBridge	156:ff21514d8981	402	#if defined(STM32F411xE)
AnnaBridge	156:ff21514d8981	403	uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
AnnaBridge	156:ff21514d8981	404	This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
AnnaBridge	156:ff21514d8981	405	#endif /* STM32F411xE */
AnnaBridge	156:ff21514d8981	406
AnnaBridge	156:ff21514d8981	407	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
AnnaBridge	156:ff21514d8981	408	This parameter must be a number between Min_Data = 50 and Max_Data = 432
AnnaBridge	156:ff21514d8981	409	Except for STM32F411xE devices where the Min_Data = 192.
AnnaBridge	156:ff21514d8981	410	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
AnnaBridge	156:ff21514d8981	411
AnnaBridge	156:ff21514d8981	412	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
AnnaBridge	156:ff21514d8981	413	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	156:ff21514d8981	414	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
AnnaBridge	156:ff21514d8981	415
AnnaBridge	156:ff21514d8981	416	}RCC_PLLI2SInitTypeDef;
AnnaBridge	156:ff21514d8981	417
AnnaBridge	156:ff21514d8981	418	/**
AnnaBridge	156:ff21514d8981	419	* @brief RCC extended clocks structure definition
AnnaBridge	156:ff21514d8981	420	*/
AnnaBridge	156:ff21514d8981	421	typedef struct
AnnaBridge	156:ff21514d8981	422	{
AnnaBridge	156:ff21514d8981	423	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	156:ff21514d8981	424	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	156:ff21514d8981	425
AnnaBridge	156:ff21514d8981	426	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
AnnaBridge	156:ff21514d8981	427	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
AnnaBridge	156:ff21514d8981	428
AnnaBridge	156:ff21514d8981	429	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
AnnaBridge	156:ff21514d8981	430	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	156:ff21514d8981	431	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
AnnaBridge	156:ff21514d8981	432	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
AnnaBridge	156:ff21514d8981	433	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
AnnaBridge	156:ff21514d8981	434	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
AnnaBridge	156:ff21514d8981	435	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	156:ff21514d8981	436	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
AnnaBridge	156:ff21514d8981	437	/**
AnnaBridge	156:ff21514d8981	438	* @}
AnnaBridge	156:ff21514d8981	439	*/
AnnaBridge	156:ff21514d8981	440
AnnaBridge	156:ff21514d8981	441	/* Exported constants --------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	442	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
AnnaBridge	156:ff21514d8981	443	* @{
AnnaBridge	156:ff21514d8981	444	*/
AnnaBridge	156:ff21514d8981	445
AnnaBridge	156:ff21514d8981	446	/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
AnnaBridge	156:ff21514d8981	447	* @{
AnnaBridge	156:ff21514d8981	448	*/
AnnaBridge	156:ff21514d8981	449	/* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */
AnnaBridge	156:ff21514d8981	450	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
AnnaBridge	156:ff21514d8981	451	defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	452	#define RCC_PERIPHCLK_I2S_APB1 0x00000001U
AnnaBridge	156:ff21514d8981	453	#define RCC_PERIPHCLK_I2S_APB2 0x00000002U
AnnaBridge	156:ff21514d8981	454	#define RCC_PERIPHCLK_TIM 0x00000004U
AnnaBridge	156:ff21514d8981	455	#define RCC_PERIPHCLK_RTC 0x00000008U
AnnaBridge	156:ff21514d8981	456	#define RCC_PERIPHCLK_FMPI2C1 0x00000010U
AnnaBridge	156:ff21514d8981	457	#define RCC_PERIPHCLK_CLK48 0x00000020U
AnnaBridge	156:ff21514d8981	458	#define RCC_PERIPHCLK_SDIO 0x00000040U
AnnaBridge	156:ff21514d8981	459	#define RCC_PERIPHCLK_PLLI2S 0x00000080U
AnnaBridge	156:ff21514d8981	460	#define RCC_PERIPHCLK_DFSDM1 0x00000100U
AnnaBridge	156:ff21514d8981	461	#define RCC_PERIPHCLK_DFSDM1_AUDIO 0x00000200U
AnnaBridge	156:ff21514d8981	462	#endif /* STM32F412Zx \|\| STM32F412Vx) \|\| STM32F412Rx \|\| STM32F412Cx */
AnnaBridge	156:ff21514d8981	463	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	464	#define RCC_PERIPHCLK_DFSDM2 0x00000400U
AnnaBridge	156:ff21514d8981	465	#define RCC_PERIPHCLK_DFSDM2_AUDIO 0x00000800U
AnnaBridge	156:ff21514d8981	466	#define RCC_PERIPHCLK_LPTIM1 0x00001000U
AnnaBridge	156:ff21514d8981	467	#define RCC_PERIPHCLK_SAIA 0x00002000U
AnnaBridge	156:ff21514d8981	468	#define RCC_PERIPHCLK_SAIB 0x00004000U
AnnaBridge	156:ff21514d8981	469	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	470	/----------------------------------------------------------------------------/
AnnaBridge	156:ff21514d8981	471
AnnaBridge	156:ff21514d8981	472	/------------------- Peripheral Clock source for STM32F410xx ----------------/
AnnaBridge	156:ff21514d8981	473	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	156:ff21514d8981	474	#define RCC_PERIPHCLK_I2S 0x00000001U
AnnaBridge	156:ff21514d8981	475	#define RCC_PERIPHCLK_TIM 0x00000002U
AnnaBridge	156:ff21514d8981	476	#define RCC_PERIPHCLK_RTC 0x00000004U
AnnaBridge	156:ff21514d8981	477	#define RCC_PERIPHCLK_FMPI2C1 0x00000008U
AnnaBridge	156:ff21514d8981	478	#define RCC_PERIPHCLK_LPTIM1 0x00000010U
AnnaBridge	156:ff21514d8981	479	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	156:ff21514d8981	480	/----------------------------------------------------------------------------/
AnnaBridge	156:ff21514d8981	481
AnnaBridge	156:ff21514d8981	482	/------------------- Peripheral Clock source for STM32F446xx ----------------/
AnnaBridge	156:ff21514d8981	483	#if defined(STM32F446xx)
AnnaBridge	156:ff21514d8981	484	#define RCC_PERIPHCLK_I2S_APB1 0x00000001U
AnnaBridge	156:ff21514d8981	485	#define RCC_PERIPHCLK_I2S_APB2 0x00000002U
AnnaBridge	156:ff21514d8981	486	#define RCC_PERIPHCLK_SAI1 0x00000004U
AnnaBridge	156:ff21514d8981	487	#define RCC_PERIPHCLK_SAI2 0x00000008U
AnnaBridge	156:ff21514d8981	488	#define RCC_PERIPHCLK_TIM 0x00000010U
AnnaBridge	156:ff21514d8981	489	#define RCC_PERIPHCLK_RTC 0x00000020U
AnnaBridge	156:ff21514d8981	490	#define RCC_PERIPHCLK_CEC 0x00000040U
AnnaBridge	156:ff21514d8981	491	#define RCC_PERIPHCLK_FMPI2C1 0x00000080U
AnnaBridge	156:ff21514d8981	492	#define RCC_PERIPHCLK_CLK48 0x00000100U
AnnaBridge	156:ff21514d8981	493	#define RCC_PERIPHCLK_SDIO 0x00000200U
AnnaBridge	156:ff21514d8981	494	#define RCC_PERIPHCLK_SPDIFRX 0x00000400U
AnnaBridge	156:ff21514d8981	495	#define RCC_PERIPHCLK_PLLI2S 0x00000800U
AnnaBridge	156:ff21514d8981	496	#endif /* STM32F446xx */
AnnaBridge	156:ff21514d8981	497	/-----------------------------------------------------------------------------/
AnnaBridge	156:ff21514d8981	498
AnnaBridge	156:ff21514d8981	499	/----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------/
AnnaBridge	156:ff21514d8981	500	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	501	#define RCC_PERIPHCLK_I2S 0x00000001U
AnnaBridge	156:ff21514d8981	502	#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U
AnnaBridge	156:ff21514d8981	503	#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U
AnnaBridge	156:ff21514d8981	504	#define RCC_PERIPHCLK_LTDC 0x00000008U
AnnaBridge	156:ff21514d8981	505	#define RCC_PERIPHCLK_TIM 0x00000010U
AnnaBridge	156:ff21514d8981	506	#define RCC_PERIPHCLK_RTC 0x00000020U
AnnaBridge	156:ff21514d8981	507	#define RCC_PERIPHCLK_PLLI2S 0x00000040U
AnnaBridge	156:ff21514d8981	508	#define RCC_PERIPHCLK_CLK48 0x00000080U
AnnaBridge	156:ff21514d8981	509	#define RCC_PERIPHCLK_SDIO 0x00000100U
AnnaBridge	156:ff21514d8981	510	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	511	/----------------------------------------------------------------------------/
AnnaBridge	156:ff21514d8981	512
AnnaBridge	156:ff21514d8981	513	/-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------/
AnnaBridge	156:ff21514d8981	514	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
AnnaBridge	156:ff21514d8981	515	#define RCC_PERIPHCLK_I2S 0x00000001U
AnnaBridge	156:ff21514d8981	516	#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U
AnnaBridge	156:ff21514d8981	517	#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U
AnnaBridge	156:ff21514d8981	518	#define RCC_PERIPHCLK_LTDC 0x00000008U
AnnaBridge	156:ff21514d8981	519	#define RCC_PERIPHCLK_TIM 0x00000010U
AnnaBridge	156:ff21514d8981	520	#define RCC_PERIPHCLK_RTC 0x00000020U
AnnaBridge	156:ff21514d8981	521	#define RCC_PERIPHCLK_PLLI2S 0x00000040U
AnnaBridge	156:ff21514d8981	522	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
AnnaBridge	156:ff21514d8981	523	/----------------------------------------------------------------------------/
AnnaBridge	156:ff21514d8981	524
AnnaBridge	156:ff21514d8981	525	/-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------/
AnnaBridge	156:ff21514d8981	526	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
AnnaBridge	156:ff21514d8981	527	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
AnnaBridge	156:ff21514d8981	528	#define RCC_PERIPHCLK_I2S 0x00000001U
AnnaBridge	156:ff21514d8981	529	#define RCC_PERIPHCLK_RTC 0x00000002U
AnnaBridge	156:ff21514d8981	530	#define RCC_PERIPHCLK_PLLI2S 0x00000004U
AnnaBridge	156:ff21514d8981	531	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
AnnaBridge	156:ff21514d8981	532	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
AnnaBridge	156:ff21514d8981	533	#define RCC_PERIPHCLK_TIM 0x00000008U
AnnaBridge	156:ff21514d8981	534	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
AnnaBridge	156:ff21514d8981	535	/----------------------------------------------------------------------------/
AnnaBridge	156:ff21514d8981	536	/**
AnnaBridge	156:ff21514d8981	537	* @}
AnnaBridge	156:ff21514d8981	538	*/
AnnaBridge	156:ff21514d8981	539	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
AnnaBridge	156:ff21514d8981	540	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
AnnaBridge	156:ff21514d8981	541	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F469xx) \|\| \
AnnaBridge	156:ff21514d8981	542	defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	543	/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
AnnaBridge	156:ff21514d8981	544	* @{
AnnaBridge	156:ff21514d8981	545	*/
AnnaBridge	156:ff21514d8981	546	#define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U
AnnaBridge	156:ff21514d8981	547	#define RCC_I2SCLKSOURCE_EXT 0x00000001U
AnnaBridge	156:ff21514d8981	548	/**
AnnaBridge	156:ff21514d8981	549	* @}
AnnaBridge	156:ff21514d8981	550	*/
AnnaBridge	156:ff21514d8981	551	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
AnnaBridge	156:ff21514d8981	552	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	553
AnnaBridge	156:ff21514d8981	554	/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
AnnaBridge	156:ff21514d8981	555	* @{
AnnaBridge	156:ff21514d8981	556	*/
AnnaBridge	156:ff21514d8981	557	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\|\
AnnaBridge	156:ff21514d8981	558	defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	559	#define RCC_PLLSAIDIVR_2 0x00000000U
AnnaBridge	156:ff21514d8981	560	#define RCC_PLLSAIDIVR_4 0x00010000U
AnnaBridge	156:ff21514d8981	561	#define RCC_PLLSAIDIVR_8 0x00020000U
AnnaBridge	156:ff21514d8981	562	#define RCC_PLLSAIDIVR_16 0x00030000U
AnnaBridge	156:ff21514d8981	563	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	564	/**
AnnaBridge	156:ff21514d8981	565	* @}
AnnaBridge	156:ff21514d8981	566	*/
AnnaBridge	156:ff21514d8981	567
AnnaBridge	156:ff21514d8981	568	/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
AnnaBridge	156:ff21514d8981	569	* @{
AnnaBridge	156:ff21514d8981	570	*/
AnnaBridge	156:ff21514d8981	571	#if defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	156:ff21514d8981	572	defined(STM32F412Rx) \|\| defined(STM32F412Cx)
AnnaBridge	156:ff21514d8981	573	#define RCC_PLLI2SP_DIV2 0x00000002U
AnnaBridge	156:ff21514d8981	574	#define RCC_PLLI2SP_DIV4 0x00000004U
AnnaBridge	156:ff21514d8981	575	#define RCC_PLLI2SP_DIV6 0x00000006U
AnnaBridge	156:ff21514d8981	576	#define RCC_PLLI2SP_DIV8 0x00000008U
AnnaBridge	156:ff21514d8981	577	#endif /* STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
AnnaBridge	156:ff21514d8981	578	/**
AnnaBridge	156:ff21514d8981	579	* @}
AnnaBridge	156:ff21514d8981	580	*/
AnnaBridge	156:ff21514d8981	581
AnnaBridge	156:ff21514d8981	582	/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
AnnaBridge	156:ff21514d8981	583	* @{
AnnaBridge	156:ff21514d8981	584	*/
AnnaBridge	156:ff21514d8981	585	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	586	#define RCC_PLLSAIP_DIV2 0x00000002U
AnnaBridge	156:ff21514d8981	587	#define RCC_PLLSAIP_DIV4 0x00000004U
AnnaBridge	156:ff21514d8981	588	#define RCC_PLLSAIP_DIV6 0x00000006U
AnnaBridge	156:ff21514d8981	589	#define RCC_PLLSAIP_DIV8 0x00000008U
AnnaBridge	156:ff21514d8981	590	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	591	/**
AnnaBridge	156:ff21514d8981	592	* @}
AnnaBridge	156:ff21514d8981	593	*/
AnnaBridge	156:ff21514d8981	594
AnnaBridge	156:ff21514d8981	595	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	596	/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source
AnnaBridge	156:ff21514d8981	597	* @{
AnnaBridge	156:ff21514d8981	598	*/
AnnaBridge	156:ff21514d8981	599	#define RCC_SAIACLKSOURCE_PLLSAI 0x00000000U
AnnaBridge	156:ff21514d8981	600	#define RCC_SAIACLKSOURCE_PLLI2S 0x00100000U
AnnaBridge	156:ff21514d8981	601	#define RCC_SAIACLKSOURCE_EXT 0x00200000U
AnnaBridge	156:ff21514d8981	602	/**
AnnaBridge	156:ff21514d8981	603	* @}
AnnaBridge	156:ff21514d8981	604	*/
AnnaBridge	156:ff21514d8981	605
AnnaBridge	156:ff21514d8981	606	/** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source
AnnaBridge	156:ff21514d8981	607	* @{
AnnaBridge	156:ff21514d8981	608	*/
AnnaBridge	156:ff21514d8981	609	#define RCC_SAIBCLKSOURCE_PLLSAI 0x00000000U
AnnaBridge	156:ff21514d8981	610	#define RCC_SAIBCLKSOURCE_PLLI2S 0x00400000U
AnnaBridge	156:ff21514d8981	611	#define RCC_SAIBCLKSOURCE_EXT 0x00800000U
AnnaBridge	156:ff21514d8981	612	/**
AnnaBridge	156:ff21514d8981	613	* @}
AnnaBridge	156:ff21514d8981	614	*/
AnnaBridge	156:ff21514d8981	615	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	616
AnnaBridge	156:ff21514d8981	617	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	618	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
AnnaBridge	156:ff21514d8981	619	* @{
AnnaBridge	156:ff21514d8981	620	*/
AnnaBridge	156:ff21514d8981	621	#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
AnnaBridge	156:ff21514d8981	622	#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL)
AnnaBridge	156:ff21514d8981	623	/**
AnnaBridge	156:ff21514d8981	624	* @}
AnnaBridge	156:ff21514d8981	625	*/
AnnaBridge	156:ff21514d8981	626
AnnaBridge	156:ff21514d8981	627	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
AnnaBridge	156:ff21514d8981	628	* @{
AnnaBridge	156:ff21514d8981	629	*/
AnnaBridge	156:ff21514d8981	630	#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
AnnaBridge	156:ff21514d8981	631	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL)
AnnaBridge	156:ff21514d8981	632	/**
AnnaBridge	156:ff21514d8981	633	* @}
AnnaBridge	156:ff21514d8981	634	*/
AnnaBridge	156:ff21514d8981	635
AnnaBridge	156:ff21514d8981	636	/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source
AnnaBridge	156:ff21514d8981	637	* @{
AnnaBridge	156:ff21514d8981	638	*/
AnnaBridge	156:ff21514d8981	639	#define RCC_DSICLKSOURCE_DSIPHY 0x00000000U
AnnaBridge	156:ff21514d8981	640	#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL)
AnnaBridge	156:ff21514d8981	641	/**
AnnaBridge	156:ff21514d8981	642	* @}
AnnaBridge	156:ff21514d8981	643	*/
AnnaBridge	156:ff21514d8981	644	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	645
AnnaBridge	156:ff21514d8981	646	#if defined(STM32F446xx)
AnnaBridge	156:ff21514d8981	647	/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source
AnnaBridge	156:ff21514d8981	648	* @{
AnnaBridge	156:ff21514d8981	649	*/
AnnaBridge	156:ff21514d8981	650	#define RCC_SAI1CLKSOURCE_PLLSAI 0x00000000U
AnnaBridge	156:ff21514d8981	651	#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
AnnaBridge	156:ff21514d8981	652	#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
AnnaBridge	156:ff21514d8981	653	#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
AnnaBridge	156:ff21514d8981	654	/**
AnnaBridge	156:ff21514d8981	655	* @}
AnnaBridge	156:ff21514d8981	656	*/
AnnaBridge	156:ff21514d8981	657
AnnaBridge	156:ff21514d8981	658	/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source
AnnaBridge	156:ff21514d8981	659	* @{
AnnaBridge	156:ff21514d8981	660	*/
AnnaBridge	156:ff21514d8981	661	#define RCC_SAI2CLKSOURCE_PLLSAI 0x00000000U
AnnaBridge	156:ff21514d8981	662	#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
AnnaBridge	156:ff21514d8981	663	#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
AnnaBridge	156:ff21514d8981	664	#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
AnnaBridge	156:ff21514d8981	665	/**
AnnaBridge	156:ff21514d8981	666	* @}
AnnaBridge	156:ff21514d8981	667	*/
AnnaBridge	156:ff21514d8981	668
AnnaBridge	156:ff21514d8981	669	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
AnnaBridge	156:ff21514d8981	670	* @{
AnnaBridge	156:ff21514d8981	671	*/
AnnaBridge	156:ff21514d8981	672	#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U
AnnaBridge	156:ff21514d8981	673	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
AnnaBridge	156:ff21514d8981	674	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
AnnaBridge	156:ff21514d8981	675	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
AnnaBridge	156:ff21514d8981	676	/**
AnnaBridge	156:ff21514d8981	677	* @}
AnnaBridge	156:ff21514d8981	678	*/
AnnaBridge	156:ff21514d8981	679
AnnaBridge	156:ff21514d8981	680	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
AnnaBridge	156:ff21514d8981	681	* @{
AnnaBridge	156:ff21514d8981	682	*/
AnnaBridge	156:ff21514d8981	683	#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U
AnnaBridge	156:ff21514d8981	684	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
AnnaBridge	156:ff21514d8981	685	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
AnnaBridge	156:ff21514d8981	686	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
AnnaBridge	156:ff21514d8981	687	/**
AnnaBridge	156:ff21514d8981	688	* @}
AnnaBridge	156:ff21514d8981	689	*/
AnnaBridge	156:ff21514d8981	690
AnnaBridge	156:ff21514d8981	691	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
AnnaBridge	156:ff21514d8981	692	* @{
AnnaBridge	156:ff21514d8981	693	*/
AnnaBridge	156:ff21514d8981	694	#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	156:ff21514d8981	695	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
AnnaBridge	156:ff21514d8981	696	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
AnnaBridge	156:ff21514d8981	697	/**
AnnaBridge	156:ff21514d8981	698	* @}
AnnaBridge	156:ff21514d8981	699	*/
AnnaBridge	156:ff21514d8981	700
AnnaBridge	156:ff21514d8981	701	/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source
AnnaBridge	156:ff21514d8981	702	* @{
AnnaBridge	156:ff21514d8981	703	*/
AnnaBridge	156:ff21514d8981	704	#define RCC_CECCLKSOURCE_HSI 0x00000000U
AnnaBridge	156:ff21514d8981	705	#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
AnnaBridge	156:ff21514d8981	706	/**
AnnaBridge	156:ff21514d8981	707	* @}
AnnaBridge	156:ff21514d8981	708	*/
AnnaBridge	156:ff21514d8981	709
AnnaBridge	156:ff21514d8981	710	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
AnnaBridge	156:ff21514d8981	711	* @{
AnnaBridge	156:ff21514d8981	712	*/
AnnaBridge	156:ff21514d8981	713	#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
AnnaBridge	156:ff21514d8981	714	#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
AnnaBridge	156:ff21514d8981	715	/**
AnnaBridge	156:ff21514d8981	716	* @}
AnnaBridge	156:ff21514d8981	717	*/
AnnaBridge	156:ff21514d8981	718
AnnaBridge	156:ff21514d8981	719	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
AnnaBridge	156:ff21514d8981	720	* @{
AnnaBridge	156:ff21514d8981	721	*/
AnnaBridge	156:ff21514d8981	722	#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
AnnaBridge	156:ff21514d8981	723	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
AnnaBridge	156:ff21514d8981	724	/**
AnnaBridge	156:ff21514d8981	725	* @}
AnnaBridge	156:ff21514d8981	726	*/
AnnaBridge	156:ff21514d8981	727
AnnaBridge	156:ff21514d8981	728	/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source
AnnaBridge	156:ff21514d8981	729	* @{
AnnaBridge	156:ff21514d8981	730	*/
AnnaBridge	156:ff21514d8981	731	#define RCC_SPDIFRXCLKSOURCE_PLLR 0x00000000U
AnnaBridge	156:ff21514d8981	732	#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
AnnaBridge	156:ff21514d8981	733	/**
AnnaBridge	156:ff21514d8981	734	* @}
AnnaBridge	156:ff21514d8981	735	*/
AnnaBridge	163:e59c8e839560	736
AnnaBridge	156:ff21514d8981	737	#endif /* STM32F446xx */
AnnaBridge	156:ff21514d8981	738
AnnaBridge	156:ff21514d8981	739	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	740	/** @defgroup RCCEx_SAI1_BlockA_Clock_Source RCC SAI BlockA Clock Source
AnnaBridge	156:ff21514d8981	741	* @{
AnnaBridge	156:ff21514d8981	742	*/
AnnaBridge	156:ff21514d8981	743	#define RCC_SAIACLKSOURCE_PLLI2SR 0x00000000U
AnnaBridge	156:ff21514d8981	744	#define RCC_SAIACLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0)
AnnaBridge	156:ff21514d8981	745	#define RCC_SAIACLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1)
AnnaBridge	156:ff21514d8981	746	#define RCC_SAIACLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 \| RCC_DCKCFGR_SAI1ASRC_1)
AnnaBridge	156:ff21514d8981	747	/**
AnnaBridge	156:ff21514d8981	748	* @}
AnnaBridge	156:ff21514d8981	749	*/
AnnaBridge	156:ff21514d8981	750
AnnaBridge	156:ff21514d8981	751	/** @defgroup RCCEx_SAI1_BlockB_Clock_Source RCC SAI BlockB Clock Source
AnnaBridge	156:ff21514d8981	752	* @{
AnnaBridge	156:ff21514d8981	753	*/
AnnaBridge	156:ff21514d8981	754	#define RCC_SAIBCLKSOURCE_PLLI2SR 0x00000000U
AnnaBridge	156:ff21514d8981	755	#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0)
AnnaBridge	156:ff21514d8981	756	#define RCC_SAIBCLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1)
AnnaBridge	156:ff21514d8981	757	#define RCC_SAIBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 \| RCC_DCKCFGR_SAI1BSRC_1)
AnnaBridge	156:ff21514d8981	758	/**
AnnaBridge	156:ff21514d8981	759	* @}
AnnaBridge	156:ff21514d8981	760	*/
AnnaBridge	156:ff21514d8981	761
AnnaBridge	156:ff21514d8981	762	/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
AnnaBridge	156:ff21514d8981	763	* @{
AnnaBridge	156:ff21514d8981	764	*/
AnnaBridge	156:ff21514d8981	765	#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	156:ff21514d8981	766	#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
AnnaBridge	156:ff21514d8981	767	#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
AnnaBridge	156:ff21514d8981	768	#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 \| RCC_DCKCFGR2_LPTIM1SEL_1)
AnnaBridge	156:ff21514d8981	769	/**
AnnaBridge	156:ff21514d8981	770	* @}
AnnaBridge	156:ff21514d8981	771	*/
AnnaBridge	156:ff21514d8981	772
AnnaBridge	156:ff21514d8981	773
AnnaBridge	156:ff21514d8981	774	/** @defgroup RCCEx_DFSDM2_Audio_Clock_Source RCC DFSDM2 Audio Clock Source
AnnaBridge	156:ff21514d8981	775	* @{
AnnaBridge	156:ff21514d8981	776	*/
AnnaBridge	156:ff21514d8981	777	#define RCC_DFSDM2AUDIOCLKSOURCE_I2S1 0x00000000U
AnnaBridge	156:ff21514d8981	778	#define RCC_DFSDM2AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL)
AnnaBridge	156:ff21514d8981	779	/**
AnnaBridge	156:ff21514d8981	780	* @}
AnnaBridge	156:ff21514d8981	781	*/
AnnaBridge	156:ff21514d8981	782
AnnaBridge	156:ff21514d8981	783	/** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source RCC DFSDM2 Kernel Clock Source
AnnaBridge	156:ff21514d8981	784	* @{
AnnaBridge	156:ff21514d8981	785	*/
AnnaBridge	156:ff21514d8981	786	#define RCC_DFSDM2CLKSOURCE_PCLK2 0x00000000U
AnnaBridge	156:ff21514d8981	787	#define RCC_DFSDM2CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
AnnaBridge	156:ff21514d8981	788	/**
AnnaBridge	156:ff21514d8981	789	* @}
AnnaBridge	156:ff21514d8981	790	*/
AnnaBridge	156:ff21514d8981	791
AnnaBridge	156:ff21514d8981	792	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	793
AnnaBridge	156:ff21514d8981	794	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	795	/** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source
AnnaBridge	156:ff21514d8981	796	* @{
AnnaBridge	156:ff21514d8981	797	*/
AnnaBridge	156:ff21514d8981	798	#define RCC_PLLI2SCLKSOURCE_PLLSRC 0x00000000U
AnnaBridge	156:ff21514d8981	799	#define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC)
AnnaBridge	156:ff21514d8981	800	/**
AnnaBridge	156:ff21514d8981	801	* @}
AnnaBridge	156:ff21514d8981	802	*/
AnnaBridge	156:ff21514d8981	803
AnnaBridge	156:ff21514d8981	804	/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source RCC DFSDM1 Audio Clock Source
AnnaBridge	156:ff21514d8981	805	* @{
AnnaBridge	156:ff21514d8981	806	*/
AnnaBridge	156:ff21514d8981	807	#define RCC_DFSDM1AUDIOCLKSOURCE_I2S1 0x00000000U
AnnaBridge	156:ff21514d8981	808	#define RCC_DFSDM1AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
AnnaBridge	156:ff21514d8981	809	/**
AnnaBridge	156:ff21514d8981	810	* @}
AnnaBridge	156:ff21514d8981	811	*/
AnnaBridge	156:ff21514d8981	812
AnnaBridge	156:ff21514d8981	813	/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCC DFSDM1 Kernel Clock Source
AnnaBridge	156:ff21514d8981	814	* @{
AnnaBridge	156:ff21514d8981	815	*/
AnnaBridge	156:ff21514d8981	816	#define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U
AnnaBridge	156:ff21514d8981	817	#define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
AnnaBridge	156:ff21514d8981	818	/**
AnnaBridge	156:ff21514d8981	819	* @}
AnnaBridge	156:ff21514d8981	820	*/
AnnaBridge	156:ff21514d8981	821
AnnaBridge	156:ff21514d8981	822	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
AnnaBridge	156:ff21514d8981	823	* @{
AnnaBridge	156:ff21514d8981	824	*/
AnnaBridge	156:ff21514d8981	825	#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U
AnnaBridge	156:ff21514d8981	826	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
AnnaBridge	156:ff21514d8981	827	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
AnnaBridge	156:ff21514d8981	828	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
AnnaBridge	156:ff21514d8981	829	/**
AnnaBridge	156:ff21514d8981	830	* @}
AnnaBridge	156:ff21514d8981	831	*/
AnnaBridge	156:ff21514d8981	832
AnnaBridge	156:ff21514d8981	833	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
AnnaBridge	156:ff21514d8981	834	* @{
AnnaBridge	156:ff21514d8981	835	*/
AnnaBridge	156:ff21514d8981	836	#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U
AnnaBridge	156:ff21514d8981	837	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
AnnaBridge	156:ff21514d8981	838	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
AnnaBridge	156:ff21514d8981	839	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
AnnaBridge	156:ff21514d8981	840	/**
AnnaBridge	156:ff21514d8981	841	* @}
AnnaBridge	156:ff21514d8981	842	*/
AnnaBridge	156:ff21514d8981	843
AnnaBridge	156:ff21514d8981	844	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
AnnaBridge	156:ff21514d8981	845	* @{
AnnaBridge	156:ff21514d8981	846	*/
AnnaBridge	156:ff21514d8981	847	#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	156:ff21514d8981	848	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
AnnaBridge	156:ff21514d8981	849	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
AnnaBridge	156:ff21514d8981	850	/**
AnnaBridge	156:ff21514d8981	851	* @}
AnnaBridge	156:ff21514d8981	852	*/
AnnaBridge	156:ff21514d8981	853
AnnaBridge	156:ff21514d8981	854	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
AnnaBridge	156:ff21514d8981	855	* @{
AnnaBridge	156:ff21514d8981	856	*/
AnnaBridge	156:ff21514d8981	857	#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U
AnnaBridge	156:ff21514d8981	858	#define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
AnnaBridge	156:ff21514d8981	859	/**
AnnaBridge	156:ff21514d8981	860	* @}
AnnaBridge	156:ff21514d8981	861	*/
AnnaBridge	156:ff21514d8981	862
AnnaBridge	156:ff21514d8981	863	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
AnnaBridge	156:ff21514d8981	864	* @{
AnnaBridge	156:ff21514d8981	865	*/
AnnaBridge	156:ff21514d8981	866	#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U
AnnaBridge	156:ff21514d8981	867	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
AnnaBridge	156:ff21514d8981	868	/**
AnnaBridge	156:ff21514d8981	869	* @}
AnnaBridge	156:ff21514d8981	870	*/
AnnaBridge	156:ff21514d8981	871	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	872
AnnaBridge	156:ff21514d8981	873	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	163:e59c8e839560	874
AnnaBridge	156:ff21514d8981	875	/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
AnnaBridge	156:ff21514d8981	876	* @{
AnnaBridge	156:ff21514d8981	877	*/
AnnaBridge	156:ff21514d8981	878	#define RCC_I2SAPBCLKSOURCE_PLLR 0x00000000U
AnnaBridge	156:ff21514d8981	879	#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
AnnaBridge	156:ff21514d8981	880	#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
AnnaBridge	156:ff21514d8981	881	/**
AnnaBridge	156:ff21514d8981	882	* @}
AnnaBridge	156:ff21514d8981	883	*/
AnnaBridge	156:ff21514d8981	884
AnnaBridge	156:ff21514d8981	885	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
AnnaBridge	156:ff21514d8981	886	* @{
AnnaBridge	156:ff21514d8981	887	*/
AnnaBridge	156:ff21514d8981	888	#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	156:ff21514d8981	889	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
AnnaBridge	156:ff21514d8981	890	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
AnnaBridge	156:ff21514d8981	891	/**
AnnaBridge	156:ff21514d8981	892	* @}
AnnaBridge	156:ff21514d8981	893	*/
AnnaBridge	156:ff21514d8981	894
AnnaBridge	156:ff21514d8981	895	/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
AnnaBridge	156:ff21514d8981	896	* @{
AnnaBridge	156:ff21514d8981	897	*/
AnnaBridge	156:ff21514d8981	898	#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	156:ff21514d8981	899	#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
AnnaBridge	156:ff21514d8981	900	#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
AnnaBridge	156:ff21514d8981	901	#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 \| RCC_DCKCFGR2_LPTIM1SEL_1)
AnnaBridge	156:ff21514d8981	902	/**
AnnaBridge	156:ff21514d8981	903	* @}
AnnaBridge	156:ff21514d8981	904	*/
AnnaBridge	156:ff21514d8981	905	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	156:ff21514d8981	906
AnnaBridge	156:ff21514d8981	907	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
AnnaBridge	156:ff21514d8981	908	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
AnnaBridge	156:ff21514d8981	909	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
AnnaBridge	156:ff21514d8981	910	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
AnnaBridge	156:ff21514d8981	911	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	912	/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
AnnaBridge	156:ff21514d8981	913	* @{
AnnaBridge	156:ff21514d8981	914	*/
AnnaBridge	156:ff21514d8981	915	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
AnnaBridge	156:ff21514d8981	916	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
AnnaBridge	156:ff21514d8981	917	/**
AnnaBridge	156:ff21514d8981	918	* @}
AnnaBridge	156:ff21514d8981	919	*/
AnnaBridge	156:ff21514d8981	920	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\|\
AnnaBridge	156:ff21514d8981	921	STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\|\
AnnaBridge	156:ff21514d8981	922	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	923
AnnaBridge	156:ff21514d8981	924	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\|\
AnnaBridge	156:ff21514d8981	925	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
AnnaBridge	156:ff21514d8981	926	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\|\
AnnaBridge	156:ff21514d8981	927	defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	928	/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection
AnnaBridge	156:ff21514d8981	929	* @{
AnnaBridge	156:ff21514d8981	930	*/
AnnaBridge	156:ff21514d8981	931	#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
AnnaBridge	156:ff21514d8981	932	#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
AnnaBridge	156:ff21514d8981	933	/**
AnnaBridge	156:ff21514d8981	934	* @}
AnnaBridge	156:ff21514d8981	935	*/
AnnaBridge	156:ff21514d8981	936	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|\
AnnaBridge	156:ff21514d8981	937	STM32F412Rx \|\| STM32F412Cx */
AnnaBridge	156:ff21514d8981	938
AnnaBridge	156:ff21514d8981	939	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
AnnaBridge	156:ff21514d8981	940	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
AnnaBridge	156:ff21514d8981	941	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
AnnaBridge	156:ff21514d8981	942	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	156:ff21514d8981	943	defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	944	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
AnnaBridge	156:ff21514d8981	945	* @{
AnnaBridge	156:ff21514d8981	946	*/
AnnaBridge	156:ff21514d8981	947	#define RCC_MCO2SOURCE_SYSCLK 0x00000000U
AnnaBridge	156:ff21514d8981	948	#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
AnnaBridge	156:ff21514d8981	949	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
AnnaBridge	156:ff21514d8981	950	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
AnnaBridge	156:ff21514d8981	951	/**
AnnaBridge	156:ff21514d8981	952	* @}
AnnaBridge	156:ff21514d8981	953	*/
AnnaBridge	156:ff21514d8981	954	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
AnnaBridge	156:ff21514d8981	955	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
AnnaBridge	156:ff21514d8981	956	STM32F412Rx \|\| STM32F413xx \| STM32F423xx */
AnnaBridge	156:ff21514d8981	957
AnnaBridge	156:ff21514d8981	958	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	156:ff21514d8981	959	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
AnnaBridge	156:ff21514d8981	960	* @{
AnnaBridge	156:ff21514d8981	961	*/
AnnaBridge	156:ff21514d8981	962	#define RCC_MCO2SOURCE_SYSCLK 0x00000000U
AnnaBridge	156:ff21514d8981	963	#define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0
AnnaBridge	156:ff21514d8981	964	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
AnnaBridge	156:ff21514d8981	965	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
AnnaBridge	156:ff21514d8981	966	/**
AnnaBridge	156:ff21514d8981	967	* @}
AnnaBridge	156:ff21514d8981	968	*/
AnnaBridge	156:ff21514d8981	969	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	156:ff21514d8981	970
AnnaBridge	156:ff21514d8981	971	/**
AnnaBridge	156:ff21514d8981	972	* @}
AnnaBridge	156:ff21514d8981	973	*/
AnnaBridge	156:ff21514d8981	974
AnnaBridge	156:ff21514d8981	975	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	976	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
AnnaBridge	156:ff21514d8981	977	* @{
AnnaBridge	156:ff21514d8981	978	*/
AnnaBridge	156:ff21514d8981	979	/------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------/
AnnaBridge	156:ff21514d8981	980	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	981	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	982	* @brief Enables or disables the AHB1 peripheral clock.
AnnaBridge	156:ff21514d8981	983	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	984	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	985	* using it.
AnnaBridge	156:ff21514d8981	986	* @{
AnnaBridge	156:ff21514d8981	987	*/
AnnaBridge	156:ff21514d8981	988	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	989	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	990	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
AnnaBridge	156:ff21514d8981	991	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	992	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
AnnaBridge	156:ff21514d8981	993	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	994	} while(0U)
AnnaBridge	156:ff21514d8981	995	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	996	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	997	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
AnnaBridge	156:ff21514d8981	998	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	999	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
AnnaBridge	156:ff21514d8981	1000	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1001	} while(0U)
AnnaBridge	156:ff21514d8981	1002	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1003	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1004	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	156:ff21514d8981	1005	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1006	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	156:ff21514d8981	1007	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1008	} while(0U)
AnnaBridge	156:ff21514d8981	1009	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1010	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1011	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	156:ff21514d8981	1012	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1013	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	156:ff21514d8981	1014	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1015	} while(0U)
AnnaBridge	156:ff21514d8981	1016	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1017	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1018	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	156:ff21514d8981	1019	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1020	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	156:ff21514d8981	1021	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1022	} while(0U)
AnnaBridge	156:ff21514d8981	1023	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1024	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1025	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
AnnaBridge	156:ff21514d8981	1026	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1027	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
AnnaBridge	156:ff21514d8981	1028	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1029	} while(0U)
AnnaBridge	156:ff21514d8981	1030	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1031	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1032	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge	156:ff21514d8981	1033	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1034	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge	156:ff21514d8981	1035	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1036	} while(0U)
AnnaBridge	156:ff21514d8981	1037	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1038	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1039	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge	156:ff21514d8981	1040	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1041	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge	156:ff21514d8981	1042	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1043	} while(0U)
AnnaBridge	156:ff21514d8981	1044	#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1045	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1046	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
AnnaBridge	156:ff21514d8981	1047	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1048	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
AnnaBridge	156:ff21514d8981	1049	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1050	} while(0U)
AnnaBridge	156:ff21514d8981	1051	#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1052	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1053	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
AnnaBridge	156:ff21514d8981	1054	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1055	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
AnnaBridge	156:ff21514d8981	1056	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1057	} while(0U)
AnnaBridge	156:ff21514d8981	1058	#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1059	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1060	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
AnnaBridge	156:ff21514d8981	1061	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1062	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
AnnaBridge	156:ff21514d8981	1063	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1064	} while(0U)
AnnaBridge	156:ff21514d8981	1065	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1066	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1067	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
AnnaBridge	156:ff21514d8981	1068	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1069	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
AnnaBridge	156:ff21514d8981	1070	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1071	} while(0U)
AnnaBridge	156:ff21514d8981	1072	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1073	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1074	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
AnnaBridge	156:ff21514d8981	1075	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1076	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
AnnaBridge	156:ff21514d8981	1077	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1078	} while(0U)
AnnaBridge	156:ff21514d8981	1079	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1080	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1081	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
AnnaBridge	156:ff21514d8981	1082	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1083	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
AnnaBridge	156:ff21514d8981	1084	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1085	} while(0U)
AnnaBridge	156:ff21514d8981	1086	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1087	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1088	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
AnnaBridge	156:ff21514d8981	1089	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1090	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
AnnaBridge	156:ff21514d8981	1091	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1092	} while(0U)
AnnaBridge	156:ff21514d8981	1093	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1094	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1095	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
AnnaBridge	156:ff21514d8981	1096	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1097	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
AnnaBridge	156:ff21514d8981	1098	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1099	} while(0U)
AnnaBridge	156:ff21514d8981	1100	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1101	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1102	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
AnnaBridge	156:ff21514d8981	1103	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1104	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
AnnaBridge	156:ff21514d8981	1105	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1106	} while(0U)
AnnaBridge	156:ff21514d8981	1107	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
AnnaBridge	156:ff21514d8981	1108	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
AnnaBridge	156:ff21514d8981	1109	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
AnnaBridge	156:ff21514d8981	1110	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
AnnaBridge	156:ff21514d8981	1111	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
AnnaBridge	156:ff21514d8981	1112	#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
AnnaBridge	156:ff21514d8981	1113	#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
AnnaBridge	156:ff21514d8981	1114	#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
AnnaBridge	156:ff21514d8981	1115	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
AnnaBridge	156:ff21514d8981	1116	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
AnnaBridge	156:ff21514d8981	1117	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
AnnaBridge	156:ff21514d8981	1118	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
AnnaBridge	156:ff21514d8981	1119	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
AnnaBridge	156:ff21514d8981	1120	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
AnnaBridge	156:ff21514d8981	1121	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
AnnaBridge	156:ff21514d8981	1122	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
AnnaBridge	156:ff21514d8981	1123	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
AnnaBridge	156:ff21514d8981	1124
AnnaBridge	156:ff21514d8981	1125	/**
AnnaBridge	156:ff21514d8981	1126	* @brief Enable ETHERNET clock.
AnnaBridge	156:ff21514d8981	1127	*/
AnnaBridge	156:ff21514d8981	1128	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1129	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
AnnaBridge	156:ff21514d8981	1130	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
AnnaBridge	156:ff21514d8981	1131	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
AnnaBridge	156:ff21514d8981	1132	} while(0U)
AnnaBridge	156:ff21514d8981	1133	/**
AnnaBridge	156:ff21514d8981	1134	* @brief Disable ETHERNET clock.
AnnaBridge	156:ff21514d8981	1135	*/
AnnaBridge	156:ff21514d8981	1136	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
AnnaBridge	156:ff21514d8981	1137	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
AnnaBridge	156:ff21514d8981	1138	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
AnnaBridge	156:ff21514d8981	1139	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
AnnaBridge	156:ff21514d8981	1140	} while(0U)
AnnaBridge	156:ff21514d8981	1141	/**
AnnaBridge	156:ff21514d8981	1142	* @}
AnnaBridge	156:ff21514d8981	1143	*/
AnnaBridge	156:ff21514d8981	1144
AnnaBridge	156:ff21514d8981	1145	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	1146	* @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge	156:ff21514d8981	1147	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	1148	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	1149	* using it.
AnnaBridge	156:ff21514d8981	1150	* @{
AnnaBridge	156:ff21514d8981	1151	*/
AnnaBridge	156:ff21514d8981	1152	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
AnnaBridge	156:ff21514d8981	1153	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
AnnaBridge	156:ff21514d8981	1154	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
AnnaBridge	156:ff21514d8981	1155	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
AnnaBridge	156:ff21514d8981	1156	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
AnnaBridge	156:ff21514d8981	1157	#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
AnnaBridge	156:ff21514d8981	1158	#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
AnnaBridge	156:ff21514d8981	1159	#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
AnnaBridge	156:ff21514d8981	1160	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
AnnaBridge	156:ff21514d8981	1161	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
AnnaBridge	156:ff21514d8981	1162	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
AnnaBridge	156:ff21514d8981	1163	#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
AnnaBridge	156:ff21514d8981	1164	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
AnnaBridge	156:ff21514d8981	1165	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
AnnaBridge	156:ff21514d8981	1166	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
AnnaBridge	156:ff21514d8981	1167	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
AnnaBridge	156:ff21514d8981	1168	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
AnnaBridge	156:ff21514d8981	1169	#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
AnnaBridge	156:ff21514d8981	1170	__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
AnnaBridge	156:ff21514d8981	1171	__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
AnnaBridge	156:ff21514d8981	1172
AnnaBridge	156:ff21514d8981	1173	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
AnnaBridge	156:ff21514d8981	1174	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
AnnaBridge	156:ff21514d8981	1175	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
AnnaBridge	156:ff21514d8981	1176	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
AnnaBridge	156:ff21514d8981	1177	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
AnnaBridge	156:ff21514d8981	1178	#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
AnnaBridge	156:ff21514d8981	1179	#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
AnnaBridge	156:ff21514d8981	1180	#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
AnnaBridge	156:ff21514d8981	1181	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
AnnaBridge	156:ff21514d8981	1182	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
AnnaBridge	156:ff21514d8981	1183	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
AnnaBridge	156:ff21514d8981	1184	#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
AnnaBridge	156:ff21514d8981	1185	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
AnnaBridge	156:ff21514d8981	1186	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
AnnaBridge	156:ff21514d8981	1187	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
AnnaBridge	156:ff21514d8981	1188	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
AnnaBridge	156:ff21514d8981	1189	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
AnnaBridge	156:ff21514d8981	1190	#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
AnnaBridge	156:ff21514d8981	1191	__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
AnnaBridge	156:ff21514d8981	1192	__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
AnnaBridge	156:ff21514d8981	1193	/**
AnnaBridge	156:ff21514d8981	1194	* @}
AnnaBridge	156:ff21514d8981	1195	*/
AnnaBridge	156:ff21514d8981	1196
AnnaBridge	156:ff21514d8981	1197	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	1198	* @brief Enable or disable the AHB2 peripheral clock.
AnnaBridge	156:ff21514d8981	1199	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	1200	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	1201	* using it.
AnnaBridge	156:ff21514d8981	1202	* @{
AnnaBridge	156:ff21514d8981	1203	*/
AnnaBridge	156:ff21514d8981	1204	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1205	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1206	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
AnnaBridge	156:ff21514d8981	1207	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1208	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
AnnaBridge	156:ff21514d8981	1209	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1210	} while(0U)
AnnaBridge	156:ff21514d8981	1211	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
AnnaBridge	156:ff21514d8981	1212
AnnaBridge	156:ff21514d8981	1213	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	1214	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1215	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1216	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
AnnaBridge	156:ff21514d8981	1217	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1218	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
AnnaBridge	156:ff21514d8981	1219	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1220	} while(0U)
AnnaBridge	156:ff21514d8981	1221	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1222	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1223	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
AnnaBridge	156:ff21514d8981	1224	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1225	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
AnnaBridge	156:ff21514d8981	1226	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1227	} while(0U)
AnnaBridge	156:ff21514d8981	1228
AnnaBridge	156:ff21514d8981	1229	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
AnnaBridge	156:ff21514d8981	1230	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
AnnaBridge	156:ff21514d8981	1231	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	1232
AnnaBridge	156:ff21514d8981	1233	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
AnnaBridge	156:ff21514d8981	1234	__HAL_RCC_SYSCFG_CLK_ENABLE();\
AnnaBridge	156:ff21514d8981	1235	}while(0U)
AnnaBridge	156:ff21514d8981	1236
AnnaBridge	156:ff21514d8981	1237	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
AnnaBridge	156:ff21514d8981	1238
AnnaBridge	156:ff21514d8981	1239	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1240	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1241	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge	156:ff21514d8981	1242	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1243	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge	156:ff21514d8981	1244	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1245	} while(0U)
AnnaBridge	156:ff21514d8981	1246	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
AnnaBridge	156:ff21514d8981	1247	/**
AnnaBridge	156:ff21514d8981	1248	* @}
AnnaBridge	156:ff21514d8981	1249	*/
AnnaBridge	156:ff21514d8981	1250
AnnaBridge	156:ff21514d8981	1251	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	1252	* @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge	156:ff21514d8981	1253	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	1254	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	1255	* using it.
AnnaBridge	156:ff21514d8981	1256	* @{
AnnaBridge	156:ff21514d8981	1257	*/
AnnaBridge	156:ff21514d8981	1258	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
AnnaBridge	156:ff21514d8981	1259	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
AnnaBridge	156:ff21514d8981	1260
AnnaBridge	156:ff21514d8981	1261	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	1262	#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
AnnaBridge	156:ff21514d8981	1263	#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
AnnaBridge	156:ff21514d8981	1264
AnnaBridge	156:ff21514d8981	1265	#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
AnnaBridge	156:ff21514d8981	1266	#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
AnnaBridge	156:ff21514d8981	1267	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	1268
AnnaBridge	156:ff21514d8981	1269	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
AnnaBridge	156:ff21514d8981	1270	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
AnnaBridge	156:ff21514d8981	1271
AnnaBridge	156:ff21514d8981	1272	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
AnnaBridge	156:ff21514d8981	1273	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
AnnaBridge	156:ff21514d8981	1274	/**
AnnaBridge	156:ff21514d8981	1275	* @}
AnnaBridge	156:ff21514d8981	1276	*/
AnnaBridge	156:ff21514d8981	1277
AnnaBridge	156:ff21514d8981	1278	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	1279	* @brief Enables or disables the AHB3 peripheral clock.
AnnaBridge	156:ff21514d8981	1280	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	1281	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	1282	* using it.
AnnaBridge	156:ff21514d8981	1283	* @{
AnnaBridge	156:ff21514d8981	1284	*/
AnnaBridge	156:ff21514d8981	1285	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1286	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1287	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
AnnaBridge	156:ff21514d8981	1288	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1289	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
AnnaBridge	156:ff21514d8981	1290	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1291	} while(0U)
AnnaBridge	156:ff21514d8981	1292	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
AnnaBridge	156:ff21514d8981	1293	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	1294	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1295	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1296	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
AnnaBridge	156:ff21514d8981	1297	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1298	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
AnnaBridge	156:ff21514d8981	1299	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1300	} while(0U)
AnnaBridge	156:ff21514d8981	1301	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
AnnaBridge	156:ff21514d8981	1302	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	1303	/**
AnnaBridge	156:ff21514d8981	1304	* @}
AnnaBridge	156:ff21514d8981	1305	*/
AnnaBridge	156:ff21514d8981	1306
AnnaBridge	156:ff21514d8981	1307
AnnaBridge	156:ff21514d8981	1308	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	1309	* @brief Get the enable or disable status of the AHB3 peripheral clock.
AnnaBridge	156:ff21514d8981	1310	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	1311	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	1312	* using it.
AnnaBridge	156:ff21514d8981	1313	* @{
AnnaBridge	156:ff21514d8981	1314	*/
AnnaBridge	156:ff21514d8981	1315	#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
AnnaBridge	156:ff21514d8981	1316	#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
AnnaBridge	156:ff21514d8981	1317	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	1318	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
AnnaBridge	156:ff21514d8981	1319	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
AnnaBridge	156:ff21514d8981	1320	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	1321	/**
AnnaBridge	156:ff21514d8981	1322	* @}
AnnaBridge	156:ff21514d8981	1323	*/
AnnaBridge	156:ff21514d8981	1324
AnnaBridge	156:ff21514d8981	1325	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	1326	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	156:ff21514d8981	1327	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	1328	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	1329	* using it.
AnnaBridge	156:ff21514d8981	1330	* @{
AnnaBridge	156:ff21514d8981	1331	*/
AnnaBridge	156:ff21514d8981	1332	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1333	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1334	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	156:ff21514d8981	1335	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1336	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	156:ff21514d8981	1337	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1338	} while(0U)
AnnaBridge	156:ff21514d8981	1339	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1340	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1341	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	156:ff21514d8981	1342	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1343	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	156:ff21514d8981	1344	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1345	} while(0U)
AnnaBridge	156:ff21514d8981	1346	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1347	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1348	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	156:ff21514d8981	1349	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1350	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	156:ff21514d8981	1351	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1352	} while(0U)
AnnaBridge	156:ff21514d8981	1353	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1354	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1355	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	156:ff21514d8981	1356	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1357	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	156:ff21514d8981	1358	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1359	} while(0U)
AnnaBridge	156:ff21514d8981	1360	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1361	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1362	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	156:ff21514d8981	1363	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1364	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	156:ff21514d8981	1365	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1366	} while(0U)
AnnaBridge	156:ff21514d8981	1367	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1368	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1369	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	156:ff21514d8981	1370	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1371	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	156:ff21514d8981	1372	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1373	} while(0U)
AnnaBridge	156:ff21514d8981	1374	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1375	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1376	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	156:ff21514d8981	1377	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1378	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	156:ff21514d8981	1379	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1380	} while(0U)
AnnaBridge	156:ff21514d8981	1381	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1382	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1383	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	156:ff21514d8981	1384	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1385	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	156:ff21514d8981	1386	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1387	} while(0U)
AnnaBridge	156:ff21514d8981	1388	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1389	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1390	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	156:ff21514d8981	1391	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1392	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	156:ff21514d8981	1393	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1394	} while(0U)
AnnaBridge	156:ff21514d8981	1395	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1396	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1397	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	156:ff21514d8981	1398	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1399	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	156:ff21514d8981	1400	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1401	} while(0U)
AnnaBridge	156:ff21514d8981	1402	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1403	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1404	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	156:ff21514d8981	1405	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1406	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	156:ff21514d8981	1407	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1408	} while(0U)
AnnaBridge	156:ff21514d8981	1409	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1410	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1411	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	156:ff21514d8981	1412	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1413	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	156:ff21514d8981	1414	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1415	} while(0U)
AnnaBridge	156:ff21514d8981	1416	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1417	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1418	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
AnnaBridge	156:ff21514d8981	1419	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1420	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
AnnaBridge	156:ff21514d8981	1421	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1422	} while(0U)
AnnaBridge	156:ff21514d8981	1423	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1424	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1425	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
AnnaBridge	156:ff21514d8981	1426	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1427	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
AnnaBridge	156:ff21514d8981	1428	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1429	} while(0U)
AnnaBridge	156:ff21514d8981	1430	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1431	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1432	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	156:ff21514d8981	1433	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1434	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	156:ff21514d8981	1435	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1436	} while(0U)
AnnaBridge	156:ff21514d8981	1437	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1438	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1439	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	156:ff21514d8981	1440	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1441	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	156:ff21514d8981	1442	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1443	} while(0U)
AnnaBridge	156:ff21514d8981	1444	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1445	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1446	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	156:ff21514d8981	1447	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1448	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	156:ff21514d8981	1449	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1450	} while(0U)
AnnaBridge	156:ff21514d8981	1451	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1452	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1453	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	156:ff21514d8981	1454	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1455	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	156:ff21514d8981	1456	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1457	} while(0U)
AnnaBridge	156:ff21514d8981	1458	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1459	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1460	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	156:ff21514d8981	1461	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1462	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	156:ff21514d8981	1463	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1464	} while(0U)
AnnaBridge	156:ff21514d8981	1465	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
AnnaBridge	156:ff21514d8981	1466	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge	156:ff21514d8981	1467	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
AnnaBridge	156:ff21514d8981	1468	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge	156:ff21514d8981	1469	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
AnnaBridge	156:ff21514d8981	1470	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
AnnaBridge	156:ff21514d8981	1471	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
AnnaBridge	156:ff21514d8981	1472	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
AnnaBridge	156:ff21514d8981	1473	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
AnnaBridge	156:ff21514d8981	1474	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
AnnaBridge	156:ff21514d8981	1475	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
AnnaBridge	156:ff21514d8981	1476	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
AnnaBridge	156:ff21514d8981	1477	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
AnnaBridge	156:ff21514d8981	1478	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
AnnaBridge	156:ff21514d8981	1479	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
AnnaBridge	156:ff21514d8981	1480	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
AnnaBridge	156:ff21514d8981	1481	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
AnnaBridge	156:ff21514d8981	1482	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
AnnaBridge	156:ff21514d8981	1483	/**
AnnaBridge	156:ff21514d8981	1484	* @}
AnnaBridge	156:ff21514d8981	1485	*/
AnnaBridge	156:ff21514d8981	1486
AnnaBridge	156:ff21514d8981	1487	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	1488	* @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge	156:ff21514d8981	1489	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	1490	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	1491	* using it.
AnnaBridge	156:ff21514d8981	1492	* @{
AnnaBridge	156:ff21514d8981	1493	*/
AnnaBridge	156:ff21514d8981	1494	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
AnnaBridge	156:ff21514d8981	1495	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge	156:ff21514d8981	1496	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
AnnaBridge	156:ff21514d8981	1497	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge	156:ff21514d8981	1498	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
AnnaBridge	156:ff21514d8981	1499	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
AnnaBridge	156:ff21514d8981	1500	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
AnnaBridge	156:ff21514d8981	1501	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
AnnaBridge	156:ff21514d8981	1502	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
AnnaBridge	156:ff21514d8981	1503	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
AnnaBridge	156:ff21514d8981	1504	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
AnnaBridge	156:ff21514d8981	1505	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
AnnaBridge	156:ff21514d8981	1506	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
AnnaBridge	156:ff21514d8981	1507	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
AnnaBridge	156:ff21514d8981	1508	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
AnnaBridge	156:ff21514d8981	1509	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
AnnaBridge	156:ff21514d8981	1510	#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
AnnaBridge	156:ff21514d8981	1511	#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
AnnaBridge	156:ff21514d8981	1512
AnnaBridge	156:ff21514d8981	1513	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
AnnaBridge	156:ff21514d8981	1514	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge	156:ff21514d8981	1515	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
AnnaBridge	156:ff21514d8981	1516	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge	156:ff21514d8981	1517	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
AnnaBridge	156:ff21514d8981	1518	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
AnnaBridge	156:ff21514d8981	1519	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
AnnaBridge	156:ff21514d8981	1520	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
AnnaBridge	156:ff21514d8981	1521	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
AnnaBridge	156:ff21514d8981	1522	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
AnnaBridge	156:ff21514d8981	1523	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
AnnaBridge	156:ff21514d8981	1524	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
AnnaBridge	156:ff21514d8981	1525	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
AnnaBridge	156:ff21514d8981	1526	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
AnnaBridge	156:ff21514d8981	1527	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
AnnaBridge	156:ff21514d8981	1528	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
AnnaBridge	156:ff21514d8981	1529	#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
AnnaBridge	156:ff21514d8981	1530	#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
AnnaBridge	156:ff21514d8981	1531	/**
AnnaBridge	156:ff21514d8981	1532	* @}
AnnaBridge	156:ff21514d8981	1533	*/
AnnaBridge	156:ff21514d8981	1534
AnnaBridge	156:ff21514d8981	1535	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	1536	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	156:ff21514d8981	1537	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	1538	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	1539	* using it.
AnnaBridge	156:ff21514d8981	1540	* @{
AnnaBridge	156:ff21514d8981	1541	*/
AnnaBridge	156:ff21514d8981	1542	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1543	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1544	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	156:ff21514d8981	1545	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1546	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	156:ff21514d8981	1547	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1548	} while(0U)
AnnaBridge	156:ff21514d8981	1549	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1550	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1551	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
AnnaBridge	156:ff21514d8981	1552	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1553	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
AnnaBridge	156:ff21514d8981	1554	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1555	} while(0U)
AnnaBridge	156:ff21514d8981	1556	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1557	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1558	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
AnnaBridge	156:ff21514d8981	1559	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1560	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
AnnaBridge	156:ff21514d8981	1561	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1562	} while(0U)
AnnaBridge	156:ff21514d8981	1563	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1564	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1565	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
AnnaBridge	156:ff21514d8981	1566	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1567	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
AnnaBridge	156:ff21514d8981	1568	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1569	} while(0U)
AnnaBridge	156:ff21514d8981	1570	#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1571	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1572	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
AnnaBridge	156:ff21514d8981	1573	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1574	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
AnnaBridge	156:ff21514d8981	1575	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1576	} while(0U)
AnnaBridge	156:ff21514d8981	1577	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1578	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1579	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
AnnaBridge	156:ff21514d8981	1580	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1581	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
AnnaBridge	156:ff21514d8981	1582	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1583	} while(0U)
AnnaBridge	156:ff21514d8981	1584	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1585	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1586	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	156:ff21514d8981	1587	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1588	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	156:ff21514d8981	1589	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1590	} while(0U)
AnnaBridge	156:ff21514d8981	1591	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1592	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1593	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	156:ff21514d8981	1594	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1595	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	156:ff21514d8981	1596	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1597	} while(0U)
AnnaBridge	156:ff21514d8981	1598	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1599	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1600	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	156:ff21514d8981	1601	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1602	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	156:ff21514d8981	1603	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1604	} while(0U)
AnnaBridge	156:ff21514d8981	1605	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
AnnaBridge	156:ff21514d8981	1606	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
AnnaBridge	156:ff21514d8981	1607	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
AnnaBridge	156:ff21514d8981	1608	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
AnnaBridge	156:ff21514d8981	1609	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
AnnaBridge	156:ff21514d8981	1610	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
AnnaBridge	156:ff21514d8981	1611	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
AnnaBridge	156:ff21514d8981	1612	#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
AnnaBridge	156:ff21514d8981	1613	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
AnnaBridge	156:ff21514d8981	1614
AnnaBridge	156:ff21514d8981	1615	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	1616	#define __HAL_RCC_LTDC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1617	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1618	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
AnnaBridge	156:ff21514d8981	1619	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1620	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
AnnaBridge	156:ff21514d8981	1621	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1622	} while(0U)
AnnaBridge	156:ff21514d8981	1623
AnnaBridge	156:ff21514d8981	1624	#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
AnnaBridge	156:ff21514d8981	1625	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	1626
AnnaBridge	156:ff21514d8981	1627	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	1628	#define __HAL_RCC_DSI_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1629	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	1630	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
AnnaBridge	156:ff21514d8981	1631	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1632	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
AnnaBridge	156:ff21514d8981	1633	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1634	} while(0U)
AnnaBridge	156:ff21514d8981	1635
AnnaBridge	156:ff21514d8981	1636	#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
AnnaBridge	156:ff21514d8981	1637	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	1638	/**
AnnaBridge	156:ff21514d8981	1639	* @}
AnnaBridge	156:ff21514d8981	1640	*/
AnnaBridge	156:ff21514d8981	1641
AnnaBridge	156:ff21514d8981	1642	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	1643	* @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge	156:ff21514d8981	1644	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	1645	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	1646	* using it.
AnnaBridge	156:ff21514d8981	1647	* @{
AnnaBridge	156:ff21514d8981	1648	*/
AnnaBridge	156:ff21514d8981	1649	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
AnnaBridge	156:ff21514d8981	1650	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
AnnaBridge	156:ff21514d8981	1651	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
AnnaBridge	156:ff21514d8981	1652	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
AnnaBridge	156:ff21514d8981	1653	#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
AnnaBridge	156:ff21514d8981	1654	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
AnnaBridge	156:ff21514d8981	1655	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
AnnaBridge	156:ff21514d8981	1656	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
AnnaBridge	156:ff21514d8981	1657	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET)
AnnaBridge	156:ff21514d8981	1658
AnnaBridge	156:ff21514d8981	1659	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
AnnaBridge	156:ff21514d8981	1660	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
AnnaBridge	156:ff21514d8981	1661	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET)
AnnaBridge	156:ff21514d8981	1662	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
AnnaBridge	156:ff21514d8981	1663	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
AnnaBridge	156:ff21514d8981	1664	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
AnnaBridge	156:ff21514d8981	1665	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
AnnaBridge	156:ff21514d8981	1666	#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
AnnaBridge	156:ff21514d8981	1667	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
AnnaBridge	156:ff21514d8981	1668
AnnaBridge	156:ff21514d8981	1669	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	1670	#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
AnnaBridge	156:ff21514d8981	1671	#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
AnnaBridge	156:ff21514d8981	1672	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	1673
AnnaBridge	156:ff21514d8981	1674	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	1675	#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
AnnaBridge	156:ff21514d8981	1676	#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
AnnaBridge	156:ff21514d8981	1677	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	1678	/**
AnnaBridge	156:ff21514d8981	1679	* @}
AnnaBridge	156:ff21514d8981	1680	*/
AnnaBridge	156:ff21514d8981	1681
AnnaBridge	156:ff21514d8981	1682	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
AnnaBridge	156:ff21514d8981	1683	* @brief Force or release AHB1 peripheral reset.
AnnaBridge	156:ff21514d8981	1684	* @{
AnnaBridge	156:ff21514d8981	1685	*/
AnnaBridge	156:ff21514d8981	1686	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
AnnaBridge	156:ff21514d8981	1687	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
AnnaBridge	156:ff21514d8981	1688	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
AnnaBridge	156:ff21514d8981	1689	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
AnnaBridge	156:ff21514d8981	1690	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
AnnaBridge	156:ff21514d8981	1691	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
AnnaBridge	156:ff21514d8981	1692	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
AnnaBridge	156:ff21514d8981	1693	#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOJRST))
AnnaBridge	156:ff21514d8981	1694	#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOKRST))
AnnaBridge	156:ff21514d8981	1695	#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2DRST))
AnnaBridge	156:ff21514d8981	1696	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
AnnaBridge	156:ff21514d8981	1697
AnnaBridge	156:ff21514d8981	1698	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
AnnaBridge	156:ff21514d8981	1699	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
AnnaBridge	156:ff21514d8981	1700	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
AnnaBridge	156:ff21514d8981	1701	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
AnnaBridge	156:ff21514d8981	1702	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
AnnaBridge	156:ff21514d8981	1703	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
AnnaBridge	156:ff21514d8981	1704	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
AnnaBridge	156:ff21514d8981	1705	#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
AnnaBridge	156:ff21514d8981	1706	#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
AnnaBridge	156:ff21514d8981	1707	#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
AnnaBridge	156:ff21514d8981	1708	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
AnnaBridge	156:ff21514d8981	1709	/**
AnnaBridge	156:ff21514d8981	1710	* @}
AnnaBridge	156:ff21514d8981	1711	*/
AnnaBridge	156:ff21514d8981	1712
AnnaBridge	156:ff21514d8981	1713	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
AnnaBridge	156:ff21514d8981	1714	* @brief Force or release AHB2 peripheral reset.
AnnaBridge	156:ff21514d8981	1715	* @{
AnnaBridge	156:ff21514d8981	1716	*/
AnnaBridge	156:ff21514d8981	1717	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
AnnaBridge	156:ff21514d8981	1718	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	156:ff21514d8981	1719	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
AnnaBridge	156:ff21514d8981	1720	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
AnnaBridge	156:ff21514d8981	1721
AnnaBridge	156:ff21514d8981	1722	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
AnnaBridge	156:ff21514d8981	1723	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	156:ff21514d8981	1724	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
AnnaBridge	156:ff21514d8981	1725	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
AnnaBridge	156:ff21514d8981	1726
AnnaBridge	156:ff21514d8981	1727	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	1728	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
AnnaBridge	156:ff21514d8981	1729	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
AnnaBridge	156:ff21514d8981	1730
AnnaBridge	156:ff21514d8981	1731	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
AnnaBridge	156:ff21514d8981	1732	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
AnnaBridge	156:ff21514d8981	1733	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	1734	/**
AnnaBridge	156:ff21514d8981	1735	* @}
AnnaBridge	156:ff21514d8981	1736	*/
AnnaBridge	156:ff21514d8981	1737
AnnaBridge	156:ff21514d8981	1738	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
AnnaBridge	156:ff21514d8981	1739	* @brief Force or release AHB3 peripheral reset.
AnnaBridge	156:ff21514d8981	1740	* @{
AnnaBridge	156:ff21514d8981	1741	*/
AnnaBridge	156:ff21514d8981	1742	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
AnnaBridge	156:ff21514d8981	1743	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
AnnaBridge	156:ff21514d8981	1744	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
AnnaBridge	156:ff21514d8981	1745	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
AnnaBridge	156:ff21514d8981	1746
AnnaBridge	156:ff21514d8981	1747	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	1748	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
AnnaBridge	156:ff21514d8981	1749	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
AnnaBridge	156:ff21514d8981	1750	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	1751	/**
AnnaBridge	156:ff21514d8981	1752	* @}
AnnaBridge	156:ff21514d8981	1753	*/
AnnaBridge	156:ff21514d8981	1754
AnnaBridge	156:ff21514d8981	1755	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
AnnaBridge	156:ff21514d8981	1756	* @brief Force or release APB1 peripheral reset.
AnnaBridge	156:ff21514d8981	1757	* @{
AnnaBridge	156:ff21514d8981	1758	*/
AnnaBridge	156:ff21514d8981	1759	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
AnnaBridge	156:ff21514d8981	1760	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
AnnaBridge	156:ff21514d8981	1761	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
AnnaBridge	156:ff21514d8981	1762	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
AnnaBridge	156:ff21514d8981	1763	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
AnnaBridge	156:ff21514d8981	1764	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
AnnaBridge	156:ff21514d8981	1765	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
AnnaBridge	156:ff21514d8981	1766	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
AnnaBridge	156:ff21514d8981	1767	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
AnnaBridge	156:ff21514d8981	1768	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
AnnaBridge	156:ff21514d8981	1769	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
AnnaBridge	156:ff21514d8981	1770	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
AnnaBridge	156:ff21514d8981	1771	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
AnnaBridge	156:ff21514d8981	1772	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
AnnaBridge	156:ff21514d8981	1773	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
AnnaBridge	156:ff21514d8981	1774	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
AnnaBridge	156:ff21514d8981	1775	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
AnnaBridge	156:ff21514d8981	1776	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
AnnaBridge	156:ff21514d8981	1777
AnnaBridge	156:ff21514d8981	1778	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
AnnaBridge	156:ff21514d8981	1779	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge	156:ff21514d8981	1780	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge	156:ff21514d8981	1781	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge	156:ff21514d8981	1782	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
AnnaBridge	156:ff21514d8981	1783	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
AnnaBridge	156:ff21514d8981	1784	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
AnnaBridge	156:ff21514d8981	1785	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
AnnaBridge	156:ff21514d8981	1786	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
AnnaBridge	156:ff21514d8981	1787	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
AnnaBridge	156:ff21514d8981	1788	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
AnnaBridge	156:ff21514d8981	1789	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
AnnaBridge	156:ff21514d8981	1790	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
AnnaBridge	156:ff21514d8981	1791	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
AnnaBridge	156:ff21514d8981	1792	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
AnnaBridge	156:ff21514d8981	1793	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
AnnaBridge	156:ff21514d8981	1794	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
AnnaBridge	156:ff21514d8981	1795	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
AnnaBridge	156:ff21514d8981	1796	/**
AnnaBridge	156:ff21514d8981	1797	* @}
AnnaBridge	156:ff21514d8981	1798	*/
AnnaBridge	156:ff21514d8981	1799
AnnaBridge	156:ff21514d8981	1800	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
AnnaBridge	156:ff21514d8981	1801	* @brief Force or release APB2 peripheral reset.
AnnaBridge	156:ff21514d8981	1802	* @{
AnnaBridge	156:ff21514d8981	1803	*/
AnnaBridge	156:ff21514d8981	1804	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
AnnaBridge	156:ff21514d8981	1805	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
AnnaBridge	156:ff21514d8981	1806	#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI6RST))
AnnaBridge	156:ff21514d8981	1807	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
AnnaBridge	156:ff21514d8981	1808	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
AnnaBridge	156:ff21514d8981	1809	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
AnnaBridge	156:ff21514d8981	1810	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
AnnaBridge	156:ff21514d8981	1811
AnnaBridge	156:ff21514d8981	1812	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
AnnaBridge	156:ff21514d8981	1813	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
AnnaBridge	156:ff21514d8981	1814	#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
AnnaBridge	156:ff21514d8981	1815	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
AnnaBridge	156:ff21514d8981	1816	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
AnnaBridge	156:ff21514d8981	1817	#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
AnnaBridge	156:ff21514d8981	1818	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
AnnaBridge	156:ff21514d8981	1819
AnnaBridge	156:ff21514d8981	1820	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	1821	#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_LTDCRST))
AnnaBridge	156:ff21514d8981	1822	#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
AnnaBridge	156:ff21514d8981	1823	#endif /* STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	1824
AnnaBridge	156:ff21514d8981	1825	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	1826	#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DSIRST))
AnnaBridge	156:ff21514d8981	1827	#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
AnnaBridge	156:ff21514d8981	1828	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	1829	/**
AnnaBridge	156:ff21514d8981	1830	* @}
AnnaBridge	156:ff21514d8981	1831	*/
AnnaBridge	156:ff21514d8981	1832
AnnaBridge	156:ff21514d8981	1833	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	1834	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	1835	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	1836	* power consumption.
AnnaBridge	156:ff21514d8981	1837	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	1838	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	1839	* @{
AnnaBridge	156:ff21514d8981	1840	*/
AnnaBridge	156:ff21514d8981	1841	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	156:ff21514d8981	1842	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	156:ff21514d8981	1843	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge	156:ff21514d8981	1844	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge	156:ff21514d8981	1845	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
AnnaBridge	156:ff21514d8981	1846	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	156:ff21514d8981	1847	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
AnnaBridge	156:ff21514d8981	1848	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
AnnaBridge	156:ff21514d8981	1849	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
AnnaBridge	156:ff21514d8981	1850	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
AnnaBridge	156:ff21514d8981	1851	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
AnnaBridge	156:ff21514d8981	1852	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
AnnaBridge	156:ff21514d8981	1853	#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOJLPEN))
AnnaBridge	156:ff21514d8981	1854	#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOKLPEN))
AnnaBridge	156:ff21514d8981	1855	#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM3LPEN))
AnnaBridge	156:ff21514d8981	1856	#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2DLPEN))
AnnaBridge	156:ff21514d8981	1857	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	156:ff21514d8981	1858	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	156:ff21514d8981	1859	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	156:ff21514d8981	1860	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
AnnaBridge	156:ff21514d8981	1861
AnnaBridge	156:ff21514d8981	1862	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	156:ff21514d8981	1863	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	156:ff21514d8981	1864	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge	156:ff21514d8981	1865	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge	156:ff21514d8981	1866	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
AnnaBridge	156:ff21514d8981	1867	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	156:ff21514d8981	1868	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
AnnaBridge	156:ff21514d8981	1869	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
AnnaBridge	156:ff21514d8981	1870	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
AnnaBridge	156:ff21514d8981	1871	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
AnnaBridge	156:ff21514d8981	1872	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
AnnaBridge	156:ff21514d8981	1873	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
AnnaBridge	156:ff21514d8981	1874	#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
AnnaBridge	156:ff21514d8981	1875	#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
AnnaBridge	156:ff21514d8981	1876	#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
AnnaBridge	156:ff21514d8981	1877	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	156:ff21514d8981	1878	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	156:ff21514d8981	1879	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	156:ff21514d8981	1880	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
AnnaBridge	156:ff21514d8981	1881	/**
AnnaBridge	156:ff21514d8981	1882	* @}
AnnaBridge	156:ff21514d8981	1883	*/
AnnaBridge	156:ff21514d8981	1884
AnnaBridge	156:ff21514d8981	1885	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	1886	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	1887	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	1888	* power consumption.
AnnaBridge	156:ff21514d8981	1889	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	1890	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	1891	* @{
AnnaBridge	156:ff21514d8981	1892	*/
AnnaBridge	156:ff21514d8981	1893	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	156:ff21514d8981	1894	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	156:ff21514d8981	1895
AnnaBridge	156:ff21514d8981	1896	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
AnnaBridge	156:ff21514d8981	1897	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
AnnaBridge	156:ff21514d8981	1898
AnnaBridge	156:ff21514d8981	1899	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
AnnaBridge	156:ff21514d8981	1900	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
AnnaBridge	156:ff21514d8981	1901
AnnaBridge	156:ff21514d8981	1902	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	1903	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
AnnaBridge	156:ff21514d8981	1904	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
AnnaBridge	156:ff21514d8981	1905
AnnaBridge	156:ff21514d8981	1906	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
AnnaBridge	156:ff21514d8981	1907	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
AnnaBridge	156:ff21514d8981	1908	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	1909	/**
AnnaBridge	156:ff21514d8981	1910	* @}
AnnaBridge	156:ff21514d8981	1911	*/
AnnaBridge	156:ff21514d8981	1912
AnnaBridge	156:ff21514d8981	1913	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	1914	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	1915	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	1916	* power consumption.
AnnaBridge	156:ff21514d8981	1917	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	1918	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	1919	* @{
AnnaBridge	156:ff21514d8981	1920	*/
AnnaBridge	156:ff21514d8981	1921	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
AnnaBridge	156:ff21514d8981	1922	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
AnnaBridge	156:ff21514d8981	1923
AnnaBridge	156:ff21514d8981	1924	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	1925	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
AnnaBridge	156:ff21514d8981	1926	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
AnnaBridge	156:ff21514d8981	1927	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	1928	/**
AnnaBridge	156:ff21514d8981	1929	* @}
AnnaBridge	156:ff21514d8981	1930	*/
AnnaBridge	156:ff21514d8981	1931
AnnaBridge	156:ff21514d8981	1932	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	1933	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	1934	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	1935	* power consumption.
AnnaBridge	156:ff21514d8981	1936	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	1937	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	1938	* @{
AnnaBridge	156:ff21514d8981	1939	*/
AnnaBridge	156:ff21514d8981	1940	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	156:ff21514d8981	1941	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	156:ff21514d8981	1942	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
AnnaBridge	156:ff21514d8981	1943	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
AnnaBridge	156:ff21514d8981	1944	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	156:ff21514d8981	1945	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
AnnaBridge	156:ff21514d8981	1946	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
AnnaBridge	156:ff21514d8981	1947	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
AnnaBridge	156:ff21514d8981	1948	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
AnnaBridge	156:ff21514d8981	1949	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	156:ff21514d8981	1950	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
AnnaBridge	156:ff21514d8981	1951	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
AnnaBridge	156:ff21514d8981	1952	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
AnnaBridge	156:ff21514d8981	1953	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	156:ff21514d8981	1954	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	156:ff21514d8981	1955	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	156:ff21514d8981	1956	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	156:ff21514d8981	1957	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	156:ff21514d8981	1958
AnnaBridge	156:ff21514d8981	1959	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	156:ff21514d8981	1960	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	156:ff21514d8981	1961	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	156:ff21514d8981	1962	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	156:ff21514d8981	1963	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	156:ff21514d8981	1964	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	156:ff21514d8981	1965	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	156:ff21514d8981	1966	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
AnnaBridge	156:ff21514d8981	1967	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
AnnaBridge	156:ff21514d8981	1968	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	156:ff21514d8981	1969	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
AnnaBridge	156:ff21514d8981	1970	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
AnnaBridge	156:ff21514d8981	1971	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
AnnaBridge	156:ff21514d8981	1972	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
AnnaBridge	156:ff21514d8981	1973	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	156:ff21514d8981	1974	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
AnnaBridge	156:ff21514d8981	1975	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
AnnaBridge	156:ff21514d8981	1976	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
AnnaBridge	156:ff21514d8981	1977	/**
AnnaBridge	156:ff21514d8981	1978	* @}
AnnaBridge	156:ff21514d8981	1979	*/
AnnaBridge	156:ff21514d8981	1980
AnnaBridge	156:ff21514d8981	1981	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	1982	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	1983	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	1984	* power consumption.
AnnaBridge	156:ff21514d8981	1985	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	1986	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	1987	* @{
AnnaBridge	156:ff21514d8981	1988	*/
AnnaBridge	156:ff21514d8981	1989	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	156:ff21514d8981	1990	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
AnnaBridge	156:ff21514d8981	1991	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
AnnaBridge	156:ff21514d8981	1992	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
AnnaBridge	156:ff21514d8981	1993	#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI6LPEN))
AnnaBridge	156:ff21514d8981	1994	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
AnnaBridge	156:ff21514d8981	1995	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	156:ff21514d8981	1996	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	156:ff21514d8981	1997	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	156:ff21514d8981	1998
AnnaBridge	156:ff21514d8981	1999	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	156:ff21514d8981	2000	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	156:ff21514d8981	2001	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	156:ff21514d8981	2002	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	156:ff21514d8981	2003	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
AnnaBridge	156:ff21514d8981	2004	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
AnnaBridge	156:ff21514d8981	2005	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
AnnaBridge	156:ff21514d8981	2006	#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
AnnaBridge	156:ff21514d8981	2007	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
AnnaBridge	156:ff21514d8981	2008
AnnaBridge	156:ff21514d8981	2009	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	2010	#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_LTDCLPEN))
AnnaBridge	156:ff21514d8981	2011
AnnaBridge	156:ff21514d8981	2012	#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
AnnaBridge	156:ff21514d8981	2013	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	2014
AnnaBridge	156:ff21514d8981	2015	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	2016	#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DSILPEN))
AnnaBridge	156:ff21514d8981	2017	#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
AnnaBridge	156:ff21514d8981	2018	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	2019	/**
AnnaBridge	156:ff21514d8981	2020	* @}
AnnaBridge	156:ff21514d8981	2021	*/
AnnaBridge	156:ff21514d8981	2022	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	2023	/----------------------------------------------------------------------------/
AnnaBridge	156:ff21514d8981	2024
AnnaBridge	156:ff21514d8981	2025	/----------------------------------- STM32F40xxx/STM32F41xxx-----------------/
AnnaBridge	156:ff21514d8981	2026	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
AnnaBridge	156:ff21514d8981	2027	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	2028	* @brief Enables or disables the AHB1 peripheral clock.
AnnaBridge	156:ff21514d8981	2029	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	2030	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	2031	* using it.
AnnaBridge	156:ff21514d8981	2032	* @{
AnnaBridge	156:ff21514d8981	2033	*/
AnnaBridge	156:ff21514d8981	2034	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2035	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2036	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
AnnaBridge	156:ff21514d8981	2037	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2038	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
AnnaBridge	156:ff21514d8981	2039	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2040	} while(0U)
AnnaBridge	156:ff21514d8981	2041	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2042	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2043	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
AnnaBridge	156:ff21514d8981	2044	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2045	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
AnnaBridge	156:ff21514d8981	2046	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2047	} while(0U)
AnnaBridge	156:ff21514d8981	2048	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2049	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2050	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	156:ff21514d8981	2051	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2052	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	156:ff21514d8981	2053	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2054	} while(0U)
AnnaBridge	156:ff21514d8981	2055	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2056	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2057	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	156:ff21514d8981	2058	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2059	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	156:ff21514d8981	2060	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2061	} while(0U)
AnnaBridge	156:ff21514d8981	2062	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2063	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2064	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	156:ff21514d8981	2065	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2066	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	156:ff21514d8981	2067	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2068	} while(0U)
AnnaBridge	156:ff21514d8981	2069	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2070	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2071	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
AnnaBridge	156:ff21514d8981	2072	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2073	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
AnnaBridge	156:ff21514d8981	2074	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2075	} while(0U)
AnnaBridge	156:ff21514d8981	2076	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2077	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2078	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge	156:ff21514d8981	2079	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2080	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge	156:ff21514d8981	2081	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2082	} while(0U)
AnnaBridge	156:ff21514d8981	2083	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2084	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2085	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge	156:ff21514d8981	2086	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2087	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge	156:ff21514d8981	2088	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2089	} while(0U)
AnnaBridge	156:ff21514d8981	2090	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2091	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2092	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
AnnaBridge	156:ff21514d8981	2093	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2094	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
AnnaBridge	156:ff21514d8981	2095	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2096	} while(0U)
AnnaBridge	156:ff21514d8981	2097	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2098	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2099	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
AnnaBridge	156:ff21514d8981	2100	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2101	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
AnnaBridge	156:ff21514d8981	2102	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2103	} while(0U)
AnnaBridge	156:ff21514d8981	2104	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
AnnaBridge	156:ff21514d8981	2105	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
AnnaBridge	156:ff21514d8981	2106	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
AnnaBridge	156:ff21514d8981	2107	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
AnnaBridge	156:ff21514d8981	2108	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
AnnaBridge	156:ff21514d8981	2109	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
AnnaBridge	156:ff21514d8981	2110	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
AnnaBridge	156:ff21514d8981	2111	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
AnnaBridge	156:ff21514d8981	2112	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
AnnaBridge	156:ff21514d8981	2113	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
AnnaBridge	156:ff21514d8981	2114	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
AnnaBridge	156:ff21514d8981	2115	/**
AnnaBridge	156:ff21514d8981	2116	* @brief Enable ETHERNET clock.
AnnaBridge	156:ff21514d8981	2117	*/
AnnaBridge	156:ff21514d8981	2118	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2119	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2120	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
AnnaBridge	156:ff21514d8981	2121	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2122	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
AnnaBridge	156:ff21514d8981	2123	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2124	} while(0U)
AnnaBridge	156:ff21514d8981	2125	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2126	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2127	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
AnnaBridge	156:ff21514d8981	2128	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2129	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
AnnaBridge	156:ff21514d8981	2130	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2131	} while(0U)
AnnaBridge	156:ff21514d8981	2132	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2133	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2134	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
AnnaBridge	156:ff21514d8981	2135	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2136	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
AnnaBridge	156:ff21514d8981	2137	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2138	} while(0U)
AnnaBridge	156:ff21514d8981	2139	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2140	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2141	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
AnnaBridge	156:ff21514d8981	2142	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2143	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
AnnaBridge	156:ff21514d8981	2144	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2145	} while(0U)
AnnaBridge	156:ff21514d8981	2146	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2147	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
AnnaBridge	156:ff21514d8981	2148	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
AnnaBridge	156:ff21514d8981	2149	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
AnnaBridge	156:ff21514d8981	2150	} while(0U)
AnnaBridge	156:ff21514d8981	2151
AnnaBridge	156:ff21514d8981	2152	/**
AnnaBridge	156:ff21514d8981	2153	* @brief Disable ETHERNET clock.
AnnaBridge	156:ff21514d8981	2154	*/
AnnaBridge	156:ff21514d8981	2155	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
AnnaBridge	156:ff21514d8981	2156	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
AnnaBridge	156:ff21514d8981	2157	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
AnnaBridge	156:ff21514d8981	2158	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
AnnaBridge	156:ff21514d8981	2159	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
AnnaBridge	156:ff21514d8981	2160	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
AnnaBridge	156:ff21514d8981	2161	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
AnnaBridge	156:ff21514d8981	2162	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
AnnaBridge	156:ff21514d8981	2163	} while(0U)
AnnaBridge	156:ff21514d8981	2164	#endif /* STM32F407xx \|\| STM32F417xx */
AnnaBridge	156:ff21514d8981	2165	/**
AnnaBridge	156:ff21514d8981	2166	* @}
AnnaBridge	156:ff21514d8981	2167	*/
AnnaBridge	156:ff21514d8981	2168
AnnaBridge	156:ff21514d8981	2169	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	2170	* @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge	156:ff21514d8981	2171	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	2172	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	2173	* using it.
AnnaBridge	156:ff21514d8981	2174	* @{
AnnaBridge	156:ff21514d8981	2175	*/
AnnaBridge	156:ff21514d8981	2176	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
AnnaBridge	156:ff21514d8981	2177	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
AnnaBridge	156:ff21514d8981	2178	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
AnnaBridge	156:ff21514d8981	2179	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
AnnaBridge	156:ff21514d8981	2180	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
AnnaBridge	156:ff21514d8981	2181	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
AnnaBridge	156:ff21514d8981	2182	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
AnnaBridge	156:ff21514d8981	2183	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
AnnaBridge	156:ff21514d8981	2184	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
AnnaBridge	156:ff21514d8981	2185	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
AnnaBridge	156:ff21514d8981	2186
AnnaBridge	156:ff21514d8981	2187	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
AnnaBridge	156:ff21514d8981	2188	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
AnnaBridge	156:ff21514d8981	2189	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
AnnaBridge	156:ff21514d8981	2190	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
AnnaBridge	156:ff21514d8981	2191	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
AnnaBridge	156:ff21514d8981	2192	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
AnnaBridge	156:ff21514d8981	2193	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET)
AnnaBridge	156:ff21514d8981	2194	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
AnnaBridge	156:ff21514d8981	2195	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
AnnaBridge	156:ff21514d8981	2196	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
AnnaBridge	156:ff21514d8981	2197	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
AnnaBridge	156:ff21514d8981	2198	/**
AnnaBridge	156:ff21514d8981	2199	* @brief Enable ETHERNET clock.
AnnaBridge	156:ff21514d8981	2200	*/
AnnaBridge	156:ff21514d8981	2201	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
AnnaBridge	156:ff21514d8981	2202	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
AnnaBridge	156:ff21514d8981	2203	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
AnnaBridge	156:ff21514d8981	2204	#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
AnnaBridge	156:ff21514d8981	2205	#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
AnnaBridge	156:ff21514d8981	2206	__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
AnnaBridge	156:ff21514d8981	2207	__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
AnnaBridge	156:ff21514d8981	2208	/**
AnnaBridge	156:ff21514d8981	2209	* @brief Disable ETHERNET clock.
AnnaBridge	156:ff21514d8981	2210	*/
AnnaBridge	156:ff21514d8981	2211	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
AnnaBridge	156:ff21514d8981	2212	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
AnnaBridge	156:ff21514d8981	2213	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
AnnaBridge	156:ff21514d8981	2214	#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
AnnaBridge	156:ff21514d8981	2215	#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
AnnaBridge	156:ff21514d8981	2216	__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
AnnaBridge	156:ff21514d8981	2217	__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
AnnaBridge	156:ff21514d8981	2218	#endif /* STM32F407xx \|\| STM32F417xx */
AnnaBridge	156:ff21514d8981	2219	/**
AnnaBridge	156:ff21514d8981	2220	* @}
AnnaBridge	156:ff21514d8981	2221	*/
AnnaBridge	156:ff21514d8981	2222
AnnaBridge	156:ff21514d8981	2223	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	2224	* @brief Enable or disable the AHB2 peripheral clock.
AnnaBridge	156:ff21514d8981	2225	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	2226	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	2227	* using it.
AnnaBridge	156:ff21514d8981	2228	* @{
AnnaBridge	156:ff21514d8981	2229	*/
AnnaBridge	156:ff21514d8981	2230	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
AnnaBridge	156:ff21514d8981	2231	__HAL_RCC_SYSCFG_CLK_ENABLE();\
AnnaBridge	156:ff21514d8981	2232	}while(0U)
AnnaBridge	156:ff21514d8981	2233
AnnaBridge	156:ff21514d8981	2234	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
AnnaBridge	156:ff21514d8981	2235
AnnaBridge	156:ff21514d8981	2236	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2237	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2238	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge	156:ff21514d8981	2239	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2240	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge	156:ff21514d8981	2241	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2242	} while(0U)
AnnaBridge	156:ff21514d8981	2243	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
AnnaBridge	156:ff21514d8981	2244
AnnaBridge	156:ff21514d8981	2245	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
AnnaBridge	156:ff21514d8981	2246	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2247	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2248	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
AnnaBridge	156:ff21514d8981	2249	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2250	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
AnnaBridge	156:ff21514d8981	2251	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2252	} while(0U)
AnnaBridge	156:ff21514d8981	2253	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
AnnaBridge	156:ff21514d8981	2254	#endif /* STM32F407xx \|\| STM32F417xx */
AnnaBridge	156:ff21514d8981	2255
AnnaBridge	156:ff21514d8981	2256	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
AnnaBridge	156:ff21514d8981	2257	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2258	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2259	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
AnnaBridge	156:ff21514d8981	2260	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2261	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
AnnaBridge	156:ff21514d8981	2262	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2263	} while(0U)
AnnaBridge	156:ff21514d8981	2264	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2265	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2266	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
AnnaBridge	156:ff21514d8981	2267	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2268	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
AnnaBridge	156:ff21514d8981	2269	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2270	} while(0U)
AnnaBridge	156:ff21514d8981	2271	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
AnnaBridge	156:ff21514d8981	2272	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
AnnaBridge	156:ff21514d8981	2273	#endif /* STM32F415xx \|\| STM32F417xx */
AnnaBridge	156:ff21514d8981	2274	/**
AnnaBridge	156:ff21514d8981	2275	* @}
AnnaBridge	156:ff21514d8981	2276	*/
AnnaBridge	156:ff21514d8981	2277
AnnaBridge	156:ff21514d8981	2278
AnnaBridge	156:ff21514d8981	2279	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	2280	* @brief Get the enable or disable status of the AHB2 peripheral clock.
AnnaBridge	156:ff21514d8981	2281	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	2282	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	2283	* using it.
AnnaBridge	156:ff21514d8981	2284	* @{
AnnaBridge	156:ff21514d8981	2285	*/
AnnaBridge	156:ff21514d8981	2286	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
AnnaBridge	156:ff21514d8981	2287	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
AnnaBridge	156:ff21514d8981	2288
AnnaBridge	156:ff21514d8981	2289	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
AnnaBridge	156:ff21514d8981	2290	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
AnnaBridge	156:ff21514d8981	2291
AnnaBridge	156:ff21514d8981	2292	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
AnnaBridge	156:ff21514d8981	2293	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
AnnaBridge	156:ff21514d8981	2294	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
AnnaBridge	156:ff21514d8981	2295	#endif /* STM32F407xx \|\| STM32F417xx */
AnnaBridge	156:ff21514d8981	2296
AnnaBridge	156:ff21514d8981	2297	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
AnnaBridge	156:ff21514d8981	2298	#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
AnnaBridge	156:ff21514d8981	2299	#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
AnnaBridge	156:ff21514d8981	2300
AnnaBridge	156:ff21514d8981	2301	#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
AnnaBridge	156:ff21514d8981	2302	#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
AnnaBridge	156:ff21514d8981	2303	#endif /* STM32F415xx \|\| STM32F417xx */
AnnaBridge	156:ff21514d8981	2304	/**
AnnaBridge	156:ff21514d8981	2305	* @}
AnnaBridge	156:ff21514d8981	2306	*/
AnnaBridge	156:ff21514d8981	2307
AnnaBridge	156:ff21514d8981	2308	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	2309	* @brief Enables or disables the AHB3 peripheral clock.
AnnaBridge	156:ff21514d8981	2310	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	2311	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	2312	* using it.
AnnaBridge	156:ff21514d8981	2313	* @{
AnnaBridge	156:ff21514d8981	2314	*/
AnnaBridge	156:ff21514d8981	2315	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2316	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2317	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
AnnaBridge	156:ff21514d8981	2318	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2319	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
AnnaBridge	156:ff21514d8981	2320	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2321	} while(0U)
AnnaBridge	156:ff21514d8981	2322	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
AnnaBridge	156:ff21514d8981	2323	/**
AnnaBridge	156:ff21514d8981	2324	* @}
AnnaBridge	156:ff21514d8981	2325	*/
AnnaBridge	156:ff21514d8981	2326
AnnaBridge	156:ff21514d8981	2327	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	2328	* @brief Get the enable or disable status of the AHB3 peripheral clock.
AnnaBridge	156:ff21514d8981	2329	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	2330	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	2331	* using it.
AnnaBridge	156:ff21514d8981	2332	* @{
AnnaBridge	156:ff21514d8981	2333	*/
AnnaBridge	156:ff21514d8981	2334	#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
AnnaBridge	156:ff21514d8981	2335	#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
AnnaBridge	156:ff21514d8981	2336	/**
AnnaBridge	156:ff21514d8981	2337	* @}
AnnaBridge	156:ff21514d8981	2338	*/
AnnaBridge	156:ff21514d8981	2339
AnnaBridge	156:ff21514d8981	2340	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	2341	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	156:ff21514d8981	2342	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	2343	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	2344	* using it.
AnnaBridge	156:ff21514d8981	2345	* @{
AnnaBridge	156:ff21514d8981	2346	*/
AnnaBridge	156:ff21514d8981	2347	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2348	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2349	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	156:ff21514d8981	2350	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2351	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	156:ff21514d8981	2352	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2353	} while(0U)
AnnaBridge	156:ff21514d8981	2354	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2355	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2356	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	156:ff21514d8981	2357	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2358	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	156:ff21514d8981	2359	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2360	} while(0U)
AnnaBridge	156:ff21514d8981	2361	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2362	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2363	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	156:ff21514d8981	2364	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2365	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	156:ff21514d8981	2366	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2367	} while(0U)
AnnaBridge	156:ff21514d8981	2368	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2369	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2370	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	156:ff21514d8981	2371	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2372	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	156:ff21514d8981	2373	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2374	} while(0U)
AnnaBridge	156:ff21514d8981	2375	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2376	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2377	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	156:ff21514d8981	2378	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2379	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	156:ff21514d8981	2380	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2381	} while(0U)
AnnaBridge	156:ff21514d8981	2382	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2383	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2384	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	156:ff21514d8981	2385	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2386	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	156:ff21514d8981	2387	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2388	} while(0U)
AnnaBridge	156:ff21514d8981	2389	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2390	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2391	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	156:ff21514d8981	2392	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2393	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	156:ff21514d8981	2394	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2395	} while(0U)
AnnaBridge	156:ff21514d8981	2396	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2397	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2398	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	156:ff21514d8981	2399	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2400	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	156:ff21514d8981	2401	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2402	} while(0U)
AnnaBridge	156:ff21514d8981	2403	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2404	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2405	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	156:ff21514d8981	2406	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2407	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	156:ff21514d8981	2408	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2409	} while(0U)
AnnaBridge	156:ff21514d8981	2410	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2411	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2412	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	156:ff21514d8981	2413	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2414	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	156:ff21514d8981	2415	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2416	} while(0U)
AnnaBridge	156:ff21514d8981	2417	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2418	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2419	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	156:ff21514d8981	2420	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2421	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	156:ff21514d8981	2422	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2423	} while(0U)
AnnaBridge	156:ff21514d8981	2424	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2425	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2426	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	156:ff21514d8981	2427	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2428	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	156:ff21514d8981	2429	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2430	} while(0U)
AnnaBridge	156:ff21514d8981	2431	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2432	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2433	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	156:ff21514d8981	2434	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2435	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	156:ff21514d8981	2436	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2437	} while(0U)
AnnaBridge	156:ff21514d8981	2438	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2439	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2440	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	156:ff21514d8981	2441	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2442	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	156:ff21514d8981	2443	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2444	} while(0U)
AnnaBridge	156:ff21514d8981	2445	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2446	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2447	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	156:ff21514d8981	2448	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2449	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	156:ff21514d8981	2450	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2451	} while(0U)
AnnaBridge	156:ff21514d8981	2452	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2453	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2454	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	156:ff21514d8981	2455	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2456	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	156:ff21514d8981	2457	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2458	} while(0U)
AnnaBridge	156:ff21514d8981	2459	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
AnnaBridge	156:ff21514d8981	2460	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge	156:ff21514d8981	2461	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
AnnaBridge	156:ff21514d8981	2462	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge	156:ff21514d8981	2463	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
AnnaBridge	156:ff21514d8981	2464	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
AnnaBridge	156:ff21514d8981	2465	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
AnnaBridge	156:ff21514d8981	2466	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
AnnaBridge	156:ff21514d8981	2467	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
AnnaBridge	156:ff21514d8981	2468	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
AnnaBridge	156:ff21514d8981	2469	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
AnnaBridge	156:ff21514d8981	2470	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
AnnaBridge	156:ff21514d8981	2471	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
AnnaBridge	156:ff21514d8981	2472	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
AnnaBridge	156:ff21514d8981	2473	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
AnnaBridge	156:ff21514d8981	2474	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
AnnaBridge	156:ff21514d8981	2475	/**
AnnaBridge	156:ff21514d8981	2476	* @}
AnnaBridge	156:ff21514d8981	2477	*/
AnnaBridge	156:ff21514d8981	2478
AnnaBridge	156:ff21514d8981	2479	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	2480	* @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge	156:ff21514d8981	2481	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	2482	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	2483	* using it.
AnnaBridge	156:ff21514d8981	2484	* @{
AnnaBridge	156:ff21514d8981	2485	*/
AnnaBridge	156:ff21514d8981	2486	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
AnnaBridge	156:ff21514d8981	2487	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge	156:ff21514d8981	2488	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
AnnaBridge	156:ff21514d8981	2489	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge	156:ff21514d8981	2490	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
AnnaBridge	156:ff21514d8981	2491	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
AnnaBridge	156:ff21514d8981	2492	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
AnnaBridge	156:ff21514d8981	2493	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
AnnaBridge	156:ff21514d8981	2494	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
AnnaBridge	156:ff21514d8981	2495	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
AnnaBridge	156:ff21514d8981	2496	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
AnnaBridge	156:ff21514d8981	2497	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
AnnaBridge	156:ff21514d8981	2498	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
AnnaBridge	156:ff21514d8981	2499	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
AnnaBridge	156:ff21514d8981	2500	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
AnnaBridge	156:ff21514d8981	2501	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
AnnaBridge	156:ff21514d8981	2502
AnnaBridge	156:ff21514d8981	2503	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
AnnaBridge	156:ff21514d8981	2504	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge	156:ff21514d8981	2505	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
AnnaBridge	156:ff21514d8981	2506	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge	156:ff21514d8981	2507	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
AnnaBridge	156:ff21514d8981	2508	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
AnnaBridge	156:ff21514d8981	2509	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
AnnaBridge	156:ff21514d8981	2510	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
AnnaBridge	156:ff21514d8981	2511	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
AnnaBridge	156:ff21514d8981	2512	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
AnnaBridge	156:ff21514d8981	2513	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
AnnaBridge	156:ff21514d8981	2514	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
AnnaBridge	156:ff21514d8981	2515	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
AnnaBridge	156:ff21514d8981	2516	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
AnnaBridge	156:ff21514d8981	2517	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
AnnaBridge	156:ff21514d8981	2518	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
AnnaBridge	156:ff21514d8981	2519	/**
AnnaBridge	156:ff21514d8981	2520	* @}
AnnaBridge	156:ff21514d8981	2521	*/
AnnaBridge	156:ff21514d8981	2522
AnnaBridge	156:ff21514d8981	2523	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	2524	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	156:ff21514d8981	2525	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	2526	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	2527	* using it.
AnnaBridge	156:ff21514d8981	2528	* @{
AnnaBridge	156:ff21514d8981	2529	*/
AnnaBridge	156:ff21514d8981	2530	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2531	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2532	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	156:ff21514d8981	2533	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2534	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	156:ff21514d8981	2535	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2536	} while(0U)
AnnaBridge	156:ff21514d8981	2537	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2538	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2539	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
AnnaBridge	156:ff21514d8981	2540	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2541	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
AnnaBridge	156:ff21514d8981	2542	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2543	} while(0U)
AnnaBridge	156:ff21514d8981	2544	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2545	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2546	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
AnnaBridge	156:ff21514d8981	2547	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2548	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
AnnaBridge	156:ff21514d8981	2549	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2550	} while(0U)
AnnaBridge	156:ff21514d8981	2551	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2552	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2553	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	156:ff21514d8981	2554	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2555	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	156:ff21514d8981	2556	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2557	} while(0U)
AnnaBridge	156:ff21514d8981	2558	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2559	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2560	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	156:ff21514d8981	2561	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2562	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	156:ff21514d8981	2563	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2564	} while(0U)
AnnaBridge	156:ff21514d8981	2565	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2566	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2567	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	156:ff21514d8981	2568	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2569	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	156:ff21514d8981	2570	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2571	} while(0U)
AnnaBridge	156:ff21514d8981	2572
AnnaBridge	156:ff21514d8981	2573	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
AnnaBridge	156:ff21514d8981	2574	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
AnnaBridge	156:ff21514d8981	2575	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
AnnaBridge	156:ff21514d8981	2576	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
AnnaBridge	156:ff21514d8981	2577	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
AnnaBridge	156:ff21514d8981	2578	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
AnnaBridge	156:ff21514d8981	2579	/**
AnnaBridge	156:ff21514d8981	2580	* @}
AnnaBridge	156:ff21514d8981	2581	*/
AnnaBridge	156:ff21514d8981	2582
AnnaBridge	156:ff21514d8981	2583	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	2584	* @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge	156:ff21514d8981	2585	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	2586	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	2587	* using it.
AnnaBridge	156:ff21514d8981	2588	* @{
AnnaBridge	156:ff21514d8981	2589	*/
AnnaBridge	156:ff21514d8981	2590	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
AnnaBridge	156:ff21514d8981	2591	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
AnnaBridge	156:ff21514d8981	2592	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
AnnaBridge	156:ff21514d8981	2593	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
AnnaBridge	156:ff21514d8981	2594	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
AnnaBridge	156:ff21514d8981	2595	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
AnnaBridge	156:ff21514d8981	2596
AnnaBridge	156:ff21514d8981	2597	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
AnnaBridge	156:ff21514d8981	2598	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
AnnaBridge	156:ff21514d8981	2599	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
AnnaBridge	156:ff21514d8981	2600	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
AnnaBridge	156:ff21514d8981	2601	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
AnnaBridge	156:ff21514d8981	2602	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
AnnaBridge	156:ff21514d8981	2603	/**
AnnaBridge	156:ff21514d8981	2604	* @}
AnnaBridge	156:ff21514d8981	2605	*/
AnnaBridge	156:ff21514d8981	2606
AnnaBridge	156:ff21514d8981	2607	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
AnnaBridge	156:ff21514d8981	2608	* @brief Force or release AHB1 peripheral reset.
AnnaBridge	156:ff21514d8981	2609	* @{
AnnaBridge	156:ff21514d8981	2610	*/
AnnaBridge	156:ff21514d8981	2611	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
AnnaBridge	156:ff21514d8981	2612	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
AnnaBridge	156:ff21514d8981	2613	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
AnnaBridge	156:ff21514d8981	2614	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
AnnaBridge	156:ff21514d8981	2615	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
AnnaBridge	156:ff21514d8981	2616	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
AnnaBridge	156:ff21514d8981	2617	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
AnnaBridge	156:ff21514d8981	2618	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
AnnaBridge	156:ff21514d8981	2619
AnnaBridge	156:ff21514d8981	2620	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
AnnaBridge	156:ff21514d8981	2621	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
AnnaBridge	156:ff21514d8981	2622	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
AnnaBridge	156:ff21514d8981	2623	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
AnnaBridge	156:ff21514d8981	2624	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
AnnaBridge	156:ff21514d8981	2625	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
AnnaBridge	156:ff21514d8981	2626	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
AnnaBridge	156:ff21514d8981	2627	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
AnnaBridge	156:ff21514d8981	2628	/**
AnnaBridge	156:ff21514d8981	2629	* @}
AnnaBridge	156:ff21514d8981	2630	*/
AnnaBridge	156:ff21514d8981	2631
AnnaBridge	156:ff21514d8981	2632	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
AnnaBridge	156:ff21514d8981	2633	* @brief Force or release AHB2 peripheral reset.
AnnaBridge	156:ff21514d8981	2634	* @{
AnnaBridge	156:ff21514d8981	2635	*/
AnnaBridge	156:ff21514d8981	2636	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
AnnaBridge	156:ff21514d8981	2637	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
AnnaBridge	156:ff21514d8981	2638
AnnaBridge	156:ff21514d8981	2639	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
AnnaBridge	156:ff21514d8981	2640	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
AnnaBridge	156:ff21514d8981	2641	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
AnnaBridge	156:ff21514d8981	2642	#endif /* STM32F407xx \|\| STM32F417xx */
AnnaBridge	156:ff21514d8981	2643
AnnaBridge	156:ff21514d8981	2644	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
AnnaBridge	156:ff21514d8981	2645	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
AnnaBridge	156:ff21514d8981	2646	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
AnnaBridge	156:ff21514d8981	2647
AnnaBridge	156:ff21514d8981	2648	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
AnnaBridge	156:ff21514d8981	2649	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
AnnaBridge	156:ff21514d8981	2650	#endif /* STM32F415xx \|\| STM32F417xx */
AnnaBridge	156:ff21514d8981	2651
AnnaBridge	156:ff21514d8981	2652	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	156:ff21514d8981	2653	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	156:ff21514d8981	2654
AnnaBridge	156:ff21514d8981	2655	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
AnnaBridge	156:ff21514d8981	2656	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
AnnaBridge	156:ff21514d8981	2657	/**
AnnaBridge	156:ff21514d8981	2658	* @}
AnnaBridge	156:ff21514d8981	2659	*/
AnnaBridge	156:ff21514d8981	2660
AnnaBridge	156:ff21514d8981	2661	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
AnnaBridge	156:ff21514d8981	2662	* @brief Force or release AHB3 peripheral reset.
AnnaBridge	156:ff21514d8981	2663	* @{
AnnaBridge	156:ff21514d8981	2664	*/
AnnaBridge	156:ff21514d8981	2665	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
AnnaBridge	156:ff21514d8981	2666	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
AnnaBridge	156:ff21514d8981	2667
AnnaBridge	156:ff21514d8981	2668	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
AnnaBridge	156:ff21514d8981	2669	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
AnnaBridge	156:ff21514d8981	2670	/**
AnnaBridge	156:ff21514d8981	2671	* @}
AnnaBridge	156:ff21514d8981	2672	*/
AnnaBridge	156:ff21514d8981	2673
AnnaBridge	156:ff21514d8981	2674	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
AnnaBridge	156:ff21514d8981	2675	* @brief Force or release APB1 peripheral reset.
AnnaBridge	156:ff21514d8981	2676	* @{
AnnaBridge	156:ff21514d8981	2677	*/
AnnaBridge	156:ff21514d8981	2678	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
AnnaBridge	156:ff21514d8981	2679	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
AnnaBridge	156:ff21514d8981	2680	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
AnnaBridge	156:ff21514d8981	2681	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
AnnaBridge	156:ff21514d8981	2682	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
AnnaBridge	156:ff21514d8981	2683	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
AnnaBridge	156:ff21514d8981	2684	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
AnnaBridge	156:ff21514d8981	2685	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
AnnaBridge	156:ff21514d8981	2686	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
AnnaBridge	156:ff21514d8981	2687	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
AnnaBridge	156:ff21514d8981	2688	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
AnnaBridge	156:ff21514d8981	2689	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
AnnaBridge	156:ff21514d8981	2690	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
AnnaBridge	156:ff21514d8981	2691	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
AnnaBridge	156:ff21514d8981	2692	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
AnnaBridge	156:ff21514d8981	2693	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
AnnaBridge	156:ff21514d8981	2694
AnnaBridge	156:ff21514d8981	2695	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
AnnaBridge	156:ff21514d8981	2696	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge	156:ff21514d8981	2697	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge	156:ff21514d8981	2698	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge	156:ff21514d8981	2699	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
AnnaBridge	156:ff21514d8981	2700	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
AnnaBridge	156:ff21514d8981	2701	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
AnnaBridge	156:ff21514d8981	2702	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
AnnaBridge	156:ff21514d8981	2703	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
AnnaBridge	156:ff21514d8981	2704	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
AnnaBridge	156:ff21514d8981	2705	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
AnnaBridge	156:ff21514d8981	2706	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
AnnaBridge	156:ff21514d8981	2707	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
AnnaBridge	156:ff21514d8981	2708	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
AnnaBridge	156:ff21514d8981	2709	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
AnnaBridge	156:ff21514d8981	2710	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
AnnaBridge	156:ff21514d8981	2711	/**
AnnaBridge	156:ff21514d8981	2712	* @}
AnnaBridge	156:ff21514d8981	2713	*/
AnnaBridge	156:ff21514d8981	2714
AnnaBridge	156:ff21514d8981	2715	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
AnnaBridge	156:ff21514d8981	2716	* @brief Force or release APB2 peripheral reset.
AnnaBridge	156:ff21514d8981	2717	* @{
AnnaBridge	156:ff21514d8981	2718	*/
AnnaBridge	156:ff21514d8981	2719	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
AnnaBridge	156:ff21514d8981	2720	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
AnnaBridge	156:ff21514d8981	2721	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
AnnaBridge	156:ff21514d8981	2722	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
AnnaBridge	156:ff21514d8981	2723
AnnaBridge	156:ff21514d8981	2724	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
AnnaBridge	156:ff21514d8981	2725	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
AnnaBridge	156:ff21514d8981	2726	#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
AnnaBridge	156:ff21514d8981	2727	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
AnnaBridge	156:ff21514d8981	2728	/**
AnnaBridge	156:ff21514d8981	2729	* @}
AnnaBridge	156:ff21514d8981	2730	*/
AnnaBridge	156:ff21514d8981	2731
AnnaBridge	156:ff21514d8981	2732	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	2733	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	2734	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	2735	* power consumption.
AnnaBridge	156:ff21514d8981	2736	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	2737	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	2738	* @{
AnnaBridge	156:ff21514d8981	2739	*/
AnnaBridge	156:ff21514d8981	2740	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	156:ff21514d8981	2741	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	156:ff21514d8981	2742	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge	156:ff21514d8981	2743	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge	156:ff21514d8981	2744	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
AnnaBridge	156:ff21514d8981	2745	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	156:ff21514d8981	2746	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
AnnaBridge	156:ff21514d8981	2747	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
AnnaBridge	156:ff21514d8981	2748	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
AnnaBridge	156:ff21514d8981	2749	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
AnnaBridge	156:ff21514d8981	2750	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
AnnaBridge	156:ff21514d8981	2751	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
AnnaBridge	156:ff21514d8981	2752	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	156:ff21514d8981	2753	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	156:ff21514d8981	2754	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	156:ff21514d8981	2755	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
AnnaBridge	156:ff21514d8981	2756
AnnaBridge	156:ff21514d8981	2757	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	156:ff21514d8981	2758	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	156:ff21514d8981	2759	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge	156:ff21514d8981	2760	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge	156:ff21514d8981	2761	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
AnnaBridge	156:ff21514d8981	2762	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	156:ff21514d8981	2763	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
AnnaBridge	156:ff21514d8981	2764	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
AnnaBridge	156:ff21514d8981	2765	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
AnnaBridge	156:ff21514d8981	2766	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
AnnaBridge	156:ff21514d8981	2767	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
AnnaBridge	156:ff21514d8981	2768	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
AnnaBridge	156:ff21514d8981	2769	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	156:ff21514d8981	2770	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	156:ff21514d8981	2771	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	156:ff21514d8981	2772	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
AnnaBridge	156:ff21514d8981	2773	/**
AnnaBridge	156:ff21514d8981	2774	* @}
AnnaBridge	156:ff21514d8981	2775	*/
AnnaBridge	156:ff21514d8981	2776
AnnaBridge	156:ff21514d8981	2777	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	2778	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	2779	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	2780	* power consumption.
AnnaBridge	156:ff21514d8981	2781	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	2782	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	2783	* @{
AnnaBridge	156:ff21514d8981	2784	*/
AnnaBridge	156:ff21514d8981	2785	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	156:ff21514d8981	2786	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	156:ff21514d8981	2787
AnnaBridge	156:ff21514d8981	2788	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
AnnaBridge	156:ff21514d8981	2789	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
AnnaBridge	156:ff21514d8981	2790
AnnaBridge	156:ff21514d8981	2791	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
AnnaBridge	156:ff21514d8981	2792	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
AnnaBridge	156:ff21514d8981	2793	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
AnnaBridge	156:ff21514d8981	2794	#endif /* STM32F407xx \|\| STM32F417xx */
AnnaBridge	156:ff21514d8981	2795
AnnaBridge	156:ff21514d8981	2796	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
AnnaBridge	156:ff21514d8981	2797	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
AnnaBridge	156:ff21514d8981	2798	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
AnnaBridge	156:ff21514d8981	2799
AnnaBridge	156:ff21514d8981	2800	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
AnnaBridge	156:ff21514d8981	2801	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
AnnaBridge	156:ff21514d8981	2802	#endif /* STM32F415xx \|\| STM32F417xx */
AnnaBridge	156:ff21514d8981	2803	/**
AnnaBridge	156:ff21514d8981	2804	* @}
AnnaBridge	156:ff21514d8981	2805	*/
AnnaBridge	156:ff21514d8981	2806
AnnaBridge	156:ff21514d8981	2807	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	2808	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	2809	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	2810	* power consumption.
AnnaBridge	156:ff21514d8981	2811	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	2812	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	2813	* @{
AnnaBridge	156:ff21514d8981	2814	*/
AnnaBridge	156:ff21514d8981	2815	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
AnnaBridge	156:ff21514d8981	2816	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
AnnaBridge	156:ff21514d8981	2817	/**
AnnaBridge	156:ff21514d8981	2818	* @}
AnnaBridge	156:ff21514d8981	2819	*/
AnnaBridge	156:ff21514d8981	2820
AnnaBridge	156:ff21514d8981	2821	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	2822	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	2823	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	2824	* power consumption.
AnnaBridge	156:ff21514d8981	2825	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	2826	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	2827	* @{
AnnaBridge	156:ff21514d8981	2828	*/
AnnaBridge	156:ff21514d8981	2829	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	156:ff21514d8981	2830	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	156:ff21514d8981	2831	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
AnnaBridge	156:ff21514d8981	2832	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
AnnaBridge	156:ff21514d8981	2833	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	156:ff21514d8981	2834	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
AnnaBridge	156:ff21514d8981	2835	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
AnnaBridge	156:ff21514d8981	2836	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
AnnaBridge	156:ff21514d8981	2837	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
AnnaBridge	156:ff21514d8981	2838	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	156:ff21514d8981	2839	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
AnnaBridge	156:ff21514d8981	2840	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	156:ff21514d8981	2841	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	156:ff21514d8981	2842	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	156:ff21514d8981	2843	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	156:ff21514d8981	2844	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	156:ff21514d8981	2845
AnnaBridge	156:ff21514d8981	2846	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	156:ff21514d8981	2847	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	156:ff21514d8981	2848	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	156:ff21514d8981	2849	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	156:ff21514d8981	2850	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	156:ff21514d8981	2851	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	156:ff21514d8981	2852	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	156:ff21514d8981	2853	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
AnnaBridge	156:ff21514d8981	2854	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
AnnaBridge	156:ff21514d8981	2855	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	156:ff21514d8981	2856	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
AnnaBridge	156:ff21514d8981	2857	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
AnnaBridge	156:ff21514d8981	2858	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
AnnaBridge	156:ff21514d8981	2859	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
AnnaBridge	156:ff21514d8981	2860	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	156:ff21514d8981	2861	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
AnnaBridge	156:ff21514d8981	2862	/**
AnnaBridge	156:ff21514d8981	2863	* @}
AnnaBridge	156:ff21514d8981	2864	*/
AnnaBridge	156:ff21514d8981	2865
AnnaBridge	156:ff21514d8981	2866	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	2867	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	2868	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	2869	* power consumption.
AnnaBridge	156:ff21514d8981	2870	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	2871	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	2872	* @{
AnnaBridge	156:ff21514d8981	2873	*/
AnnaBridge	156:ff21514d8981	2874	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	156:ff21514d8981	2875	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
AnnaBridge	156:ff21514d8981	2876	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
AnnaBridge	156:ff21514d8981	2877	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	156:ff21514d8981	2878	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	156:ff21514d8981	2879	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	156:ff21514d8981	2880
AnnaBridge	156:ff21514d8981	2881	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	156:ff21514d8981	2882	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	156:ff21514d8981	2883	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	156:ff21514d8981	2884	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	156:ff21514d8981	2885	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
AnnaBridge	156:ff21514d8981	2886	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
AnnaBridge	156:ff21514d8981	2887	/**
AnnaBridge	156:ff21514d8981	2888	* @}
AnnaBridge	156:ff21514d8981	2889	*/
AnnaBridge	156:ff21514d8981	2890	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	156:ff21514d8981	2891	/----------------------------------------------------------------------------/
AnnaBridge	156:ff21514d8981	2892
AnnaBridge	156:ff21514d8981	2893	/------------------------- STM32F401xE/STM32F401xC --------------------------/
AnnaBridge	156:ff21514d8981	2894	#if defined(STM32F401xC) \|\| defined(STM32F401xE)
AnnaBridge	156:ff21514d8981	2895	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	2896	* @brief Enable or disable the AHB1 peripheral clock.
AnnaBridge	156:ff21514d8981	2897	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	2898	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	2899	* using it.
AnnaBridge	156:ff21514d8981	2900	* @{
AnnaBridge	156:ff21514d8981	2901	*/
AnnaBridge	156:ff21514d8981	2902	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2903	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2904	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	156:ff21514d8981	2905	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2906	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	156:ff21514d8981	2907	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2908	} while(0U)
AnnaBridge	156:ff21514d8981	2909	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2910	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2911	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	156:ff21514d8981	2912	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2913	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	156:ff21514d8981	2914	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2915	} while(0U)
AnnaBridge	156:ff21514d8981	2916	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2917	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2918	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	156:ff21514d8981	2919	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2920	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	156:ff21514d8981	2921	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2922	} while(0U)
AnnaBridge	156:ff21514d8981	2923	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2924	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2925	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
AnnaBridge	156:ff21514d8981	2926	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2927	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
AnnaBridge	156:ff21514d8981	2928	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	2929	} while(0U)
AnnaBridge	156:ff21514d8981	2930
AnnaBridge	156:ff21514d8981	2931	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
AnnaBridge	156:ff21514d8981	2932	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
AnnaBridge	156:ff21514d8981	2933	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
AnnaBridge	156:ff21514d8981	2934	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
AnnaBridge	156:ff21514d8981	2935	/**
AnnaBridge	156:ff21514d8981	2936	* @}
AnnaBridge	156:ff21514d8981	2937	*/
AnnaBridge	156:ff21514d8981	2938
AnnaBridge	156:ff21514d8981	2939	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	2940	* @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge	156:ff21514d8981	2941	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	2942	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	2943	* using it.
AnnaBridge	156:ff21514d8981	2944	* @{
AnnaBridge	156:ff21514d8981	2945	*/
AnnaBridge	156:ff21514d8981	2946	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
AnnaBridge	156:ff21514d8981	2947	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
AnnaBridge	156:ff21514d8981	2948	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
AnnaBridge	156:ff21514d8981	2949	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
AnnaBridge	156:ff21514d8981	2950
AnnaBridge	156:ff21514d8981	2951	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
AnnaBridge	156:ff21514d8981	2952	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
AnnaBridge	156:ff21514d8981	2953	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
AnnaBridge	156:ff21514d8981	2954	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
AnnaBridge	156:ff21514d8981	2955	/**
AnnaBridge	156:ff21514d8981	2956	* @}
AnnaBridge	156:ff21514d8981	2957	*/
AnnaBridge	156:ff21514d8981	2958
AnnaBridge	156:ff21514d8981	2959	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	2960	* @brief Enable or disable the AHB2 peripheral clock.
AnnaBridge	156:ff21514d8981	2961	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	2962	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	2963	* using it.
AnnaBridge	156:ff21514d8981	2964	* @{
AnnaBridge	156:ff21514d8981	2965	*/
AnnaBridge	156:ff21514d8981	2966	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
AnnaBridge	156:ff21514d8981	2967	__HAL_RCC_SYSCFG_CLK_ENABLE();\
AnnaBridge	156:ff21514d8981	2968	}while(0U)
AnnaBridge	156:ff21514d8981	2969
AnnaBridge	156:ff21514d8981	2970	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
AnnaBridge	156:ff21514d8981	2971	/**
AnnaBridge	156:ff21514d8981	2972	* @}
AnnaBridge	156:ff21514d8981	2973	*/
AnnaBridge	156:ff21514d8981	2974
AnnaBridge	156:ff21514d8981	2975	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	2976	* @brief Get the enable or disable status of the AHB2 peripheral clock.
AnnaBridge	156:ff21514d8981	2977	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	2978	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	2979	* using it.
AnnaBridge	156:ff21514d8981	2980	* @{
AnnaBridge	156:ff21514d8981	2981	*/
AnnaBridge	156:ff21514d8981	2982	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
AnnaBridge	156:ff21514d8981	2983	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
AnnaBridge	156:ff21514d8981	2984	/**
AnnaBridge	156:ff21514d8981	2985	* @}
AnnaBridge	156:ff21514d8981	2986	*/
AnnaBridge	156:ff21514d8981	2987
AnnaBridge	156:ff21514d8981	2988	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	2989	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	156:ff21514d8981	2990	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	2991	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	2992	* using it.
AnnaBridge	156:ff21514d8981	2993	* @{
AnnaBridge	156:ff21514d8981	2994	*/
AnnaBridge	156:ff21514d8981	2995	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	2996	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	2997	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	156:ff21514d8981	2998	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	2999	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	156:ff21514d8981	3000	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3001	} while(0U)
AnnaBridge	156:ff21514d8981	3002	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3003	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3004	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	156:ff21514d8981	3005	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3006	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	156:ff21514d8981	3007	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3008	} while(0U)
AnnaBridge	156:ff21514d8981	3009	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3010	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3011	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	156:ff21514d8981	3012	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3013	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	156:ff21514d8981	3014	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3015	} while(0U)
AnnaBridge	156:ff21514d8981	3016	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3017	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3018	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	156:ff21514d8981	3019	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3020	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	156:ff21514d8981	3021	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3022	} while(0U)
AnnaBridge	156:ff21514d8981	3023	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3024	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3025	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	156:ff21514d8981	3026	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3027	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	156:ff21514d8981	3028	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3029	} while(0U)
AnnaBridge	156:ff21514d8981	3030	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
AnnaBridge	156:ff21514d8981	3031	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge	156:ff21514d8981	3032	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
AnnaBridge	156:ff21514d8981	3033	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge	156:ff21514d8981	3034	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
AnnaBridge	156:ff21514d8981	3035	/**
AnnaBridge	156:ff21514d8981	3036	* @}
AnnaBridge	156:ff21514d8981	3037	*/
AnnaBridge	156:ff21514d8981	3038
AnnaBridge	156:ff21514d8981	3039	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	3040	* @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge	156:ff21514d8981	3041	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	3042	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	3043	* using it.
AnnaBridge	156:ff21514d8981	3044	* @{
AnnaBridge	156:ff21514d8981	3045	*/
AnnaBridge	156:ff21514d8981	3046	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
AnnaBridge	156:ff21514d8981	3047	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge	156:ff21514d8981	3048	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
AnnaBridge	156:ff21514d8981	3049	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge	156:ff21514d8981	3050	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
AnnaBridge	156:ff21514d8981	3051
AnnaBridge	156:ff21514d8981	3052	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
AnnaBridge	156:ff21514d8981	3053	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge	156:ff21514d8981	3054	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
AnnaBridge	156:ff21514d8981	3055	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge	156:ff21514d8981	3056	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
AnnaBridge	156:ff21514d8981	3057	/**
AnnaBridge	156:ff21514d8981	3058	* @}
AnnaBridge	156:ff21514d8981	3059	*/
AnnaBridge	156:ff21514d8981	3060
AnnaBridge	156:ff21514d8981	3061	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	3062	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	156:ff21514d8981	3063	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	3064	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	3065	* using it.
AnnaBridge	156:ff21514d8981	3066	* @{
AnnaBridge	156:ff21514d8981	3067	*/
AnnaBridge	156:ff21514d8981	3068	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3069	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3070	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	156:ff21514d8981	3071	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3072	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	156:ff21514d8981	3073	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3074	} while(0U)
AnnaBridge	156:ff21514d8981	3075	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3076	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3077	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	156:ff21514d8981	3078	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3079	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	156:ff21514d8981	3080	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3081	} while(0U)
AnnaBridge	156:ff21514d8981	3082	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3083	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3084	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	156:ff21514d8981	3085	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3086	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	156:ff21514d8981	3087	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3088	} while(0U)
AnnaBridge	156:ff21514d8981	3089
AnnaBridge	156:ff21514d8981	3090	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
AnnaBridge	156:ff21514d8981	3091	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
AnnaBridge	156:ff21514d8981	3092	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
AnnaBridge	156:ff21514d8981	3093	/**
AnnaBridge	156:ff21514d8981	3094	* @}
AnnaBridge	156:ff21514d8981	3095	*/
AnnaBridge	156:ff21514d8981	3096
AnnaBridge	156:ff21514d8981	3097	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	3098	* @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge	156:ff21514d8981	3099	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	3100	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	3101	* using it.
AnnaBridge	156:ff21514d8981	3102	* @{
AnnaBridge	156:ff21514d8981	3103	*/
AnnaBridge	156:ff21514d8981	3104	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
AnnaBridge	156:ff21514d8981	3105	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
AnnaBridge	156:ff21514d8981	3106	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
AnnaBridge	156:ff21514d8981	3107
AnnaBridge	156:ff21514d8981	3108	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
AnnaBridge	156:ff21514d8981	3109	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
AnnaBridge	156:ff21514d8981	3110	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
AnnaBridge	156:ff21514d8981	3111	/**
AnnaBridge	156:ff21514d8981	3112	* @}
AnnaBridge	156:ff21514d8981	3113	*/
AnnaBridge	156:ff21514d8981	3114	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
AnnaBridge	156:ff21514d8981	3115	* @brief Force or release AHB1 peripheral reset.
AnnaBridge	156:ff21514d8981	3116	* @{
AnnaBridge	156:ff21514d8981	3117	*/
AnnaBridge	156:ff21514d8981	3118	#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
AnnaBridge	156:ff21514d8981	3119	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
AnnaBridge	156:ff21514d8981	3120	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
AnnaBridge	156:ff21514d8981	3121	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
AnnaBridge	156:ff21514d8981	3122
AnnaBridge	156:ff21514d8981	3123	#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
AnnaBridge	156:ff21514d8981	3124	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
AnnaBridge	156:ff21514d8981	3125	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
AnnaBridge	156:ff21514d8981	3126	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
AnnaBridge	156:ff21514d8981	3127	/**
AnnaBridge	156:ff21514d8981	3128	* @}
AnnaBridge	156:ff21514d8981	3129	*/
AnnaBridge	156:ff21514d8981	3130
AnnaBridge	156:ff21514d8981	3131	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
AnnaBridge	156:ff21514d8981	3132	* @brief Force or release AHB2 peripheral reset.
AnnaBridge	156:ff21514d8981	3133	* @{
AnnaBridge	156:ff21514d8981	3134	*/
AnnaBridge	156:ff21514d8981	3135	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
AnnaBridge	156:ff21514d8981	3136	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	156:ff21514d8981	3137
AnnaBridge	156:ff21514d8981	3138	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
AnnaBridge	156:ff21514d8981	3139	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	156:ff21514d8981	3140	/**
AnnaBridge	156:ff21514d8981	3141	* @}
AnnaBridge	156:ff21514d8981	3142	*/
AnnaBridge	156:ff21514d8981	3143
AnnaBridge	156:ff21514d8981	3144	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
AnnaBridge	156:ff21514d8981	3145	* @brief Force or release APB1 peripheral reset.
AnnaBridge	156:ff21514d8981	3146	* @{
AnnaBridge	156:ff21514d8981	3147	*/
AnnaBridge	156:ff21514d8981	3148	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
AnnaBridge	156:ff21514d8981	3149	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
AnnaBridge	156:ff21514d8981	3150	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
AnnaBridge	156:ff21514d8981	3151	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
AnnaBridge	156:ff21514d8981	3152	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
AnnaBridge	156:ff21514d8981	3153	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
AnnaBridge	156:ff21514d8981	3154
AnnaBridge	156:ff21514d8981	3155	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
AnnaBridge	156:ff21514d8981	3156	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
AnnaBridge	156:ff21514d8981	3157	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge	156:ff21514d8981	3158	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge	156:ff21514d8981	3159	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge	156:ff21514d8981	3160	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
AnnaBridge	156:ff21514d8981	3161	/**
AnnaBridge	156:ff21514d8981	3162	* @}
AnnaBridge	156:ff21514d8981	3163	*/
AnnaBridge	156:ff21514d8981	3164
AnnaBridge	156:ff21514d8981	3165	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
AnnaBridge	156:ff21514d8981	3166	* @brief Force or release APB2 peripheral reset.
AnnaBridge	156:ff21514d8981	3167	* @{
AnnaBridge	156:ff21514d8981	3168	*/
AnnaBridge	156:ff21514d8981	3169	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
AnnaBridge	156:ff21514d8981	3170	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
AnnaBridge	156:ff21514d8981	3171	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
AnnaBridge	156:ff21514d8981	3172	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
AnnaBridge	156:ff21514d8981	3173
AnnaBridge	156:ff21514d8981	3174	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
AnnaBridge	156:ff21514d8981	3175	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
AnnaBridge	156:ff21514d8981	3176	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
AnnaBridge	156:ff21514d8981	3177	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
AnnaBridge	156:ff21514d8981	3178	/**
AnnaBridge	156:ff21514d8981	3179	* @}
AnnaBridge	156:ff21514d8981	3180	*/
AnnaBridge	156:ff21514d8981	3181
AnnaBridge	156:ff21514d8981	3182	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
AnnaBridge	156:ff21514d8981	3183	* @brief Force or release AHB3 peripheral reset.
AnnaBridge	156:ff21514d8981	3184	* @{
AnnaBridge	156:ff21514d8981	3185	*/
AnnaBridge	156:ff21514d8981	3186	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
AnnaBridge	156:ff21514d8981	3187	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
AnnaBridge	156:ff21514d8981	3188	/**
AnnaBridge	156:ff21514d8981	3189	* @}
AnnaBridge	156:ff21514d8981	3190	*/
AnnaBridge	156:ff21514d8981	3191
AnnaBridge	156:ff21514d8981	3192	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	3193	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	3194	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	3195	* power consumption.
AnnaBridge	156:ff21514d8981	3196	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	3197	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	3198	* @{
AnnaBridge	156:ff21514d8981	3199	*/
AnnaBridge	156:ff21514d8981	3200	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	156:ff21514d8981	3201	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	156:ff21514d8981	3202	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	156:ff21514d8981	3203	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	156:ff21514d8981	3204	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	156:ff21514d8981	3205
AnnaBridge	156:ff21514d8981	3206	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	156:ff21514d8981	3207	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	156:ff21514d8981	3208	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	156:ff21514d8981	3209	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	156:ff21514d8981	3210	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	156:ff21514d8981	3211	/**
AnnaBridge	156:ff21514d8981	3212	* @}
AnnaBridge	156:ff21514d8981	3213	*/
AnnaBridge	156:ff21514d8981	3214
AnnaBridge	156:ff21514d8981	3215	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	3216	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	3217	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	3218	* power consumption.
AnnaBridge	156:ff21514d8981	3219	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	3220	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	3221	* @{
AnnaBridge	156:ff21514d8981	3222	*/
AnnaBridge	156:ff21514d8981	3223	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	156:ff21514d8981	3224
AnnaBridge	156:ff21514d8981	3225	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	156:ff21514d8981	3226	/**
AnnaBridge	156:ff21514d8981	3227	* @}
AnnaBridge	156:ff21514d8981	3228	*/
AnnaBridge	156:ff21514d8981	3229
AnnaBridge	156:ff21514d8981	3230	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	3231	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	3232	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	3233	* power consumption.
AnnaBridge	156:ff21514d8981	3234	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	3235	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	3236	* @{
AnnaBridge	156:ff21514d8981	3237	*/
AnnaBridge	156:ff21514d8981	3238	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	156:ff21514d8981	3239	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	156:ff21514d8981	3240	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	156:ff21514d8981	3241	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	156:ff21514d8981	3242	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	156:ff21514d8981	3243
AnnaBridge	156:ff21514d8981	3244	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	156:ff21514d8981	3245	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	156:ff21514d8981	3246	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	156:ff21514d8981	3247	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	156:ff21514d8981	3248	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	156:ff21514d8981	3249	/**
AnnaBridge	156:ff21514d8981	3250	* @}
AnnaBridge	156:ff21514d8981	3251	*/
AnnaBridge	156:ff21514d8981	3252
AnnaBridge	156:ff21514d8981	3253	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	3254	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	3255	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	3256	* power consumption.
AnnaBridge	156:ff21514d8981	3257	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	3258	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	3259	* @{
AnnaBridge	156:ff21514d8981	3260	*/
AnnaBridge	156:ff21514d8981	3261	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	156:ff21514d8981	3262	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	156:ff21514d8981	3263	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	156:ff21514d8981	3264
AnnaBridge	156:ff21514d8981	3265	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	156:ff21514d8981	3266	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	156:ff21514d8981	3267	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	156:ff21514d8981	3268	/**
AnnaBridge	156:ff21514d8981	3269	* @}
AnnaBridge	156:ff21514d8981	3270	*/
AnnaBridge	156:ff21514d8981	3271	#endif /* STM32F401xC \|\| STM32F401xE*/
AnnaBridge	156:ff21514d8981	3272	/----------------------------------------------------------------------------/
AnnaBridge	156:ff21514d8981	3273
AnnaBridge	156:ff21514d8981	3274	/-------------------------------- STM32F410xx -------------------------------/
AnnaBridge	156:ff21514d8981	3275	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	156:ff21514d8981	3276	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	3277	* @brief Enables or disables the AHB1 peripheral clock.
AnnaBridge	156:ff21514d8981	3278	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	3279	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	3280	* using it.
AnnaBridge	156:ff21514d8981	3281	* @{
AnnaBridge	156:ff21514d8981	3282	*/
AnnaBridge	156:ff21514d8981	3283	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3284	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3285	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	156:ff21514d8981	3286	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3287	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	156:ff21514d8981	3288	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3289	} while(0U)
AnnaBridge	156:ff21514d8981	3290	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3291	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3292	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
AnnaBridge	156:ff21514d8981	3293	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3294	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
AnnaBridge	156:ff21514d8981	3295	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3296	} while(0U)
AnnaBridge	156:ff21514d8981	3297	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
AnnaBridge	156:ff21514d8981	3298	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))
AnnaBridge	156:ff21514d8981	3299	/**
AnnaBridge	156:ff21514d8981	3300	* @}
AnnaBridge	156:ff21514d8981	3301	*/
AnnaBridge	156:ff21514d8981	3302
AnnaBridge	156:ff21514d8981	3303	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	3304	* @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge	156:ff21514d8981	3305	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	3306	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	3307	* using it.
AnnaBridge	156:ff21514d8981	3308	* @{
AnnaBridge	156:ff21514d8981	3309	*/
AnnaBridge	156:ff21514d8981	3310	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
AnnaBridge	156:ff21514d8981	3311	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET)
AnnaBridge	156:ff21514d8981	3312
AnnaBridge	156:ff21514d8981	3313	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
AnnaBridge	156:ff21514d8981	3314	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET)
AnnaBridge	156:ff21514d8981	3315	/**
AnnaBridge	156:ff21514d8981	3316	* @}
AnnaBridge	156:ff21514d8981	3317	*/
AnnaBridge	156:ff21514d8981	3318
AnnaBridge	156:ff21514d8981	3319	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	3320	* @brief Enable or disable the High Speed APB (APB1) peripheral clock.
AnnaBridge	156:ff21514d8981	3321	* @{
AnnaBridge	156:ff21514d8981	3322	*/
AnnaBridge	156:ff21514d8981	3323	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3324	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3325	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	156:ff21514d8981	3326	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3327	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	156:ff21514d8981	3328	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3329	} while(0U)
AnnaBridge	156:ff21514d8981	3330	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3331	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3332	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
AnnaBridge	156:ff21514d8981	3333	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3334	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
AnnaBridge	156:ff21514d8981	3335	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3336	} while(0U)
AnnaBridge	156:ff21514d8981	3337	#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3338	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3339	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
AnnaBridge	156:ff21514d8981	3340	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3341	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
AnnaBridge	156:ff21514d8981	3342	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3343	} while(0U)
AnnaBridge	156:ff21514d8981	3344	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3345	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3346	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
AnnaBridge	156:ff21514d8981	3347	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3348	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
AnnaBridge	156:ff21514d8981	3349	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3350	} while(0U)
AnnaBridge	156:ff21514d8981	3351	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3352	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3353	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	156:ff21514d8981	3354	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3355	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	156:ff21514d8981	3356	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3357	} while(0U)
AnnaBridge	156:ff21514d8981	3358
AnnaBridge	156:ff21514d8981	3359	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
AnnaBridge	156:ff21514d8981	3360	#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
AnnaBridge	156:ff21514d8981	3361	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
AnnaBridge	156:ff21514d8981	3362	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
AnnaBridge	156:ff21514d8981	3363	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
AnnaBridge	156:ff21514d8981	3364	/**
AnnaBridge	156:ff21514d8981	3365	* @}
AnnaBridge	156:ff21514d8981	3366	*/
AnnaBridge	156:ff21514d8981	3367
AnnaBridge	156:ff21514d8981	3368	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	3369	* @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge	156:ff21514d8981	3370	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	3371	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	3372	* using it.
AnnaBridge	156:ff21514d8981	3373	* @{
AnnaBridge	156:ff21514d8981	3374	*/
AnnaBridge	156:ff21514d8981	3375	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
AnnaBridge	156:ff21514d8981	3376	#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
AnnaBridge	156:ff21514d8981	3377	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
AnnaBridge	156:ff21514d8981	3378	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
AnnaBridge	156:ff21514d8981	3379	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
AnnaBridge	156:ff21514d8981	3380
AnnaBridge	156:ff21514d8981	3381	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
AnnaBridge	156:ff21514d8981	3382	#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
AnnaBridge	156:ff21514d8981	3383	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
AnnaBridge	156:ff21514d8981	3384	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
AnnaBridge	156:ff21514d8981	3385	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
AnnaBridge	156:ff21514d8981	3386	/**
AnnaBridge	156:ff21514d8981	3387	* @}
AnnaBridge	156:ff21514d8981	3388	*/
AnnaBridge	156:ff21514d8981	3389
AnnaBridge	156:ff21514d8981	3390	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	3391	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	156:ff21514d8981	3392	* @{
AnnaBridge	156:ff21514d8981	3393	*/
AnnaBridge	156:ff21514d8981	3394	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3395	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3396	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
AnnaBridge	156:ff21514d8981	3397	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3398	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
AnnaBridge	156:ff21514d8981	3399	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3400	} while(0U)
AnnaBridge	156:ff21514d8981	3401	#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3402	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3403	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
AnnaBridge	156:ff21514d8981	3404	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3405	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
AnnaBridge	156:ff21514d8981	3406	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3407	} while(0U)
AnnaBridge	156:ff21514d8981	3408	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
AnnaBridge	156:ff21514d8981	3409	#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
AnnaBridge	156:ff21514d8981	3410	/**
AnnaBridge	156:ff21514d8981	3411	* @}
AnnaBridge	156:ff21514d8981	3412	*/
AnnaBridge	156:ff21514d8981	3413
AnnaBridge	156:ff21514d8981	3414	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	3415	* @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge	156:ff21514d8981	3416	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	3417	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	3418	* using it.
AnnaBridge	156:ff21514d8981	3419	* @{
AnnaBridge	156:ff21514d8981	3420	*/
AnnaBridge	156:ff21514d8981	3421	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
AnnaBridge	156:ff21514d8981	3422	#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
AnnaBridge	156:ff21514d8981	3423
AnnaBridge	156:ff21514d8981	3424	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
AnnaBridge	156:ff21514d8981	3425	#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
AnnaBridge	156:ff21514d8981	3426	/**
AnnaBridge	156:ff21514d8981	3427	* @}
AnnaBridge	156:ff21514d8981	3428	*/
AnnaBridge	156:ff21514d8981	3429
AnnaBridge	156:ff21514d8981	3430	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
AnnaBridge	156:ff21514d8981	3431	* @brief Force or release AHB1 peripheral reset.
AnnaBridge	156:ff21514d8981	3432	* @{
AnnaBridge	156:ff21514d8981	3433	*/
AnnaBridge	156:ff21514d8981	3434	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
AnnaBridge	156:ff21514d8981	3435	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_RNGRST))
AnnaBridge	156:ff21514d8981	3436	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
AnnaBridge	156:ff21514d8981	3437	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))
AnnaBridge	156:ff21514d8981	3438	/**
AnnaBridge	156:ff21514d8981	3439	* @}
AnnaBridge	156:ff21514d8981	3440	*/
AnnaBridge	156:ff21514d8981	3441
AnnaBridge	156:ff21514d8981	3442	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
AnnaBridge	156:ff21514d8981	3443	* @brief Force or release AHB2 peripheral reset.
AnnaBridge	156:ff21514d8981	3444	* @{
AnnaBridge	156:ff21514d8981	3445	*/
AnnaBridge	156:ff21514d8981	3446	#define __HAL_RCC_AHB2_FORCE_RESET()
AnnaBridge	156:ff21514d8981	3447	#define __HAL_RCC_AHB2_RELEASE_RESET()
AnnaBridge	156:ff21514d8981	3448	/**
AnnaBridge	156:ff21514d8981	3449	* @}
AnnaBridge	156:ff21514d8981	3450	*/
AnnaBridge	156:ff21514d8981	3451
AnnaBridge	156:ff21514d8981	3452	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
AnnaBridge	156:ff21514d8981	3453	* @brief Force or release AHB3 peripheral reset.
AnnaBridge	156:ff21514d8981	3454	* @{
AnnaBridge	156:ff21514d8981	3455	*/
AnnaBridge	156:ff21514d8981	3456	#define __HAL_RCC_AHB3_FORCE_RESET()
AnnaBridge	156:ff21514d8981	3457	#define __HAL_RCC_AHB3_RELEASE_RESET()
AnnaBridge	156:ff21514d8981	3458	/**
AnnaBridge	156:ff21514d8981	3459	* @}
AnnaBridge	156:ff21514d8981	3460	*/
AnnaBridge	156:ff21514d8981	3461
AnnaBridge	156:ff21514d8981	3462	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
AnnaBridge	156:ff21514d8981	3463	* @brief Force or release APB1 peripheral reset.
AnnaBridge	156:ff21514d8981	3464	* @{
AnnaBridge	156:ff21514d8981	3465	*/
AnnaBridge	156:ff21514d8981	3466	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
AnnaBridge	156:ff21514d8981	3467	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
AnnaBridge	156:ff21514d8981	3468	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
AnnaBridge	156:ff21514d8981	3469	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
AnnaBridge	156:ff21514d8981	3470
AnnaBridge	156:ff21514d8981	3471	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
AnnaBridge	156:ff21514d8981	3472	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
AnnaBridge	156:ff21514d8981	3473	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
AnnaBridge	156:ff21514d8981	3474	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
AnnaBridge	156:ff21514d8981	3475	/**
AnnaBridge	156:ff21514d8981	3476	* @}
AnnaBridge	156:ff21514d8981	3477	*/
AnnaBridge	156:ff21514d8981	3478
AnnaBridge	156:ff21514d8981	3479	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
AnnaBridge	156:ff21514d8981	3480	* @brief Force or release APB2 peripheral reset.
AnnaBridge	156:ff21514d8981	3481	* @{
AnnaBridge	156:ff21514d8981	3482	*/
AnnaBridge	156:ff21514d8981	3483	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
AnnaBridge	156:ff21514d8981	3484	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
AnnaBridge	156:ff21514d8981	3485	/**
AnnaBridge	156:ff21514d8981	3486	* @}
AnnaBridge	156:ff21514d8981	3487	*/
AnnaBridge	156:ff21514d8981	3488
AnnaBridge	156:ff21514d8981	3489	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	3490	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	3491	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	3492	* power consumption.
AnnaBridge	156:ff21514d8981	3493	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	3494	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	3495	* @{
AnnaBridge	156:ff21514d8981	3496	*/
AnnaBridge	156:ff21514d8981	3497	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_RNGLPEN))
AnnaBridge	156:ff21514d8981	3498	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	156:ff21514d8981	3499	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	156:ff21514d8981	3500	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	156:ff21514d8981	3501
AnnaBridge	156:ff21514d8981	3502	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
AnnaBridge	156:ff21514d8981	3503	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	156:ff21514d8981	3504	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	156:ff21514d8981	3505	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	156:ff21514d8981	3506	/**
AnnaBridge	156:ff21514d8981	3507	* @}
AnnaBridge	156:ff21514d8981	3508	*/
AnnaBridge	156:ff21514d8981	3509
AnnaBridge	156:ff21514d8981	3510	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	3511	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	3512	* @{
AnnaBridge	156:ff21514d8981	3513	*/
AnnaBridge	156:ff21514d8981	3514	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	156:ff21514d8981	3515	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_LPTIM1LPEN))
AnnaBridge	156:ff21514d8981	3516	#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_RTCAPBLPEN))
AnnaBridge	156:ff21514d8981	3517	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
AnnaBridge	156:ff21514d8981	3518	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
AnnaBridge	156:ff21514d8981	3519
AnnaBridge	156:ff21514d8981	3520	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	156:ff21514d8981	3521	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
AnnaBridge	156:ff21514d8981	3522	#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
AnnaBridge	156:ff21514d8981	3523	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
AnnaBridge	156:ff21514d8981	3524	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
AnnaBridge	156:ff21514d8981	3525	/**
AnnaBridge	156:ff21514d8981	3526	* @}
AnnaBridge	156:ff21514d8981	3527	*/
AnnaBridge	156:ff21514d8981	3528
AnnaBridge	156:ff21514d8981	3529	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	3530	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	3531	* @{
AnnaBridge	156:ff21514d8981	3532	*/
AnnaBridge	156:ff21514d8981	3533	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
AnnaBridge	156:ff21514d8981	3534	#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_EXTITLPEN))
AnnaBridge	156:ff21514d8981	3535	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
AnnaBridge	156:ff21514d8981	3536	#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
AnnaBridge	156:ff21514d8981	3537	/**
AnnaBridge	156:ff21514d8981	3538	* @}
AnnaBridge	156:ff21514d8981	3539	*/
AnnaBridge	156:ff21514d8981	3540
AnnaBridge	156:ff21514d8981	3541	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	156:ff21514d8981	3542	/----------------------------------------------------------------------------/
AnnaBridge	156:ff21514d8981	3543
AnnaBridge	156:ff21514d8981	3544	/-------------------------------- STM32F411xx -------------------------------/
AnnaBridge	156:ff21514d8981	3545	#if defined(STM32F411xE)
AnnaBridge	156:ff21514d8981	3546	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	3547	* @brief Enables or disables the AHB1 peripheral clock.
AnnaBridge	156:ff21514d8981	3548	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	3549	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	3550	* using it.
AnnaBridge	156:ff21514d8981	3551	* @{
AnnaBridge	156:ff21514d8981	3552	*/
AnnaBridge	156:ff21514d8981	3553	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3554	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3555	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
AnnaBridge	156:ff21514d8981	3556	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3557	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
AnnaBridge	156:ff21514d8981	3558	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3559	} while(0U)
AnnaBridge	156:ff21514d8981	3560	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3561	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3562	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	156:ff21514d8981	3563	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3564	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	156:ff21514d8981	3565	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3566	} while(0U)
AnnaBridge	156:ff21514d8981	3567	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3568	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3569	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	156:ff21514d8981	3570	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3571	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	156:ff21514d8981	3572	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3573	} while(0U)
AnnaBridge	156:ff21514d8981	3574	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3575	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3576	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	156:ff21514d8981	3577	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3578	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	156:ff21514d8981	3579	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3580	} while(0U)
AnnaBridge	156:ff21514d8981	3581	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
AnnaBridge	156:ff21514d8981	3582	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
AnnaBridge	156:ff21514d8981	3583	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
AnnaBridge	156:ff21514d8981	3584	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
AnnaBridge	156:ff21514d8981	3585	/**
AnnaBridge	156:ff21514d8981	3586	* @}
AnnaBridge	156:ff21514d8981	3587	*/
AnnaBridge	156:ff21514d8981	3588
AnnaBridge	156:ff21514d8981	3589	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	3590	* @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge	156:ff21514d8981	3591	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	3592	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	3593	* using it.
AnnaBridge	156:ff21514d8981	3594	* @{
AnnaBridge	156:ff21514d8981	3595	*/
AnnaBridge	156:ff21514d8981	3596	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
AnnaBridge	156:ff21514d8981	3597	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
AnnaBridge	156:ff21514d8981	3598	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
AnnaBridge	156:ff21514d8981	3599	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
AnnaBridge	156:ff21514d8981	3600
AnnaBridge	156:ff21514d8981	3601	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
AnnaBridge	156:ff21514d8981	3602	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
AnnaBridge	156:ff21514d8981	3603	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
AnnaBridge	156:ff21514d8981	3604	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
AnnaBridge	156:ff21514d8981	3605	/**
AnnaBridge	156:ff21514d8981	3606	* @}
AnnaBridge	156:ff21514d8981	3607	*/
AnnaBridge	156:ff21514d8981	3608
AnnaBridge	156:ff21514d8981	3609	/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	3610	* @brief Enable or disable the AHB2 peripheral clock.
AnnaBridge	156:ff21514d8981	3611	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	3612	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	3613	* using it.
AnnaBridge	156:ff21514d8981	3614	* @{
AnnaBridge	156:ff21514d8981	3615	*/
AnnaBridge	156:ff21514d8981	3616	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
AnnaBridge	156:ff21514d8981	3617	__HAL_RCC_SYSCFG_CLK_ENABLE();\
AnnaBridge	156:ff21514d8981	3618	}while(0U)
AnnaBridge	156:ff21514d8981	3619
AnnaBridge	156:ff21514d8981	3620	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
AnnaBridge	156:ff21514d8981	3621	/**
AnnaBridge	156:ff21514d8981	3622	* @}
AnnaBridge	156:ff21514d8981	3623	*/
AnnaBridge	156:ff21514d8981	3624
AnnaBridge	156:ff21514d8981	3625	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	3626	* @brief Get the enable or disable status of the AHB2 peripheral clock.
AnnaBridge	156:ff21514d8981	3627	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	3628	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	3629	* using it.
AnnaBridge	156:ff21514d8981	3630	* @{
AnnaBridge	156:ff21514d8981	3631	*/
AnnaBridge	156:ff21514d8981	3632	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
AnnaBridge	156:ff21514d8981	3633	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
AnnaBridge	156:ff21514d8981	3634	/**
AnnaBridge	156:ff21514d8981	3635	* @}
AnnaBridge	156:ff21514d8981	3636	*/
AnnaBridge	156:ff21514d8981	3637
AnnaBridge	156:ff21514d8981	3638	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	3639	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	156:ff21514d8981	3640	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	3641	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	3642	* using it.
AnnaBridge	156:ff21514d8981	3643	* @{
AnnaBridge	156:ff21514d8981	3644	*/
AnnaBridge	156:ff21514d8981	3645	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3646	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3647	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	156:ff21514d8981	3648	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3649	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	156:ff21514d8981	3650	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3651	} while(0U)
AnnaBridge	156:ff21514d8981	3652	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3653	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3654	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	156:ff21514d8981	3655	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3656	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	156:ff21514d8981	3657	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3658	} while(0U)
AnnaBridge	156:ff21514d8981	3659	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3660	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3661	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	156:ff21514d8981	3662	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3663	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	156:ff21514d8981	3664	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3665	} while(0U)
AnnaBridge	156:ff21514d8981	3666	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3667	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3668	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	156:ff21514d8981	3669	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3670	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	156:ff21514d8981	3671	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3672	} while(0U)
AnnaBridge	156:ff21514d8981	3673	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3674	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3675	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	156:ff21514d8981	3676	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3677	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	156:ff21514d8981	3678	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3679	} while(0U)
AnnaBridge	156:ff21514d8981	3680	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
AnnaBridge	156:ff21514d8981	3681	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge	156:ff21514d8981	3682	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
AnnaBridge	156:ff21514d8981	3683	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge	156:ff21514d8981	3684	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
AnnaBridge	156:ff21514d8981	3685	/**
AnnaBridge	156:ff21514d8981	3686	* @}
AnnaBridge	156:ff21514d8981	3687	*/
AnnaBridge	156:ff21514d8981	3688
AnnaBridge	156:ff21514d8981	3689	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	3690	* @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge	156:ff21514d8981	3691	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	3692	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	3693	* using it.
AnnaBridge	156:ff21514d8981	3694	* @{
AnnaBridge	156:ff21514d8981	3695	*/
AnnaBridge	156:ff21514d8981	3696	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
AnnaBridge	156:ff21514d8981	3697	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge	156:ff21514d8981	3698	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
AnnaBridge	156:ff21514d8981	3699	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge	156:ff21514d8981	3700	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
AnnaBridge	156:ff21514d8981	3701
AnnaBridge	156:ff21514d8981	3702	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
AnnaBridge	156:ff21514d8981	3703	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge	156:ff21514d8981	3704	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
AnnaBridge	156:ff21514d8981	3705	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge	156:ff21514d8981	3706	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
AnnaBridge	156:ff21514d8981	3707	/**
AnnaBridge	156:ff21514d8981	3708	* @}
AnnaBridge	156:ff21514d8981	3709	*/
AnnaBridge	156:ff21514d8981	3710
AnnaBridge	156:ff21514d8981	3711	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	3712	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	156:ff21514d8981	3713	* @{
AnnaBridge	156:ff21514d8981	3714	*/
AnnaBridge	156:ff21514d8981	3715	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3716	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3717	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
AnnaBridge	156:ff21514d8981	3718	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3719	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
AnnaBridge	156:ff21514d8981	3720	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3721	} while(0U)
AnnaBridge	156:ff21514d8981	3722	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3723	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3724	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	156:ff21514d8981	3725	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3726	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	156:ff21514d8981	3727	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3728	} while(0U)
AnnaBridge	156:ff21514d8981	3729	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3730	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3731	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	156:ff21514d8981	3732	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3733	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	156:ff21514d8981	3734	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3735	} while(0U)
AnnaBridge	156:ff21514d8981	3736	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3737	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3738	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	156:ff21514d8981	3739	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3740	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	156:ff21514d8981	3741	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3742	} while(0U)
AnnaBridge	156:ff21514d8981	3743	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
AnnaBridge	156:ff21514d8981	3744	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
AnnaBridge	156:ff21514d8981	3745	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
AnnaBridge	156:ff21514d8981	3746	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
AnnaBridge	156:ff21514d8981	3747	/**
AnnaBridge	156:ff21514d8981	3748	* @}
AnnaBridge	156:ff21514d8981	3749	*/
AnnaBridge	156:ff21514d8981	3750
AnnaBridge	156:ff21514d8981	3751	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	3752	* @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge	156:ff21514d8981	3753	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	3754	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	3755	* using it.
AnnaBridge	156:ff21514d8981	3756	* @{
AnnaBridge	156:ff21514d8981	3757	*/
AnnaBridge	156:ff21514d8981	3758	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
AnnaBridge	156:ff21514d8981	3759	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
AnnaBridge	156:ff21514d8981	3760	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
AnnaBridge	156:ff21514d8981	3761	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
AnnaBridge	156:ff21514d8981	3762
AnnaBridge	156:ff21514d8981	3763	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
AnnaBridge	156:ff21514d8981	3764	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
AnnaBridge	156:ff21514d8981	3765	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
AnnaBridge	156:ff21514d8981	3766	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
AnnaBridge	156:ff21514d8981	3767	/**
AnnaBridge	156:ff21514d8981	3768	* @}
AnnaBridge	156:ff21514d8981	3769	*/
AnnaBridge	156:ff21514d8981	3770
AnnaBridge	156:ff21514d8981	3771	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
AnnaBridge	156:ff21514d8981	3772	* @brief Force or release AHB1 peripheral reset.
AnnaBridge	156:ff21514d8981	3773	* @{
AnnaBridge	156:ff21514d8981	3774	*/
AnnaBridge	156:ff21514d8981	3775	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
AnnaBridge	156:ff21514d8981	3776	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
AnnaBridge	156:ff21514d8981	3777	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
AnnaBridge	156:ff21514d8981	3778
AnnaBridge	156:ff21514d8981	3779	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
AnnaBridge	156:ff21514d8981	3780	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
AnnaBridge	156:ff21514d8981	3781	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
AnnaBridge	156:ff21514d8981	3782	/**
AnnaBridge	156:ff21514d8981	3783	* @}
AnnaBridge	156:ff21514d8981	3784	*/
AnnaBridge	156:ff21514d8981	3785
AnnaBridge	156:ff21514d8981	3786	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
AnnaBridge	156:ff21514d8981	3787	* @brief Force or release AHB2 peripheral reset.
AnnaBridge	156:ff21514d8981	3788	* @{
AnnaBridge	156:ff21514d8981	3789	*/
AnnaBridge	156:ff21514d8981	3790	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
AnnaBridge	156:ff21514d8981	3791	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	156:ff21514d8981	3792
AnnaBridge	156:ff21514d8981	3793	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
AnnaBridge	156:ff21514d8981	3794	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	156:ff21514d8981	3795	/**
AnnaBridge	156:ff21514d8981	3796	* @}
AnnaBridge	156:ff21514d8981	3797	*/
AnnaBridge	156:ff21514d8981	3798
AnnaBridge	156:ff21514d8981	3799	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
AnnaBridge	156:ff21514d8981	3800	* @brief Force or release AHB3 peripheral reset.
AnnaBridge	156:ff21514d8981	3801	* @{
AnnaBridge	156:ff21514d8981	3802	*/
AnnaBridge	156:ff21514d8981	3803	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
AnnaBridge	156:ff21514d8981	3804	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
AnnaBridge	156:ff21514d8981	3805	/**
AnnaBridge	156:ff21514d8981	3806	* @}
AnnaBridge	156:ff21514d8981	3807	*/
AnnaBridge	156:ff21514d8981	3808
AnnaBridge	156:ff21514d8981	3809	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
AnnaBridge	156:ff21514d8981	3810	* @brief Force or release APB1 peripheral reset.
AnnaBridge	156:ff21514d8981	3811	* @{
AnnaBridge	156:ff21514d8981	3812	*/
AnnaBridge	156:ff21514d8981	3813	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
AnnaBridge	156:ff21514d8981	3814	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
AnnaBridge	156:ff21514d8981	3815	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
AnnaBridge	156:ff21514d8981	3816	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
AnnaBridge	156:ff21514d8981	3817	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
AnnaBridge	156:ff21514d8981	3818
AnnaBridge	156:ff21514d8981	3819	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
AnnaBridge	156:ff21514d8981	3820	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge	156:ff21514d8981	3821	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge	156:ff21514d8981	3822	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge	156:ff21514d8981	3823	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
AnnaBridge	156:ff21514d8981	3824	/**
AnnaBridge	156:ff21514d8981	3825	* @}
AnnaBridge	156:ff21514d8981	3826	*/
AnnaBridge	156:ff21514d8981	3827
AnnaBridge	156:ff21514d8981	3828	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
AnnaBridge	156:ff21514d8981	3829	* @brief Force or release APB2 peripheral reset.
AnnaBridge	156:ff21514d8981	3830	* @{
AnnaBridge	156:ff21514d8981	3831	*/
AnnaBridge	156:ff21514d8981	3832	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
AnnaBridge	156:ff21514d8981	3833	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
AnnaBridge	156:ff21514d8981	3834	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
AnnaBridge	156:ff21514d8981	3835	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
AnnaBridge	156:ff21514d8981	3836
AnnaBridge	156:ff21514d8981	3837	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
AnnaBridge	156:ff21514d8981	3838	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
AnnaBridge	156:ff21514d8981	3839	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
AnnaBridge	156:ff21514d8981	3840	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
AnnaBridge	156:ff21514d8981	3841	/**
AnnaBridge	156:ff21514d8981	3842	* @}
AnnaBridge	156:ff21514d8981	3843	*/
AnnaBridge	156:ff21514d8981	3844
AnnaBridge	156:ff21514d8981	3845	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	3846	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	3847	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	3848	* power consumption.
AnnaBridge	156:ff21514d8981	3849	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	3850	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	3851	* @{
AnnaBridge	156:ff21514d8981	3852	*/
AnnaBridge	156:ff21514d8981	3853	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	156:ff21514d8981	3854	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	156:ff21514d8981	3855	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	156:ff21514d8981	3856	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	156:ff21514d8981	3857	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	156:ff21514d8981	3858
AnnaBridge	156:ff21514d8981	3859	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	156:ff21514d8981	3860	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	156:ff21514d8981	3861	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	156:ff21514d8981	3862	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	156:ff21514d8981	3863	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	156:ff21514d8981	3864	/**
AnnaBridge	156:ff21514d8981	3865	* @}
AnnaBridge	156:ff21514d8981	3866	*/
AnnaBridge	156:ff21514d8981	3867
AnnaBridge	156:ff21514d8981	3868	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	3869	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	3870	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	3871	* power consumption.
AnnaBridge	156:ff21514d8981	3872	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	3873	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	3874	* @{
AnnaBridge	156:ff21514d8981	3875	*/
AnnaBridge	156:ff21514d8981	3876	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	156:ff21514d8981	3877	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	156:ff21514d8981	3878	/**
AnnaBridge	156:ff21514d8981	3879	* @}
AnnaBridge	156:ff21514d8981	3880	*/
AnnaBridge	156:ff21514d8981	3881
AnnaBridge	156:ff21514d8981	3882	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	3883	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	3884	* @{
AnnaBridge	156:ff21514d8981	3885	*/
AnnaBridge	156:ff21514d8981	3886	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	156:ff21514d8981	3887	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	156:ff21514d8981	3888	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	156:ff21514d8981	3889	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	156:ff21514d8981	3890	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	156:ff21514d8981	3891
AnnaBridge	156:ff21514d8981	3892	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	156:ff21514d8981	3893	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	156:ff21514d8981	3894	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	156:ff21514d8981	3895	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	156:ff21514d8981	3896	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	156:ff21514d8981	3897	/**
AnnaBridge	156:ff21514d8981	3898	* @}
AnnaBridge	156:ff21514d8981	3899	*/
AnnaBridge	156:ff21514d8981	3900
AnnaBridge	156:ff21514d8981	3901	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	3902	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	3903	* @{
AnnaBridge	156:ff21514d8981	3904	*/
AnnaBridge	156:ff21514d8981	3905	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
AnnaBridge	156:ff21514d8981	3906	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	156:ff21514d8981	3907	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	156:ff21514d8981	3908	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	156:ff21514d8981	3909
AnnaBridge	156:ff21514d8981	3910	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	156:ff21514d8981	3911	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	156:ff21514d8981	3912	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	156:ff21514d8981	3913	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
AnnaBridge	156:ff21514d8981	3914	/**
AnnaBridge	156:ff21514d8981	3915	* @}
AnnaBridge	156:ff21514d8981	3916	*/
AnnaBridge	156:ff21514d8981	3917	#endif /* STM32F411xE */
AnnaBridge	156:ff21514d8981	3918	/----------------------------------------------------------------------------/
AnnaBridge	156:ff21514d8981	3919
AnnaBridge	156:ff21514d8981	3920	/---------------------------------- STM32F446xx -----------------------------/
AnnaBridge	156:ff21514d8981	3921	#if defined(STM32F446xx)
AnnaBridge	156:ff21514d8981	3922	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	3923	* @brief Enables or disables the AHB1 peripheral clock.
AnnaBridge	156:ff21514d8981	3924	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	3925	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	3926	* using it.
AnnaBridge	156:ff21514d8981	3927	* @{
AnnaBridge	156:ff21514d8981	3928	*/
AnnaBridge	156:ff21514d8981	3929	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3930	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3931	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
AnnaBridge	156:ff21514d8981	3932	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3933	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
AnnaBridge	156:ff21514d8981	3934	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3935	} while(0U)
AnnaBridge	156:ff21514d8981	3936	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3937	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3938	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
AnnaBridge	156:ff21514d8981	3939	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3940	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
AnnaBridge	156:ff21514d8981	3941	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3942	} while(0U)
AnnaBridge	156:ff21514d8981	3943	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3944	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3945	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	156:ff21514d8981	3946	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3947	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	156:ff21514d8981	3948	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3949	} while(0U)
AnnaBridge	156:ff21514d8981	3950	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3951	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3952	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	156:ff21514d8981	3953	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3954	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	156:ff21514d8981	3955	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3956	} while(0U)
AnnaBridge	156:ff21514d8981	3957	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3958	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3959	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	156:ff21514d8981	3960	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3961	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	156:ff21514d8981	3962	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3963	} while(0U)
AnnaBridge	156:ff21514d8981	3964	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3965	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3966	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge	156:ff21514d8981	3967	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3968	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge	156:ff21514d8981	3969	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3970	} while(0U)
AnnaBridge	156:ff21514d8981	3971	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3972	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3973	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge	156:ff21514d8981	3974	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3975	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge	156:ff21514d8981	3976	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3977	} while(0U)
AnnaBridge	156:ff21514d8981	3978	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3979	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3980	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
AnnaBridge	156:ff21514d8981	3981	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3982	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
AnnaBridge	156:ff21514d8981	3983	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3984	} while(0U)
AnnaBridge	156:ff21514d8981	3985	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	3986	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	3987	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
AnnaBridge	156:ff21514d8981	3988	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	3989	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
AnnaBridge	156:ff21514d8981	3990	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	3991	} while(0U)
AnnaBridge	156:ff21514d8981	3992	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
AnnaBridge	156:ff21514d8981	3993	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
AnnaBridge	156:ff21514d8981	3994	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
AnnaBridge	156:ff21514d8981	3995	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
AnnaBridge	156:ff21514d8981	3996	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
AnnaBridge	156:ff21514d8981	3997	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
AnnaBridge	156:ff21514d8981	3998	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
AnnaBridge	156:ff21514d8981	3999	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
AnnaBridge	156:ff21514d8981	4000	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
AnnaBridge	156:ff21514d8981	4001	/**
AnnaBridge	156:ff21514d8981	4002	* @}
AnnaBridge	156:ff21514d8981	4003	*/
AnnaBridge	156:ff21514d8981	4004
AnnaBridge	156:ff21514d8981	4005	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	4006	* @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge	156:ff21514d8981	4007	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	4008	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	4009	* using it.
AnnaBridge	156:ff21514d8981	4010	* @{
AnnaBridge	156:ff21514d8981	4011	*/
AnnaBridge	156:ff21514d8981	4012	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
AnnaBridge	156:ff21514d8981	4013	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
AnnaBridge	156:ff21514d8981	4014	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
AnnaBridge	156:ff21514d8981	4015	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
AnnaBridge	156:ff21514d8981	4016	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
AnnaBridge	156:ff21514d8981	4017	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
AnnaBridge	156:ff21514d8981	4018	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
AnnaBridge	156:ff21514d8981	4019	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET)
AnnaBridge	156:ff21514d8981	4020	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
AnnaBridge	156:ff21514d8981	4021
AnnaBridge	156:ff21514d8981	4022	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
AnnaBridge	156:ff21514d8981	4023	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
AnnaBridge	156:ff21514d8981	4024	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
AnnaBridge	156:ff21514d8981	4025	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
AnnaBridge	156:ff21514d8981	4026	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
AnnaBridge	156:ff21514d8981	4027	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
AnnaBridge	156:ff21514d8981	4028	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
AnnaBridge	156:ff21514d8981	4029	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
AnnaBridge	156:ff21514d8981	4030	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
AnnaBridge	156:ff21514d8981	4031	/**
AnnaBridge	156:ff21514d8981	4032	* @}
AnnaBridge	156:ff21514d8981	4033	*/
AnnaBridge	156:ff21514d8981	4034
AnnaBridge	156:ff21514d8981	4035	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	4036	* @brief Enable or disable the AHB2 peripheral clock.
AnnaBridge	156:ff21514d8981	4037	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	4038	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	4039	* using it.
AnnaBridge	156:ff21514d8981	4040	* @{
AnnaBridge	156:ff21514d8981	4041	*/
AnnaBridge	156:ff21514d8981	4042	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4043	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4044	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
AnnaBridge	156:ff21514d8981	4045	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4046	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
AnnaBridge	156:ff21514d8981	4047	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4048	} while(0U)
AnnaBridge	156:ff21514d8981	4049	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
AnnaBridge	156:ff21514d8981	4050	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
AnnaBridge	156:ff21514d8981	4051	__HAL_RCC_SYSCFG_CLK_ENABLE();\
AnnaBridge	156:ff21514d8981	4052	}while(0U)
AnnaBridge	156:ff21514d8981	4053
AnnaBridge	156:ff21514d8981	4054	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
AnnaBridge	156:ff21514d8981	4055
AnnaBridge	156:ff21514d8981	4056	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4057	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4058	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge	156:ff21514d8981	4059	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4060	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge	156:ff21514d8981	4061	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4062	} while(0U)
AnnaBridge	156:ff21514d8981	4063	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
AnnaBridge	156:ff21514d8981	4064	/**
AnnaBridge	156:ff21514d8981	4065	* @}
AnnaBridge	156:ff21514d8981	4066	*/
AnnaBridge	156:ff21514d8981	4067
AnnaBridge	156:ff21514d8981	4068	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	4069	* @brief Get the enable or disable status of the AHB2 peripheral clock.
AnnaBridge	156:ff21514d8981	4070	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	4071	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	4072	* using it.
AnnaBridge	156:ff21514d8981	4073	* @{
AnnaBridge	156:ff21514d8981	4074	*/
AnnaBridge	156:ff21514d8981	4075	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
AnnaBridge	156:ff21514d8981	4076	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
AnnaBridge	156:ff21514d8981	4077
AnnaBridge	156:ff21514d8981	4078	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
AnnaBridge	156:ff21514d8981	4079	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
AnnaBridge	156:ff21514d8981	4080
AnnaBridge	156:ff21514d8981	4081	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
AnnaBridge	156:ff21514d8981	4082	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
AnnaBridge	156:ff21514d8981	4083	/**
AnnaBridge	156:ff21514d8981	4084	* @}
AnnaBridge	156:ff21514d8981	4085	*/
AnnaBridge	156:ff21514d8981	4086
AnnaBridge	156:ff21514d8981	4087	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	4088	* @brief Enables or disables the AHB3 peripheral clock.
AnnaBridge	156:ff21514d8981	4089	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	4090	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	4091	* using it.
AnnaBridge	156:ff21514d8981	4092	* @{
AnnaBridge	156:ff21514d8981	4093	*/
AnnaBridge	156:ff21514d8981	4094	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4095	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4096	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
AnnaBridge	156:ff21514d8981	4097	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4098	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
AnnaBridge	156:ff21514d8981	4099	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4100	} while(0U)
AnnaBridge	156:ff21514d8981	4101	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4102	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4103	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
AnnaBridge	156:ff21514d8981	4104	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4105	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
AnnaBridge	156:ff21514d8981	4106	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4107	} while(0U)
AnnaBridge	156:ff21514d8981	4108
AnnaBridge	156:ff21514d8981	4109	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
AnnaBridge	156:ff21514d8981	4110	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
AnnaBridge	156:ff21514d8981	4111	/**
AnnaBridge	156:ff21514d8981	4112	* @}
AnnaBridge	156:ff21514d8981	4113	*/
AnnaBridge	156:ff21514d8981	4114
AnnaBridge	156:ff21514d8981	4115	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	4116	* @brief Get the enable or disable status of the AHB3 peripheral clock.
AnnaBridge	156:ff21514d8981	4117	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	4118	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	4119	* using it.
AnnaBridge	156:ff21514d8981	4120	* @{
AnnaBridge	156:ff21514d8981	4121	*/
AnnaBridge	156:ff21514d8981	4122	#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
AnnaBridge	156:ff21514d8981	4123	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
AnnaBridge	156:ff21514d8981	4124
AnnaBridge	156:ff21514d8981	4125	#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
AnnaBridge	156:ff21514d8981	4126	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
AnnaBridge	156:ff21514d8981	4127	/**
AnnaBridge	156:ff21514d8981	4128	* @}
AnnaBridge	156:ff21514d8981	4129	*/
AnnaBridge	156:ff21514d8981	4130
AnnaBridge	156:ff21514d8981	4131	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	4132	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	156:ff21514d8981	4133	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	4134	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	4135	* using it.
AnnaBridge	156:ff21514d8981	4136	* @{
AnnaBridge	156:ff21514d8981	4137	*/
AnnaBridge	156:ff21514d8981	4138	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4139	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4140	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	156:ff21514d8981	4141	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4142	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	156:ff21514d8981	4143	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4144	} while(0U)
AnnaBridge	156:ff21514d8981	4145	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4146	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4147	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	156:ff21514d8981	4148	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4149	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	156:ff21514d8981	4150	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4151	} while(0U)
AnnaBridge	156:ff21514d8981	4152	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4153	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4154	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	156:ff21514d8981	4155	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4156	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	156:ff21514d8981	4157	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4158	} while(0U)
AnnaBridge	156:ff21514d8981	4159	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4160	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4161	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	156:ff21514d8981	4162	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4163	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	156:ff21514d8981	4164	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4165	} while(0U)
AnnaBridge	156:ff21514d8981	4166	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4167	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4168	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	156:ff21514d8981	4169	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4170	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	156:ff21514d8981	4171	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4172	} while(0U)
AnnaBridge	156:ff21514d8981	4173	#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4174	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4175	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
AnnaBridge	156:ff21514d8981	4176	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4177	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
AnnaBridge	156:ff21514d8981	4178	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4179	} while(0U)
AnnaBridge	156:ff21514d8981	4180	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4181	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4182	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	156:ff21514d8981	4183	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4184	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	156:ff21514d8981	4185	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4186	} while(0U)
AnnaBridge	156:ff21514d8981	4187	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4188	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4189	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	156:ff21514d8981	4190	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4191	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	156:ff21514d8981	4192	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4193	} while(0U)
AnnaBridge	156:ff21514d8981	4194	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4195	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4196	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	156:ff21514d8981	4197	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4198	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	156:ff21514d8981	4199	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4200	} while(0U)
AnnaBridge	156:ff21514d8981	4201	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4202	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4203	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
AnnaBridge	156:ff21514d8981	4204	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4205	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
AnnaBridge	156:ff21514d8981	4206	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4207	} while(0U)
AnnaBridge	156:ff21514d8981	4208	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4209	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4210	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	156:ff21514d8981	4211	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4212	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	156:ff21514d8981	4213	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4214	} while(0U)
AnnaBridge	156:ff21514d8981	4215	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4216	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4217	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	156:ff21514d8981	4218	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4219	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	156:ff21514d8981	4220	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4221	} while(0U)
AnnaBridge	156:ff21514d8981	4222	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4223	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4224	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
AnnaBridge	156:ff21514d8981	4225	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4226	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
AnnaBridge	156:ff21514d8981	4227	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4228	} while(0U)
AnnaBridge	156:ff21514d8981	4229	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4230	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4231	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	156:ff21514d8981	4232	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4233	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	156:ff21514d8981	4234	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4235	} while(0U)
AnnaBridge	156:ff21514d8981	4236	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4237	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4238	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	156:ff21514d8981	4239	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4240	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	156:ff21514d8981	4241	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4242	} while(0U)
AnnaBridge	156:ff21514d8981	4243	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4244	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4245	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	156:ff21514d8981	4246	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4247	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	156:ff21514d8981	4248	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4249	} while(0U)
AnnaBridge	156:ff21514d8981	4250	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4251	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4252	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	156:ff21514d8981	4253	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4254	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	156:ff21514d8981	4255	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4256	} while(0U)
AnnaBridge	156:ff21514d8981	4257	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4258	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4259	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	156:ff21514d8981	4260	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4261	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	156:ff21514d8981	4262	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4263	} while(0U)
AnnaBridge	156:ff21514d8981	4264	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4265	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4266	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	156:ff21514d8981	4267	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4268	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	156:ff21514d8981	4269	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4270	} while(0U)
AnnaBridge	156:ff21514d8981	4271	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
AnnaBridge	156:ff21514d8981	4272	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge	156:ff21514d8981	4273	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
AnnaBridge	156:ff21514d8981	4274	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge	156:ff21514d8981	4275	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
AnnaBridge	156:ff21514d8981	4276	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
AnnaBridge	156:ff21514d8981	4277	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
AnnaBridge	156:ff21514d8981	4278	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
AnnaBridge	156:ff21514d8981	4279	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
AnnaBridge	156:ff21514d8981	4280	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
AnnaBridge	156:ff21514d8981	4281	#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
AnnaBridge	156:ff21514d8981	4282	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
AnnaBridge	156:ff21514d8981	4283	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
AnnaBridge	156:ff21514d8981	4284	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
AnnaBridge	156:ff21514d8981	4285	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
AnnaBridge	156:ff21514d8981	4286	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
AnnaBridge	156:ff21514d8981	4287	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
AnnaBridge	156:ff21514d8981	4288	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
AnnaBridge	156:ff21514d8981	4289	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
AnnaBridge	156:ff21514d8981	4290	/**
AnnaBridge	156:ff21514d8981	4291	* @}
AnnaBridge	156:ff21514d8981	4292	*/
AnnaBridge	156:ff21514d8981	4293
AnnaBridge	156:ff21514d8981	4294	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	4295	* @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge	156:ff21514d8981	4296	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	4297	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	4298	* using it.
AnnaBridge	156:ff21514d8981	4299	* @{
AnnaBridge	156:ff21514d8981	4300	*/
AnnaBridge	156:ff21514d8981	4301	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
AnnaBridge	156:ff21514d8981	4302	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge	156:ff21514d8981	4303	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
AnnaBridge	156:ff21514d8981	4304	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge	156:ff21514d8981	4305	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
AnnaBridge	156:ff21514d8981	4306	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
AnnaBridge	156:ff21514d8981	4307	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
AnnaBridge	156:ff21514d8981	4308	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
AnnaBridge	156:ff21514d8981	4309	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
AnnaBridge	156:ff21514d8981	4310	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
AnnaBridge	156:ff21514d8981	4311	#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
AnnaBridge	156:ff21514d8981	4312	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
AnnaBridge	156:ff21514d8981	4313	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
AnnaBridge	156:ff21514d8981	4314	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
AnnaBridge	156:ff21514d8981	4315	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
AnnaBridge	156:ff21514d8981	4316	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
AnnaBridge	156:ff21514d8981	4317	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
AnnaBridge	156:ff21514d8981	4318	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
AnnaBridge	156:ff21514d8981	4319	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
AnnaBridge	156:ff21514d8981	4320
AnnaBridge	156:ff21514d8981	4321	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
AnnaBridge	156:ff21514d8981	4322	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge	156:ff21514d8981	4323	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
AnnaBridge	156:ff21514d8981	4324	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge	156:ff21514d8981	4325	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
AnnaBridge	156:ff21514d8981	4326	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
AnnaBridge	156:ff21514d8981	4327	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
AnnaBridge	156:ff21514d8981	4328	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
AnnaBridge	156:ff21514d8981	4329	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
AnnaBridge	156:ff21514d8981	4330	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
AnnaBridge	156:ff21514d8981	4331	#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
AnnaBridge	156:ff21514d8981	4332	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
AnnaBridge	156:ff21514d8981	4333	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
AnnaBridge	156:ff21514d8981	4334	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
AnnaBridge	156:ff21514d8981	4335	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
AnnaBridge	156:ff21514d8981	4336	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
AnnaBridge	156:ff21514d8981	4337	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
AnnaBridge	156:ff21514d8981	4338	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
AnnaBridge	156:ff21514d8981	4339	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
AnnaBridge	156:ff21514d8981	4340	/**
AnnaBridge	156:ff21514d8981	4341	* @}
AnnaBridge	156:ff21514d8981	4342	*/
AnnaBridge	156:ff21514d8981	4343
AnnaBridge	156:ff21514d8981	4344	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	4345	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	156:ff21514d8981	4346	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	4347	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	4348	* using it.
AnnaBridge	156:ff21514d8981	4349	* @{
AnnaBridge	156:ff21514d8981	4350	*/
AnnaBridge	156:ff21514d8981	4351	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4352	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4353	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	156:ff21514d8981	4354	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4355	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	156:ff21514d8981	4356	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4357	} while(0U)
AnnaBridge	156:ff21514d8981	4358	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4359	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4360	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
AnnaBridge	156:ff21514d8981	4361	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4362	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
AnnaBridge	156:ff21514d8981	4363	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4364	} while(0U)
AnnaBridge	156:ff21514d8981	4365	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4366	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4367	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
AnnaBridge	156:ff21514d8981	4368	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4369	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
AnnaBridge	156:ff21514d8981	4370	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4371	} while(0U)
AnnaBridge	156:ff21514d8981	4372	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4373	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4374	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
AnnaBridge	156:ff21514d8981	4375	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4376	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
AnnaBridge	156:ff21514d8981	4377	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4378	} while(0U)
AnnaBridge	156:ff21514d8981	4379	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4380	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4381	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
AnnaBridge	156:ff21514d8981	4382	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4383	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
AnnaBridge	156:ff21514d8981	4384	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4385	} while(0U)
AnnaBridge	156:ff21514d8981	4386	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4387	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4388	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	156:ff21514d8981	4389	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4390	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	156:ff21514d8981	4391	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4392	} while(0U)
AnnaBridge	156:ff21514d8981	4393	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4394	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4395	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	156:ff21514d8981	4396	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4397	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	156:ff21514d8981	4398	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4399	} while(0U)
AnnaBridge	156:ff21514d8981	4400	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4401	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4402	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	156:ff21514d8981	4403	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4404	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	156:ff21514d8981	4405	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4406	} while(0U)
AnnaBridge	156:ff21514d8981	4407	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
AnnaBridge	156:ff21514d8981	4408	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
AnnaBridge	156:ff21514d8981	4409	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
AnnaBridge	156:ff21514d8981	4410	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
AnnaBridge	156:ff21514d8981	4411	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
AnnaBridge	156:ff21514d8981	4412	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
AnnaBridge	156:ff21514d8981	4413	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
AnnaBridge	156:ff21514d8981	4414	#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
AnnaBridge	156:ff21514d8981	4415	/**
AnnaBridge	156:ff21514d8981	4416	* @}
AnnaBridge	156:ff21514d8981	4417	*/
AnnaBridge	156:ff21514d8981	4418
AnnaBridge	156:ff21514d8981	4419	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	4420	* @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge	156:ff21514d8981	4421	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	4422	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	4423	* using it.
AnnaBridge	156:ff21514d8981	4424	* @{
AnnaBridge	156:ff21514d8981	4425	*/
AnnaBridge	156:ff21514d8981	4426	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
AnnaBridge	156:ff21514d8981	4427	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
AnnaBridge	156:ff21514d8981	4428	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
AnnaBridge	156:ff21514d8981	4429	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
AnnaBridge	156:ff21514d8981	4430	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
AnnaBridge	156:ff21514d8981	4431	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
AnnaBridge	156:ff21514d8981	4432	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
AnnaBridge	156:ff21514d8981	4433	#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
AnnaBridge	156:ff21514d8981	4434
AnnaBridge	156:ff21514d8981	4435	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
AnnaBridge	156:ff21514d8981	4436	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
AnnaBridge	156:ff21514d8981	4437	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
AnnaBridge	156:ff21514d8981	4438	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
AnnaBridge	156:ff21514d8981	4439	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
AnnaBridge	156:ff21514d8981	4440	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
AnnaBridge	156:ff21514d8981	4441	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
AnnaBridge	156:ff21514d8981	4442	#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
AnnaBridge	156:ff21514d8981	4443	/**
AnnaBridge	156:ff21514d8981	4444	* @}
AnnaBridge	156:ff21514d8981	4445	*/
AnnaBridge	156:ff21514d8981	4446
AnnaBridge	156:ff21514d8981	4447	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
AnnaBridge	156:ff21514d8981	4448	* @brief Force or release AHB1 peripheral reset.
AnnaBridge	156:ff21514d8981	4449	* @{
AnnaBridge	156:ff21514d8981	4450	*/
AnnaBridge	156:ff21514d8981	4451	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
AnnaBridge	156:ff21514d8981	4452	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
AnnaBridge	156:ff21514d8981	4453	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
AnnaBridge	156:ff21514d8981	4454	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
AnnaBridge	156:ff21514d8981	4455	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
AnnaBridge	156:ff21514d8981	4456	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
AnnaBridge	156:ff21514d8981	4457
AnnaBridge	156:ff21514d8981	4458	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
AnnaBridge	156:ff21514d8981	4459	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
AnnaBridge	156:ff21514d8981	4460	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
AnnaBridge	156:ff21514d8981	4461	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
AnnaBridge	156:ff21514d8981	4462	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
AnnaBridge	156:ff21514d8981	4463	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
AnnaBridge	156:ff21514d8981	4464	/**
AnnaBridge	156:ff21514d8981	4465	* @}
AnnaBridge	156:ff21514d8981	4466	*/
AnnaBridge	156:ff21514d8981	4467
AnnaBridge	156:ff21514d8981	4468	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
AnnaBridge	156:ff21514d8981	4469	* @brief Force or release AHB2 peripheral reset.
AnnaBridge	156:ff21514d8981	4470	* @{
AnnaBridge	156:ff21514d8981	4471	*/
AnnaBridge	156:ff21514d8981	4472	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
AnnaBridge	156:ff21514d8981	4473	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	156:ff21514d8981	4474	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
AnnaBridge	156:ff21514d8981	4475	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
AnnaBridge	156:ff21514d8981	4476
AnnaBridge	156:ff21514d8981	4477	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
AnnaBridge	156:ff21514d8981	4478	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	156:ff21514d8981	4479	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
AnnaBridge	156:ff21514d8981	4480	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
AnnaBridge	156:ff21514d8981	4481	/**
AnnaBridge	156:ff21514d8981	4482	* @}
AnnaBridge	156:ff21514d8981	4483	*/
AnnaBridge	156:ff21514d8981	4484
AnnaBridge	156:ff21514d8981	4485	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
AnnaBridge	156:ff21514d8981	4486	* @brief Force or release AHB3 peripheral reset.
AnnaBridge	156:ff21514d8981	4487	* @{
AnnaBridge	156:ff21514d8981	4488	*/
AnnaBridge	156:ff21514d8981	4489	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
AnnaBridge	156:ff21514d8981	4490	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
AnnaBridge	156:ff21514d8981	4491
AnnaBridge	156:ff21514d8981	4492	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
AnnaBridge	156:ff21514d8981	4493	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
AnnaBridge	156:ff21514d8981	4494
AnnaBridge	156:ff21514d8981	4495	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
AnnaBridge	156:ff21514d8981	4496	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
AnnaBridge	156:ff21514d8981	4497	/**
AnnaBridge	156:ff21514d8981	4498	* @}
AnnaBridge	156:ff21514d8981	4499	*/
AnnaBridge	156:ff21514d8981	4500
AnnaBridge	156:ff21514d8981	4501	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
AnnaBridge	156:ff21514d8981	4502	* @brief Force or release APB1 peripheral reset.
AnnaBridge	156:ff21514d8981	4503	* @{
AnnaBridge	156:ff21514d8981	4504	*/
AnnaBridge	156:ff21514d8981	4505	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
AnnaBridge	156:ff21514d8981	4506	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
AnnaBridge	156:ff21514d8981	4507	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
AnnaBridge	156:ff21514d8981	4508	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
AnnaBridge	156:ff21514d8981	4509	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
AnnaBridge	156:ff21514d8981	4510	#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPDIFRXRST))
AnnaBridge	156:ff21514d8981	4511	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
AnnaBridge	156:ff21514d8981	4512	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
AnnaBridge	156:ff21514d8981	4513	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
AnnaBridge	156:ff21514d8981	4514	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
AnnaBridge	156:ff21514d8981	4515	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
AnnaBridge	156:ff21514d8981	4516	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
AnnaBridge	156:ff21514d8981	4517	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
AnnaBridge	156:ff21514d8981	4518	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
AnnaBridge	156:ff21514d8981	4519	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
AnnaBridge	156:ff21514d8981	4520	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
AnnaBridge	156:ff21514d8981	4521	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
AnnaBridge	156:ff21514d8981	4522	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
AnnaBridge	156:ff21514d8981	4523	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
AnnaBridge	156:ff21514d8981	4524
AnnaBridge	156:ff21514d8981	4525	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
AnnaBridge	156:ff21514d8981	4526	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge	156:ff21514d8981	4527	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge	156:ff21514d8981	4528	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge	156:ff21514d8981	4529	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
AnnaBridge	156:ff21514d8981	4530	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
AnnaBridge	156:ff21514d8981	4531	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
AnnaBridge	156:ff21514d8981	4532	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
AnnaBridge	156:ff21514d8981	4533	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
AnnaBridge	156:ff21514d8981	4534	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
AnnaBridge	156:ff21514d8981	4535	#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
AnnaBridge	156:ff21514d8981	4536	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
AnnaBridge	156:ff21514d8981	4537	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
AnnaBridge	156:ff21514d8981	4538	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
AnnaBridge	156:ff21514d8981	4539	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
AnnaBridge	156:ff21514d8981	4540	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
AnnaBridge	156:ff21514d8981	4541	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
AnnaBridge	156:ff21514d8981	4542	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
AnnaBridge	156:ff21514d8981	4543	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
AnnaBridge	156:ff21514d8981	4544	/**
AnnaBridge	156:ff21514d8981	4545	* @}
AnnaBridge	156:ff21514d8981	4546	*/
AnnaBridge	156:ff21514d8981	4547
AnnaBridge	156:ff21514d8981	4548	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
AnnaBridge	156:ff21514d8981	4549	* @brief Force or release APB2 peripheral reset.
AnnaBridge	156:ff21514d8981	4550	* @{
AnnaBridge	156:ff21514d8981	4551	*/
AnnaBridge	156:ff21514d8981	4552	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
AnnaBridge	156:ff21514d8981	4553	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
AnnaBridge	156:ff21514d8981	4554	#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI2RST))
AnnaBridge	156:ff21514d8981	4555	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
AnnaBridge	156:ff21514d8981	4556	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
AnnaBridge	156:ff21514d8981	4557	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
AnnaBridge	156:ff21514d8981	4558
AnnaBridge	156:ff21514d8981	4559	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
AnnaBridge	156:ff21514d8981	4560	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
AnnaBridge	156:ff21514d8981	4561	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
AnnaBridge	156:ff21514d8981	4562	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
AnnaBridge	156:ff21514d8981	4563	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
AnnaBridge	156:ff21514d8981	4564	#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
AnnaBridge	156:ff21514d8981	4565	/**
AnnaBridge	156:ff21514d8981	4566	* @}
AnnaBridge	156:ff21514d8981	4567	*/
AnnaBridge	156:ff21514d8981	4568
AnnaBridge	156:ff21514d8981	4569	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	4570	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	4571	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	4572	* power consumption.
AnnaBridge	156:ff21514d8981	4573	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	4574	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	4575	* @{
AnnaBridge	156:ff21514d8981	4576	*/
AnnaBridge	156:ff21514d8981	4577	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	156:ff21514d8981	4578	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	156:ff21514d8981	4579	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge	156:ff21514d8981	4580	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge	156:ff21514d8981	4581	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	156:ff21514d8981	4582	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
AnnaBridge	156:ff21514d8981	4583	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
AnnaBridge	156:ff21514d8981	4584	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	156:ff21514d8981	4585	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	156:ff21514d8981	4586	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	156:ff21514d8981	4587	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
AnnaBridge	156:ff21514d8981	4588
AnnaBridge	156:ff21514d8981	4589	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	156:ff21514d8981	4590	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	156:ff21514d8981	4591	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge	156:ff21514d8981	4592	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge	156:ff21514d8981	4593	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	156:ff21514d8981	4594	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
AnnaBridge	156:ff21514d8981	4595	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
AnnaBridge	156:ff21514d8981	4596	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	156:ff21514d8981	4597	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	156:ff21514d8981	4598	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	156:ff21514d8981	4599	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
AnnaBridge	156:ff21514d8981	4600	/**
AnnaBridge	156:ff21514d8981	4601	* @}
AnnaBridge	156:ff21514d8981	4602	*/
AnnaBridge	156:ff21514d8981	4603
AnnaBridge	156:ff21514d8981	4604	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	4605	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	4606	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	4607	* power consumption.
AnnaBridge	156:ff21514d8981	4608	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	4609	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	4610	* @{
AnnaBridge	156:ff21514d8981	4611	*/
AnnaBridge	156:ff21514d8981	4612	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	156:ff21514d8981	4613	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	156:ff21514d8981	4614
AnnaBridge	156:ff21514d8981	4615	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
AnnaBridge	156:ff21514d8981	4616	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
AnnaBridge	156:ff21514d8981	4617
AnnaBridge	156:ff21514d8981	4618	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
AnnaBridge	156:ff21514d8981	4619	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
AnnaBridge	156:ff21514d8981	4620	/**
AnnaBridge	156:ff21514d8981	4621	* @}
AnnaBridge	156:ff21514d8981	4622	*/
AnnaBridge	156:ff21514d8981	4623
AnnaBridge	156:ff21514d8981	4624	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	4625	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	4626	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	4627	* power consumption.
AnnaBridge	156:ff21514d8981	4628	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	4629	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	4630	* @{
AnnaBridge	156:ff21514d8981	4631	*/
AnnaBridge	156:ff21514d8981	4632	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
AnnaBridge	156:ff21514d8981	4633	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
AnnaBridge	156:ff21514d8981	4634
AnnaBridge	156:ff21514d8981	4635	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
AnnaBridge	156:ff21514d8981	4636	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
AnnaBridge	156:ff21514d8981	4637	/**
AnnaBridge	156:ff21514d8981	4638	* @}
AnnaBridge	156:ff21514d8981	4639	*/
AnnaBridge	156:ff21514d8981	4640
AnnaBridge	156:ff21514d8981	4641	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	4642	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	4643	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	4644	* power consumption.
AnnaBridge	156:ff21514d8981	4645	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	4646	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	4647	* @{
AnnaBridge	156:ff21514d8981	4648	*/
AnnaBridge	156:ff21514d8981	4649	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	156:ff21514d8981	4650	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	156:ff21514d8981	4651	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
AnnaBridge	156:ff21514d8981	4652	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
AnnaBridge	156:ff21514d8981	4653	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	156:ff21514d8981	4654	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPDIFRXLPEN))
AnnaBridge	156:ff21514d8981	4655	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
AnnaBridge	156:ff21514d8981	4656	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
AnnaBridge	156:ff21514d8981	4657	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
AnnaBridge	156:ff21514d8981	4658	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
AnnaBridge	156:ff21514d8981	4659	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
AnnaBridge	156:ff21514d8981	4660	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	156:ff21514d8981	4661	#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CECLPEN))
AnnaBridge	156:ff21514d8981	4662	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
AnnaBridge	156:ff21514d8981	4663	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	156:ff21514d8981	4664	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	156:ff21514d8981	4665	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	156:ff21514d8981	4666	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	156:ff21514d8981	4667	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	156:ff21514d8981	4668
AnnaBridge	156:ff21514d8981	4669	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	156:ff21514d8981	4670	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	156:ff21514d8981	4671	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	156:ff21514d8981	4672	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	156:ff21514d8981	4673	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	156:ff21514d8981	4674	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	156:ff21514d8981	4675	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	156:ff21514d8981	4676	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
AnnaBridge	156:ff21514d8981	4677	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
AnnaBridge	156:ff21514d8981	4678	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	156:ff21514d8981	4679	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
AnnaBridge	156:ff21514d8981	4680	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
AnnaBridge	156:ff21514d8981	4681	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
AnnaBridge	156:ff21514d8981	4682	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
AnnaBridge	156:ff21514d8981	4683	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
AnnaBridge	156:ff21514d8981	4684	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
AnnaBridge	156:ff21514d8981	4685	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	156:ff21514d8981	4686	#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
AnnaBridge	156:ff21514d8981	4687	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
AnnaBridge	156:ff21514d8981	4688	/**
AnnaBridge	156:ff21514d8981	4689	* @}
AnnaBridge	156:ff21514d8981	4690	*/
AnnaBridge	156:ff21514d8981	4691
AnnaBridge	156:ff21514d8981	4692	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	4693	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	4694	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	4695	* power consumption.
AnnaBridge	156:ff21514d8981	4696	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	4697	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	4698	* @{
AnnaBridge	156:ff21514d8981	4699	*/
AnnaBridge	156:ff21514d8981	4700	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	156:ff21514d8981	4701	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
AnnaBridge	156:ff21514d8981	4702	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
AnnaBridge	156:ff21514d8981	4703	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
AnnaBridge	156:ff21514d8981	4704	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI2LPEN))
AnnaBridge	156:ff21514d8981	4705	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	156:ff21514d8981	4706	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	156:ff21514d8981	4707	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	156:ff21514d8981	4708
AnnaBridge	156:ff21514d8981	4709	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	156:ff21514d8981	4710	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	156:ff21514d8981	4711	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	156:ff21514d8981	4712	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	156:ff21514d8981	4713	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
AnnaBridge	156:ff21514d8981	4714	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
AnnaBridge	156:ff21514d8981	4715	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
AnnaBridge	156:ff21514d8981	4716	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
AnnaBridge	156:ff21514d8981	4717	/**
AnnaBridge	156:ff21514d8981	4718	* @}
AnnaBridge	156:ff21514d8981	4719	*/
AnnaBridge	156:ff21514d8981	4720
AnnaBridge	156:ff21514d8981	4721	#endif /* STM32F446xx */
AnnaBridge	156:ff21514d8981	4722	/----------------------------------------------------------------------------/
AnnaBridge	156:ff21514d8981	4723
AnnaBridge	156:ff21514d8981	4724	/-------STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx-------/
AnnaBridge	156:ff21514d8981	4725	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	4726	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	4727	* @brief Enables or disables the AHB1 peripheral clock.
AnnaBridge	156:ff21514d8981	4728	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	4729	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	4730	* using it.
AnnaBridge	156:ff21514d8981	4731	* @{
AnnaBridge	156:ff21514d8981	4732	*/
AnnaBridge	156:ff21514d8981	4733	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4734	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4735	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	156:ff21514d8981	4736	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4737	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	156:ff21514d8981	4738	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4739	} while(0U)
AnnaBridge	156:ff21514d8981	4740	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4741	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4742	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	156:ff21514d8981	4743	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4744	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	156:ff21514d8981	4745	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4746	} while(0U)
AnnaBridge	156:ff21514d8981	4747	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4748	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4749	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge	156:ff21514d8981	4750	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4751	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge	156:ff21514d8981	4752	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4753	} while(0U)
AnnaBridge	156:ff21514d8981	4754	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4755	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4756	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge	156:ff21514d8981	4757	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4758	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge	156:ff21514d8981	4759	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4760	} while(0U)
AnnaBridge	156:ff21514d8981	4761	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4762	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4763	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	156:ff21514d8981	4764	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4765	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	156:ff21514d8981	4766	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4767	} while(0U)
AnnaBridge	156:ff21514d8981	4768
AnnaBridge	156:ff21514d8981	4769	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
AnnaBridge	156:ff21514d8981	4770	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
AnnaBridge	156:ff21514d8981	4771	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
AnnaBridge	156:ff21514d8981	4772	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
AnnaBridge	156:ff21514d8981	4773	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
AnnaBridge	156:ff21514d8981	4774	/**
AnnaBridge	156:ff21514d8981	4775	* @}
AnnaBridge	156:ff21514d8981	4776	*/
AnnaBridge	156:ff21514d8981	4777
AnnaBridge	156:ff21514d8981	4778	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	4779	* @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge	156:ff21514d8981	4780	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	4781	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	4782	* using it.
AnnaBridge	156:ff21514d8981	4783	* @{
AnnaBridge	156:ff21514d8981	4784	*/
AnnaBridge	156:ff21514d8981	4785	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
AnnaBridge	156:ff21514d8981	4786	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
AnnaBridge	156:ff21514d8981	4787	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
AnnaBridge	156:ff21514d8981	4788	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
AnnaBridge	156:ff21514d8981	4789	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
AnnaBridge	156:ff21514d8981	4790
AnnaBridge	156:ff21514d8981	4791	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
AnnaBridge	156:ff21514d8981	4792	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
AnnaBridge	156:ff21514d8981	4793	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
AnnaBridge	156:ff21514d8981	4794	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
AnnaBridge	156:ff21514d8981	4795	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
AnnaBridge	156:ff21514d8981	4796	/**
AnnaBridge	156:ff21514d8981	4797	* @}
AnnaBridge	156:ff21514d8981	4798	*/
AnnaBridge	156:ff21514d8981	4799
AnnaBridge	156:ff21514d8981	4800	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	4801	* @brief Enable or disable the AHB2 peripheral clock.
AnnaBridge	156:ff21514d8981	4802	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	4803	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	4804	* using it.
AnnaBridge	156:ff21514d8981	4805	* @{
AnnaBridge	156:ff21514d8981	4806	*/
AnnaBridge	156:ff21514d8981	4807	#if defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	4808	#define __HAL_RCC_AES_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4809	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4810	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
AnnaBridge	156:ff21514d8981	4811	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4812	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
AnnaBridge	156:ff21514d8981	4813	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4814	} while(0U)
AnnaBridge	156:ff21514d8981	4815
AnnaBridge	156:ff21514d8981	4816	#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN))
AnnaBridge	156:ff21514d8981	4817	#endif /* STM32F423xx */
AnnaBridge	156:ff21514d8981	4818
AnnaBridge	156:ff21514d8981	4819	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4820	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4821	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge	156:ff21514d8981	4822	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4823	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge	156:ff21514d8981	4824	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4825	} while(0U)
AnnaBridge	156:ff21514d8981	4826	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
AnnaBridge	156:ff21514d8981	4827
AnnaBridge	156:ff21514d8981	4828	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
AnnaBridge	156:ff21514d8981	4829	__HAL_RCC_SYSCFG_CLK_ENABLE();\
AnnaBridge	156:ff21514d8981	4830	}while(0U)
AnnaBridge	156:ff21514d8981	4831
AnnaBridge	156:ff21514d8981	4832	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
AnnaBridge	156:ff21514d8981	4833	/**
AnnaBridge	156:ff21514d8981	4834	* @}
AnnaBridge	156:ff21514d8981	4835	*/
AnnaBridge	156:ff21514d8981	4836
AnnaBridge	156:ff21514d8981	4837	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	4838	* @brief Get the enable or disable status of the AHB2 peripheral clock.
AnnaBridge	156:ff21514d8981	4839	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	4840	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	4841	* using it.
AnnaBridge	156:ff21514d8981	4842	* @{
AnnaBridge	156:ff21514d8981	4843	*/
AnnaBridge	156:ff21514d8981	4844	#if defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	4845	#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET)
AnnaBridge	156:ff21514d8981	4846	#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET)
AnnaBridge	156:ff21514d8981	4847	#endif /* STM32F423xx */
AnnaBridge	156:ff21514d8981	4848
AnnaBridge	156:ff21514d8981	4849	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
AnnaBridge	156:ff21514d8981	4850	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
AnnaBridge	156:ff21514d8981	4851
AnnaBridge	156:ff21514d8981	4852	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
AnnaBridge	156:ff21514d8981	4853	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
AnnaBridge	156:ff21514d8981	4854	/**
AnnaBridge	156:ff21514d8981	4855	* @}
AnnaBridge	156:ff21514d8981	4856	*/
AnnaBridge	156:ff21514d8981	4857
AnnaBridge	156:ff21514d8981	4858	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	4859	* @brief Enables or disables the AHB3 peripheral clock.
AnnaBridge	156:ff21514d8981	4860	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	4861	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	4862	* using it.
AnnaBridge	156:ff21514d8981	4863	* @{
AnnaBridge	156:ff21514d8981	4864	*/
AnnaBridge	156:ff21514d8981	4865	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	4866	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4867	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4868	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
AnnaBridge	156:ff21514d8981	4869	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4870	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
AnnaBridge	156:ff21514d8981	4871	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4872	} while(0U)
AnnaBridge	156:ff21514d8981	4873	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4874	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4875	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
AnnaBridge	156:ff21514d8981	4876	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4877	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
AnnaBridge	156:ff21514d8981	4878	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4879	} while(0U)
AnnaBridge	156:ff21514d8981	4880
AnnaBridge	156:ff21514d8981	4881	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
AnnaBridge	156:ff21514d8981	4882	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
AnnaBridge	156:ff21514d8981	4883	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	4884	/**
AnnaBridge	156:ff21514d8981	4885	* @}
AnnaBridge	156:ff21514d8981	4886	*/
AnnaBridge	156:ff21514d8981	4887
AnnaBridge	156:ff21514d8981	4888	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	4889	* @brief Get the enable or disable status of the AHB3 peripheral clock.
AnnaBridge	156:ff21514d8981	4890	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	4891	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	4892	* using it.
AnnaBridge	156:ff21514d8981	4893	* @{
AnnaBridge	156:ff21514d8981	4894	*/
AnnaBridge	156:ff21514d8981	4895	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	4896	#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
AnnaBridge	156:ff21514d8981	4897	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
AnnaBridge	156:ff21514d8981	4898
AnnaBridge	156:ff21514d8981	4899	#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
AnnaBridge	156:ff21514d8981	4900	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
AnnaBridge	156:ff21514d8981	4901	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	4902
AnnaBridge	156:ff21514d8981	4903	/**
AnnaBridge	156:ff21514d8981	4904	* @}
AnnaBridge	156:ff21514d8981	4905	*/
AnnaBridge	156:ff21514d8981	4906
AnnaBridge	156:ff21514d8981	4907	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	4908	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	156:ff21514d8981	4909	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	4910	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	4911	* using it.
AnnaBridge	156:ff21514d8981	4912	* @{
AnnaBridge	156:ff21514d8981	4913	*/
AnnaBridge	156:ff21514d8981	4914	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4915	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4916	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	156:ff21514d8981	4917	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4918	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	156:ff21514d8981	4919	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4920	} while(0U)
AnnaBridge	156:ff21514d8981	4921	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4922	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4923	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	156:ff21514d8981	4924	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4925	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	156:ff21514d8981	4926	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4927	} while(0U)
AnnaBridge	156:ff21514d8981	4928	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4929	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4930	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	156:ff21514d8981	4931	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4932	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	156:ff21514d8981	4933	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4934	} while(0U)
AnnaBridge	156:ff21514d8981	4935	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4936	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4937	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	156:ff21514d8981	4938	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4939	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	156:ff21514d8981	4940	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4941	} while(0U)
AnnaBridge	156:ff21514d8981	4942	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4943	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4944	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	156:ff21514d8981	4945	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4946	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	156:ff21514d8981	4947	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4948	} while(0U)
AnnaBridge	156:ff21514d8981	4949	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	4950	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4951	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4952	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
AnnaBridge	156:ff21514d8981	4953	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4954	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
AnnaBridge	156:ff21514d8981	4955	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4956	} while(0U)
AnnaBridge	156:ff21514d8981	4957	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	4958	#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4959	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4960	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
AnnaBridge	156:ff21514d8981	4961	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4962	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
AnnaBridge	156:ff21514d8981	4963	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4964	} while(0U)
AnnaBridge	156:ff21514d8981	4965	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	4966	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4967	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4968	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	156:ff21514d8981	4969	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4970	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	156:ff21514d8981	4971	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4972	} while(0U)
AnnaBridge	156:ff21514d8981	4973	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	4974
AnnaBridge	156:ff21514d8981	4975	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	4976	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4977	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4978	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	156:ff21514d8981	4979	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4980	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	156:ff21514d8981	4981	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4982	} while(0U)
AnnaBridge	156:ff21514d8981	4983	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4984	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4985	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	156:ff21514d8981	4986	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4987	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	156:ff21514d8981	4988	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4989	} while(0U)
AnnaBridge	156:ff21514d8981	4990	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	4991
AnnaBridge	156:ff21514d8981	4992	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	4993	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	4994	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
AnnaBridge	156:ff21514d8981	4995	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	4996	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
AnnaBridge	156:ff21514d8981	4997	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	4998	} while(0U)
AnnaBridge	156:ff21514d8981	4999	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5000	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5001	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	156:ff21514d8981	5002	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5003	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	156:ff21514d8981	5004	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5005	} while(0U)
AnnaBridge	156:ff21514d8981	5006	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5007	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5008	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	156:ff21514d8981	5009	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5010	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	156:ff21514d8981	5011	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5012	} while(0U)
AnnaBridge	156:ff21514d8981	5013	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5014	#define __HAL_RCC_CAN3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5015	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5016	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
AnnaBridge	156:ff21514d8981	5017	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5018	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
AnnaBridge	156:ff21514d8981	5019	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5020	} while(0U)
AnnaBridge	156:ff21514d8981	5021	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5022	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5023	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5024	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	156:ff21514d8981	5025	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5026	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	156:ff21514d8981	5027	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5028	} while(0U)
AnnaBridge	156:ff21514d8981	5029	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5030	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5031	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	156:ff21514d8981	5032	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5033	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	156:ff21514d8981	5034	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5035	} while(0U)
AnnaBridge	156:ff21514d8981	5036	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5037	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5038	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	156:ff21514d8981	5039	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5040	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	156:ff21514d8981	5041	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5042	} while(0U)
AnnaBridge	156:ff21514d8981	5043	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5044	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5045	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	156:ff21514d8981	5046	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5047	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	156:ff21514d8981	5048	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5049	} while(0U)
AnnaBridge	156:ff21514d8981	5050	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5051	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5052	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	156:ff21514d8981	5053	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5054	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	156:ff21514d8981	5055	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5056	} while(0U)
AnnaBridge	156:ff21514d8981	5057	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5058	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5059	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5060	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	156:ff21514d8981	5061	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5062	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	156:ff21514d8981	5063	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5064	} while(0U)
AnnaBridge	156:ff21514d8981	5065	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5066	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5067	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
AnnaBridge	156:ff21514d8981	5068	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5069	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
AnnaBridge	156:ff21514d8981	5070	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5071	} while(0U)
AnnaBridge	156:ff21514d8981	5072	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5073	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5074	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
AnnaBridge	156:ff21514d8981	5075	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5076	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
AnnaBridge	156:ff21514d8981	5077	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5078	} while(0U)
AnnaBridge	156:ff21514d8981	5079	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5080
AnnaBridge	156:ff21514d8981	5081	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
AnnaBridge	156:ff21514d8981	5082	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge	156:ff21514d8981	5083	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
AnnaBridge	156:ff21514d8981	5084	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
AnnaBridge	156:ff21514d8981	5085	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
AnnaBridge	156:ff21514d8981	5086	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
AnnaBridge	156:ff21514d8981	5087	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
AnnaBridge	156:ff21514d8981	5088	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
AnnaBridge	156:ff21514d8981	5089	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5090	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
AnnaBridge	156:ff21514d8981	5091	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5092	#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
AnnaBridge	156:ff21514d8981	5093	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge	156:ff21514d8981	5094	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5095	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
AnnaBridge	156:ff21514d8981	5096	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5097	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5098	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
AnnaBridge	156:ff21514d8981	5099	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
AnnaBridge	156:ff21514d8981	5100	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5101	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
AnnaBridge	156:ff21514d8981	5102	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
AnnaBridge	156:ff21514d8981	5103	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
AnnaBridge	156:ff21514d8981	5104	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
AnnaBridge	156:ff21514d8981	5105	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5106	#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))
AnnaBridge	156:ff21514d8981	5107	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
AnnaBridge	156:ff21514d8981	5108	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
AnnaBridge	156:ff21514d8981	5109	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
AnnaBridge	156:ff21514d8981	5110	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5111
AnnaBridge	156:ff21514d8981	5112	/**
AnnaBridge	156:ff21514d8981	5113	* @}
AnnaBridge	156:ff21514d8981	5114	*/
AnnaBridge	156:ff21514d8981	5115
AnnaBridge	156:ff21514d8981	5116	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	5117	* @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge	156:ff21514d8981	5118	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	5119	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	5120	* using it.
AnnaBridge	156:ff21514d8981	5121	* @{
AnnaBridge	156:ff21514d8981	5122	*/
AnnaBridge	156:ff21514d8981	5123	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
AnnaBridge	156:ff21514d8981	5124	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge	156:ff21514d8981	5125	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
AnnaBridge	156:ff21514d8981	5126	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
AnnaBridge	156:ff21514d8981	5127	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
AnnaBridge	156:ff21514d8981	5128	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
AnnaBridge	156:ff21514d8981	5129	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
AnnaBridge	156:ff21514d8981	5130	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
AnnaBridge	156:ff21514d8981	5131	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5132	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
AnnaBridge	156:ff21514d8981	5133	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5134	#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
AnnaBridge	156:ff21514d8981	5135	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge	156:ff21514d8981	5136	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5137	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
AnnaBridge	156:ff21514d8981	5138	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \| STM32F423xx */
AnnaBridge	156:ff21514d8981	5139	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5140	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
AnnaBridge	156:ff21514d8981	5141	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
AnnaBridge	156:ff21514d8981	5142	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5143	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
AnnaBridge	156:ff21514d8981	5144	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
AnnaBridge	156:ff21514d8981	5145	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET)
AnnaBridge	156:ff21514d8981	5146	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
AnnaBridge	156:ff21514d8981	5147	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5148	#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)
AnnaBridge	156:ff21514d8981	5149	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
AnnaBridge	156:ff21514d8981	5150	#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
AnnaBridge	156:ff21514d8981	5151	#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
AnnaBridge	156:ff21514d8981	5152	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5153
AnnaBridge	156:ff21514d8981	5154	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
AnnaBridge	156:ff21514d8981	5155	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge	156:ff21514d8981	5156	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
AnnaBridge	156:ff21514d8981	5157	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
AnnaBridge	156:ff21514d8981	5158	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
AnnaBridge	156:ff21514d8981	5159	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
AnnaBridge	156:ff21514d8981	5160	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
AnnaBridge	156:ff21514d8981	5161	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
AnnaBridge	156:ff21514d8981	5162	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5163	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
AnnaBridge	156:ff21514d8981	5164	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5165	#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
AnnaBridge	156:ff21514d8981	5166	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge	156:ff21514d8981	5167	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5168	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
AnnaBridge	156:ff21514d8981	5169	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \| STM32F423xx */
AnnaBridge	156:ff21514d8981	5170	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5171	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
AnnaBridge	156:ff21514d8981	5172	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
AnnaBridge	156:ff21514d8981	5173	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5174	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
AnnaBridge	156:ff21514d8981	5175	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
AnnaBridge	156:ff21514d8981	5176	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
AnnaBridge	156:ff21514d8981	5177	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
AnnaBridge	156:ff21514d8981	5178	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5179	#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)
AnnaBridge	156:ff21514d8981	5180	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
AnnaBridge	156:ff21514d8981	5181	#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
AnnaBridge	156:ff21514d8981	5182	#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
AnnaBridge	156:ff21514d8981	5183	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5184	/**
AnnaBridge	156:ff21514d8981	5185	* @}
AnnaBridge	156:ff21514d8981	5186	*/
AnnaBridge	156:ff21514d8981	5187	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	5188	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	156:ff21514d8981	5189	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	5190	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	5191	* using it.
AnnaBridge	156:ff21514d8981	5192	* @{
AnnaBridge	156:ff21514d8981	5193	*/
AnnaBridge	156:ff21514d8981	5194	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5195	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5196	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	156:ff21514d8981	5197	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5198	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	156:ff21514d8981	5199	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5200	} while(0U)
AnnaBridge	156:ff21514d8981	5201	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5202	#define __HAL_RCC_UART9_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5203	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5204	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
AnnaBridge	156:ff21514d8981	5205	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5206	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
AnnaBridge	156:ff21514d8981	5207	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5208	} while(0U)
AnnaBridge	156:ff21514d8981	5209	#define __HAL_RCC_UART10_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5210	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5211	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
AnnaBridge	156:ff21514d8981	5212	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5213	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
AnnaBridge	156:ff21514d8981	5214	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5215	} while(0U)
AnnaBridge	156:ff21514d8981	5216	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5217	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5218	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5219	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	156:ff21514d8981	5220	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5221	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	156:ff21514d8981	5222	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5223	} while(0U)
AnnaBridge	156:ff21514d8981	5224	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5225	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5226	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	156:ff21514d8981	5227	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5228	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
AnnaBridge	156:ff21514d8981	5229	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5230	} while(0U)
AnnaBridge	156:ff21514d8981	5231	#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5232	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5233	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
AnnaBridge	156:ff21514d8981	5234	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5235	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
AnnaBridge	156:ff21514d8981	5236	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5237	} while(0U)
AnnaBridge	156:ff21514d8981	5238	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5239	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5240	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	156:ff21514d8981	5241	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5242	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	156:ff21514d8981	5243	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5244	} while(0U)
AnnaBridge	156:ff21514d8981	5245	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5246	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5247	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
AnnaBridge	156:ff21514d8981	5248	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5249	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
AnnaBridge	156:ff21514d8981	5250	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5251	} while(0U)
AnnaBridge	156:ff21514d8981	5252	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5253	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5254	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5255	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
AnnaBridge	156:ff21514d8981	5256	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5257	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
AnnaBridge	156:ff21514d8981	5258	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5259	} while(0U)
AnnaBridge	156:ff21514d8981	5260	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5261	#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5262	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5263	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
AnnaBridge	156:ff21514d8981	5264	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5265	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
AnnaBridge	156:ff21514d8981	5266	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5267	} while(0U)
AnnaBridge	156:ff21514d8981	5268	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5269	#define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	5270	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	156:ff21514d8981	5271	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
AnnaBridge	156:ff21514d8981	5272	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	5273	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
AnnaBridge	156:ff21514d8981	5274	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	5275	} while(0U)
AnnaBridge	156:ff21514d8981	5276	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5277
AnnaBridge	156:ff21514d8981	5278	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
AnnaBridge	156:ff21514d8981	5279	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5280	#define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN))
AnnaBridge	156:ff21514d8981	5281	#define __HAL_RCC_UART10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN))
AnnaBridge	156:ff21514d8981	5282	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5283	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
AnnaBridge	156:ff21514d8981	5284	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
AnnaBridge	156:ff21514d8981	5285	#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
AnnaBridge	156:ff21514d8981	5286	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
AnnaBridge	156:ff21514d8981	5287	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
AnnaBridge	156:ff21514d8981	5288	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5289	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
AnnaBridge	156:ff21514d8981	5290	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5291	#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
AnnaBridge	156:ff21514d8981	5292	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5293	#define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN))
AnnaBridge	156:ff21514d8981	5294	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5295	/**
AnnaBridge	156:ff21514d8981	5296	* @}
AnnaBridge	156:ff21514d8981	5297	*/
AnnaBridge	156:ff21514d8981	5298
AnnaBridge	156:ff21514d8981	5299	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	5300	* @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge	156:ff21514d8981	5301	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	5302	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	5303	* using it.
AnnaBridge	156:ff21514d8981	5304	* @{
AnnaBridge	156:ff21514d8981	5305	*/
AnnaBridge	156:ff21514d8981	5306	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
AnnaBridge	156:ff21514d8981	5307	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5308	#define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET)
AnnaBridge	156:ff21514d8981	5309	#define __HAL_RCC_UART10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET)
AnnaBridge	156:ff21514d8981	5310	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5311	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
AnnaBridge	156:ff21514d8981	5312	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
AnnaBridge	156:ff21514d8981	5313	#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
AnnaBridge	156:ff21514d8981	5314	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
AnnaBridge	156:ff21514d8981	5315	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
AnnaBridge	156:ff21514d8981	5316	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5317	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
AnnaBridge	156:ff21514d8981	5318	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5319	#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
AnnaBridge	156:ff21514d8981	5320	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5321	#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET)
AnnaBridge	156:ff21514d8981	5322	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5323
AnnaBridge	156:ff21514d8981	5324	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
AnnaBridge	156:ff21514d8981	5325	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5326	#define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET)
AnnaBridge	156:ff21514d8981	5327	#define __HAL_RCC_UART10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET)
AnnaBridge	156:ff21514d8981	5328	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5329	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
AnnaBridge	156:ff21514d8981	5330	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
AnnaBridge	156:ff21514d8981	5331	#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
AnnaBridge	156:ff21514d8981	5332	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
AnnaBridge	156:ff21514d8981	5333	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
AnnaBridge	156:ff21514d8981	5334	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5335	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
AnnaBridge	156:ff21514d8981	5336	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5337	#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
AnnaBridge	156:ff21514d8981	5338	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5339	#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET)
AnnaBridge	156:ff21514d8981	5340	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5341	/**
AnnaBridge	156:ff21514d8981	5342	* @}
AnnaBridge	156:ff21514d8981	5343	*/
AnnaBridge	156:ff21514d8981	5344
AnnaBridge	156:ff21514d8981	5345	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
AnnaBridge	156:ff21514d8981	5346	* @brief Force or release AHB1 peripheral reset.
AnnaBridge	156:ff21514d8981	5347	* @{
AnnaBridge	156:ff21514d8981	5348	*/
AnnaBridge	156:ff21514d8981	5349	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
AnnaBridge	156:ff21514d8981	5350	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
AnnaBridge	156:ff21514d8981	5351	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
AnnaBridge	156:ff21514d8981	5352	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
AnnaBridge	156:ff21514d8981	5353	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
AnnaBridge	156:ff21514d8981	5354
AnnaBridge	156:ff21514d8981	5355	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
AnnaBridge	156:ff21514d8981	5356	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
AnnaBridge	156:ff21514d8981	5357	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
AnnaBridge	156:ff21514d8981	5358	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
AnnaBridge	156:ff21514d8981	5359	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
AnnaBridge	156:ff21514d8981	5360	/**
AnnaBridge	156:ff21514d8981	5361	* @}
AnnaBridge	156:ff21514d8981	5362	*/
AnnaBridge	156:ff21514d8981	5363
AnnaBridge	156:ff21514d8981	5364	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
AnnaBridge	156:ff21514d8981	5365	* @brief Force or release AHB2 peripheral reset.
AnnaBridge	156:ff21514d8981	5366	* @{
AnnaBridge	156:ff21514d8981	5367	*/
AnnaBridge	156:ff21514d8981	5368	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
AnnaBridge	156:ff21514d8981	5369	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
AnnaBridge	156:ff21514d8981	5370
AnnaBridge	156:ff21514d8981	5371	#if defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5372	#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_AESRST))
AnnaBridge	156:ff21514d8981	5373	#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST))
AnnaBridge	156:ff21514d8981	5374	#endif /* STM32F423xx */
AnnaBridge	156:ff21514d8981	5375
AnnaBridge	156:ff21514d8981	5376	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	156:ff21514d8981	5377	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	156:ff21514d8981	5378
AnnaBridge	156:ff21514d8981	5379	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
AnnaBridge	156:ff21514d8981	5380	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
AnnaBridge	156:ff21514d8981	5381	/**
AnnaBridge	156:ff21514d8981	5382	* @}
AnnaBridge	156:ff21514d8981	5383	*/
AnnaBridge	156:ff21514d8981	5384
AnnaBridge	156:ff21514d8981	5385	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
AnnaBridge	156:ff21514d8981	5386	* @brief Force or release AHB3 peripheral reset.
AnnaBridge	156:ff21514d8981	5387	* @{
AnnaBridge	156:ff21514d8981	5388	*/
AnnaBridge	156:ff21514d8981	5389	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5390	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
AnnaBridge	156:ff21514d8981	5391	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
AnnaBridge	156:ff21514d8981	5392
AnnaBridge	156:ff21514d8981	5393	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
AnnaBridge	156:ff21514d8981	5394	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
AnnaBridge	156:ff21514d8981	5395
AnnaBridge	156:ff21514d8981	5396	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
AnnaBridge	156:ff21514d8981	5397	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
AnnaBridge	156:ff21514d8981	5398	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5399	#if defined(STM32F412Cx)
AnnaBridge	156:ff21514d8981	5400	#define __HAL_RCC_AHB3_FORCE_RESET()
AnnaBridge	156:ff21514d8981	5401	#define __HAL_RCC_AHB3_RELEASE_RESET()
AnnaBridge	156:ff21514d8981	5402
AnnaBridge	156:ff21514d8981	5403	#define __HAL_RCC_FSMC_FORCE_RESET()
AnnaBridge	156:ff21514d8981	5404	#define __HAL_RCC_QSPI_FORCE_RESET()
AnnaBridge	156:ff21514d8981	5405
AnnaBridge	156:ff21514d8981	5406	#define __HAL_RCC_FSMC_RELEASE_RESET()
AnnaBridge	156:ff21514d8981	5407	#define __HAL_RCC_QSPI_RELEASE_RESET()
AnnaBridge	156:ff21514d8981	5408	#endif /* STM32F412Cx */
AnnaBridge	156:ff21514d8981	5409	/**
AnnaBridge	156:ff21514d8981	5410	* @}
AnnaBridge	156:ff21514d8981	5411	*/
AnnaBridge	156:ff21514d8981	5412
AnnaBridge	156:ff21514d8981	5413	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
AnnaBridge	156:ff21514d8981	5414	* @brief Force or release APB1 peripheral reset.
AnnaBridge	156:ff21514d8981	5415	* @{
AnnaBridge	156:ff21514d8981	5416	*/
AnnaBridge	156:ff21514d8981	5417	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
AnnaBridge	156:ff21514d8981	5418	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
AnnaBridge	156:ff21514d8981	5419	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
AnnaBridge	156:ff21514d8981	5420	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
AnnaBridge	156:ff21514d8981	5421	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
AnnaBridge	156:ff21514d8981	5422	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
AnnaBridge	156:ff21514d8981	5423	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
AnnaBridge	156:ff21514d8981	5424	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
AnnaBridge	156:ff21514d8981	5425	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5426	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
AnnaBridge	156:ff21514d8981	5427	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5428	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
AnnaBridge	156:ff21514d8981	5429	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5430	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
AnnaBridge	156:ff21514d8981	5431	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5432	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5433	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
AnnaBridge	156:ff21514d8981	5434	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
AnnaBridge	156:ff21514d8981	5435	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5436	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
AnnaBridge	156:ff21514d8981	5437	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
AnnaBridge	156:ff21514d8981	5438	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
AnnaBridge	156:ff21514d8981	5439	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
AnnaBridge	156:ff21514d8981	5440	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5441	#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN3RST))
AnnaBridge	156:ff21514d8981	5442	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
AnnaBridge	156:ff21514d8981	5443	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
AnnaBridge	156:ff21514d8981	5444	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
AnnaBridge	156:ff21514d8981	5445	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5446
AnnaBridge	156:ff21514d8981	5447	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
AnnaBridge	156:ff21514d8981	5448	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge	156:ff21514d8981	5449	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge	156:ff21514d8981	5450	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
AnnaBridge	156:ff21514d8981	5451	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
AnnaBridge	156:ff21514d8981	5452	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
AnnaBridge	156:ff21514d8981	5453	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
AnnaBridge	156:ff21514d8981	5454	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
AnnaBridge	156:ff21514d8981	5455	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5456	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
AnnaBridge	156:ff21514d8981	5457	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5458	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge	156:ff21514d8981	5459	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5460	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
AnnaBridge	156:ff21514d8981	5461	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5462	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5463	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
AnnaBridge	156:ff21514d8981	5464	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
AnnaBridge	156:ff21514d8981	5465	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5466	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
AnnaBridge	156:ff21514d8981	5467	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
AnnaBridge	156:ff21514d8981	5468	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
AnnaBridge	156:ff21514d8981	5469	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
AnnaBridge	156:ff21514d8981	5470	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5471	#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))
AnnaBridge	156:ff21514d8981	5472	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
AnnaBridge	156:ff21514d8981	5473	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
AnnaBridge	156:ff21514d8981	5474	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
AnnaBridge	156:ff21514d8981	5475	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5476	/**
AnnaBridge	156:ff21514d8981	5477	* @}
AnnaBridge	156:ff21514d8981	5478	*/
AnnaBridge	156:ff21514d8981	5479
AnnaBridge	156:ff21514d8981	5480	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
AnnaBridge	156:ff21514d8981	5481	* @brief Force or release APB2 peripheral reset.
AnnaBridge	156:ff21514d8981	5482	* @{
AnnaBridge	156:ff21514d8981	5483	*/
AnnaBridge	156:ff21514d8981	5484	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
AnnaBridge	156:ff21514d8981	5485	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5486	#define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_UART9RST))
AnnaBridge	156:ff21514d8981	5487	#define __HAL_RCC_UART10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_UART10RST))
AnnaBridge	156:ff21514d8981	5488	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5489	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
AnnaBridge	156:ff21514d8981	5490	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
AnnaBridge	156:ff21514d8981	5491	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
AnnaBridge	156:ff21514d8981	5492	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
AnnaBridge	156:ff21514d8981	5493	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5494	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
AnnaBridge	156:ff21514d8981	5495	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5496	#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DFSDM1RST))
AnnaBridge	156:ff21514d8981	5497	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5498	#define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DFSDM2RST))
AnnaBridge	156:ff21514d8981	5499	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5500
AnnaBridge	156:ff21514d8981	5501	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
AnnaBridge	156:ff21514d8981	5502	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5503	#define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST))
AnnaBridge	156:ff21514d8981	5504	#define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST))
AnnaBridge	156:ff21514d8981	5505	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5506	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
AnnaBridge	156:ff21514d8981	5507	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
AnnaBridge	156:ff21514d8981	5508	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
AnnaBridge	156:ff21514d8981	5509	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
AnnaBridge	156:ff21514d8981	5510	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5511	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
AnnaBridge	156:ff21514d8981	5512	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5513	#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
AnnaBridge	156:ff21514d8981	5514	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5515	#define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST))
AnnaBridge	156:ff21514d8981	5516	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5517	/**
AnnaBridge	156:ff21514d8981	5518	* @}
AnnaBridge	156:ff21514d8981	5519	*/
AnnaBridge	156:ff21514d8981	5520
AnnaBridge	156:ff21514d8981	5521	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	5522	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	5523	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	5524	* power consumption.
AnnaBridge	156:ff21514d8981	5525	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	5526	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	5527	* @{
AnnaBridge	156:ff21514d8981	5528	*/
AnnaBridge	156:ff21514d8981	5529	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	156:ff21514d8981	5530	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	156:ff21514d8981	5531	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge	156:ff21514d8981	5532	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge	156:ff21514d8981	5533	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	156:ff21514d8981	5534	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	156:ff21514d8981	5535	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	156:ff21514d8981	5536	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5537	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	156:ff21514d8981	5538	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5539
AnnaBridge	156:ff21514d8981	5540	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	156:ff21514d8981	5541	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	156:ff21514d8981	5542	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge	156:ff21514d8981	5543	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge	156:ff21514d8981	5544	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	156:ff21514d8981	5545	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	156:ff21514d8981	5546	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	156:ff21514d8981	5547	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5548	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	156:ff21514d8981	5549	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5550	/**
AnnaBridge	156:ff21514d8981	5551	* @}
AnnaBridge	156:ff21514d8981	5552	*/
AnnaBridge	156:ff21514d8981	5553
AnnaBridge	156:ff21514d8981	5554	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	5555	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	5556	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	5557	* power consumption.
AnnaBridge	156:ff21514d8981	5558	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	5559	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	5560	* @{
AnnaBridge	156:ff21514d8981	5561	*/
AnnaBridge	156:ff21514d8981	5562	#if defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5563	#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_AESLPEN))
AnnaBridge	156:ff21514d8981	5564	#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN))
AnnaBridge	156:ff21514d8981	5565	#endif /* STM32F423xx */
AnnaBridge	156:ff21514d8981	5566
AnnaBridge	156:ff21514d8981	5567	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	156:ff21514d8981	5568	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	156:ff21514d8981	5569
AnnaBridge	156:ff21514d8981	5570	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
AnnaBridge	156:ff21514d8981	5571	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
AnnaBridge	156:ff21514d8981	5572	/**
AnnaBridge	156:ff21514d8981	5573	* @}
AnnaBridge	156:ff21514d8981	5574	*/
AnnaBridge	156:ff21514d8981	5575
AnnaBridge	156:ff21514d8981	5576	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	5577	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	5578	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	5579	* power consumption.
AnnaBridge	156:ff21514d8981	5580	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	5581	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	5582	* @{
AnnaBridge	156:ff21514d8981	5583	*/
AnnaBridge	156:ff21514d8981	5584	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5585	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
AnnaBridge	156:ff21514d8981	5586	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
AnnaBridge	156:ff21514d8981	5587
AnnaBridge	156:ff21514d8981	5588	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
AnnaBridge	156:ff21514d8981	5589	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
AnnaBridge	156:ff21514d8981	5590	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5591
AnnaBridge	156:ff21514d8981	5592	/**
AnnaBridge	156:ff21514d8981	5593	* @}
AnnaBridge	156:ff21514d8981	5594	*/
AnnaBridge	156:ff21514d8981	5595
AnnaBridge	156:ff21514d8981	5596	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	5597	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	5598	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	5599	* power consumption.
AnnaBridge	156:ff21514d8981	5600	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	5601	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	5602	* @{
AnnaBridge	156:ff21514d8981	5603	*/
AnnaBridge	156:ff21514d8981	5604	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	156:ff21514d8981	5605	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	156:ff21514d8981	5606	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	156:ff21514d8981	5607	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	156:ff21514d8981	5608	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	156:ff21514d8981	5609	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
AnnaBridge	156:ff21514d8981	5610	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
AnnaBridge	156:ff21514d8981	5611	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	156:ff21514d8981	5612	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5613	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_LPTIM1LPEN))
AnnaBridge	156:ff21514d8981	5614	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5615	#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_RTCAPBLPEN))
AnnaBridge	156:ff21514d8981	5616	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	156:ff21514d8981	5617	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5618	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
AnnaBridge	156:ff21514d8981	5619	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5620	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5621	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
AnnaBridge	156:ff21514d8981	5622	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
AnnaBridge	156:ff21514d8981	5623	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5624	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	156:ff21514d8981	5625	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
AnnaBridge	156:ff21514d8981	5626	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
AnnaBridge	156:ff21514d8981	5627	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	156:ff21514d8981	5628	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5629	#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN3LPEN))
AnnaBridge	156:ff21514d8981	5630	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
AnnaBridge	156:ff21514d8981	5631	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
AnnaBridge	156:ff21514d8981	5632	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
AnnaBridge	156:ff21514d8981	5633	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5634
AnnaBridge	156:ff21514d8981	5635	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	156:ff21514d8981	5636	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	156:ff21514d8981	5637	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	156:ff21514d8981	5638	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	156:ff21514d8981	5639	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	156:ff21514d8981	5640	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
AnnaBridge	156:ff21514d8981	5641	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
AnnaBridge	156:ff21514d8981	5642	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	156:ff21514d8981	5643	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5644	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
AnnaBridge	156:ff21514d8981	5645	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5646	#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
AnnaBridge	156:ff21514d8981	5647	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	156:ff21514d8981	5648	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5649	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
AnnaBridge	156:ff21514d8981	5650	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5651	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5652	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
AnnaBridge	156:ff21514d8981	5653	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
AnnaBridge	156:ff21514d8981	5654	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5655	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	156:ff21514d8981	5656	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
AnnaBridge	156:ff21514d8981	5657	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
AnnaBridge	156:ff21514d8981	5658	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	156:ff21514d8981	5659	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5660	#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))
AnnaBridge	156:ff21514d8981	5661	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
AnnaBridge	156:ff21514d8981	5662	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
AnnaBridge	156:ff21514d8981	5663	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
AnnaBridge	156:ff21514d8981	5664	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5665	/**
AnnaBridge	156:ff21514d8981	5666	* @}
AnnaBridge	156:ff21514d8981	5667	*/
AnnaBridge	156:ff21514d8981	5668
AnnaBridge	156:ff21514d8981	5669	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
AnnaBridge	156:ff21514d8981	5670	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	5671	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	5672	* power consumption.
AnnaBridge	156:ff21514d8981	5673	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	5674	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	5675	* @{
AnnaBridge	156:ff21514d8981	5676	*/
AnnaBridge	156:ff21514d8981	5677	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	156:ff21514d8981	5678	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5679	#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_UART9LPEN))
AnnaBridge	156:ff21514d8981	5680	#define __HAL_RCC_UART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_UART10LPEN))
AnnaBridge	156:ff21514d8981	5681	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5682	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	156:ff21514d8981	5683	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	156:ff21514d8981	5684	#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_EXTITLPEN))
AnnaBridge	156:ff21514d8981	5685	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	156:ff21514d8981	5686	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
AnnaBridge	156:ff21514d8981	5687	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5688	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
AnnaBridge	156:ff21514d8981	5689	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5690	#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DFSDM1LPEN))
AnnaBridge	156:ff21514d8981	5691	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5692	#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DFSDM2LPEN))
AnnaBridge	156:ff21514d8981	5693	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5694
AnnaBridge	156:ff21514d8981	5695	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	156:ff21514d8981	5696	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5697	#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN))
AnnaBridge	156:ff21514d8981	5698	#define __HAL_RCC_UART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN))
AnnaBridge	156:ff21514d8981	5699	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5700	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	156:ff21514d8981	5701	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
AnnaBridge	156:ff21514d8981	5702	#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
AnnaBridge	156:ff21514d8981	5703	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	156:ff21514d8981	5704	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
AnnaBridge	156:ff21514d8981	5705	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5706	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
AnnaBridge	156:ff21514d8981	5707	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5708	#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
AnnaBridge	156:ff21514d8981	5709	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5710	#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN))
AnnaBridge	156:ff21514d8981	5711	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5712	/**
AnnaBridge	156:ff21514d8981	5713	* @}
AnnaBridge	156:ff21514d8981	5714	*/
AnnaBridge	156:ff21514d8981	5715	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	5716	/----------------------------------------------------------------------------/
AnnaBridge	156:ff21514d8981	5717
AnnaBridge	156:ff21514d8981	5718	/------------------------------- PLL Configuration --------------------------/
AnnaBridge	156:ff21514d8981	5719	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\|\
AnnaBridge	156:ff21514d8981	5720	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	156:ff21514d8981	5721	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5722	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
AnnaBridge	156:ff21514d8981	5723	* @note This function must be used only when the main PLL is disabled.
AnnaBridge	163:e59c8e839560	5724	* @param __RCC_PLLSource__ specifies the PLL entry clock source.
AnnaBridge	156:ff21514d8981	5725	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	5726	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
AnnaBridge	156:ff21514d8981	5727	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
AnnaBridge	156:ff21514d8981	5728	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
AnnaBridge	163:e59c8e839560	5729	* @param __PLLM__ specifies the division factor for PLL VCO input clock
AnnaBridge	156:ff21514d8981	5730	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
AnnaBridge	156:ff21514d8981	5731	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge	156:ff21514d8981	5732	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
AnnaBridge	156:ff21514d8981	5733	* of 2 MHz to limit PLL jitter.
AnnaBridge	163:e59c8e839560	5734	* @param __PLLN__ specifies the multiplication factor for PLL VCO output clock
AnnaBridge	156:ff21514d8981	5735	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	156:ff21514d8981	5736	* @note You have to set the PLLN parameter correctly to ensure that the VCO
AnnaBridge	156:ff21514d8981	5737	* output frequency is between 100 and 432 MHz.
AnnaBridge	156:ff21514d8981	5738	*
AnnaBridge	163:e59c8e839560	5739	* @param __PLLP__ specifies the division factor for main system clock (SYSCLK)
AnnaBridge	156:ff21514d8981	5740	* This parameter must be a number in the range {2, 4, 6, or 8}.
AnnaBridge	156:ff21514d8981	5741	*
AnnaBridge	163:e59c8e839560	5742	* @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks
AnnaBridge	156:ff21514d8981	5743	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	156:ff21514d8981	5744	* @note If the USB OTG FS is used in your application, you have to set the
AnnaBridge	156:ff21514d8981	5745	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
AnnaBridge	156:ff21514d8981	5746	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
AnnaBridge	156:ff21514d8981	5747	* correctly.
AnnaBridge	156:ff21514d8981	5748	*
AnnaBridge	163:e59c8e839560	5749	* @param __PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
AnnaBridge	156:ff21514d8981	5750	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	156:ff21514d8981	5751	* @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/
AnnaBridge	156:ff21514d8981	5752	STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.
AnnaBridge	156:ff21514d8981	5753	*
AnnaBridge	156:ff21514d8981	5754	*/
AnnaBridge	156:ff21514d8981	5755	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
AnnaBridge	156:ff21514d8981	5756	(RCC->PLLCFGR = ((__RCC_PLLSource__) \| (__PLLM__) \| \
AnnaBridge	163:e59c8e839560	5757	((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) \| \
AnnaBridge	163:e59c8e839560	5758	((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) \| \
AnnaBridge	163:e59c8e839560	5759	((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) \| \
AnnaBridge	163:e59c8e839560	5760	((__PLLR__) << RCC_PLLCFGR_PLLR_Pos)))
AnnaBridge	156:ff21514d8981	5761	#else
AnnaBridge	156:ff21514d8981	5762	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
AnnaBridge	156:ff21514d8981	5763	* @note This function must be used only when the main PLL is disabled.
AnnaBridge	163:e59c8e839560	5764	* @param __RCC_PLLSource__ specifies the PLL entry clock source.
AnnaBridge	156:ff21514d8981	5765	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	5766	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
AnnaBridge	156:ff21514d8981	5767	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
AnnaBridge	156:ff21514d8981	5768	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
AnnaBridge	163:e59c8e839560	5769	* @param __PLLM__ specifies the division factor for PLL VCO input clock
AnnaBridge	156:ff21514d8981	5770	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
AnnaBridge	156:ff21514d8981	5771	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge	156:ff21514d8981	5772	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
AnnaBridge	156:ff21514d8981	5773	* of 2 MHz to limit PLL jitter.
AnnaBridge	163:e59c8e839560	5774	* @param __PLLN__ specifies the multiplication factor for PLL VCO output clock
AnnaBridge	156:ff21514d8981	5775	* This parameter must be a number between Min_Data = 50 and Max_Data = 432
AnnaBridge	156:ff21514d8981	5776	* Except for STM32F411xE devices where Min_Data = 192.
AnnaBridge	156:ff21514d8981	5777	* @note You have to set the PLLN parameter correctly to ensure that the VCO
AnnaBridge	156:ff21514d8981	5778	* output frequency is between 100 and 432 MHz, Except for STM32F411xE devices
AnnaBridge	156:ff21514d8981	5779	* where frequency is between 192 and 432 MHz.
AnnaBridge	163:e59c8e839560	5780	* @param __PLLP__ specifies the division factor for main system clock (SYSCLK)
AnnaBridge	156:ff21514d8981	5781	* This parameter must be a number in the range {2, 4, 6, or 8}.
AnnaBridge	156:ff21514d8981	5782	*
AnnaBridge	163:e59c8e839560	5783	* @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks
AnnaBridge	156:ff21514d8981	5784	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	156:ff21514d8981	5785	* @note If the USB OTG FS is used in your application, you have to set the
AnnaBridge	156:ff21514d8981	5786	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
AnnaBridge	156:ff21514d8981	5787	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
AnnaBridge	156:ff21514d8981	5788	* correctly.
AnnaBridge	156:ff21514d8981	5789	*
AnnaBridge	156:ff21514d8981	5790	*/
AnnaBridge	156:ff21514d8981	5791	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
AnnaBridge	156:ff21514d8981	5792	(RCC->PLLCFGR = (0x20000000U \| (__RCC_PLLSource__) \| (__PLLM__)\| \
AnnaBridge	163:e59c8e839560	5793	((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) \| \
AnnaBridge	163:e59c8e839560	5794	((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) \| \
AnnaBridge	163:e59c8e839560	5795	((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)))
AnnaBridge	156:ff21514d8981	5796	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
AnnaBridge	156:ff21514d8981	5797	/----------------------------------------------------------------------------/
AnnaBridge	156:ff21514d8981	5798
AnnaBridge	156:ff21514d8981	5799	/----------------------------PLLI2S Configuration ---------------------------/
AnnaBridge	156:ff21514d8981	5800	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
AnnaBridge	156:ff21514d8981	5801	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
AnnaBridge	156:ff21514d8981	5802	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
AnnaBridge	156:ff21514d8981	5803	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	156:ff21514d8981	5804	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5805
AnnaBridge	156:ff21514d8981	5806	/** @brief Macros to enable or disable the PLLI2S.
AnnaBridge	156:ff21514d8981	5807	* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	156:ff21514d8981	5808	*/
AnnaBridge	156:ff21514d8981	5809	#define __HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = ENABLE)
AnnaBridge	156:ff21514d8981	5810	#define __HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = DISABLE)
AnnaBridge	156:ff21514d8981	5811
AnnaBridge	156:ff21514d8981	5812	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
AnnaBridge	156:ff21514d8981	5813	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
AnnaBridge	156:ff21514d8981	5814	STM32F412Rx \|\| STM32F412Cx */
AnnaBridge	156:ff21514d8981	5815	#if defined(STM32F446xx)
AnnaBridge	156:ff21514d8981	5816	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
AnnaBridge	156:ff21514d8981	5817	* @note This macro must be used only when the PLLI2S is disabled.
AnnaBridge	156:ff21514d8981	5818	* @note PLLI2S clock source is common with the main PLL (configured in
AnnaBridge	156:ff21514d8981	5819	* HAL_RCC_ClockConfig() API).
AnnaBridge	163:e59c8e839560	5820	* @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
AnnaBridge	156:ff21514d8981	5821	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
AnnaBridge	156:ff21514d8981	5822	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
AnnaBridge	156:ff21514d8981	5823	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
AnnaBridge	156:ff21514d8981	5824	* of 1 MHz to limit PLLI2S jitter.
AnnaBridge	156:ff21514d8981	5825	*
AnnaBridge	163:e59c8e839560	5826	* @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
AnnaBridge	156:ff21514d8981	5827	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	156:ff21514d8981	5828	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
AnnaBridge	156:ff21514d8981	5829	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
AnnaBridge	156:ff21514d8981	5830	*
AnnaBridge	163:e59c8e839560	5831	* @param __PLLI2SP__ specifies division factor for SPDIFRX Clock.
AnnaBridge	156:ff21514d8981	5832	* This parameter must be a number in the range {2, 4, 6, or 8}.
AnnaBridge	156:ff21514d8981	5833	* @note the PLLI2SP parameter is only available with STM32F446xx Devices
AnnaBridge	156:ff21514d8981	5834	*
AnnaBridge	163:e59c8e839560	5835	* @param __PLLI2SR__ specifies the division factor for I2S clock
AnnaBridge	156:ff21514d8981	5836	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	156:ff21514d8981	5837	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
AnnaBridge	156:ff21514d8981	5838	* on the I2S clock frequency.
AnnaBridge	156:ff21514d8981	5839	*
AnnaBridge	163:e59c8e839560	5840	* @param __PLLI2SQ__ specifies the division factor for SAI clock
AnnaBridge	156:ff21514d8981	5841	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	156:ff21514d8981	5842	*/
AnnaBridge	156:ff21514d8981	5843	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
AnnaBridge	156:ff21514d8981	5844	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
AnnaBridge	163:e59c8e839560	5845	((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) \|\
AnnaBridge	163:e59c8e839560	5846	((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) \|\
AnnaBridge	163:e59c8e839560	5847	((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) \|\
AnnaBridge	163:e59c8e839560	5848	((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
AnnaBridge	156:ff21514d8981	5849	#elif defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
AnnaBridge	156:ff21514d8981	5850	defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	5851	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
AnnaBridge	156:ff21514d8981	5852	* @note This macro must be used only when the PLLI2S is disabled.
AnnaBridge	156:ff21514d8981	5853	* @note PLLI2S clock source is common with the main PLL (configured in
AnnaBridge	156:ff21514d8981	5854	* HAL_RCC_ClockConfig() API).
AnnaBridge	163:e59c8e839560	5855	* @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
AnnaBridge	156:ff21514d8981	5856	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
AnnaBridge	156:ff21514d8981	5857	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
AnnaBridge	156:ff21514d8981	5858	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
AnnaBridge	156:ff21514d8981	5859	* of 1 MHz to limit PLLI2S jitter.
AnnaBridge	156:ff21514d8981	5860	*
AnnaBridge	163:e59c8e839560	5861	* @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
AnnaBridge	156:ff21514d8981	5862	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	156:ff21514d8981	5863	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
AnnaBridge	156:ff21514d8981	5864	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
AnnaBridge	156:ff21514d8981	5865	*
AnnaBridge	163:e59c8e839560	5866	* @param __PLLI2SR__ specifies the division factor for I2S clock
AnnaBridge	156:ff21514d8981	5867	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	156:ff21514d8981	5868	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
AnnaBridge	156:ff21514d8981	5869	* on the I2S clock frequency.
AnnaBridge	156:ff21514d8981	5870	*
AnnaBridge	163:e59c8e839560	5871	* @param __PLLI2SQ__ specifies the division factor for SAI clock
AnnaBridge	156:ff21514d8981	5872	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	156:ff21514d8981	5873	*/
AnnaBridge	156:ff21514d8981	5874	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \
AnnaBridge	156:ff21514d8981	5875	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
AnnaBridge	163:e59c8e839560	5876	((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) \|\
AnnaBridge	163:e59c8e839560	5877	((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) \|\
AnnaBridge	163:e59c8e839560	5878	((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
AnnaBridge	156:ff21514d8981	5879	#else
AnnaBridge	156:ff21514d8981	5880	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
AnnaBridge	156:ff21514d8981	5881	* @note This macro must be used only when the PLLI2S is disabled.
AnnaBridge	156:ff21514d8981	5882	* @note PLLI2S clock source is common with the main PLL (configured in
AnnaBridge	156:ff21514d8981	5883	* HAL_RCC_ClockConfig() API).
AnnaBridge	163:e59c8e839560	5884	* @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
AnnaBridge	156:ff21514d8981	5885	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	156:ff21514d8981	5886	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
AnnaBridge	156:ff21514d8981	5887	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
AnnaBridge	156:ff21514d8981	5888	*
AnnaBridge	163:e59c8e839560	5889	* @param __PLLI2SR__ specifies the division factor for I2S clock
AnnaBridge	156:ff21514d8981	5890	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	156:ff21514d8981	5891	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
AnnaBridge	156:ff21514d8981	5892	* on the I2S clock frequency.
AnnaBridge	156:ff21514d8981	5893	*
AnnaBridge	156:ff21514d8981	5894	*/
AnnaBridge	156:ff21514d8981	5895	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
AnnaBridge	163:e59c8e839560	5896	(RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) \|\
AnnaBridge	163:e59c8e839560	5897	((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
AnnaBridge	156:ff21514d8981	5898	#endif /* STM32F446xx */
AnnaBridge	156:ff21514d8981	5899
AnnaBridge	156:ff21514d8981	5900	#if defined(STM32F411xE)
AnnaBridge	156:ff21514d8981	5901	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
AnnaBridge	156:ff21514d8981	5902	* @note This macro must be used only when the PLLI2S is disabled.
AnnaBridge	156:ff21514d8981	5903	* @note This macro must be used only when the PLLI2S is disabled.
AnnaBridge	156:ff21514d8981	5904	* @note PLLI2S clock source is common with the main PLL (configured in
AnnaBridge	156:ff21514d8981	5905	* HAL_RCC_ClockConfig() API).
AnnaBridge	163:e59c8e839560	5906	* @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
AnnaBridge	156:ff21514d8981	5907	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
AnnaBridge	156:ff21514d8981	5908	* @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices
AnnaBridge	156:ff21514d8981	5909	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
AnnaBridge	156:ff21514d8981	5910	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
AnnaBridge	156:ff21514d8981	5911	* of 2 MHz to limit PLLI2S jitter.
AnnaBridge	163:e59c8e839560	5912	* @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
AnnaBridge	156:ff21514d8981	5913	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
AnnaBridge	156:ff21514d8981	5914	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
AnnaBridge	156:ff21514d8981	5915	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
AnnaBridge	163:e59c8e839560	5916	* @param __PLLI2SR__ specifies the division factor for I2S clock
AnnaBridge	156:ff21514d8981	5917	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	156:ff21514d8981	5918	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
AnnaBridge	156:ff21514d8981	5919	* on the I2S clock frequency.
AnnaBridge	156:ff21514d8981	5920	*/
AnnaBridge	156:ff21514d8981	5921	#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
AnnaBridge	163:e59c8e839560	5922	((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) \|\
AnnaBridge	163:e59c8e839560	5923	((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
AnnaBridge	156:ff21514d8981	5924	#endif /* STM32F411xE */
AnnaBridge	156:ff21514d8981	5925
AnnaBridge	156:ff21514d8981	5926	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	5927	/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
AnnaBridge	156:ff21514d8981	5928	* @note This macro must be used only when the PLLI2S is disabled.
AnnaBridge	156:ff21514d8981	5929	* @note PLLI2S clock source is common with the main PLL (configured in
AnnaBridge	156:ff21514d8981	5930	* HAL_RCC_ClockConfig() API)
AnnaBridge	163:e59c8e839560	5931	* @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock.
AnnaBridge	156:ff21514d8981	5932	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	156:ff21514d8981	5933	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
AnnaBridge	156:ff21514d8981	5934	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
AnnaBridge	163:e59c8e839560	5935	* @param __PLLI2SQ__ specifies the division factor for SAI1 clock.
AnnaBridge	156:ff21514d8981	5936	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	156:ff21514d8981	5937	* @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx
AnnaBridge	156:ff21514d8981	5938	* Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
AnnaBridge	163:e59c8e839560	5939	* @param __PLLI2SR__ specifies the division factor for I2S clock
AnnaBridge	156:ff21514d8981	5940	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	156:ff21514d8981	5941	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
AnnaBridge	156:ff21514d8981	5942	* on the I2S clock frequency.
AnnaBridge	156:ff21514d8981	5943	*/
AnnaBridge	156:ff21514d8981	5944	#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U) \|\
AnnaBridge	156:ff21514d8981	5945	((__PLLI2SQ__) << 24U) \|\
AnnaBridge	156:ff21514d8981	5946	((__PLLI2SR__) << 28U))
AnnaBridge	156:ff21514d8981	5947	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	5948	/----------------------------------------------------------------------------/
AnnaBridge	156:ff21514d8981	5949
AnnaBridge	156:ff21514d8981	5950	/------------------------------ PLLSAI Configuration ------------------------/
AnnaBridge	156:ff21514d8981	5951	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	5952	/** @brief Macros to Enable or Disable the PLLISAI.
AnnaBridge	156:ff21514d8981	5953	* @note The PLLSAI is only available with STM32F429x/439x Devices.
AnnaBridge	156:ff21514d8981	5954	* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	156:ff21514d8981	5955	*/
AnnaBridge	156:ff21514d8981	5956	#define __HAL_RCC_PLLSAI_ENABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = ENABLE)
AnnaBridge	156:ff21514d8981	5957	#define __HAL_RCC_PLLSAI_DISABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = DISABLE)
AnnaBridge	156:ff21514d8981	5958
AnnaBridge	156:ff21514d8981	5959	#if defined(STM32F446xx)
AnnaBridge	156:ff21514d8981	5960	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
AnnaBridge	156:ff21514d8981	5961	*
AnnaBridge	163:e59c8e839560	5962	* @param __PLLSAIM__ specifies the division factor for PLLSAI VCO input clock
AnnaBridge	156:ff21514d8981	5963	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
AnnaBridge	156:ff21514d8981	5964	* @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
AnnaBridge	156:ff21514d8981	5965	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
AnnaBridge	156:ff21514d8981	5966	* of 1 MHz to limit PLLI2S jitter.
AnnaBridge	156:ff21514d8981	5967	* @note The PLLSAIM parameter is only used with STM32F446xx Devices
AnnaBridge	156:ff21514d8981	5968	*
AnnaBridge	163:e59c8e839560	5969	* @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
AnnaBridge	156:ff21514d8981	5970	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	156:ff21514d8981	5971	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
AnnaBridge	156:ff21514d8981	5972	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
AnnaBridge	156:ff21514d8981	5973	*
AnnaBridge	163:e59c8e839560	5974	* @param __PLLSAIP__ specifies division factor for OTG FS, SDIO and RNG clocks.
AnnaBridge	156:ff21514d8981	5975	* This parameter must be a number in the range {2, 4, 6, or 8}.
AnnaBridge	156:ff21514d8981	5976	* @note the PLLSAIP parameter is only available with STM32F446xx Devices
AnnaBridge	156:ff21514d8981	5977	*
AnnaBridge	163:e59c8e839560	5978	* @param __PLLSAIQ__ specifies the division factor for SAI clock
AnnaBridge	156:ff21514d8981	5979	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	156:ff21514d8981	5980	*
AnnaBridge	163:e59c8e839560	5981	* @param __PLLSAIR__ specifies the division factor for LTDC clock
AnnaBridge	156:ff21514d8981	5982	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	156:ff21514d8981	5983	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
AnnaBridge	156:ff21514d8981	5984	*/
AnnaBridge	156:ff21514d8981	5985	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
AnnaBridge	156:ff21514d8981	5986	(RCC->PLLSAICFGR = ((__PLLSAIM__) \| \
AnnaBridge	163:e59c8e839560	5987	((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) \| \
AnnaBridge	163:e59c8e839560	5988	((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) \| \
AnnaBridge	163:e59c8e839560	5989	((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)))
AnnaBridge	156:ff21514d8981	5990	#endif /* STM32F446xx */
AnnaBridge	156:ff21514d8981	5991
AnnaBridge	156:ff21514d8981	5992	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	5993	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
AnnaBridge	156:ff21514d8981	5994	*
AnnaBridge	163:e59c8e839560	5995	* @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
AnnaBridge	156:ff21514d8981	5996	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	156:ff21514d8981	5997	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
AnnaBridge	156:ff21514d8981	5998	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
AnnaBridge	156:ff21514d8981	5999	*
AnnaBridge	163:e59c8e839560	6000	* @param __PLLSAIP__ specifies division factor for SDIO and CLK48 clocks.
AnnaBridge	156:ff21514d8981	6001	* This parameter must be a number in the range {2, 4, 6, or 8}.
AnnaBridge	156:ff21514d8981	6002	*
AnnaBridge	163:e59c8e839560	6003	* @param __PLLSAIQ__ specifies the division factor for SAI clock
AnnaBridge	156:ff21514d8981	6004	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	156:ff21514d8981	6005	*
AnnaBridge	163:e59c8e839560	6006	* @param __PLLSAIR__ specifies the division factor for LTDC clock
AnnaBridge	156:ff21514d8981	6007	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	156:ff21514d8981	6008	*/
AnnaBridge	156:ff21514d8981	6009	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
AnnaBridge	163:e59c8e839560	6010	(RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) \|\
AnnaBridge	163:e59c8e839560	6011	((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) \|\
AnnaBridge	163:e59c8e839560	6012	((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) \|\
AnnaBridge	163:e59c8e839560	6013	((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))
AnnaBridge	156:ff21514d8981	6014	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	6015
AnnaBridge	156:ff21514d8981	6016	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
AnnaBridge	156:ff21514d8981	6017	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
AnnaBridge	156:ff21514d8981	6018	*
AnnaBridge	163:e59c8e839560	6019	* @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
AnnaBridge	156:ff21514d8981	6020	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
AnnaBridge	156:ff21514d8981	6021	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
AnnaBridge	156:ff21514d8981	6022	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
AnnaBridge	156:ff21514d8981	6023	*
AnnaBridge	163:e59c8e839560	6024	* @param __PLLSAIQ__ specifies the division factor for SAI clock
AnnaBridge	156:ff21514d8981	6025	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	156:ff21514d8981	6026	*
AnnaBridge	163:e59c8e839560	6027	* @param __PLLSAIR__ specifies the division factor for LTDC clock
AnnaBridge	156:ff21514d8981	6028	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	156:ff21514d8981	6029	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
AnnaBridge	156:ff21514d8981	6030	*/
AnnaBridge	156:ff21514d8981	6031	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
AnnaBridge	163:e59c8e839560	6032	(RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) \| \
AnnaBridge	163:e59c8e839560	6033	((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) \| \
AnnaBridge	163:e59c8e839560	6034	((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))
AnnaBridge	156:ff21514d8981	6035	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
AnnaBridge	156:ff21514d8981	6036
AnnaBridge	156:ff21514d8981	6037	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	6038	/----------------------------------------------------------------------------/
AnnaBridge	156:ff21514d8981	6039
AnnaBridge	156:ff21514d8981	6040	/------------------- PLLSAI/PLLI2S Dividers Configuration -------------------/
AnnaBridge	156:ff21514d8981	6041	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	6042	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
AnnaBridge	156:ff21514d8981	6043	* @note This function must be called before enabling the PLLI2S.
AnnaBridge	163:e59c8e839560	6044	* @param __PLLI2SDivR__ specifies the PLLI2S division factor for SAI1 clock.
AnnaBridge	156:ff21514d8981	6045	* This parameter must be a number between 1 and 32.
AnnaBridge	156:ff21514d8981	6046	* SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__
AnnaBridge	156:ff21514d8981	6047	*/
AnnaBridge	156:ff21514d8981	6048	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U))
AnnaBridge	156:ff21514d8981	6049
AnnaBridge	156:ff21514d8981	6050	/** @brief Macro to configure the SAI clock Divider coming from PLL.
AnnaBridge	163:e59c8e839560	6051	* @param __PLLDivR__ specifies the PLL division factor for SAI1 clock.
AnnaBridge	156:ff21514d8981	6052	* This parameter must be a number between 1 and 32.
AnnaBridge	156:ff21514d8981	6053	* SAI1 clock frequency = f(PLLR) / __PLLDivR__
AnnaBridge	156:ff21514d8981	6054	*/
AnnaBridge	156:ff21514d8981	6055	#define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U))
AnnaBridge	156:ff21514d8981	6056	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	6057
AnnaBridge	156:ff21514d8981	6058	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\|\
AnnaBridge	156:ff21514d8981	6059	defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	6060	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
AnnaBridge	156:ff21514d8981	6061	* @note This function must be called before enabling the PLLI2S.
AnnaBridge	163:e59c8e839560	6062	* @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock.
AnnaBridge	156:ff21514d8981	6063	* This parameter must be a number between 1 and 32.
AnnaBridge	156:ff21514d8981	6064	* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
AnnaBridge	156:ff21514d8981	6065	*/
AnnaBridge	156:ff21514d8981	6066	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U))
AnnaBridge	156:ff21514d8981	6067
AnnaBridge	156:ff21514d8981	6068	/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
AnnaBridge	156:ff21514d8981	6069	* @note This function must be called before enabling the PLLSAI.
AnnaBridge	163:e59c8e839560	6070	* @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock .
AnnaBridge	156:ff21514d8981	6071	* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
AnnaBridge	156:ff21514d8981	6072	* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
AnnaBridge	156:ff21514d8981	6073	*/
AnnaBridge	156:ff21514d8981	6074	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U))
AnnaBridge	156:ff21514d8981	6075	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	6076
AnnaBridge	156:ff21514d8981	6077	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	6078	/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
AnnaBridge	156:ff21514d8981	6079	*
AnnaBridge	156:ff21514d8981	6080	* @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
AnnaBridge	156:ff21514d8981	6081	* @note This function must be called before enabling the PLLSAI.
AnnaBridge	163:e59c8e839560	6082	* @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock .
AnnaBridge	156:ff21514d8981	6083	* This parameter must be a number between Min_Data = 2 and Max_Data = 16.
AnnaBridge	156:ff21514d8981	6084	* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
AnnaBridge	156:ff21514d8981	6085	*/
AnnaBridge	156:ff21514d8981	6086	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
AnnaBridge	156:ff21514d8981	6087	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	6088	/----------------------------------------------------------------------------/
AnnaBridge	156:ff21514d8981	6089
AnnaBridge	156:ff21514d8981	6090	/------------------------- Peripheral Clock selection -----------------------/
AnnaBridge	156:ff21514d8981	6091	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
AnnaBridge	156:ff21514d8981	6092	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
AnnaBridge	156:ff21514d8981	6093	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F469xx) \|\|\
AnnaBridge	156:ff21514d8981	6094	defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	6095	/** @brief Macro to configure the I2S clock source (I2SCLK).
AnnaBridge	156:ff21514d8981	6096	* @note This function must be called before enabling the I2S APB clock.
AnnaBridge	163:e59c8e839560	6097	* @param __SOURCE__ specifies the I2S clock source.
AnnaBridge	156:ff21514d8981	6098	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6099	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
AnnaBridge	156:ff21514d8981	6100	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
AnnaBridge	156:ff21514d8981	6101	* used as I2S clock source.
AnnaBridge	156:ff21514d8981	6102	*/
AnnaBridge	156:ff21514d8981	6103	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
AnnaBridge	156:ff21514d8981	6104
AnnaBridge	156:ff21514d8981	6105
AnnaBridge	156:ff21514d8981	6106	/** @brief Macro to get the I2S clock source (I2SCLK).
AnnaBridge	156:ff21514d8981	6107	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6108	* @arg @ref RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
AnnaBridge	156:ff21514d8981	6109	* @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
AnnaBridge	156:ff21514d8981	6110	* used as I2S clock source
AnnaBridge	156:ff21514d8981	6111	*/
AnnaBridge	156:ff21514d8981	6112	#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
AnnaBridge	156:ff21514d8981	6113	#endif /* STM32F40xxx \|\| STM32F41xxx \|\| STM32F42xxx \|\| STM32F43xxx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	6114
AnnaBridge	156:ff21514d8981	6115	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	6116
AnnaBridge	156:ff21514d8981	6117	/** @brief Macro to configure SAI1BlockA clock source selection.
AnnaBridge	156:ff21514d8981	6118	* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
AnnaBridge	156:ff21514d8981	6119	* @note This function must be called before enabling PLLSAI, PLLI2S and
AnnaBridge	156:ff21514d8981	6120	* the SAI clock.
AnnaBridge	163:e59c8e839560	6121	* @param __SOURCE__ specifies the SAI Block A clock source.
AnnaBridge	156:ff21514d8981	6122	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6123	* @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
AnnaBridge	156:ff21514d8981	6124	* as SAI1 Block A clock.
AnnaBridge	156:ff21514d8981	6125	* @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
AnnaBridge	156:ff21514d8981	6126	* as SAI1 Block A clock.
AnnaBridge	156:ff21514d8981	6127	* @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
AnnaBridge	156:ff21514d8981	6128	* used as SAI1 Block A clock.
AnnaBridge	156:ff21514d8981	6129	*/
AnnaBridge	156:ff21514d8981	6130	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
AnnaBridge	156:ff21514d8981	6131
AnnaBridge	156:ff21514d8981	6132	/** @brief Macro to configure SAI1BlockB clock source selection.
AnnaBridge	156:ff21514d8981	6133	* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
AnnaBridge	156:ff21514d8981	6134	* @note This function must be called before enabling PLLSAI, PLLI2S and
AnnaBridge	156:ff21514d8981	6135	* the SAI clock.
AnnaBridge	163:e59c8e839560	6136	* @param __SOURCE__ specifies the SAI Block B clock source.
AnnaBridge	156:ff21514d8981	6137	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6138	* @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
AnnaBridge	156:ff21514d8981	6139	* as SAI1 Block B clock.
AnnaBridge	156:ff21514d8981	6140	* @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
AnnaBridge	156:ff21514d8981	6141	* as SAI1 Block B clock.
AnnaBridge	156:ff21514d8981	6142	* @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
AnnaBridge	156:ff21514d8981	6143	* used as SAI1 Block B clock.
AnnaBridge	156:ff21514d8981	6144	*/
AnnaBridge	156:ff21514d8981	6145	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
AnnaBridge	156:ff21514d8981	6146	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	6147
AnnaBridge	156:ff21514d8981	6148	#if defined(STM32F446xx)
AnnaBridge	156:ff21514d8981	6149	/** @brief Macro to configure SAI1 clock source selection.
AnnaBridge	156:ff21514d8981	6150	* @note This configuration is only available with STM32F446xx Devices.
AnnaBridge	156:ff21514d8981	6151	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
AnnaBridge	156:ff21514d8981	6152	* the SAI clock.
AnnaBridge	163:e59c8e839560	6153	* @param __SOURCE__ specifies the SAI1 clock source.
AnnaBridge	156:ff21514d8981	6154	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6155	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
AnnaBridge	156:ff21514d8981	6156	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
AnnaBridge	156:ff21514d8981	6157	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
AnnaBridge	156:ff21514d8981	6158	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
AnnaBridge	156:ff21514d8981	6159	*/
AnnaBridge	156:ff21514d8981	6160	#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
AnnaBridge	156:ff21514d8981	6161
AnnaBridge	156:ff21514d8981	6162	/** @brief Macro to Get SAI1 clock source selection.
AnnaBridge	156:ff21514d8981	6163	* @note This configuration is only available with STM32F446xx Devices.
AnnaBridge	156:ff21514d8981	6164	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6165	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
AnnaBridge	156:ff21514d8981	6166	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
AnnaBridge	156:ff21514d8981	6167	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
AnnaBridge	156:ff21514d8981	6168	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
AnnaBridge	156:ff21514d8981	6169	*/
AnnaBridge	156:ff21514d8981	6170	#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
AnnaBridge	156:ff21514d8981	6171
AnnaBridge	156:ff21514d8981	6172	/** @brief Macro to configure SAI2 clock source selection.
AnnaBridge	156:ff21514d8981	6173	* @note This configuration is only available with STM32F446xx Devices.
AnnaBridge	156:ff21514d8981	6174	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
AnnaBridge	156:ff21514d8981	6175	* the SAI clock.
AnnaBridge	163:e59c8e839560	6176	* @param __SOURCE__ specifies the SAI2 clock source.
AnnaBridge	156:ff21514d8981	6177	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6178	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
AnnaBridge	156:ff21514d8981	6179	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
AnnaBridge	156:ff21514d8981	6180	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
AnnaBridge	156:ff21514d8981	6181	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
AnnaBridge	156:ff21514d8981	6182	*/
AnnaBridge	156:ff21514d8981	6183	#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
AnnaBridge	156:ff21514d8981	6184
AnnaBridge	156:ff21514d8981	6185	/** @brief Macro to Get SAI2 clock source selection.
AnnaBridge	156:ff21514d8981	6186	* @note This configuration is only available with STM32F446xx Devices.
AnnaBridge	156:ff21514d8981	6187	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6188	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
AnnaBridge	156:ff21514d8981	6189	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
AnnaBridge	156:ff21514d8981	6190	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
AnnaBridge	156:ff21514d8981	6191	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
AnnaBridge	156:ff21514d8981	6192	*/
AnnaBridge	156:ff21514d8981	6193	#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
AnnaBridge	156:ff21514d8981	6194
AnnaBridge	156:ff21514d8981	6195	/** @brief Macro to configure I2S APB1 clock source selection.
AnnaBridge	156:ff21514d8981	6196	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
AnnaBridge	163:e59c8e839560	6197	* @param __SOURCE__ specifies the I2S APB1 clock source.
AnnaBridge	156:ff21514d8981	6198	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6199	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
AnnaBridge	156:ff21514d8981	6200	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
AnnaBridge	156:ff21514d8981	6201	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.
AnnaBridge	156:ff21514d8981	6202	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	156:ff21514d8981	6203	*/
AnnaBridge	156:ff21514d8981	6204	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
AnnaBridge	156:ff21514d8981	6205
AnnaBridge	156:ff21514d8981	6206	/** @brief Macro to Get I2S APB1 clock source selection.
AnnaBridge	156:ff21514d8981	6207	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6208	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
AnnaBridge	156:ff21514d8981	6209	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
AnnaBridge	156:ff21514d8981	6210	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.
AnnaBridge	156:ff21514d8981	6211	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	156:ff21514d8981	6212	*/
AnnaBridge	156:ff21514d8981	6213	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
AnnaBridge	156:ff21514d8981	6214
AnnaBridge	156:ff21514d8981	6215	/** @brief Macro to configure I2S APB2 clock source selection.
AnnaBridge	156:ff21514d8981	6216	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
AnnaBridge	163:e59c8e839560	6217	* @param __SOURCE__ specifies the SAI Block A clock source.
AnnaBridge	156:ff21514d8981	6218	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6219	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
AnnaBridge	156:ff21514d8981	6220	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
AnnaBridge	156:ff21514d8981	6221	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.
AnnaBridge	156:ff21514d8981	6222	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	156:ff21514d8981	6223	*/
AnnaBridge	156:ff21514d8981	6224	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
AnnaBridge	156:ff21514d8981	6225
AnnaBridge	156:ff21514d8981	6226	/** @brief Macro to Get I2S APB2 clock source selection.
AnnaBridge	156:ff21514d8981	6227	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6228	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
AnnaBridge	156:ff21514d8981	6229	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
AnnaBridge	156:ff21514d8981	6230	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.
AnnaBridge	156:ff21514d8981	6231	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	156:ff21514d8981	6232	*/
AnnaBridge	156:ff21514d8981	6233	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
AnnaBridge	156:ff21514d8981	6234
AnnaBridge	156:ff21514d8981	6235	/** @brief Macro to configure the CEC clock.
AnnaBridge	163:e59c8e839560	6236	* @param __SOURCE__ specifies the CEC clock source.
AnnaBridge	156:ff21514d8981	6237	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6238	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
AnnaBridge	156:ff21514d8981	6239	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
AnnaBridge	156:ff21514d8981	6240	*/
AnnaBridge	156:ff21514d8981	6241	#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
AnnaBridge	156:ff21514d8981	6242
AnnaBridge	156:ff21514d8981	6243	/** @brief Macro to Get the CEC clock.
AnnaBridge	156:ff21514d8981	6244	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6245	* @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
AnnaBridge	156:ff21514d8981	6246	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
AnnaBridge	156:ff21514d8981	6247	*/
AnnaBridge	156:ff21514d8981	6248	#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
AnnaBridge	156:ff21514d8981	6249
AnnaBridge	156:ff21514d8981	6250	/** @brief Macro to configure the FMPI2C1 clock.
AnnaBridge	163:e59c8e839560	6251	* @param __SOURCE__ specifies the FMPI2C1 clock source.
AnnaBridge	156:ff21514d8981	6252	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6253	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
AnnaBridge	156:ff21514d8981	6254	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
AnnaBridge	156:ff21514d8981	6255	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
AnnaBridge	156:ff21514d8981	6256	*/
AnnaBridge	156:ff21514d8981	6257	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
AnnaBridge	156:ff21514d8981	6258
AnnaBridge	156:ff21514d8981	6259	/** @brief Macro to Get the FMPI2C1 clock.
AnnaBridge	156:ff21514d8981	6260	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6261	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
AnnaBridge	156:ff21514d8981	6262	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
AnnaBridge	156:ff21514d8981	6263	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
AnnaBridge	156:ff21514d8981	6264	*/
AnnaBridge	156:ff21514d8981	6265	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
AnnaBridge	156:ff21514d8981	6266
AnnaBridge	156:ff21514d8981	6267	/** @brief Macro to configure the CLK48 clock.
AnnaBridge	163:e59c8e839560	6268	* @param __SOURCE__ specifies the CLK48 clock source.
AnnaBridge	156:ff21514d8981	6269	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6270	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
AnnaBridge	156:ff21514d8981	6271	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
AnnaBridge	156:ff21514d8981	6272	*/
AnnaBridge	156:ff21514d8981	6273	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
AnnaBridge	156:ff21514d8981	6274
AnnaBridge	156:ff21514d8981	6275	/** @brief Macro to Get the CLK48 clock.
AnnaBridge	156:ff21514d8981	6276	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6277	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
AnnaBridge	156:ff21514d8981	6278	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
AnnaBridge	156:ff21514d8981	6279	*/
AnnaBridge	156:ff21514d8981	6280	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
AnnaBridge	156:ff21514d8981	6281
AnnaBridge	156:ff21514d8981	6282	/** @brief Macro to configure the SDIO clock.
AnnaBridge	163:e59c8e839560	6283	* @param __SOURCE__ specifies the SDIO clock source.
AnnaBridge	156:ff21514d8981	6284	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6285	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
AnnaBridge	156:ff21514d8981	6286	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
AnnaBridge	156:ff21514d8981	6287	*/
AnnaBridge	156:ff21514d8981	6288	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
AnnaBridge	156:ff21514d8981	6289
AnnaBridge	156:ff21514d8981	6290	/** @brief Macro to Get the SDIO clock.
AnnaBridge	156:ff21514d8981	6291	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6292	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
AnnaBridge	156:ff21514d8981	6293	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
AnnaBridge	156:ff21514d8981	6294	*/
AnnaBridge	156:ff21514d8981	6295	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
AnnaBridge	156:ff21514d8981	6296
AnnaBridge	156:ff21514d8981	6297	/** @brief Macro to configure the SPDIFRX clock.
AnnaBridge	163:e59c8e839560	6298	* @param __SOURCE__ specifies the SPDIFRX clock source.
AnnaBridge	156:ff21514d8981	6299	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6300	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
AnnaBridge	156:ff21514d8981	6301	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
AnnaBridge	156:ff21514d8981	6302	*/
AnnaBridge	156:ff21514d8981	6303	#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
AnnaBridge	156:ff21514d8981	6304
AnnaBridge	156:ff21514d8981	6305	/** @brief Macro to Get the SPDIFRX clock.
AnnaBridge	156:ff21514d8981	6306	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6307	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
AnnaBridge	156:ff21514d8981	6308	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
AnnaBridge	156:ff21514d8981	6309	*/
AnnaBridge	156:ff21514d8981	6310	#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
AnnaBridge	156:ff21514d8981	6311	#endif /* STM32F446xx */
AnnaBridge	156:ff21514d8981	6312
AnnaBridge	156:ff21514d8981	6313	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	6314
AnnaBridge	156:ff21514d8981	6315	/** @brief Macro to configure the CLK48 clock.
AnnaBridge	163:e59c8e839560	6316	* @param __SOURCE__ specifies the CLK48 clock source.
AnnaBridge	156:ff21514d8981	6317	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6318	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
AnnaBridge	156:ff21514d8981	6319	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
AnnaBridge	156:ff21514d8981	6320	*/
AnnaBridge	156:ff21514d8981	6321	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
AnnaBridge	156:ff21514d8981	6322
AnnaBridge	156:ff21514d8981	6323	/** @brief Macro to Get the CLK48 clock.
AnnaBridge	156:ff21514d8981	6324	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6325	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
AnnaBridge	156:ff21514d8981	6326	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
AnnaBridge	156:ff21514d8981	6327	*/
AnnaBridge	156:ff21514d8981	6328	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
AnnaBridge	156:ff21514d8981	6329
AnnaBridge	156:ff21514d8981	6330	/** @brief Macro to configure the SDIO clock.
AnnaBridge	163:e59c8e839560	6331	* @param __SOURCE__ specifies the SDIO clock source.
AnnaBridge	156:ff21514d8981	6332	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6333	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
AnnaBridge	156:ff21514d8981	6334	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
AnnaBridge	156:ff21514d8981	6335	*/
AnnaBridge	156:ff21514d8981	6336	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
AnnaBridge	156:ff21514d8981	6337
AnnaBridge	156:ff21514d8981	6338	/** @brief Macro to Get the SDIO clock.
AnnaBridge	156:ff21514d8981	6339	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6340	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
AnnaBridge	156:ff21514d8981	6341	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
AnnaBridge	156:ff21514d8981	6342	*/
AnnaBridge	156:ff21514d8981	6343	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))
AnnaBridge	156:ff21514d8981	6344
AnnaBridge	156:ff21514d8981	6345	/** @brief Macro to configure the DSI clock.
AnnaBridge	163:e59c8e839560	6346	* @param __SOURCE__ specifies the DSI clock source.
AnnaBridge	156:ff21514d8981	6347	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6348	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
AnnaBridge	156:ff21514d8981	6349	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
AnnaBridge	156:ff21514d8981	6350	*/
AnnaBridge	156:ff21514d8981	6351	#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))
AnnaBridge	156:ff21514d8981	6352
AnnaBridge	156:ff21514d8981	6353	/** @brief Macro to Get the DSI clock.
AnnaBridge	156:ff21514d8981	6354	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6355	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
AnnaBridge	156:ff21514d8981	6356	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
AnnaBridge	156:ff21514d8981	6357	*/
AnnaBridge	156:ff21514d8981	6358	#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))
AnnaBridge	156:ff21514d8981	6359
AnnaBridge	156:ff21514d8981	6360	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	6361
AnnaBridge	156:ff21514d8981	6362	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
AnnaBridge	156:ff21514d8981	6363	defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	6364	/** @brief Macro to configure the DFSDM1 clock.
AnnaBridge	163:e59c8e839560	6365	* @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
AnnaBridge	156:ff21514d8981	6366	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6367	* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
AnnaBridge	156:ff21514d8981	6368	* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
AnnaBridge	156:ff21514d8981	6369	* @retval None
AnnaBridge	156:ff21514d8981	6370	*/
AnnaBridge	156:ff21514d8981	6371	#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__))
AnnaBridge	156:ff21514d8981	6372
AnnaBridge	156:ff21514d8981	6373	/** @brief Macro to get the DFSDM1 clock source.
AnnaBridge	156:ff21514d8981	6374	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6375	* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
AnnaBridge	156:ff21514d8981	6376	* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
AnnaBridge	156:ff21514d8981	6377	*/
AnnaBridge	156:ff21514d8981	6378	#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
AnnaBridge	156:ff21514d8981	6379
AnnaBridge	156:ff21514d8981	6380	/** @brief Macro to configure DFSDM1 Audio clock source selection.
AnnaBridge	156:ff21514d8981	6381	* @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
AnnaBridge	156:ff21514d8981	6382	STM32F413xx/STM32F423xx Devices.
AnnaBridge	163:e59c8e839560	6383	* @param __SOURCE__ specifies the DFSDM1 Audio clock source.
AnnaBridge	156:ff21514d8981	6384	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6385	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
AnnaBridge	156:ff21514d8981	6386	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
AnnaBridge	156:ff21514d8981	6387	*/
AnnaBridge	156:ff21514d8981	6388	#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__)))
AnnaBridge	156:ff21514d8981	6389
AnnaBridge	156:ff21514d8981	6390	/** @brief Macro to Get DFSDM1 Audio clock source selection.
AnnaBridge	156:ff21514d8981	6391	* @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
AnnaBridge	156:ff21514d8981	6392	STM32F413xx/STM32F423xx Devices.
AnnaBridge	156:ff21514d8981	6393	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6394	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
AnnaBridge	156:ff21514d8981	6395	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
AnnaBridge	156:ff21514d8981	6396	*/
AnnaBridge	156:ff21514d8981	6397	#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL))
AnnaBridge	156:ff21514d8981	6398
AnnaBridge	156:ff21514d8981	6399	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	6400	/** @brief Macro to configure the DFSDM2 clock.
AnnaBridge	163:e59c8e839560	6401	* @param __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source.
AnnaBridge	156:ff21514d8981	6402	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6403	* @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
AnnaBridge	156:ff21514d8981	6404	* @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock.
AnnaBridge	156:ff21514d8981	6405	* @retval None
AnnaBridge	156:ff21514d8981	6406	*/
AnnaBridge	156:ff21514d8981	6407	#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__))
AnnaBridge	156:ff21514d8981	6408
AnnaBridge	156:ff21514d8981	6409	/** @brief Macro to get the DFSDM2 clock source.
AnnaBridge	156:ff21514d8981	6410	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6411	* @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
AnnaBridge	156:ff21514d8981	6412	* @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock.
AnnaBridge	156:ff21514d8981	6413	*/
AnnaBridge	156:ff21514d8981	6414	#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
AnnaBridge	156:ff21514d8981	6415
AnnaBridge	156:ff21514d8981	6416	/** @brief Macro to configure DFSDM1 Audio clock source selection.
AnnaBridge	156:ff21514d8981	6417	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
AnnaBridge	163:e59c8e839560	6418	* @param __SOURCE__ specifies the DFSDM2 Audio clock source.
AnnaBridge	156:ff21514d8981	6419	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6420	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
AnnaBridge	156:ff21514d8981	6421	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
AnnaBridge	156:ff21514d8981	6422	*/
AnnaBridge	156:ff21514d8981	6423	#define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__)))
AnnaBridge	156:ff21514d8981	6424
AnnaBridge	156:ff21514d8981	6425	/** @brief Macro to Get DFSDM2 Audio clock source selection.
AnnaBridge	156:ff21514d8981	6426	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
AnnaBridge	156:ff21514d8981	6427	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6428	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
AnnaBridge	156:ff21514d8981	6429	* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
AnnaBridge	156:ff21514d8981	6430	*/
AnnaBridge	156:ff21514d8981	6431	#define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL))
AnnaBridge	156:ff21514d8981	6432
AnnaBridge	156:ff21514d8981	6433	/** @brief Macro to configure SAI1BlockA clock source selection.
AnnaBridge	156:ff21514d8981	6434	* @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.
AnnaBridge	156:ff21514d8981	6435	* @note This function must be called before enabling PLLSAI, PLLI2S and
AnnaBridge	156:ff21514d8981	6436	* the SAI clock.
AnnaBridge	163:e59c8e839560	6437	* @param __SOURCE__ specifies the SAI Block A clock source.
AnnaBridge	156:ff21514d8981	6438	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6439	* @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
AnnaBridge	156:ff21514d8981	6440	* @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
AnnaBridge	156:ff21514d8981	6441	* @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
AnnaBridge	156:ff21514d8981	6442	* @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	156:ff21514d8981	6443	*/
AnnaBridge	156:ff21514d8981	6444	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
AnnaBridge	156:ff21514d8981	6445
AnnaBridge	156:ff21514d8981	6446	/** @brief Macro to Get SAI1 BlockA clock source selection.
AnnaBridge	156:ff21514d8981	6447	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
AnnaBridge	156:ff21514d8981	6448	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6449	* @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
AnnaBridge	156:ff21514d8981	6450	* @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
AnnaBridge	156:ff21514d8981	6451	* @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
AnnaBridge	156:ff21514d8981	6452	* @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	156:ff21514d8981	6453	*/
AnnaBridge	156:ff21514d8981	6454	#define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC))
AnnaBridge	156:ff21514d8981	6455
AnnaBridge	156:ff21514d8981	6456	/** @brief Macro to configure SAI1 BlockB clock source selection.
AnnaBridge	156:ff21514d8981	6457	* @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.
AnnaBridge	156:ff21514d8981	6458	* @note This function must be called before enabling PLLSAI, PLLI2S and
AnnaBridge	156:ff21514d8981	6459	* the SAI clock.
AnnaBridge	163:e59c8e839560	6460	* @param __SOURCE__ specifies the SAI Block B clock source.
AnnaBridge	156:ff21514d8981	6461	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6462	* @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
AnnaBridge	156:ff21514d8981	6463	* @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
AnnaBridge	156:ff21514d8981	6464	* @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
AnnaBridge	156:ff21514d8981	6465	* @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	156:ff21514d8981	6466	*/
AnnaBridge	156:ff21514d8981	6467	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
AnnaBridge	156:ff21514d8981	6468
AnnaBridge	156:ff21514d8981	6469	/** @brief Macro to Get SAI1 BlockB clock source selection.
AnnaBridge	156:ff21514d8981	6470	* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
AnnaBridge	156:ff21514d8981	6471	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6472	* @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
AnnaBridge	156:ff21514d8981	6473	* @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
AnnaBridge	156:ff21514d8981	6474	* @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
AnnaBridge	156:ff21514d8981	6475	* @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	156:ff21514d8981	6476	*/
AnnaBridge	156:ff21514d8981	6477	#define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC))
AnnaBridge	156:ff21514d8981	6478
AnnaBridge	156:ff21514d8981	6479	/** @brief Macro to configure the LPTIM1 clock.
AnnaBridge	163:e59c8e839560	6480	* @param __SOURCE__ specifies the LPTIM1 clock source.
AnnaBridge	156:ff21514d8981	6481	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6482	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
AnnaBridge	156:ff21514d8981	6483	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
AnnaBridge	156:ff21514d8981	6484	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
AnnaBridge	156:ff21514d8981	6485	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
AnnaBridge	156:ff21514d8981	6486	*/
AnnaBridge	156:ff21514d8981	6487	#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
AnnaBridge	156:ff21514d8981	6488
AnnaBridge	156:ff21514d8981	6489	/** @brief Macro to Get the LPTIM1 clock.
AnnaBridge	156:ff21514d8981	6490	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6491	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
AnnaBridge	156:ff21514d8981	6492	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
AnnaBridge	156:ff21514d8981	6493	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
AnnaBridge	156:ff21514d8981	6494	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
AnnaBridge	156:ff21514d8981	6495	*/
AnnaBridge	156:ff21514d8981	6496	#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
AnnaBridge	156:ff21514d8981	6497	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	6498
AnnaBridge	156:ff21514d8981	6499	/** @brief Macro to configure I2S APB1 clock source selection.
AnnaBridge	163:e59c8e839560	6500	* @param __SOURCE__ specifies the I2S APB1 clock source.
AnnaBridge	156:ff21514d8981	6501	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6502	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
AnnaBridge	156:ff21514d8981	6503	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
AnnaBridge	156:ff21514d8981	6504	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
AnnaBridge	156:ff21514d8981	6505	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	156:ff21514d8981	6506	*/
AnnaBridge	156:ff21514d8981	6507	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
AnnaBridge	156:ff21514d8981	6508
AnnaBridge	156:ff21514d8981	6509	/** @brief Macro to Get I2S APB1 clock source selection.
AnnaBridge	156:ff21514d8981	6510	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6511	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
AnnaBridge	156:ff21514d8981	6512	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
AnnaBridge	156:ff21514d8981	6513	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
AnnaBridge	156:ff21514d8981	6514	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	156:ff21514d8981	6515	*/
AnnaBridge	156:ff21514d8981	6516	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
AnnaBridge	156:ff21514d8981	6517
AnnaBridge	156:ff21514d8981	6518	/** @brief Macro to configure I2S APB2 clock source selection.
AnnaBridge	163:e59c8e839560	6519	* @param __SOURCE__ specifies the I2S APB2 clock source.
AnnaBridge	156:ff21514d8981	6520	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6521	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
AnnaBridge	156:ff21514d8981	6522	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
AnnaBridge	156:ff21514d8981	6523	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
AnnaBridge	156:ff21514d8981	6524	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	156:ff21514d8981	6525	*/
AnnaBridge	156:ff21514d8981	6526	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
AnnaBridge	156:ff21514d8981	6527
AnnaBridge	156:ff21514d8981	6528	/** @brief Macro to Get I2S APB2 clock source selection.
AnnaBridge	156:ff21514d8981	6529	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6530	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
AnnaBridge	156:ff21514d8981	6531	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
AnnaBridge	156:ff21514d8981	6532	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
AnnaBridge	156:ff21514d8981	6533	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	156:ff21514d8981	6534	*/
AnnaBridge	156:ff21514d8981	6535	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
AnnaBridge	156:ff21514d8981	6536
AnnaBridge	156:ff21514d8981	6537	/** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK).
AnnaBridge	156:ff21514d8981	6538	* @note This macro must be called before enabling the I2S APB clock.
AnnaBridge	163:e59c8e839560	6539	* @param __SOURCE__ specifies the I2S clock source.
AnnaBridge	156:ff21514d8981	6540	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6541	* @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
AnnaBridge	156:ff21514d8981	6542	* @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
AnnaBridge	156:ff21514d8981	6543	* used as I2S clock source.
AnnaBridge	156:ff21514d8981	6544	*/
AnnaBridge	156:ff21514d8981	6545	#define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__))
AnnaBridge	156:ff21514d8981	6546
AnnaBridge	156:ff21514d8981	6547	/** @brief Macro to configure the FMPI2C1 clock.
AnnaBridge	163:e59c8e839560	6548	* @param __SOURCE__ specifies the FMPI2C1 clock source.
AnnaBridge	156:ff21514d8981	6549	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6550	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
AnnaBridge	156:ff21514d8981	6551	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
AnnaBridge	156:ff21514d8981	6552	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
AnnaBridge	156:ff21514d8981	6553	*/
AnnaBridge	156:ff21514d8981	6554	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
AnnaBridge	156:ff21514d8981	6555
AnnaBridge	156:ff21514d8981	6556	/** @brief Macro to Get the FMPI2C1 clock.
AnnaBridge	156:ff21514d8981	6557	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6558	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
AnnaBridge	156:ff21514d8981	6559	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
AnnaBridge	156:ff21514d8981	6560	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
AnnaBridge	156:ff21514d8981	6561	*/
AnnaBridge	156:ff21514d8981	6562	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
AnnaBridge	156:ff21514d8981	6563
AnnaBridge	156:ff21514d8981	6564	/** @brief Macro to configure the CLK48 clock.
AnnaBridge	163:e59c8e839560	6565	* @param __SOURCE__ specifies the CLK48 clock source.
AnnaBridge	156:ff21514d8981	6566	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6567	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
AnnaBridge	156:ff21514d8981	6568	* @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock.
AnnaBridge	156:ff21514d8981	6569	*/
AnnaBridge	156:ff21514d8981	6570	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
AnnaBridge	156:ff21514d8981	6571
AnnaBridge	156:ff21514d8981	6572	/** @brief Macro to Get the CLK48 clock.
AnnaBridge	156:ff21514d8981	6573	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6574	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
AnnaBridge	156:ff21514d8981	6575	* @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock
AnnaBridge	156:ff21514d8981	6576	*/
AnnaBridge	156:ff21514d8981	6577	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
AnnaBridge	156:ff21514d8981	6578
AnnaBridge	156:ff21514d8981	6579	/** @brief Macro to configure the SDIO clock.
AnnaBridge	163:e59c8e839560	6580	* @param __SOURCE__ specifies the SDIO clock source.
AnnaBridge	156:ff21514d8981	6581	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6582	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
AnnaBridge	156:ff21514d8981	6583	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
AnnaBridge	156:ff21514d8981	6584	*/
AnnaBridge	156:ff21514d8981	6585	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
AnnaBridge	156:ff21514d8981	6586
AnnaBridge	156:ff21514d8981	6587	/** @brief Macro to Get the SDIO clock.
AnnaBridge	156:ff21514d8981	6588	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6589	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
AnnaBridge	156:ff21514d8981	6590	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
AnnaBridge	156:ff21514d8981	6591	*/
AnnaBridge	156:ff21514d8981	6592	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
AnnaBridge	156:ff21514d8981	6593
AnnaBridge	156:ff21514d8981	6594	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
AnnaBridge	156:ff21514d8981	6595
AnnaBridge	156:ff21514d8981	6596	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	156:ff21514d8981	6597	/** @brief Macro to configure I2S clock source selection.
AnnaBridge	163:e59c8e839560	6598	* @param __SOURCE__ specifies the I2S clock source.
AnnaBridge	156:ff21514d8981	6599	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6600	* @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
AnnaBridge	156:ff21514d8981	6601	* @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
AnnaBridge	156:ff21514d8981	6602	* @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
AnnaBridge	156:ff21514d8981	6603	*/
AnnaBridge	156:ff21514d8981	6604	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
AnnaBridge	156:ff21514d8981	6605
AnnaBridge	156:ff21514d8981	6606	/** @brief Macro to Get I2S clock source selection.
AnnaBridge	156:ff21514d8981	6607	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6608	* @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
AnnaBridge	156:ff21514d8981	6609	* @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
AnnaBridge	156:ff21514d8981	6610	* @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
AnnaBridge	156:ff21514d8981	6611	*/
AnnaBridge	156:ff21514d8981	6612	#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
AnnaBridge	156:ff21514d8981	6613
AnnaBridge	156:ff21514d8981	6614	/** @brief Macro to configure the FMPI2C1 clock.
AnnaBridge	163:e59c8e839560	6615	* @param __SOURCE__ specifies the FMPI2C1 clock source.
AnnaBridge	156:ff21514d8981	6616	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6617	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
AnnaBridge	156:ff21514d8981	6618	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
AnnaBridge	156:ff21514d8981	6619	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
AnnaBridge	156:ff21514d8981	6620	*/
AnnaBridge	156:ff21514d8981	6621	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
AnnaBridge	156:ff21514d8981	6622
AnnaBridge	156:ff21514d8981	6623	/** @brief Macro to Get the FMPI2C1 clock.
AnnaBridge	156:ff21514d8981	6624	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6625	* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
AnnaBridge	156:ff21514d8981	6626	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
AnnaBridge	156:ff21514d8981	6627	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
AnnaBridge	156:ff21514d8981	6628	*/
AnnaBridge	156:ff21514d8981	6629	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
AnnaBridge	156:ff21514d8981	6630
AnnaBridge	156:ff21514d8981	6631	/** @brief Macro to configure the LPTIM1 clock.
AnnaBridge	163:e59c8e839560	6632	* @param __SOURCE__ specifies the LPTIM1 clock source.
AnnaBridge	156:ff21514d8981	6633	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6634	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
AnnaBridge	156:ff21514d8981	6635	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
AnnaBridge	156:ff21514d8981	6636	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
AnnaBridge	156:ff21514d8981	6637	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
AnnaBridge	156:ff21514d8981	6638	*/
AnnaBridge	156:ff21514d8981	6639	#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
AnnaBridge	156:ff21514d8981	6640
AnnaBridge	156:ff21514d8981	6641	/** @brief Macro to Get the LPTIM1 clock.
AnnaBridge	156:ff21514d8981	6642	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	6643	* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
AnnaBridge	156:ff21514d8981	6644	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
AnnaBridge	156:ff21514d8981	6645	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
AnnaBridge	156:ff21514d8981	6646	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
AnnaBridge	156:ff21514d8981	6647	*/
AnnaBridge	156:ff21514d8981	6648	#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
AnnaBridge	156:ff21514d8981	6649	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	156:ff21514d8981	6650
AnnaBridge	156:ff21514d8981	6651	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
AnnaBridge	156:ff21514d8981	6652	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
AnnaBridge	156:ff21514d8981	6653	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
AnnaBridge	156:ff21514d8981	6654	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
AnnaBridge	156:ff21514d8981	6655	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	6656	/** @brief Macro to configure the Timers clocks prescalers
AnnaBridge	156:ff21514d8981	6657	* @note This feature is only available with STM32F429x/439x Devices.
AnnaBridge	163:e59c8e839560	6658	* @param __PRESC__ specifies the Timers clocks prescalers selection
AnnaBridge	156:ff21514d8981	6659	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	6660	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
AnnaBridge	156:ff21514d8981	6661	* equal to HPRE if PPREx is corresponding to division by 1 or 2,
AnnaBridge	156:ff21514d8981	6662	* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
AnnaBridge	156:ff21514d8981	6663	* division by 4 or more.
AnnaBridge	156:ff21514d8981	6664	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
AnnaBridge	156:ff21514d8981	6665	* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
AnnaBridge	156:ff21514d8981	6666	* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
AnnaBridge	156:ff21514d8981	6667	* to division by 8 or more.
AnnaBridge	156:ff21514d8981	6668	*/
AnnaBridge	156:ff21514d8981	6669	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) ((__IO uint32_t ) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
AnnaBridge	156:ff21514d8981	6670
AnnaBridge	156:ff21514d8981	6671	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx) \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F410xx \|\| STM32F411xE \|\|\
AnnaBridge	156:ff21514d8981	6672	STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\|\
AnnaBridge	156:ff21514d8981	6673	STM32F423xx */
AnnaBridge	156:ff21514d8981	6674
AnnaBridge	156:ff21514d8981	6675	/----------------------------------------------------------------------------/
AnnaBridge	156:ff21514d8981	6676
AnnaBridge	156:ff21514d8981	6677	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	6678	/** @brief Enable PLLSAI_RDY interrupt.
AnnaBridge	156:ff21514d8981	6679	*/
AnnaBridge	156:ff21514d8981	6680	#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
AnnaBridge	156:ff21514d8981	6681
AnnaBridge	156:ff21514d8981	6682	/** @brief Disable PLLSAI_RDY interrupt.
AnnaBridge	156:ff21514d8981	6683	*/
AnnaBridge	156:ff21514d8981	6684	#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
AnnaBridge	156:ff21514d8981	6685
AnnaBridge	156:ff21514d8981	6686	/** @brief Clear the PLLSAI RDY interrupt pending bits.
AnnaBridge	156:ff21514d8981	6687	*/
AnnaBridge	156:ff21514d8981	6688	#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
AnnaBridge	156:ff21514d8981	6689
AnnaBridge	156:ff21514d8981	6690	/** @brief Check the PLLSAI RDY interrupt has occurred or not.
AnnaBridge	156:ff21514d8981	6691	* @retval The new state (TRUE or FALSE).
AnnaBridge	156:ff21514d8981	6692	*/
AnnaBridge	156:ff21514d8981	6693	#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
AnnaBridge	156:ff21514d8981	6694
AnnaBridge	156:ff21514d8981	6695	/** @brief Check PLLSAI RDY flag is set or not.
AnnaBridge	156:ff21514d8981	6696	* @retval The new state (TRUE or FALSE).
AnnaBridge	156:ff21514d8981	6697	*/
AnnaBridge	156:ff21514d8981	6698	#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
AnnaBridge	156:ff21514d8981	6699
AnnaBridge	156:ff21514d8981	6700	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	6701
AnnaBridge	156:ff21514d8981	6702	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	156:ff21514d8981	6703	/** @brief Macros to enable or disable the RCC MCO1 feature.
AnnaBridge	156:ff21514d8981	6704	*/
AnnaBridge	156:ff21514d8981	6705	#define __HAL_RCC_MCO1_ENABLE() ((__IO uint32_t ) RCC_CFGR_MCO1EN_BB = ENABLE)
AnnaBridge	156:ff21514d8981	6706	#define __HAL_RCC_MCO1_DISABLE() ((__IO uint32_t ) RCC_CFGR_MCO1EN_BB = DISABLE)
AnnaBridge	156:ff21514d8981	6707
AnnaBridge	156:ff21514d8981	6708	/** @brief Macros to enable or disable the RCC MCO2 feature.
AnnaBridge	156:ff21514d8981	6709	*/
AnnaBridge	156:ff21514d8981	6710	#define __HAL_RCC_MCO2_ENABLE() ((__IO uint32_t ) RCC_CFGR_MCO2EN_BB = ENABLE)
AnnaBridge	156:ff21514d8981	6711	#define __HAL_RCC_MCO2_DISABLE() ((__IO uint32_t ) RCC_CFGR_MCO2EN_BB = DISABLE)
AnnaBridge	156:ff21514d8981	6712
AnnaBridge	156:ff21514d8981	6713	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	156:ff21514d8981	6714
AnnaBridge	156:ff21514d8981	6715	/**
AnnaBridge	156:ff21514d8981	6716	* @}
AnnaBridge	156:ff21514d8981	6717	*/
AnnaBridge	156:ff21514d8981	6718
AnnaBridge	156:ff21514d8981	6719	/* Exported functions --------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	6720	/** @addtogroup RCCEx_Exported_Functions
AnnaBridge	156:ff21514d8981	6721	* @{
AnnaBridge	156:ff21514d8981	6722	*/
AnnaBridge	156:ff21514d8981	6723
AnnaBridge	156:ff21514d8981	6724	/** @addtogroup RCCEx_Exported_Functions_Group1
AnnaBridge	156:ff21514d8981	6725	* @{
AnnaBridge	156:ff21514d8981	6726	*/
AnnaBridge	156:ff21514d8981	6727	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge	156:ff21514d8981	6728	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge	156:ff21514d8981	6729
AnnaBridge	156:ff21514d8981	6730	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
AnnaBridge	156:ff21514d8981	6731
AnnaBridge	156:ff21514d8981	6732	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\|\
AnnaBridge	156:ff21514d8981	6733	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
AnnaBridge	156:ff21514d8981	6734	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\|\
AnnaBridge	156:ff21514d8981	6735	defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	6736	void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
AnnaBridge	156:ff21514d8981	6737	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	163:e59c8e839560	6738	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	163:e59c8e839560	6739	HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
AnnaBridge	163:e59c8e839560	6740	HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
AnnaBridge	163:e59c8e839560	6741	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	163:e59c8e839560	6742	#if defined(RCC_PLLSAI_SUPPORT)
AnnaBridge	163:e59c8e839560	6743	HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit);
AnnaBridge	163:e59c8e839560	6744	HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);
AnnaBridge	163:e59c8e839560	6745	#endif /* RCC_PLLSAI_SUPPORT */
AnnaBridge	156:ff21514d8981	6746	/**
AnnaBridge	156:ff21514d8981	6747	* @}
AnnaBridge	156:ff21514d8981	6748	*/
AnnaBridge	156:ff21514d8981	6749
AnnaBridge	156:ff21514d8981	6750	/**
AnnaBridge	156:ff21514d8981	6751	* @}
AnnaBridge	156:ff21514d8981	6752	*/
AnnaBridge	156:ff21514d8981	6753	/* Private types -------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	6754	/* Private variables ---------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	6755	/* Private constants ---------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	6756	/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
AnnaBridge	156:ff21514d8981	6757	* @{
AnnaBridge	156:ff21514d8981	6758	*/
AnnaBridge	156:ff21514d8981	6759
AnnaBridge	156:ff21514d8981	6760	/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
AnnaBridge	156:ff21514d8981	6761	* @brief RCC registers bit address in the alias region
AnnaBridge	156:ff21514d8981	6762	* @{
AnnaBridge	156:ff21514d8981	6763	*/
AnnaBridge	156:ff21514d8981	6764	/* --- CR Register ---*/
AnnaBridge	156:ff21514d8981	6765	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
AnnaBridge	156:ff21514d8981	6766	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	6767	/* Alias word address of PLLSAION bit */
AnnaBridge	156:ff21514d8981	6768	#define RCC_PLLSAION_BIT_NUMBER 0x1CU
AnnaBridge	156:ff21514d8981	6769	#define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U))
AnnaBridge	156:ff21514d8981	6770
AnnaBridge	156:ff21514d8981	6771	#define PLLSAI_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
AnnaBridge	156:ff21514d8981	6772	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	6773
AnnaBridge	156:ff21514d8981	6774	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
AnnaBridge	156:ff21514d8981	6775	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
AnnaBridge	156:ff21514d8981	6776	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
AnnaBridge	156:ff21514d8981	6777	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	156:ff21514d8981	6778	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	6779	/* Alias word address of PLLI2SON bit */
AnnaBridge	156:ff21514d8981	6780	#define RCC_PLLI2SON_BIT_NUMBER 0x1AU
AnnaBridge	156:ff21514d8981	6781	#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U))
AnnaBridge	156:ff21514d8981	6782	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
AnnaBridge	156:ff21514d8981	6783	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
AnnaBridge	156:ff21514d8981	6784	STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	6785
AnnaBridge	156:ff21514d8981	6786	/* --- DCKCFGR Register ---*/
AnnaBridge	156:ff21514d8981	6787	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
AnnaBridge	156:ff21514d8981	6788	defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F401xC) \|\|\
AnnaBridge	156:ff21514d8981	6789	defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
AnnaBridge	156:ff21514d8981	6790	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
AnnaBridge	156:ff21514d8981	6791	defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	6792	/* Alias word address of TIMPRE bit */
AnnaBridge	156:ff21514d8981	6793	#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8CU)
AnnaBridge	156:ff21514d8981	6794	#define RCC_TIMPRE_BIT_NUMBER 0x18U
AnnaBridge	156:ff21514d8981	6795	#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U))
AnnaBridge	156:ff21514d8981	6796	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F410xx \|\| STM32F401xC \|\|\
AnnaBridge	156:ff21514d8981	6797	STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\|\
AnnaBridge	156:ff21514d8981	6798	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	6799
AnnaBridge	156:ff21514d8981	6800	/* --- CFGR Register ---*/
AnnaBridge	156:ff21514d8981	6801	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
AnnaBridge	156:ff21514d8981	6802	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
AnnaBridge	156:ff21514d8981	6803	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
AnnaBridge	156:ff21514d8981	6804	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
AnnaBridge	156:ff21514d8981	6805	defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	6806	/* Alias word address of I2SSRC bit */
AnnaBridge	156:ff21514d8981	6807	#define RCC_I2SSRC_BIT_NUMBER 0x17U
AnnaBridge	156:ff21514d8981	6808	#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U))
AnnaBridge	156:ff21514d8981	6809
AnnaBridge	156:ff21514d8981	6810	#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
AnnaBridge	156:ff21514d8981	6811	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
AnnaBridge	156:ff21514d8981	6812	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	6813
AnnaBridge	156:ff21514d8981	6814	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
AnnaBridge	156:ff21514d8981	6815	defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	6816	/* --- PLLI2SCFGR Register ---*/
AnnaBridge	156:ff21514d8981	6817	#define RCC_PLLI2SCFGR_OFFSET (RCC_OFFSET + 0x84U)
AnnaBridge	156:ff21514d8981	6818	/* Alias word address of PLLI2SSRC bit */
AnnaBridge	156:ff21514d8981	6819	#define RCC_PLLI2SSRC_BIT_NUMBER 0x16U
AnnaBridge	156:ff21514d8981	6820	#define RCC_PLLI2SCFGR_PLLI2SSRC_BB (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U))
AnnaBridge	156:ff21514d8981	6821
AnnaBridge	156:ff21514d8981	6822	#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */
AnnaBridge	156:ff21514d8981	6823	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \| STM32F423xx */
AnnaBridge	156:ff21514d8981	6824
AnnaBridge	156:ff21514d8981	6825	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	156:ff21514d8981	6826	/* Alias word address of MCO1EN bit */
AnnaBridge	156:ff21514d8981	6827	#define RCC_MCO1EN_BIT_NUMBER 0x8U
AnnaBridge	156:ff21514d8981	6828	#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U))
AnnaBridge	156:ff21514d8981	6829
AnnaBridge	156:ff21514d8981	6830	/* Alias word address of MCO2EN bit */
AnnaBridge	156:ff21514d8981	6831	#define RCC_MCO2EN_BIT_NUMBER 0x9U
AnnaBridge	156:ff21514d8981	6832	#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U))
AnnaBridge	156:ff21514d8981	6833	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	156:ff21514d8981	6834
AnnaBridge	156:ff21514d8981	6835	#define PLL_TIMEOUT_VALUE 2U /* 2 ms */
AnnaBridge	156:ff21514d8981	6836	/**
AnnaBridge	156:ff21514d8981	6837	* @}
AnnaBridge	156:ff21514d8981	6838	*/
AnnaBridge	156:ff21514d8981	6839
AnnaBridge	156:ff21514d8981	6840	/**
AnnaBridge	156:ff21514d8981	6841	* @}
AnnaBridge	156:ff21514d8981	6842	*/
AnnaBridge	156:ff21514d8981	6843
AnnaBridge	156:ff21514d8981	6844	/* Private macros ------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	6845	/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
AnnaBridge	156:ff21514d8981	6846	* @{
AnnaBridge	156:ff21514d8981	6847	*/
AnnaBridge	156:ff21514d8981	6848	/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
AnnaBridge	156:ff21514d8981	6849	* @{
AnnaBridge	156:ff21514d8981	6850	*/
AnnaBridge	156:ff21514d8981	6851	#if defined(STM32F411xE)
AnnaBridge	156:ff21514d8981	6852	#define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
AnnaBridge	156:ff21514d8981	6853	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
AnnaBridge	156:ff21514d8981	6854	#else /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\|
AnnaBridge	156:ff21514d8981	6855	STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F410Tx \|\| STM32F410Cx \|\|
AnnaBridge	156:ff21514d8981	6856	STM32F410Rx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Cx \|\| STM32F412Rx \|\|
AnnaBridge	156:ff21514d8981	6857	STM32F412Vx \|\| STM32F412Zx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	6858	#define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
AnnaBridge	156:ff21514d8981	6859	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
AnnaBridge	156:ff21514d8981	6860	#endif /* STM32F411xE */
AnnaBridge	156:ff21514d8981	6861
AnnaBridge	156:ff21514d8981	6862	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
AnnaBridge	156:ff21514d8981	6863	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))
AnnaBridge	156:ff21514d8981	6864	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
AnnaBridge	156:ff21514d8981	6865
AnnaBridge	156:ff21514d8981	6866	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
AnnaBridge	156:ff21514d8981	6867	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U))
AnnaBridge	156:ff21514d8981	6868	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
AnnaBridge	156:ff21514d8981	6869
AnnaBridge	156:ff21514d8981	6870	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
AnnaBridge	156:ff21514d8981	6871	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU))
AnnaBridge	156:ff21514d8981	6872	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
AnnaBridge	156:ff21514d8981	6873
AnnaBridge	156:ff21514d8981	6874	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	156:ff21514d8981	6875	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))
AnnaBridge	156:ff21514d8981	6876	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	156:ff21514d8981	6877
AnnaBridge	156:ff21514d8981	6878	#if defined(STM32F446xx)
AnnaBridge	156:ff21514d8981	6879	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU))
AnnaBridge	156:ff21514d8981	6880	#endif /* STM32F446xx */
AnnaBridge	156:ff21514d8981	6881
AnnaBridge	156:ff21514d8981	6882	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	6883	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU))
AnnaBridge	156:ff21514d8981	6884	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	6885
AnnaBridge	156:ff21514d8981	6886	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
AnnaBridge	156:ff21514d8981	6887	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU))
AnnaBridge	156:ff21514d8981	6888	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
AnnaBridge	156:ff21514d8981	6889
AnnaBridge	156:ff21514d8981	6890	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	6891	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU))
AnnaBridge	156:ff21514d8981	6892	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	6893
AnnaBridge	156:ff21514d8981	6894	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
AnnaBridge	156:ff21514d8981	6895
AnnaBridge	156:ff21514d8981	6896	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
AnnaBridge	156:ff21514d8981	6897	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	6898	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
AnnaBridge	156:ff21514d8981	6899
AnnaBridge	156:ff21514d8981	6900	#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
AnnaBridge	156:ff21514d8981	6901
AnnaBridge	156:ff21514d8981	6902	#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
AnnaBridge	156:ff21514d8981	6903
AnnaBridge	156:ff21514d8981	6904	#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
AnnaBridge	156:ff21514d8981	6905
AnnaBridge	156:ff21514d8981	6906	#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
AnnaBridge	156:ff21514d8981	6907
AnnaBridge	156:ff21514d8981	6908	#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
AnnaBridge	156:ff21514d8981	6909
AnnaBridge	156:ff21514d8981	6910	#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) \|\|\
AnnaBridge	156:ff21514d8981	6911	((VALUE) == RCC_PLLSAIDIVR_4) \|\|\
AnnaBridge	156:ff21514d8981	6912	((VALUE) == RCC_PLLSAIDIVR_8) \|\|\
AnnaBridge	156:ff21514d8981	6913	((VALUE) == RCC_PLLSAIDIVR_16))
AnnaBridge	156:ff21514d8981	6914	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	6915
AnnaBridge	156:ff21514d8981	6916	#if defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	156:ff21514d8981	6917	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	6918	#define IS_RCC_PLLI2SM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U))
AnnaBridge	156:ff21514d8981	6919
AnnaBridge	156:ff21514d8981	6920	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
AnnaBridge	156:ff21514d8981	6921	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
AnnaBridge	156:ff21514d8981	6922	#endif /* STM32F411xE \|\| STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	6923
AnnaBridge	156:ff21514d8981	6924	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	156:ff21514d8981	6925	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
AnnaBridge	156:ff21514d8981	6926
AnnaBridge	156:ff21514d8981	6927	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
AnnaBridge	156:ff21514d8981	6928	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
AnnaBridge	156:ff21514d8981	6929
AnnaBridge	156:ff21514d8981	6930	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) \|\|\
AnnaBridge	156:ff21514d8981	6931	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
AnnaBridge	156:ff21514d8981	6932	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
AnnaBridge	156:ff21514d8981	6933
AnnaBridge	156:ff21514d8981	6934	#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) \|\|\
AnnaBridge	156:ff21514d8981	6935	((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) \|\|\
AnnaBridge	156:ff21514d8981	6936	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\|\
AnnaBridge	156:ff21514d8981	6937	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
AnnaBridge	156:ff21514d8981	6938
AnnaBridge	156:ff21514d8981	6939	#define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) \|\|\
AnnaBridge	156:ff21514d8981	6940	((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) \|\|\
AnnaBridge	156:ff21514d8981	6941	((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
AnnaBridge	156:ff21514d8981	6942	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	156:ff21514d8981	6943
AnnaBridge	156:ff21514d8981	6944	#if defined(STM32F446xx)
AnnaBridge	156:ff21514d8981	6945	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
AnnaBridge	156:ff21514d8981	6946
AnnaBridge	156:ff21514d8981	6947	#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) \|\|\
AnnaBridge	156:ff21514d8981	6948	((VALUE) == RCC_PLLI2SP_DIV4) \|\|\
AnnaBridge	156:ff21514d8981	6949	((VALUE) == RCC_PLLI2SP_DIV6) \|\|\
AnnaBridge	156:ff21514d8981	6950	((VALUE) == RCC_PLLI2SP_DIV8))
AnnaBridge	156:ff21514d8981	6951
AnnaBridge	156:ff21514d8981	6952	#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63U)
AnnaBridge	156:ff21514d8981	6953
AnnaBridge	156:ff21514d8981	6954	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
AnnaBridge	156:ff21514d8981	6955	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
AnnaBridge	156:ff21514d8981	6956	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
AnnaBridge	156:ff21514d8981	6957	((VALUE) == RCC_PLLSAIP_DIV8))
AnnaBridge	156:ff21514d8981	6958
AnnaBridge	156:ff21514d8981	6959	#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) \|\|\
AnnaBridge	156:ff21514d8981	6960	((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) \|\|\
AnnaBridge	156:ff21514d8981	6961	((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) \|\|\
AnnaBridge	156:ff21514d8981	6962	((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
AnnaBridge	156:ff21514d8981	6963
AnnaBridge	156:ff21514d8981	6964	#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) \|\|\
AnnaBridge	156:ff21514d8981	6965	((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) \|\|\
AnnaBridge	156:ff21514d8981	6966	((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) \|\|\
AnnaBridge	156:ff21514d8981	6967	((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
AnnaBridge	156:ff21514d8981	6968
AnnaBridge	156:ff21514d8981	6969	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
AnnaBridge	156:ff21514d8981	6970	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
AnnaBridge	156:ff21514d8981	6971	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
AnnaBridge	156:ff21514d8981	6972	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
AnnaBridge	156:ff21514d8981	6973
AnnaBridge	156:ff21514d8981	6974	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
AnnaBridge	156:ff21514d8981	6975	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
AnnaBridge	156:ff21514d8981	6976	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
AnnaBridge	156:ff21514d8981	6977	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
AnnaBridge	156:ff21514d8981	6978
AnnaBridge	156:ff21514d8981	6979	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) \|\|\
AnnaBridge	156:ff21514d8981	6980	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
AnnaBridge	156:ff21514d8981	6981	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
AnnaBridge	156:ff21514d8981	6982
AnnaBridge	156:ff21514d8981	6983	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\|\
AnnaBridge	156:ff21514d8981	6984	((SOURCE) == RCC_CECCLKSOURCE_LSE))
AnnaBridge	156:ff21514d8981	6985
AnnaBridge	156:ff21514d8981	6986	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
AnnaBridge	156:ff21514d8981	6987	((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
AnnaBridge	156:ff21514d8981	6988
AnnaBridge	156:ff21514d8981	6989	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
AnnaBridge	156:ff21514d8981	6990	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
AnnaBridge	156:ff21514d8981	6991
AnnaBridge	156:ff21514d8981	6992	#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) \|\|\
AnnaBridge	156:ff21514d8981	6993	((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
AnnaBridge	156:ff21514d8981	6994	#endif /* STM32F446xx */
AnnaBridge	156:ff21514d8981	6995
AnnaBridge	156:ff21514d8981	6996	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
AnnaBridge	156:ff21514d8981	6997	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
AnnaBridge	156:ff21514d8981	6998
AnnaBridge	156:ff21514d8981	6999	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
AnnaBridge	156:ff21514d8981	7000	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
AnnaBridge	156:ff21514d8981	7001	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
AnnaBridge	156:ff21514d8981	7002	((VALUE) == RCC_PLLSAIP_DIV8))
AnnaBridge	156:ff21514d8981	7003
AnnaBridge	156:ff21514d8981	7004	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
AnnaBridge	156:ff21514d8981	7005	((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
AnnaBridge	156:ff21514d8981	7006
AnnaBridge	156:ff21514d8981	7007	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
AnnaBridge	156:ff21514d8981	7008	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
AnnaBridge	156:ff21514d8981	7009
AnnaBridge	156:ff21514d8981	7010	#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) \|\|\
AnnaBridge	156:ff21514d8981	7011	((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
AnnaBridge	156:ff21514d8981	7012
AnnaBridge	156:ff21514d8981	7013	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
AnnaBridge	156:ff21514d8981	7014	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
AnnaBridge	156:ff21514d8981	7015	#endif /* STM32F469xx \|\| STM32F479xx */
AnnaBridge	156:ff21514d8981	7016
AnnaBridge	156:ff21514d8981	7017	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\|\
AnnaBridge	156:ff21514d8981	7018	defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	7019	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
AnnaBridge	156:ff21514d8981	7020
AnnaBridge	156:ff21514d8981	7021	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
AnnaBridge	156:ff21514d8981	7022
AnnaBridge	156:ff21514d8981	7023	#define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) \|\| \
AnnaBridge	156:ff21514d8981	7024	((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT))
AnnaBridge	156:ff21514d8981	7025
AnnaBridge	156:ff21514d8981	7026	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
AnnaBridge	156:ff21514d8981	7027	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
AnnaBridge	156:ff21514d8981	7028	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
AnnaBridge	156:ff21514d8981	7029	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
AnnaBridge	156:ff21514d8981	7030
AnnaBridge	156:ff21514d8981	7031	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
AnnaBridge	156:ff21514d8981	7032	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
AnnaBridge	156:ff21514d8981	7033	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
AnnaBridge	156:ff21514d8981	7034	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
AnnaBridge	156:ff21514d8981	7035
AnnaBridge	156:ff21514d8981	7036	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) \|\|\
AnnaBridge	156:ff21514d8981	7037	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
AnnaBridge	156:ff21514d8981	7038	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
AnnaBridge	156:ff21514d8981	7039
AnnaBridge	156:ff21514d8981	7040	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
AnnaBridge	156:ff21514d8981	7041	((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ))
AnnaBridge	156:ff21514d8981	7042
AnnaBridge	156:ff21514d8981	7043	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
AnnaBridge	156:ff21514d8981	7044	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
AnnaBridge	156:ff21514d8981	7045
AnnaBridge	156:ff21514d8981	7046	#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) \|\| \
AnnaBridge	156:ff21514d8981	7047	((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
AnnaBridge	156:ff21514d8981	7048
AnnaBridge	156:ff21514d8981	7049	#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) \|\| \
AnnaBridge	156:ff21514d8981	7050	((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2))
AnnaBridge	156:ff21514d8981	7051
AnnaBridge	156:ff21514d8981	7052	#if defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	7053	#define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) \|\| \
AnnaBridge	156:ff21514d8981	7054	((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK))
AnnaBridge	156:ff21514d8981	7055
AnnaBridge	156:ff21514d8981	7056	#define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) \|\| \
AnnaBridge	156:ff21514d8981	7057	((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2))
AnnaBridge	156:ff21514d8981	7058
AnnaBridge	156:ff21514d8981	7059	#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) \|\|\
AnnaBridge	156:ff21514d8981	7060	((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) \|\|\
AnnaBridge	156:ff21514d8981	7061	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\|\
AnnaBridge	156:ff21514d8981	7062	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
AnnaBridge	156:ff21514d8981	7063
AnnaBridge	156:ff21514d8981	7064	#define IS_RCC_SAIACLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) \|\|\
AnnaBridge	156:ff21514d8981	7065	((SOURCE) == RCC_SAIACLKSOURCE_EXT) \|\|\
AnnaBridge	156:ff21514d8981	7066	((SOURCE) == RCC_SAIACLKSOURCE_PLLR) \|\|\
AnnaBridge	156:ff21514d8981	7067	((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC))
AnnaBridge	156:ff21514d8981	7068
AnnaBridge	156:ff21514d8981	7069	#define IS_RCC_SAIBCLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) \|\|\
AnnaBridge	156:ff21514d8981	7070	((SOURCE) == RCC_SAIBCLKSOURCE_EXT) \|\|\
AnnaBridge	156:ff21514d8981	7071	((SOURCE) == RCC_SAIBCLKSOURCE_PLLR) \|\|\
AnnaBridge	156:ff21514d8981	7072	((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC))
AnnaBridge	156:ff21514d8981	7073
AnnaBridge	156:ff21514d8981	7074	#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
AnnaBridge	156:ff21514d8981	7075
AnnaBridge	156:ff21514d8981	7076	#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
AnnaBridge	156:ff21514d8981	7077
AnnaBridge	156:ff21514d8981	7078	#endif /* STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	7079	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
AnnaBridge	156:ff21514d8981	7080
AnnaBridge	156:ff21514d8981	7081	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
AnnaBridge	156:ff21514d8981	7082	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
AnnaBridge	156:ff21514d8981	7083	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
AnnaBridge	156:ff21514d8981	7084	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	156:ff21514d8981	7085	defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	156:ff21514d8981	7086
AnnaBridge	156:ff21514d8981	7087	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)\|\| \
AnnaBridge	156:ff21514d8981	7088	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
AnnaBridge	156:ff21514d8981	7089
AnnaBridge	156:ff21514d8981	7090	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
AnnaBridge	156:ff21514d8981	7091	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| \
AnnaBridge	156:ff21514d8981	7092	STM32F412Rx */
AnnaBridge	156:ff21514d8981	7093
AnnaBridge	156:ff21514d8981	7094	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
AnnaBridge	156:ff21514d8981	7095	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)\|\| \
AnnaBridge	156:ff21514d8981	7096	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
AnnaBridge	156:ff21514d8981	7097	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
AnnaBridge	156:ff21514d8981	7098	/**
AnnaBridge	156:ff21514d8981	7099	* @}
AnnaBridge	156:ff21514d8981	7100	*/
AnnaBridge	156:ff21514d8981	7101
AnnaBridge	156:ff21514d8981	7102	/**
AnnaBridge	156:ff21514d8981	7103	* @}
AnnaBridge	156:ff21514d8981	7104	*/
AnnaBridge	156:ff21514d8981	7105
AnnaBridge	156:ff21514d8981	7106	/**
AnnaBridge	156:ff21514d8981	7107	* @}
AnnaBridge	156:ff21514d8981	7108	*/
AnnaBridge	156:ff21514d8981	7109
AnnaBridge	156:ff21514d8981	7110	/**
AnnaBridge	156:ff21514d8981	7111	* @}
AnnaBridge	156:ff21514d8981	7112	*/
AnnaBridge	156:ff21514d8981	7113	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	7114	}
AnnaBridge	156:ff21514d8981	7115	#endif
AnnaBridge	156:ff21514d8981	7116
AnnaBridge	156:ff21514d8981	7117	#endif /* __STM32F4xx_HAL_RCC_EX_H */
AnnaBridge	156:ff21514d8981	7118
AnnaBridge	156:ff21514d8981	7119	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/