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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F302R8/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dma.h@128:9bcdf88f62b0, 2016-10-27 (annotated)

Committer:
<>
Date:
Thu Oct 27 16:45:56 2016 +0100
Revision:
128:9bcdf88f62b0
Parent:
TARGET_NUCLEO_F334R8/stm32f3xx_hal_dma.h@123:b0220dba8be7
Child:
135:176b8275d35d
Release 128 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



2966: Add kw24 support https://github.com/ARMmbed/mbed-os/pull/2966

3068: MultiTech mDot - clean up PeripheralPins.c and add new pin names https://github.com/ARMmbed/mbed-os/pull/3068

3089: Kinetis HAL: Remove clock initialization code from serial and ticker  https://github.com/ARMmbed/mbed-os/pull/3089

2943: [NRF5] NVIC_SetVector functionality https://github.com/ARMmbed/mbed-os/pull/2943

2938: InterruptIn changes in NCS36510 HAL. https://github.com/ARMmbed/mbed-os/pull/2938

3108: Fix sleep function for NRF52. https://github.com/ARMmbed/mbed-os/pull/3108

3076: STM32F1: Correct timer master value reading https://github.com/ARMmbed/mbed-os/pull/3076

3085: Add LOWPOWERTIMER capability for NUCLEO_F303ZE https://github.com/ARMmbed/mbed-os/pull/3085

3046: [BEETLE] Update BLE stack on Beetle board https://github.com/ARMmbed/mbed-os/pull/3046

3122: [Silicon Labs] Update of Silicon Labs HAL https://github.com/ARMmbed/mbed-os/pull/3122

3022: OnSemi RAM usage fix https://github.com/ARMmbed/mbed-os/pull/3022

3121: STM32F3: Correct UART4 and UART5 defines when using DEVICE_SERIAL_ASYNCH https://github.com/ARMmbed/mbed-os/pull/3121

3142: Targets- NUMAKER_PFM_NUC47216 remove mbed 2 https://github.com/ARMmbed/mbed-os/pull/3142

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 86:04dd9b1680ae 1 /**
bogdanm 86:04dd9b1680ae 2 ******************************************************************************
bogdanm 86:04dd9b1680ae 3 * @file stm32f3xx_hal_dma.h
bogdanm 86:04dd9b1680ae 4 * @author MCD Application Team
Kojto 123:b0220dba8be7 5 * @version V1.3.0
Kojto 123:b0220dba8be7 6 * @date 01-July-2016
bogdanm 86:04dd9b1680ae 7 * @brief Header file of DMA HAL module.
bogdanm 86:04dd9b1680ae 8 ******************************************************************************
bogdanm 86:04dd9b1680ae 9 * @attention
bogdanm 86:04dd9b1680ae 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 86:04dd9b1680ae 12 *
bogdanm 86:04dd9b1680ae 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 86:04dd9b1680ae 14 * are permitted provided that the following conditions are met:
bogdanm 86:04dd9b1680ae 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 86:04dd9b1680ae 16 * this list of conditions and the following disclaimer.
bogdanm 86:04dd9b1680ae 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 86:04dd9b1680ae 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 86:04dd9b1680ae 19 * and/or other materials provided with the distribution.
bogdanm 86:04dd9b1680ae 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 86:04dd9b1680ae 21 * may be used to endorse or promote products derived from this software
bogdanm 86:04dd9b1680ae 22 * without specific prior written permission.
bogdanm 86:04dd9b1680ae 23 *
bogdanm 86:04dd9b1680ae 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 86:04dd9b1680ae 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 86:04dd9b1680ae 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 86:04dd9b1680ae 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 86:04dd9b1680ae 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 86:04dd9b1680ae 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 86:04dd9b1680ae 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 86:04dd9b1680ae 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 86:04dd9b1680ae 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 86:04dd9b1680ae 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 86:04dd9b1680ae 34 *
bogdanm 86:04dd9b1680ae 35 ******************************************************************************
bogdanm 86:04dd9b1680ae 36 */
bogdanm 86:04dd9b1680ae 37
bogdanm 86:04dd9b1680ae 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 86:04dd9b1680ae 39 #ifndef __STM32F3xx_HAL_DMA_H
bogdanm 86:04dd9b1680ae 40 #define __STM32F3xx_HAL_DMA_H
bogdanm 86:04dd9b1680ae 41
bogdanm 86:04dd9b1680ae 42 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 43 extern "C" {
bogdanm 86:04dd9b1680ae 44 #endif
bogdanm 86:04dd9b1680ae 45
bogdanm 86:04dd9b1680ae 46 /* Includes ------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 47 #include "stm32f3xx_hal_def.h"
bogdanm 86:04dd9b1680ae 48
bogdanm 86:04dd9b1680ae 49 /** @addtogroup STM32F3xx_HAL_Driver
bogdanm 86:04dd9b1680ae 50 * @{
bogdanm 86:04dd9b1680ae 51 */
bogdanm 86:04dd9b1680ae 52
Kojto 122:f9eeca106725 53 /** @addtogroup DMA
bogdanm 86:04dd9b1680ae 54 * @{
bogdanm 86:04dd9b1680ae 55 */
bogdanm 86:04dd9b1680ae 56
bogdanm 86:04dd9b1680ae 57 /* Exported types ------------------------------------------------------------*/
Kojto 122:f9eeca106725 58
bogdanm 92:4fc01daae5a5 59 /** @defgroup DMA_Exported_Types DMA Exported Types
bogdanm 92:4fc01daae5a5 60 * @{
bogdanm 92:4fc01daae5a5 61 */
bogdanm 86:04dd9b1680ae 62
bogdanm 86:04dd9b1680ae 63 /**
bogdanm 86:04dd9b1680ae 64 * @brief DMA Configuration Structure definition
bogdanm 86:04dd9b1680ae 65 */
bogdanm 86:04dd9b1680ae 66 typedef struct
bogdanm 86:04dd9b1680ae 67 {
bogdanm 86:04dd9b1680ae 68 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
bogdanm 86:04dd9b1680ae 69 from memory to memory or from peripheral to memory.
bogdanm 86:04dd9b1680ae 70 This parameter can be a value of @ref DMA_Data_transfer_direction */
bogdanm 86:04dd9b1680ae 71
bogdanm 86:04dd9b1680ae 72 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
bogdanm 86:04dd9b1680ae 73 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
bogdanm 86:04dd9b1680ae 74
bogdanm 86:04dd9b1680ae 75 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
bogdanm 86:04dd9b1680ae 76 This parameter can be a value of @ref DMA_Memory_incremented_mode */
bogdanm 86:04dd9b1680ae 77
bogdanm 86:04dd9b1680ae 78 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
bogdanm 86:04dd9b1680ae 79 This parameter can be a value of @ref DMA_Peripheral_data_size */
bogdanm 86:04dd9b1680ae 80
bogdanm 86:04dd9b1680ae 81 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
bogdanm 86:04dd9b1680ae 82 This parameter can be a value of @ref DMA_Memory_data_size */
bogdanm 86:04dd9b1680ae 83
bogdanm 86:04dd9b1680ae 84 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
bogdanm 86:04dd9b1680ae 85 This parameter can be a value of @ref DMA_mode
bogdanm 86:04dd9b1680ae 86 @note The circular buffer mode cannot be used if the memory-to-memory
bogdanm 86:04dd9b1680ae 87 data transfer is configured on the selected Channel */
bogdanm 86:04dd9b1680ae 88
bogdanm 86:04dd9b1680ae 89 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
bogdanm 86:04dd9b1680ae 90 This parameter can be a value of @ref DMA_Priority_level */
bogdanm 86:04dd9b1680ae 91 } DMA_InitTypeDef;
bogdanm 86:04dd9b1680ae 92
bogdanm 86:04dd9b1680ae 93 /**
bogdanm 86:04dd9b1680ae 94 * @brief DMA Configuration enumeration values definition
bogdanm 86:04dd9b1680ae 95 */
bogdanm 86:04dd9b1680ae 96 typedef enum
bogdanm 86:04dd9b1680ae 97 {
bogdanm 86:04dd9b1680ae 98 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
bogdanm 86:04dd9b1680ae 99 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
bogdanm 86:04dd9b1680ae 100
bogdanm 86:04dd9b1680ae 101 } DMA_ControlTypeDef;
bogdanm 86:04dd9b1680ae 102
bogdanm 86:04dd9b1680ae 103 /**
bogdanm 86:04dd9b1680ae 104 * @brief HAL DMA State structures definition
bogdanm 86:04dd9b1680ae 105 */
bogdanm 86:04dd9b1680ae 106 typedef enum
bogdanm 86:04dd9b1680ae 107 {
bogdanm 86:04dd9b1680ae 108 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
Kojto 122:f9eeca106725 109 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
bogdanm 86:04dd9b1680ae 110 HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
bogdanm 86:04dd9b1680ae 111 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
bogdanm 86:04dd9b1680ae 112 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
bogdanm 86:04dd9b1680ae 113 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
bogdanm 86:04dd9b1680ae 114 }HAL_DMA_StateTypeDef;
bogdanm 86:04dd9b1680ae 115
bogdanm 86:04dd9b1680ae 116 /**
bogdanm 86:04dd9b1680ae 117 * @brief HAL DMA Error Code structure definition
bogdanm 86:04dd9b1680ae 118 */
bogdanm 86:04dd9b1680ae 119 typedef enum
bogdanm 86:04dd9b1680ae 120 {
bogdanm 86:04dd9b1680ae 121 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
bogdanm 86:04dd9b1680ae 122 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
bogdanm 86:04dd9b1680ae 123 }HAL_DMA_LevelCompleteTypeDef;
Kojto 122:f9eeca106725 124
bogdanm 86:04dd9b1680ae 125 /**
bogdanm 86:04dd9b1680ae 126 * @brief DMA handle Structure definition
bogdanm 86:04dd9b1680ae 127 */
bogdanm 86:04dd9b1680ae 128 typedef struct __DMA_HandleTypeDef
bogdanm 86:04dd9b1680ae 129 {
Kojto 122:f9eeca106725 130 DMA_Channel_TypeDef *Instance; /*!< Register base address */
bogdanm 86:04dd9b1680ae 131
bogdanm 86:04dd9b1680ae 132 DMA_InitTypeDef Init; /*!< DMA communication parameters */
bogdanm 86:04dd9b1680ae 133
bogdanm 86:04dd9b1680ae 134 HAL_LockTypeDef Lock; /*!< DMA locking object */
bogdanm 86:04dd9b1680ae 135
bogdanm 86:04dd9b1680ae 136 HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
bogdanm 86:04dd9b1680ae 137
bogdanm 86:04dd9b1680ae 138 void *Parent; /*!< Parent object state */
bogdanm 86:04dd9b1680ae 139
bogdanm 86:04dd9b1680ae 140 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
bogdanm 86:04dd9b1680ae 141
bogdanm 86:04dd9b1680ae 142 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
Kojto 122:f9eeca106725 143
bogdanm 86:04dd9b1680ae 144 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
bogdanm 86:04dd9b1680ae 145
Kojto 122:f9eeca106725 146 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
bogdanm 86:04dd9b1680ae 147
Kojto 122:f9eeca106725 148 __IO uint32_t ErrorCode; /*!< DMA Error code */
bogdanm 86:04dd9b1680ae 149 } DMA_HandleTypeDef;
bogdanm 92:4fc01daae5a5 150 /**
bogdanm 92:4fc01daae5a5 151 * @}
bogdanm 92:4fc01daae5a5 152 */
bogdanm 86:04dd9b1680ae 153
bogdanm 86:04dd9b1680ae 154 /* Exported constants --------------------------------------------------------*/
Kojto 122:f9eeca106725 155
bogdanm 92:4fc01daae5a5 156 /** @defgroup DMA_Exported_Constants DMA Exported Constants
bogdanm 86:04dd9b1680ae 157 * @{
bogdanm 86:04dd9b1680ae 158 */
bogdanm 86:04dd9b1680ae 159
Kojto 122:f9eeca106725 160 /** @defgroup DMA_Error_Code DMA Error Code
bogdanm 86:04dd9b1680ae 161 * @{
bogdanm 86:04dd9b1680ae 162 */
Kojto 122:f9eeca106725 163 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
Kojto 122:f9eeca106725 164 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
Kojto 122:f9eeca106725 165 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004) /*!< no ongoin transfer */
Kojto 122:f9eeca106725 166 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
bogdanm 86:04dd9b1680ae 167 /**
bogdanm 86:04dd9b1680ae 168 * @}
bogdanm 86:04dd9b1680ae 169 */
bogdanm 86:04dd9b1680ae 170
Kojto 122:f9eeca106725 171 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
bogdanm 86:04dd9b1680ae 172 * @{
bogdanm 86:04dd9b1680ae 173 */
bogdanm 86:04dd9b1680ae 174 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
bogdanm 86:04dd9b1680ae 175 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
Kojto 122:f9eeca106725 176 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
bogdanm 86:04dd9b1680ae 177
bogdanm 86:04dd9b1680ae 178 /**
bogdanm 86:04dd9b1680ae 179 * @}
bogdanm 86:04dd9b1680ae 180 */
bogdanm 86:04dd9b1680ae 181
bogdanm 92:4fc01daae5a5 182 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
bogdanm 86:04dd9b1680ae 183 * @{
bogdanm 86:04dd9b1680ae 184 */
bogdanm 86:04dd9b1680ae 185 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
bogdanm 86:04dd9b1680ae 186 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
bogdanm 86:04dd9b1680ae 187 /**
bogdanm 86:04dd9b1680ae 188 * @}
bogdanm 86:04dd9b1680ae 189 */
bogdanm 86:04dd9b1680ae 190
bogdanm 92:4fc01daae5a5 191 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
bogdanm 86:04dd9b1680ae 192 * @{
bogdanm 86:04dd9b1680ae 193 */
bogdanm 86:04dd9b1680ae 194 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
bogdanm 86:04dd9b1680ae 195 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
bogdanm 86:04dd9b1680ae 196 /**
bogdanm 86:04dd9b1680ae 197 * @}
bogdanm 86:04dd9b1680ae 198 */
bogdanm 86:04dd9b1680ae 199
bogdanm 92:4fc01daae5a5 200 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
bogdanm 86:04dd9b1680ae 201 * @{
bogdanm 86:04dd9b1680ae 202 */
bogdanm 86:04dd9b1680ae 203 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
bogdanm 86:04dd9b1680ae 204 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
bogdanm 86:04dd9b1680ae 205 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
bogdanm 86:04dd9b1680ae 206 /**
bogdanm 86:04dd9b1680ae 207 * @}
bogdanm 86:04dd9b1680ae 208 */
bogdanm 86:04dd9b1680ae 209
bogdanm 92:4fc01daae5a5 210 /** @defgroup DMA_Memory_data_size DMA Memory data size
bogdanm 86:04dd9b1680ae 211 * @{
bogdanm 86:04dd9b1680ae 212 */
bogdanm 86:04dd9b1680ae 213 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
bogdanm 86:04dd9b1680ae 214 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
bogdanm 86:04dd9b1680ae 215 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
bogdanm 86:04dd9b1680ae 216 /**
bogdanm 86:04dd9b1680ae 217 * @}
bogdanm 86:04dd9b1680ae 218 */
bogdanm 86:04dd9b1680ae 219
bogdanm 92:4fc01daae5a5 220 /** @defgroup DMA_mode DMA mode
bogdanm 86:04dd9b1680ae 221 * @{
bogdanm 86:04dd9b1680ae 222 */
Kojto 122:f9eeca106725 223 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
Kojto 122:f9eeca106725 224 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
bogdanm 86:04dd9b1680ae 225 /**
bogdanm 86:04dd9b1680ae 226 * @}
bogdanm 86:04dd9b1680ae 227 */
bogdanm 86:04dd9b1680ae 228
bogdanm 92:4fc01daae5a5 229 /** @defgroup DMA_Priority_level DMA Priority level
bogdanm 86:04dd9b1680ae 230 * @{
bogdanm 86:04dd9b1680ae 231 */
bogdanm 86:04dd9b1680ae 232 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
bogdanm 86:04dd9b1680ae 233 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
bogdanm 86:04dd9b1680ae 234 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
bogdanm 86:04dd9b1680ae 235 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
bogdanm 86:04dd9b1680ae 236 /**
bogdanm 86:04dd9b1680ae 237 * @}
bogdanm 86:04dd9b1680ae 238 */
bogdanm 86:04dd9b1680ae 239
bogdanm 86:04dd9b1680ae 240
bogdanm 92:4fc01daae5a5 241 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
bogdanm 86:04dd9b1680ae 242 * @{
bogdanm 86:04dd9b1680ae 243 */
bogdanm 86:04dd9b1680ae 244 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
bogdanm 86:04dd9b1680ae 245 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
bogdanm 86:04dd9b1680ae 246 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
bogdanm 86:04dd9b1680ae 247 /**
bogdanm 86:04dd9b1680ae 248 * @}
bogdanm 86:04dd9b1680ae 249 */
bogdanm 86:04dd9b1680ae 250
bogdanm 92:4fc01daae5a5 251 /** @defgroup DMA_flag_definitions DMA flag definitions
bogdanm 86:04dd9b1680ae 252 * @{
bogdanm 86:04dd9b1680ae 253 */
bogdanm 86:04dd9b1680ae 254 #define DMA_FLAG_GL1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 255 #define DMA_FLAG_TC1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 256 #define DMA_FLAG_HT1 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 257 #define DMA_FLAG_TE1 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 258 #define DMA_FLAG_GL2 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 259 #define DMA_FLAG_TC2 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 260 #define DMA_FLAG_HT2 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 261 #define DMA_FLAG_TE2 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 262 #define DMA_FLAG_GL3 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 263 #define DMA_FLAG_TC3 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 264 #define DMA_FLAG_HT3 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 265 #define DMA_FLAG_TE3 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 266 #define DMA_FLAG_GL4 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 267 #define DMA_FLAG_TC4 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 268 #define DMA_FLAG_HT4 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 269 #define DMA_FLAG_TE4 ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 270 #define DMA_FLAG_GL5 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 271 #define DMA_FLAG_TC5 ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 272 #define DMA_FLAG_HT5 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 273 #define DMA_FLAG_TE5 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 274 #define DMA_FLAG_GL6 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 275 #define DMA_FLAG_TC6 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 276 #define DMA_FLAG_HT6 ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 277 #define DMA_FLAG_TE6 ((uint32_t)0x00800000)
bogdanm 86:04dd9b1680ae 278 #define DMA_FLAG_GL7 ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 279 #define DMA_FLAG_TC7 ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 280 #define DMA_FLAG_HT7 ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 281 #define DMA_FLAG_TE7 ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 282 /**
bogdanm 86:04dd9b1680ae 283 * @}
bogdanm 86:04dd9b1680ae 284 */
bogdanm 86:04dd9b1680ae 285
bogdanm 86:04dd9b1680ae 286 /**
bogdanm 86:04dd9b1680ae 287 * @}
bogdanm 86:04dd9b1680ae 288 */
bogdanm 86:04dd9b1680ae 289
Kojto 122:f9eeca106725 290
Kojto 122:f9eeca106725 291 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 292 /** @defgroup DMA_Exported_Macros DMA Exported Macros
bogdanm 92:4fc01daae5a5 293 * @{
bogdanm 92:4fc01daae5a5 294 */
bogdanm 86:04dd9b1680ae 295
bogdanm 86:04dd9b1680ae 296 /** @brief Reset DMA handle state
bogdanm 86:04dd9b1680ae 297 * @param __HANDLE__: DMA handle.
bogdanm 86:04dd9b1680ae 298 * @retval None
bogdanm 86:04dd9b1680ae 299 */
bogdanm 86:04dd9b1680ae 300 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
bogdanm 86:04dd9b1680ae 301
bogdanm 86:04dd9b1680ae 302 /**
bogdanm 86:04dd9b1680ae 303 * @brief Enable the specified DMA Channel.
bogdanm 86:04dd9b1680ae 304 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 305 * @retval None.
bogdanm 86:04dd9b1680ae 306 */
Kojto 122:f9eeca106725 307 #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
bogdanm 86:04dd9b1680ae 308
bogdanm 86:04dd9b1680ae 309 /**
bogdanm 86:04dd9b1680ae 310 * @brief Disable the specified DMA Channel.
bogdanm 86:04dd9b1680ae 311 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 312 * @retval None.
bogdanm 86:04dd9b1680ae 313 */
Kojto 122:f9eeca106725 314 #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
bogdanm 86:04dd9b1680ae 315
bogdanm 86:04dd9b1680ae 316
bogdanm 86:04dd9b1680ae 317 /* Interrupt & Flag management */
bogdanm 86:04dd9b1680ae 318
bogdanm 86:04dd9b1680ae 319 /**
bogdanm 86:04dd9b1680ae 320 * @brief Enables the specified DMA Channel interrupts.
bogdanm 86:04dd9b1680ae 321 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 322 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 86:04dd9b1680ae 323 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 324 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 86:04dd9b1680ae 325 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 86:04dd9b1680ae 326 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 86:04dd9b1680ae 327 * @retval None
bogdanm 86:04dd9b1680ae 328 */
Kojto 122:f9eeca106725 329 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
bogdanm 86:04dd9b1680ae 330
bogdanm 86:04dd9b1680ae 331 /**
bogdanm 86:04dd9b1680ae 332 * @brief Disables the specified DMA Channel interrupts.
bogdanm 86:04dd9b1680ae 333 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 334 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 86:04dd9b1680ae 335 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 336 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 86:04dd9b1680ae 337 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 86:04dd9b1680ae 338 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 86:04dd9b1680ae 339 * @retval None
bogdanm 86:04dd9b1680ae 340 */
Kojto 122:f9eeca106725 341 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
bogdanm 86:04dd9b1680ae 342
bogdanm 86:04dd9b1680ae 343 /**
Kojto 122:f9eeca106725 344 * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
bogdanm 86:04dd9b1680ae 345 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 346 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
bogdanm 86:04dd9b1680ae 347 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 348 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 86:04dd9b1680ae 349 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 86:04dd9b1680ae 350 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 86:04dd9b1680ae 351 * @retval The state of DMA_IT (SET or RESET).
bogdanm 86:04dd9b1680ae 352 */
bogdanm 86:04dd9b1680ae 353 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 86:04dd9b1680ae 354
bogdanm 92:4fc01daae5a5 355 /**
Kojto 122:f9eeca106725 356 * @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
Kojto 122:f9eeca106725 357 * @param __HANDLE__: DMA handle
Kojto 122:f9eeca106725 358 *
Kojto 122:f9eeca106725 359 * @retval The number of remaining data units in the current DMA Channel transfer.
Kojto 122:f9eeca106725 360 */
Kojto 122:f9eeca106725 361 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
Kojto 122:f9eeca106725 362
Kojto 122:f9eeca106725 363 /**
bogdanm 92:4fc01daae5a5 364 * @}
bogdanm 92:4fc01daae5a5 365 */
bogdanm 92:4fc01daae5a5 366
bogdanm 92:4fc01daae5a5 367 /* Include DMA HAL Extended module */
bogdanm 86:04dd9b1680ae 368 #include "stm32f3xx_hal_dma_ex.h"
bogdanm 86:04dd9b1680ae 369
bogdanm 86:04dd9b1680ae 370 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 371 /** @addtogroup DMA_Exported_Functions DMA Exported Functions
bogdanm 92:4fc01daae5a5 372 * @{
bogdanm 92:4fc01daae5a5 373 */
bogdanm 92:4fc01daae5a5 374
bogdanm 92:4fc01daae5a5 375 /** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 92:4fc01daae5a5 376 * @{
bogdanm 92:4fc01daae5a5 377 */
bogdanm 86:04dd9b1680ae 378 /* Initialization and de-initialization functions *****************************/
Kojto 122:f9eeca106725 379 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 380 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 381 /**
bogdanm 92:4fc01daae5a5 382 * @}
bogdanm 92:4fc01daae5a5 383 */
bogdanm 92:4fc01daae5a5 384
bogdanm 92:4fc01daae5a5 385 /** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
bogdanm 92:4fc01daae5a5 386 * @{
bogdanm 92:4fc01daae5a5 387 */
bogdanm 86:04dd9b1680ae 388 /* IO operation functions *****************************************************/
bogdanm 86:04dd9b1680ae 389 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 86:04dd9b1680ae 390 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 86:04dd9b1680ae 391 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 392 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 393 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
bogdanm 86:04dd9b1680ae 394 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 395 /**
bogdanm 92:4fc01daae5a5 396 * @}
bogdanm 92:4fc01daae5a5 397 */
bogdanm 92:4fc01daae5a5 398
bogdanm 92:4fc01daae5a5 399 /** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
bogdanm 92:4fc01daae5a5 400 * @{
bogdanm 92:4fc01daae5a5 401 */
bogdanm 86:04dd9b1680ae 402 /* Peripheral State and Error functions ***************************************/
bogdanm 86:04dd9b1680ae 403 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 404 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 405 /**
bogdanm 86:04dd9b1680ae 406 * @}
bogdanm 92:4fc01daae5a5 407 */
bogdanm 92:4fc01daae5a5 408
bogdanm 92:4fc01daae5a5 409 /**
bogdanm 92:4fc01daae5a5 410 * @}
bogdanm 92:4fc01daae5a5 411 */
Kojto 122:f9eeca106725 412 /* Private macros ------------------------------------------------------------*/
Kojto 122:f9eeca106725 413 /** @defgroup DMA_Private_Macros DMA Private Macros
Kojto 122:f9eeca106725 414 * @brief DMA private macros
Kojto 122:f9eeca106725 415 * @{
Kojto 122:f9eeca106725 416 */
Kojto 122:f9eeca106725 417
Kojto 122:f9eeca106725 418 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
Kojto 122:f9eeca106725 419
Kojto 122:f9eeca106725 420 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
Kojto 122:f9eeca106725 421 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
Kojto 122:f9eeca106725 422 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
Kojto 122:f9eeca106725 423
Kojto 122:f9eeca106725 424 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
Kojto 122:f9eeca106725 425 ((STATE) == DMA_PINC_DISABLE))
Kojto 122:f9eeca106725 426
Kojto 122:f9eeca106725 427 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
Kojto 122:f9eeca106725 428 ((STATE) == DMA_MINC_DISABLE))
Kojto 122:f9eeca106725 429
Kojto 122:f9eeca106725 430 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
Kojto 122:f9eeca106725 431 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
Kojto 122:f9eeca106725 432 ((SIZE) == DMA_PDATAALIGN_WORD))
Kojto 122:f9eeca106725 433
Kojto 122:f9eeca106725 434 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
Kojto 122:f9eeca106725 435 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
Kojto 122:f9eeca106725 436 ((SIZE) == DMA_MDATAALIGN_WORD ))
Kojto 122:f9eeca106725 437
Kojto 122:f9eeca106725 438 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
Kojto 122:f9eeca106725 439 ((MODE) == DMA_CIRCULAR))
Kojto 122:f9eeca106725 440
Kojto 122:f9eeca106725 441 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
Kojto 122:f9eeca106725 442 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
Kojto 122:f9eeca106725 443 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
Kojto 122:f9eeca106725 444 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
Kojto 122:f9eeca106725 445
Kojto 122:f9eeca106725 446 /**
Kojto 122:f9eeca106725 447 * @}
Kojto 122:f9eeca106725 448 */
Kojto 122:f9eeca106725 449
bogdanm 92:4fc01daae5a5 450
bogdanm 92:4fc01daae5a5 451 /**
bogdanm 92:4fc01daae5a5 452 * @}
bogdanm 86:04dd9b1680ae 453 */
bogdanm 86:04dd9b1680ae 454
bogdanm 86:04dd9b1680ae 455 /**
bogdanm 86:04dd9b1680ae 456 * @}
bogdanm 86:04dd9b1680ae 457 */
bogdanm 86:04dd9b1680ae 458
bogdanm 86:04dd9b1680ae 459 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 460 }
bogdanm 86:04dd9b1680ae 461 #endif
bogdanm 86:04dd9b1680ae 462
bogdanm 86:04dd9b1680ae 463 #endif /* __STM32F3xx_HAL_DMA_H */
bogdanm 86:04dd9b1680ae 464
bogdanm 86:04dd9b1680ae 465 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/