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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MOTE_L152RC/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_sram.h@128:9bcdf88f62b0, 2016-10-27 (annotated)

Committer:
<>
Date:
Thu Oct 27 16:45:56 2016 +0100
Revision:
128:9bcdf88f62b0
Child:
165:d1b4690b3f8b
Release 128 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



2966: Add kw24 support https://github.com/ARMmbed/mbed-os/pull/2966

3068: MultiTech mDot - clean up PeripheralPins.c and add new pin names https://github.com/ARMmbed/mbed-os/pull/3068

3089: Kinetis HAL: Remove clock initialization code from serial and ticker  https://github.com/ARMmbed/mbed-os/pull/3089

2943: [NRF5] NVIC_SetVector functionality https://github.com/ARMmbed/mbed-os/pull/2943

2938: InterruptIn changes in NCS36510 HAL. https://github.com/ARMmbed/mbed-os/pull/2938

3108: Fix sleep function for NRF52. https://github.com/ARMmbed/mbed-os/pull/3108

3076: STM32F1: Correct timer master value reading https://github.com/ARMmbed/mbed-os/pull/3076

3085: Add LOWPOWERTIMER capability for NUCLEO_F303ZE https://github.com/ARMmbed/mbed-os/pull/3085

3046: [BEETLE] Update BLE stack on Beetle board https://github.com/ARMmbed/mbed-os/pull/3046

3122: [Silicon Labs] Update of Silicon Labs HAL https://github.com/ARMmbed/mbed-os/pull/3122

3022: OnSemi RAM usage fix https://github.com/ARMmbed/mbed-os/pull/3022

3121: STM32F3: Correct UART4 and UART5 defines when using DEVICE_SERIAL_ASYNCH https://github.com/ARMmbed/mbed-os/pull/3121

3142: Targets- NUMAKER_PFM_NUC47216 remove mbed 2 https://github.com/ARMmbed/mbed-os/pull/3142

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l1xx_hal_sram.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @version V1.2.0
<> 128:9bcdf88f62b0 6 * @date 01-July-2016
<> 128:9bcdf88f62b0 7 * @brief Header file of SRAM HAL module.
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 * @attention
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 12 *
<> 128:9bcdf88f62b0 13 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 14 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 16 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 18 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 19 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 21 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 22 * without specific prior written permission.
<> 128:9bcdf88f62b0 23 *
<> 128:9bcdf88f62b0 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 34 *
<> 128:9bcdf88f62b0 35 ******************************************************************************
<> 128:9bcdf88f62b0 36 */
<> 128:9bcdf88f62b0 37
<> 128:9bcdf88f62b0 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 39 #ifndef __STM32L1xx_HAL_SRAM_H
<> 128:9bcdf88f62b0 40 #define __STM32L1xx_HAL_SRAM_H
<> 128:9bcdf88f62b0 41
<> 128:9bcdf88f62b0 42 #ifdef __cplusplus
<> 128:9bcdf88f62b0 43 extern "C" {
<> 128:9bcdf88f62b0 44 #endif
<> 128:9bcdf88f62b0 45
<> 128:9bcdf88f62b0 46 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 47 #include "stm32l1xx_ll_fsmc.h"
<> 128:9bcdf88f62b0 48
<> 128:9bcdf88f62b0 49 /** @addtogroup STM32L1xx_HAL_Driver
<> 128:9bcdf88f62b0 50 * @{
<> 128:9bcdf88f62b0 51 */
<> 128:9bcdf88f62b0 52
<> 128:9bcdf88f62b0 53 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
<> 128:9bcdf88f62b0 54
<> 128:9bcdf88f62b0 55 /** @addtogroup SRAM
<> 128:9bcdf88f62b0 56 * @{
<> 128:9bcdf88f62b0 57 */
<> 128:9bcdf88f62b0 58
<> 128:9bcdf88f62b0 59 /* Exported typedef ----------------------------------------------------------*/
<> 128:9bcdf88f62b0 60
<> 128:9bcdf88f62b0 61 /** @defgroup SRAM_Exported_Types SRAM Exported Types
<> 128:9bcdf88f62b0 62 * @{
<> 128:9bcdf88f62b0 63 */
<> 128:9bcdf88f62b0 64 /**
<> 128:9bcdf88f62b0 65 * @brief HAL SRAM State structures definition
<> 128:9bcdf88f62b0 66 */
<> 128:9bcdf88f62b0 67 typedef enum
<> 128:9bcdf88f62b0 68 {
<> 128:9bcdf88f62b0 69 HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */
<> 128:9bcdf88f62b0 70 HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */
<> 128:9bcdf88f62b0 71 HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */
<> 128:9bcdf88f62b0 72 HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */
<> 128:9bcdf88f62b0 73 HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */
<> 128:9bcdf88f62b0 74
<> 128:9bcdf88f62b0 75 }HAL_SRAM_StateTypeDef;
<> 128:9bcdf88f62b0 76
<> 128:9bcdf88f62b0 77 /**
<> 128:9bcdf88f62b0 78 * @brief SRAM handle Structure definition
<> 128:9bcdf88f62b0 79 */
<> 128:9bcdf88f62b0 80 typedef struct
<> 128:9bcdf88f62b0 81 {
<> 128:9bcdf88f62b0 82 FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
<> 128:9bcdf88f62b0 83
<> 128:9bcdf88f62b0 84 FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
<> 128:9bcdf88f62b0 85
<> 128:9bcdf88f62b0 86 FSMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
<> 128:9bcdf88f62b0 87
<> 128:9bcdf88f62b0 88 HAL_LockTypeDef Lock; /*!< SRAM locking object */
<> 128:9bcdf88f62b0 89
<> 128:9bcdf88f62b0 90 __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
<> 128:9bcdf88f62b0 91
<> 128:9bcdf88f62b0 92 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
<> 128:9bcdf88f62b0 93
<> 128:9bcdf88f62b0 94 }SRAM_HandleTypeDef;
<> 128:9bcdf88f62b0 95
<> 128:9bcdf88f62b0 96 /**
<> 128:9bcdf88f62b0 97 * @}
<> 128:9bcdf88f62b0 98 */
<> 128:9bcdf88f62b0 99
<> 128:9bcdf88f62b0 100 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 101 /* Exported macro ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 102
<> 128:9bcdf88f62b0 103 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
<> 128:9bcdf88f62b0 104 * @{
<> 128:9bcdf88f62b0 105 */
<> 128:9bcdf88f62b0 106
<> 128:9bcdf88f62b0 107 /** @brief Reset SRAM handle state
<> 128:9bcdf88f62b0 108 * @param __HANDLE__: SRAM handle
<> 128:9bcdf88f62b0 109 * @retval None
<> 128:9bcdf88f62b0 110 */
<> 128:9bcdf88f62b0 111 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
<> 128:9bcdf88f62b0 112
<> 128:9bcdf88f62b0 113 /**
<> 128:9bcdf88f62b0 114 * @}
<> 128:9bcdf88f62b0 115 */
<> 128:9bcdf88f62b0 116
<> 128:9bcdf88f62b0 117 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 118
<> 128:9bcdf88f62b0 119 /** @addtogroup SRAM_Exported_Functions
<> 128:9bcdf88f62b0 120 * @{
<> 128:9bcdf88f62b0 121 */
<> 128:9bcdf88f62b0 122
<> 128:9bcdf88f62b0 123 /** @addtogroup SRAM_Exported_Functions_Group1
<> 128:9bcdf88f62b0 124 * @{
<> 128:9bcdf88f62b0 125 */
<> 128:9bcdf88f62b0 126
<> 128:9bcdf88f62b0 127 /* Initialization/de-initialization functions **********************************/
<> 128:9bcdf88f62b0 128 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
<> 128:9bcdf88f62b0 129 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
<> 128:9bcdf88f62b0 130 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
<> 128:9bcdf88f62b0 131 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
<> 128:9bcdf88f62b0 132
<> 128:9bcdf88f62b0 133 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
<> 128:9bcdf88f62b0 134 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
<> 128:9bcdf88f62b0 135
<> 128:9bcdf88f62b0 136 /**
<> 128:9bcdf88f62b0 137 * @}
<> 128:9bcdf88f62b0 138 */
<> 128:9bcdf88f62b0 139
<> 128:9bcdf88f62b0 140 /** @addtogroup SRAM_Exported_Functions_Group2
<> 128:9bcdf88f62b0 141 * @{
<> 128:9bcdf88f62b0 142 */
<> 128:9bcdf88f62b0 143
<> 128:9bcdf88f62b0 144 /* I/O operation functions *****************************************************/
<> 128:9bcdf88f62b0 145 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
<> 128:9bcdf88f62b0 146 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
<> 128:9bcdf88f62b0 147 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
<> 128:9bcdf88f62b0 148 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
<> 128:9bcdf88f62b0 149 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
<> 128:9bcdf88f62b0 150 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
<> 128:9bcdf88f62b0 151 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
<> 128:9bcdf88f62b0 152 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
<> 128:9bcdf88f62b0 153
<> 128:9bcdf88f62b0 154 /**
<> 128:9bcdf88f62b0 155 * @}
<> 128:9bcdf88f62b0 156 */
<> 128:9bcdf88f62b0 157
<> 128:9bcdf88f62b0 158 /** @addtogroup SRAM_Exported_Functions_Group3
<> 128:9bcdf88f62b0 159 * @{
<> 128:9bcdf88f62b0 160 */
<> 128:9bcdf88f62b0 161
<> 128:9bcdf88f62b0 162 /* SRAM Control functions ******************************************************/
<> 128:9bcdf88f62b0 163 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
<> 128:9bcdf88f62b0 164 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
<> 128:9bcdf88f62b0 165
<> 128:9bcdf88f62b0 166 /**
<> 128:9bcdf88f62b0 167 * @}
<> 128:9bcdf88f62b0 168 */
<> 128:9bcdf88f62b0 169
<> 128:9bcdf88f62b0 170 /** @addtogroup SRAM_Exported_Functions_Group4
<> 128:9bcdf88f62b0 171 * @{
<> 128:9bcdf88f62b0 172 */
<> 128:9bcdf88f62b0 173
<> 128:9bcdf88f62b0 174 /* SRAM State functions *********************************************************/
<> 128:9bcdf88f62b0 175 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
<> 128:9bcdf88f62b0 176
<> 128:9bcdf88f62b0 177 /**
<> 128:9bcdf88f62b0 178 * @}
<> 128:9bcdf88f62b0 179 */
<> 128:9bcdf88f62b0 180
<> 128:9bcdf88f62b0 181 /**
<> 128:9bcdf88f62b0 182 * @}
<> 128:9bcdf88f62b0 183 */
<> 128:9bcdf88f62b0 184
<> 128:9bcdf88f62b0 185 /**
<> 128:9bcdf88f62b0 186 * @}
<> 128:9bcdf88f62b0 187 */
<> 128:9bcdf88f62b0 188
<> 128:9bcdf88f62b0 189 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
<> 128:9bcdf88f62b0 190
<> 128:9bcdf88f62b0 191 /**
<> 128:9bcdf88f62b0 192 * @}
<> 128:9bcdf88f62b0 193 */
<> 128:9bcdf88f62b0 194
<> 128:9bcdf88f62b0 195 #ifdef __cplusplus
<> 128:9bcdf88f62b0 196 }
<> 128:9bcdf88f62b0 197 #endif
<> 128:9bcdf88f62b0 198
<> 128:9bcdf88f62b0 199 #endif /* __STM32L1xx_HAL_SRAM_H */
<> 128:9bcdf88f62b0 200
<> 128:9bcdf88f62b0 201 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/