mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32LG_STK3600/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_uart.h@128:9bcdf88f62b0, 2016-10-27 (annotated)

Committer:
<>
Date:
Thu Oct 27 16:45:56 2016 +0100
Revision:
128:9bcdf88f62b0
Child:
139:856d2700e60b
Release 128 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



2966: Add kw24 support https://github.com/ARMmbed/mbed-os/pull/2966

3068: MultiTech mDot - clean up PeripheralPins.c and add new pin names https://github.com/ARMmbed/mbed-os/pull/3068

3089: Kinetis HAL: Remove clock initialization code from serial and ticker  https://github.com/ARMmbed/mbed-os/pull/3089

2943: [NRF5] NVIC_SetVector functionality https://github.com/ARMmbed/mbed-os/pull/2943

2938: InterruptIn changes in NCS36510 HAL. https://github.com/ARMmbed/mbed-os/pull/2938

3108: Fix sleep function for NRF52. https://github.com/ARMmbed/mbed-os/pull/3108

3076: STM32F1: Correct timer master value reading https://github.com/ARMmbed/mbed-os/pull/3076

3085: Add LOWPOWERTIMER capability for NUCLEO_F303ZE https://github.com/ARMmbed/mbed-os/pull/3085

3046: [BEETLE] Update BLE stack on Beetle board https://github.com/ARMmbed/mbed-os/pull/3046

3122: [Silicon Labs] Update of Silicon Labs HAL https://github.com/ARMmbed/mbed-os/pull/3122

3022: OnSemi RAM usage fix https://github.com/ARMmbed/mbed-os/pull/3022

3121: STM32F3: Correct UART4 and UART5 defines when using DEVICE_SERIAL_ASYNCH https://github.com/ARMmbed/mbed-os/pull/3121

3142: Targets- NUMAKER_PFM_NUC47216 remove mbed 2 https://github.com/ARMmbed/mbed-os/pull/3142

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**************************************************************************//**
<> 128:9bcdf88f62b0 2 * @file efm32lg_uart.h
<> 128:9bcdf88f62b0 3 * @brief EFM32LG_UART register and bit field definitions
<> 128:9bcdf88f62b0 4 * @version 5.0.0
<> 128:9bcdf88f62b0 5 ******************************************************************************
<> 128:9bcdf88f62b0 6 * @section License
<> 128:9bcdf88f62b0 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 *
<> 128:9bcdf88f62b0 10 * Permission is granted to anyone to use this software for any purpose,
<> 128:9bcdf88f62b0 11 * including commercial applications, and to alter it and redistribute it
<> 128:9bcdf88f62b0 12 * freely, subject to the following restrictions:
<> 128:9bcdf88f62b0 13 *
<> 128:9bcdf88f62b0 14 * 1. The origin of this software must not be misrepresented; you must not
<> 128:9bcdf88f62b0 15 * claim that you wrote the original software.@n
<> 128:9bcdf88f62b0 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 128:9bcdf88f62b0 17 * misrepresented as being the original software.@n
<> 128:9bcdf88f62b0 18 * 3. This notice may not be removed or altered from any source distribution.
<> 128:9bcdf88f62b0 19 *
<> 128:9bcdf88f62b0 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 128:9bcdf88f62b0 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 128:9bcdf88f62b0 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 128:9bcdf88f62b0 23 * kind, including, but not limited to, any implied warranties of
<> 128:9bcdf88f62b0 24 * merchantability or fitness for any particular purpose or warranties against
<> 128:9bcdf88f62b0 25 * infringement of any proprietary rights of a third party.
<> 128:9bcdf88f62b0 26 *
<> 128:9bcdf88f62b0 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 128:9bcdf88f62b0 28 * incidental, or special damages, or any other relief, or for any claim by
<> 128:9bcdf88f62b0 29 * any third party, arising from your use of this Software.
<> 128:9bcdf88f62b0 30 *
<> 128:9bcdf88f62b0 31 *****************************************************************************/
<> 128:9bcdf88f62b0 32 /**************************************************************************//**
<> 128:9bcdf88f62b0 33 * @addtogroup Parts
<> 128:9bcdf88f62b0 34 * @{
<> 128:9bcdf88f62b0 35 ******************************************************************************/
<> 128:9bcdf88f62b0 36
<> 128:9bcdf88f62b0 37 /**************************************************************************//**
<> 128:9bcdf88f62b0 38 * @defgroup EFM32LG_UART_BitFields
<> 128:9bcdf88f62b0 39 * @{
<> 128:9bcdf88f62b0 40 *****************************************************************************/
<> 128:9bcdf88f62b0 41
<> 128:9bcdf88f62b0 42 /* Bit fields for UART CTRL */
<> 128:9bcdf88f62b0 43 #define _UART_CTRL_RESETVALUE 0x00000000UL /**< Default value for UART_CTRL */
<> 128:9bcdf88f62b0 44 #define _UART_CTRL_MASK 0xFFFFFF7FUL /**< Mask for UART_CTRL */
<> 128:9bcdf88f62b0 45 #define UART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */
<> 128:9bcdf88f62b0 46 #define _UART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */
<> 128:9bcdf88f62b0 47 #define _UART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */
<> 128:9bcdf88f62b0 48 #define _UART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 49 #define UART_CTRL_SYNC_DEFAULT (_UART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 50 #define UART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */
<> 128:9bcdf88f62b0 51 #define _UART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */
<> 128:9bcdf88f62b0 52 #define _UART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */
<> 128:9bcdf88f62b0 53 #define _UART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 54 #define UART_CTRL_LOOPBK_DEFAULT (_UART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 55 #define UART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */
<> 128:9bcdf88f62b0 56 #define _UART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */
<> 128:9bcdf88f62b0 57 #define _UART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */
<> 128:9bcdf88f62b0 58 #define _UART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 59 #define UART_CTRL_CCEN_DEFAULT (_UART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 60 #define UART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */
<> 128:9bcdf88f62b0 61 #define _UART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */
<> 128:9bcdf88f62b0 62 #define _UART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */
<> 128:9bcdf88f62b0 63 #define _UART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 64 #define UART_CTRL_MPM_DEFAULT (_UART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 65 #define UART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */
<> 128:9bcdf88f62b0 66 #define _UART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */
<> 128:9bcdf88f62b0 67 #define _UART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */
<> 128:9bcdf88f62b0 68 #define _UART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 69 #define UART_CTRL_MPAB_DEFAULT (_UART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 70 #define _UART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */
<> 128:9bcdf88f62b0 71 #define _UART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */
<> 128:9bcdf88f62b0 72 #define _UART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 73 #define _UART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for UART_CTRL */
<> 128:9bcdf88f62b0 74 #define _UART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for UART_CTRL */
<> 128:9bcdf88f62b0 75 #define _UART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for UART_CTRL */
<> 128:9bcdf88f62b0 76 #define _UART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for UART_CTRL */
<> 128:9bcdf88f62b0 77 #define UART_CTRL_OVS_DEFAULT (_UART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 78 #define UART_CTRL_OVS_X16 (_UART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for UART_CTRL */
<> 128:9bcdf88f62b0 79 #define UART_CTRL_OVS_X8 (_UART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for UART_CTRL */
<> 128:9bcdf88f62b0 80 #define UART_CTRL_OVS_X6 (_UART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for UART_CTRL */
<> 128:9bcdf88f62b0 81 #define UART_CTRL_OVS_X4 (_UART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for UART_CTRL */
<> 128:9bcdf88f62b0 82 #define UART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */
<> 128:9bcdf88f62b0 83 #define _UART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */
<> 128:9bcdf88f62b0 84 #define _UART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */
<> 128:9bcdf88f62b0 85 #define _UART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 86 #define _UART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for UART_CTRL */
<> 128:9bcdf88f62b0 87 #define _UART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for UART_CTRL */
<> 128:9bcdf88f62b0 88 #define UART_CTRL_CLKPOL_DEFAULT (_UART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 89 #define UART_CTRL_CLKPOL_IDLELOW (_UART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for UART_CTRL */
<> 128:9bcdf88f62b0 90 #define UART_CTRL_CLKPOL_IDLEHIGH (_UART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for UART_CTRL */
<> 128:9bcdf88f62b0 91 #define UART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */
<> 128:9bcdf88f62b0 92 #define _UART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */
<> 128:9bcdf88f62b0 93 #define _UART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */
<> 128:9bcdf88f62b0 94 #define _UART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 95 #define _UART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for UART_CTRL */
<> 128:9bcdf88f62b0 96 #define _UART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for UART_CTRL */
<> 128:9bcdf88f62b0 97 #define UART_CTRL_CLKPHA_DEFAULT (_UART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 98 #define UART_CTRL_CLKPHA_SAMPLELEADING (_UART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for UART_CTRL */
<> 128:9bcdf88f62b0 99 #define UART_CTRL_CLKPHA_SAMPLETRAILING (_UART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for UART_CTRL */
<> 128:9bcdf88f62b0 100 #define UART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */
<> 128:9bcdf88f62b0 101 #define _UART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */
<> 128:9bcdf88f62b0 102 #define _UART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */
<> 128:9bcdf88f62b0 103 #define _UART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 104 #define UART_CTRL_MSBF_DEFAULT (_UART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 105 #define UART_CTRL_CSMA (0x1UL << 11) /**< Action On Slave-Select In Master Mode */
<> 128:9bcdf88f62b0 106 #define _UART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */
<> 128:9bcdf88f62b0 107 #define _UART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */
<> 128:9bcdf88f62b0 108 #define _UART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 109 #define _UART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for UART_CTRL */
<> 128:9bcdf88f62b0 110 #define _UART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for UART_CTRL */
<> 128:9bcdf88f62b0 111 #define UART_CTRL_CSMA_DEFAULT (_UART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 112 #define UART_CTRL_CSMA_NOACTION (_UART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for UART_CTRL */
<> 128:9bcdf88f62b0 113 #define UART_CTRL_CSMA_GOTOSLAVEMODE (_UART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for UART_CTRL */
<> 128:9bcdf88f62b0 114 #define UART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */
<> 128:9bcdf88f62b0 115 #define _UART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */
<> 128:9bcdf88f62b0 116 #define _UART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */
<> 128:9bcdf88f62b0 117 #define _UART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 118 #define _UART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for UART_CTRL */
<> 128:9bcdf88f62b0 119 #define _UART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for UART_CTRL */
<> 128:9bcdf88f62b0 120 #define UART_CTRL_TXBIL_DEFAULT (_UART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 121 #define UART_CTRL_TXBIL_EMPTY (_UART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for UART_CTRL */
<> 128:9bcdf88f62b0 122 #define UART_CTRL_TXBIL_HALFFULL (_UART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for UART_CTRL */
<> 128:9bcdf88f62b0 123 #define UART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */
<> 128:9bcdf88f62b0 124 #define _UART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */
<> 128:9bcdf88f62b0 125 #define _UART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */
<> 128:9bcdf88f62b0 126 #define _UART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 127 #define UART_CTRL_RXINV_DEFAULT (_UART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 128 #define UART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */
<> 128:9bcdf88f62b0 129 #define _UART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */
<> 128:9bcdf88f62b0 130 #define _UART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */
<> 128:9bcdf88f62b0 131 #define _UART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 132 #define UART_CTRL_TXINV_DEFAULT (_UART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 133 #define UART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */
<> 128:9bcdf88f62b0 134 #define _UART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */
<> 128:9bcdf88f62b0 135 #define _UART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */
<> 128:9bcdf88f62b0 136 #define _UART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 137 #define UART_CTRL_CSINV_DEFAULT (_UART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 138 #define UART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */
<> 128:9bcdf88f62b0 139 #define _UART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */
<> 128:9bcdf88f62b0 140 #define _UART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */
<> 128:9bcdf88f62b0 141 #define _UART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 142 #define UART_CTRL_AUTOCS_DEFAULT (_UART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 143 #define UART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */
<> 128:9bcdf88f62b0 144 #define _UART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */
<> 128:9bcdf88f62b0 145 #define _UART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */
<> 128:9bcdf88f62b0 146 #define _UART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 147 #define UART_CTRL_AUTOTRI_DEFAULT (_UART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 148 #define UART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */
<> 128:9bcdf88f62b0 149 #define _UART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */
<> 128:9bcdf88f62b0 150 #define _UART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */
<> 128:9bcdf88f62b0 151 #define _UART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 152 #define UART_CTRL_SCMODE_DEFAULT (_UART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 153 #define UART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */
<> 128:9bcdf88f62b0 154 #define _UART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */
<> 128:9bcdf88f62b0 155 #define _UART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */
<> 128:9bcdf88f62b0 156 #define _UART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 157 #define UART_CTRL_SCRETRANS_DEFAULT (_UART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 158 #define UART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */
<> 128:9bcdf88f62b0 159 #define _UART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */
<> 128:9bcdf88f62b0 160 #define _UART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */
<> 128:9bcdf88f62b0 161 #define _UART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 162 #define UART_CTRL_SKIPPERRF_DEFAULT (_UART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 163 #define UART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */
<> 128:9bcdf88f62b0 164 #define _UART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */
<> 128:9bcdf88f62b0 165 #define _UART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */
<> 128:9bcdf88f62b0 166 #define _UART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 167 #define UART_CTRL_BIT8DV_DEFAULT (_UART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 168 #define UART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */
<> 128:9bcdf88f62b0 169 #define _UART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */
<> 128:9bcdf88f62b0 170 #define _UART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */
<> 128:9bcdf88f62b0 171 #define _UART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 172 #define UART_CTRL_ERRSDMA_DEFAULT (_UART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 173 #define UART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */
<> 128:9bcdf88f62b0 174 #define _UART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */
<> 128:9bcdf88f62b0 175 #define _UART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */
<> 128:9bcdf88f62b0 176 #define _UART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 177 #define UART_CTRL_ERRSRX_DEFAULT (_UART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 178 #define UART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */
<> 128:9bcdf88f62b0 179 #define _UART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */
<> 128:9bcdf88f62b0 180 #define _UART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */
<> 128:9bcdf88f62b0 181 #define _UART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 182 #define UART_CTRL_ERRSTX_DEFAULT (_UART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 183 #define UART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */
<> 128:9bcdf88f62b0 184 #define _UART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */
<> 128:9bcdf88f62b0 185 #define _UART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */
<> 128:9bcdf88f62b0 186 #define _UART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 187 #define UART_CTRL_SSSEARLY_DEFAULT (_UART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 188 #define _UART_CTRL_TXDELAY_SHIFT 26 /**< Shift value for USART_TXDELAY */
<> 128:9bcdf88f62b0 189 #define _UART_CTRL_TXDELAY_MASK 0xC000000UL /**< Bit mask for USART_TXDELAY */
<> 128:9bcdf88f62b0 190 #define _UART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 191 #define _UART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for UART_CTRL */
<> 128:9bcdf88f62b0 192 #define _UART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for UART_CTRL */
<> 128:9bcdf88f62b0 193 #define _UART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for UART_CTRL */
<> 128:9bcdf88f62b0 194 #define _UART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for UART_CTRL */
<> 128:9bcdf88f62b0 195 #define UART_CTRL_TXDELAY_DEFAULT (_UART_CTRL_TXDELAY_DEFAULT << 26) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 196 #define UART_CTRL_TXDELAY_NONE (_UART_CTRL_TXDELAY_NONE << 26) /**< Shifted mode NONE for UART_CTRL */
<> 128:9bcdf88f62b0 197 #define UART_CTRL_TXDELAY_SINGLE (_UART_CTRL_TXDELAY_SINGLE << 26) /**< Shifted mode SINGLE for UART_CTRL */
<> 128:9bcdf88f62b0 198 #define UART_CTRL_TXDELAY_DOUBLE (_UART_CTRL_TXDELAY_DOUBLE << 26) /**< Shifted mode DOUBLE for UART_CTRL */
<> 128:9bcdf88f62b0 199 #define UART_CTRL_TXDELAY_TRIPLE (_UART_CTRL_TXDELAY_TRIPLE << 26) /**< Shifted mode TRIPLE for UART_CTRL */
<> 128:9bcdf88f62b0 200 #define UART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */
<> 128:9bcdf88f62b0 201 #define _UART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */
<> 128:9bcdf88f62b0 202 #define _UART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */
<> 128:9bcdf88f62b0 203 #define _UART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 204 #define UART_CTRL_BYTESWAP_DEFAULT (_UART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 205 #define UART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */
<> 128:9bcdf88f62b0 206 #define _UART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */
<> 128:9bcdf88f62b0 207 #define _UART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */
<> 128:9bcdf88f62b0 208 #define _UART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 209 #define UART_CTRL_AUTOTX_DEFAULT (_UART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 210 #define UART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */
<> 128:9bcdf88f62b0 211 #define _UART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */
<> 128:9bcdf88f62b0 212 #define _UART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */
<> 128:9bcdf88f62b0 213 #define _UART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 214 #define UART_CTRL_MVDIS_DEFAULT (_UART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 215 #define UART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */
<> 128:9bcdf88f62b0 216 #define _UART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */
<> 128:9bcdf88f62b0 217 #define _UART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */
<> 128:9bcdf88f62b0 218 #define _UART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 219 #define UART_CTRL_SMSDELAY_DEFAULT (_UART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_CTRL */
<> 128:9bcdf88f62b0 220
<> 128:9bcdf88f62b0 221 /* Bit fields for UART FRAME */
<> 128:9bcdf88f62b0 222 #define _UART_FRAME_RESETVALUE 0x00001005UL /**< Default value for UART_FRAME */
<> 128:9bcdf88f62b0 223 #define _UART_FRAME_MASK 0x0000330FUL /**< Mask for UART_FRAME */
<> 128:9bcdf88f62b0 224 #define _UART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */
<> 128:9bcdf88f62b0 225 #define _UART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */
<> 128:9bcdf88f62b0 226 #define _UART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for UART_FRAME */
<> 128:9bcdf88f62b0 227 #define _UART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for UART_FRAME */
<> 128:9bcdf88f62b0 228 #define _UART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for UART_FRAME */
<> 128:9bcdf88f62b0 229 #define _UART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for UART_FRAME */
<> 128:9bcdf88f62b0 230 #define _UART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for UART_FRAME */
<> 128:9bcdf88f62b0 231 #define _UART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for UART_FRAME */
<> 128:9bcdf88f62b0 232 #define _UART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for UART_FRAME */
<> 128:9bcdf88f62b0 233 #define _UART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for UART_FRAME */
<> 128:9bcdf88f62b0 234 #define _UART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for UART_FRAME */
<> 128:9bcdf88f62b0 235 #define _UART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for UART_FRAME */
<> 128:9bcdf88f62b0 236 #define _UART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for UART_FRAME */
<> 128:9bcdf88f62b0 237 #define _UART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for UART_FRAME */
<> 128:9bcdf88f62b0 238 #define _UART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for UART_FRAME */
<> 128:9bcdf88f62b0 239 #define _UART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for UART_FRAME */
<> 128:9bcdf88f62b0 240 #define UART_FRAME_DATABITS_FOUR (_UART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for UART_FRAME */
<> 128:9bcdf88f62b0 241 #define UART_FRAME_DATABITS_FIVE (_UART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for UART_FRAME */
<> 128:9bcdf88f62b0 242 #define UART_FRAME_DATABITS_SIX (_UART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for UART_FRAME */
<> 128:9bcdf88f62b0 243 #define UART_FRAME_DATABITS_SEVEN (_UART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for UART_FRAME */
<> 128:9bcdf88f62b0 244 #define UART_FRAME_DATABITS_DEFAULT (_UART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_FRAME */
<> 128:9bcdf88f62b0 245 #define UART_FRAME_DATABITS_EIGHT (_UART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for UART_FRAME */
<> 128:9bcdf88f62b0 246 #define UART_FRAME_DATABITS_NINE (_UART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for UART_FRAME */
<> 128:9bcdf88f62b0 247 #define UART_FRAME_DATABITS_TEN (_UART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for UART_FRAME */
<> 128:9bcdf88f62b0 248 #define UART_FRAME_DATABITS_ELEVEN (_UART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for UART_FRAME */
<> 128:9bcdf88f62b0 249 #define UART_FRAME_DATABITS_TWELVE (_UART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for UART_FRAME */
<> 128:9bcdf88f62b0 250 #define UART_FRAME_DATABITS_THIRTEEN (_UART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for UART_FRAME */
<> 128:9bcdf88f62b0 251 #define UART_FRAME_DATABITS_FOURTEEN (_UART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for UART_FRAME */
<> 128:9bcdf88f62b0 252 #define UART_FRAME_DATABITS_FIFTEEN (_UART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for UART_FRAME */
<> 128:9bcdf88f62b0 253 #define UART_FRAME_DATABITS_SIXTEEN (_UART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for UART_FRAME */
<> 128:9bcdf88f62b0 254 #define _UART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */
<> 128:9bcdf88f62b0 255 #define _UART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */
<> 128:9bcdf88f62b0 256 #define _UART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_FRAME */
<> 128:9bcdf88f62b0 257 #define _UART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for UART_FRAME */
<> 128:9bcdf88f62b0 258 #define _UART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for UART_FRAME */
<> 128:9bcdf88f62b0 259 #define _UART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for UART_FRAME */
<> 128:9bcdf88f62b0 260 #define UART_FRAME_PARITY_DEFAULT (_UART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_FRAME */
<> 128:9bcdf88f62b0 261 #define UART_FRAME_PARITY_NONE (_UART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for UART_FRAME */
<> 128:9bcdf88f62b0 262 #define UART_FRAME_PARITY_EVEN (_UART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for UART_FRAME */
<> 128:9bcdf88f62b0 263 #define UART_FRAME_PARITY_ODD (_UART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for UART_FRAME */
<> 128:9bcdf88f62b0 264 #define _UART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */
<> 128:9bcdf88f62b0 265 #define _UART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */
<> 128:9bcdf88f62b0 266 #define _UART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for UART_FRAME */
<> 128:9bcdf88f62b0 267 #define _UART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_FRAME */
<> 128:9bcdf88f62b0 268 #define _UART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for UART_FRAME */
<> 128:9bcdf88f62b0 269 #define _UART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for UART_FRAME */
<> 128:9bcdf88f62b0 270 #define _UART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for UART_FRAME */
<> 128:9bcdf88f62b0 271 #define UART_FRAME_STOPBITS_HALF (_UART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for UART_FRAME */
<> 128:9bcdf88f62b0 272 #define UART_FRAME_STOPBITS_DEFAULT (_UART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_FRAME */
<> 128:9bcdf88f62b0 273 #define UART_FRAME_STOPBITS_ONE (_UART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for UART_FRAME */
<> 128:9bcdf88f62b0 274 #define UART_FRAME_STOPBITS_ONEANDAHALF (_UART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for UART_FRAME */
<> 128:9bcdf88f62b0 275 #define UART_FRAME_STOPBITS_TWO (_UART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for UART_FRAME */
<> 128:9bcdf88f62b0 276
<> 128:9bcdf88f62b0 277 /* Bit fields for UART TRIGCTRL */
<> 128:9bcdf88f62b0 278 #define _UART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 279 #define _UART_TRIGCTRL_MASK 0x00000077UL /**< Mask for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 280 #define _UART_TRIGCTRL_TSEL_SHIFT 0 /**< Shift value for USART_TSEL */
<> 128:9bcdf88f62b0 281 #define _UART_TRIGCTRL_TSEL_MASK 0x7UL /**< Bit mask for USART_TSEL */
<> 128:9bcdf88f62b0 282 #define _UART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 283 #define _UART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 284 #define _UART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 285 #define _UART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 286 #define _UART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 287 #define _UART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 288 #define _UART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 289 #define _UART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 290 #define _UART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 291 #define UART_TRIGCTRL_TSEL_DEFAULT (_UART_TRIGCTRL_TSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 292 #define UART_TRIGCTRL_TSEL_PRSCH0 (_UART_TRIGCTRL_TSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 293 #define UART_TRIGCTRL_TSEL_PRSCH1 (_UART_TRIGCTRL_TSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 294 #define UART_TRIGCTRL_TSEL_PRSCH2 (_UART_TRIGCTRL_TSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 295 #define UART_TRIGCTRL_TSEL_PRSCH3 (_UART_TRIGCTRL_TSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 296 #define UART_TRIGCTRL_TSEL_PRSCH4 (_UART_TRIGCTRL_TSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 297 #define UART_TRIGCTRL_TSEL_PRSCH5 (_UART_TRIGCTRL_TSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 298 #define UART_TRIGCTRL_TSEL_PRSCH6 (_UART_TRIGCTRL_TSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 299 #define UART_TRIGCTRL_TSEL_PRSCH7 (_UART_TRIGCTRL_TSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 300 #define UART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */
<> 128:9bcdf88f62b0 301 #define _UART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */
<> 128:9bcdf88f62b0 302 #define _UART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */
<> 128:9bcdf88f62b0 303 #define _UART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 304 #define UART_TRIGCTRL_RXTEN_DEFAULT (_UART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 305 #define UART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */
<> 128:9bcdf88f62b0 306 #define _UART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */
<> 128:9bcdf88f62b0 307 #define _UART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */
<> 128:9bcdf88f62b0 308 #define _UART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 309 #define UART_TRIGCTRL_TXTEN_DEFAULT (_UART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 310 #define UART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */
<> 128:9bcdf88f62b0 311 #define _UART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */
<> 128:9bcdf88f62b0 312 #define _UART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */
<> 128:9bcdf88f62b0 313 #define _UART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 314 #define UART_TRIGCTRL_AUTOTXTEN_DEFAULT (_UART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_TRIGCTRL */
<> 128:9bcdf88f62b0 315
<> 128:9bcdf88f62b0 316 /* Bit fields for UART CMD */
<> 128:9bcdf88f62b0 317 #define _UART_CMD_RESETVALUE 0x00000000UL /**< Default value for UART_CMD */
<> 128:9bcdf88f62b0 318 #define _UART_CMD_MASK 0x00000FFFUL /**< Mask for UART_CMD */
<> 128:9bcdf88f62b0 319 #define UART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */
<> 128:9bcdf88f62b0 320 #define _UART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */
<> 128:9bcdf88f62b0 321 #define _UART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */
<> 128:9bcdf88f62b0 322 #define _UART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 323 #define UART_CMD_RXEN_DEFAULT (_UART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 324 #define UART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */
<> 128:9bcdf88f62b0 325 #define _UART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */
<> 128:9bcdf88f62b0 326 #define _UART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */
<> 128:9bcdf88f62b0 327 #define _UART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 328 #define UART_CMD_RXDIS_DEFAULT (_UART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 329 #define UART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */
<> 128:9bcdf88f62b0 330 #define _UART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */
<> 128:9bcdf88f62b0 331 #define _UART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */
<> 128:9bcdf88f62b0 332 #define _UART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 333 #define UART_CMD_TXEN_DEFAULT (_UART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 334 #define UART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */
<> 128:9bcdf88f62b0 335 #define _UART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */
<> 128:9bcdf88f62b0 336 #define _UART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */
<> 128:9bcdf88f62b0 337 #define _UART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 338 #define UART_CMD_TXDIS_DEFAULT (_UART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 339 #define UART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */
<> 128:9bcdf88f62b0 340 #define _UART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */
<> 128:9bcdf88f62b0 341 #define _UART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */
<> 128:9bcdf88f62b0 342 #define _UART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 343 #define UART_CMD_MASTEREN_DEFAULT (_UART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 344 #define UART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */
<> 128:9bcdf88f62b0 345 #define _UART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */
<> 128:9bcdf88f62b0 346 #define _UART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */
<> 128:9bcdf88f62b0 347 #define _UART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 348 #define UART_CMD_MASTERDIS_DEFAULT (_UART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 349 #define UART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */
<> 128:9bcdf88f62b0 350 #define _UART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */
<> 128:9bcdf88f62b0 351 #define _UART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */
<> 128:9bcdf88f62b0 352 #define _UART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 353 #define UART_CMD_RXBLOCKEN_DEFAULT (_UART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 354 #define UART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */
<> 128:9bcdf88f62b0 355 #define _UART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */
<> 128:9bcdf88f62b0 356 #define _UART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */
<> 128:9bcdf88f62b0 357 #define _UART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 358 #define UART_CMD_RXBLOCKDIS_DEFAULT (_UART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 359 #define UART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */
<> 128:9bcdf88f62b0 360 #define _UART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */
<> 128:9bcdf88f62b0 361 #define _UART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */
<> 128:9bcdf88f62b0 362 #define _UART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 363 #define UART_CMD_TXTRIEN_DEFAULT (_UART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 364 #define UART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */
<> 128:9bcdf88f62b0 365 #define _UART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */
<> 128:9bcdf88f62b0 366 #define _UART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */
<> 128:9bcdf88f62b0 367 #define _UART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 368 #define UART_CMD_TXTRIDIS_DEFAULT (_UART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 369 #define UART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */
<> 128:9bcdf88f62b0 370 #define _UART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */
<> 128:9bcdf88f62b0 371 #define _UART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */
<> 128:9bcdf88f62b0 372 #define _UART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 373 #define UART_CMD_CLEARTX_DEFAULT (_UART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 374 #define UART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */
<> 128:9bcdf88f62b0 375 #define _UART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */
<> 128:9bcdf88f62b0 376 #define _UART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */
<> 128:9bcdf88f62b0 377 #define _UART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 378 #define UART_CMD_CLEARRX_DEFAULT (_UART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_CMD */
<> 128:9bcdf88f62b0 379
<> 128:9bcdf88f62b0 380 /* Bit fields for UART STATUS */
<> 128:9bcdf88f62b0 381 #define _UART_STATUS_RESETVALUE 0x00000040UL /**< Default value for UART_STATUS */
<> 128:9bcdf88f62b0 382 #define _UART_STATUS_MASK 0x00001FFFUL /**< Mask for UART_STATUS */
<> 128:9bcdf88f62b0 383 #define UART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */
<> 128:9bcdf88f62b0 384 #define _UART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */
<> 128:9bcdf88f62b0 385 #define _UART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */
<> 128:9bcdf88f62b0 386 #define _UART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 387 #define UART_STATUS_RXENS_DEFAULT (_UART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 388 #define UART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */
<> 128:9bcdf88f62b0 389 #define _UART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */
<> 128:9bcdf88f62b0 390 #define _UART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */
<> 128:9bcdf88f62b0 391 #define _UART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 392 #define UART_STATUS_TXENS_DEFAULT (_UART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 393 #define UART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */
<> 128:9bcdf88f62b0 394 #define _UART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */
<> 128:9bcdf88f62b0 395 #define _UART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */
<> 128:9bcdf88f62b0 396 #define _UART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 397 #define UART_STATUS_MASTER_DEFAULT (_UART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 398 #define UART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */
<> 128:9bcdf88f62b0 399 #define _UART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */
<> 128:9bcdf88f62b0 400 #define _UART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */
<> 128:9bcdf88f62b0 401 #define _UART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 402 #define UART_STATUS_RXBLOCK_DEFAULT (_UART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 403 #define UART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */
<> 128:9bcdf88f62b0 404 #define _UART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */
<> 128:9bcdf88f62b0 405 #define _UART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */
<> 128:9bcdf88f62b0 406 #define _UART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 407 #define UART_STATUS_TXTRI_DEFAULT (_UART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 408 #define UART_STATUS_TXC (0x1UL << 5) /**< TX Complete */
<> 128:9bcdf88f62b0 409 #define _UART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */
<> 128:9bcdf88f62b0 410 #define _UART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */
<> 128:9bcdf88f62b0 411 #define _UART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 412 #define UART_STATUS_TXC_DEFAULT (_UART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 413 #define UART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */
<> 128:9bcdf88f62b0 414 #define _UART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */
<> 128:9bcdf88f62b0 415 #define _UART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */
<> 128:9bcdf88f62b0 416 #define _UART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 417 #define UART_STATUS_TXBL_DEFAULT (_UART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 418 #define UART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */
<> 128:9bcdf88f62b0 419 #define _UART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */
<> 128:9bcdf88f62b0 420 #define _UART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */
<> 128:9bcdf88f62b0 421 #define _UART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 422 #define UART_STATUS_RXDATAV_DEFAULT (_UART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 423 #define UART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */
<> 128:9bcdf88f62b0 424 #define _UART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */
<> 128:9bcdf88f62b0 425 #define _UART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */
<> 128:9bcdf88f62b0 426 #define _UART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 427 #define UART_STATUS_RXFULL_DEFAULT (_UART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 428 #define UART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */
<> 128:9bcdf88f62b0 429 #define _UART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */
<> 128:9bcdf88f62b0 430 #define _UART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */
<> 128:9bcdf88f62b0 431 #define _UART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 432 #define UART_STATUS_TXBDRIGHT_DEFAULT (_UART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 433 #define UART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */
<> 128:9bcdf88f62b0 434 #define _UART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */
<> 128:9bcdf88f62b0 435 #define _UART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */
<> 128:9bcdf88f62b0 436 #define _UART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 437 #define UART_STATUS_TXBSRIGHT_DEFAULT (_UART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 438 #define UART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */
<> 128:9bcdf88f62b0 439 #define _UART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */
<> 128:9bcdf88f62b0 440 #define _UART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */
<> 128:9bcdf88f62b0 441 #define _UART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 442 #define UART_STATUS_RXDATAVRIGHT_DEFAULT (_UART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 443 #define UART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */
<> 128:9bcdf88f62b0 444 #define _UART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */
<> 128:9bcdf88f62b0 445 #define _UART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */
<> 128:9bcdf88f62b0 446 #define _UART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 447 #define UART_STATUS_RXFULLRIGHT_DEFAULT (_UART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_STATUS */
<> 128:9bcdf88f62b0 448
<> 128:9bcdf88f62b0 449 /* Bit fields for UART CLKDIV */
<> 128:9bcdf88f62b0 450 #define _UART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for UART_CLKDIV */
<> 128:9bcdf88f62b0 451 #define _UART_CLKDIV_MASK 0x001FFFC0UL /**< Mask for UART_CLKDIV */
<> 128:9bcdf88f62b0 452 #define _UART_CLKDIV_DIV_SHIFT 6 /**< Shift value for USART_DIV */
<> 128:9bcdf88f62b0 453 #define _UART_CLKDIV_DIV_MASK 0x1FFFC0UL /**< Bit mask for USART_DIV */
<> 128:9bcdf88f62b0 454 #define _UART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CLKDIV */
<> 128:9bcdf88f62b0 455 #define UART_CLKDIV_DIV_DEFAULT (_UART_CLKDIV_DIV_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_CLKDIV */
<> 128:9bcdf88f62b0 456
<> 128:9bcdf88f62b0 457 /* Bit fields for UART RXDATAX */
<> 128:9bcdf88f62b0 458 #define _UART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATAX */
<> 128:9bcdf88f62b0 459 #define _UART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for UART_RXDATAX */
<> 128:9bcdf88f62b0 460 #define _UART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
<> 128:9bcdf88f62b0 461 #define _UART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */
<> 128:9bcdf88f62b0 462 #define _UART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */
<> 128:9bcdf88f62b0 463 #define UART_RXDATAX_RXDATA_DEFAULT (_UART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDATAX */
<> 128:9bcdf88f62b0 464 #define UART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */
<> 128:9bcdf88f62b0 465 #define _UART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */
<> 128:9bcdf88f62b0 466 #define _UART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */
<> 128:9bcdf88f62b0 467 #define _UART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */
<> 128:9bcdf88f62b0 468 #define UART_RXDATAX_PERR_DEFAULT (_UART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDATAX */
<> 128:9bcdf88f62b0 469 #define UART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */
<> 128:9bcdf88f62b0 470 #define _UART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */
<> 128:9bcdf88f62b0 471 #define _UART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */
<> 128:9bcdf88f62b0 472 #define _UART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */
<> 128:9bcdf88f62b0 473 #define UART_RXDATAX_FERR_DEFAULT (_UART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDATAX */
<> 128:9bcdf88f62b0 474
<> 128:9bcdf88f62b0 475 /* Bit fields for UART RXDATA */
<> 128:9bcdf88f62b0 476 #define _UART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATA */
<> 128:9bcdf88f62b0 477 #define _UART_RXDATA_MASK 0x000000FFUL /**< Mask for UART_RXDATA */
<> 128:9bcdf88f62b0 478 #define _UART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
<> 128:9bcdf88f62b0 479 #define _UART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */
<> 128:9bcdf88f62b0 480 #define _UART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATA */
<> 128:9bcdf88f62b0 481 #define UART_RXDATA_RXDATA_DEFAULT (_UART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDATA */
<> 128:9bcdf88f62b0 482
<> 128:9bcdf88f62b0 483 /* Bit fields for UART RXDOUBLEX */
<> 128:9bcdf88f62b0 484 #define _UART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLEX */
<> 128:9bcdf88f62b0 485 #define _UART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for UART_RXDOUBLEX */
<> 128:9bcdf88f62b0 486 #define _UART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
<> 128:9bcdf88f62b0 487 #define _UART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */
<> 128:9bcdf88f62b0 488 #define _UART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
<> 128:9bcdf88f62b0 489 #define UART_RXDOUBLEX_RXDATA0_DEFAULT (_UART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
<> 128:9bcdf88f62b0 490 #define UART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */
<> 128:9bcdf88f62b0 491 #define _UART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */
<> 128:9bcdf88f62b0 492 #define _UART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */
<> 128:9bcdf88f62b0 493 #define _UART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
<> 128:9bcdf88f62b0 494 #define UART_RXDOUBLEX_PERR0_DEFAULT (_UART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
<> 128:9bcdf88f62b0 495 #define UART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */
<> 128:9bcdf88f62b0 496 #define _UART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */
<> 128:9bcdf88f62b0 497 #define _UART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */
<> 128:9bcdf88f62b0 498 #define _UART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
<> 128:9bcdf88f62b0 499 #define UART_RXDOUBLEX_FERR0_DEFAULT (_UART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
<> 128:9bcdf88f62b0 500 #define _UART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */
<> 128:9bcdf88f62b0 501 #define _UART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */
<> 128:9bcdf88f62b0 502 #define _UART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
<> 128:9bcdf88f62b0 503 #define UART_RXDOUBLEX_RXDATA1_DEFAULT (_UART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
<> 128:9bcdf88f62b0 504 #define UART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */
<> 128:9bcdf88f62b0 505 #define _UART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */
<> 128:9bcdf88f62b0 506 #define _UART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */
<> 128:9bcdf88f62b0 507 #define _UART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
<> 128:9bcdf88f62b0 508 #define UART_RXDOUBLEX_PERR1_DEFAULT (_UART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
<> 128:9bcdf88f62b0 509 #define UART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */
<> 128:9bcdf88f62b0 510 #define _UART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */
<> 128:9bcdf88f62b0 511 #define _UART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */
<> 128:9bcdf88f62b0 512 #define _UART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
<> 128:9bcdf88f62b0 513 #define UART_RXDOUBLEX_FERR1_DEFAULT (_UART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
<> 128:9bcdf88f62b0 514
<> 128:9bcdf88f62b0 515 /* Bit fields for UART RXDOUBLE */
<> 128:9bcdf88f62b0 516 #define _UART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLE */
<> 128:9bcdf88f62b0 517 #define _UART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for UART_RXDOUBLE */
<> 128:9bcdf88f62b0 518 #define _UART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
<> 128:9bcdf88f62b0 519 #define _UART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */
<> 128:9bcdf88f62b0 520 #define _UART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLE */
<> 128:9bcdf88f62b0 521 #define UART_RXDOUBLE_RXDATA0_DEFAULT (_UART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLE */
<> 128:9bcdf88f62b0 522 #define _UART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */
<> 128:9bcdf88f62b0 523 #define _UART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */
<> 128:9bcdf88f62b0 524 #define _UART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLE */
<> 128:9bcdf88f62b0 525 #define UART_RXDOUBLE_RXDATA1_DEFAULT (_UART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_RXDOUBLE */
<> 128:9bcdf88f62b0 526
<> 128:9bcdf88f62b0 527 /* Bit fields for UART RXDATAXP */
<> 128:9bcdf88f62b0 528 #define _UART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATAXP */
<> 128:9bcdf88f62b0 529 #define _UART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for UART_RXDATAXP */
<> 128:9bcdf88f62b0 530 #define _UART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */
<> 128:9bcdf88f62b0 531 #define _UART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */
<> 128:9bcdf88f62b0 532 #define _UART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */
<> 128:9bcdf88f62b0 533 #define UART_RXDATAXP_RXDATAP_DEFAULT (_UART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDATAXP */
<> 128:9bcdf88f62b0 534 #define UART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */
<> 128:9bcdf88f62b0 535 #define _UART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */
<> 128:9bcdf88f62b0 536 #define _UART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */
<> 128:9bcdf88f62b0 537 #define _UART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */
<> 128:9bcdf88f62b0 538 #define UART_RXDATAXP_PERRP_DEFAULT (_UART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDATAXP */
<> 128:9bcdf88f62b0 539 #define UART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */
<> 128:9bcdf88f62b0 540 #define _UART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */
<> 128:9bcdf88f62b0 541 #define _UART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */
<> 128:9bcdf88f62b0 542 #define _UART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */
<> 128:9bcdf88f62b0 543 #define UART_RXDATAXP_FERRP_DEFAULT (_UART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDATAXP */
<> 128:9bcdf88f62b0 544
<> 128:9bcdf88f62b0 545 /* Bit fields for UART RXDOUBLEXP */
<> 128:9bcdf88f62b0 546 #define _UART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLEXP */
<> 128:9bcdf88f62b0 547 #define _UART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for UART_RXDOUBLEXP */
<> 128:9bcdf88f62b0 548 #define _UART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */
<> 128:9bcdf88f62b0 549 #define _UART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */
<> 128:9bcdf88f62b0 550 #define _UART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
<> 128:9bcdf88f62b0 551 #define UART_RXDOUBLEXP_RXDATAP0_DEFAULT (_UART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
<> 128:9bcdf88f62b0 552 #define UART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */
<> 128:9bcdf88f62b0 553 #define _UART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */
<> 128:9bcdf88f62b0 554 #define _UART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */
<> 128:9bcdf88f62b0 555 #define _UART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
<> 128:9bcdf88f62b0 556 #define UART_RXDOUBLEXP_PERRP0_DEFAULT (_UART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
<> 128:9bcdf88f62b0 557 #define UART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */
<> 128:9bcdf88f62b0 558 #define _UART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */
<> 128:9bcdf88f62b0 559 #define _UART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */
<> 128:9bcdf88f62b0 560 #define _UART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
<> 128:9bcdf88f62b0 561 #define UART_RXDOUBLEXP_FERRP0_DEFAULT (_UART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
<> 128:9bcdf88f62b0 562 #define _UART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */
<> 128:9bcdf88f62b0 563 #define _UART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */
<> 128:9bcdf88f62b0 564 #define _UART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
<> 128:9bcdf88f62b0 565 #define UART_RXDOUBLEXP_RXDATAP1_DEFAULT (_UART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
<> 128:9bcdf88f62b0 566 #define UART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */
<> 128:9bcdf88f62b0 567 #define _UART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */
<> 128:9bcdf88f62b0 568 #define _UART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */
<> 128:9bcdf88f62b0 569 #define _UART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
<> 128:9bcdf88f62b0 570 #define UART_RXDOUBLEXP_PERRP1_DEFAULT (_UART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
<> 128:9bcdf88f62b0 571 #define UART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */
<> 128:9bcdf88f62b0 572 #define _UART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */
<> 128:9bcdf88f62b0 573 #define _UART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */
<> 128:9bcdf88f62b0 574 #define _UART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
<> 128:9bcdf88f62b0 575 #define UART_RXDOUBLEXP_FERRP1_DEFAULT (_UART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
<> 128:9bcdf88f62b0 576
<> 128:9bcdf88f62b0 577 /* Bit fields for UART TXDATAX */
<> 128:9bcdf88f62b0 578 #define _UART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for UART_TXDATAX */
<> 128:9bcdf88f62b0 579 #define _UART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for UART_TXDATAX */
<> 128:9bcdf88f62b0 580 #define _UART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */
<> 128:9bcdf88f62b0 581 #define _UART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */
<> 128:9bcdf88f62b0 582 #define _UART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
<> 128:9bcdf88f62b0 583 #define UART_TXDATAX_TXDATAX_DEFAULT (_UART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDATAX */
<> 128:9bcdf88f62b0 584 #define UART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */
<> 128:9bcdf88f62b0 585 #define _UART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */
<> 128:9bcdf88f62b0 586 #define _UART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */
<> 128:9bcdf88f62b0 587 #define _UART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
<> 128:9bcdf88f62b0 588 #define UART_TXDATAX_UBRXAT_DEFAULT (_UART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_TXDATAX */
<> 128:9bcdf88f62b0 589 #define UART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */
<> 128:9bcdf88f62b0 590 #define _UART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */
<> 128:9bcdf88f62b0 591 #define _UART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */
<> 128:9bcdf88f62b0 592 #define _UART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
<> 128:9bcdf88f62b0 593 #define UART_TXDATAX_TXTRIAT_DEFAULT (_UART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_TXDATAX */
<> 128:9bcdf88f62b0 594 #define UART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */
<> 128:9bcdf88f62b0 595 #define _UART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */
<> 128:9bcdf88f62b0 596 #define _UART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */
<> 128:9bcdf88f62b0 597 #define _UART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
<> 128:9bcdf88f62b0 598 #define UART_TXDATAX_TXBREAK_DEFAULT (_UART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_TXDATAX */
<> 128:9bcdf88f62b0 599 #define UART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */
<> 128:9bcdf88f62b0 600 #define _UART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */
<> 128:9bcdf88f62b0 601 #define _UART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */
<> 128:9bcdf88f62b0 602 #define _UART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
<> 128:9bcdf88f62b0 603 #define UART_TXDATAX_TXDISAT_DEFAULT (_UART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_TXDATAX */
<> 128:9bcdf88f62b0 604 #define UART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */
<> 128:9bcdf88f62b0 605 #define _UART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */
<> 128:9bcdf88f62b0 606 #define _UART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */
<> 128:9bcdf88f62b0 607 #define _UART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
<> 128:9bcdf88f62b0 608 #define UART_TXDATAX_RXENAT_DEFAULT (_UART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_TXDATAX */
<> 128:9bcdf88f62b0 609
<> 128:9bcdf88f62b0 610 /* Bit fields for UART TXDATA */
<> 128:9bcdf88f62b0 611 #define _UART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for UART_TXDATA */
<> 128:9bcdf88f62b0 612 #define _UART_TXDATA_MASK 0x000000FFUL /**< Mask for UART_TXDATA */
<> 128:9bcdf88f62b0 613 #define _UART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */
<> 128:9bcdf88f62b0 614 #define _UART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */
<> 128:9bcdf88f62b0 615 #define _UART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATA */
<> 128:9bcdf88f62b0 616 #define UART_TXDATA_TXDATA_DEFAULT (_UART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDATA */
<> 128:9bcdf88f62b0 617
<> 128:9bcdf88f62b0 618 /* Bit fields for UART TXDOUBLEX */
<> 128:9bcdf88f62b0 619 #define _UART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 620 #define _UART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 621 #define _UART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
<> 128:9bcdf88f62b0 622 #define _UART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */
<> 128:9bcdf88f62b0 623 #define _UART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 624 #define UART_TXDOUBLEX_TXDATA0_DEFAULT (_UART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 625 #define UART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */
<> 128:9bcdf88f62b0 626 #define _UART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */
<> 128:9bcdf88f62b0 627 #define _UART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */
<> 128:9bcdf88f62b0 628 #define _UART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 629 #define UART_TXDOUBLEX_UBRXAT0_DEFAULT (_UART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 630 #define UART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */
<> 128:9bcdf88f62b0 631 #define _UART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */
<> 128:9bcdf88f62b0 632 #define _UART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */
<> 128:9bcdf88f62b0 633 #define _UART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 634 #define UART_TXDOUBLEX_TXTRIAT0_DEFAULT (_UART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 635 #define UART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */
<> 128:9bcdf88f62b0 636 #define _UART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */
<> 128:9bcdf88f62b0 637 #define _UART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */
<> 128:9bcdf88f62b0 638 #define _UART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 639 #define UART_TXDOUBLEX_TXBREAK0_DEFAULT (_UART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 640 #define UART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */
<> 128:9bcdf88f62b0 641 #define _UART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */
<> 128:9bcdf88f62b0 642 #define _UART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */
<> 128:9bcdf88f62b0 643 #define _UART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 644 #define UART_TXDOUBLEX_TXDISAT0_DEFAULT (_UART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 645 #define UART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */
<> 128:9bcdf88f62b0 646 #define _UART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */
<> 128:9bcdf88f62b0 647 #define _UART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */
<> 128:9bcdf88f62b0 648 #define _UART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 649 #define UART_TXDOUBLEX_RXENAT0_DEFAULT (_UART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 650 #define _UART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */
<> 128:9bcdf88f62b0 651 #define _UART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */
<> 128:9bcdf88f62b0 652 #define _UART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 653 #define UART_TXDOUBLEX_TXDATA1_DEFAULT (_UART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 654 #define UART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */
<> 128:9bcdf88f62b0 655 #define _UART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */
<> 128:9bcdf88f62b0 656 #define _UART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */
<> 128:9bcdf88f62b0 657 #define _UART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 658 #define UART_TXDOUBLEX_UBRXAT1_DEFAULT (_UART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 659 #define UART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */
<> 128:9bcdf88f62b0 660 #define _UART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */
<> 128:9bcdf88f62b0 661 #define _UART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */
<> 128:9bcdf88f62b0 662 #define _UART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 663 #define UART_TXDOUBLEX_TXTRIAT1_DEFAULT (_UART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 664 #define UART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */
<> 128:9bcdf88f62b0 665 #define _UART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */
<> 128:9bcdf88f62b0 666 #define _UART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */
<> 128:9bcdf88f62b0 667 #define _UART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 668 #define UART_TXDOUBLEX_TXBREAK1_DEFAULT (_UART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 669 #define UART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */
<> 128:9bcdf88f62b0 670 #define _UART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */
<> 128:9bcdf88f62b0 671 #define _UART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */
<> 128:9bcdf88f62b0 672 #define _UART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 673 #define UART_TXDOUBLEX_TXDISAT1_DEFAULT (_UART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 674 #define UART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */
<> 128:9bcdf88f62b0 675 #define _UART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */
<> 128:9bcdf88f62b0 676 #define _UART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */
<> 128:9bcdf88f62b0 677 #define _UART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 678 #define UART_TXDOUBLEX_RXENAT1_DEFAULT (_UART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
<> 128:9bcdf88f62b0 679
<> 128:9bcdf88f62b0 680 /* Bit fields for UART TXDOUBLE */
<> 128:9bcdf88f62b0 681 #define _UART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for UART_TXDOUBLE */
<> 128:9bcdf88f62b0 682 #define _UART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for UART_TXDOUBLE */
<> 128:9bcdf88f62b0 683 #define _UART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
<> 128:9bcdf88f62b0 684 #define _UART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */
<> 128:9bcdf88f62b0 685 #define _UART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLE */
<> 128:9bcdf88f62b0 686 #define UART_TXDOUBLE_TXDATA0_DEFAULT (_UART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDOUBLE */
<> 128:9bcdf88f62b0 687 #define _UART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */
<> 128:9bcdf88f62b0 688 #define _UART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */
<> 128:9bcdf88f62b0 689 #define _UART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLE */
<> 128:9bcdf88f62b0 690 #define UART_TXDOUBLE_TXDATA1_DEFAULT (_UART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_TXDOUBLE */
<> 128:9bcdf88f62b0 691
<> 128:9bcdf88f62b0 692 /* Bit fields for UART IF */
<> 128:9bcdf88f62b0 693 #define _UART_IF_RESETVALUE 0x00000002UL /**< Default value for UART_IF */
<> 128:9bcdf88f62b0 694 #define _UART_IF_MASK 0x00001FFFUL /**< Mask for UART_IF */
<> 128:9bcdf88f62b0 695 #define UART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */
<> 128:9bcdf88f62b0 696 #define _UART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */
<> 128:9bcdf88f62b0 697 #define _UART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
<> 128:9bcdf88f62b0 698 #define _UART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 699 #define UART_IF_TXC_DEFAULT (_UART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 700 #define UART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */
<> 128:9bcdf88f62b0 701 #define _UART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
<> 128:9bcdf88f62b0 702 #define _UART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
<> 128:9bcdf88f62b0 703 #define _UART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 704 #define UART_IF_TXBL_DEFAULT (_UART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 705 #define UART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */
<> 128:9bcdf88f62b0 706 #define _UART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
<> 128:9bcdf88f62b0 707 #define _UART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
<> 128:9bcdf88f62b0 708 #define _UART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 709 #define UART_IF_RXDATAV_DEFAULT (_UART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 710 #define UART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */
<> 128:9bcdf88f62b0 711 #define _UART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
<> 128:9bcdf88f62b0 712 #define _UART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
<> 128:9bcdf88f62b0 713 #define _UART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 714 #define UART_IF_RXFULL_DEFAULT (_UART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 715 #define UART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */
<> 128:9bcdf88f62b0 716 #define _UART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
<> 128:9bcdf88f62b0 717 #define _UART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
<> 128:9bcdf88f62b0 718 #define _UART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 719 #define UART_IF_RXOF_DEFAULT (_UART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 720 #define UART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */
<> 128:9bcdf88f62b0 721 #define _UART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
<> 128:9bcdf88f62b0 722 #define _UART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
<> 128:9bcdf88f62b0 723 #define _UART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 724 #define UART_IF_RXUF_DEFAULT (_UART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 725 #define UART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */
<> 128:9bcdf88f62b0 726 #define _UART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
<> 128:9bcdf88f62b0 727 #define _UART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
<> 128:9bcdf88f62b0 728 #define _UART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 729 #define UART_IF_TXOF_DEFAULT (_UART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 730 #define UART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */
<> 128:9bcdf88f62b0 731 #define _UART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
<> 128:9bcdf88f62b0 732 #define _UART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
<> 128:9bcdf88f62b0 733 #define _UART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 734 #define UART_IF_TXUF_DEFAULT (_UART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 735 #define UART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */
<> 128:9bcdf88f62b0 736 #define _UART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */
<> 128:9bcdf88f62b0 737 #define _UART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
<> 128:9bcdf88f62b0 738 #define _UART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 739 #define UART_IF_PERR_DEFAULT (_UART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 740 #define UART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */
<> 128:9bcdf88f62b0 741 #define _UART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */
<> 128:9bcdf88f62b0 742 #define _UART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
<> 128:9bcdf88f62b0 743 #define _UART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 744 #define UART_IF_FERR_DEFAULT (_UART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 745 #define UART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */
<> 128:9bcdf88f62b0 746 #define _UART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
<> 128:9bcdf88f62b0 747 #define _UART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
<> 128:9bcdf88f62b0 748 #define _UART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 749 #define UART_IF_MPAF_DEFAULT (_UART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 750 #define UART_IF_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Flag */
<> 128:9bcdf88f62b0 751 #define _UART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */
<> 128:9bcdf88f62b0 752 #define _UART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
<> 128:9bcdf88f62b0 753 #define _UART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 754 #define UART_IF_SSM_DEFAULT (_UART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 755 #define UART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */
<> 128:9bcdf88f62b0 756 #define _UART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */
<> 128:9bcdf88f62b0 757 #define _UART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
<> 128:9bcdf88f62b0 758 #define _UART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 759 #define UART_IF_CCF_DEFAULT (_UART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IF */
<> 128:9bcdf88f62b0 760
<> 128:9bcdf88f62b0 761 /* Bit fields for UART IFS */
<> 128:9bcdf88f62b0 762 #define _UART_IFS_RESETVALUE 0x00000000UL /**< Default value for UART_IFS */
<> 128:9bcdf88f62b0 763 #define _UART_IFS_MASK 0x00001FF9UL /**< Mask for UART_IFS */
<> 128:9bcdf88f62b0 764 #define UART_IFS_TXC (0x1UL << 0) /**< Set TX Complete Interrupt Flag */
<> 128:9bcdf88f62b0 765 #define _UART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */
<> 128:9bcdf88f62b0 766 #define _UART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
<> 128:9bcdf88f62b0 767 #define _UART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 768 #define UART_IFS_TXC_DEFAULT (_UART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 769 #define UART_IFS_RXFULL (0x1UL << 3) /**< Set RX Buffer Full Interrupt Flag */
<> 128:9bcdf88f62b0 770 #define _UART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
<> 128:9bcdf88f62b0 771 #define _UART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
<> 128:9bcdf88f62b0 772 #define _UART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 773 #define UART_IFS_RXFULL_DEFAULT (_UART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 774 #define UART_IFS_RXOF (0x1UL << 4) /**< Set RX Overflow Interrupt Flag */
<> 128:9bcdf88f62b0 775 #define _UART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
<> 128:9bcdf88f62b0 776 #define _UART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
<> 128:9bcdf88f62b0 777 #define _UART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 778 #define UART_IFS_RXOF_DEFAULT (_UART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 779 #define UART_IFS_RXUF (0x1UL << 5) /**< Set RX Underflow Interrupt Flag */
<> 128:9bcdf88f62b0 780 #define _UART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
<> 128:9bcdf88f62b0 781 #define _UART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
<> 128:9bcdf88f62b0 782 #define _UART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 783 #define UART_IFS_RXUF_DEFAULT (_UART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 784 #define UART_IFS_TXOF (0x1UL << 6) /**< Set TX Overflow Interrupt Flag */
<> 128:9bcdf88f62b0 785 #define _UART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
<> 128:9bcdf88f62b0 786 #define _UART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
<> 128:9bcdf88f62b0 787 #define _UART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 788 #define UART_IFS_TXOF_DEFAULT (_UART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 789 #define UART_IFS_TXUF (0x1UL << 7) /**< Set TX Underflow Interrupt Flag */
<> 128:9bcdf88f62b0 790 #define _UART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
<> 128:9bcdf88f62b0 791 #define _UART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
<> 128:9bcdf88f62b0 792 #define _UART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 793 #define UART_IFS_TXUF_DEFAULT (_UART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 794 #define UART_IFS_PERR (0x1UL << 8) /**< Set Parity Error Interrupt Flag */
<> 128:9bcdf88f62b0 795 #define _UART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */
<> 128:9bcdf88f62b0 796 #define _UART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
<> 128:9bcdf88f62b0 797 #define _UART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 798 #define UART_IFS_PERR_DEFAULT (_UART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 799 #define UART_IFS_FERR (0x1UL << 9) /**< Set Framing Error Interrupt Flag */
<> 128:9bcdf88f62b0 800 #define _UART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */
<> 128:9bcdf88f62b0 801 #define _UART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
<> 128:9bcdf88f62b0 802 #define _UART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 803 #define UART_IFS_FERR_DEFAULT (_UART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 804 #define UART_IFS_MPAF (0x1UL << 10) /**< Set Multi-Processor Address Frame Interrupt Flag */
<> 128:9bcdf88f62b0 805 #define _UART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
<> 128:9bcdf88f62b0 806 #define _UART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
<> 128:9bcdf88f62b0 807 #define _UART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 808 #define UART_IFS_MPAF_DEFAULT (_UART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 809 #define UART_IFS_SSM (0x1UL << 11) /**< Set Slave-Select in Master mode Interrupt Flag */
<> 128:9bcdf88f62b0 810 #define _UART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */
<> 128:9bcdf88f62b0 811 #define _UART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
<> 128:9bcdf88f62b0 812 #define _UART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 813 #define UART_IFS_SSM_DEFAULT (_UART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 814 #define UART_IFS_CCF (0x1UL << 12) /**< Set Collision Check Fail Interrupt Flag */
<> 128:9bcdf88f62b0 815 #define _UART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */
<> 128:9bcdf88f62b0 816 #define _UART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
<> 128:9bcdf88f62b0 817 #define _UART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 818 #define UART_IFS_CCF_DEFAULT (_UART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IFS */
<> 128:9bcdf88f62b0 819
<> 128:9bcdf88f62b0 820 /* Bit fields for UART IFC */
<> 128:9bcdf88f62b0 821 #define _UART_IFC_RESETVALUE 0x00000000UL /**< Default value for UART_IFC */
<> 128:9bcdf88f62b0 822 #define _UART_IFC_MASK 0x00001FF9UL /**< Mask for UART_IFC */
<> 128:9bcdf88f62b0 823 #define UART_IFC_TXC (0x1UL << 0) /**< Clear TX Complete Interrupt Flag */
<> 128:9bcdf88f62b0 824 #define _UART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */
<> 128:9bcdf88f62b0 825 #define _UART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
<> 128:9bcdf88f62b0 826 #define _UART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 827 #define UART_IFC_TXC_DEFAULT (_UART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 828 #define UART_IFC_RXFULL (0x1UL << 3) /**< Clear RX Buffer Full Interrupt Flag */
<> 128:9bcdf88f62b0 829 #define _UART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
<> 128:9bcdf88f62b0 830 #define _UART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
<> 128:9bcdf88f62b0 831 #define _UART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 832 #define UART_IFC_RXFULL_DEFAULT (_UART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 833 #define UART_IFC_RXOF (0x1UL << 4) /**< Clear RX Overflow Interrupt Flag */
<> 128:9bcdf88f62b0 834 #define _UART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
<> 128:9bcdf88f62b0 835 #define _UART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
<> 128:9bcdf88f62b0 836 #define _UART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 837 #define UART_IFC_RXOF_DEFAULT (_UART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 838 #define UART_IFC_RXUF (0x1UL << 5) /**< Clear RX Underflow Interrupt Flag */
<> 128:9bcdf88f62b0 839 #define _UART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
<> 128:9bcdf88f62b0 840 #define _UART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
<> 128:9bcdf88f62b0 841 #define _UART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 842 #define UART_IFC_RXUF_DEFAULT (_UART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 843 #define UART_IFC_TXOF (0x1UL << 6) /**< Clear TX Overflow Interrupt Flag */
<> 128:9bcdf88f62b0 844 #define _UART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
<> 128:9bcdf88f62b0 845 #define _UART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
<> 128:9bcdf88f62b0 846 #define _UART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 847 #define UART_IFC_TXOF_DEFAULT (_UART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 848 #define UART_IFC_TXUF (0x1UL << 7) /**< Clear TX Underflow Interrupt Flag */
<> 128:9bcdf88f62b0 849 #define _UART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
<> 128:9bcdf88f62b0 850 #define _UART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
<> 128:9bcdf88f62b0 851 #define _UART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 852 #define UART_IFC_TXUF_DEFAULT (_UART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 853 #define UART_IFC_PERR (0x1UL << 8) /**< Clear Parity Error Interrupt Flag */
<> 128:9bcdf88f62b0 854 #define _UART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */
<> 128:9bcdf88f62b0 855 #define _UART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
<> 128:9bcdf88f62b0 856 #define _UART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 857 #define UART_IFC_PERR_DEFAULT (_UART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 858 #define UART_IFC_FERR (0x1UL << 9) /**< Clear Framing Error Interrupt Flag */
<> 128:9bcdf88f62b0 859 #define _UART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */
<> 128:9bcdf88f62b0 860 #define _UART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
<> 128:9bcdf88f62b0 861 #define _UART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 862 #define UART_IFC_FERR_DEFAULT (_UART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 863 #define UART_IFC_MPAF (0x1UL << 10) /**< Clear Multi-Processor Address Frame Interrupt Flag */
<> 128:9bcdf88f62b0 864 #define _UART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
<> 128:9bcdf88f62b0 865 #define _UART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
<> 128:9bcdf88f62b0 866 #define _UART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 867 #define UART_IFC_MPAF_DEFAULT (_UART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 868 #define UART_IFC_SSM (0x1UL << 11) /**< Clear Slave-Select In Master Mode Interrupt Flag */
<> 128:9bcdf88f62b0 869 #define _UART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */
<> 128:9bcdf88f62b0 870 #define _UART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
<> 128:9bcdf88f62b0 871 #define _UART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 872 #define UART_IFC_SSM_DEFAULT (_UART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 873 #define UART_IFC_CCF (0x1UL << 12) /**< Clear Collision Check Fail Interrupt Flag */
<> 128:9bcdf88f62b0 874 #define _UART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */
<> 128:9bcdf88f62b0 875 #define _UART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
<> 128:9bcdf88f62b0 876 #define _UART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 877 #define UART_IFC_CCF_DEFAULT (_UART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IFC */
<> 128:9bcdf88f62b0 878
<> 128:9bcdf88f62b0 879 /* Bit fields for UART IEN */
<> 128:9bcdf88f62b0 880 #define _UART_IEN_RESETVALUE 0x00000000UL /**< Default value for UART_IEN */
<> 128:9bcdf88f62b0 881 #define _UART_IEN_MASK 0x00001FFFUL /**< Mask for UART_IEN */
<> 128:9bcdf88f62b0 882 #define UART_IEN_TXC (0x1UL << 0) /**< TX Complete Interrupt Enable */
<> 128:9bcdf88f62b0 883 #define _UART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */
<> 128:9bcdf88f62b0 884 #define _UART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
<> 128:9bcdf88f62b0 885 #define _UART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 886 #define UART_IEN_TXC_DEFAULT (_UART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 887 #define UART_IEN_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Enable */
<> 128:9bcdf88f62b0 888 #define _UART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
<> 128:9bcdf88f62b0 889 #define _UART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
<> 128:9bcdf88f62b0 890 #define _UART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 891 #define UART_IEN_TXBL_DEFAULT (_UART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 892 #define UART_IEN_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Enable */
<> 128:9bcdf88f62b0 893 #define _UART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
<> 128:9bcdf88f62b0 894 #define _UART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
<> 128:9bcdf88f62b0 895 #define _UART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 896 #define UART_IEN_RXDATAV_DEFAULT (_UART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 897 #define UART_IEN_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Enable */
<> 128:9bcdf88f62b0 898 #define _UART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
<> 128:9bcdf88f62b0 899 #define _UART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
<> 128:9bcdf88f62b0 900 #define _UART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 901 #define UART_IEN_RXFULL_DEFAULT (_UART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 902 #define UART_IEN_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Enable */
<> 128:9bcdf88f62b0 903 #define _UART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
<> 128:9bcdf88f62b0 904 #define _UART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
<> 128:9bcdf88f62b0 905 #define _UART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 906 #define UART_IEN_RXOF_DEFAULT (_UART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 907 #define UART_IEN_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Enable */
<> 128:9bcdf88f62b0 908 #define _UART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
<> 128:9bcdf88f62b0 909 #define _UART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
<> 128:9bcdf88f62b0 910 #define _UART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 911 #define UART_IEN_RXUF_DEFAULT (_UART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 912 #define UART_IEN_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Enable */
<> 128:9bcdf88f62b0 913 #define _UART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
<> 128:9bcdf88f62b0 914 #define _UART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
<> 128:9bcdf88f62b0 915 #define _UART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 916 #define UART_IEN_TXOF_DEFAULT (_UART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 917 #define UART_IEN_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Enable */
<> 128:9bcdf88f62b0 918 #define _UART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
<> 128:9bcdf88f62b0 919 #define _UART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
<> 128:9bcdf88f62b0 920 #define _UART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 921 #define UART_IEN_TXUF_DEFAULT (_UART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 922 #define UART_IEN_PERR (0x1UL << 8) /**< Parity Error Interrupt Enable */
<> 128:9bcdf88f62b0 923 #define _UART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */
<> 128:9bcdf88f62b0 924 #define _UART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
<> 128:9bcdf88f62b0 925 #define _UART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 926 #define UART_IEN_PERR_DEFAULT (_UART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 927 #define UART_IEN_FERR (0x1UL << 9) /**< Framing Error Interrupt Enable */
<> 128:9bcdf88f62b0 928 #define _UART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */
<> 128:9bcdf88f62b0 929 #define _UART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
<> 128:9bcdf88f62b0 930 #define _UART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 931 #define UART_IEN_FERR_DEFAULT (_UART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 932 #define UART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Enable */
<> 128:9bcdf88f62b0 933 #define _UART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
<> 128:9bcdf88f62b0 934 #define _UART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
<> 128:9bcdf88f62b0 935 #define _UART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 936 #define UART_IEN_MPAF_DEFAULT (_UART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 937 #define UART_IEN_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Enable */
<> 128:9bcdf88f62b0 938 #define _UART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */
<> 128:9bcdf88f62b0 939 #define _UART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
<> 128:9bcdf88f62b0 940 #define _UART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 941 #define UART_IEN_SSM_DEFAULT (_UART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 942 #define UART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Enable */
<> 128:9bcdf88f62b0 943 #define _UART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */
<> 128:9bcdf88f62b0 944 #define _UART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
<> 128:9bcdf88f62b0 945 #define _UART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 946 #define UART_IEN_CCF_DEFAULT (_UART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IEN */
<> 128:9bcdf88f62b0 947
<> 128:9bcdf88f62b0 948 /* Bit fields for UART IRCTRL */
<> 128:9bcdf88f62b0 949 #define _UART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for UART_IRCTRL */
<> 128:9bcdf88f62b0 950 #define _UART_IRCTRL_MASK 0x000000FFUL /**< Mask for UART_IRCTRL */
<> 128:9bcdf88f62b0 951 #define UART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */
<> 128:9bcdf88f62b0 952 #define _UART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */
<> 128:9bcdf88f62b0 953 #define _UART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */
<> 128:9bcdf88f62b0 954 #define _UART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */
<> 128:9bcdf88f62b0 955 #define UART_IRCTRL_IREN_DEFAULT (_UART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IRCTRL */
<> 128:9bcdf88f62b0 956 #define _UART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */
<> 128:9bcdf88f62b0 957 #define _UART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */
<> 128:9bcdf88f62b0 958 #define _UART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */
<> 128:9bcdf88f62b0 959 #define _UART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for UART_IRCTRL */
<> 128:9bcdf88f62b0 960 #define _UART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for UART_IRCTRL */
<> 128:9bcdf88f62b0 961 #define _UART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for UART_IRCTRL */
<> 128:9bcdf88f62b0 962 #define _UART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for UART_IRCTRL */
<> 128:9bcdf88f62b0 963 #define UART_IRCTRL_IRPW_DEFAULT (_UART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_IRCTRL */
<> 128:9bcdf88f62b0 964 #define UART_IRCTRL_IRPW_ONE (_UART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for UART_IRCTRL */
<> 128:9bcdf88f62b0 965 #define UART_IRCTRL_IRPW_TWO (_UART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for UART_IRCTRL */
<> 128:9bcdf88f62b0 966 #define UART_IRCTRL_IRPW_THREE (_UART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for UART_IRCTRL */
<> 128:9bcdf88f62b0 967 #define UART_IRCTRL_IRPW_FOUR (_UART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for UART_IRCTRL */
<> 128:9bcdf88f62b0 968 #define UART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */
<> 128:9bcdf88f62b0 969 #define _UART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */
<> 128:9bcdf88f62b0 970 #define _UART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */
<> 128:9bcdf88f62b0 971 #define _UART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */
<> 128:9bcdf88f62b0 972 #define UART_IRCTRL_IRFILT_DEFAULT (_UART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IRCTRL */
<> 128:9bcdf88f62b0 973 #define _UART_IRCTRL_IRPRSSEL_SHIFT 4 /**< Shift value for USART_IRPRSSEL */
<> 128:9bcdf88f62b0 974 #define _UART_IRCTRL_IRPRSSEL_MASK 0x70UL /**< Bit mask for USART_IRPRSSEL */
<> 128:9bcdf88f62b0 975 #define _UART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */
<> 128:9bcdf88f62b0 976 #define _UART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_IRCTRL */
<> 128:9bcdf88f62b0 977 #define _UART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_IRCTRL */
<> 128:9bcdf88f62b0 978 #define _UART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_IRCTRL */
<> 128:9bcdf88f62b0 979 #define _UART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_IRCTRL */
<> 128:9bcdf88f62b0 980 #define _UART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_IRCTRL */
<> 128:9bcdf88f62b0 981 #define _UART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_IRCTRL */
<> 128:9bcdf88f62b0 982 #define _UART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_IRCTRL */
<> 128:9bcdf88f62b0 983 #define _UART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_IRCTRL */
<> 128:9bcdf88f62b0 984 #define UART_IRCTRL_IRPRSSEL_DEFAULT (_UART_IRCTRL_IRPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IRCTRL */
<> 128:9bcdf88f62b0 985 #define UART_IRCTRL_IRPRSSEL_PRSCH0 (_UART_IRCTRL_IRPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for UART_IRCTRL */
<> 128:9bcdf88f62b0 986 #define UART_IRCTRL_IRPRSSEL_PRSCH1 (_UART_IRCTRL_IRPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for UART_IRCTRL */
<> 128:9bcdf88f62b0 987 #define UART_IRCTRL_IRPRSSEL_PRSCH2 (_UART_IRCTRL_IRPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for UART_IRCTRL */
<> 128:9bcdf88f62b0 988 #define UART_IRCTRL_IRPRSSEL_PRSCH3 (_UART_IRCTRL_IRPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for UART_IRCTRL */
<> 128:9bcdf88f62b0 989 #define UART_IRCTRL_IRPRSSEL_PRSCH4 (_UART_IRCTRL_IRPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for UART_IRCTRL */
<> 128:9bcdf88f62b0 990 #define UART_IRCTRL_IRPRSSEL_PRSCH5 (_UART_IRCTRL_IRPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for UART_IRCTRL */
<> 128:9bcdf88f62b0 991 #define UART_IRCTRL_IRPRSSEL_PRSCH6 (_UART_IRCTRL_IRPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for UART_IRCTRL */
<> 128:9bcdf88f62b0 992 #define UART_IRCTRL_IRPRSSEL_PRSCH7 (_UART_IRCTRL_IRPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for UART_IRCTRL */
<> 128:9bcdf88f62b0 993 #define UART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */
<> 128:9bcdf88f62b0 994 #define _UART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */
<> 128:9bcdf88f62b0 995 #define _UART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */
<> 128:9bcdf88f62b0 996 #define _UART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */
<> 128:9bcdf88f62b0 997 #define UART_IRCTRL_IRPRSEN_DEFAULT (_UART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IRCTRL */
<> 128:9bcdf88f62b0 998
<> 128:9bcdf88f62b0 999 /* Bit fields for UART ROUTE */
<> 128:9bcdf88f62b0 1000 #define _UART_ROUTE_RESETVALUE 0x00000000UL /**< Default value for UART_ROUTE */
<> 128:9bcdf88f62b0 1001 #define _UART_ROUTE_MASK 0x0000070FUL /**< Mask for UART_ROUTE */
<> 128:9bcdf88f62b0 1002 #define UART_ROUTE_RXPEN (0x1UL << 0) /**< RX Pin Enable */
<> 128:9bcdf88f62b0 1003 #define _UART_ROUTE_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */
<> 128:9bcdf88f62b0 1004 #define _UART_ROUTE_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */
<> 128:9bcdf88f62b0 1005 #define _UART_ROUTE_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */
<> 128:9bcdf88f62b0 1006 #define UART_ROUTE_RXPEN_DEFAULT (_UART_ROUTE_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_ROUTE */
<> 128:9bcdf88f62b0 1007 #define UART_ROUTE_TXPEN (0x1UL << 1) /**< TX Pin Enable */
<> 128:9bcdf88f62b0 1008 #define _UART_ROUTE_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */
<> 128:9bcdf88f62b0 1009 #define _UART_ROUTE_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */
<> 128:9bcdf88f62b0 1010 #define _UART_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */
<> 128:9bcdf88f62b0 1011 #define UART_ROUTE_TXPEN_DEFAULT (_UART_ROUTE_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_ROUTE */
<> 128:9bcdf88f62b0 1012 #define UART_ROUTE_CSPEN (0x1UL << 2) /**< CS Pin Enable */
<> 128:9bcdf88f62b0 1013 #define _UART_ROUTE_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */
<> 128:9bcdf88f62b0 1014 #define _UART_ROUTE_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */
<> 128:9bcdf88f62b0 1015 #define _UART_ROUTE_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */
<> 128:9bcdf88f62b0 1016 #define UART_ROUTE_CSPEN_DEFAULT (_UART_ROUTE_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_ROUTE */
<> 128:9bcdf88f62b0 1017 #define UART_ROUTE_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */
<> 128:9bcdf88f62b0 1018 #define _UART_ROUTE_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */
<> 128:9bcdf88f62b0 1019 #define _UART_ROUTE_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */
<> 128:9bcdf88f62b0 1020 #define _UART_ROUTE_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */
<> 128:9bcdf88f62b0 1021 #define UART_ROUTE_CLKPEN_DEFAULT (_UART_ROUTE_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_ROUTE */
<> 128:9bcdf88f62b0 1022 #define _UART_ROUTE_LOCATION_SHIFT 8 /**< Shift value for USART_LOCATION */
<> 128:9bcdf88f62b0 1023 #define _UART_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for USART_LOCATION */
<> 128:9bcdf88f62b0 1024 #define _UART_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTE */
<> 128:9bcdf88f62b0 1025 #define _UART_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */
<> 128:9bcdf88f62b0 1026 #define _UART_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTE */
<> 128:9bcdf88f62b0 1027 #define _UART_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTE */
<> 128:9bcdf88f62b0 1028 #define _UART_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTE */
<> 128:9bcdf88f62b0 1029 #define _UART_ROUTE_LOCATION_LOC4 0x00000004UL /**< Mode LOC4 for UART_ROUTE */
<> 128:9bcdf88f62b0 1030 #define _UART_ROUTE_LOCATION_LOC5 0x00000005UL /**< Mode LOC5 for UART_ROUTE */
<> 128:9bcdf88f62b0 1031 #define UART_ROUTE_LOCATION_LOC0 (_UART_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for UART_ROUTE */
<> 128:9bcdf88f62b0 1032 #define UART_ROUTE_LOCATION_DEFAULT (_UART_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_ROUTE */
<> 128:9bcdf88f62b0 1033 #define UART_ROUTE_LOCATION_LOC1 (_UART_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for UART_ROUTE */
<> 128:9bcdf88f62b0 1034 #define UART_ROUTE_LOCATION_LOC2 (_UART_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for UART_ROUTE */
<> 128:9bcdf88f62b0 1035 #define UART_ROUTE_LOCATION_LOC3 (_UART_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for UART_ROUTE */
<> 128:9bcdf88f62b0 1036 #define UART_ROUTE_LOCATION_LOC4 (_UART_ROUTE_LOCATION_LOC4 << 8) /**< Shifted mode LOC4 for UART_ROUTE */
<> 128:9bcdf88f62b0 1037 #define UART_ROUTE_LOCATION_LOC5 (_UART_ROUTE_LOCATION_LOC5 << 8) /**< Shifted mode LOC5 for UART_ROUTE */
<> 128:9bcdf88f62b0 1038
<> 128:9bcdf88f62b0 1039 /* Bit fields for UART INPUT */
<> 128:9bcdf88f62b0 1040 #define _UART_INPUT_RESETVALUE 0x00000000UL /**< Default value for UART_INPUT */
<> 128:9bcdf88f62b0 1041 #define _UART_INPUT_MASK 0x0000001FUL /**< Mask for UART_INPUT */
<> 128:9bcdf88f62b0 1042 #define _UART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */
<> 128:9bcdf88f62b0 1043 #define _UART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for USART_RXPRSSEL */
<> 128:9bcdf88f62b0 1044 #define _UART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_INPUT */
<> 128:9bcdf88f62b0 1045 #define _UART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_INPUT */
<> 128:9bcdf88f62b0 1046 #define _UART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_INPUT */
<> 128:9bcdf88f62b0 1047 #define _UART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_INPUT */
<> 128:9bcdf88f62b0 1048 #define _UART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_INPUT */
<> 128:9bcdf88f62b0 1049 #define _UART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_INPUT */
<> 128:9bcdf88f62b0 1050 #define _UART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_INPUT */
<> 128:9bcdf88f62b0 1051 #define _UART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_INPUT */
<> 128:9bcdf88f62b0 1052 #define _UART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_INPUT */
<> 128:9bcdf88f62b0 1053 #define _UART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for UART_INPUT */
<> 128:9bcdf88f62b0 1054 #define _UART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for UART_INPUT */
<> 128:9bcdf88f62b0 1055 #define _UART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for UART_INPUT */
<> 128:9bcdf88f62b0 1056 #define _UART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for UART_INPUT */
<> 128:9bcdf88f62b0 1057 #define UART_INPUT_RXPRSSEL_DEFAULT (_UART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_INPUT */
<> 128:9bcdf88f62b0 1058 #define UART_INPUT_RXPRSSEL_PRSCH0 (_UART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for UART_INPUT */
<> 128:9bcdf88f62b0 1059 #define UART_INPUT_RXPRSSEL_PRSCH1 (_UART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for UART_INPUT */
<> 128:9bcdf88f62b0 1060 #define UART_INPUT_RXPRSSEL_PRSCH2 (_UART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for UART_INPUT */
<> 128:9bcdf88f62b0 1061 #define UART_INPUT_RXPRSSEL_PRSCH3 (_UART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for UART_INPUT */
<> 128:9bcdf88f62b0 1062 #define UART_INPUT_RXPRSSEL_PRSCH4 (_UART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for UART_INPUT */
<> 128:9bcdf88f62b0 1063 #define UART_INPUT_RXPRSSEL_PRSCH5 (_UART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for UART_INPUT */
<> 128:9bcdf88f62b0 1064 #define UART_INPUT_RXPRSSEL_PRSCH6 (_UART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for UART_INPUT */
<> 128:9bcdf88f62b0 1065 #define UART_INPUT_RXPRSSEL_PRSCH7 (_UART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for UART_INPUT */
<> 128:9bcdf88f62b0 1066 #define UART_INPUT_RXPRSSEL_PRSCH8 (_UART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for UART_INPUT */
<> 128:9bcdf88f62b0 1067 #define UART_INPUT_RXPRSSEL_PRSCH9 (_UART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for UART_INPUT */
<> 128:9bcdf88f62b0 1068 #define UART_INPUT_RXPRSSEL_PRSCH10 (_UART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for UART_INPUT */
<> 128:9bcdf88f62b0 1069 #define UART_INPUT_RXPRSSEL_PRSCH11 (_UART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for UART_INPUT */
<> 128:9bcdf88f62b0 1070 #define UART_INPUT_RXPRS (0x1UL << 4) /**< PRS RX Enable */
<> 128:9bcdf88f62b0 1071 #define _UART_INPUT_RXPRS_SHIFT 4 /**< Shift value for USART_RXPRS */
<> 128:9bcdf88f62b0 1072 #define _UART_INPUT_RXPRS_MASK 0x10UL /**< Bit mask for USART_RXPRS */
<> 128:9bcdf88f62b0 1073 #define _UART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_INPUT */
<> 128:9bcdf88f62b0 1074 #define UART_INPUT_RXPRS_DEFAULT (_UART_INPUT_RXPRS_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_INPUT */
<> 128:9bcdf88f62b0 1075
<> 128:9bcdf88f62b0 1076 /* Bit fields for UART I2SCTRL */
<> 128:9bcdf88f62b0 1077 #define _UART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1078 #define _UART_I2SCTRL_MASK 0x0000071FUL /**< Mask for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1079 #define UART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */
<> 128:9bcdf88f62b0 1080 #define _UART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */
<> 128:9bcdf88f62b0 1081 #define _UART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */
<> 128:9bcdf88f62b0 1082 #define _UART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1083 #define UART_I2SCTRL_EN_DEFAULT (_UART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1084 #define UART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */
<> 128:9bcdf88f62b0 1085 #define _UART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */
<> 128:9bcdf88f62b0 1086 #define _UART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */
<> 128:9bcdf88f62b0 1087 #define _UART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1088 #define UART_I2SCTRL_MONO_DEFAULT (_UART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1089 #define UART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */
<> 128:9bcdf88f62b0 1090 #define _UART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */
<> 128:9bcdf88f62b0 1091 #define _UART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */
<> 128:9bcdf88f62b0 1092 #define _UART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1093 #define _UART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1094 #define _UART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1095 #define UART_I2SCTRL_JUSTIFY_DEFAULT (_UART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1096 #define UART_I2SCTRL_JUSTIFY_LEFT (_UART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1097 #define UART_I2SCTRL_JUSTIFY_RIGHT (_UART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1098 #define UART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */
<> 128:9bcdf88f62b0 1099 #define _UART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */
<> 128:9bcdf88f62b0 1100 #define _UART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */
<> 128:9bcdf88f62b0 1101 #define _UART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1102 #define UART_I2SCTRL_DMASPLIT_DEFAULT (_UART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1103 #define UART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */
<> 128:9bcdf88f62b0 1104 #define _UART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */
<> 128:9bcdf88f62b0 1105 #define _UART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */
<> 128:9bcdf88f62b0 1106 #define _UART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1107 #define UART_I2SCTRL_DELAY_DEFAULT (_UART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1108 #define _UART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */
<> 128:9bcdf88f62b0 1109 #define _UART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */
<> 128:9bcdf88f62b0 1110 #define _UART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1111 #define _UART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1112 #define _UART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1113 #define _UART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1114 #define _UART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1115 #define _UART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1116 #define _UART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1117 #define _UART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1118 #define _UART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1119 #define UART_I2SCTRL_FORMAT_DEFAULT (_UART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1120 #define UART_I2SCTRL_FORMAT_W32D32 (_UART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1121 #define UART_I2SCTRL_FORMAT_W32D24M (_UART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1122 #define UART_I2SCTRL_FORMAT_W32D24 (_UART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1123 #define UART_I2SCTRL_FORMAT_W32D16 (_UART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1124 #define UART_I2SCTRL_FORMAT_W32D8 (_UART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1125 #define UART_I2SCTRL_FORMAT_W16D16 (_UART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1126 #define UART_I2SCTRL_FORMAT_W16D8 (_UART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1127 #define UART_I2SCTRL_FORMAT_W8D8 (_UART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for UART_I2SCTRL */
<> 128:9bcdf88f62b0 1128
<> 128:9bcdf88f62b0 1129 /** @} End of group EFM32LG_UART */
<> 128:9bcdf88f62b0 1130 /** @} End of group Parts */
<> 128:9bcdf88f62b0 1131