mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32LG_STK3600/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_msc.h@128:9bcdf88f62b0, 2016-10-27 (annotated)

Committer:
<>
Date:
Thu Oct 27 16:45:56 2016 +0100
Revision:
128:9bcdf88f62b0
Child:
139:856d2700e60b
Release 128 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



2966: Add kw24 support https://github.com/ARMmbed/mbed-os/pull/2966

3068: MultiTech mDot - clean up PeripheralPins.c and add new pin names https://github.com/ARMmbed/mbed-os/pull/3068

3089: Kinetis HAL: Remove clock initialization code from serial and ticker  https://github.com/ARMmbed/mbed-os/pull/3089

2943: [NRF5] NVIC_SetVector functionality https://github.com/ARMmbed/mbed-os/pull/2943

2938: InterruptIn changes in NCS36510 HAL. https://github.com/ARMmbed/mbed-os/pull/2938

3108: Fix sleep function for NRF52. https://github.com/ARMmbed/mbed-os/pull/3108

3076: STM32F1: Correct timer master value reading https://github.com/ARMmbed/mbed-os/pull/3076

3085: Add LOWPOWERTIMER capability for NUCLEO_F303ZE https://github.com/ARMmbed/mbed-os/pull/3085

3046: [BEETLE] Update BLE stack on Beetle board https://github.com/ARMmbed/mbed-os/pull/3046

3122: [Silicon Labs] Update of Silicon Labs HAL https://github.com/ARMmbed/mbed-os/pull/3122

3022: OnSemi RAM usage fix https://github.com/ARMmbed/mbed-os/pull/3022

3121: STM32F3: Correct UART4 and UART5 defines when using DEVICE_SERIAL_ASYNCH https://github.com/ARMmbed/mbed-os/pull/3121

3142: Targets- NUMAKER_PFM_NUC47216 remove mbed 2 https://github.com/ARMmbed/mbed-os/pull/3142

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**************************************************************************//**
<> 128:9bcdf88f62b0 2 * @file efm32lg_msc.h
<> 128:9bcdf88f62b0 3 * @brief EFM32LG_MSC register and bit field definitions
<> 128:9bcdf88f62b0 4 * @version 5.0.0
<> 128:9bcdf88f62b0 5 ******************************************************************************
<> 128:9bcdf88f62b0 6 * @section License
<> 128:9bcdf88f62b0 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 *
<> 128:9bcdf88f62b0 10 * Permission is granted to anyone to use this software for any purpose,
<> 128:9bcdf88f62b0 11 * including commercial applications, and to alter it and redistribute it
<> 128:9bcdf88f62b0 12 * freely, subject to the following restrictions:
<> 128:9bcdf88f62b0 13 *
<> 128:9bcdf88f62b0 14 * 1. The origin of this software must not be misrepresented; you must not
<> 128:9bcdf88f62b0 15 * claim that you wrote the original software.@n
<> 128:9bcdf88f62b0 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 128:9bcdf88f62b0 17 * misrepresented as being the original software.@n
<> 128:9bcdf88f62b0 18 * 3. This notice may not be removed or altered from any source distribution.
<> 128:9bcdf88f62b0 19 *
<> 128:9bcdf88f62b0 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 128:9bcdf88f62b0 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 128:9bcdf88f62b0 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 128:9bcdf88f62b0 23 * kind, including, but not limited to, any implied warranties of
<> 128:9bcdf88f62b0 24 * merchantability or fitness for any particular purpose or warranties against
<> 128:9bcdf88f62b0 25 * infringement of any proprietary rights of a third party.
<> 128:9bcdf88f62b0 26 *
<> 128:9bcdf88f62b0 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 128:9bcdf88f62b0 28 * incidental, or special damages, or any other relief, or for any claim by
<> 128:9bcdf88f62b0 29 * any third party, arising from your use of this Software.
<> 128:9bcdf88f62b0 30 *
<> 128:9bcdf88f62b0 31 *****************************************************************************/
<> 128:9bcdf88f62b0 32 /**************************************************************************//**
<> 128:9bcdf88f62b0 33 * @addtogroup Parts
<> 128:9bcdf88f62b0 34 * @{
<> 128:9bcdf88f62b0 35 ******************************************************************************/
<> 128:9bcdf88f62b0 36 /**************************************************************************//**
<> 128:9bcdf88f62b0 37 * @defgroup EFM32LG_MSC
<> 128:9bcdf88f62b0 38 * @{
<> 128:9bcdf88f62b0 39 * @brief EFM32LG_MSC Register Declaration
<> 128:9bcdf88f62b0 40 *****************************************************************************/
<> 128:9bcdf88f62b0 41 typedef struct
<> 128:9bcdf88f62b0 42 {
<> 128:9bcdf88f62b0 43 __IOM uint32_t CTRL; /**< Memory System Control Register */
<> 128:9bcdf88f62b0 44 __IOM uint32_t READCTRL; /**< Read Control Register */
<> 128:9bcdf88f62b0 45 __IOM uint32_t WRITECTRL; /**< Write Control Register */
<> 128:9bcdf88f62b0 46 __IOM uint32_t WRITECMD; /**< Write Command Register */
<> 128:9bcdf88f62b0 47 __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */
<> 128:9bcdf88f62b0 48
<> 128:9bcdf88f62b0 49 uint32_t RESERVED0[1]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 50 __IOM uint32_t WDATA; /**< Write Data Register */
<> 128:9bcdf88f62b0 51 __IM uint32_t STATUS; /**< Status Register */
<> 128:9bcdf88f62b0 52
<> 128:9bcdf88f62b0 53 uint32_t RESERVED1[3]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 54 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 128:9bcdf88f62b0 55 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 128:9bcdf88f62b0 56 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 128:9bcdf88f62b0 57 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 128:9bcdf88f62b0 58 __IOM uint32_t LOCK; /**< Configuration Lock Register */
<> 128:9bcdf88f62b0 59 __IOM uint32_t CMD; /**< Command Register */
<> 128:9bcdf88f62b0 60 __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */
<> 128:9bcdf88f62b0 61 __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */
<> 128:9bcdf88f62b0 62 uint32_t RESERVED2[1]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 63 __IOM uint32_t TIMEBASE; /**< Flash Write and Erase Timebase */
<> 128:9bcdf88f62b0 64 __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */
<> 128:9bcdf88f62b0 65 } MSC_TypeDef; /** @} */
<> 128:9bcdf88f62b0 66
<> 128:9bcdf88f62b0 67 /**************************************************************************//**
<> 128:9bcdf88f62b0 68 * @defgroup EFM32LG_MSC_BitFields
<> 128:9bcdf88f62b0 69 * @{
<> 128:9bcdf88f62b0 70 *****************************************************************************/
<> 128:9bcdf88f62b0 71
<> 128:9bcdf88f62b0 72 /* Bit fields for MSC CTRL */
<> 128:9bcdf88f62b0 73 #define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */
<> 128:9bcdf88f62b0 74 #define _MSC_CTRL_MASK 0x00000001UL /**< Mask for MSC_CTRL */
<> 128:9bcdf88f62b0 75 #define MSC_CTRL_BUSFAULT (0x1UL << 0) /**< Bus Fault Response Enable */
<> 128:9bcdf88f62b0 76 #define _MSC_CTRL_BUSFAULT_SHIFT 0 /**< Shift value for MSC_BUSFAULT */
<> 128:9bcdf88f62b0 77 #define _MSC_CTRL_BUSFAULT_MASK 0x1UL /**< Bit mask for MSC_BUSFAULT */
<> 128:9bcdf88f62b0 78 #define _MSC_CTRL_BUSFAULT_GENERATE 0x00000000UL /**< Mode GENERATE for MSC_CTRL */
<> 128:9bcdf88f62b0 79 #define _MSC_CTRL_BUSFAULT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */
<> 128:9bcdf88f62b0 80 #define _MSC_CTRL_BUSFAULT_IGNORE 0x00000001UL /**< Mode IGNORE for MSC_CTRL */
<> 128:9bcdf88f62b0 81 #define MSC_CTRL_BUSFAULT_GENERATE (_MSC_CTRL_BUSFAULT_GENERATE << 0) /**< Shifted mode GENERATE for MSC_CTRL */
<> 128:9bcdf88f62b0 82 #define MSC_CTRL_BUSFAULT_DEFAULT (_MSC_CTRL_BUSFAULT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */
<> 128:9bcdf88f62b0 83 #define MSC_CTRL_BUSFAULT_IGNORE (_MSC_CTRL_BUSFAULT_IGNORE << 0) /**< Shifted mode IGNORE for MSC_CTRL */
<> 128:9bcdf88f62b0 84
<> 128:9bcdf88f62b0 85 /* Bit fields for MSC READCTRL */
<> 128:9bcdf88f62b0 86 #define _MSC_READCTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_READCTRL */
<> 128:9bcdf88f62b0 87 #define _MSC_READCTRL_MASK 0x000300FFUL /**< Mask for MSC_READCTRL */
<> 128:9bcdf88f62b0 88 #define _MSC_READCTRL_MODE_SHIFT 0 /**< Shift value for MSC_MODE */
<> 128:9bcdf88f62b0 89 #define _MSC_READCTRL_MODE_MASK 0x7UL /**< Bit mask for MSC_MODE */
<> 128:9bcdf88f62b0 90 #define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */
<> 128:9bcdf88f62b0 91 #define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */
<> 128:9bcdf88f62b0 92 #define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */
<> 128:9bcdf88f62b0 93 #define _MSC_READCTRL_MODE_WS0SCBTP 0x00000002UL /**< Mode WS0SCBTP for MSC_READCTRL */
<> 128:9bcdf88f62b0 94 #define _MSC_READCTRL_MODE_WS1SCBTP 0x00000003UL /**< Mode WS1SCBTP for MSC_READCTRL */
<> 128:9bcdf88f62b0 95 #define _MSC_READCTRL_MODE_WS2 0x00000004UL /**< Mode WS2 for MSC_READCTRL */
<> 128:9bcdf88f62b0 96 #define _MSC_READCTRL_MODE_WS2SCBTP 0x00000005UL /**< Mode WS2SCBTP for MSC_READCTRL */
<> 128:9bcdf88f62b0 97 #define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 0) /**< Shifted mode WS0 for MSC_READCTRL */
<> 128:9bcdf88f62b0 98 #define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_READCTRL */
<> 128:9bcdf88f62b0 99 #define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 0) /**< Shifted mode WS1 for MSC_READCTRL */
<> 128:9bcdf88f62b0 100 #define MSC_READCTRL_MODE_WS0SCBTP (_MSC_READCTRL_MODE_WS0SCBTP << 0) /**< Shifted mode WS0SCBTP for MSC_READCTRL */
<> 128:9bcdf88f62b0 101 #define MSC_READCTRL_MODE_WS1SCBTP (_MSC_READCTRL_MODE_WS1SCBTP << 0) /**< Shifted mode WS1SCBTP for MSC_READCTRL */
<> 128:9bcdf88f62b0 102 #define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 0) /**< Shifted mode WS2 for MSC_READCTRL */
<> 128:9bcdf88f62b0 103 #define MSC_READCTRL_MODE_WS2SCBTP (_MSC_READCTRL_MODE_WS2SCBTP << 0) /**< Shifted mode WS2SCBTP for MSC_READCTRL */
<> 128:9bcdf88f62b0 104 #define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */
<> 128:9bcdf88f62b0 105 #define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */
<> 128:9bcdf88f62b0 106 #define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */
<> 128:9bcdf88f62b0 107 #define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
<> 128:9bcdf88f62b0 108 #define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */
<> 128:9bcdf88f62b0 109 #define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */
<> 128:9bcdf88f62b0 110 #define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */
<> 128:9bcdf88f62b0 111 #define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */
<> 128:9bcdf88f62b0 112 #define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
<> 128:9bcdf88f62b0 113 #define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */
<> 128:9bcdf88f62b0 114 #define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */
<> 128:9bcdf88f62b0 115 #define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */
<> 128:9bcdf88f62b0 116 #define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */
<> 128:9bcdf88f62b0 117 #define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
<> 128:9bcdf88f62b0 118 #define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */
<> 128:9bcdf88f62b0 119 #define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */
<> 128:9bcdf88f62b0 120 #define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */
<> 128:9bcdf88f62b0 121 #define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */
<> 128:9bcdf88f62b0 122 #define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
<> 128:9bcdf88f62b0 123 #define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */
<> 128:9bcdf88f62b0 124 #define MSC_READCTRL_RAMCEN (0x1UL << 7) /**< RAM Cache Enable */
<> 128:9bcdf88f62b0 125 #define _MSC_READCTRL_RAMCEN_SHIFT 7 /**< Shift value for MSC_RAMCEN */
<> 128:9bcdf88f62b0 126 #define _MSC_READCTRL_RAMCEN_MASK 0x80UL /**< Bit mask for MSC_RAMCEN */
<> 128:9bcdf88f62b0 127 #define _MSC_READCTRL_RAMCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
<> 128:9bcdf88f62b0 128 #define MSC_READCTRL_RAMCEN_DEFAULT (_MSC_READCTRL_RAMCEN_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_READCTRL */
<> 128:9bcdf88f62b0 129 #define _MSC_READCTRL_BUSSTRATEGY_SHIFT 16 /**< Shift value for MSC_BUSSTRATEGY */
<> 128:9bcdf88f62b0 130 #define _MSC_READCTRL_BUSSTRATEGY_MASK 0x30000UL /**< Bit mask for MSC_BUSSTRATEGY */
<> 128:9bcdf88f62b0 131 #define _MSC_READCTRL_BUSSTRATEGY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
<> 128:9bcdf88f62b0 132 #define _MSC_READCTRL_BUSSTRATEGY_CPU 0x00000000UL /**< Mode CPU for MSC_READCTRL */
<> 128:9bcdf88f62b0 133 #define _MSC_READCTRL_BUSSTRATEGY_DMA 0x00000001UL /**< Mode DMA for MSC_READCTRL */
<> 128:9bcdf88f62b0 134 #define _MSC_READCTRL_BUSSTRATEGY_DMAEM1 0x00000002UL /**< Mode DMAEM1 for MSC_READCTRL */
<> 128:9bcdf88f62b0 135 #define _MSC_READCTRL_BUSSTRATEGY_NONE 0x00000003UL /**< Mode NONE for MSC_READCTRL */
<> 128:9bcdf88f62b0 136 #define MSC_READCTRL_BUSSTRATEGY_DEFAULT (_MSC_READCTRL_BUSSTRATEGY_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_READCTRL */
<> 128:9bcdf88f62b0 137 #define MSC_READCTRL_BUSSTRATEGY_CPU (_MSC_READCTRL_BUSSTRATEGY_CPU << 16) /**< Shifted mode CPU for MSC_READCTRL */
<> 128:9bcdf88f62b0 138 #define MSC_READCTRL_BUSSTRATEGY_DMA (_MSC_READCTRL_BUSSTRATEGY_DMA << 16) /**< Shifted mode DMA for MSC_READCTRL */
<> 128:9bcdf88f62b0 139 #define MSC_READCTRL_BUSSTRATEGY_DMAEM1 (_MSC_READCTRL_BUSSTRATEGY_DMAEM1 << 16) /**< Shifted mode DMAEM1 for MSC_READCTRL */
<> 128:9bcdf88f62b0 140 #define MSC_READCTRL_BUSSTRATEGY_NONE (_MSC_READCTRL_BUSSTRATEGY_NONE << 16) /**< Shifted mode NONE for MSC_READCTRL */
<> 128:9bcdf88f62b0 141
<> 128:9bcdf88f62b0 142 /* Bit fields for MSC WRITECTRL */
<> 128:9bcdf88f62b0 143 #define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */
<> 128:9bcdf88f62b0 144 #define _MSC_WRITECTRL_MASK 0x00000003UL /**< Mask for MSC_WRITECTRL */
<> 128:9bcdf88f62b0 145 #define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */
<> 128:9bcdf88f62b0 146 #define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */
<> 128:9bcdf88f62b0 147 #define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */
<> 128:9bcdf88f62b0 148 #define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
<> 128:9bcdf88f62b0 149 #define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
<> 128:9bcdf88f62b0 150 #define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */
<> 128:9bcdf88f62b0 151 #define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */
<> 128:9bcdf88f62b0 152 #define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */
<> 128:9bcdf88f62b0 153 #define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
<> 128:9bcdf88f62b0 154 #define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
<> 128:9bcdf88f62b0 155
<> 128:9bcdf88f62b0 156 /* Bit fields for MSC WRITECMD */
<> 128:9bcdf88f62b0 157 #define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */
<> 128:9bcdf88f62b0 158 #define _MSC_WRITECMD_MASK 0x0000113FUL /**< Mask for MSC_WRITECMD */
<> 128:9bcdf88f62b0 159 #define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB into ADDR */
<> 128:9bcdf88f62b0 160 #define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */
<> 128:9bcdf88f62b0 161 #define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */
<> 128:9bcdf88f62b0 162 #define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 128:9bcdf88f62b0 163 #define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 128:9bcdf88f62b0 164 #define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */
<> 128:9bcdf88f62b0 165 #define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */
<> 128:9bcdf88f62b0 166 #define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */
<> 128:9bcdf88f62b0 167 #define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 128:9bcdf88f62b0 168 #define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 128:9bcdf88f62b0 169 #define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */
<> 128:9bcdf88f62b0 170 #define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */
<> 128:9bcdf88f62b0 171 #define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */
<> 128:9bcdf88f62b0 172 #define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 128:9bcdf88f62b0 173 #define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 128:9bcdf88f62b0 174 #define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */
<> 128:9bcdf88f62b0 175 #define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */
<> 128:9bcdf88f62b0 176 #define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */
<> 128:9bcdf88f62b0 177 #define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 128:9bcdf88f62b0 178 #define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 128:9bcdf88f62b0 179 #define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */
<> 128:9bcdf88f62b0 180 #define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */
<> 128:9bcdf88f62b0 181 #define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */
<> 128:9bcdf88f62b0 182 #define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 128:9bcdf88f62b0 183 #define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 128:9bcdf88f62b0 184 #define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */
<> 128:9bcdf88f62b0 185 #define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */
<> 128:9bcdf88f62b0 186 #define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */
<> 128:9bcdf88f62b0 187 #define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 128:9bcdf88f62b0 188 #define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 128:9bcdf88f62b0 189 #define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */
<> 128:9bcdf88f62b0 190 #define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */
<> 128:9bcdf88f62b0 191 #define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */
<> 128:9bcdf88f62b0 192 #define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 128:9bcdf88f62b0 193 #define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 128:9bcdf88f62b0 194 #define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */
<> 128:9bcdf88f62b0 195 #define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */
<> 128:9bcdf88f62b0 196 #define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */
<> 128:9bcdf88f62b0 197 #define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 128:9bcdf88f62b0 198 #define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 128:9bcdf88f62b0 199
<> 128:9bcdf88f62b0 200 /* Bit fields for MSC ADDRB */
<> 128:9bcdf88f62b0 201 #define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */
<> 128:9bcdf88f62b0 202 #define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */
<> 128:9bcdf88f62b0 203 #define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */
<> 128:9bcdf88f62b0 204 #define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */
<> 128:9bcdf88f62b0 205 #define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */
<> 128:9bcdf88f62b0 206 #define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */
<> 128:9bcdf88f62b0 207
<> 128:9bcdf88f62b0 208 /* Bit fields for MSC WDATA */
<> 128:9bcdf88f62b0 209 #define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */
<> 128:9bcdf88f62b0 210 #define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */
<> 128:9bcdf88f62b0 211 #define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */
<> 128:9bcdf88f62b0 212 #define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */
<> 128:9bcdf88f62b0 213 #define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */
<> 128:9bcdf88f62b0 214 #define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */
<> 128:9bcdf88f62b0 215
<> 128:9bcdf88f62b0 216 /* Bit fields for MSC STATUS */
<> 128:9bcdf88f62b0 217 #define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */
<> 128:9bcdf88f62b0 218 #define _MSC_STATUS_MASK 0x0000007FUL /**< Mask for MSC_STATUS */
<> 128:9bcdf88f62b0 219 #define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */
<> 128:9bcdf88f62b0 220 #define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */
<> 128:9bcdf88f62b0 221 #define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */
<> 128:9bcdf88f62b0 222 #define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
<> 128:9bcdf88f62b0 223 #define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 128:9bcdf88f62b0 224 #define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */
<> 128:9bcdf88f62b0 225 #define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */
<> 128:9bcdf88f62b0 226 #define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */
<> 128:9bcdf88f62b0 227 #define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
<> 128:9bcdf88f62b0 228 #define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 128:9bcdf88f62b0 229 #define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */
<> 128:9bcdf88f62b0 230 #define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */
<> 128:9bcdf88f62b0 231 #define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */
<> 128:9bcdf88f62b0 232 #define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
<> 128:9bcdf88f62b0 233 #define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 128:9bcdf88f62b0 234 #define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */
<> 128:9bcdf88f62b0 235 #define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */
<> 128:9bcdf88f62b0 236 #define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */
<> 128:9bcdf88f62b0 237 #define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */
<> 128:9bcdf88f62b0 238 #define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 128:9bcdf88f62b0 239 #define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */
<> 128:9bcdf88f62b0 240 #define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */
<> 128:9bcdf88f62b0 241 #define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */
<> 128:9bcdf88f62b0 242 #define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
<> 128:9bcdf88f62b0 243 #define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 128:9bcdf88f62b0 244 #define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */
<> 128:9bcdf88f62b0 245 #define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */
<> 128:9bcdf88f62b0 246 #define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */
<> 128:9bcdf88f62b0 247 #define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
<> 128:9bcdf88f62b0 248 #define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 128:9bcdf88f62b0 249 #define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */
<> 128:9bcdf88f62b0 250 #define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */
<> 128:9bcdf88f62b0 251 #define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */
<> 128:9bcdf88f62b0 252 #define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
<> 128:9bcdf88f62b0 253 #define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 128:9bcdf88f62b0 254
<> 128:9bcdf88f62b0 255 /* Bit fields for MSC IF */
<> 128:9bcdf88f62b0 256 #define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */
<> 128:9bcdf88f62b0 257 #define _MSC_IF_MASK 0x0000000FUL /**< Mask for MSC_IF */
<> 128:9bcdf88f62b0 258 #define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */
<> 128:9bcdf88f62b0 259 #define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
<> 128:9bcdf88f62b0 260 #define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
<> 128:9bcdf88f62b0 261 #define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
<> 128:9bcdf88f62b0 262 #define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */
<> 128:9bcdf88f62b0 263 #define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */
<> 128:9bcdf88f62b0 264 #define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
<> 128:9bcdf88f62b0 265 #define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
<> 128:9bcdf88f62b0 266 #define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
<> 128:9bcdf88f62b0 267 #define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */
<> 128:9bcdf88f62b0 268 #define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */
<> 128:9bcdf88f62b0 269 #define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
<> 128:9bcdf88f62b0 270 #define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
<> 128:9bcdf88f62b0 271 #define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
<> 128:9bcdf88f62b0 272 #define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */
<> 128:9bcdf88f62b0 273 #define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */
<> 128:9bcdf88f62b0 274 #define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
<> 128:9bcdf88f62b0 275 #define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
<> 128:9bcdf88f62b0 276 #define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
<> 128:9bcdf88f62b0 277 #define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */
<> 128:9bcdf88f62b0 278
<> 128:9bcdf88f62b0 279 /* Bit fields for MSC IFS */
<> 128:9bcdf88f62b0 280 #define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */
<> 128:9bcdf88f62b0 281 #define _MSC_IFS_MASK 0x0000000FUL /**< Mask for MSC_IFS */
<> 128:9bcdf88f62b0 282 #define MSC_IFS_ERASE (0x1UL << 0) /**< Erase Done Interrupt Set */
<> 128:9bcdf88f62b0 283 #define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
<> 128:9bcdf88f62b0 284 #define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
<> 128:9bcdf88f62b0 285 #define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
<> 128:9bcdf88f62b0 286 #define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */
<> 128:9bcdf88f62b0 287 #define MSC_IFS_WRITE (0x1UL << 1) /**< Write Done Interrupt Set */
<> 128:9bcdf88f62b0 288 #define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
<> 128:9bcdf88f62b0 289 #define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
<> 128:9bcdf88f62b0 290 #define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
<> 128:9bcdf88f62b0 291 #define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */
<> 128:9bcdf88f62b0 292 #define MSC_IFS_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Set */
<> 128:9bcdf88f62b0 293 #define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
<> 128:9bcdf88f62b0 294 #define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
<> 128:9bcdf88f62b0 295 #define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
<> 128:9bcdf88f62b0 296 #define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */
<> 128:9bcdf88f62b0 297 #define MSC_IFS_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Set */
<> 128:9bcdf88f62b0 298 #define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
<> 128:9bcdf88f62b0 299 #define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
<> 128:9bcdf88f62b0 300 #define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
<> 128:9bcdf88f62b0 301 #define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */
<> 128:9bcdf88f62b0 302
<> 128:9bcdf88f62b0 303 /* Bit fields for MSC IFC */
<> 128:9bcdf88f62b0 304 #define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */
<> 128:9bcdf88f62b0 305 #define _MSC_IFC_MASK 0x0000000FUL /**< Mask for MSC_IFC */
<> 128:9bcdf88f62b0 306 #define MSC_IFC_ERASE (0x1UL << 0) /**< Erase Done Interrupt Clear */
<> 128:9bcdf88f62b0 307 #define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
<> 128:9bcdf88f62b0 308 #define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
<> 128:9bcdf88f62b0 309 #define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
<> 128:9bcdf88f62b0 310 #define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */
<> 128:9bcdf88f62b0 311 #define MSC_IFC_WRITE (0x1UL << 1) /**< Write Done Interrupt Clear */
<> 128:9bcdf88f62b0 312 #define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
<> 128:9bcdf88f62b0 313 #define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
<> 128:9bcdf88f62b0 314 #define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
<> 128:9bcdf88f62b0 315 #define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */
<> 128:9bcdf88f62b0 316 #define MSC_IFC_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Clear */
<> 128:9bcdf88f62b0 317 #define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
<> 128:9bcdf88f62b0 318 #define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
<> 128:9bcdf88f62b0 319 #define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
<> 128:9bcdf88f62b0 320 #define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */
<> 128:9bcdf88f62b0 321 #define MSC_IFC_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Clear */
<> 128:9bcdf88f62b0 322 #define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
<> 128:9bcdf88f62b0 323 #define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
<> 128:9bcdf88f62b0 324 #define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
<> 128:9bcdf88f62b0 325 #define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */
<> 128:9bcdf88f62b0 326
<> 128:9bcdf88f62b0 327 /* Bit fields for MSC IEN */
<> 128:9bcdf88f62b0 328 #define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */
<> 128:9bcdf88f62b0 329 #define _MSC_IEN_MASK 0x0000000FUL /**< Mask for MSC_IEN */
<> 128:9bcdf88f62b0 330 #define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt Enable */
<> 128:9bcdf88f62b0 331 #define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
<> 128:9bcdf88f62b0 332 #define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
<> 128:9bcdf88f62b0 333 #define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
<> 128:9bcdf88f62b0 334 #define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */
<> 128:9bcdf88f62b0 335 #define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt Enable */
<> 128:9bcdf88f62b0 336 #define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
<> 128:9bcdf88f62b0 337 #define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
<> 128:9bcdf88f62b0 338 #define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
<> 128:9bcdf88f62b0 339 #define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */
<> 128:9bcdf88f62b0 340 #define MSC_IEN_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Enable */
<> 128:9bcdf88f62b0 341 #define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
<> 128:9bcdf88f62b0 342 #define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
<> 128:9bcdf88f62b0 343 #define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
<> 128:9bcdf88f62b0 344 #define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */
<> 128:9bcdf88f62b0 345 #define MSC_IEN_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Enable */
<> 128:9bcdf88f62b0 346 #define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
<> 128:9bcdf88f62b0 347 #define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
<> 128:9bcdf88f62b0 348 #define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
<> 128:9bcdf88f62b0 349 #define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */
<> 128:9bcdf88f62b0 350
<> 128:9bcdf88f62b0 351 /* Bit fields for MSC LOCK */
<> 128:9bcdf88f62b0 352 #define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */
<> 128:9bcdf88f62b0 353 #define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */
<> 128:9bcdf88f62b0 354 #define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
<> 128:9bcdf88f62b0 355 #define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
<> 128:9bcdf88f62b0 356 #define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
<> 128:9bcdf88f62b0 357 #define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
<> 128:9bcdf88f62b0 358 #define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */
<> 128:9bcdf88f62b0 359 #define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */
<> 128:9bcdf88f62b0 360 #define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
<> 128:9bcdf88f62b0 361 #define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
<> 128:9bcdf88f62b0 362 #define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
<> 128:9bcdf88f62b0 363 #define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
<> 128:9bcdf88f62b0 364 #define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */
<> 128:9bcdf88f62b0 365 #define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
<> 128:9bcdf88f62b0 366
<> 128:9bcdf88f62b0 367 /* Bit fields for MSC CMD */
<> 128:9bcdf88f62b0 368 #define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */
<> 128:9bcdf88f62b0 369 #define _MSC_CMD_MASK 0x00000007UL /**< Mask for MSC_CMD */
<> 128:9bcdf88f62b0 370 #define MSC_CMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */
<> 128:9bcdf88f62b0 371 #define _MSC_CMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */
<> 128:9bcdf88f62b0 372 #define _MSC_CMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */
<> 128:9bcdf88f62b0 373 #define _MSC_CMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
<> 128:9bcdf88f62b0 374 #define MSC_CMD_INVCACHE_DEFAULT (_MSC_CMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */
<> 128:9bcdf88f62b0 375 #define MSC_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */
<> 128:9bcdf88f62b0 376 #define _MSC_CMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */
<> 128:9bcdf88f62b0 377 #define _MSC_CMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */
<> 128:9bcdf88f62b0 378 #define _MSC_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
<> 128:9bcdf88f62b0 379 #define MSC_CMD_STARTPC_DEFAULT (_MSC_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */
<> 128:9bcdf88f62b0 380 #define MSC_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */
<> 128:9bcdf88f62b0 381 #define _MSC_CMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */
<> 128:9bcdf88f62b0 382 #define _MSC_CMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */
<> 128:9bcdf88f62b0 383 #define _MSC_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
<> 128:9bcdf88f62b0 384 #define MSC_CMD_STOPPC_DEFAULT (_MSC_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CMD */
<> 128:9bcdf88f62b0 385
<> 128:9bcdf88f62b0 386 /* Bit fields for MSC CACHEHITS */
<> 128:9bcdf88f62b0 387 #define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */
<> 128:9bcdf88f62b0 388 #define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */
<> 128:9bcdf88f62b0 389 #define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */
<> 128:9bcdf88f62b0 390 #define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */
<> 128:9bcdf88f62b0 391 #define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */
<> 128:9bcdf88f62b0 392 #define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */
<> 128:9bcdf88f62b0 393
<> 128:9bcdf88f62b0 394 /* Bit fields for MSC CACHEMISSES */
<> 128:9bcdf88f62b0 395 #define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */
<> 128:9bcdf88f62b0 396 #define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */
<> 128:9bcdf88f62b0 397 #define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */
<> 128:9bcdf88f62b0 398 #define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */
<> 128:9bcdf88f62b0 399 #define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */
<> 128:9bcdf88f62b0 400 #define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */
<> 128:9bcdf88f62b0 401
<> 128:9bcdf88f62b0 402 /* Bit fields for MSC TIMEBASE */
<> 128:9bcdf88f62b0 403 #define _MSC_TIMEBASE_RESETVALUE 0x00000010UL /**< Default value for MSC_TIMEBASE */
<> 128:9bcdf88f62b0 404 #define _MSC_TIMEBASE_MASK 0x0001003FUL /**< Mask for MSC_TIMEBASE */
<> 128:9bcdf88f62b0 405 #define _MSC_TIMEBASE_BASE_SHIFT 0 /**< Shift value for MSC_BASE */
<> 128:9bcdf88f62b0 406 #define _MSC_TIMEBASE_BASE_MASK 0x3FUL /**< Bit mask for MSC_BASE */
<> 128:9bcdf88f62b0 407 #define _MSC_TIMEBASE_BASE_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_TIMEBASE */
<> 128:9bcdf88f62b0 408 #define MSC_TIMEBASE_BASE_DEFAULT (_MSC_TIMEBASE_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_TIMEBASE */
<> 128:9bcdf88f62b0 409 #define MSC_TIMEBASE_PERIOD (0x1UL << 16) /**< Sets the timebase period */
<> 128:9bcdf88f62b0 410 #define _MSC_TIMEBASE_PERIOD_SHIFT 16 /**< Shift value for MSC_PERIOD */
<> 128:9bcdf88f62b0 411 #define _MSC_TIMEBASE_PERIOD_MASK 0x10000UL /**< Bit mask for MSC_PERIOD */
<> 128:9bcdf88f62b0 412 #define _MSC_TIMEBASE_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_TIMEBASE */
<> 128:9bcdf88f62b0 413 #define _MSC_TIMEBASE_PERIOD_1US 0x00000000UL /**< Mode 1US for MSC_TIMEBASE */
<> 128:9bcdf88f62b0 414 #define _MSC_TIMEBASE_PERIOD_5US 0x00000001UL /**< Mode 5US for MSC_TIMEBASE */
<> 128:9bcdf88f62b0 415 #define MSC_TIMEBASE_PERIOD_DEFAULT (_MSC_TIMEBASE_PERIOD_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_TIMEBASE */
<> 128:9bcdf88f62b0 416 #define MSC_TIMEBASE_PERIOD_1US (_MSC_TIMEBASE_PERIOD_1US << 16) /**< Shifted mode 1US for MSC_TIMEBASE */
<> 128:9bcdf88f62b0 417 #define MSC_TIMEBASE_PERIOD_5US (_MSC_TIMEBASE_PERIOD_5US << 16) /**< Shifted mode 5US for MSC_TIMEBASE */
<> 128:9bcdf88f62b0 418
<> 128:9bcdf88f62b0 419 /* Bit fields for MSC MASSLOCK */
<> 128:9bcdf88f62b0 420 #define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */
<> 128:9bcdf88f62b0 421 #define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */
<> 128:9bcdf88f62b0 422 #define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
<> 128:9bcdf88f62b0 423 #define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
<> 128:9bcdf88f62b0 424 #define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
<> 128:9bcdf88f62b0 425 #define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */
<> 128:9bcdf88f62b0 426 #define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */
<> 128:9bcdf88f62b0 427 #define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */
<> 128:9bcdf88f62b0 428 #define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */
<> 128:9bcdf88f62b0 429 #define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
<> 128:9bcdf88f62b0 430 #define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
<> 128:9bcdf88f62b0 431 #define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */
<> 128:9bcdf88f62b0 432 #define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */
<> 128:9bcdf88f62b0 433 #define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */
<> 128:9bcdf88f62b0 434
<> 128:9bcdf88f62b0 435 /** @} End of group EFM32LG_MSC */
<> 128:9bcdf88f62b0 436 /** @} End of group Parts */
<> 128:9bcdf88f62b0 437