mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32LG_STK3600/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_gpio.h@128:9bcdf88f62b0, 2016-10-27 (annotated)

Committer:
<>
Date:
Thu Oct 27 16:45:56 2016 +0100
Revision:
128:9bcdf88f62b0
Child:
139:856d2700e60b
Release 128 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



2966: Add kw24 support https://github.com/ARMmbed/mbed-os/pull/2966

3068: MultiTech mDot - clean up PeripheralPins.c and add new pin names https://github.com/ARMmbed/mbed-os/pull/3068

3089: Kinetis HAL: Remove clock initialization code from serial and ticker  https://github.com/ARMmbed/mbed-os/pull/3089

2943: [NRF5] NVIC_SetVector functionality https://github.com/ARMmbed/mbed-os/pull/2943

2938: InterruptIn changes in NCS36510 HAL. https://github.com/ARMmbed/mbed-os/pull/2938

3108: Fix sleep function for NRF52. https://github.com/ARMmbed/mbed-os/pull/3108

3076: STM32F1: Correct timer master value reading https://github.com/ARMmbed/mbed-os/pull/3076

3085: Add LOWPOWERTIMER capability for NUCLEO_F303ZE https://github.com/ARMmbed/mbed-os/pull/3085

3046: [BEETLE] Update BLE stack on Beetle board https://github.com/ARMmbed/mbed-os/pull/3046

3122: [Silicon Labs] Update of Silicon Labs HAL https://github.com/ARMmbed/mbed-os/pull/3122

3022: OnSemi RAM usage fix https://github.com/ARMmbed/mbed-os/pull/3022

3121: STM32F3: Correct UART4 and UART5 defines when using DEVICE_SERIAL_ASYNCH https://github.com/ARMmbed/mbed-os/pull/3121

3142: Targets- NUMAKER_PFM_NUC47216 remove mbed 2 https://github.com/ARMmbed/mbed-os/pull/3142

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**************************************************************************//**
<> 128:9bcdf88f62b0 2 * @file efm32lg_gpio.h
<> 128:9bcdf88f62b0 3 * @brief EFM32LG_GPIO register and bit field definitions
<> 128:9bcdf88f62b0 4 * @version 5.0.0
<> 128:9bcdf88f62b0 5 ******************************************************************************
<> 128:9bcdf88f62b0 6 * @section License
<> 128:9bcdf88f62b0 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 *
<> 128:9bcdf88f62b0 10 * Permission is granted to anyone to use this software for any purpose,
<> 128:9bcdf88f62b0 11 * including commercial applications, and to alter it and redistribute it
<> 128:9bcdf88f62b0 12 * freely, subject to the following restrictions:
<> 128:9bcdf88f62b0 13 *
<> 128:9bcdf88f62b0 14 * 1. The origin of this software must not be misrepresented; you must not
<> 128:9bcdf88f62b0 15 * claim that you wrote the original software.@n
<> 128:9bcdf88f62b0 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 128:9bcdf88f62b0 17 * misrepresented as being the original software.@n
<> 128:9bcdf88f62b0 18 * 3. This notice may not be removed or altered from any source distribution.
<> 128:9bcdf88f62b0 19 *
<> 128:9bcdf88f62b0 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 128:9bcdf88f62b0 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 128:9bcdf88f62b0 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 128:9bcdf88f62b0 23 * kind, including, but not limited to, any implied warranties of
<> 128:9bcdf88f62b0 24 * merchantability or fitness for any particular purpose or warranties against
<> 128:9bcdf88f62b0 25 * infringement of any proprietary rights of a third party.
<> 128:9bcdf88f62b0 26 *
<> 128:9bcdf88f62b0 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 128:9bcdf88f62b0 28 * incidental, or special damages, or any other relief, or for any claim by
<> 128:9bcdf88f62b0 29 * any third party, arising from your use of this Software.
<> 128:9bcdf88f62b0 30 *
<> 128:9bcdf88f62b0 31 *****************************************************************************/
<> 128:9bcdf88f62b0 32 /**************************************************************************//**
<> 128:9bcdf88f62b0 33 * @addtogroup Parts
<> 128:9bcdf88f62b0 34 * @{
<> 128:9bcdf88f62b0 35 ******************************************************************************/
<> 128:9bcdf88f62b0 36 /**************************************************************************//**
<> 128:9bcdf88f62b0 37 * @defgroup EFM32LG_GPIO
<> 128:9bcdf88f62b0 38 * @{
<> 128:9bcdf88f62b0 39 * @brief EFM32LG_GPIO Register Declaration
<> 128:9bcdf88f62b0 40 *****************************************************************************/
<> 128:9bcdf88f62b0 41 typedef struct
<> 128:9bcdf88f62b0 42 {
<> 128:9bcdf88f62b0 43 GPIO_P_TypeDef P[6]; /**< Port configuration bits */
<> 128:9bcdf88f62b0 44
<> 128:9bcdf88f62b0 45 uint32_t RESERVED0[10]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 46 __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low Register */
<> 128:9bcdf88f62b0 47 __IOM uint32_t EXTIPSELH; /**< External Interrupt Port Select High Register */
<> 128:9bcdf88f62b0 48 __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger Register */
<> 128:9bcdf88f62b0 49 __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger Register */
<> 128:9bcdf88f62b0 50 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 128:9bcdf88f62b0 51 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 128:9bcdf88f62b0 52 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 128:9bcdf88f62b0 53 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 128:9bcdf88f62b0 54
<> 128:9bcdf88f62b0 55 __IOM uint32_t ROUTE; /**< I/O Routing Register */
<> 128:9bcdf88f62b0 56 __IOM uint32_t INSENSE; /**< Input Sense Register */
<> 128:9bcdf88f62b0 57 __IOM uint32_t LOCK; /**< Configuration Lock Register */
<> 128:9bcdf88f62b0 58 __IOM uint32_t CTRL; /**< GPIO Control Register */
<> 128:9bcdf88f62b0 59 __IOM uint32_t CMD; /**< GPIO Command Register */
<> 128:9bcdf88f62b0 60 __IOM uint32_t EM4WUEN; /**< EM4 Wake-up Enable Register */
<> 128:9bcdf88f62b0 61 __IOM uint32_t EM4WUPOL; /**< EM4 Wake-up Polarity Register */
<> 128:9bcdf88f62b0 62 __IM uint32_t EM4WUCAUSE; /**< EM4 Wake-up Cause Register */
<> 128:9bcdf88f62b0 63 } GPIO_TypeDef; /** @} */
<> 128:9bcdf88f62b0 64
<> 128:9bcdf88f62b0 65 /**************************************************************************//**
<> 128:9bcdf88f62b0 66 * @defgroup EFM32LG_GPIO_BitFields
<> 128:9bcdf88f62b0 67 * @{
<> 128:9bcdf88f62b0 68 *****************************************************************************/
<> 128:9bcdf88f62b0 69
<> 128:9bcdf88f62b0 70 /* Bit fields for GPIO P_CTRL */
<> 128:9bcdf88f62b0 71 #define _GPIO_P_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_CTRL */
<> 128:9bcdf88f62b0 72 #define _GPIO_P_CTRL_MASK 0x00000003UL /**< Mask for GPIO_P_CTRL */
<> 128:9bcdf88f62b0 73 #define _GPIO_P_CTRL_DRIVEMODE_SHIFT 0 /**< Shift value for GPIO_DRIVEMODE */
<> 128:9bcdf88f62b0 74 #define _GPIO_P_CTRL_DRIVEMODE_MASK 0x3UL /**< Bit mask for GPIO_DRIVEMODE */
<> 128:9bcdf88f62b0 75 #define _GPIO_P_CTRL_DRIVEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */
<> 128:9bcdf88f62b0 76 #define _GPIO_P_CTRL_DRIVEMODE_STANDARD 0x00000000UL /**< Mode STANDARD for GPIO_P_CTRL */
<> 128:9bcdf88f62b0 77 #define _GPIO_P_CTRL_DRIVEMODE_LOWEST 0x00000001UL /**< Mode LOWEST for GPIO_P_CTRL */
<> 128:9bcdf88f62b0 78 #define _GPIO_P_CTRL_DRIVEMODE_HIGH 0x00000002UL /**< Mode HIGH for GPIO_P_CTRL */
<> 128:9bcdf88f62b0 79 #define _GPIO_P_CTRL_DRIVEMODE_LOW 0x00000003UL /**< Mode LOW for GPIO_P_CTRL */
<> 128:9bcdf88f62b0 80 #define GPIO_P_CTRL_DRIVEMODE_DEFAULT (_GPIO_P_CTRL_DRIVEMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_CTRL */
<> 128:9bcdf88f62b0 81 #define GPIO_P_CTRL_DRIVEMODE_STANDARD (_GPIO_P_CTRL_DRIVEMODE_STANDARD << 0) /**< Shifted mode STANDARD for GPIO_P_CTRL */
<> 128:9bcdf88f62b0 82 #define GPIO_P_CTRL_DRIVEMODE_LOWEST (_GPIO_P_CTRL_DRIVEMODE_LOWEST << 0) /**< Shifted mode LOWEST for GPIO_P_CTRL */
<> 128:9bcdf88f62b0 83 #define GPIO_P_CTRL_DRIVEMODE_HIGH (_GPIO_P_CTRL_DRIVEMODE_HIGH << 0) /**< Shifted mode HIGH for GPIO_P_CTRL */
<> 128:9bcdf88f62b0 84 #define GPIO_P_CTRL_DRIVEMODE_LOW (_GPIO_P_CTRL_DRIVEMODE_LOW << 0) /**< Shifted mode LOW for GPIO_P_CTRL */
<> 128:9bcdf88f62b0 85
<> 128:9bcdf88f62b0 86 /* Bit fields for GPIO P_MODEL */
<> 128:9bcdf88f62b0 87 #define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 88 #define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 89 #define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */
<> 128:9bcdf88f62b0 90 #define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */
<> 128:9bcdf88f62b0 91 #define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 92 #define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 93 #define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 94 #define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 95 #define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 96 #define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 97 #define _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 98 #define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 99 #define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 100 #define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 101 #define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 102 #define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 103 #define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 104 #define _GPIO_P_MODEL_MODE0_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 105 #define _GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 106 #define _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 107 #define _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 108 #define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 109 #define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 110 #define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 111 #define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 112 #define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 113 #define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 114 #define GPIO_P_MODEL_MODE0_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE0_PUSHPULLDRIVE << 0) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 115 #define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 116 #define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 117 #define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 118 #define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 119 #define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 120 #define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 121 #define GPIO_P_MODEL_MODE0_WIREDANDDRIVE (_GPIO_P_MODEL_MODE0_WIREDANDDRIVE << 0) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 122 #define GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER << 0) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 123 #define GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP << 0) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 124 #define GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER << 0) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 125 #define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */
<> 128:9bcdf88f62b0 126 #define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */
<> 128:9bcdf88f62b0 127 #define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 128 #define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 129 #define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 130 #define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 131 #define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 132 #define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 133 #define _GPIO_P_MODEL_MODE1_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 134 #define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 135 #define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 136 #define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 137 #define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 138 #define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 139 #define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 140 #define _GPIO_P_MODEL_MODE1_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 141 #define _GPIO_P_MODEL_MODE1_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 142 #define _GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 143 #define _GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 144 #define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 145 #define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 146 #define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 147 #define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 148 #define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 149 #define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 150 #define GPIO_P_MODEL_MODE1_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE1_PUSHPULLDRIVE << 4) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 151 #define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 152 #define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 153 #define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 154 #define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 155 #define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 156 #define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 157 #define GPIO_P_MODEL_MODE1_WIREDANDDRIVE (_GPIO_P_MODEL_MODE1_WIREDANDDRIVE << 4) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 158 #define GPIO_P_MODEL_MODE1_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE1_WIREDANDDRIVEFILTER << 4) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 159 #define GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUP << 4) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 160 #define GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDDRIVEPULLUPFILTER << 4) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 161 #define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */
<> 128:9bcdf88f62b0 162 #define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */
<> 128:9bcdf88f62b0 163 #define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 164 #define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 165 #define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 166 #define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 167 #define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 168 #define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 169 #define _GPIO_P_MODEL_MODE2_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 170 #define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 171 #define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 172 #define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 173 #define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 174 #define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 175 #define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 176 #define _GPIO_P_MODEL_MODE2_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 177 #define _GPIO_P_MODEL_MODE2_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 178 #define _GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 179 #define _GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 180 #define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 181 #define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 182 #define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 183 #define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 184 #define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 185 #define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 186 #define GPIO_P_MODEL_MODE2_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE2_PUSHPULLDRIVE << 8) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 187 #define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 188 #define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 189 #define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 190 #define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 191 #define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 192 #define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 193 #define GPIO_P_MODEL_MODE2_WIREDANDDRIVE (_GPIO_P_MODEL_MODE2_WIREDANDDRIVE << 8) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 194 #define GPIO_P_MODEL_MODE2_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE2_WIREDANDDRIVEFILTER << 8) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 195 #define GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUP << 8) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 196 #define GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDDRIVEPULLUPFILTER << 8) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 197 #define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */
<> 128:9bcdf88f62b0 198 #define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */
<> 128:9bcdf88f62b0 199 #define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 200 #define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 201 #define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 202 #define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 203 #define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 204 #define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 205 #define _GPIO_P_MODEL_MODE3_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 206 #define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 207 #define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 208 #define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 209 #define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 210 #define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 211 #define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 212 #define _GPIO_P_MODEL_MODE3_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 213 #define _GPIO_P_MODEL_MODE3_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 214 #define _GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 215 #define _GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 216 #define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 217 #define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 218 #define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 219 #define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 220 #define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 221 #define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 222 #define GPIO_P_MODEL_MODE3_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE3_PUSHPULLDRIVE << 12) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 223 #define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 224 #define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 225 #define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 226 #define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 227 #define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 228 #define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 229 #define GPIO_P_MODEL_MODE3_WIREDANDDRIVE (_GPIO_P_MODEL_MODE3_WIREDANDDRIVE << 12) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 230 #define GPIO_P_MODEL_MODE3_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE3_WIREDANDDRIVEFILTER << 12) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 231 #define GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUP << 12) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 232 #define GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDDRIVEPULLUPFILTER << 12) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 233 #define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */
<> 128:9bcdf88f62b0 234 #define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */
<> 128:9bcdf88f62b0 235 #define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 236 #define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 237 #define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 238 #define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 239 #define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 240 #define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 241 #define _GPIO_P_MODEL_MODE4_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 242 #define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 243 #define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 244 #define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 245 #define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 246 #define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 247 #define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 248 #define _GPIO_P_MODEL_MODE4_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 249 #define _GPIO_P_MODEL_MODE4_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 250 #define _GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 251 #define _GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 252 #define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 253 #define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 254 #define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 255 #define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 256 #define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 257 #define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 258 #define GPIO_P_MODEL_MODE4_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE4_PUSHPULLDRIVE << 16) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 259 #define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 260 #define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 261 #define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 262 #define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 263 #define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 264 #define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 265 #define GPIO_P_MODEL_MODE4_WIREDANDDRIVE (_GPIO_P_MODEL_MODE4_WIREDANDDRIVE << 16) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 266 #define GPIO_P_MODEL_MODE4_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE4_WIREDANDDRIVEFILTER << 16) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 267 #define GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUP << 16) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 268 #define GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDDRIVEPULLUPFILTER << 16) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 269 #define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */
<> 128:9bcdf88f62b0 270 #define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */
<> 128:9bcdf88f62b0 271 #define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 272 #define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 273 #define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 274 #define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 275 #define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 276 #define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 277 #define _GPIO_P_MODEL_MODE5_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 278 #define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 279 #define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 280 #define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 281 #define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 282 #define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 283 #define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 284 #define _GPIO_P_MODEL_MODE5_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 285 #define _GPIO_P_MODEL_MODE5_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 286 #define _GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 287 #define _GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 288 #define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 289 #define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 290 #define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 291 #define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 292 #define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 293 #define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 294 #define GPIO_P_MODEL_MODE5_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE5_PUSHPULLDRIVE << 20) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 295 #define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 296 #define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 297 #define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 298 #define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 299 #define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 300 #define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 301 #define GPIO_P_MODEL_MODE5_WIREDANDDRIVE (_GPIO_P_MODEL_MODE5_WIREDANDDRIVE << 20) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 302 #define GPIO_P_MODEL_MODE5_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE5_WIREDANDDRIVEFILTER << 20) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 303 #define GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUP << 20) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 304 #define GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDDRIVEPULLUPFILTER << 20) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 305 #define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */
<> 128:9bcdf88f62b0 306 #define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */
<> 128:9bcdf88f62b0 307 #define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 308 #define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 309 #define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 310 #define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 311 #define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 312 #define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 313 #define _GPIO_P_MODEL_MODE6_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 314 #define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 315 #define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 316 #define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 317 #define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 318 #define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 319 #define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 320 #define _GPIO_P_MODEL_MODE6_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 321 #define _GPIO_P_MODEL_MODE6_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 322 #define _GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 323 #define _GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 324 #define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 325 #define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 326 #define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 327 #define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 328 #define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 329 #define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 330 #define GPIO_P_MODEL_MODE6_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE6_PUSHPULLDRIVE << 24) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 331 #define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 332 #define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 333 #define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 334 #define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 335 #define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 336 #define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 337 #define GPIO_P_MODEL_MODE6_WIREDANDDRIVE (_GPIO_P_MODEL_MODE6_WIREDANDDRIVE << 24) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 338 #define GPIO_P_MODEL_MODE6_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE6_WIREDANDDRIVEFILTER << 24) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 339 #define GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUP << 24) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 340 #define GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDDRIVEPULLUPFILTER << 24) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 341 #define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */
<> 128:9bcdf88f62b0 342 #define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */
<> 128:9bcdf88f62b0 343 #define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 344 #define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 345 #define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 346 #define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 347 #define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 348 #define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 349 #define _GPIO_P_MODEL_MODE7_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 350 #define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 351 #define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 352 #define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 353 #define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 354 #define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 355 #define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 356 #define _GPIO_P_MODEL_MODE7_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 357 #define _GPIO_P_MODEL_MODE7_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 358 #define _GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 359 #define _GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 360 #define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 361 #define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 362 #define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 363 #define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 364 #define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 365 #define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 366 #define GPIO_P_MODEL_MODE7_PUSHPULLDRIVE (_GPIO_P_MODEL_MODE7_PUSHPULLDRIVE << 28) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 367 #define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 368 #define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 369 #define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 370 #define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 371 #define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 372 #define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 373 #define GPIO_P_MODEL_MODE7_WIREDANDDRIVE (_GPIO_P_MODEL_MODE7_WIREDANDDRIVE << 28) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 374 #define GPIO_P_MODEL_MODE7_WIREDANDDRIVEFILTER (_GPIO_P_MODEL_MODE7_WIREDANDDRIVEFILTER << 28) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 375 #define GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUP << 28) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 376 #define GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDDRIVEPULLUPFILTER << 28) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEL */
<> 128:9bcdf88f62b0 377
<> 128:9bcdf88f62b0 378 /* Bit fields for GPIO P_MODEH */
<> 128:9bcdf88f62b0 379 #define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 380 #define _GPIO_P_MODEH_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 381 #define _GPIO_P_MODEH_MODE8_SHIFT 0 /**< Shift value for GPIO_MODE8 */
<> 128:9bcdf88f62b0 382 #define _GPIO_P_MODEH_MODE8_MASK 0xFUL /**< Bit mask for GPIO_MODE8 */
<> 128:9bcdf88f62b0 383 #define _GPIO_P_MODEH_MODE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 384 #define _GPIO_P_MODEH_MODE8_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 385 #define _GPIO_P_MODEH_MODE8_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 386 #define _GPIO_P_MODEH_MODE8_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 387 #define _GPIO_P_MODEH_MODE8_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 388 #define _GPIO_P_MODEH_MODE8_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 389 #define _GPIO_P_MODEH_MODE8_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 390 #define _GPIO_P_MODEH_MODE8_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 391 #define _GPIO_P_MODEH_MODE8_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 392 #define _GPIO_P_MODEH_MODE8_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 393 #define _GPIO_P_MODEH_MODE8_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 394 #define _GPIO_P_MODEH_MODE8_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 395 #define _GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 396 #define _GPIO_P_MODEH_MODE8_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 397 #define _GPIO_P_MODEH_MODE8_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 398 #define _GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 399 #define _GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 400 #define GPIO_P_MODEH_MODE8_DEFAULT (_GPIO_P_MODEH_MODE8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 401 #define GPIO_P_MODEH_MODE8_DISABLED (_GPIO_P_MODEH_MODE8_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 402 #define GPIO_P_MODEH_MODE8_INPUT (_GPIO_P_MODEH_MODE8_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 403 #define GPIO_P_MODEH_MODE8_INPUTPULL (_GPIO_P_MODEH_MODE8_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 404 #define GPIO_P_MODEH_MODE8_INPUTPULLFILTER (_GPIO_P_MODEH_MODE8_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 405 #define GPIO_P_MODEH_MODE8_PUSHPULL (_GPIO_P_MODEH_MODE8_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 406 #define GPIO_P_MODEH_MODE8_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE8_PUSHPULLDRIVE << 0) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 407 #define GPIO_P_MODEH_MODE8_WIREDOR (_GPIO_P_MODEH_MODE8_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 408 #define GPIO_P_MODEH_MODE8_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE8_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 409 #define GPIO_P_MODEH_MODE8_WIREDAND (_GPIO_P_MODEH_MODE8_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 410 #define GPIO_P_MODEH_MODE8_WIREDANDFILTER (_GPIO_P_MODEH_MODE8_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 411 #define GPIO_P_MODEH_MODE8_WIREDANDPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 412 #define GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 413 #define GPIO_P_MODEH_MODE8_WIREDANDDRIVE (_GPIO_P_MODEH_MODE8_WIREDANDDRIVE << 0) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 414 #define GPIO_P_MODEH_MODE8_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE8_WIREDANDDRIVEFILTER << 0) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 415 #define GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUP << 0) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 416 #define GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE8_WIREDANDDRIVEPULLUPFILTER << 0) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 417 #define _GPIO_P_MODEH_MODE9_SHIFT 4 /**< Shift value for GPIO_MODE9 */
<> 128:9bcdf88f62b0 418 #define _GPIO_P_MODEH_MODE9_MASK 0xF0UL /**< Bit mask for GPIO_MODE9 */
<> 128:9bcdf88f62b0 419 #define _GPIO_P_MODEH_MODE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 420 #define _GPIO_P_MODEH_MODE9_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 421 #define _GPIO_P_MODEH_MODE9_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 422 #define _GPIO_P_MODEH_MODE9_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 423 #define _GPIO_P_MODEH_MODE9_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 424 #define _GPIO_P_MODEH_MODE9_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 425 #define _GPIO_P_MODEH_MODE9_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 426 #define _GPIO_P_MODEH_MODE9_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 427 #define _GPIO_P_MODEH_MODE9_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 428 #define _GPIO_P_MODEH_MODE9_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 429 #define _GPIO_P_MODEH_MODE9_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 430 #define _GPIO_P_MODEH_MODE9_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 431 #define _GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 432 #define _GPIO_P_MODEH_MODE9_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 433 #define _GPIO_P_MODEH_MODE9_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 434 #define _GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 435 #define _GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 436 #define GPIO_P_MODEH_MODE9_DEFAULT (_GPIO_P_MODEH_MODE9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 437 #define GPIO_P_MODEH_MODE9_DISABLED (_GPIO_P_MODEH_MODE9_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 438 #define GPIO_P_MODEH_MODE9_INPUT (_GPIO_P_MODEH_MODE9_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 439 #define GPIO_P_MODEH_MODE9_INPUTPULL (_GPIO_P_MODEH_MODE9_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 440 #define GPIO_P_MODEH_MODE9_INPUTPULLFILTER (_GPIO_P_MODEH_MODE9_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 441 #define GPIO_P_MODEH_MODE9_PUSHPULL (_GPIO_P_MODEH_MODE9_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 442 #define GPIO_P_MODEH_MODE9_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE9_PUSHPULLDRIVE << 4) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 443 #define GPIO_P_MODEH_MODE9_WIREDOR (_GPIO_P_MODEH_MODE9_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 444 #define GPIO_P_MODEH_MODE9_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE9_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 445 #define GPIO_P_MODEH_MODE9_WIREDAND (_GPIO_P_MODEH_MODE9_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 446 #define GPIO_P_MODEH_MODE9_WIREDANDFILTER (_GPIO_P_MODEH_MODE9_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 447 #define GPIO_P_MODEH_MODE9_WIREDANDPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 448 #define GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 449 #define GPIO_P_MODEH_MODE9_WIREDANDDRIVE (_GPIO_P_MODEH_MODE9_WIREDANDDRIVE << 4) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 450 #define GPIO_P_MODEH_MODE9_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE9_WIREDANDDRIVEFILTER << 4) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 451 #define GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUP << 4) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 452 #define GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE9_WIREDANDDRIVEPULLUPFILTER << 4) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 453 #define _GPIO_P_MODEH_MODE10_SHIFT 8 /**< Shift value for GPIO_MODE10 */
<> 128:9bcdf88f62b0 454 #define _GPIO_P_MODEH_MODE10_MASK 0xF00UL /**< Bit mask for GPIO_MODE10 */
<> 128:9bcdf88f62b0 455 #define _GPIO_P_MODEH_MODE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 456 #define _GPIO_P_MODEH_MODE10_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 457 #define _GPIO_P_MODEH_MODE10_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 458 #define _GPIO_P_MODEH_MODE10_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 459 #define _GPIO_P_MODEH_MODE10_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 460 #define _GPIO_P_MODEH_MODE10_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 461 #define _GPIO_P_MODEH_MODE10_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 462 #define _GPIO_P_MODEH_MODE10_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 463 #define _GPIO_P_MODEH_MODE10_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 464 #define _GPIO_P_MODEH_MODE10_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 465 #define _GPIO_P_MODEH_MODE10_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 466 #define _GPIO_P_MODEH_MODE10_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 467 #define _GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 468 #define _GPIO_P_MODEH_MODE10_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 469 #define _GPIO_P_MODEH_MODE10_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 470 #define _GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 471 #define _GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 472 #define GPIO_P_MODEH_MODE10_DEFAULT (_GPIO_P_MODEH_MODE10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 473 #define GPIO_P_MODEH_MODE10_DISABLED (_GPIO_P_MODEH_MODE10_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 474 #define GPIO_P_MODEH_MODE10_INPUT (_GPIO_P_MODEH_MODE10_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 475 #define GPIO_P_MODEH_MODE10_INPUTPULL (_GPIO_P_MODEH_MODE10_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 476 #define GPIO_P_MODEH_MODE10_INPUTPULLFILTER (_GPIO_P_MODEH_MODE10_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 477 #define GPIO_P_MODEH_MODE10_PUSHPULL (_GPIO_P_MODEH_MODE10_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 478 #define GPIO_P_MODEH_MODE10_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE10_PUSHPULLDRIVE << 8) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 479 #define GPIO_P_MODEH_MODE10_WIREDOR (_GPIO_P_MODEH_MODE10_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 480 #define GPIO_P_MODEH_MODE10_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE10_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 481 #define GPIO_P_MODEH_MODE10_WIREDAND (_GPIO_P_MODEH_MODE10_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 482 #define GPIO_P_MODEH_MODE10_WIREDANDFILTER (_GPIO_P_MODEH_MODE10_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 483 #define GPIO_P_MODEH_MODE10_WIREDANDPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 484 #define GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 485 #define GPIO_P_MODEH_MODE10_WIREDANDDRIVE (_GPIO_P_MODEH_MODE10_WIREDANDDRIVE << 8) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 486 #define GPIO_P_MODEH_MODE10_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE10_WIREDANDDRIVEFILTER << 8) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 487 #define GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUP << 8) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 488 #define GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE10_WIREDANDDRIVEPULLUPFILTER << 8) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 489 #define _GPIO_P_MODEH_MODE11_SHIFT 12 /**< Shift value for GPIO_MODE11 */
<> 128:9bcdf88f62b0 490 #define _GPIO_P_MODEH_MODE11_MASK 0xF000UL /**< Bit mask for GPIO_MODE11 */
<> 128:9bcdf88f62b0 491 #define _GPIO_P_MODEH_MODE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 492 #define _GPIO_P_MODEH_MODE11_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 493 #define _GPIO_P_MODEH_MODE11_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 494 #define _GPIO_P_MODEH_MODE11_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 495 #define _GPIO_P_MODEH_MODE11_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 496 #define _GPIO_P_MODEH_MODE11_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 497 #define _GPIO_P_MODEH_MODE11_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 498 #define _GPIO_P_MODEH_MODE11_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 499 #define _GPIO_P_MODEH_MODE11_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 500 #define _GPIO_P_MODEH_MODE11_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 501 #define _GPIO_P_MODEH_MODE11_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 502 #define _GPIO_P_MODEH_MODE11_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 503 #define _GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 504 #define _GPIO_P_MODEH_MODE11_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 505 #define _GPIO_P_MODEH_MODE11_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 506 #define _GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 507 #define _GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 508 #define GPIO_P_MODEH_MODE11_DEFAULT (_GPIO_P_MODEH_MODE11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 509 #define GPIO_P_MODEH_MODE11_DISABLED (_GPIO_P_MODEH_MODE11_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 510 #define GPIO_P_MODEH_MODE11_INPUT (_GPIO_P_MODEH_MODE11_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 511 #define GPIO_P_MODEH_MODE11_INPUTPULL (_GPIO_P_MODEH_MODE11_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 512 #define GPIO_P_MODEH_MODE11_INPUTPULLFILTER (_GPIO_P_MODEH_MODE11_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 513 #define GPIO_P_MODEH_MODE11_PUSHPULL (_GPIO_P_MODEH_MODE11_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 514 #define GPIO_P_MODEH_MODE11_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE11_PUSHPULLDRIVE << 12) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 515 #define GPIO_P_MODEH_MODE11_WIREDOR (_GPIO_P_MODEH_MODE11_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 516 #define GPIO_P_MODEH_MODE11_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE11_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 517 #define GPIO_P_MODEH_MODE11_WIREDAND (_GPIO_P_MODEH_MODE11_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 518 #define GPIO_P_MODEH_MODE11_WIREDANDFILTER (_GPIO_P_MODEH_MODE11_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 519 #define GPIO_P_MODEH_MODE11_WIREDANDPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 520 #define GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 521 #define GPIO_P_MODEH_MODE11_WIREDANDDRIVE (_GPIO_P_MODEH_MODE11_WIREDANDDRIVE << 12) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 522 #define GPIO_P_MODEH_MODE11_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE11_WIREDANDDRIVEFILTER << 12) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 523 #define GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUP << 12) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 524 #define GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE11_WIREDANDDRIVEPULLUPFILTER << 12) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 525 #define _GPIO_P_MODEH_MODE12_SHIFT 16 /**< Shift value for GPIO_MODE12 */
<> 128:9bcdf88f62b0 526 #define _GPIO_P_MODEH_MODE12_MASK 0xF0000UL /**< Bit mask for GPIO_MODE12 */
<> 128:9bcdf88f62b0 527 #define _GPIO_P_MODEH_MODE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 528 #define _GPIO_P_MODEH_MODE12_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 529 #define _GPIO_P_MODEH_MODE12_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 530 #define _GPIO_P_MODEH_MODE12_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 531 #define _GPIO_P_MODEH_MODE12_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 532 #define _GPIO_P_MODEH_MODE12_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 533 #define _GPIO_P_MODEH_MODE12_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 534 #define _GPIO_P_MODEH_MODE12_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 535 #define _GPIO_P_MODEH_MODE12_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 536 #define _GPIO_P_MODEH_MODE12_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 537 #define _GPIO_P_MODEH_MODE12_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 538 #define _GPIO_P_MODEH_MODE12_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 539 #define _GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 540 #define _GPIO_P_MODEH_MODE12_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 541 #define _GPIO_P_MODEH_MODE12_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 542 #define _GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 543 #define _GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 544 #define GPIO_P_MODEH_MODE12_DEFAULT (_GPIO_P_MODEH_MODE12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 545 #define GPIO_P_MODEH_MODE12_DISABLED (_GPIO_P_MODEH_MODE12_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 546 #define GPIO_P_MODEH_MODE12_INPUT (_GPIO_P_MODEH_MODE12_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 547 #define GPIO_P_MODEH_MODE12_INPUTPULL (_GPIO_P_MODEH_MODE12_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 548 #define GPIO_P_MODEH_MODE12_INPUTPULLFILTER (_GPIO_P_MODEH_MODE12_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 549 #define GPIO_P_MODEH_MODE12_PUSHPULL (_GPIO_P_MODEH_MODE12_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 550 #define GPIO_P_MODEH_MODE12_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE12_PUSHPULLDRIVE << 16) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 551 #define GPIO_P_MODEH_MODE12_WIREDOR (_GPIO_P_MODEH_MODE12_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 552 #define GPIO_P_MODEH_MODE12_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE12_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 553 #define GPIO_P_MODEH_MODE12_WIREDAND (_GPIO_P_MODEH_MODE12_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 554 #define GPIO_P_MODEH_MODE12_WIREDANDFILTER (_GPIO_P_MODEH_MODE12_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 555 #define GPIO_P_MODEH_MODE12_WIREDANDPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 556 #define GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 557 #define GPIO_P_MODEH_MODE12_WIREDANDDRIVE (_GPIO_P_MODEH_MODE12_WIREDANDDRIVE << 16) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 558 #define GPIO_P_MODEH_MODE12_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE12_WIREDANDDRIVEFILTER << 16) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 559 #define GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUP << 16) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 560 #define GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE12_WIREDANDDRIVEPULLUPFILTER << 16) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 561 #define _GPIO_P_MODEH_MODE13_SHIFT 20 /**< Shift value for GPIO_MODE13 */
<> 128:9bcdf88f62b0 562 #define _GPIO_P_MODEH_MODE13_MASK 0xF00000UL /**< Bit mask for GPIO_MODE13 */
<> 128:9bcdf88f62b0 563 #define _GPIO_P_MODEH_MODE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 564 #define _GPIO_P_MODEH_MODE13_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 565 #define _GPIO_P_MODEH_MODE13_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 566 #define _GPIO_P_MODEH_MODE13_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 567 #define _GPIO_P_MODEH_MODE13_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 568 #define _GPIO_P_MODEH_MODE13_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 569 #define _GPIO_P_MODEH_MODE13_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 570 #define _GPIO_P_MODEH_MODE13_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 571 #define _GPIO_P_MODEH_MODE13_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 572 #define _GPIO_P_MODEH_MODE13_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 573 #define _GPIO_P_MODEH_MODE13_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 574 #define _GPIO_P_MODEH_MODE13_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 575 #define _GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 576 #define _GPIO_P_MODEH_MODE13_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 577 #define _GPIO_P_MODEH_MODE13_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 578 #define _GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 579 #define _GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 580 #define GPIO_P_MODEH_MODE13_DEFAULT (_GPIO_P_MODEH_MODE13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 581 #define GPIO_P_MODEH_MODE13_DISABLED (_GPIO_P_MODEH_MODE13_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 582 #define GPIO_P_MODEH_MODE13_INPUT (_GPIO_P_MODEH_MODE13_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 583 #define GPIO_P_MODEH_MODE13_INPUTPULL (_GPIO_P_MODEH_MODE13_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 584 #define GPIO_P_MODEH_MODE13_INPUTPULLFILTER (_GPIO_P_MODEH_MODE13_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 585 #define GPIO_P_MODEH_MODE13_PUSHPULL (_GPIO_P_MODEH_MODE13_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 586 #define GPIO_P_MODEH_MODE13_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE13_PUSHPULLDRIVE << 20) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 587 #define GPIO_P_MODEH_MODE13_WIREDOR (_GPIO_P_MODEH_MODE13_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 588 #define GPIO_P_MODEH_MODE13_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE13_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 589 #define GPIO_P_MODEH_MODE13_WIREDAND (_GPIO_P_MODEH_MODE13_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 590 #define GPIO_P_MODEH_MODE13_WIREDANDFILTER (_GPIO_P_MODEH_MODE13_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 591 #define GPIO_P_MODEH_MODE13_WIREDANDPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 592 #define GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 593 #define GPIO_P_MODEH_MODE13_WIREDANDDRIVE (_GPIO_P_MODEH_MODE13_WIREDANDDRIVE << 20) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 594 #define GPIO_P_MODEH_MODE13_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE13_WIREDANDDRIVEFILTER << 20) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 595 #define GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUP << 20) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 596 #define GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE13_WIREDANDDRIVEPULLUPFILTER << 20) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 597 #define _GPIO_P_MODEH_MODE14_SHIFT 24 /**< Shift value for GPIO_MODE14 */
<> 128:9bcdf88f62b0 598 #define _GPIO_P_MODEH_MODE14_MASK 0xF000000UL /**< Bit mask for GPIO_MODE14 */
<> 128:9bcdf88f62b0 599 #define _GPIO_P_MODEH_MODE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 600 #define _GPIO_P_MODEH_MODE14_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 601 #define _GPIO_P_MODEH_MODE14_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 602 #define _GPIO_P_MODEH_MODE14_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 603 #define _GPIO_P_MODEH_MODE14_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 604 #define _GPIO_P_MODEH_MODE14_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 605 #define _GPIO_P_MODEH_MODE14_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 606 #define _GPIO_P_MODEH_MODE14_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 607 #define _GPIO_P_MODEH_MODE14_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 608 #define _GPIO_P_MODEH_MODE14_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 609 #define _GPIO_P_MODEH_MODE14_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 610 #define _GPIO_P_MODEH_MODE14_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 611 #define _GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 612 #define _GPIO_P_MODEH_MODE14_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 613 #define _GPIO_P_MODEH_MODE14_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 614 #define _GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 615 #define _GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 616 #define GPIO_P_MODEH_MODE14_DEFAULT (_GPIO_P_MODEH_MODE14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 617 #define GPIO_P_MODEH_MODE14_DISABLED (_GPIO_P_MODEH_MODE14_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 618 #define GPIO_P_MODEH_MODE14_INPUT (_GPIO_P_MODEH_MODE14_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 619 #define GPIO_P_MODEH_MODE14_INPUTPULL (_GPIO_P_MODEH_MODE14_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 620 #define GPIO_P_MODEH_MODE14_INPUTPULLFILTER (_GPIO_P_MODEH_MODE14_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 621 #define GPIO_P_MODEH_MODE14_PUSHPULL (_GPIO_P_MODEH_MODE14_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 622 #define GPIO_P_MODEH_MODE14_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE14_PUSHPULLDRIVE << 24) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 623 #define GPIO_P_MODEH_MODE14_WIREDOR (_GPIO_P_MODEH_MODE14_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 624 #define GPIO_P_MODEH_MODE14_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE14_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 625 #define GPIO_P_MODEH_MODE14_WIREDAND (_GPIO_P_MODEH_MODE14_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 626 #define GPIO_P_MODEH_MODE14_WIREDANDFILTER (_GPIO_P_MODEH_MODE14_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 627 #define GPIO_P_MODEH_MODE14_WIREDANDPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 628 #define GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 629 #define GPIO_P_MODEH_MODE14_WIREDANDDRIVE (_GPIO_P_MODEH_MODE14_WIREDANDDRIVE << 24) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 630 #define GPIO_P_MODEH_MODE14_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE14_WIREDANDDRIVEFILTER << 24) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 631 #define GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUP << 24) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 632 #define GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE14_WIREDANDDRIVEPULLUPFILTER << 24) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 633 #define _GPIO_P_MODEH_MODE15_SHIFT 28 /**< Shift value for GPIO_MODE15 */
<> 128:9bcdf88f62b0 634 #define _GPIO_P_MODEH_MODE15_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE15 */
<> 128:9bcdf88f62b0 635 #define _GPIO_P_MODEH_MODE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 636 #define _GPIO_P_MODEH_MODE15_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 637 #define _GPIO_P_MODEH_MODE15_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 638 #define _GPIO_P_MODEH_MODE15_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 639 #define _GPIO_P_MODEH_MODE15_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 640 #define _GPIO_P_MODEH_MODE15_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 641 #define _GPIO_P_MODEH_MODE15_PUSHPULLDRIVE 0x00000005UL /**< Mode PUSHPULLDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 642 #define _GPIO_P_MODEH_MODE15_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 643 #define _GPIO_P_MODEH_MODE15_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 644 #define _GPIO_P_MODEH_MODE15_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 645 #define _GPIO_P_MODEH_MODE15_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 646 #define _GPIO_P_MODEH_MODE15_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 647 #define _GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 648 #define _GPIO_P_MODEH_MODE15_WIREDANDDRIVE 0x0000000CUL /**< Mode WIREDANDDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 649 #define _GPIO_P_MODEH_MODE15_WIREDANDDRIVEFILTER 0x0000000DUL /**< Mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 650 #define _GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUP 0x0000000EUL /**< Mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 651 #define _GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 652 #define GPIO_P_MODEH_MODE15_DEFAULT (_GPIO_P_MODEH_MODE15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 653 #define GPIO_P_MODEH_MODE15_DISABLED (_GPIO_P_MODEH_MODE15_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 654 #define GPIO_P_MODEH_MODE15_INPUT (_GPIO_P_MODEH_MODE15_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 655 #define GPIO_P_MODEH_MODE15_INPUTPULL (_GPIO_P_MODEH_MODE15_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 656 #define GPIO_P_MODEH_MODE15_INPUTPULLFILTER (_GPIO_P_MODEH_MODE15_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 657 #define GPIO_P_MODEH_MODE15_PUSHPULL (_GPIO_P_MODEH_MODE15_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 658 #define GPIO_P_MODEH_MODE15_PUSHPULLDRIVE (_GPIO_P_MODEH_MODE15_PUSHPULLDRIVE << 28) /**< Shifted mode PUSHPULLDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 659 #define GPIO_P_MODEH_MODE15_WIREDOR (_GPIO_P_MODEH_MODE15_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 660 #define GPIO_P_MODEH_MODE15_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE15_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 661 #define GPIO_P_MODEH_MODE15_WIREDAND (_GPIO_P_MODEH_MODE15_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 662 #define GPIO_P_MODEH_MODE15_WIREDANDFILTER (_GPIO_P_MODEH_MODE15_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 663 #define GPIO_P_MODEH_MODE15_WIREDANDPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 664 #define GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 665 #define GPIO_P_MODEH_MODE15_WIREDANDDRIVE (_GPIO_P_MODEH_MODE15_WIREDANDDRIVE << 28) /**< Shifted mode WIREDANDDRIVE for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 666 #define GPIO_P_MODEH_MODE15_WIREDANDDRIVEFILTER (_GPIO_P_MODEH_MODE15_WIREDANDDRIVEFILTER << 28) /**< Shifted mode WIREDANDDRIVEFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 667 #define GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUP (_GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUP << 28) /**< Shifted mode WIREDANDDRIVEPULLUP for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 668 #define GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUPFILTER (_GPIO_P_MODEH_MODE15_WIREDANDDRIVEPULLUPFILTER << 28) /**< Shifted mode WIREDANDDRIVEPULLUPFILTER for GPIO_P_MODEH */
<> 128:9bcdf88f62b0 669
<> 128:9bcdf88f62b0 670 /* Bit fields for GPIO P_DOUT */
<> 128:9bcdf88f62b0 671 #define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */
<> 128:9bcdf88f62b0 672 #define _GPIO_P_DOUT_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUT */
<> 128:9bcdf88f62b0 673 #define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */
<> 128:9bcdf88f62b0 674 #define _GPIO_P_DOUT_DOUT_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUT */
<> 128:9bcdf88f62b0 675 #define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */
<> 128:9bcdf88f62b0 676 #define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */
<> 128:9bcdf88f62b0 677
<> 128:9bcdf88f62b0 678 /* Bit fields for GPIO P_DOUTSET */
<> 128:9bcdf88f62b0 679 #define _GPIO_P_DOUTSET_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUTSET */
<> 128:9bcdf88f62b0 680 #define _GPIO_P_DOUTSET_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUTSET */
<> 128:9bcdf88f62b0 681 #define _GPIO_P_DOUTSET_DOUTSET_SHIFT 0 /**< Shift value for GPIO_DOUTSET */
<> 128:9bcdf88f62b0 682 #define _GPIO_P_DOUTSET_DOUTSET_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUTSET */
<> 128:9bcdf88f62b0 683 #define _GPIO_P_DOUTSET_DOUTSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUTSET */
<> 128:9bcdf88f62b0 684 #define GPIO_P_DOUTSET_DOUTSET_DEFAULT (_GPIO_P_DOUTSET_DOUTSET_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTSET */
<> 128:9bcdf88f62b0 685
<> 128:9bcdf88f62b0 686 /* Bit fields for GPIO P_DOUTCLR */
<> 128:9bcdf88f62b0 687 #define _GPIO_P_DOUTCLR_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUTCLR */
<> 128:9bcdf88f62b0 688 #define _GPIO_P_DOUTCLR_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUTCLR */
<> 128:9bcdf88f62b0 689 #define _GPIO_P_DOUTCLR_DOUTCLR_SHIFT 0 /**< Shift value for GPIO_DOUTCLR */
<> 128:9bcdf88f62b0 690 #define _GPIO_P_DOUTCLR_DOUTCLR_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUTCLR */
<> 128:9bcdf88f62b0 691 #define _GPIO_P_DOUTCLR_DOUTCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUTCLR */
<> 128:9bcdf88f62b0 692 #define GPIO_P_DOUTCLR_DOUTCLR_DEFAULT (_GPIO_P_DOUTCLR_DOUTCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTCLR */
<> 128:9bcdf88f62b0 693
<> 128:9bcdf88f62b0 694 /* Bit fields for GPIO P_DOUTTGL */
<> 128:9bcdf88f62b0 695 #define _GPIO_P_DOUTTGL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUTTGL */
<> 128:9bcdf88f62b0 696 #define _GPIO_P_DOUTTGL_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DOUTTGL */
<> 128:9bcdf88f62b0 697 #define _GPIO_P_DOUTTGL_DOUTTGL_SHIFT 0 /**< Shift value for GPIO_DOUTTGL */
<> 128:9bcdf88f62b0 698 #define _GPIO_P_DOUTTGL_DOUTTGL_MASK 0xFFFFUL /**< Bit mask for GPIO_DOUTTGL */
<> 128:9bcdf88f62b0 699 #define _GPIO_P_DOUTTGL_DOUTTGL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUTTGL */
<> 128:9bcdf88f62b0 700 #define GPIO_P_DOUTTGL_DOUTTGL_DEFAULT (_GPIO_P_DOUTTGL_DOUTTGL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUTTGL */
<> 128:9bcdf88f62b0 701
<> 128:9bcdf88f62b0 702 /* Bit fields for GPIO P_DIN */
<> 128:9bcdf88f62b0 703 #define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */
<> 128:9bcdf88f62b0 704 #define _GPIO_P_DIN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_DIN */
<> 128:9bcdf88f62b0 705 #define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */
<> 128:9bcdf88f62b0 706 #define _GPIO_P_DIN_DIN_MASK 0xFFFFUL /**< Bit mask for GPIO_DIN */
<> 128:9bcdf88f62b0 707 #define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */
<> 128:9bcdf88f62b0 708 #define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */
<> 128:9bcdf88f62b0 709
<> 128:9bcdf88f62b0 710 /* Bit fields for GPIO P_PINLOCKN */
<> 128:9bcdf88f62b0 711 #define _GPIO_P_PINLOCKN_RESETVALUE 0x0000FFFFUL /**< Default value for GPIO_P_PINLOCKN */
<> 128:9bcdf88f62b0 712 #define _GPIO_P_PINLOCKN_MASK 0x0000FFFFUL /**< Mask for GPIO_P_PINLOCKN */
<> 128:9bcdf88f62b0 713 #define _GPIO_P_PINLOCKN_PINLOCKN_SHIFT 0 /**< Shift value for GPIO_PINLOCKN */
<> 128:9bcdf88f62b0 714 #define _GPIO_P_PINLOCKN_PINLOCKN_MASK 0xFFFFUL /**< Bit mask for GPIO_PINLOCKN */
<> 128:9bcdf88f62b0 715 #define _GPIO_P_PINLOCKN_PINLOCKN_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for GPIO_P_PINLOCKN */
<> 128:9bcdf88f62b0 716 #define GPIO_P_PINLOCKN_PINLOCKN_DEFAULT (_GPIO_P_PINLOCKN_PINLOCKN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_PINLOCKN */
<> 128:9bcdf88f62b0 717
<> 128:9bcdf88f62b0 718 /* Bit fields for GPIO EXTIPSELL */
<> 128:9bcdf88f62b0 719 #define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 720 #define _GPIO_EXTIPSELL_MASK 0x77777777UL /**< Mask for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 721 #define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */
<> 128:9bcdf88f62b0 722 #define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0x7UL /**< Bit mask for GPIO_EXTIPSEL0 */
<> 128:9bcdf88f62b0 723 #define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 724 #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 725 #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 726 #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 727 #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 728 #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 729 #define _GPIO_EXTIPSELL_EXTIPSEL0_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 730 #define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 731 #define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 732 #define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 733 #define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 734 #define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 735 #define GPIO_EXTIPSELL_EXTIPSEL0_PORTE (_GPIO_EXTIPSELL_EXTIPSEL0_PORTE << 0) /**< Shifted mode PORTE for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 736 #define GPIO_EXTIPSELL_EXTIPSEL0_PORTF (_GPIO_EXTIPSELL_EXTIPSEL0_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 737 #define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */
<> 128:9bcdf88f62b0 738 #define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0x70UL /**< Bit mask for GPIO_EXTIPSEL1 */
<> 128:9bcdf88f62b0 739 #define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 740 #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 741 #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 742 #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 743 #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 744 #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 745 #define _GPIO_EXTIPSELL_EXTIPSEL1_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 746 #define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 747 #define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 748 #define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 749 #define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 750 #define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 751 #define GPIO_EXTIPSELL_EXTIPSEL1_PORTE (_GPIO_EXTIPSELL_EXTIPSEL1_PORTE << 4) /**< Shifted mode PORTE for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 752 #define GPIO_EXTIPSELL_EXTIPSEL1_PORTF (_GPIO_EXTIPSELL_EXTIPSEL1_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 753 #define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */
<> 128:9bcdf88f62b0 754 #define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0x700UL /**< Bit mask for GPIO_EXTIPSEL2 */
<> 128:9bcdf88f62b0 755 #define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 756 #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 757 #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 758 #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 759 #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 760 #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 761 #define _GPIO_EXTIPSELL_EXTIPSEL2_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 762 #define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 763 #define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 764 #define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 765 #define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 766 #define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 767 #define GPIO_EXTIPSELL_EXTIPSEL2_PORTE (_GPIO_EXTIPSELL_EXTIPSEL2_PORTE << 8) /**< Shifted mode PORTE for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 768 #define GPIO_EXTIPSELL_EXTIPSEL2_PORTF (_GPIO_EXTIPSELL_EXTIPSEL2_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 769 #define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */
<> 128:9bcdf88f62b0 770 #define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0x7000UL /**< Bit mask for GPIO_EXTIPSEL3 */
<> 128:9bcdf88f62b0 771 #define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 772 #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 773 #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 774 #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 775 #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 776 #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 777 #define _GPIO_EXTIPSELL_EXTIPSEL3_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 778 #define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 779 #define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 780 #define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 781 #define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 782 #define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 783 #define GPIO_EXTIPSELL_EXTIPSEL3_PORTE (_GPIO_EXTIPSELL_EXTIPSEL3_PORTE << 12) /**< Shifted mode PORTE for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 784 #define GPIO_EXTIPSELL_EXTIPSEL3_PORTF (_GPIO_EXTIPSELL_EXTIPSEL3_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 785 #define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */
<> 128:9bcdf88f62b0 786 #define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0x70000UL /**< Bit mask for GPIO_EXTIPSEL4 */
<> 128:9bcdf88f62b0 787 #define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 788 #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 789 #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 790 #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 791 #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 792 #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 793 #define _GPIO_EXTIPSELL_EXTIPSEL4_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 794 #define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 795 #define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 796 #define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 797 #define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 798 #define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 799 #define GPIO_EXTIPSELL_EXTIPSEL4_PORTE (_GPIO_EXTIPSELL_EXTIPSEL4_PORTE << 16) /**< Shifted mode PORTE for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 800 #define GPIO_EXTIPSELL_EXTIPSEL4_PORTF (_GPIO_EXTIPSELL_EXTIPSEL4_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 801 #define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */
<> 128:9bcdf88f62b0 802 #define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0x700000UL /**< Bit mask for GPIO_EXTIPSEL5 */
<> 128:9bcdf88f62b0 803 #define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 804 #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 805 #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 806 #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 807 #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 808 #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 809 #define _GPIO_EXTIPSELL_EXTIPSEL5_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 810 #define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 811 #define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 812 #define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 813 #define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 814 #define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 815 #define GPIO_EXTIPSELL_EXTIPSEL5_PORTE (_GPIO_EXTIPSELL_EXTIPSEL5_PORTE << 20) /**< Shifted mode PORTE for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 816 #define GPIO_EXTIPSELL_EXTIPSEL5_PORTF (_GPIO_EXTIPSELL_EXTIPSEL5_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 817 #define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */
<> 128:9bcdf88f62b0 818 #define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0x7000000UL /**< Bit mask for GPIO_EXTIPSEL6 */
<> 128:9bcdf88f62b0 819 #define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 820 #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 821 #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 822 #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 823 #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 824 #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 825 #define _GPIO_EXTIPSELL_EXTIPSEL6_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 826 #define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 827 #define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 828 #define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 829 #define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 830 #define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 831 #define GPIO_EXTIPSELL_EXTIPSEL6_PORTE (_GPIO_EXTIPSELL_EXTIPSEL6_PORTE << 24) /**< Shifted mode PORTE for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 832 #define GPIO_EXTIPSELL_EXTIPSEL6_PORTF (_GPIO_EXTIPSELL_EXTIPSEL6_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 833 #define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */
<> 128:9bcdf88f62b0 834 #define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0x70000000UL /**< Bit mask for GPIO_EXTIPSEL7 */
<> 128:9bcdf88f62b0 835 #define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 836 #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 837 #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 838 #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 839 #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 840 #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 841 #define _GPIO_EXTIPSELL_EXTIPSEL7_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 842 #define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 843 #define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 844 #define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 845 #define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 846 #define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 847 #define GPIO_EXTIPSELL_EXTIPSEL7_PORTE (_GPIO_EXTIPSELL_EXTIPSEL7_PORTE << 28) /**< Shifted mode PORTE for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 848 #define GPIO_EXTIPSELL_EXTIPSEL7_PORTF (_GPIO_EXTIPSELL_EXTIPSEL7_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELL */
<> 128:9bcdf88f62b0 849
<> 128:9bcdf88f62b0 850 /* Bit fields for GPIO EXTIPSELH */
<> 128:9bcdf88f62b0 851 #define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 852 #define _GPIO_EXTIPSELH_MASK 0x77777777UL /**< Mask for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 853 #define _GPIO_EXTIPSELH_EXTIPSEL8_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL8 */
<> 128:9bcdf88f62b0 854 #define _GPIO_EXTIPSELH_EXTIPSEL8_MASK 0x7UL /**< Bit mask for GPIO_EXTIPSEL8 */
<> 128:9bcdf88f62b0 855 #define _GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 856 #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 857 #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 858 #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 859 #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 860 #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 861 #define _GPIO_EXTIPSELH_EXTIPSEL8_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 862 #define GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL8_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 863 #define GPIO_EXTIPSELH_EXTIPSEL8_PORTA (_GPIO_EXTIPSELH_EXTIPSEL8_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 864 #define GPIO_EXTIPSELH_EXTIPSEL8_PORTB (_GPIO_EXTIPSELH_EXTIPSEL8_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 865 #define GPIO_EXTIPSELH_EXTIPSEL8_PORTC (_GPIO_EXTIPSELH_EXTIPSEL8_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 866 #define GPIO_EXTIPSELH_EXTIPSEL8_PORTD (_GPIO_EXTIPSELH_EXTIPSEL8_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 867 #define GPIO_EXTIPSELH_EXTIPSEL8_PORTE (_GPIO_EXTIPSELH_EXTIPSEL8_PORTE << 0) /**< Shifted mode PORTE for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 868 #define GPIO_EXTIPSELH_EXTIPSEL8_PORTF (_GPIO_EXTIPSELH_EXTIPSEL8_PORTF << 0) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 869 #define _GPIO_EXTIPSELH_EXTIPSEL9_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL9 */
<> 128:9bcdf88f62b0 870 #define _GPIO_EXTIPSELH_EXTIPSEL9_MASK 0x70UL /**< Bit mask for GPIO_EXTIPSEL9 */
<> 128:9bcdf88f62b0 871 #define _GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 872 #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 873 #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 874 #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 875 #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 876 #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 877 #define _GPIO_EXTIPSELH_EXTIPSEL9_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 878 #define GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL9_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 879 #define GPIO_EXTIPSELH_EXTIPSEL9_PORTA (_GPIO_EXTIPSELH_EXTIPSEL9_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 880 #define GPIO_EXTIPSELH_EXTIPSEL9_PORTB (_GPIO_EXTIPSELH_EXTIPSEL9_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 881 #define GPIO_EXTIPSELH_EXTIPSEL9_PORTC (_GPIO_EXTIPSELH_EXTIPSEL9_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 882 #define GPIO_EXTIPSELH_EXTIPSEL9_PORTD (_GPIO_EXTIPSELH_EXTIPSEL9_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 883 #define GPIO_EXTIPSELH_EXTIPSEL9_PORTE (_GPIO_EXTIPSELH_EXTIPSEL9_PORTE << 4) /**< Shifted mode PORTE for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 884 #define GPIO_EXTIPSELH_EXTIPSEL9_PORTF (_GPIO_EXTIPSELH_EXTIPSEL9_PORTF << 4) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 885 #define _GPIO_EXTIPSELH_EXTIPSEL10_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL10 */
<> 128:9bcdf88f62b0 886 #define _GPIO_EXTIPSELH_EXTIPSEL10_MASK 0x700UL /**< Bit mask for GPIO_EXTIPSEL10 */
<> 128:9bcdf88f62b0 887 #define _GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 888 #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 889 #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 890 #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 891 #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 892 #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 893 #define _GPIO_EXTIPSELH_EXTIPSEL10_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 894 #define GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL10_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 895 #define GPIO_EXTIPSELH_EXTIPSEL10_PORTA (_GPIO_EXTIPSELH_EXTIPSEL10_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 896 #define GPIO_EXTIPSELH_EXTIPSEL10_PORTB (_GPIO_EXTIPSELH_EXTIPSEL10_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 897 #define GPIO_EXTIPSELH_EXTIPSEL10_PORTC (_GPIO_EXTIPSELH_EXTIPSEL10_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 898 #define GPIO_EXTIPSELH_EXTIPSEL10_PORTD (_GPIO_EXTIPSELH_EXTIPSEL10_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 899 #define GPIO_EXTIPSELH_EXTIPSEL10_PORTE (_GPIO_EXTIPSELH_EXTIPSEL10_PORTE << 8) /**< Shifted mode PORTE for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 900 #define GPIO_EXTIPSELH_EXTIPSEL10_PORTF (_GPIO_EXTIPSELH_EXTIPSEL10_PORTF << 8) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 901 #define _GPIO_EXTIPSELH_EXTIPSEL11_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL11 */
<> 128:9bcdf88f62b0 902 #define _GPIO_EXTIPSELH_EXTIPSEL11_MASK 0x7000UL /**< Bit mask for GPIO_EXTIPSEL11 */
<> 128:9bcdf88f62b0 903 #define _GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 904 #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 905 #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 906 #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 907 #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 908 #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 909 #define _GPIO_EXTIPSELH_EXTIPSEL11_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 910 #define GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL11_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 911 #define GPIO_EXTIPSELH_EXTIPSEL11_PORTA (_GPIO_EXTIPSELH_EXTIPSEL11_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 912 #define GPIO_EXTIPSELH_EXTIPSEL11_PORTB (_GPIO_EXTIPSELH_EXTIPSEL11_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 913 #define GPIO_EXTIPSELH_EXTIPSEL11_PORTC (_GPIO_EXTIPSELH_EXTIPSEL11_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 914 #define GPIO_EXTIPSELH_EXTIPSEL11_PORTD (_GPIO_EXTIPSELH_EXTIPSEL11_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 915 #define GPIO_EXTIPSELH_EXTIPSEL11_PORTE (_GPIO_EXTIPSELH_EXTIPSEL11_PORTE << 12) /**< Shifted mode PORTE for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 916 #define GPIO_EXTIPSELH_EXTIPSEL11_PORTF (_GPIO_EXTIPSELH_EXTIPSEL11_PORTF << 12) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 917 #define _GPIO_EXTIPSELH_EXTIPSEL12_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL12 */
<> 128:9bcdf88f62b0 918 #define _GPIO_EXTIPSELH_EXTIPSEL12_MASK 0x70000UL /**< Bit mask for GPIO_EXTIPSEL12 */
<> 128:9bcdf88f62b0 919 #define _GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 920 #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 921 #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 922 #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 923 #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 924 #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 925 #define _GPIO_EXTIPSELH_EXTIPSEL12_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 926 #define GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL12_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 927 #define GPIO_EXTIPSELH_EXTIPSEL12_PORTA (_GPIO_EXTIPSELH_EXTIPSEL12_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 928 #define GPIO_EXTIPSELH_EXTIPSEL12_PORTB (_GPIO_EXTIPSELH_EXTIPSEL12_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 929 #define GPIO_EXTIPSELH_EXTIPSEL12_PORTC (_GPIO_EXTIPSELH_EXTIPSEL12_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 930 #define GPIO_EXTIPSELH_EXTIPSEL12_PORTD (_GPIO_EXTIPSELH_EXTIPSEL12_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 931 #define GPIO_EXTIPSELH_EXTIPSEL12_PORTE (_GPIO_EXTIPSELH_EXTIPSEL12_PORTE << 16) /**< Shifted mode PORTE for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 932 #define GPIO_EXTIPSELH_EXTIPSEL12_PORTF (_GPIO_EXTIPSELH_EXTIPSEL12_PORTF << 16) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 933 #define _GPIO_EXTIPSELH_EXTIPSEL13_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL13 */
<> 128:9bcdf88f62b0 934 #define _GPIO_EXTIPSELH_EXTIPSEL13_MASK 0x700000UL /**< Bit mask for GPIO_EXTIPSEL13 */
<> 128:9bcdf88f62b0 935 #define _GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 936 #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 937 #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 938 #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 939 #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 940 #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 941 #define _GPIO_EXTIPSELH_EXTIPSEL13_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 942 #define GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL13_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 943 #define GPIO_EXTIPSELH_EXTIPSEL13_PORTA (_GPIO_EXTIPSELH_EXTIPSEL13_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 944 #define GPIO_EXTIPSELH_EXTIPSEL13_PORTB (_GPIO_EXTIPSELH_EXTIPSEL13_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 945 #define GPIO_EXTIPSELH_EXTIPSEL13_PORTC (_GPIO_EXTIPSELH_EXTIPSEL13_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 946 #define GPIO_EXTIPSELH_EXTIPSEL13_PORTD (_GPIO_EXTIPSELH_EXTIPSEL13_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 947 #define GPIO_EXTIPSELH_EXTIPSEL13_PORTE (_GPIO_EXTIPSELH_EXTIPSEL13_PORTE << 20) /**< Shifted mode PORTE for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 948 #define GPIO_EXTIPSELH_EXTIPSEL13_PORTF (_GPIO_EXTIPSELH_EXTIPSEL13_PORTF << 20) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 949 #define _GPIO_EXTIPSELH_EXTIPSEL14_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL14 */
<> 128:9bcdf88f62b0 950 #define _GPIO_EXTIPSELH_EXTIPSEL14_MASK 0x7000000UL /**< Bit mask for GPIO_EXTIPSEL14 */
<> 128:9bcdf88f62b0 951 #define _GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 952 #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 953 #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 954 #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 955 #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 956 #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 957 #define _GPIO_EXTIPSELH_EXTIPSEL14_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 958 #define GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL14_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 959 #define GPIO_EXTIPSELH_EXTIPSEL14_PORTA (_GPIO_EXTIPSELH_EXTIPSEL14_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 960 #define GPIO_EXTIPSELH_EXTIPSEL14_PORTB (_GPIO_EXTIPSELH_EXTIPSEL14_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 961 #define GPIO_EXTIPSELH_EXTIPSEL14_PORTC (_GPIO_EXTIPSELH_EXTIPSEL14_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 962 #define GPIO_EXTIPSELH_EXTIPSEL14_PORTD (_GPIO_EXTIPSELH_EXTIPSEL14_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 963 #define GPIO_EXTIPSELH_EXTIPSEL14_PORTE (_GPIO_EXTIPSELH_EXTIPSEL14_PORTE << 24) /**< Shifted mode PORTE for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 964 #define GPIO_EXTIPSELH_EXTIPSEL14_PORTF (_GPIO_EXTIPSELH_EXTIPSEL14_PORTF << 24) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 965 #define _GPIO_EXTIPSELH_EXTIPSEL15_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL15 */
<> 128:9bcdf88f62b0 966 #define _GPIO_EXTIPSELH_EXTIPSEL15_MASK 0x70000000UL /**< Bit mask for GPIO_EXTIPSEL15 */
<> 128:9bcdf88f62b0 967 #define _GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 968 #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 969 #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 970 #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 971 #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 972 #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTE 0x00000004UL /**< Mode PORTE for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 973 #define _GPIO_EXTIPSELH_EXTIPSEL15_PORTF 0x00000005UL /**< Mode PORTF for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 974 #define GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL15_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 975 #define GPIO_EXTIPSELH_EXTIPSEL15_PORTA (_GPIO_EXTIPSELH_EXTIPSEL15_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 976 #define GPIO_EXTIPSELH_EXTIPSEL15_PORTB (_GPIO_EXTIPSELH_EXTIPSEL15_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 977 #define GPIO_EXTIPSELH_EXTIPSEL15_PORTC (_GPIO_EXTIPSELH_EXTIPSEL15_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 978 #define GPIO_EXTIPSELH_EXTIPSEL15_PORTD (_GPIO_EXTIPSELH_EXTIPSEL15_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 979 #define GPIO_EXTIPSELH_EXTIPSEL15_PORTE (_GPIO_EXTIPSELH_EXTIPSEL15_PORTE << 28) /**< Shifted mode PORTE for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 980 #define GPIO_EXTIPSELH_EXTIPSEL15_PORTF (_GPIO_EXTIPSELH_EXTIPSEL15_PORTF << 28) /**< Shifted mode PORTF for GPIO_EXTIPSELH */
<> 128:9bcdf88f62b0 981
<> 128:9bcdf88f62b0 982 /* Bit fields for GPIO EXTIRISE */
<> 128:9bcdf88f62b0 983 #define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */
<> 128:9bcdf88f62b0 984 #define _GPIO_EXTIRISE_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIRISE */
<> 128:9bcdf88f62b0 985 #define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */
<> 128:9bcdf88f62b0 986 #define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIRISE */
<> 128:9bcdf88f62b0 987 #define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */
<> 128:9bcdf88f62b0 988 #define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */
<> 128:9bcdf88f62b0 989
<> 128:9bcdf88f62b0 990 /* Bit fields for GPIO EXTIFALL */
<> 128:9bcdf88f62b0 991 #define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */
<> 128:9bcdf88f62b0 992 #define _GPIO_EXTIFALL_MASK 0x0000FFFFUL /**< Mask for GPIO_EXTIFALL */
<> 128:9bcdf88f62b0 993 #define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */
<> 128:9bcdf88f62b0 994 #define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFFUL /**< Bit mask for GPIO_EXTIFALL */
<> 128:9bcdf88f62b0 995 #define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */
<> 128:9bcdf88f62b0 996 #define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */
<> 128:9bcdf88f62b0 997
<> 128:9bcdf88f62b0 998 /* Bit fields for GPIO IEN */
<> 128:9bcdf88f62b0 999 #define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */
<> 128:9bcdf88f62b0 1000 #define _GPIO_IEN_MASK 0x0000FFFFUL /**< Mask for GPIO_IEN */
<> 128:9bcdf88f62b0 1001 #define _GPIO_IEN_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */
<> 128:9bcdf88f62b0 1002 #define _GPIO_IEN_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */
<> 128:9bcdf88f62b0 1003 #define _GPIO_IEN_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */
<> 128:9bcdf88f62b0 1004 #define GPIO_IEN_EXT_DEFAULT (_GPIO_IEN_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */
<> 128:9bcdf88f62b0 1005
<> 128:9bcdf88f62b0 1006 /* Bit fields for GPIO IF */
<> 128:9bcdf88f62b0 1007 #define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */
<> 128:9bcdf88f62b0 1008 #define _GPIO_IF_MASK 0x0000FFFFUL /**< Mask for GPIO_IF */
<> 128:9bcdf88f62b0 1009 #define _GPIO_IF_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */
<> 128:9bcdf88f62b0 1010 #define _GPIO_IF_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */
<> 128:9bcdf88f62b0 1011 #define _GPIO_IF_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */
<> 128:9bcdf88f62b0 1012 #define GPIO_IF_EXT_DEFAULT (_GPIO_IF_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */
<> 128:9bcdf88f62b0 1013
<> 128:9bcdf88f62b0 1014 /* Bit fields for GPIO IFS */
<> 128:9bcdf88f62b0 1015 #define _GPIO_IFS_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFS */
<> 128:9bcdf88f62b0 1016 #define _GPIO_IFS_MASK 0x0000FFFFUL /**< Mask for GPIO_IFS */
<> 128:9bcdf88f62b0 1017 #define _GPIO_IFS_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */
<> 128:9bcdf88f62b0 1018 #define _GPIO_IFS_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */
<> 128:9bcdf88f62b0 1019 #define _GPIO_IFS_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFS */
<> 128:9bcdf88f62b0 1020 #define GPIO_IFS_EXT_DEFAULT (_GPIO_IFS_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFS */
<> 128:9bcdf88f62b0 1021
<> 128:9bcdf88f62b0 1022 /* Bit fields for GPIO IFC */
<> 128:9bcdf88f62b0 1023 #define _GPIO_IFC_RESETVALUE 0x00000000UL /**< Default value for GPIO_IFC */
<> 128:9bcdf88f62b0 1024 #define _GPIO_IFC_MASK 0x0000FFFFUL /**< Mask for GPIO_IFC */
<> 128:9bcdf88f62b0 1025 #define _GPIO_IFC_EXT_SHIFT 0 /**< Shift value for GPIO_EXT */
<> 128:9bcdf88f62b0 1026 #define _GPIO_IFC_EXT_MASK 0xFFFFUL /**< Bit mask for GPIO_EXT */
<> 128:9bcdf88f62b0 1027 #define _GPIO_IFC_EXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IFC */
<> 128:9bcdf88f62b0 1028 #define GPIO_IFC_EXT_DEFAULT (_GPIO_IFC_EXT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IFC */
<> 128:9bcdf88f62b0 1029
<> 128:9bcdf88f62b0 1030 /* Bit fields for GPIO ROUTE */
<> 128:9bcdf88f62b0 1031 #define _GPIO_ROUTE_RESETVALUE 0x00000003UL /**< Default value for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1032 #define _GPIO_ROUTE_MASK 0x0301F307UL /**< Mask for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1033 #define GPIO_ROUTE_SWCLKPEN (0x1UL << 0) /**< Serial Wire Clock Pin Enable */
<> 128:9bcdf88f62b0 1034 #define _GPIO_ROUTE_SWCLKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKPEN */
<> 128:9bcdf88f62b0 1035 #define _GPIO_ROUTE_SWCLKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKPEN */
<> 128:9bcdf88f62b0 1036 #define _GPIO_ROUTE_SWCLKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1037 #define GPIO_ROUTE_SWCLKPEN_DEFAULT (_GPIO_ROUTE_SWCLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1038 #define GPIO_ROUTE_SWDIOPEN (0x1UL << 1) /**< Serial Wire Data Pin Enable */
<> 128:9bcdf88f62b0 1039 #define _GPIO_ROUTE_SWDIOPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOPEN */
<> 128:9bcdf88f62b0 1040 #define _GPIO_ROUTE_SWDIOPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOPEN */
<> 128:9bcdf88f62b0 1041 #define _GPIO_ROUTE_SWDIOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1042 #define GPIO_ROUTE_SWDIOPEN_DEFAULT (_GPIO_ROUTE_SWDIOPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1043 #define GPIO_ROUTE_SWOPEN (0x1UL << 2) /**< Serial Wire Viewer Output Pin Enable */
<> 128:9bcdf88f62b0 1044 #define _GPIO_ROUTE_SWOPEN_SHIFT 2 /**< Shift value for GPIO_SWOPEN */
<> 128:9bcdf88f62b0 1045 #define _GPIO_ROUTE_SWOPEN_MASK 0x4UL /**< Bit mask for GPIO_SWOPEN */
<> 128:9bcdf88f62b0 1046 #define _GPIO_ROUTE_SWOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1047 #define GPIO_ROUTE_SWOPEN_DEFAULT (_GPIO_ROUTE_SWOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1048 #define _GPIO_ROUTE_SWLOCATION_SHIFT 8 /**< Shift value for GPIO_SWLOCATION */
<> 128:9bcdf88f62b0 1049 #define _GPIO_ROUTE_SWLOCATION_MASK 0x300UL /**< Bit mask for GPIO_SWLOCATION */
<> 128:9bcdf88f62b0 1050 #define _GPIO_ROUTE_SWLOCATION_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1051 #define _GPIO_ROUTE_SWLOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1052 #define _GPIO_ROUTE_SWLOCATION_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1053 #define _GPIO_ROUTE_SWLOCATION_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1054 #define _GPIO_ROUTE_SWLOCATION_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1055 #define GPIO_ROUTE_SWLOCATION_LOC0 (_GPIO_ROUTE_SWLOCATION_LOC0 << 8) /**< Shifted mode LOC0 for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1056 #define GPIO_ROUTE_SWLOCATION_DEFAULT (_GPIO_ROUTE_SWLOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1057 #define GPIO_ROUTE_SWLOCATION_LOC1 (_GPIO_ROUTE_SWLOCATION_LOC1 << 8) /**< Shifted mode LOC1 for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1058 #define GPIO_ROUTE_SWLOCATION_LOC2 (_GPIO_ROUTE_SWLOCATION_LOC2 << 8) /**< Shifted mode LOC2 for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1059 #define GPIO_ROUTE_SWLOCATION_LOC3 (_GPIO_ROUTE_SWLOCATION_LOC3 << 8) /**< Shifted mode LOC3 for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1060 #define GPIO_ROUTE_TCLKPEN (0x1UL << 12) /**< ETM Trace Clock Pin Enable */
<> 128:9bcdf88f62b0 1061 #define _GPIO_ROUTE_TCLKPEN_SHIFT 12 /**< Shift value for GPIO_TCLKPEN */
<> 128:9bcdf88f62b0 1062 #define _GPIO_ROUTE_TCLKPEN_MASK 0x1000UL /**< Bit mask for GPIO_TCLKPEN */
<> 128:9bcdf88f62b0 1063 #define _GPIO_ROUTE_TCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1064 #define GPIO_ROUTE_TCLKPEN_DEFAULT (_GPIO_ROUTE_TCLKPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1065 #define GPIO_ROUTE_TD0PEN (0x1UL << 13) /**< ETM Trace Data Pin Enable */
<> 128:9bcdf88f62b0 1066 #define _GPIO_ROUTE_TD0PEN_SHIFT 13 /**< Shift value for GPIO_TD0PEN */
<> 128:9bcdf88f62b0 1067 #define _GPIO_ROUTE_TD0PEN_MASK 0x2000UL /**< Bit mask for GPIO_TD0PEN */
<> 128:9bcdf88f62b0 1068 #define _GPIO_ROUTE_TD0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1069 #define GPIO_ROUTE_TD0PEN_DEFAULT (_GPIO_ROUTE_TD0PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1070 #define GPIO_ROUTE_TD1PEN (0x1UL << 14) /**< ETM Trace Data Pin Enable */
<> 128:9bcdf88f62b0 1071 #define _GPIO_ROUTE_TD1PEN_SHIFT 14 /**< Shift value for GPIO_TD1PEN */
<> 128:9bcdf88f62b0 1072 #define _GPIO_ROUTE_TD1PEN_MASK 0x4000UL /**< Bit mask for GPIO_TD1PEN */
<> 128:9bcdf88f62b0 1073 #define _GPIO_ROUTE_TD1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1074 #define GPIO_ROUTE_TD1PEN_DEFAULT (_GPIO_ROUTE_TD1PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1075 #define GPIO_ROUTE_TD2PEN (0x1UL << 15) /**< ETM Trace Data Pin Enable */
<> 128:9bcdf88f62b0 1076 #define _GPIO_ROUTE_TD2PEN_SHIFT 15 /**< Shift value for GPIO_TD2PEN */
<> 128:9bcdf88f62b0 1077 #define _GPIO_ROUTE_TD2PEN_MASK 0x8000UL /**< Bit mask for GPIO_TD2PEN */
<> 128:9bcdf88f62b0 1078 #define _GPIO_ROUTE_TD2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1079 #define GPIO_ROUTE_TD2PEN_DEFAULT (_GPIO_ROUTE_TD2PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1080 #define GPIO_ROUTE_TD3PEN (0x1UL << 16) /**< ETM Trace Data Pin Enable */
<> 128:9bcdf88f62b0 1081 #define _GPIO_ROUTE_TD3PEN_SHIFT 16 /**< Shift value for GPIO_TD3PEN */
<> 128:9bcdf88f62b0 1082 #define _GPIO_ROUTE_TD3PEN_MASK 0x10000UL /**< Bit mask for GPIO_TD3PEN */
<> 128:9bcdf88f62b0 1083 #define _GPIO_ROUTE_TD3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1084 #define GPIO_ROUTE_TD3PEN_DEFAULT (_GPIO_ROUTE_TD3PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1085 #define _GPIO_ROUTE_ETMLOCATION_SHIFT 24 /**< Shift value for GPIO_ETMLOCATION */
<> 128:9bcdf88f62b0 1086 #define _GPIO_ROUTE_ETMLOCATION_MASK 0x3000000UL /**< Bit mask for GPIO_ETMLOCATION */
<> 128:9bcdf88f62b0 1087 #define _GPIO_ROUTE_ETMLOCATION_LOC0 0x00000000UL /**< Mode LOC0 for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1088 #define _GPIO_ROUTE_ETMLOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1089 #define _GPIO_ROUTE_ETMLOCATION_LOC1 0x00000001UL /**< Mode LOC1 for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1090 #define _GPIO_ROUTE_ETMLOCATION_LOC2 0x00000002UL /**< Mode LOC2 for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1091 #define _GPIO_ROUTE_ETMLOCATION_LOC3 0x00000003UL /**< Mode LOC3 for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1092 #define GPIO_ROUTE_ETMLOCATION_LOC0 (_GPIO_ROUTE_ETMLOCATION_LOC0 << 24) /**< Shifted mode LOC0 for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1093 #define GPIO_ROUTE_ETMLOCATION_DEFAULT (_GPIO_ROUTE_ETMLOCATION_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1094 #define GPIO_ROUTE_ETMLOCATION_LOC1 (_GPIO_ROUTE_ETMLOCATION_LOC1 << 24) /**< Shifted mode LOC1 for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1095 #define GPIO_ROUTE_ETMLOCATION_LOC2 (_GPIO_ROUTE_ETMLOCATION_LOC2 << 24) /**< Shifted mode LOC2 for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1096 #define GPIO_ROUTE_ETMLOCATION_LOC3 (_GPIO_ROUTE_ETMLOCATION_LOC3 << 24) /**< Shifted mode LOC3 for GPIO_ROUTE */
<> 128:9bcdf88f62b0 1097
<> 128:9bcdf88f62b0 1098 /* Bit fields for GPIO INSENSE */
<> 128:9bcdf88f62b0 1099 #define _GPIO_INSENSE_RESETVALUE 0x00000003UL /**< Default value for GPIO_INSENSE */
<> 128:9bcdf88f62b0 1100 #define _GPIO_INSENSE_MASK 0x00000003UL /**< Mask for GPIO_INSENSE */
<> 128:9bcdf88f62b0 1101 #define GPIO_INSENSE_INT (0x1UL << 0) /**< Interrupt Sense Enable */
<> 128:9bcdf88f62b0 1102 #define _GPIO_INSENSE_INT_SHIFT 0 /**< Shift value for GPIO_INT */
<> 128:9bcdf88f62b0 1103 #define _GPIO_INSENSE_INT_MASK 0x1UL /**< Bit mask for GPIO_INT */
<> 128:9bcdf88f62b0 1104 #define _GPIO_INSENSE_INT_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */
<> 128:9bcdf88f62b0 1105 #define GPIO_INSENSE_INT_DEFAULT (_GPIO_INSENSE_INT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_INSENSE */
<> 128:9bcdf88f62b0 1106 #define GPIO_INSENSE_PRS (0x1UL << 1) /**< PRS Sense Enable */
<> 128:9bcdf88f62b0 1107 #define _GPIO_INSENSE_PRS_SHIFT 1 /**< Shift value for GPIO_PRS */
<> 128:9bcdf88f62b0 1108 #define _GPIO_INSENSE_PRS_MASK 0x2UL /**< Bit mask for GPIO_PRS */
<> 128:9bcdf88f62b0 1109 #define _GPIO_INSENSE_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_INSENSE */
<> 128:9bcdf88f62b0 1110 #define GPIO_INSENSE_PRS_DEFAULT (_GPIO_INSENSE_PRS_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_INSENSE */
<> 128:9bcdf88f62b0 1111
<> 128:9bcdf88f62b0 1112 /* Bit fields for GPIO LOCK */
<> 128:9bcdf88f62b0 1113 #define _GPIO_LOCK_RESETVALUE 0x00000000UL /**< Default value for GPIO_LOCK */
<> 128:9bcdf88f62b0 1114 #define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */
<> 128:9bcdf88f62b0 1115 #define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */
<> 128:9bcdf88f62b0 1116 #define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */
<> 128:9bcdf88f62b0 1117 #define _GPIO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LOCK */
<> 128:9bcdf88f62b0 1118 #define _GPIO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for GPIO_LOCK */
<> 128:9bcdf88f62b0 1119 #define _GPIO_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_LOCK */
<> 128:9bcdf88f62b0 1120 #define _GPIO_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_LOCK */
<> 128:9bcdf88f62b0 1121 #define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */
<> 128:9bcdf88f62b0 1122 #define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */
<> 128:9bcdf88f62b0 1123 #define GPIO_LOCK_LOCKKEY_LOCK (_GPIO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for GPIO_LOCK */
<> 128:9bcdf88f62b0 1124 #define GPIO_LOCK_LOCKKEY_UNLOCKED (_GPIO_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_LOCK */
<> 128:9bcdf88f62b0 1125 #define GPIO_LOCK_LOCKKEY_LOCKED (_GPIO_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_LOCK */
<> 128:9bcdf88f62b0 1126 #define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */
<> 128:9bcdf88f62b0 1127
<> 128:9bcdf88f62b0 1128 /* Bit fields for GPIO CTRL */
<> 128:9bcdf88f62b0 1129 #define _GPIO_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPIO_CTRL */
<> 128:9bcdf88f62b0 1130 #define _GPIO_CTRL_MASK 0x00000001UL /**< Mask for GPIO_CTRL */
<> 128:9bcdf88f62b0 1131 #define GPIO_CTRL_EM4RET (0x1UL << 0) /**< Enable EM4 retention */
<> 128:9bcdf88f62b0 1132 #define _GPIO_CTRL_EM4RET_SHIFT 0 /**< Shift value for GPIO_EM4RET */
<> 128:9bcdf88f62b0 1133 #define _GPIO_CTRL_EM4RET_MASK 0x1UL /**< Bit mask for GPIO_EM4RET */
<> 128:9bcdf88f62b0 1134 #define _GPIO_CTRL_EM4RET_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CTRL */
<> 128:9bcdf88f62b0 1135 #define GPIO_CTRL_EM4RET_DEFAULT (_GPIO_CTRL_EM4RET_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CTRL */
<> 128:9bcdf88f62b0 1136
<> 128:9bcdf88f62b0 1137 /* Bit fields for GPIO CMD */
<> 128:9bcdf88f62b0 1138 #define _GPIO_CMD_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMD */
<> 128:9bcdf88f62b0 1139 #define _GPIO_CMD_MASK 0x00000001UL /**< Mask for GPIO_CMD */
<> 128:9bcdf88f62b0 1140 #define GPIO_CMD_EM4WUCLR (0x1UL << 0) /**< EM4 Wake-up clear */
<> 128:9bcdf88f62b0 1141 #define _GPIO_CMD_EM4WUCLR_SHIFT 0 /**< Shift value for GPIO_EM4WUCLR */
<> 128:9bcdf88f62b0 1142 #define _GPIO_CMD_EM4WUCLR_MASK 0x1UL /**< Bit mask for GPIO_EM4WUCLR */
<> 128:9bcdf88f62b0 1143 #define _GPIO_CMD_EM4WUCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMD */
<> 128:9bcdf88f62b0 1144 #define GPIO_CMD_EM4WUCLR_DEFAULT (_GPIO_CMD_EM4WUCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMD */
<> 128:9bcdf88f62b0 1145
<> 128:9bcdf88f62b0 1146 /* Bit fields for GPIO EM4WUEN */
<> 128:9bcdf88f62b0 1147 #define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */
<> 128:9bcdf88f62b0 1148 #define _GPIO_EM4WUEN_MASK 0x0000003FUL /**< Mask for GPIO_EM4WUEN */
<> 128:9bcdf88f62b0 1149 #define _GPIO_EM4WUEN_EM4WUEN_SHIFT 0 /**< Shift value for GPIO_EM4WUEN */
<> 128:9bcdf88f62b0 1150 #define _GPIO_EM4WUEN_EM4WUEN_MASK 0x3FUL /**< Bit mask for GPIO_EM4WUEN */
<> 128:9bcdf88f62b0 1151 #define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */
<> 128:9bcdf88f62b0 1152 #define _GPIO_EM4WUEN_EM4WUEN_A0 0x00000001UL /**< Mode A0 for GPIO_EM4WUEN */
<> 128:9bcdf88f62b0 1153 #define _GPIO_EM4WUEN_EM4WUEN_A6 0x00000002UL /**< Mode A6 for GPIO_EM4WUEN */
<> 128:9bcdf88f62b0 1154 #define _GPIO_EM4WUEN_EM4WUEN_C9 0x00000004UL /**< Mode C9 for GPIO_EM4WUEN */
<> 128:9bcdf88f62b0 1155 #define _GPIO_EM4WUEN_EM4WUEN_F1 0x00000008UL /**< Mode F1 for GPIO_EM4WUEN */
<> 128:9bcdf88f62b0 1156 #define _GPIO_EM4WUEN_EM4WUEN_F2 0x00000010UL /**< Mode F2 for GPIO_EM4WUEN */
<> 128:9bcdf88f62b0 1157 #define _GPIO_EM4WUEN_EM4WUEN_E13 0x00000020UL /**< Mode E13 for GPIO_EM4WUEN */
<> 128:9bcdf88f62b0 1158 #define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */
<> 128:9bcdf88f62b0 1159 #define GPIO_EM4WUEN_EM4WUEN_A0 (_GPIO_EM4WUEN_EM4WUEN_A0 << 0) /**< Shifted mode A0 for GPIO_EM4WUEN */
<> 128:9bcdf88f62b0 1160 #define GPIO_EM4WUEN_EM4WUEN_A6 (_GPIO_EM4WUEN_EM4WUEN_A6 << 0) /**< Shifted mode A6 for GPIO_EM4WUEN */
<> 128:9bcdf88f62b0 1161 #define GPIO_EM4WUEN_EM4WUEN_C9 (_GPIO_EM4WUEN_EM4WUEN_C9 << 0) /**< Shifted mode C9 for GPIO_EM4WUEN */
<> 128:9bcdf88f62b0 1162 #define GPIO_EM4WUEN_EM4WUEN_F1 (_GPIO_EM4WUEN_EM4WUEN_F1 << 0) /**< Shifted mode F1 for GPIO_EM4WUEN */
<> 128:9bcdf88f62b0 1163 #define GPIO_EM4WUEN_EM4WUEN_F2 (_GPIO_EM4WUEN_EM4WUEN_F2 << 0) /**< Shifted mode F2 for GPIO_EM4WUEN */
<> 128:9bcdf88f62b0 1164 #define GPIO_EM4WUEN_EM4WUEN_E13 (_GPIO_EM4WUEN_EM4WUEN_E13 << 0) /**< Shifted mode E13 for GPIO_EM4WUEN */
<> 128:9bcdf88f62b0 1165
<> 128:9bcdf88f62b0 1166 /* Bit fields for GPIO EM4WUPOL */
<> 128:9bcdf88f62b0 1167 #define _GPIO_EM4WUPOL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUPOL */
<> 128:9bcdf88f62b0 1168 #define _GPIO_EM4WUPOL_MASK 0x0000003FUL /**< Mask for GPIO_EM4WUPOL */
<> 128:9bcdf88f62b0 1169 #define _GPIO_EM4WUPOL_EM4WUPOL_SHIFT 0 /**< Shift value for GPIO_EM4WUPOL */
<> 128:9bcdf88f62b0 1170 #define _GPIO_EM4WUPOL_EM4WUPOL_MASK 0x3FUL /**< Bit mask for GPIO_EM4WUPOL */
<> 128:9bcdf88f62b0 1171 #define _GPIO_EM4WUPOL_EM4WUPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUPOL */
<> 128:9bcdf88f62b0 1172 #define _GPIO_EM4WUPOL_EM4WUPOL_A0 0x00000001UL /**< Mode A0 for GPIO_EM4WUPOL */
<> 128:9bcdf88f62b0 1173 #define _GPIO_EM4WUPOL_EM4WUPOL_A6 0x00000002UL /**< Mode A6 for GPIO_EM4WUPOL */
<> 128:9bcdf88f62b0 1174 #define _GPIO_EM4WUPOL_EM4WUPOL_C9 0x00000004UL /**< Mode C9 for GPIO_EM4WUPOL */
<> 128:9bcdf88f62b0 1175 #define _GPIO_EM4WUPOL_EM4WUPOL_F1 0x00000008UL /**< Mode F1 for GPIO_EM4WUPOL */
<> 128:9bcdf88f62b0 1176 #define _GPIO_EM4WUPOL_EM4WUPOL_F2 0x00000010UL /**< Mode F2 for GPIO_EM4WUPOL */
<> 128:9bcdf88f62b0 1177 #define _GPIO_EM4WUPOL_EM4WUPOL_E13 0x00000020UL /**< Mode E13 for GPIO_EM4WUPOL */
<> 128:9bcdf88f62b0 1178 #define GPIO_EM4WUPOL_EM4WUPOL_DEFAULT (_GPIO_EM4WUPOL_EM4WUPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EM4WUPOL */
<> 128:9bcdf88f62b0 1179 #define GPIO_EM4WUPOL_EM4WUPOL_A0 (_GPIO_EM4WUPOL_EM4WUPOL_A0 << 0) /**< Shifted mode A0 for GPIO_EM4WUPOL */
<> 128:9bcdf88f62b0 1180 #define GPIO_EM4WUPOL_EM4WUPOL_A6 (_GPIO_EM4WUPOL_EM4WUPOL_A6 << 0) /**< Shifted mode A6 for GPIO_EM4WUPOL */
<> 128:9bcdf88f62b0 1181 #define GPIO_EM4WUPOL_EM4WUPOL_C9 (_GPIO_EM4WUPOL_EM4WUPOL_C9 << 0) /**< Shifted mode C9 for GPIO_EM4WUPOL */
<> 128:9bcdf88f62b0 1182 #define GPIO_EM4WUPOL_EM4WUPOL_F1 (_GPIO_EM4WUPOL_EM4WUPOL_F1 << 0) /**< Shifted mode F1 for GPIO_EM4WUPOL */
<> 128:9bcdf88f62b0 1183 #define GPIO_EM4WUPOL_EM4WUPOL_F2 (_GPIO_EM4WUPOL_EM4WUPOL_F2 << 0) /**< Shifted mode F2 for GPIO_EM4WUPOL */
<> 128:9bcdf88f62b0 1184 #define GPIO_EM4WUPOL_EM4WUPOL_E13 (_GPIO_EM4WUPOL_EM4WUPOL_E13 << 0) /**< Shifted mode E13 for GPIO_EM4WUPOL */
<> 128:9bcdf88f62b0 1185
<> 128:9bcdf88f62b0 1186 /* Bit fields for GPIO EM4WUCAUSE */
<> 128:9bcdf88f62b0 1187 #define _GPIO_EM4WUCAUSE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUCAUSE */
<> 128:9bcdf88f62b0 1188 #define _GPIO_EM4WUCAUSE_MASK 0x0000003FUL /**< Mask for GPIO_EM4WUCAUSE */
<> 128:9bcdf88f62b0 1189 #define _GPIO_EM4WUCAUSE_EM4WUCAUSE_SHIFT 0 /**< Shift value for GPIO_EM4WUCAUSE */
<> 128:9bcdf88f62b0 1190 #define _GPIO_EM4WUCAUSE_EM4WUCAUSE_MASK 0x3FUL /**< Bit mask for GPIO_EM4WUCAUSE */
<> 128:9bcdf88f62b0 1191 #define _GPIO_EM4WUCAUSE_EM4WUCAUSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUCAUSE */
<> 128:9bcdf88f62b0 1192 #define _GPIO_EM4WUCAUSE_EM4WUCAUSE_A0 0x00000001UL /**< Mode A0 for GPIO_EM4WUCAUSE */
<> 128:9bcdf88f62b0 1193 #define _GPIO_EM4WUCAUSE_EM4WUCAUSE_A6 0x00000002UL /**< Mode A6 for GPIO_EM4WUCAUSE */
<> 128:9bcdf88f62b0 1194 #define _GPIO_EM4WUCAUSE_EM4WUCAUSE_C9 0x00000004UL /**< Mode C9 for GPIO_EM4WUCAUSE */
<> 128:9bcdf88f62b0 1195 #define _GPIO_EM4WUCAUSE_EM4WUCAUSE_F1 0x00000008UL /**< Mode F1 for GPIO_EM4WUCAUSE */
<> 128:9bcdf88f62b0 1196 #define _GPIO_EM4WUCAUSE_EM4WUCAUSE_F2 0x00000010UL /**< Mode F2 for GPIO_EM4WUCAUSE */
<> 128:9bcdf88f62b0 1197 #define _GPIO_EM4WUCAUSE_EM4WUCAUSE_E13 0x00000020UL /**< Mode E13 for GPIO_EM4WUCAUSE */
<> 128:9bcdf88f62b0 1198 #define GPIO_EM4WUCAUSE_EM4WUCAUSE_DEFAULT (_GPIO_EM4WUCAUSE_EM4WUCAUSE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EM4WUCAUSE */
<> 128:9bcdf88f62b0 1199 #define GPIO_EM4WUCAUSE_EM4WUCAUSE_A0 (_GPIO_EM4WUCAUSE_EM4WUCAUSE_A0 << 0) /**< Shifted mode A0 for GPIO_EM4WUCAUSE */
<> 128:9bcdf88f62b0 1200 #define GPIO_EM4WUCAUSE_EM4WUCAUSE_A6 (_GPIO_EM4WUCAUSE_EM4WUCAUSE_A6 << 0) /**< Shifted mode A6 for GPIO_EM4WUCAUSE */
<> 128:9bcdf88f62b0 1201 #define GPIO_EM4WUCAUSE_EM4WUCAUSE_C9 (_GPIO_EM4WUCAUSE_EM4WUCAUSE_C9 << 0) /**< Shifted mode C9 for GPIO_EM4WUCAUSE */
<> 128:9bcdf88f62b0 1202 #define GPIO_EM4WUCAUSE_EM4WUCAUSE_F1 (_GPIO_EM4WUCAUSE_EM4WUCAUSE_F1 << 0) /**< Shifted mode F1 for GPIO_EM4WUCAUSE */
<> 128:9bcdf88f62b0 1203 #define GPIO_EM4WUCAUSE_EM4WUCAUSE_F2 (_GPIO_EM4WUCAUSE_EM4WUCAUSE_F2 << 0) /**< Shifted mode F2 for GPIO_EM4WUCAUSE */
<> 128:9bcdf88f62b0 1204 #define GPIO_EM4WUCAUSE_EM4WUCAUSE_E13 (_GPIO_EM4WUCAUSE_EM4WUCAUSE_E13 << 0) /**< Shifted mode E13 for GPIO_EM4WUCAUSE */
<> 128:9bcdf88f62b0 1205
<> 128:9bcdf88f62b0 1206 /** @} End of group EFM32LG_GPIO */
<> 128:9bcdf88f62b0 1207 /** @} End of group Parts */
<> 128:9bcdf88f62b0 1208