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mbed 2
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TARGET_EFM32LG_STK3600/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_dmareq.h@128:9bcdf88f62b0, 2016-10-27 (annotated)
- Committer:
- <>
- Date:
- Thu Oct 27 16:45:56 2016 +0100
- Revision:
- 128:9bcdf88f62b0
- Child:
- 139:856d2700e60b
Release 128 of the mbed library
Ports for Upcoming Targets
Fixes and Changes
2966: Add kw24 support https://github.com/ARMmbed/mbed-os/pull/2966
3068: MultiTech mDot - clean up PeripheralPins.c and add new pin names https://github.com/ARMmbed/mbed-os/pull/3068
3089: Kinetis HAL: Remove clock initialization code from serial and ticker https://github.com/ARMmbed/mbed-os/pull/3089
2943: [NRF5] NVIC_SetVector functionality https://github.com/ARMmbed/mbed-os/pull/2943
2938: InterruptIn changes in NCS36510 HAL. https://github.com/ARMmbed/mbed-os/pull/2938
3108: Fix sleep function for NRF52. https://github.com/ARMmbed/mbed-os/pull/3108
3076: STM32F1: Correct timer master value reading https://github.com/ARMmbed/mbed-os/pull/3076
3085: Add LOWPOWERTIMER capability for NUCLEO_F303ZE https://github.com/ARMmbed/mbed-os/pull/3085
3046: [BEETLE] Update BLE stack on Beetle board https://github.com/ARMmbed/mbed-os/pull/3046
3122: [Silicon Labs] Update of Silicon Labs HAL https://github.com/ARMmbed/mbed-os/pull/3122
3022: OnSemi RAM usage fix https://github.com/ARMmbed/mbed-os/pull/3022
3121: STM32F3: Correct UART4 and UART5 defines when using DEVICE_SERIAL_ASYNCH https://github.com/ARMmbed/mbed-os/pull/3121
3142: Targets- NUMAKER_PFM_NUC47216 remove mbed 2 https://github.com/ARMmbed/mbed-os/pull/3142
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 128:9bcdf88f62b0 | 1 | /**************************************************************************//** |
<> | 128:9bcdf88f62b0 | 2 | * @file efm32lg_dmareq.h |
<> | 128:9bcdf88f62b0 | 3 | * @brief EFM32LG_DMAREQ register and bit field definitions |
<> | 128:9bcdf88f62b0 | 4 | * @version 5.0.0 |
<> | 128:9bcdf88f62b0 | 5 | ****************************************************************************** |
<> | 128:9bcdf88f62b0 | 6 | * @section License |
<> | 128:9bcdf88f62b0 | 7 | * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b> |
<> | 128:9bcdf88f62b0 | 8 | ****************************************************************************** |
<> | 128:9bcdf88f62b0 | 9 | * |
<> | 128:9bcdf88f62b0 | 10 | * Permission is granted to anyone to use this software for any purpose, |
<> | 128:9bcdf88f62b0 | 11 | * including commercial applications, and to alter it and redistribute it |
<> | 128:9bcdf88f62b0 | 12 | * freely, subject to the following restrictions: |
<> | 128:9bcdf88f62b0 | 13 | * |
<> | 128:9bcdf88f62b0 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
<> | 128:9bcdf88f62b0 | 15 | * claim that you wrote the original software.@n |
<> | 128:9bcdf88f62b0 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
<> | 128:9bcdf88f62b0 | 17 | * misrepresented as being the original software.@n |
<> | 128:9bcdf88f62b0 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
<> | 128:9bcdf88f62b0 | 19 | * |
<> | 128:9bcdf88f62b0 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
<> | 128:9bcdf88f62b0 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
<> | 128:9bcdf88f62b0 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
<> | 128:9bcdf88f62b0 | 23 | * kind, including, but not limited to, any implied warranties of |
<> | 128:9bcdf88f62b0 | 24 | * merchantability or fitness for any particular purpose or warranties against |
<> | 128:9bcdf88f62b0 | 25 | * infringement of any proprietary rights of a third party. |
<> | 128:9bcdf88f62b0 | 26 | * |
<> | 128:9bcdf88f62b0 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
<> | 128:9bcdf88f62b0 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
<> | 128:9bcdf88f62b0 | 29 | * any third party, arising from your use of this Software. |
<> | 128:9bcdf88f62b0 | 30 | * |
<> | 128:9bcdf88f62b0 | 31 | *****************************************************************************/ |
<> | 128:9bcdf88f62b0 | 32 | /**************************************************************************//** |
<> | 128:9bcdf88f62b0 | 33 | * @addtogroup Parts |
<> | 128:9bcdf88f62b0 | 34 | * @{ |
<> | 128:9bcdf88f62b0 | 35 | ******************************************************************************/ |
<> | 128:9bcdf88f62b0 | 36 | |
<> | 128:9bcdf88f62b0 | 37 | /**************************************************************************//** |
<> | 128:9bcdf88f62b0 | 38 | * @defgroup EFM32LG_DMAREQ_BitFields |
<> | 128:9bcdf88f62b0 | 39 | * @{ |
<> | 128:9bcdf88f62b0 | 40 | *****************************************************************************/ |
<> | 128:9bcdf88f62b0 | 41 | #define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */ |
<> | 128:9bcdf88f62b0 | 42 | #define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */ |
<> | 128:9bcdf88f62b0 | 43 | #define DMAREQ_DAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for DAC0_CH0 */ |
<> | 128:9bcdf88f62b0 | 44 | #define DMAREQ_DAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for DAC0_CH1 */ |
<> | 128:9bcdf88f62b0 | 45 | #define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */ |
<> | 128:9bcdf88f62b0 | 46 | #define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */ |
<> | 128:9bcdf88f62b0 | 47 | #define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */ |
<> | 128:9bcdf88f62b0 | 48 | #define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */ |
<> | 128:9bcdf88f62b0 | 49 | #define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */ |
<> | 128:9bcdf88f62b0 | 50 | #define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */ |
<> | 128:9bcdf88f62b0 | 51 | #define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */ |
<> | 128:9bcdf88f62b0 | 52 | #define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */ |
<> | 128:9bcdf88f62b0 | 53 | #define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */ |
<> | 128:9bcdf88f62b0 | 54 | #define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */ |
<> | 128:9bcdf88f62b0 | 55 | #define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */ |
<> | 128:9bcdf88f62b0 | 56 | #define DMAREQ_USART2_RXDATAVRIGHT ((14 << 16) + 3) /**< DMA channel select for USART2_RXDATAVRIGHT */ |
<> | 128:9bcdf88f62b0 | 57 | #define DMAREQ_USART2_TXBLRIGHT ((14 << 16) + 4) /**< DMA channel select for USART2_TXBLRIGHT */ |
<> | 128:9bcdf88f62b0 | 58 | #define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */ |
<> | 128:9bcdf88f62b0 | 59 | #define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */ |
<> | 128:9bcdf88f62b0 | 60 | #define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */ |
<> | 128:9bcdf88f62b0 | 61 | #define DMAREQ_LEUART1_RXDATAV ((17 << 16) + 0) /**< DMA channel select for LEUART1_RXDATAV */ |
<> | 128:9bcdf88f62b0 | 62 | #define DMAREQ_LEUART1_TXBL ((17 << 16) + 1) /**< DMA channel select for LEUART1_TXBL */ |
<> | 128:9bcdf88f62b0 | 63 | #define DMAREQ_LEUART1_TXEMPTY ((17 << 16) + 2) /**< DMA channel select for LEUART1_TXEMPTY */ |
<> | 128:9bcdf88f62b0 | 64 | #define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */ |
<> | 128:9bcdf88f62b0 | 65 | #define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */ |
<> | 128:9bcdf88f62b0 | 66 | #define DMAREQ_I2C1_RXDATAV ((21 << 16) + 0) /**< DMA channel select for I2C1_RXDATAV */ |
<> | 128:9bcdf88f62b0 | 67 | #define DMAREQ_I2C1_TXBL ((21 << 16) + 1) /**< DMA channel select for I2C1_TXBL */ |
<> | 128:9bcdf88f62b0 | 68 | #define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */ |
<> | 128:9bcdf88f62b0 | 69 | #define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */ |
<> | 128:9bcdf88f62b0 | 70 | #define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */ |
<> | 128:9bcdf88f62b0 | 71 | #define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */ |
<> | 128:9bcdf88f62b0 | 72 | #define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */ |
<> | 128:9bcdf88f62b0 | 73 | #define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */ |
<> | 128:9bcdf88f62b0 | 74 | #define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */ |
<> | 128:9bcdf88f62b0 | 75 | #define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */ |
<> | 128:9bcdf88f62b0 | 76 | #define DMAREQ_TIMER2_UFOF ((26 << 16) + 0) /**< DMA channel select for TIMER2_UFOF */ |
<> | 128:9bcdf88f62b0 | 77 | #define DMAREQ_TIMER2_CC0 ((26 << 16) + 1) /**< DMA channel select for TIMER2_CC0 */ |
<> | 128:9bcdf88f62b0 | 78 | #define DMAREQ_TIMER2_CC1 ((26 << 16) + 2) /**< DMA channel select for TIMER2_CC1 */ |
<> | 128:9bcdf88f62b0 | 79 | #define DMAREQ_TIMER2_CC2 ((26 << 16) + 3) /**< DMA channel select for TIMER2_CC2 */ |
<> | 128:9bcdf88f62b0 | 80 | #define DMAREQ_TIMER3_UFOF ((27 << 16) + 0) /**< DMA channel select for TIMER3_UFOF */ |
<> | 128:9bcdf88f62b0 | 81 | #define DMAREQ_TIMER3_CC0 ((27 << 16) + 1) /**< DMA channel select for TIMER3_CC0 */ |
<> | 128:9bcdf88f62b0 | 82 | #define DMAREQ_TIMER3_CC1 ((27 << 16) + 2) /**< DMA channel select for TIMER3_CC1 */ |
<> | 128:9bcdf88f62b0 | 83 | #define DMAREQ_TIMER3_CC2 ((27 << 16) + 3) /**< DMA channel select for TIMER3_CC2 */ |
<> | 128:9bcdf88f62b0 | 84 | #define DMAREQ_UART0_RXDATAV ((44 << 16) + 0) /**< DMA channel select for UART0_RXDATAV */ |
<> | 128:9bcdf88f62b0 | 85 | #define DMAREQ_UART0_TXBL ((44 << 16) + 1) /**< DMA channel select for UART0_TXBL */ |
<> | 128:9bcdf88f62b0 | 86 | #define DMAREQ_UART0_TXEMPTY ((44 << 16) + 2) /**< DMA channel select for UART0_TXEMPTY */ |
<> | 128:9bcdf88f62b0 | 87 | #define DMAREQ_UART1_RXDATAV ((45 << 16) + 0) /**< DMA channel select for UART1_RXDATAV */ |
<> | 128:9bcdf88f62b0 | 88 | #define DMAREQ_UART1_TXBL ((45 << 16) + 1) /**< DMA channel select for UART1_TXBL */ |
<> | 128:9bcdf88f62b0 | 89 | #define DMAREQ_UART1_TXEMPTY ((45 << 16) + 2) /**< DMA channel select for UART1_TXEMPTY */ |
<> | 128:9bcdf88f62b0 | 90 | #define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */ |
<> | 128:9bcdf88f62b0 | 91 | #define DMAREQ_AES_DATAWR ((49 << 16) + 0) /**< DMA channel select for AES_DATAWR */ |
<> | 128:9bcdf88f62b0 | 92 | #define DMAREQ_AES_XORDATAWR ((49 << 16) + 1) /**< DMA channel select for AES_XORDATAWR */ |
<> | 128:9bcdf88f62b0 | 93 | #define DMAREQ_AES_DATARD ((49 << 16) + 2) /**< DMA channel select for AES_DATARD */ |
<> | 128:9bcdf88f62b0 | 94 | #define DMAREQ_AES_KEYWR ((49 << 16) + 3) /**< DMA channel select for AES_KEYWR */ |
<> | 128:9bcdf88f62b0 | 95 | #define DMAREQ_LESENSE_BUFDATAV ((50 << 16) + 0) /**< DMA channel select for LESENSE_BUFDATAV */ |
<> | 128:9bcdf88f62b0 | 96 | #define DMAREQ_EBI_PXL0EMPTY ((51 << 16) + 0) /**< DMA channel select for EBI_PXL0EMPTY */ |
<> | 128:9bcdf88f62b0 | 97 | #define DMAREQ_EBI_PXL1EMPTY ((51 << 16) + 1) /**< DMA channel select for EBI_PXL1EMPTY */ |
<> | 128:9bcdf88f62b0 | 98 | #define DMAREQ_EBI_PXLFULL ((51 << 16) + 2) /**< DMA channel select for EBI_PXLFULL */ |
<> | 128:9bcdf88f62b0 | 99 | #define DMAREQ_EBI_DDEMPTY ((51 << 16) + 3) /**< DMA channel select for EBI_DDEMPTY */ |
<> | 128:9bcdf88f62b0 | 100 | |
<> | 128:9bcdf88f62b0 | 101 | /** @} End of group EFM32LG_DMAREQ */ |
<> | 128:9bcdf88f62b0 | 102 | /** @} End of group Parts */ |
<> | 128:9bcdf88f62b0 | 103 |