mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32LG_STK3600/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_devinfo.h@128:9bcdf88f62b0, 2016-10-27 (annotated)

Committer:
<>
Date:
Thu Oct 27 16:45:56 2016 +0100
Revision:
128:9bcdf88f62b0
Child:
139:856d2700e60b
Release 128 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



2966: Add kw24 support https://github.com/ARMmbed/mbed-os/pull/2966

3068: MultiTech mDot - clean up PeripheralPins.c and add new pin names https://github.com/ARMmbed/mbed-os/pull/3068

3089: Kinetis HAL: Remove clock initialization code from serial and ticker  https://github.com/ARMmbed/mbed-os/pull/3089

2943: [NRF5] NVIC_SetVector functionality https://github.com/ARMmbed/mbed-os/pull/2943

2938: InterruptIn changes in NCS36510 HAL. https://github.com/ARMmbed/mbed-os/pull/2938

3108: Fix sleep function for NRF52. https://github.com/ARMmbed/mbed-os/pull/3108

3076: STM32F1: Correct timer master value reading https://github.com/ARMmbed/mbed-os/pull/3076

3085: Add LOWPOWERTIMER capability for NUCLEO_F303ZE https://github.com/ARMmbed/mbed-os/pull/3085

3046: [BEETLE] Update BLE stack on Beetle board https://github.com/ARMmbed/mbed-os/pull/3046

3122: [Silicon Labs] Update of Silicon Labs HAL https://github.com/ARMmbed/mbed-os/pull/3122

3022: OnSemi RAM usage fix https://github.com/ARMmbed/mbed-os/pull/3022

3121: STM32F3: Correct UART4 and UART5 defines when using DEVICE_SERIAL_ASYNCH https://github.com/ARMmbed/mbed-os/pull/3121

3142: Targets- NUMAKER_PFM_NUC47216 remove mbed 2 https://github.com/ARMmbed/mbed-os/pull/3142

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**************************************************************************//**
<> 128:9bcdf88f62b0 2 * @file efm32lg_devinfo.h
<> 128:9bcdf88f62b0 3 * @brief EFM32LG_DEVINFO register and bit field definitions
<> 128:9bcdf88f62b0 4 * @version 5.0.0
<> 128:9bcdf88f62b0 5 ******************************************************************************
<> 128:9bcdf88f62b0 6 * @section License
<> 128:9bcdf88f62b0 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 *
<> 128:9bcdf88f62b0 10 * Permission is granted to anyone to use this software for any purpose,
<> 128:9bcdf88f62b0 11 * including commercial applications, and to alter it and redistribute it
<> 128:9bcdf88f62b0 12 * freely, subject to the following restrictions:
<> 128:9bcdf88f62b0 13 *
<> 128:9bcdf88f62b0 14 * 1. The origin of this software must not be misrepresented; you must not
<> 128:9bcdf88f62b0 15 * claim that you wrote the original software.@n
<> 128:9bcdf88f62b0 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 128:9bcdf88f62b0 17 * misrepresented as being the original software.@n
<> 128:9bcdf88f62b0 18 * 3. This notice may not be removed or altered from any source distribution.
<> 128:9bcdf88f62b0 19 *
<> 128:9bcdf88f62b0 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 128:9bcdf88f62b0 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 128:9bcdf88f62b0 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 128:9bcdf88f62b0 23 * kind, including, but not limited to, any implied warranties of
<> 128:9bcdf88f62b0 24 * merchantability or fitness for any particular purpose or warranties against
<> 128:9bcdf88f62b0 25 * infringement of any proprietary rights of a third party.
<> 128:9bcdf88f62b0 26 *
<> 128:9bcdf88f62b0 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 128:9bcdf88f62b0 28 * incidental, or special damages, or any other relief, or for any claim by
<> 128:9bcdf88f62b0 29 * any third party, arising from your use of this Software.
<> 128:9bcdf88f62b0 30 *
<> 128:9bcdf88f62b0 31 *****************************************************************************/
<> 128:9bcdf88f62b0 32 /**************************************************************************//**
<> 128:9bcdf88f62b0 33 * @addtogroup Parts
<> 128:9bcdf88f62b0 34 * @{
<> 128:9bcdf88f62b0 35 ******************************************************************************/
<> 128:9bcdf88f62b0 36 /**************************************************************************//**
<> 128:9bcdf88f62b0 37 * @defgroup EFM32LG_DEVINFO
<> 128:9bcdf88f62b0 38 * @{
<> 128:9bcdf88f62b0 39 *****************************************************************************/
<> 128:9bcdf88f62b0 40 typedef struct
<> 128:9bcdf88f62b0 41 {
<> 128:9bcdf88f62b0 42 __IM uint32_t CAL; /**< Calibration temperature and checksum */
<> 128:9bcdf88f62b0 43 __IM uint32_t ADC0CAL0; /**< ADC0 Calibration register 0 */
<> 128:9bcdf88f62b0 44 __IM uint32_t ADC0CAL1; /**< ADC0 Calibration register 1 */
<> 128:9bcdf88f62b0 45 __IM uint32_t ADC0CAL2; /**< ADC0 Calibration register 2 */
<> 128:9bcdf88f62b0 46 uint32_t RESERVED0[2]; /**< Reserved */
<> 128:9bcdf88f62b0 47 __IM uint32_t DAC0CAL0; /**< DAC calibrartion register 0 */
<> 128:9bcdf88f62b0 48 __IM uint32_t DAC0CAL1; /**< DAC calibrartion register 1 */
<> 128:9bcdf88f62b0 49 __IM uint32_t DAC0CAL2; /**< DAC calibrartion register 2 */
<> 128:9bcdf88f62b0 50 __IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO calibration register 0 */
<> 128:9bcdf88f62b0 51 __IM uint32_t AUXHFRCOCAL1; /**< AUXHFRCO calibration register 1 */
<> 128:9bcdf88f62b0 52 __IM uint32_t HFRCOCAL0; /**< HFRCO calibration register 0 */
<> 128:9bcdf88f62b0 53 __IM uint32_t HFRCOCAL1; /**< HFRCO calibration register 1 */
<> 128:9bcdf88f62b0 54 __IM uint32_t MEMINFO; /**< Memory information */
<> 128:9bcdf88f62b0 55 uint32_t RESERVED2[2]; /**< Reserved */
<> 128:9bcdf88f62b0 56 __IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
<> 128:9bcdf88f62b0 57 __IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */
<> 128:9bcdf88f62b0 58 __IM uint32_t MSIZE; /**< Flash and SRAM Memory size in KiloBytes */
<> 128:9bcdf88f62b0 59 __IM uint32_t PART; /**< Part description */
<> 128:9bcdf88f62b0 60 } DEVINFO_TypeDef; /** @} */
<> 128:9bcdf88f62b0 61
<> 128:9bcdf88f62b0 62 /**************************************************************************//**
<> 128:9bcdf88f62b0 63 * @defgroup EFM32LG_DEVINFO_BitFields
<> 128:9bcdf88f62b0 64 * @{
<> 128:9bcdf88f62b0 65 *****************************************************************************/
<> 128:9bcdf88f62b0 66 /* Bit fields for EFM32LG_DEVINFO */
<> 128:9bcdf88f62b0 67 #define _DEVINFO_CAL_CRC_MASK 0x0000FFFFUL /**< Integrity CRC checksum mask */
<> 128:9bcdf88f62b0 68 #define _DEVINFO_CAL_CRC_SHIFT 0 /**< Integrity CRC checksum shift */
<> 128:9bcdf88f62b0 69 #define _DEVINFO_CAL_TEMP_MASK 0x00FF0000UL /**< Calibration temperature, DegC, mask */
<> 128:9bcdf88f62b0 70 #define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Calibration temperature shift */
<> 128:9bcdf88f62b0 71 #define _DEVINFO_ADC0CAL0_1V25_GAIN_MASK 0x00007F00UL /**< Gain for 1V25 reference, mask */
<> 128:9bcdf88f62b0 72 #define _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT 8 /**< Gain for 1V25 reference, shift */
<> 128:9bcdf88f62b0 73 #define _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK 0x0000007FUL /**< Offset for 1V25 reference, mask */
<> 128:9bcdf88f62b0 74 #define _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT 0 /**< Offset for 1V25 reference, shift */
<> 128:9bcdf88f62b0 75 #define _DEVINFO_ADC0CAL0_2V5_GAIN_MASK 0x7F000000UL /**< Gain for 2V5 reference, mask */
<> 128:9bcdf88f62b0 76 #define _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT 24 /**< Gain for 2V5 reference, shift */
<> 128:9bcdf88f62b0 77 #define _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK 0x007F0000UL /**< Offset for 2V5 reference, mask */
<> 128:9bcdf88f62b0 78 #define _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT 16 /**< Offset for 2V5 reference, shift */
<> 128:9bcdf88f62b0 79 #define _DEVINFO_ADC0CAL1_VDD_GAIN_MASK 0x00007F00UL /**< Gain for VDD reference, mask */
<> 128:9bcdf88f62b0 80 #define _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT 8 /**< Gain for VDD reference, shift */
<> 128:9bcdf88f62b0 81 #define _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK 0x0000007FUL /**< Offset for VDD reference, mask */
<> 128:9bcdf88f62b0 82 #define _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT 0 /**< Offset for VDD reference, shift */
<> 128:9bcdf88f62b0 83 #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK 0x7F000000UL /**< Gain 5VDIFF for 5VDIFF reference, mask */
<> 128:9bcdf88f62b0 84 #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT 24 /**< Gain for 5VDIFF reference, mask */
<> 128:9bcdf88f62b0 85 #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK 0x007F0000UL /**< Offset for 5VDIFF reference, mask */
<> 128:9bcdf88f62b0 86 #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT 16 /**< Offset for 5VDIFF reference, shift */
<> 128:9bcdf88f62b0 87 #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK 0x0000007FUL /**< Offset for 2XVDDVSS reference, mask */
<> 128:9bcdf88f62b0 88 #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT 0 /**< Offset for 2XVDDVSS reference, shift */
<> 128:9bcdf88f62b0 89 #define _DEVINFO_ADC0CAL2_TEMP1V25_MASK 0xFFF00000UL /**< Temperature reading at 1V25 reference, mask */
<> 128:9bcdf88f62b0 90 #define _DEVINFO_ADC0CAL2_TEMP1V25_SHIFT 20 /**< Temperature reading at 1V25 reference, DegC */
<> 128:9bcdf88f62b0 91 #define _DEVINFO_DAC0CAL0_1V25_GAIN_MASK 0x007F0000UL /**< Gain for 1V25 reference, mask */
<> 128:9bcdf88f62b0 92 #define _DEVINFO_DAC0CAL0_1V25_GAIN_SHIFT 16 /**< Gain for 1V25 reference, shift */
<> 128:9bcdf88f62b0 93 #define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_MASK 0x00003F00UL /**< Channel 1 offset for 1V25 reference, mask */
<> 128:9bcdf88f62b0 94 #define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_SHIFT 8 /**< Channel 1 offset for 1V25 reference, shift */
<> 128:9bcdf88f62b0 95 #define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_MASK 0x0000003FUL /**< Channel 0 offset for 1V25 reference, mask */
<> 128:9bcdf88f62b0 96 #define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_SHIFT 0 /**< Channel 0 offset for 1V25 reference, shift */
<> 128:9bcdf88f62b0 97 #define _DEVINFO_DAC0CAL1_2V5_GAIN_MASK 0x007F0000UL /**< Gain for 2V5 reference, mask */
<> 128:9bcdf88f62b0 98 #define _DEVINFO_DAC0CAL1_2V5_GAIN_SHIFT 16 /**< Gain for 2V5 reference, shift */
<> 128:9bcdf88f62b0 99 #define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_MASK 0x00003F00UL /**< Channel 1 offset for 2V5 reference, mask */
<> 128:9bcdf88f62b0 100 #define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_SHIFT 8 /**< Channel 1 offset for 2V5 reference, shift */
<> 128:9bcdf88f62b0 101 #define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_MASK 0x0000003FUL /**< Channel 0 offset for 2V5 reference, mask */
<> 128:9bcdf88f62b0 102 #define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_SHIFT 0 /**< Channel 0 offset for 2V5 reference, shift */
<> 128:9bcdf88f62b0 103 #define _DEVINFO_DAC0CAL2_VDD_GAIN_MASK 0x007F0000UL /**< Gain for VDD reference, mask */
<> 128:9bcdf88f62b0 104 #define _DEVINFO_DAC0CAL2_VDD_GAIN_SHIFT 16 /**< Gain for VDD reference, shift */
<> 128:9bcdf88f62b0 105 #define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_MASK 0x00003F00UL /**< Channel 1 offset for VDD reference, mask */
<> 128:9bcdf88f62b0 106 #define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_SHIFT 8 /**< Channel 1 offset for VDD reference, shift */
<> 128:9bcdf88f62b0 107 #define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_MASK 0x0000003FUL /**< Channel 0 offset for VDD reference, mask */
<> 128:9bcdf88f62b0 108 #define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_SHIFT 0 /**< Channel 0 offset for VDD reference, shift*/
<> 128:9bcdf88f62b0 109 #define _DEVINFO_AUXHFRCOCAL0_BAND1_MASK 0x000000FFUL /**< 1MHz tuning value for AUXHFRCO, mask */
<> 128:9bcdf88f62b0 110 #define _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT 0 /**< 1MHz tuning value for AUXHFRCO, shift */
<> 128:9bcdf88f62b0 111 #define _DEVINFO_AUXHFRCOCAL0_BAND7_MASK 0x0000FF00UL /**< 7MHz tuning value for AUXHFRCO, mask */
<> 128:9bcdf88f62b0 112 #define _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT 8 /**< 7MHz tuning value for AUXHFRCO, shift */
<> 128:9bcdf88f62b0 113 #define _DEVINFO_AUXHFRCOCAL0_BAND11_MASK 0x00FF0000UL /**< 11MHz tuning value for AUXHFRCO, mask */
<> 128:9bcdf88f62b0 114 #define _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT 16 /**< 11MHz tuning value for AUXHFRCO, shift */
<> 128:9bcdf88f62b0 115 #define _DEVINFO_AUXHFRCOCAL0_BAND14_MASK 0xFF000000UL /**< 14MHz tuning value for AUXHFRCO, mask */
<> 128:9bcdf88f62b0 116 #define _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT 24 /**< 14MHz tuning value for AUXHFRCO, shift */
<> 128:9bcdf88f62b0 117 #define _DEVINFO_AUXHFRCOCAL1_BAND21_MASK 0x000000FFUL /**< 21MHz tuning value for AUXHFRCO, mask */
<> 128:9bcdf88f62b0 118 #define _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT 0 /**< 21MHz tuning value for AUXHFRCO, shift */
<> 128:9bcdf88f62b0 119 #define _DEVINFO_AUXHFRCOCAL1_BAND28_MASK 0x0000FF00UL /**< 28MHz tuning value for AUXHFRCO, shift */
<> 128:9bcdf88f62b0 120 #define _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT 8 /**< 28MHz tuning value for AUXHFRCO, mask */
<> 128:9bcdf88f62b0 121 #define _DEVINFO_HFRCOCAL0_BAND1_MASK 0x000000FFUL /**< 1MHz tuning value for HFRCO, mask */
<> 128:9bcdf88f62b0 122 #define _DEVINFO_HFRCOCAL0_BAND1_SHIFT 0 /**< 1MHz tuning value for HFRCO, shift */
<> 128:9bcdf88f62b0 123 #define _DEVINFO_HFRCOCAL0_BAND7_MASK 0x0000FF00UL /**< 7MHz tuning value for HFRCO, mask */
<> 128:9bcdf88f62b0 124 #define _DEVINFO_HFRCOCAL0_BAND7_SHIFT 8 /**< 7MHz tuning value for HFRCO, shift */
<> 128:9bcdf88f62b0 125 #define _DEVINFO_HFRCOCAL0_BAND11_MASK 0x00FF0000UL /**< 11MHz tuning value for HFRCO, mask */
<> 128:9bcdf88f62b0 126 #define _DEVINFO_HFRCOCAL0_BAND11_SHIFT 16 /**< 11MHz tuning value for HFRCO, shift */
<> 128:9bcdf88f62b0 127 #define _DEVINFO_HFRCOCAL0_BAND14_MASK 0xFF000000UL /**< 14MHz tuning value for HFRCO, mask */
<> 128:9bcdf88f62b0 128 #define _DEVINFO_HFRCOCAL0_BAND14_SHIFT 24 /**< 14MHz tuning value for HFRCO, shift */
<> 128:9bcdf88f62b0 129 #define _DEVINFO_HFRCOCAL1_BAND21_MASK 0x000000FFUL /**< 21MHz tuning value for HFRCO, mask */
<> 128:9bcdf88f62b0 130 #define _DEVINFO_HFRCOCAL1_BAND21_SHIFT 0 /**< 21MHz tuning value for HFRCO, shift */
<> 128:9bcdf88f62b0 131 #define _DEVINFO_HFRCOCAL1_BAND28_MASK 0x0000FF00UL /**< 28MHz tuning value for HFRCO, shift */
<> 128:9bcdf88f62b0 132 #define _DEVINFO_HFRCOCAL1_BAND28_SHIFT 8 /**< 28MHz tuning value for HFRCO, mask */
<> 128:9bcdf88f62b0 133 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Flash page size (refer to ref.man for encoding) mask */
<> 128:9bcdf88f62b0 134 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Flash page size shift */
<> 128:9bcdf88f62b0 135 #define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Lower part of 64-bit device unique number */
<> 128:9bcdf88f62b0 136 #define _DEVINFO_UNIQUEL_SHIFT 0 /**< Unique Low 32-bit shift */
<> 128:9bcdf88f62b0 137 #define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< High part of 64-bit device unique number */
<> 128:9bcdf88f62b0 138 #define _DEVINFO_UNIQUEH_SHIFT 0 /**< Unique High 32-bit shift */
<> 128:9bcdf88f62b0 139 #define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Flash size in kilobytes */
<> 128:9bcdf88f62b0 140 #define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Bit position for flash size */
<> 128:9bcdf88f62b0 141 #define _DEVINFO_MSIZE_FLASH_MASK 0x0000FFFFUL /**< SRAM size in kilobytes */
<> 128:9bcdf88f62b0 142 #define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Bit position for SRAM size */
<> 128:9bcdf88f62b0 143 #define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Production revision */
<> 128:9bcdf88f62b0 144 #define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Bit position for production revision */
<> 128:9bcdf88f62b0 145 #define _DEVINFO_PART_DEVICE_FAMILY_MASK 0x00FF0000UL /**< Device Family, 0x47 for Gecko */
<> 128:9bcdf88f62b0 146 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Bit position for device family */
<> 128:9bcdf88f62b0 147 /* Legacy family #defines */
<> 128:9bcdf88f62b0 148 #define _DEVINFO_PART_DEVICE_FAMILY_G 71 /**< Gecko Device Family */
<> 128:9bcdf88f62b0 149 #define _DEVINFO_PART_DEVICE_FAMILY_GG 72 /**< Giant Gecko Device Family */
<> 128:9bcdf88f62b0 150 #define _DEVINFO_PART_DEVICE_FAMILY_TG 73 /**< Tiny Gecko Device Family */
<> 128:9bcdf88f62b0 151 #define _DEVINFO_PART_DEVICE_FAMILY_LG 74 /**< Leopard Gecko Device Family */
<> 128:9bcdf88f62b0 152 #define _DEVINFO_PART_DEVICE_FAMILY_WG 75 /**< Wonder Gecko Device Family */
<> 128:9bcdf88f62b0 153 #define _DEVINFO_PART_DEVICE_FAMILY_ZG 76 /**< Zero Gecko Device Family */
<> 128:9bcdf88f62b0 154 #define _DEVINFO_PART_DEVICE_FAMILY_HG 77 /**< Happy Gecko Device Family */
<> 128:9bcdf88f62b0 155 /* New style family #defines */
<> 128:9bcdf88f62b0 156 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 71 /**< Gecko Device Family */
<> 128:9bcdf88f62b0 157 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 72 /**< Giant Gecko Device Family */
<> 128:9bcdf88f62b0 158 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 73 /**< Tiny Gecko Device Family */
<> 128:9bcdf88f62b0 159 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 74 /**< Leopard Gecko Device Family */
<> 128:9bcdf88f62b0 160 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 75 /**< Wonder Gecko Device Family */
<> 128:9bcdf88f62b0 161 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 76 /**< Zero Gecko Device Family */
<> 128:9bcdf88f62b0 162 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 77 /**< Happy Gecko Device Family */
<> 128:9bcdf88f62b0 163 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 120 /**< EZR Wonder Gecko Device Family */
<> 128:9bcdf88f62b0 164 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 121 /**< EZR Leopard Gecko Device Family */
<> 128:9bcdf88f62b0 165 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 122 /**< EZR Happy Gecko Device Family */
<> 128:9bcdf88f62b0 166 #define _DEVINFO_PART_DEVICE_NUMBER_MASK 0x0000FFFFUL /**< Device number */
<> 128:9bcdf88f62b0 167 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Bit position for device number */
<> 128:9bcdf88f62b0 168
<> 128:9bcdf88f62b0 169 /** @} End of group EFM32LG_DEVINFO */
<> 128:9bcdf88f62b0 170 /** @} End of group Parts */
<> 128:9bcdf88f62b0 171