mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32LG_STK3600/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg980f64.h@128:9bcdf88f62b0, 2016-10-27 (annotated)

Committer:
<>
Date:
Thu Oct 27 16:45:56 2016 +0100
Revision:
128:9bcdf88f62b0
Child:
139:856d2700e60b
Release 128 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



2966: Add kw24 support https://github.com/ARMmbed/mbed-os/pull/2966

3068: MultiTech mDot - clean up PeripheralPins.c and add new pin names https://github.com/ARMmbed/mbed-os/pull/3068

3089: Kinetis HAL: Remove clock initialization code from serial and ticker  https://github.com/ARMmbed/mbed-os/pull/3089

2943: [NRF5] NVIC_SetVector functionality https://github.com/ARMmbed/mbed-os/pull/2943

2938: InterruptIn changes in NCS36510 HAL. https://github.com/ARMmbed/mbed-os/pull/2938

3108: Fix sleep function for NRF52. https://github.com/ARMmbed/mbed-os/pull/3108

3076: STM32F1: Correct timer master value reading https://github.com/ARMmbed/mbed-os/pull/3076

3085: Add LOWPOWERTIMER capability for NUCLEO_F303ZE https://github.com/ARMmbed/mbed-os/pull/3085

3046: [BEETLE] Update BLE stack on Beetle board https://github.com/ARMmbed/mbed-os/pull/3046

3122: [Silicon Labs] Update of Silicon Labs HAL https://github.com/ARMmbed/mbed-os/pull/3122

3022: OnSemi RAM usage fix https://github.com/ARMmbed/mbed-os/pull/3022

3121: STM32F3: Correct UART4 and UART5 defines when using DEVICE_SERIAL_ASYNCH https://github.com/ARMmbed/mbed-os/pull/3121

3142: Targets- NUMAKER_PFM_NUC47216 remove mbed 2 https://github.com/ARMmbed/mbed-os/pull/3142

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**************************************************************************//**
<> 128:9bcdf88f62b0 2 * @file efm32lg980f64.h
<> 128:9bcdf88f62b0 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
<> 128:9bcdf88f62b0 4 * for EFM32LG980F64
<> 128:9bcdf88f62b0 5 * @version 5.0.0
<> 128:9bcdf88f62b0 6 ******************************************************************************
<> 128:9bcdf88f62b0 7 * @section License
<> 128:9bcdf88f62b0 8 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 128:9bcdf88f62b0 9 ******************************************************************************
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * Permission is granted to anyone to use this software for any purpose,
<> 128:9bcdf88f62b0 12 * including commercial applications, and to alter it and redistribute it
<> 128:9bcdf88f62b0 13 * freely, subject to the following restrictions:
<> 128:9bcdf88f62b0 14 *
<> 128:9bcdf88f62b0 15 * 1. The origin of this software must not be misrepresented; you must not
<> 128:9bcdf88f62b0 16 * claim that you wrote the original software.@n
<> 128:9bcdf88f62b0 17 * 2. Altered source versions must be plainly marked as such, and must not be
<> 128:9bcdf88f62b0 18 * misrepresented as being the original software.@n
<> 128:9bcdf88f62b0 19 * 3. This notice may not be removed or altered from any source distribution.
<> 128:9bcdf88f62b0 20 *
<> 128:9bcdf88f62b0 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 128:9bcdf88f62b0 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 128:9bcdf88f62b0 23 * providing the Software "AS IS", with no express or implied warranties of any
<> 128:9bcdf88f62b0 24 * kind, including, but not limited to, any implied warranties of
<> 128:9bcdf88f62b0 25 * merchantability or fitness for any particular purpose or warranties against
<> 128:9bcdf88f62b0 26 * infringement of any proprietary rights of a third party.
<> 128:9bcdf88f62b0 27 *
<> 128:9bcdf88f62b0 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 128:9bcdf88f62b0 29 * incidental, or special damages, or any other relief, or for any claim by
<> 128:9bcdf88f62b0 30 * any third party, arising from your use of this Software.
<> 128:9bcdf88f62b0 31 *
<> 128:9bcdf88f62b0 32 *****************************************************************************/
<> 128:9bcdf88f62b0 33
<> 128:9bcdf88f62b0 34 #ifndef EFM32LG980F64_H
<> 128:9bcdf88f62b0 35 #define EFM32LG980F64_H
<> 128:9bcdf88f62b0 36
<> 128:9bcdf88f62b0 37 #ifdef __cplusplus
<> 128:9bcdf88f62b0 38 extern "C" {
<> 128:9bcdf88f62b0 39 #endif
<> 128:9bcdf88f62b0 40
<> 128:9bcdf88f62b0 41 /**************************************************************************//**
<> 128:9bcdf88f62b0 42 * @addtogroup Parts
<> 128:9bcdf88f62b0 43 * @{
<> 128:9bcdf88f62b0 44 *****************************************************************************/
<> 128:9bcdf88f62b0 45
<> 128:9bcdf88f62b0 46 /**************************************************************************//**
<> 128:9bcdf88f62b0 47 * @defgroup EFM32LG980F64 EFM32LG980F64
<> 128:9bcdf88f62b0 48 * @{
<> 128:9bcdf88f62b0 49 *****************************************************************************/
<> 128:9bcdf88f62b0 50
<> 128:9bcdf88f62b0 51 /** Interrupt Number Definition */
<> 128:9bcdf88f62b0 52 typedef enum IRQn
<> 128:9bcdf88f62b0 53 {
<> 128:9bcdf88f62b0 54 /****** Cortex-M3 Processor Exceptions Numbers ********************************************/
<> 128:9bcdf88f62b0 55 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M3 Non Maskable Interrupt */
<> 128:9bcdf88f62b0 56 HardFault_IRQn = -13, /*!< -13 Cortex-M3 Hard Fault Interrupt */
<> 128:9bcdf88f62b0 57 MemoryManagement_IRQn = -12, /*!< -12 Cortex-M3 Memory Management Interrupt */
<> 128:9bcdf88f62b0 58 BusFault_IRQn = -11, /*!< -11 Cortex-M3 Bus Fault Interrupt */
<> 128:9bcdf88f62b0 59 UsageFault_IRQn = -10, /*!< -10 Cortex-M3 Usage Fault Interrupt */
<> 128:9bcdf88f62b0 60 SVCall_IRQn = -5, /*!< -5 Cortex-M3 SV Call Interrupt */
<> 128:9bcdf88f62b0 61 DebugMonitor_IRQn = -4, /*!< -4 Cortex-M3 Debug Monitor Interrupt */
<> 128:9bcdf88f62b0 62 PendSV_IRQn = -2, /*!< -2 Cortex-M3 Pend SV Interrupt */
<> 128:9bcdf88f62b0 63 SysTick_IRQn = -1, /*!< -1 Cortex-M3 System Tick Interrupt */
<> 128:9bcdf88f62b0 64
<> 128:9bcdf88f62b0 65 /****** EFM32LG Peripheral Interrupt Numbers **********************************************/
<> 128:9bcdf88f62b0 66
<> 128:9bcdf88f62b0 67 DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
<> 128:9bcdf88f62b0 68 GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
<> 128:9bcdf88f62b0 69 TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
<> 128:9bcdf88f62b0 70 USART0_RX_IRQn = 3, /*!< 3 EFM32 USART0_RX Interrupt */
<> 128:9bcdf88f62b0 71 USART0_TX_IRQn = 4, /*!< 4 EFM32 USART0_TX Interrupt */
<> 128:9bcdf88f62b0 72 USB_IRQn = 5, /*!< 5 EFM32 USB Interrupt */
<> 128:9bcdf88f62b0 73 ACMP0_IRQn = 6, /*!< 6 EFM32 ACMP0 Interrupt */
<> 128:9bcdf88f62b0 74 ADC0_IRQn = 7, /*!< 7 EFM32 ADC0 Interrupt */
<> 128:9bcdf88f62b0 75 DAC0_IRQn = 8, /*!< 8 EFM32 DAC0 Interrupt */
<> 128:9bcdf88f62b0 76 I2C0_IRQn = 9, /*!< 9 EFM32 I2C0 Interrupt */
<> 128:9bcdf88f62b0 77 I2C1_IRQn = 10, /*!< 10 EFM32 I2C1 Interrupt */
<> 128:9bcdf88f62b0 78 GPIO_ODD_IRQn = 11, /*!< 11 EFM32 GPIO_ODD Interrupt */
<> 128:9bcdf88f62b0 79 TIMER1_IRQn = 12, /*!< 12 EFM32 TIMER1 Interrupt */
<> 128:9bcdf88f62b0 80 TIMER2_IRQn = 13, /*!< 13 EFM32 TIMER2 Interrupt */
<> 128:9bcdf88f62b0 81 TIMER3_IRQn = 14, /*!< 14 EFM32 TIMER3 Interrupt */
<> 128:9bcdf88f62b0 82 USART1_RX_IRQn = 15, /*!< 15 EFM32 USART1_RX Interrupt */
<> 128:9bcdf88f62b0 83 USART1_TX_IRQn = 16, /*!< 16 EFM32 USART1_TX Interrupt */
<> 128:9bcdf88f62b0 84 LESENSE_IRQn = 17, /*!< 17 EFM32 LESENSE Interrupt */
<> 128:9bcdf88f62b0 85 USART2_RX_IRQn = 18, /*!< 18 EFM32 USART2_RX Interrupt */
<> 128:9bcdf88f62b0 86 USART2_TX_IRQn = 19, /*!< 19 EFM32 USART2_TX Interrupt */
<> 128:9bcdf88f62b0 87 UART0_RX_IRQn = 20, /*!< 20 EFM32 UART0_RX Interrupt */
<> 128:9bcdf88f62b0 88 UART0_TX_IRQn = 21, /*!< 21 EFM32 UART0_TX Interrupt */
<> 128:9bcdf88f62b0 89 UART1_RX_IRQn = 22, /*!< 22 EFM32 UART1_RX Interrupt */
<> 128:9bcdf88f62b0 90 UART1_TX_IRQn = 23, /*!< 23 EFM32 UART1_TX Interrupt */
<> 128:9bcdf88f62b0 91 LEUART0_IRQn = 24, /*!< 24 EFM32 LEUART0 Interrupt */
<> 128:9bcdf88f62b0 92 LEUART1_IRQn = 25, /*!< 25 EFM32 LEUART1 Interrupt */
<> 128:9bcdf88f62b0 93 LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
<> 128:9bcdf88f62b0 94 PCNT0_IRQn = 27, /*!< 27 EFM32 PCNT0 Interrupt */
<> 128:9bcdf88f62b0 95 PCNT1_IRQn = 28, /*!< 28 EFM32 PCNT1 Interrupt */
<> 128:9bcdf88f62b0 96 PCNT2_IRQn = 29, /*!< 29 EFM32 PCNT2 Interrupt */
<> 128:9bcdf88f62b0 97 RTC_IRQn = 30, /*!< 30 EFM32 RTC Interrupt */
<> 128:9bcdf88f62b0 98 BURTC_IRQn = 31, /*!< 31 EFM32 BURTC Interrupt */
<> 128:9bcdf88f62b0 99 CMU_IRQn = 32, /*!< 32 EFM32 CMU Interrupt */
<> 128:9bcdf88f62b0 100 VCMP_IRQn = 33, /*!< 33 EFM32 VCMP Interrupt */
<> 128:9bcdf88f62b0 101 LCD_IRQn = 34, /*!< 34 EFM32 LCD Interrupt */
<> 128:9bcdf88f62b0 102 MSC_IRQn = 35, /*!< 35 EFM32 MSC Interrupt */
<> 128:9bcdf88f62b0 103 AES_IRQn = 36, /*!< 36 EFM32 AES Interrupt */
<> 128:9bcdf88f62b0 104 EBI_IRQn = 37, /*!< 37 EFM32 EBI Interrupt */
<> 128:9bcdf88f62b0 105 EMU_IRQn = 38, /*!< 38 EFM32 EMU Interrupt */
<> 128:9bcdf88f62b0 106 } IRQn_Type;
<> 128:9bcdf88f62b0 107
<> 128:9bcdf88f62b0 108 /**************************************************************************//**
<> 128:9bcdf88f62b0 109 * @defgroup EFM32LG980F64_Core EFM32LG980F64 Core
<> 128:9bcdf88f62b0 110 * @{
<> 128:9bcdf88f62b0 111 * @brief Processor and Core Peripheral Section
<> 128:9bcdf88f62b0 112 *****************************************************************************/
<> 128:9bcdf88f62b0 113 #define __MPU_PRESENT 1 /**< Presence of MPU */
<> 128:9bcdf88f62b0 114 #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
<> 128:9bcdf88f62b0 115 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
<> 128:9bcdf88f62b0 116 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
<> 128:9bcdf88f62b0 117
<> 128:9bcdf88f62b0 118 /** @} End of group EFM32LG980F64_Core */
<> 128:9bcdf88f62b0 119
<> 128:9bcdf88f62b0 120 /**************************************************************************//**
<> 128:9bcdf88f62b0 121 * @defgroup EFM32LG980F64_Part EFM32LG980F64 Part
<> 128:9bcdf88f62b0 122 * @{
<> 128:9bcdf88f62b0 123 ******************************************************************************/
<> 128:9bcdf88f62b0 124
<> 128:9bcdf88f62b0 125 /** Part family */
<> 128:9bcdf88f62b0 126 #define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
<> 128:9bcdf88f62b0 127 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
<> 128:9bcdf88f62b0 128 #define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
<> 128:9bcdf88f62b0 129 #define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
<> 128:9bcdf88f62b0 130 #define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
<> 128:9bcdf88f62b0 131 #define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
<> 128:9bcdf88f62b0 132
<> 128:9bcdf88f62b0 133 /* If part number is not defined as compiler option, define it */
<> 128:9bcdf88f62b0 134 #if !defined(EFM32LG980F64)
<> 128:9bcdf88f62b0 135 #define EFM32LG980F64 1 /**< Giant/Leopard Gecko Part */
<> 128:9bcdf88f62b0 136 #endif
<> 128:9bcdf88f62b0 137
<> 128:9bcdf88f62b0 138 /** Configure part number */
<> 128:9bcdf88f62b0 139 #define PART_NUMBER "EFM32LG980F64" /**< Part Number */
<> 128:9bcdf88f62b0 140
<> 128:9bcdf88f62b0 141 /** Memory Base addresses and limits */
<> 128:9bcdf88f62b0 142 #define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
<> 128:9bcdf88f62b0 143 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
<> 128:9bcdf88f62b0 144 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
<> 128:9bcdf88f62b0 145 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
<> 128:9bcdf88f62b0 146 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
<> 128:9bcdf88f62b0 147 #define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
<> 128:9bcdf88f62b0 148 #define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
<> 128:9bcdf88f62b0 149 #define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
<> 128:9bcdf88f62b0 150 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
<> 128:9bcdf88f62b0 151 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
<> 128:9bcdf88f62b0 152 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
<> 128:9bcdf88f62b0 153 #define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
<> 128:9bcdf88f62b0 154 #define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
<> 128:9bcdf88f62b0 155 #define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
<> 128:9bcdf88f62b0 156 #define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
<> 128:9bcdf88f62b0 157 #define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
<> 128:9bcdf88f62b0 158 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
<> 128:9bcdf88f62b0 159 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
<> 128:9bcdf88f62b0 160 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
<> 128:9bcdf88f62b0 161 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
<> 128:9bcdf88f62b0 162 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
<> 128:9bcdf88f62b0 163 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
<> 128:9bcdf88f62b0 164 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
<> 128:9bcdf88f62b0 165 #define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
<> 128:9bcdf88f62b0 166 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
<> 128:9bcdf88f62b0 167 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
<> 128:9bcdf88f62b0 168 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
<> 128:9bcdf88f62b0 169 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
<> 128:9bcdf88f62b0 170 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
<> 128:9bcdf88f62b0 171 #define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
<> 128:9bcdf88f62b0 172 #define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
<> 128:9bcdf88f62b0 173 #define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
<> 128:9bcdf88f62b0 174
<> 128:9bcdf88f62b0 175 /** Bit banding area */
<> 128:9bcdf88f62b0 176 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
<> 128:9bcdf88f62b0 177 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
<> 128:9bcdf88f62b0 178
<> 128:9bcdf88f62b0 179 /** Flash and SRAM limits for EFM32LG980F64 */
<> 128:9bcdf88f62b0 180 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
<> 128:9bcdf88f62b0 181 #define FLASH_SIZE (0x00010000UL) /**< Available Flash Memory */
<> 128:9bcdf88f62b0 182 #define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
<> 128:9bcdf88f62b0 183 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
<> 128:9bcdf88f62b0 184 #define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
<> 128:9bcdf88f62b0 185 #define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
<> 128:9bcdf88f62b0 186 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
<> 128:9bcdf88f62b0 187 #define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
<> 128:9bcdf88f62b0 188 #define EXT_IRQ_COUNT 40 /**< Number of External (NVIC) interrupts */
<> 128:9bcdf88f62b0 189
<> 128:9bcdf88f62b0 190 /** AF channels connect the different on-chip peripherals with the af-mux */
<> 128:9bcdf88f62b0 191 #define AFCHAN_MAX 163
<> 128:9bcdf88f62b0 192 #define AFCHANLOC_MAX 7
<> 128:9bcdf88f62b0 193 /** Analog AF channels */
<> 128:9bcdf88f62b0 194 #define AFACHAN_MAX 53
<> 128:9bcdf88f62b0 195
<> 128:9bcdf88f62b0 196 /* Part number capabilities */
<> 128:9bcdf88f62b0 197
<> 128:9bcdf88f62b0 198 #define USART_PRESENT /**< USART is available in this part */
<> 128:9bcdf88f62b0 199 #define USART_COUNT 3 /**< 3 USARTs available */
<> 128:9bcdf88f62b0 200 #define UART_PRESENT /**< UART is available in this part */
<> 128:9bcdf88f62b0 201 #define UART_COUNT 2 /**< 2 UARTs available */
<> 128:9bcdf88f62b0 202 #define TIMER_PRESENT /**< TIMER is available in this part */
<> 128:9bcdf88f62b0 203 #define TIMER_COUNT 4 /**< 4 TIMERs available */
<> 128:9bcdf88f62b0 204 #define ACMP_PRESENT /**< ACMP is available in this part */
<> 128:9bcdf88f62b0 205 #define ACMP_COUNT 2 /**< 2 ACMPs available */
<> 128:9bcdf88f62b0 206 #define LEUART_PRESENT /**< LEUART is available in this part */
<> 128:9bcdf88f62b0 207 #define LEUART_COUNT 2 /**< 2 LEUARTs available */
<> 128:9bcdf88f62b0 208 #define LETIMER_PRESENT /**< LETIMER is available in this part */
<> 128:9bcdf88f62b0 209 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */
<> 128:9bcdf88f62b0 210 #define PCNT_PRESENT /**< PCNT is available in this part */
<> 128:9bcdf88f62b0 211 #define PCNT_COUNT 3 /**< 3 PCNTs available */
<> 128:9bcdf88f62b0 212 #define I2C_PRESENT /**< I2C is available in this part */
<> 128:9bcdf88f62b0 213 #define I2C_COUNT 2 /**< 2 I2Cs available */
<> 128:9bcdf88f62b0 214 #define ADC_PRESENT /**< ADC is available in this part */
<> 128:9bcdf88f62b0 215 #define ADC_COUNT 1 /**< 1 ADCs available */
<> 128:9bcdf88f62b0 216 #define DAC_PRESENT /**< DAC is available in this part */
<> 128:9bcdf88f62b0 217 #define DAC_COUNT 1 /**< 1 DACs available */
<> 128:9bcdf88f62b0 218 #define DMA_PRESENT
<> 128:9bcdf88f62b0 219 #define DMA_COUNT 1
<> 128:9bcdf88f62b0 220 #define AES_PRESENT
<> 128:9bcdf88f62b0 221 #define AES_COUNT 1
<> 128:9bcdf88f62b0 222 #define USBC_PRESENT
<> 128:9bcdf88f62b0 223 #define USBC_COUNT 1
<> 128:9bcdf88f62b0 224 #define USB_PRESENT
<> 128:9bcdf88f62b0 225 #define USB_COUNT 1
<> 128:9bcdf88f62b0 226 #define LE_PRESENT
<> 128:9bcdf88f62b0 227 #define LE_COUNT 1
<> 128:9bcdf88f62b0 228 #define MSC_PRESENT
<> 128:9bcdf88f62b0 229 #define MSC_COUNT 1
<> 128:9bcdf88f62b0 230 #define EMU_PRESENT
<> 128:9bcdf88f62b0 231 #define EMU_COUNT 1
<> 128:9bcdf88f62b0 232 #define RMU_PRESENT
<> 128:9bcdf88f62b0 233 #define RMU_COUNT 1
<> 128:9bcdf88f62b0 234 #define CMU_PRESENT
<> 128:9bcdf88f62b0 235 #define CMU_COUNT 1
<> 128:9bcdf88f62b0 236 #define LESENSE_PRESENT
<> 128:9bcdf88f62b0 237 #define LESENSE_COUNT 1
<> 128:9bcdf88f62b0 238 #define EBI_PRESENT
<> 128:9bcdf88f62b0 239 #define EBI_COUNT 1
<> 128:9bcdf88f62b0 240 #define RTC_PRESENT
<> 128:9bcdf88f62b0 241 #define RTC_COUNT 1
<> 128:9bcdf88f62b0 242 #define GPIO_PRESENT
<> 128:9bcdf88f62b0 243 #define GPIO_COUNT 1
<> 128:9bcdf88f62b0 244 #define VCMP_PRESENT
<> 128:9bcdf88f62b0 245 #define VCMP_COUNT 1
<> 128:9bcdf88f62b0 246 #define PRS_PRESENT
<> 128:9bcdf88f62b0 247 #define PRS_COUNT 1
<> 128:9bcdf88f62b0 248 #define OPAMP_PRESENT
<> 128:9bcdf88f62b0 249 #define OPAMP_COUNT 1
<> 128:9bcdf88f62b0 250 #define BU_PRESENT
<> 128:9bcdf88f62b0 251 #define BU_COUNT 1
<> 128:9bcdf88f62b0 252 #define LCD_PRESENT
<> 128:9bcdf88f62b0 253 #define LCD_COUNT 1
<> 128:9bcdf88f62b0 254 #define BURTC_PRESENT
<> 128:9bcdf88f62b0 255 #define BURTC_COUNT 1
<> 128:9bcdf88f62b0 256 #define HFXTAL_PRESENT
<> 128:9bcdf88f62b0 257 #define HFXTAL_COUNT 1
<> 128:9bcdf88f62b0 258 #define LFXTAL_PRESENT
<> 128:9bcdf88f62b0 259 #define LFXTAL_COUNT 1
<> 128:9bcdf88f62b0 260 #define WDOG_PRESENT
<> 128:9bcdf88f62b0 261 #define WDOG_COUNT 1
<> 128:9bcdf88f62b0 262 #define DBG_PRESENT
<> 128:9bcdf88f62b0 263 #define DBG_COUNT 1
<> 128:9bcdf88f62b0 264 #define ETM_PRESENT
<> 128:9bcdf88f62b0 265 #define ETM_COUNT 1
<> 128:9bcdf88f62b0 266 #define BOOTLOADER_PRESENT
<> 128:9bcdf88f62b0 267 #define BOOTLOADER_COUNT 1
<> 128:9bcdf88f62b0 268 #define ANALOG_PRESENT
<> 128:9bcdf88f62b0 269 #define ANALOG_COUNT 1
<> 128:9bcdf88f62b0 270
<> 128:9bcdf88f62b0 271 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
<> 128:9bcdf88f62b0 272 #include "system_efm32lg.h" /* System Header */
<> 128:9bcdf88f62b0 273
<> 128:9bcdf88f62b0 274 /** @} End of group EFM32LG980F64_Part */
<> 128:9bcdf88f62b0 275
<> 128:9bcdf88f62b0 276 /**************************************************************************//**
<> 128:9bcdf88f62b0 277 * @defgroup EFM32LG980F64_Peripheral_TypeDefs EFM32LG980F64 Peripheral TypeDefs
<> 128:9bcdf88f62b0 278 * @{
<> 128:9bcdf88f62b0 279 * @brief Device Specific Peripheral Register Structures
<> 128:9bcdf88f62b0 280 *****************************************************************************/
<> 128:9bcdf88f62b0 281
<> 128:9bcdf88f62b0 282 #include "efm32lg_dma_ch.h"
<> 128:9bcdf88f62b0 283 #include "efm32lg_dma.h"
<> 128:9bcdf88f62b0 284 #include "efm32lg_aes.h"
<> 128:9bcdf88f62b0 285 #include "efm32lg_usb_hc.h"
<> 128:9bcdf88f62b0 286 #include "efm32lg_usb_diep.h"
<> 128:9bcdf88f62b0 287 #include "efm32lg_usb_doep.h"
<> 128:9bcdf88f62b0 288 #include "efm32lg_usb.h"
<> 128:9bcdf88f62b0 289 #include "efm32lg_msc.h"
<> 128:9bcdf88f62b0 290 #include "efm32lg_emu.h"
<> 128:9bcdf88f62b0 291 #include "efm32lg_rmu.h"
<> 128:9bcdf88f62b0 292 #include "efm32lg_cmu.h"
<> 128:9bcdf88f62b0 293 #include "efm32lg_lesense_st.h"
<> 128:9bcdf88f62b0 294 #include "efm32lg_lesense_buf.h"
<> 128:9bcdf88f62b0 295 #include "efm32lg_lesense_ch.h"
<> 128:9bcdf88f62b0 296 #include "efm32lg_lesense.h"
<> 128:9bcdf88f62b0 297 #include "efm32lg_ebi.h"
<> 128:9bcdf88f62b0 298 #include "efm32lg_usart.h"
<> 128:9bcdf88f62b0 299 #include "efm32lg_timer_cc.h"
<> 128:9bcdf88f62b0 300 #include "efm32lg_timer.h"
<> 128:9bcdf88f62b0 301 #include "efm32lg_acmp.h"
<> 128:9bcdf88f62b0 302 #include "efm32lg_leuart.h"
<> 128:9bcdf88f62b0 303 #include "efm32lg_rtc.h"
<> 128:9bcdf88f62b0 304 #include "efm32lg_letimer.h"
<> 128:9bcdf88f62b0 305 #include "efm32lg_pcnt.h"
<> 128:9bcdf88f62b0 306 #include "efm32lg_i2c.h"
<> 128:9bcdf88f62b0 307 #include "efm32lg_gpio_p.h"
<> 128:9bcdf88f62b0 308 #include "efm32lg_gpio.h"
<> 128:9bcdf88f62b0 309 #include "efm32lg_vcmp.h"
<> 128:9bcdf88f62b0 310 #include "efm32lg_prs_ch.h"
<> 128:9bcdf88f62b0 311 #include "efm32lg_prs.h"
<> 128:9bcdf88f62b0 312 #include "efm32lg_adc.h"
<> 128:9bcdf88f62b0 313 #include "efm32lg_dac.h"
<> 128:9bcdf88f62b0 314 #include "efm32lg_lcd.h"
<> 128:9bcdf88f62b0 315 #include "efm32lg_burtc_ret.h"
<> 128:9bcdf88f62b0 316 #include "efm32lg_burtc.h"
<> 128:9bcdf88f62b0 317 #include "efm32lg_wdog.h"
<> 128:9bcdf88f62b0 318 #include "efm32lg_etm.h"
<> 128:9bcdf88f62b0 319 #include "efm32lg_dma_descriptor.h"
<> 128:9bcdf88f62b0 320 #include "efm32lg_devinfo.h"
<> 128:9bcdf88f62b0 321 #include "efm32lg_romtable.h"
<> 128:9bcdf88f62b0 322 #include "efm32lg_calibrate.h"
<> 128:9bcdf88f62b0 323
<> 128:9bcdf88f62b0 324 /** @} End of group EFM32LG980F64_Peripheral_TypeDefs */
<> 128:9bcdf88f62b0 325
<> 128:9bcdf88f62b0 326 /**************************************************************************//**
<> 128:9bcdf88f62b0 327 * @defgroup EFM32LG980F64_Peripheral_Base EFM32LG980F64 Peripheral Memory Map
<> 128:9bcdf88f62b0 328 * @{
<> 128:9bcdf88f62b0 329 *****************************************************************************/
<> 128:9bcdf88f62b0 330
<> 128:9bcdf88f62b0 331 #define DMA_BASE (0x400C2000UL) /**< DMA base address */
<> 128:9bcdf88f62b0 332 #define AES_BASE (0x400E0000UL) /**< AES base address */
<> 128:9bcdf88f62b0 333 #define USB_BASE (0x400C4000UL) /**< USB base address */
<> 128:9bcdf88f62b0 334 #define MSC_BASE (0x400C0000UL) /**< MSC base address */
<> 128:9bcdf88f62b0 335 #define EMU_BASE (0x400C6000UL) /**< EMU base address */
<> 128:9bcdf88f62b0 336 #define RMU_BASE (0x400CA000UL) /**< RMU base address */
<> 128:9bcdf88f62b0 337 #define CMU_BASE (0x400C8000UL) /**< CMU base address */
<> 128:9bcdf88f62b0 338 #define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
<> 128:9bcdf88f62b0 339 #define EBI_BASE (0x40008000UL) /**< EBI base address */
<> 128:9bcdf88f62b0 340 #define USART0_BASE (0x4000C000UL) /**< USART0 base address */
<> 128:9bcdf88f62b0 341 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */
<> 128:9bcdf88f62b0 342 #define USART2_BASE (0x4000C800UL) /**< USART2 base address */
<> 128:9bcdf88f62b0 343 #define UART0_BASE (0x4000E000UL) /**< UART0 base address */
<> 128:9bcdf88f62b0 344 #define UART1_BASE (0x4000E400UL) /**< UART1 base address */
<> 128:9bcdf88f62b0 345 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
<> 128:9bcdf88f62b0 346 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
<> 128:9bcdf88f62b0 347 #define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
<> 128:9bcdf88f62b0 348 #define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
<> 128:9bcdf88f62b0 349 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
<> 128:9bcdf88f62b0 350 #define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
<> 128:9bcdf88f62b0 351 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
<> 128:9bcdf88f62b0 352 #define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
<> 128:9bcdf88f62b0 353 #define RTC_BASE (0x40080000UL) /**< RTC base address */
<> 128:9bcdf88f62b0 354 #define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
<> 128:9bcdf88f62b0 355 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
<> 128:9bcdf88f62b0 356 #define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
<> 128:9bcdf88f62b0 357 #define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
<> 128:9bcdf88f62b0 358 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
<> 128:9bcdf88f62b0 359 #define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
<> 128:9bcdf88f62b0 360 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */
<> 128:9bcdf88f62b0 361 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */
<> 128:9bcdf88f62b0 362 #define PRS_BASE (0x400CC000UL) /**< PRS base address */
<> 128:9bcdf88f62b0 363 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
<> 128:9bcdf88f62b0 364 #define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
<> 128:9bcdf88f62b0 365 #define LCD_BASE (0x4008A000UL) /**< LCD base address */
<> 128:9bcdf88f62b0 366 #define BURTC_BASE (0x40081000UL) /**< BURTC base address */
<> 128:9bcdf88f62b0 367 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */
<> 128:9bcdf88f62b0 368 #define ETM_BASE (0xE0041000UL) /**< ETM base address */
<> 128:9bcdf88f62b0 369 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
<> 128:9bcdf88f62b0 370 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
<> 128:9bcdf88f62b0 371 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
<> 128:9bcdf88f62b0 372 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
<> 128:9bcdf88f62b0 373 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
<> 128:9bcdf88f62b0 374
<> 128:9bcdf88f62b0 375 /** @} End of group EFM32LG980F64_Peripheral_Base */
<> 128:9bcdf88f62b0 376
<> 128:9bcdf88f62b0 377 /**************************************************************************//**
<> 128:9bcdf88f62b0 378 * @defgroup EFM32LG980F64_Peripheral_Declaration EFM32LG980F64 Peripheral Declarations
<> 128:9bcdf88f62b0 379 * @{
<> 128:9bcdf88f62b0 380 *****************************************************************************/
<> 128:9bcdf88f62b0 381
<> 128:9bcdf88f62b0 382 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
<> 128:9bcdf88f62b0 383 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
<> 128:9bcdf88f62b0 384 #define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
<> 128:9bcdf88f62b0 385 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
<> 128:9bcdf88f62b0 386 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
<> 128:9bcdf88f62b0 387 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
<> 128:9bcdf88f62b0 388 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
<> 128:9bcdf88f62b0 389 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
<> 128:9bcdf88f62b0 390 #define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
<> 128:9bcdf88f62b0 391 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
<> 128:9bcdf88f62b0 392 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
<> 128:9bcdf88f62b0 393 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
<> 128:9bcdf88f62b0 394 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
<> 128:9bcdf88f62b0 395 #define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
<> 128:9bcdf88f62b0 396 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
<> 128:9bcdf88f62b0 397 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
<> 128:9bcdf88f62b0 398 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
<> 128:9bcdf88f62b0 399 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
<> 128:9bcdf88f62b0 400 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
<> 128:9bcdf88f62b0 401 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
<> 128:9bcdf88f62b0 402 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
<> 128:9bcdf88f62b0 403 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
<> 128:9bcdf88f62b0 404 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
<> 128:9bcdf88f62b0 405 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
<> 128:9bcdf88f62b0 406 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
<> 128:9bcdf88f62b0 407 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
<> 128:9bcdf88f62b0 408 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
<> 128:9bcdf88f62b0 409 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
<> 128:9bcdf88f62b0 410 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
<> 128:9bcdf88f62b0 411 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
<> 128:9bcdf88f62b0 412 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
<> 128:9bcdf88f62b0 413 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
<> 128:9bcdf88f62b0 414 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
<> 128:9bcdf88f62b0 415 #define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
<> 128:9bcdf88f62b0 416 #define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
<> 128:9bcdf88f62b0 417 #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
<> 128:9bcdf88f62b0 418 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
<> 128:9bcdf88f62b0 419 #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
<> 128:9bcdf88f62b0 420 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
<> 128:9bcdf88f62b0 421 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
<> 128:9bcdf88f62b0 422 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
<> 128:9bcdf88f62b0 423
<> 128:9bcdf88f62b0 424 /** @} End of group EFM32LG980F64_Peripheral_Declaration */
<> 128:9bcdf88f62b0 425
<> 128:9bcdf88f62b0 426 /**************************************************************************//**
<> 128:9bcdf88f62b0 427 * @defgroup EFM32LG980F64_BitFields EFM32LG980F64 Bit Fields
<> 128:9bcdf88f62b0 428 * @{
<> 128:9bcdf88f62b0 429 *****************************************************************************/
<> 128:9bcdf88f62b0 430
<> 128:9bcdf88f62b0 431 #include "efm32lg_prs_signals.h"
<> 128:9bcdf88f62b0 432 #include "efm32lg_dmareq.h"
<> 128:9bcdf88f62b0 433 #include "efm32lg_dmactrl.h"
<> 128:9bcdf88f62b0 434 #include "efm32lg_uart.h"
<> 128:9bcdf88f62b0 435
<> 128:9bcdf88f62b0 436 /**************************************************************************//**
<> 128:9bcdf88f62b0 437 * @defgroup EFM32LG980F64_UNLOCK EFM32LG980F64 Unlock Codes
<> 128:9bcdf88f62b0 438 * @{
<> 128:9bcdf88f62b0 439 *****************************************************************************/
<> 128:9bcdf88f62b0 440 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
<> 128:9bcdf88f62b0 441 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
<> 128:9bcdf88f62b0 442 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
<> 128:9bcdf88f62b0 443 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
<> 128:9bcdf88f62b0 444 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
<> 128:9bcdf88f62b0 445 #define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
<> 128:9bcdf88f62b0 446
<> 128:9bcdf88f62b0 447 /** @} End of group EFM32LG980F64_UNLOCK */
<> 128:9bcdf88f62b0 448
<> 128:9bcdf88f62b0 449 /** @} End of group EFM32LG980F64_BitFields */
<> 128:9bcdf88f62b0 450
<> 128:9bcdf88f62b0 451 /**************************************************************************//**
<> 128:9bcdf88f62b0 452 * @defgroup EFM32LG980F64_Alternate_Function EFM32LG980F64 Alternate Function
<> 128:9bcdf88f62b0 453 * @{
<> 128:9bcdf88f62b0 454 *****************************************************************************/
<> 128:9bcdf88f62b0 455
<> 128:9bcdf88f62b0 456 #include "efm32lg_af_ports.h"
<> 128:9bcdf88f62b0 457 #include "efm32lg_af_pins.h"
<> 128:9bcdf88f62b0 458
<> 128:9bcdf88f62b0 459 /** @} End of group EFM32LG980F64_Alternate_Function */
<> 128:9bcdf88f62b0 460
<> 128:9bcdf88f62b0 461 /**************************************************************************//**
<> 128:9bcdf88f62b0 462 * @brief Set the value of a bit field within a register.
<> 128:9bcdf88f62b0 463 *
<> 128:9bcdf88f62b0 464 * @param REG
<> 128:9bcdf88f62b0 465 * The register to update
<> 128:9bcdf88f62b0 466 * @param MASK
<> 128:9bcdf88f62b0 467 * The mask for the bit field to update
<> 128:9bcdf88f62b0 468 * @param VALUE
<> 128:9bcdf88f62b0 469 * The value to write to the bit field
<> 128:9bcdf88f62b0 470 * @param OFFSET
<> 128:9bcdf88f62b0 471 * The number of bits that the field is offset within the register.
<> 128:9bcdf88f62b0 472 * 0 (zero) means LSB.
<> 128:9bcdf88f62b0 473 *****************************************************************************/
<> 128:9bcdf88f62b0 474 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
<> 128:9bcdf88f62b0 475 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
<> 128:9bcdf88f62b0 476
<> 128:9bcdf88f62b0 477 /** @} End of group EFM32LG980F64 */
<> 128:9bcdf88f62b0 478
<> 128:9bcdf88f62b0 479 /** @} End of group Parts */
<> 128:9bcdf88f62b0 480
<> 128:9bcdf88f62b0 481 #ifdef __cplusplus
<> 128:9bcdf88f62b0 482 }
<> 128:9bcdf88f62b0 483 #endif
<> 128:9bcdf88f62b0 484 #endif /* EFM32LG980F64_H */