mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32LG_STK3600/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg840f64.h@128:9bcdf88f62b0, 2016-10-27 (annotated)

Committer:
<>
Date:
Thu Oct 27 16:45:56 2016 +0100
Revision:
128:9bcdf88f62b0
Child:
139:856d2700e60b
Release 128 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



2966: Add kw24 support https://github.com/ARMmbed/mbed-os/pull/2966

3068: MultiTech mDot - clean up PeripheralPins.c and add new pin names https://github.com/ARMmbed/mbed-os/pull/3068

3089: Kinetis HAL: Remove clock initialization code from serial and ticker  https://github.com/ARMmbed/mbed-os/pull/3089

2943: [NRF5] NVIC_SetVector functionality https://github.com/ARMmbed/mbed-os/pull/2943

2938: InterruptIn changes in NCS36510 HAL. https://github.com/ARMmbed/mbed-os/pull/2938

3108: Fix sleep function for NRF52. https://github.com/ARMmbed/mbed-os/pull/3108

3076: STM32F1: Correct timer master value reading https://github.com/ARMmbed/mbed-os/pull/3076

3085: Add LOWPOWERTIMER capability for NUCLEO_F303ZE https://github.com/ARMmbed/mbed-os/pull/3085

3046: [BEETLE] Update BLE stack on Beetle board https://github.com/ARMmbed/mbed-os/pull/3046

3122: [Silicon Labs] Update of Silicon Labs HAL https://github.com/ARMmbed/mbed-os/pull/3122

3022: OnSemi RAM usage fix https://github.com/ARMmbed/mbed-os/pull/3022

3121: STM32F3: Correct UART4 and UART5 defines when using DEVICE_SERIAL_ASYNCH https://github.com/ARMmbed/mbed-os/pull/3121

3142: Targets- NUMAKER_PFM_NUC47216 remove mbed 2 https://github.com/ARMmbed/mbed-os/pull/3142

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**************************************************************************//**
<> 128:9bcdf88f62b0 2 * @file efm32lg840f64.h
<> 128:9bcdf88f62b0 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
<> 128:9bcdf88f62b0 4 * for EFM32LG840F64
<> 128:9bcdf88f62b0 5 * @version 5.0.0
<> 128:9bcdf88f62b0 6 ******************************************************************************
<> 128:9bcdf88f62b0 7 * @section License
<> 128:9bcdf88f62b0 8 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 128:9bcdf88f62b0 9 ******************************************************************************
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * Permission is granted to anyone to use this software for any purpose,
<> 128:9bcdf88f62b0 12 * including commercial applications, and to alter it and redistribute it
<> 128:9bcdf88f62b0 13 * freely, subject to the following restrictions:
<> 128:9bcdf88f62b0 14 *
<> 128:9bcdf88f62b0 15 * 1. The origin of this software must not be misrepresented; you must not
<> 128:9bcdf88f62b0 16 * claim that you wrote the original software.@n
<> 128:9bcdf88f62b0 17 * 2. Altered source versions must be plainly marked as such, and must not be
<> 128:9bcdf88f62b0 18 * misrepresented as being the original software.@n
<> 128:9bcdf88f62b0 19 * 3. This notice may not be removed or altered from any source distribution.
<> 128:9bcdf88f62b0 20 *
<> 128:9bcdf88f62b0 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 128:9bcdf88f62b0 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 128:9bcdf88f62b0 23 * providing the Software "AS IS", with no express or implied warranties of any
<> 128:9bcdf88f62b0 24 * kind, including, but not limited to, any implied warranties of
<> 128:9bcdf88f62b0 25 * merchantability or fitness for any particular purpose or warranties against
<> 128:9bcdf88f62b0 26 * infringement of any proprietary rights of a third party.
<> 128:9bcdf88f62b0 27 *
<> 128:9bcdf88f62b0 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 128:9bcdf88f62b0 29 * incidental, or special damages, or any other relief, or for any claim by
<> 128:9bcdf88f62b0 30 * any third party, arising from your use of this Software.
<> 128:9bcdf88f62b0 31 *
<> 128:9bcdf88f62b0 32 *****************************************************************************/
<> 128:9bcdf88f62b0 33
<> 128:9bcdf88f62b0 34 #ifndef EFM32LG840F64_H
<> 128:9bcdf88f62b0 35 #define EFM32LG840F64_H
<> 128:9bcdf88f62b0 36
<> 128:9bcdf88f62b0 37 #ifdef __cplusplus
<> 128:9bcdf88f62b0 38 extern "C" {
<> 128:9bcdf88f62b0 39 #endif
<> 128:9bcdf88f62b0 40
<> 128:9bcdf88f62b0 41 /**************************************************************************//**
<> 128:9bcdf88f62b0 42 * @addtogroup Parts
<> 128:9bcdf88f62b0 43 * @{
<> 128:9bcdf88f62b0 44 *****************************************************************************/
<> 128:9bcdf88f62b0 45
<> 128:9bcdf88f62b0 46 /**************************************************************************//**
<> 128:9bcdf88f62b0 47 * @defgroup EFM32LG840F64 EFM32LG840F64
<> 128:9bcdf88f62b0 48 * @{
<> 128:9bcdf88f62b0 49 *****************************************************************************/
<> 128:9bcdf88f62b0 50
<> 128:9bcdf88f62b0 51 /** Interrupt Number Definition */
<> 128:9bcdf88f62b0 52 typedef enum IRQn
<> 128:9bcdf88f62b0 53 {
<> 128:9bcdf88f62b0 54 /****** Cortex-M3 Processor Exceptions Numbers ********************************************/
<> 128:9bcdf88f62b0 55 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M3 Non Maskable Interrupt */
<> 128:9bcdf88f62b0 56 HardFault_IRQn = -13, /*!< -13 Cortex-M3 Hard Fault Interrupt */
<> 128:9bcdf88f62b0 57 MemoryManagement_IRQn = -12, /*!< -12 Cortex-M3 Memory Management Interrupt */
<> 128:9bcdf88f62b0 58 BusFault_IRQn = -11, /*!< -11 Cortex-M3 Bus Fault Interrupt */
<> 128:9bcdf88f62b0 59 UsageFault_IRQn = -10, /*!< -10 Cortex-M3 Usage Fault Interrupt */
<> 128:9bcdf88f62b0 60 SVCall_IRQn = -5, /*!< -5 Cortex-M3 SV Call Interrupt */
<> 128:9bcdf88f62b0 61 DebugMonitor_IRQn = -4, /*!< -4 Cortex-M3 Debug Monitor Interrupt */
<> 128:9bcdf88f62b0 62 PendSV_IRQn = -2, /*!< -2 Cortex-M3 Pend SV Interrupt */
<> 128:9bcdf88f62b0 63 SysTick_IRQn = -1, /*!< -1 Cortex-M3 System Tick Interrupt */
<> 128:9bcdf88f62b0 64
<> 128:9bcdf88f62b0 65 /****** EFM32LG Peripheral Interrupt Numbers **********************************************/
<> 128:9bcdf88f62b0 66
<> 128:9bcdf88f62b0 67 DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
<> 128:9bcdf88f62b0 68 GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
<> 128:9bcdf88f62b0 69 TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
<> 128:9bcdf88f62b0 70 USART0_RX_IRQn = 3, /*!< 3 EFM32 USART0_RX Interrupt */
<> 128:9bcdf88f62b0 71 USART0_TX_IRQn = 4, /*!< 4 EFM32 USART0_TX Interrupt */
<> 128:9bcdf88f62b0 72 ACMP0_IRQn = 6, /*!< 6 EFM32 ACMP0 Interrupt */
<> 128:9bcdf88f62b0 73 ADC0_IRQn = 7, /*!< 7 EFM32 ADC0 Interrupt */
<> 128:9bcdf88f62b0 74 DAC0_IRQn = 8, /*!< 8 EFM32 DAC0 Interrupt */
<> 128:9bcdf88f62b0 75 I2C0_IRQn = 9, /*!< 9 EFM32 I2C0 Interrupt */
<> 128:9bcdf88f62b0 76 I2C1_IRQn = 10, /*!< 10 EFM32 I2C1 Interrupt */
<> 128:9bcdf88f62b0 77 GPIO_ODD_IRQn = 11, /*!< 11 EFM32 GPIO_ODD Interrupt */
<> 128:9bcdf88f62b0 78 TIMER1_IRQn = 12, /*!< 12 EFM32 TIMER1 Interrupt */
<> 128:9bcdf88f62b0 79 TIMER2_IRQn = 13, /*!< 13 EFM32 TIMER2 Interrupt */
<> 128:9bcdf88f62b0 80 TIMER3_IRQn = 14, /*!< 14 EFM32 TIMER3 Interrupt */
<> 128:9bcdf88f62b0 81 USART1_RX_IRQn = 15, /*!< 15 EFM32 USART1_RX Interrupt */
<> 128:9bcdf88f62b0 82 USART1_TX_IRQn = 16, /*!< 16 EFM32 USART1_TX Interrupt */
<> 128:9bcdf88f62b0 83 LESENSE_IRQn = 17, /*!< 17 EFM32 LESENSE Interrupt */
<> 128:9bcdf88f62b0 84 USART2_RX_IRQn = 18, /*!< 18 EFM32 USART2_RX Interrupt */
<> 128:9bcdf88f62b0 85 USART2_TX_IRQn = 19, /*!< 19 EFM32 USART2_TX Interrupt */
<> 128:9bcdf88f62b0 86 LEUART0_IRQn = 24, /*!< 24 EFM32 LEUART0 Interrupt */
<> 128:9bcdf88f62b0 87 LEUART1_IRQn = 25, /*!< 25 EFM32 LEUART1 Interrupt */
<> 128:9bcdf88f62b0 88 LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
<> 128:9bcdf88f62b0 89 PCNT0_IRQn = 27, /*!< 27 EFM32 PCNT0 Interrupt */
<> 128:9bcdf88f62b0 90 PCNT1_IRQn = 28, /*!< 28 EFM32 PCNT1 Interrupt */
<> 128:9bcdf88f62b0 91 PCNT2_IRQn = 29, /*!< 29 EFM32 PCNT2 Interrupt */
<> 128:9bcdf88f62b0 92 RTC_IRQn = 30, /*!< 30 EFM32 RTC Interrupt */
<> 128:9bcdf88f62b0 93 BURTC_IRQn = 31, /*!< 31 EFM32 BURTC Interrupt */
<> 128:9bcdf88f62b0 94 CMU_IRQn = 32, /*!< 32 EFM32 CMU Interrupt */
<> 128:9bcdf88f62b0 95 VCMP_IRQn = 33, /*!< 33 EFM32 VCMP Interrupt */
<> 128:9bcdf88f62b0 96 LCD_IRQn = 34, /*!< 34 EFM32 LCD Interrupt */
<> 128:9bcdf88f62b0 97 MSC_IRQn = 35, /*!< 35 EFM32 MSC Interrupt */
<> 128:9bcdf88f62b0 98 AES_IRQn = 36, /*!< 36 EFM32 AES Interrupt */
<> 128:9bcdf88f62b0 99 EMU_IRQn = 38, /*!< 38 EFM32 EMU Interrupt */
<> 128:9bcdf88f62b0 100 } IRQn_Type;
<> 128:9bcdf88f62b0 101
<> 128:9bcdf88f62b0 102 /**************************************************************************//**
<> 128:9bcdf88f62b0 103 * @defgroup EFM32LG840F64_Core EFM32LG840F64 Core
<> 128:9bcdf88f62b0 104 * @{
<> 128:9bcdf88f62b0 105 * @brief Processor and Core Peripheral Section
<> 128:9bcdf88f62b0 106 *****************************************************************************/
<> 128:9bcdf88f62b0 107 #define __MPU_PRESENT 1 /**< Presence of MPU */
<> 128:9bcdf88f62b0 108 #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
<> 128:9bcdf88f62b0 109 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
<> 128:9bcdf88f62b0 110 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
<> 128:9bcdf88f62b0 111
<> 128:9bcdf88f62b0 112 /** @} End of group EFM32LG840F64_Core */
<> 128:9bcdf88f62b0 113
<> 128:9bcdf88f62b0 114 /**************************************************************************//**
<> 128:9bcdf88f62b0 115 * @defgroup EFM32LG840F64_Part EFM32LG840F64 Part
<> 128:9bcdf88f62b0 116 * @{
<> 128:9bcdf88f62b0 117 ******************************************************************************/
<> 128:9bcdf88f62b0 118
<> 128:9bcdf88f62b0 119 /** Part family */
<> 128:9bcdf88f62b0 120 #define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
<> 128:9bcdf88f62b0 121 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
<> 128:9bcdf88f62b0 122 #define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
<> 128:9bcdf88f62b0 123 #define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
<> 128:9bcdf88f62b0 124 #define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
<> 128:9bcdf88f62b0 125 #define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
<> 128:9bcdf88f62b0 126
<> 128:9bcdf88f62b0 127 /* If part number is not defined as compiler option, define it */
<> 128:9bcdf88f62b0 128 #if !defined(EFM32LG840F64)
<> 128:9bcdf88f62b0 129 #define EFM32LG840F64 1 /**< Giant/Leopard Gecko Part */
<> 128:9bcdf88f62b0 130 #endif
<> 128:9bcdf88f62b0 131
<> 128:9bcdf88f62b0 132 /** Configure part number */
<> 128:9bcdf88f62b0 133 #define PART_NUMBER "EFM32LG840F64" /**< Part Number */
<> 128:9bcdf88f62b0 134
<> 128:9bcdf88f62b0 135 /** Memory Base addresses and limits */
<> 128:9bcdf88f62b0 136 #define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
<> 128:9bcdf88f62b0 137 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
<> 128:9bcdf88f62b0 138 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
<> 128:9bcdf88f62b0 139 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
<> 128:9bcdf88f62b0 140 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
<> 128:9bcdf88f62b0 141 #define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
<> 128:9bcdf88f62b0 142 #define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
<> 128:9bcdf88f62b0 143 #define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
<> 128:9bcdf88f62b0 144 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
<> 128:9bcdf88f62b0 145 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
<> 128:9bcdf88f62b0 146 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
<> 128:9bcdf88f62b0 147 #define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
<> 128:9bcdf88f62b0 148 #define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
<> 128:9bcdf88f62b0 149 #define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
<> 128:9bcdf88f62b0 150 #define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
<> 128:9bcdf88f62b0 151 #define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
<> 128:9bcdf88f62b0 152 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
<> 128:9bcdf88f62b0 153 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
<> 128:9bcdf88f62b0 154 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
<> 128:9bcdf88f62b0 155 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
<> 128:9bcdf88f62b0 156 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
<> 128:9bcdf88f62b0 157 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
<> 128:9bcdf88f62b0 158 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
<> 128:9bcdf88f62b0 159 #define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
<> 128:9bcdf88f62b0 160 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
<> 128:9bcdf88f62b0 161 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
<> 128:9bcdf88f62b0 162 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
<> 128:9bcdf88f62b0 163 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
<> 128:9bcdf88f62b0 164 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
<> 128:9bcdf88f62b0 165 #define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
<> 128:9bcdf88f62b0 166 #define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
<> 128:9bcdf88f62b0 167 #define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
<> 128:9bcdf88f62b0 168
<> 128:9bcdf88f62b0 169 /** Bit banding area */
<> 128:9bcdf88f62b0 170 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
<> 128:9bcdf88f62b0 171 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
<> 128:9bcdf88f62b0 172
<> 128:9bcdf88f62b0 173 /** Flash and SRAM limits for EFM32LG840F64 */
<> 128:9bcdf88f62b0 174 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
<> 128:9bcdf88f62b0 175 #define FLASH_SIZE (0x00010000UL) /**< Available Flash Memory */
<> 128:9bcdf88f62b0 176 #define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
<> 128:9bcdf88f62b0 177 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
<> 128:9bcdf88f62b0 178 #define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
<> 128:9bcdf88f62b0 179 #define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
<> 128:9bcdf88f62b0 180 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
<> 128:9bcdf88f62b0 181 #define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
<> 128:9bcdf88f62b0 182 #define EXT_IRQ_COUNT 40 /**< Number of External (NVIC) interrupts */
<> 128:9bcdf88f62b0 183
<> 128:9bcdf88f62b0 184 /** AF channels connect the different on-chip peripherals with the af-mux */
<> 128:9bcdf88f62b0 185 #define AFCHAN_MAX 163
<> 128:9bcdf88f62b0 186 #define AFCHANLOC_MAX 7
<> 128:9bcdf88f62b0 187 /** Analog AF channels */
<> 128:9bcdf88f62b0 188 #define AFACHAN_MAX 53
<> 128:9bcdf88f62b0 189
<> 128:9bcdf88f62b0 190 /* Part number capabilities */
<> 128:9bcdf88f62b0 191
<> 128:9bcdf88f62b0 192 #define USART_PRESENT /**< USART is available in this part */
<> 128:9bcdf88f62b0 193 #define USART_COUNT 3 /**< 3 USARTs available */
<> 128:9bcdf88f62b0 194 #define TIMER_PRESENT /**< TIMER is available in this part */
<> 128:9bcdf88f62b0 195 #define TIMER_COUNT 4 /**< 4 TIMERs available */
<> 128:9bcdf88f62b0 196 #define ACMP_PRESENT /**< ACMP is available in this part */
<> 128:9bcdf88f62b0 197 #define ACMP_COUNT 2 /**< 2 ACMPs available */
<> 128:9bcdf88f62b0 198 #define LEUART_PRESENT /**< LEUART is available in this part */
<> 128:9bcdf88f62b0 199 #define LEUART_COUNT 2 /**< 2 LEUARTs available */
<> 128:9bcdf88f62b0 200 #define LETIMER_PRESENT /**< LETIMER is available in this part */
<> 128:9bcdf88f62b0 201 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */
<> 128:9bcdf88f62b0 202 #define PCNT_PRESENT /**< PCNT is available in this part */
<> 128:9bcdf88f62b0 203 #define PCNT_COUNT 3 /**< 3 PCNTs available */
<> 128:9bcdf88f62b0 204 #define I2C_PRESENT /**< I2C is available in this part */
<> 128:9bcdf88f62b0 205 #define I2C_COUNT 2 /**< 2 I2Cs available */
<> 128:9bcdf88f62b0 206 #define ADC_PRESENT /**< ADC is available in this part */
<> 128:9bcdf88f62b0 207 #define ADC_COUNT 1 /**< 1 ADCs available */
<> 128:9bcdf88f62b0 208 #define DAC_PRESENT /**< DAC is available in this part */
<> 128:9bcdf88f62b0 209 #define DAC_COUNT 1 /**< 1 DACs available */
<> 128:9bcdf88f62b0 210 #define DMA_PRESENT
<> 128:9bcdf88f62b0 211 #define DMA_COUNT 1
<> 128:9bcdf88f62b0 212 #define AES_PRESENT
<> 128:9bcdf88f62b0 213 #define AES_COUNT 1
<> 128:9bcdf88f62b0 214 #define LE_PRESENT
<> 128:9bcdf88f62b0 215 #define LE_COUNT 1
<> 128:9bcdf88f62b0 216 #define MSC_PRESENT
<> 128:9bcdf88f62b0 217 #define MSC_COUNT 1
<> 128:9bcdf88f62b0 218 #define EMU_PRESENT
<> 128:9bcdf88f62b0 219 #define EMU_COUNT 1
<> 128:9bcdf88f62b0 220 #define RMU_PRESENT
<> 128:9bcdf88f62b0 221 #define RMU_COUNT 1
<> 128:9bcdf88f62b0 222 #define CMU_PRESENT
<> 128:9bcdf88f62b0 223 #define CMU_COUNT 1
<> 128:9bcdf88f62b0 224 #define LESENSE_PRESENT
<> 128:9bcdf88f62b0 225 #define LESENSE_COUNT 1
<> 128:9bcdf88f62b0 226 #define RTC_PRESENT
<> 128:9bcdf88f62b0 227 #define RTC_COUNT 1
<> 128:9bcdf88f62b0 228 #define GPIO_PRESENT
<> 128:9bcdf88f62b0 229 #define GPIO_COUNT 1
<> 128:9bcdf88f62b0 230 #define VCMP_PRESENT
<> 128:9bcdf88f62b0 231 #define VCMP_COUNT 1
<> 128:9bcdf88f62b0 232 #define PRS_PRESENT
<> 128:9bcdf88f62b0 233 #define PRS_COUNT 1
<> 128:9bcdf88f62b0 234 #define OPAMP_PRESENT
<> 128:9bcdf88f62b0 235 #define OPAMP_COUNT 1
<> 128:9bcdf88f62b0 236 #define BU_PRESENT
<> 128:9bcdf88f62b0 237 #define BU_COUNT 1
<> 128:9bcdf88f62b0 238 #define LCD_PRESENT
<> 128:9bcdf88f62b0 239 #define LCD_COUNT 1
<> 128:9bcdf88f62b0 240 #define BURTC_PRESENT
<> 128:9bcdf88f62b0 241 #define BURTC_COUNT 1
<> 128:9bcdf88f62b0 242 #define HFXTAL_PRESENT
<> 128:9bcdf88f62b0 243 #define HFXTAL_COUNT 1
<> 128:9bcdf88f62b0 244 #define LFXTAL_PRESENT
<> 128:9bcdf88f62b0 245 #define LFXTAL_COUNT 1
<> 128:9bcdf88f62b0 246 #define WDOG_PRESENT
<> 128:9bcdf88f62b0 247 #define WDOG_COUNT 1
<> 128:9bcdf88f62b0 248 #define DBG_PRESENT
<> 128:9bcdf88f62b0 249 #define DBG_COUNT 1
<> 128:9bcdf88f62b0 250 #define ETM_PRESENT
<> 128:9bcdf88f62b0 251 #define ETM_COUNT 1
<> 128:9bcdf88f62b0 252 #define BOOTLOADER_PRESENT
<> 128:9bcdf88f62b0 253 #define BOOTLOADER_COUNT 1
<> 128:9bcdf88f62b0 254 #define ANALOG_PRESENT
<> 128:9bcdf88f62b0 255 #define ANALOG_COUNT 1
<> 128:9bcdf88f62b0 256
<> 128:9bcdf88f62b0 257 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
<> 128:9bcdf88f62b0 258 #include "system_efm32lg.h" /* System Header */
<> 128:9bcdf88f62b0 259
<> 128:9bcdf88f62b0 260 /** @} End of group EFM32LG840F64_Part */
<> 128:9bcdf88f62b0 261
<> 128:9bcdf88f62b0 262 /**************************************************************************//**
<> 128:9bcdf88f62b0 263 * @defgroup EFM32LG840F64_Peripheral_TypeDefs EFM32LG840F64 Peripheral TypeDefs
<> 128:9bcdf88f62b0 264 * @{
<> 128:9bcdf88f62b0 265 * @brief Device Specific Peripheral Register Structures
<> 128:9bcdf88f62b0 266 *****************************************************************************/
<> 128:9bcdf88f62b0 267
<> 128:9bcdf88f62b0 268 #include "efm32lg_dma_ch.h"
<> 128:9bcdf88f62b0 269
<> 128:9bcdf88f62b0 270 /**************************************************************************//**
<> 128:9bcdf88f62b0 271 * @defgroup EFM32LG840F64_DMA EFM32LG840F64 DMA
<> 128:9bcdf88f62b0 272 * @{
<> 128:9bcdf88f62b0 273 * @brief EFM32LG840F64_DMA Register Declaration
<> 128:9bcdf88f62b0 274 *****************************************************************************/
<> 128:9bcdf88f62b0 275 typedef struct
<> 128:9bcdf88f62b0 276 {
<> 128:9bcdf88f62b0 277 __IM uint32_t STATUS; /**< DMA Status Registers */
<> 128:9bcdf88f62b0 278 __OM uint32_t CONFIG; /**< DMA Configuration Register */
<> 128:9bcdf88f62b0 279 __IOM uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */
<> 128:9bcdf88f62b0 280 __IM uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */
<> 128:9bcdf88f62b0 281 __IM uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */
<> 128:9bcdf88f62b0 282 __OM uint32_t CHSWREQ; /**< Channel Software Request Register */
<> 128:9bcdf88f62b0 283 __IOM uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */
<> 128:9bcdf88f62b0 284 __OM uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */
<> 128:9bcdf88f62b0 285 __IOM uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */
<> 128:9bcdf88f62b0 286 __OM uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */
<> 128:9bcdf88f62b0 287 __IOM uint32_t CHENS; /**< Channel Enable Set Register */
<> 128:9bcdf88f62b0 288 __OM uint32_t CHENC; /**< Channel Enable Clear Register */
<> 128:9bcdf88f62b0 289 __IOM uint32_t CHALTS; /**< Channel Alternate Set Register */
<> 128:9bcdf88f62b0 290 __OM uint32_t CHALTC; /**< Channel Alternate Clear Register */
<> 128:9bcdf88f62b0 291 __IOM uint32_t CHPRIS; /**< Channel Priority Set Register */
<> 128:9bcdf88f62b0 292 __OM uint32_t CHPRIC; /**< Channel Priority Clear Register */
<> 128:9bcdf88f62b0 293 uint32_t RESERVED0[3]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 294 __IOM uint32_t ERRORC; /**< Bus Error Clear Register */
<> 128:9bcdf88f62b0 295
<> 128:9bcdf88f62b0 296 uint32_t RESERVED1[880]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 297 __IM uint32_t CHREQSTATUS; /**< Channel Request Status */
<> 128:9bcdf88f62b0 298 uint32_t RESERVED2[1]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 299 __IM uint32_t CHSREQSTATUS; /**< Channel Single Request Status */
<> 128:9bcdf88f62b0 300
<> 128:9bcdf88f62b0 301 uint32_t RESERVED3[121]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 302 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 128:9bcdf88f62b0 303 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 128:9bcdf88f62b0 304 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 128:9bcdf88f62b0 305 __IOM uint32_t IEN; /**< Interrupt Enable register */
<> 128:9bcdf88f62b0 306 __IOM uint32_t CTRL; /**< DMA Control Register */
<> 128:9bcdf88f62b0 307 __IOM uint32_t RDS; /**< DMA Retain Descriptor State */
<> 128:9bcdf88f62b0 308
<> 128:9bcdf88f62b0 309 uint32_t RESERVED4[2]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 310 __IOM uint32_t LOOP0; /**< Channel 0 Loop Register */
<> 128:9bcdf88f62b0 311 __IOM uint32_t LOOP1; /**< Channel 1 Loop Register */
<> 128:9bcdf88f62b0 312 uint32_t RESERVED5[14]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 313 __IOM uint32_t RECT0; /**< Channel 0 Rectangle Register */
<> 128:9bcdf88f62b0 314
<> 128:9bcdf88f62b0 315 uint32_t RESERVED6[39]; /**< Reserved registers */
<> 128:9bcdf88f62b0 316 DMA_CH_TypeDef CH[12]; /**< Channel registers */
<> 128:9bcdf88f62b0 317 } DMA_TypeDef; /** @} */
<> 128:9bcdf88f62b0 318
<> 128:9bcdf88f62b0 319 #include "efm32lg_aes.h"
<> 128:9bcdf88f62b0 320 #include "efm32lg_msc.h"
<> 128:9bcdf88f62b0 321 #include "efm32lg_emu.h"
<> 128:9bcdf88f62b0 322 #include "efm32lg_rmu.h"
<> 128:9bcdf88f62b0 323
<> 128:9bcdf88f62b0 324 /**************************************************************************//**
<> 128:9bcdf88f62b0 325 * @defgroup EFM32LG840F64_CMU EFM32LG840F64 CMU
<> 128:9bcdf88f62b0 326 * @{
<> 128:9bcdf88f62b0 327 * @brief EFM32LG840F64_CMU Register Declaration
<> 128:9bcdf88f62b0 328 *****************************************************************************/
<> 128:9bcdf88f62b0 329 typedef struct
<> 128:9bcdf88f62b0 330 {
<> 128:9bcdf88f62b0 331 __IOM uint32_t CTRL; /**< CMU Control Register */
<> 128:9bcdf88f62b0 332 __IOM uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */
<> 128:9bcdf88f62b0 333 __IOM uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */
<> 128:9bcdf88f62b0 334 __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */
<> 128:9bcdf88f62b0 335 __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */
<> 128:9bcdf88f62b0 336 __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */
<> 128:9bcdf88f62b0 337 __IOM uint32_t CALCTRL; /**< Calibration Control Register */
<> 128:9bcdf88f62b0 338 __IOM uint32_t CALCNT; /**< Calibration Counter Register */
<> 128:9bcdf88f62b0 339 __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */
<> 128:9bcdf88f62b0 340 __IOM uint32_t CMD; /**< Command Register */
<> 128:9bcdf88f62b0 341 __IOM uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */
<> 128:9bcdf88f62b0 342 __IM uint32_t STATUS; /**< Status Register */
<> 128:9bcdf88f62b0 343 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 128:9bcdf88f62b0 344 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 128:9bcdf88f62b0 345 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 128:9bcdf88f62b0 346 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 128:9bcdf88f62b0 347 __IOM uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */
<> 128:9bcdf88f62b0 348 __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */
<> 128:9bcdf88f62b0 349 uint32_t RESERVED0[2]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 350 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
<> 128:9bcdf88f62b0 351 __IOM uint32_t FREEZE; /**< Freeze Register */
<> 128:9bcdf88f62b0 352 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */
<> 128:9bcdf88f62b0 353 uint32_t RESERVED1[1]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 354 __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */
<> 128:9bcdf88f62b0 355
<> 128:9bcdf88f62b0 356 uint32_t RESERVED2[1]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 357 __IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */
<> 128:9bcdf88f62b0 358 uint32_t RESERVED3[1]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 359 __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */
<> 128:9bcdf88f62b0 360 uint32_t RESERVED4[1]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 361 __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */
<> 128:9bcdf88f62b0 362 __IOM uint32_t LCDCTRL; /**< LCD Control Register */
<> 128:9bcdf88f62b0 363 __IOM uint32_t ROUTE; /**< I/O Routing Register */
<> 128:9bcdf88f62b0 364 __IOM uint32_t LOCK; /**< Configuration Lock Register */
<> 128:9bcdf88f62b0 365 } CMU_TypeDef; /** @} */
<> 128:9bcdf88f62b0 366
<> 128:9bcdf88f62b0 367 #include "efm32lg_lesense_st.h"
<> 128:9bcdf88f62b0 368 #include "efm32lg_lesense_buf.h"
<> 128:9bcdf88f62b0 369 #include "efm32lg_lesense_ch.h"
<> 128:9bcdf88f62b0 370 #include "efm32lg_lesense.h"
<> 128:9bcdf88f62b0 371 #include "efm32lg_usart.h"
<> 128:9bcdf88f62b0 372 #include "efm32lg_timer_cc.h"
<> 128:9bcdf88f62b0 373 #include "efm32lg_timer.h"
<> 128:9bcdf88f62b0 374 #include "efm32lg_acmp.h"
<> 128:9bcdf88f62b0 375 #include "efm32lg_leuart.h"
<> 128:9bcdf88f62b0 376 #include "efm32lg_rtc.h"
<> 128:9bcdf88f62b0 377 #include "efm32lg_letimer.h"
<> 128:9bcdf88f62b0 378 #include "efm32lg_pcnt.h"
<> 128:9bcdf88f62b0 379 #include "efm32lg_i2c.h"
<> 128:9bcdf88f62b0 380 #include "efm32lg_gpio_p.h"
<> 128:9bcdf88f62b0 381 #include "efm32lg_gpio.h"
<> 128:9bcdf88f62b0 382 #include "efm32lg_vcmp.h"
<> 128:9bcdf88f62b0 383 #include "efm32lg_prs_ch.h"
<> 128:9bcdf88f62b0 384
<> 128:9bcdf88f62b0 385 /**************************************************************************//**
<> 128:9bcdf88f62b0 386 * @defgroup EFM32LG840F64_PRS EFM32LG840F64 PRS
<> 128:9bcdf88f62b0 387 * @{
<> 128:9bcdf88f62b0 388 * @brief EFM32LG840F64_PRS Register Declaration
<> 128:9bcdf88f62b0 389 *****************************************************************************/
<> 128:9bcdf88f62b0 390 typedef struct
<> 128:9bcdf88f62b0 391 {
<> 128:9bcdf88f62b0 392 __IOM uint32_t SWPULSE; /**< Software Pulse Register */
<> 128:9bcdf88f62b0 393 __IOM uint32_t SWLEVEL; /**< Software Level Register */
<> 128:9bcdf88f62b0 394 __IOM uint32_t ROUTE; /**< I/O Routing Register */
<> 128:9bcdf88f62b0 395
<> 128:9bcdf88f62b0 396 uint32_t RESERVED0[1]; /**< Reserved registers */
<> 128:9bcdf88f62b0 397 PRS_CH_TypeDef CH[12]; /**< Channel registers */
<> 128:9bcdf88f62b0 398 } PRS_TypeDef; /** @} */
<> 128:9bcdf88f62b0 399
<> 128:9bcdf88f62b0 400 #include "efm32lg_adc.h"
<> 128:9bcdf88f62b0 401 #include "efm32lg_dac.h"
<> 128:9bcdf88f62b0 402 #include "efm32lg_lcd.h"
<> 128:9bcdf88f62b0 403 #include "efm32lg_burtc_ret.h"
<> 128:9bcdf88f62b0 404 #include "efm32lg_burtc.h"
<> 128:9bcdf88f62b0 405 #include "efm32lg_wdog.h"
<> 128:9bcdf88f62b0 406 #include "efm32lg_etm.h"
<> 128:9bcdf88f62b0 407 #include "efm32lg_dma_descriptor.h"
<> 128:9bcdf88f62b0 408 #include "efm32lg_devinfo.h"
<> 128:9bcdf88f62b0 409 #include "efm32lg_romtable.h"
<> 128:9bcdf88f62b0 410 #include "efm32lg_calibrate.h"
<> 128:9bcdf88f62b0 411
<> 128:9bcdf88f62b0 412 /** @} End of group EFM32LG840F64_Peripheral_TypeDefs */
<> 128:9bcdf88f62b0 413
<> 128:9bcdf88f62b0 414 /**************************************************************************//**
<> 128:9bcdf88f62b0 415 * @defgroup EFM32LG840F64_Peripheral_Base EFM32LG840F64 Peripheral Memory Map
<> 128:9bcdf88f62b0 416 * @{
<> 128:9bcdf88f62b0 417 *****************************************************************************/
<> 128:9bcdf88f62b0 418
<> 128:9bcdf88f62b0 419 #define DMA_BASE (0x400C2000UL) /**< DMA base address */
<> 128:9bcdf88f62b0 420 #define AES_BASE (0x400E0000UL) /**< AES base address */
<> 128:9bcdf88f62b0 421 #define MSC_BASE (0x400C0000UL) /**< MSC base address */
<> 128:9bcdf88f62b0 422 #define EMU_BASE (0x400C6000UL) /**< EMU base address */
<> 128:9bcdf88f62b0 423 #define RMU_BASE (0x400CA000UL) /**< RMU base address */
<> 128:9bcdf88f62b0 424 #define CMU_BASE (0x400C8000UL) /**< CMU base address */
<> 128:9bcdf88f62b0 425 #define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
<> 128:9bcdf88f62b0 426 #define USART0_BASE (0x4000C000UL) /**< USART0 base address */
<> 128:9bcdf88f62b0 427 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */
<> 128:9bcdf88f62b0 428 #define USART2_BASE (0x4000C800UL) /**< USART2 base address */
<> 128:9bcdf88f62b0 429 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
<> 128:9bcdf88f62b0 430 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
<> 128:9bcdf88f62b0 431 #define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
<> 128:9bcdf88f62b0 432 #define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
<> 128:9bcdf88f62b0 433 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
<> 128:9bcdf88f62b0 434 #define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
<> 128:9bcdf88f62b0 435 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
<> 128:9bcdf88f62b0 436 #define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
<> 128:9bcdf88f62b0 437 #define RTC_BASE (0x40080000UL) /**< RTC base address */
<> 128:9bcdf88f62b0 438 #define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
<> 128:9bcdf88f62b0 439 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
<> 128:9bcdf88f62b0 440 #define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
<> 128:9bcdf88f62b0 441 #define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
<> 128:9bcdf88f62b0 442 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
<> 128:9bcdf88f62b0 443 #define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
<> 128:9bcdf88f62b0 444 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */
<> 128:9bcdf88f62b0 445 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */
<> 128:9bcdf88f62b0 446 #define PRS_BASE (0x400CC000UL) /**< PRS base address */
<> 128:9bcdf88f62b0 447 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
<> 128:9bcdf88f62b0 448 #define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
<> 128:9bcdf88f62b0 449 #define LCD_BASE (0x4008A000UL) /**< LCD base address */
<> 128:9bcdf88f62b0 450 #define BURTC_BASE (0x40081000UL) /**< BURTC base address */
<> 128:9bcdf88f62b0 451 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */
<> 128:9bcdf88f62b0 452 #define ETM_BASE (0xE0041000UL) /**< ETM base address */
<> 128:9bcdf88f62b0 453 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
<> 128:9bcdf88f62b0 454 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
<> 128:9bcdf88f62b0 455 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
<> 128:9bcdf88f62b0 456 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
<> 128:9bcdf88f62b0 457 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
<> 128:9bcdf88f62b0 458
<> 128:9bcdf88f62b0 459 /** @} End of group EFM32LG840F64_Peripheral_Base */
<> 128:9bcdf88f62b0 460
<> 128:9bcdf88f62b0 461 /**************************************************************************//**
<> 128:9bcdf88f62b0 462 * @defgroup EFM32LG840F64_Peripheral_Declaration EFM32LG840F64 Peripheral Declarations
<> 128:9bcdf88f62b0 463 * @{
<> 128:9bcdf88f62b0 464 *****************************************************************************/
<> 128:9bcdf88f62b0 465
<> 128:9bcdf88f62b0 466 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
<> 128:9bcdf88f62b0 467 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
<> 128:9bcdf88f62b0 468 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
<> 128:9bcdf88f62b0 469 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
<> 128:9bcdf88f62b0 470 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
<> 128:9bcdf88f62b0 471 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
<> 128:9bcdf88f62b0 472 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
<> 128:9bcdf88f62b0 473 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
<> 128:9bcdf88f62b0 474 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
<> 128:9bcdf88f62b0 475 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
<> 128:9bcdf88f62b0 476 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
<> 128:9bcdf88f62b0 477 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
<> 128:9bcdf88f62b0 478 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
<> 128:9bcdf88f62b0 479 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
<> 128:9bcdf88f62b0 480 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
<> 128:9bcdf88f62b0 481 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
<> 128:9bcdf88f62b0 482 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
<> 128:9bcdf88f62b0 483 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
<> 128:9bcdf88f62b0 484 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
<> 128:9bcdf88f62b0 485 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
<> 128:9bcdf88f62b0 486 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
<> 128:9bcdf88f62b0 487 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
<> 128:9bcdf88f62b0 488 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
<> 128:9bcdf88f62b0 489 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
<> 128:9bcdf88f62b0 490 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
<> 128:9bcdf88f62b0 491 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
<> 128:9bcdf88f62b0 492 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
<> 128:9bcdf88f62b0 493 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
<> 128:9bcdf88f62b0 494 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
<> 128:9bcdf88f62b0 495 #define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
<> 128:9bcdf88f62b0 496 #define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
<> 128:9bcdf88f62b0 497 #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
<> 128:9bcdf88f62b0 498 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
<> 128:9bcdf88f62b0 499 #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
<> 128:9bcdf88f62b0 500 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
<> 128:9bcdf88f62b0 501 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
<> 128:9bcdf88f62b0 502 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
<> 128:9bcdf88f62b0 503
<> 128:9bcdf88f62b0 504 /** @} End of group EFM32LG840F64_Peripheral_Declaration */
<> 128:9bcdf88f62b0 505
<> 128:9bcdf88f62b0 506 /**************************************************************************//**
<> 128:9bcdf88f62b0 507 * @defgroup EFM32LG840F64_BitFields EFM32LG840F64 Bit Fields
<> 128:9bcdf88f62b0 508 * @{
<> 128:9bcdf88f62b0 509 *****************************************************************************/
<> 128:9bcdf88f62b0 510
<> 128:9bcdf88f62b0 511 /**************************************************************************//**
<> 128:9bcdf88f62b0 512 * @addtogroup EFM32LG840F64_PRS_Signals
<> 128:9bcdf88f62b0 513 * @{
<> 128:9bcdf88f62b0 514 * @brief PRS Signal names
<> 128:9bcdf88f62b0 515 *****************************************************************************/
<> 128:9bcdf88f62b0 516 #define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */
<> 128:9bcdf88f62b0 517 #define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */
<> 128:9bcdf88f62b0 518 #define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */
<> 128:9bcdf88f62b0 519 #define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */
<> 128:9bcdf88f62b0 520 #define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */
<> 128:9bcdf88f62b0 521 #define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */
<> 128:9bcdf88f62b0 522 #define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */
<> 128:9bcdf88f62b0 523 #define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */
<> 128:9bcdf88f62b0 524 #define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */
<> 128:9bcdf88f62b0 525 #define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */
<> 128:9bcdf88f62b0 526 #define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */
<> 128:9bcdf88f62b0 527 #define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */
<> 128:9bcdf88f62b0 528 #define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */
<> 128:9bcdf88f62b0 529 #define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */
<> 128:9bcdf88f62b0 530 #define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */
<> 128:9bcdf88f62b0 531 #define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */
<> 128:9bcdf88f62b0 532 #define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */
<> 128:9bcdf88f62b0 533 #define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */
<> 128:9bcdf88f62b0 534 #define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */
<> 128:9bcdf88f62b0 535 #define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */
<> 128:9bcdf88f62b0 536 #define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */
<> 128:9bcdf88f62b0 537 #define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */
<> 128:9bcdf88f62b0 538 #define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */
<> 128:9bcdf88f62b0 539 #define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */
<> 128:9bcdf88f62b0 540 #define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */
<> 128:9bcdf88f62b0 541 #define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */
<> 128:9bcdf88f62b0 542 #define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */
<> 128:9bcdf88f62b0 543 #define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */
<> 128:9bcdf88f62b0 544 #define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */
<> 128:9bcdf88f62b0 545 #define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */
<> 128:9bcdf88f62b0 546 #define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */
<> 128:9bcdf88f62b0 547 #define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */
<> 128:9bcdf88f62b0 548 #define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */
<> 128:9bcdf88f62b0 549 #define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */
<> 128:9bcdf88f62b0 550 #define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */
<> 128:9bcdf88f62b0 551 #define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */
<> 128:9bcdf88f62b0 552 #define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */
<> 128:9bcdf88f62b0 553 #define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */
<> 128:9bcdf88f62b0 554 #define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */
<> 128:9bcdf88f62b0 555 #define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */
<> 128:9bcdf88f62b0 556 #define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */
<> 128:9bcdf88f62b0 557 #define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */
<> 128:9bcdf88f62b0 558 #define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */
<> 128:9bcdf88f62b0 559 #define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */
<> 128:9bcdf88f62b0 560 #define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */
<> 128:9bcdf88f62b0 561 #define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */
<> 128:9bcdf88f62b0 562 #define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */
<> 128:9bcdf88f62b0 563 #define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */
<> 128:9bcdf88f62b0 564 #define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */
<> 128:9bcdf88f62b0 565 #define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */
<> 128:9bcdf88f62b0 566 #define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */
<> 128:9bcdf88f62b0 567 #define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */
<> 128:9bcdf88f62b0 568 #define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */
<> 128:9bcdf88f62b0 569 #define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */
<> 128:9bcdf88f62b0 570 #define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */
<> 128:9bcdf88f62b0 571 #define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */
<> 128:9bcdf88f62b0 572 #define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */
<> 128:9bcdf88f62b0 573 #define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */
<> 128:9bcdf88f62b0 574 #define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */
<> 128:9bcdf88f62b0 575 #define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */
<> 128:9bcdf88f62b0 576 #define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */
<> 128:9bcdf88f62b0 577 #define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */
<> 128:9bcdf88f62b0 578 #define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */
<> 128:9bcdf88f62b0 579 #define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */
<> 128:9bcdf88f62b0 580 #define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */
<> 128:9bcdf88f62b0 581 #define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */
<> 128:9bcdf88f62b0 582 #define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */
<> 128:9bcdf88f62b0 583 #define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */
<> 128:9bcdf88f62b0 584 #define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */
<> 128:9bcdf88f62b0 585 #define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */
<> 128:9bcdf88f62b0 586 #define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */
<> 128:9bcdf88f62b0 587 #define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */
<> 128:9bcdf88f62b0 588 #define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */
<> 128:9bcdf88f62b0 589 #define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */
<> 128:9bcdf88f62b0 590 #define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */
<> 128:9bcdf88f62b0 591 #define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */
<> 128:9bcdf88f62b0 592
<> 128:9bcdf88f62b0 593 /** @} End of group EFM32LG840F64_PRS */
<> 128:9bcdf88f62b0 594
<> 128:9bcdf88f62b0 595 #include "efm32lg_dmareq.h"
<> 128:9bcdf88f62b0 596 #include "efm32lg_dmactrl.h"
<> 128:9bcdf88f62b0 597
<> 128:9bcdf88f62b0 598 /**************************************************************************//**
<> 128:9bcdf88f62b0 599 * @defgroup EFM32LG840F64_DMA_BitFields EFM32LG840F64_DMA Bit Fields
<> 128:9bcdf88f62b0 600 * @{
<> 128:9bcdf88f62b0 601 *****************************************************************************/
<> 128:9bcdf88f62b0 602
<> 128:9bcdf88f62b0 603 /* Bit fields for DMA STATUS */
<> 128:9bcdf88f62b0 604 #define _DMA_STATUS_RESETVALUE 0x100B0000UL /**< Default value for DMA_STATUS */
<> 128:9bcdf88f62b0 605 #define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */
<> 128:9bcdf88f62b0 606 #define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */
<> 128:9bcdf88f62b0 607 #define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */
<> 128:9bcdf88f62b0 608 #define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */
<> 128:9bcdf88f62b0 609 #define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */
<> 128:9bcdf88f62b0 610 #define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */
<> 128:9bcdf88f62b0 611 #define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */
<> 128:9bcdf88f62b0 612 #define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */
<> 128:9bcdf88f62b0 613 #define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */
<> 128:9bcdf88f62b0 614 #define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */
<> 128:9bcdf88f62b0 615 #define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */
<> 128:9bcdf88f62b0 616 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */
<> 128:9bcdf88f62b0 617 #define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */
<> 128:9bcdf88f62b0 618 #define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */
<> 128:9bcdf88f62b0 619 #define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */
<> 128:9bcdf88f62b0 620 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */
<> 128:9bcdf88f62b0 621 #define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */
<> 128:9bcdf88f62b0 622 #define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */
<> 128:9bcdf88f62b0 623 #define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */
<> 128:9bcdf88f62b0 624 #define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */
<> 128:9bcdf88f62b0 625 #define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */
<> 128:9bcdf88f62b0 626 #define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */
<> 128:9bcdf88f62b0 627 #define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */
<> 128:9bcdf88f62b0 628 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */
<> 128:9bcdf88f62b0 629 #define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */
<> 128:9bcdf88f62b0 630 #define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */
<> 128:9bcdf88f62b0 631 #define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */
<> 128:9bcdf88f62b0 632 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */
<> 128:9bcdf88f62b0 633 #define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */
<> 128:9bcdf88f62b0 634 #define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */
<> 128:9bcdf88f62b0 635 #define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */
<> 128:9bcdf88f62b0 636 #define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */
<> 128:9bcdf88f62b0 637 #define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */
<> 128:9bcdf88f62b0 638 #define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */
<> 128:9bcdf88f62b0 639 #define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DMA_STATUS */
<> 128:9bcdf88f62b0 640 #define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */
<> 128:9bcdf88f62b0 641
<> 128:9bcdf88f62b0 642 /* Bit fields for DMA CONFIG */
<> 128:9bcdf88f62b0 643 #define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */
<> 128:9bcdf88f62b0 644 #define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */
<> 128:9bcdf88f62b0 645 #define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */
<> 128:9bcdf88f62b0 646 #define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */
<> 128:9bcdf88f62b0 647 #define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */
<> 128:9bcdf88f62b0 648 #define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */
<> 128:9bcdf88f62b0 649 #define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */
<> 128:9bcdf88f62b0 650 #define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */
<> 128:9bcdf88f62b0 651 #define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */
<> 128:9bcdf88f62b0 652 #define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */
<> 128:9bcdf88f62b0 653 #define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */
<> 128:9bcdf88f62b0 654 #define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */
<> 128:9bcdf88f62b0 655
<> 128:9bcdf88f62b0 656 /* Bit fields for DMA CTRLBASE */
<> 128:9bcdf88f62b0 657 #define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */
<> 128:9bcdf88f62b0 658 #define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */
<> 128:9bcdf88f62b0 659 #define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */
<> 128:9bcdf88f62b0 660 #define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */
<> 128:9bcdf88f62b0 661 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */
<> 128:9bcdf88f62b0 662 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */
<> 128:9bcdf88f62b0 663
<> 128:9bcdf88f62b0 664 /* Bit fields for DMA ALTCTRLBASE */
<> 128:9bcdf88f62b0 665 #define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL /**< Default value for DMA_ALTCTRLBASE */
<> 128:9bcdf88f62b0 666 #define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */
<> 128:9bcdf88f62b0 667 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */
<> 128:9bcdf88f62b0 668 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */
<> 128:9bcdf88f62b0 669 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */
<> 128:9bcdf88f62b0 670 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */
<> 128:9bcdf88f62b0 671
<> 128:9bcdf88f62b0 672 /* Bit fields for DMA CHWAITSTATUS */
<> 128:9bcdf88f62b0 673 #define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL /**< Default value for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 674 #define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 675 #define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */
<> 128:9bcdf88f62b0 676 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */
<> 128:9bcdf88f62b0 677 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */
<> 128:9bcdf88f62b0 678 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 679 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 680 #define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */
<> 128:9bcdf88f62b0 681 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */
<> 128:9bcdf88f62b0 682 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */
<> 128:9bcdf88f62b0 683 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 684 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 685 #define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */
<> 128:9bcdf88f62b0 686 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */
<> 128:9bcdf88f62b0 687 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */
<> 128:9bcdf88f62b0 688 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 689 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 690 #define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */
<> 128:9bcdf88f62b0 691 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */
<> 128:9bcdf88f62b0 692 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */
<> 128:9bcdf88f62b0 693 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 694 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 695 #define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */
<> 128:9bcdf88f62b0 696 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */
<> 128:9bcdf88f62b0 697 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */
<> 128:9bcdf88f62b0 698 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 699 #define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 700 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */
<> 128:9bcdf88f62b0 701 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */
<> 128:9bcdf88f62b0 702 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */
<> 128:9bcdf88f62b0 703 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 704 #define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 705 #define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) /**< Channel 6 Wait on Request Status */
<> 128:9bcdf88f62b0 706 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 /**< Shift value for DMA_CH6WAITSTATUS */
<> 128:9bcdf88f62b0 707 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6WAITSTATUS */
<> 128:9bcdf88f62b0 708 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 709 #define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 710 #define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) /**< Channel 7 Wait on Request Status */
<> 128:9bcdf88f62b0 711 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 /**< Shift value for DMA_CH7WAITSTATUS */
<> 128:9bcdf88f62b0 712 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7WAITSTATUS */
<> 128:9bcdf88f62b0 713 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 714 #define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 715 #define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8) /**< Channel 8 Wait on Request Status */
<> 128:9bcdf88f62b0 716 #define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8 /**< Shift value for DMA_CH8WAITSTATUS */
<> 128:9bcdf88f62b0 717 #define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8WAITSTATUS */
<> 128:9bcdf88f62b0 718 #define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 719 #define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 720 #define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9) /**< Channel 9 Wait on Request Status */
<> 128:9bcdf88f62b0 721 #define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9 /**< Shift value for DMA_CH9WAITSTATUS */
<> 128:9bcdf88f62b0 722 #define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9WAITSTATUS */
<> 128:9bcdf88f62b0 723 #define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 724 #define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 725 #define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10) /**< Channel 10 Wait on Request Status */
<> 128:9bcdf88f62b0 726 #define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10 /**< Shift value for DMA_CH10WAITSTATUS */
<> 128:9bcdf88f62b0 727 #define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10WAITSTATUS */
<> 128:9bcdf88f62b0 728 #define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 729 #define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 730 #define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11) /**< Channel 11 Wait on Request Status */
<> 128:9bcdf88f62b0 731 #define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11 /**< Shift value for DMA_CH11WAITSTATUS */
<> 128:9bcdf88f62b0 732 #define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11WAITSTATUS */
<> 128:9bcdf88f62b0 733 #define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 734 #define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 735
<> 128:9bcdf88f62b0 736 /* Bit fields for DMA CHSWREQ */
<> 128:9bcdf88f62b0 737 #define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 738 #define _DMA_CHSWREQ_MASK 0x00000FFFUL /**< Mask for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 739 #define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */
<> 128:9bcdf88f62b0 740 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */
<> 128:9bcdf88f62b0 741 #define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */
<> 128:9bcdf88f62b0 742 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 743 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 744 #define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */
<> 128:9bcdf88f62b0 745 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */
<> 128:9bcdf88f62b0 746 #define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */
<> 128:9bcdf88f62b0 747 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 748 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 749 #define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */
<> 128:9bcdf88f62b0 750 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */
<> 128:9bcdf88f62b0 751 #define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */
<> 128:9bcdf88f62b0 752 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 753 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 754 #define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */
<> 128:9bcdf88f62b0 755 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */
<> 128:9bcdf88f62b0 756 #define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */
<> 128:9bcdf88f62b0 757 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 758 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 759 #define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */
<> 128:9bcdf88f62b0 760 #define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */
<> 128:9bcdf88f62b0 761 #define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */
<> 128:9bcdf88f62b0 762 #define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 763 #define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 764 #define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */
<> 128:9bcdf88f62b0 765 #define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */
<> 128:9bcdf88f62b0 766 #define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */
<> 128:9bcdf88f62b0 767 #define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 768 #define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 769 #define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) /**< Channel 6 Software Request */
<> 128:9bcdf88f62b0 770 #define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 /**< Shift value for DMA_CH6SWREQ */
<> 128:9bcdf88f62b0 771 #define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL /**< Bit mask for DMA_CH6SWREQ */
<> 128:9bcdf88f62b0 772 #define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 773 #define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 774 #define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) /**< Channel 7 Software Request */
<> 128:9bcdf88f62b0 775 #define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 /**< Shift value for DMA_CH7SWREQ */
<> 128:9bcdf88f62b0 776 #define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL /**< Bit mask for DMA_CH7SWREQ */
<> 128:9bcdf88f62b0 777 #define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 778 #define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 779 #define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8) /**< Channel 8 Software Request */
<> 128:9bcdf88f62b0 780 #define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8 /**< Shift value for DMA_CH8SWREQ */
<> 128:9bcdf88f62b0 781 #define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL /**< Bit mask for DMA_CH8SWREQ */
<> 128:9bcdf88f62b0 782 #define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 783 #define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 784 #define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9) /**< Channel 9 Software Request */
<> 128:9bcdf88f62b0 785 #define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9 /**< Shift value for DMA_CH9SWREQ */
<> 128:9bcdf88f62b0 786 #define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL /**< Bit mask for DMA_CH9SWREQ */
<> 128:9bcdf88f62b0 787 #define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 788 #define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 789 #define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10) /**< Channel 10 Software Request */
<> 128:9bcdf88f62b0 790 #define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10 /**< Shift value for DMA_CH10SWREQ */
<> 128:9bcdf88f62b0 791 #define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL /**< Bit mask for DMA_CH10SWREQ */
<> 128:9bcdf88f62b0 792 #define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 793 #define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 794 #define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11) /**< Channel 11 Software Request */
<> 128:9bcdf88f62b0 795 #define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11 /**< Shift value for DMA_CH11SWREQ */
<> 128:9bcdf88f62b0 796 #define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL /**< Bit mask for DMA_CH11SWREQ */
<> 128:9bcdf88f62b0 797 #define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 798 #define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 799
<> 128:9bcdf88f62b0 800 /* Bit fields for DMA CHUSEBURSTS */
<> 128:9bcdf88f62b0 801 #define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 802 #define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 803 #define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */
<> 128:9bcdf88f62b0 804 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */
<> 128:9bcdf88f62b0 805 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */
<> 128:9bcdf88f62b0 806 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 807 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 808 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 809 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 810 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 811 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 812 #define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */
<> 128:9bcdf88f62b0 813 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */
<> 128:9bcdf88f62b0 814 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */
<> 128:9bcdf88f62b0 815 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 816 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 817 #define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */
<> 128:9bcdf88f62b0 818 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */
<> 128:9bcdf88f62b0 819 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */
<> 128:9bcdf88f62b0 820 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 821 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 822 #define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */
<> 128:9bcdf88f62b0 823 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */
<> 128:9bcdf88f62b0 824 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */
<> 128:9bcdf88f62b0 825 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 826 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 827 #define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */
<> 128:9bcdf88f62b0 828 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */
<> 128:9bcdf88f62b0 829 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */
<> 128:9bcdf88f62b0 830 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 831 #define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 832 #define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */
<> 128:9bcdf88f62b0 833 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */
<> 128:9bcdf88f62b0 834 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */
<> 128:9bcdf88f62b0 835 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 836 #define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 837 #define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) /**< Channel 6 Useburst Set */
<> 128:9bcdf88f62b0 838 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTS */
<> 128:9bcdf88f62b0 839 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTS */
<> 128:9bcdf88f62b0 840 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 841 #define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 842 #define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) /**< Channel 7 Useburst Set */
<> 128:9bcdf88f62b0 843 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTS */
<> 128:9bcdf88f62b0 844 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTS */
<> 128:9bcdf88f62b0 845 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 846 #define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 847 #define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8) /**< Channel 8 Useburst Set */
<> 128:9bcdf88f62b0 848 #define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8 /**< Shift value for DMA_CH8USEBURSTS */
<> 128:9bcdf88f62b0 849 #define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL /**< Bit mask for DMA_CH8USEBURSTS */
<> 128:9bcdf88f62b0 850 #define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 851 #define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 852 #define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9) /**< Channel 9 Useburst Set */
<> 128:9bcdf88f62b0 853 #define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTS */
<> 128:9bcdf88f62b0 854 #define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTS */
<> 128:9bcdf88f62b0 855 #define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 856 #define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 857 #define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10) /**< Channel 10 Useburst Set */
<> 128:9bcdf88f62b0 858 #define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTS */
<> 128:9bcdf88f62b0 859 #define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTS */
<> 128:9bcdf88f62b0 860 #define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 861 #define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 862 #define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11) /**< Channel 11 Useburst Set */
<> 128:9bcdf88f62b0 863 #define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTS */
<> 128:9bcdf88f62b0 864 #define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTS */
<> 128:9bcdf88f62b0 865 #define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 866 #define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 867
<> 128:9bcdf88f62b0 868 /* Bit fields for DMA CHUSEBURSTC */
<> 128:9bcdf88f62b0 869 #define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 870 #define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 871 #define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */
<> 128:9bcdf88f62b0 872 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */
<> 128:9bcdf88f62b0 873 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */
<> 128:9bcdf88f62b0 874 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 875 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 876 #define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */
<> 128:9bcdf88f62b0 877 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */
<> 128:9bcdf88f62b0 878 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */
<> 128:9bcdf88f62b0 879 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 880 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 881 #define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */
<> 128:9bcdf88f62b0 882 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */
<> 128:9bcdf88f62b0 883 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */
<> 128:9bcdf88f62b0 884 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 885 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 886 #define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */
<> 128:9bcdf88f62b0 887 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */
<> 128:9bcdf88f62b0 888 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */
<> 128:9bcdf88f62b0 889 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 890 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 891 #define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */
<> 128:9bcdf88f62b0 892 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */
<> 128:9bcdf88f62b0 893 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */
<> 128:9bcdf88f62b0 894 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 895 #define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 896 #define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */
<> 128:9bcdf88f62b0 897 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */
<> 128:9bcdf88f62b0 898 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */
<> 128:9bcdf88f62b0 899 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 900 #define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 901 #define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) /**< Channel 6 Useburst Clear */
<> 128:9bcdf88f62b0 902 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTC */
<> 128:9bcdf88f62b0 903 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTC */
<> 128:9bcdf88f62b0 904 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 905 #define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 906 #define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) /**< Channel 7 Useburst Clear */
<> 128:9bcdf88f62b0 907 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTC */
<> 128:9bcdf88f62b0 908 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTC */
<> 128:9bcdf88f62b0 909 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 910 #define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 911 #define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8) /**< Channel 8 Useburst Clear */
<> 128:9bcdf88f62b0 912 #define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8 /**< Shift value for DMA_CH08USEBURSTC */
<> 128:9bcdf88f62b0 913 #define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL /**< Bit mask for DMA_CH08USEBURSTC */
<> 128:9bcdf88f62b0 914 #define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 915 #define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 916 #define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9) /**< Channel 9 Useburst Clear */
<> 128:9bcdf88f62b0 917 #define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTC */
<> 128:9bcdf88f62b0 918 #define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTC */
<> 128:9bcdf88f62b0 919 #define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 920 #define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 921 #define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10) /**< Channel 10 Useburst Clear */
<> 128:9bcdf88f62b0 922 #define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTC */
<> 128:9bcdf88f62b0 923 #define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTC */
<> 128:9bcdf88f62b0 924 #define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 925 #define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 926 #define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11) /**< Channel 11 Useburst Clear */
<> 128:9bcdf88f62b0 927 #define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTC */
<> 128:9bcdf88f62b0 928 #define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTC */
<> 128:9bcdf88f62b0 929 #define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 930 #define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 931
<> 128:9bcdf88f62b0 932 /* Bit fields for DMA CHREQMASKS */
<> 128:9bcdf88f62b0 933 #define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 934 #define _DMA_CHREQMASKS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 935 #define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */
<> 128:9bcdf88f62b0 936 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */
<> 128:9bcdf88f62b0 937 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */
<> 128:9bcdf88f62b0 938 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 939 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 940 #define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */
<> 128:9bcdf88f62b0 941 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */
<> 128:9bcdf88f62b0 942 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */
<> 128:9bcdf88f62b0 943 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 944 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 945 #define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */
<> 128:9bcdf88f62b0 946 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */
<> 128:9bcdf88f62b0 947 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */
<> 128:9bcdf88f62b0 948 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 949 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 950 #define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */
<> 128:9bcdf88f62b0 951 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */
<> 128:9bcdf88f62b0 952 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */
<> 128:9bcdf88f62b0 953 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 954 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 955 #define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */
<> 128:9bcdf88f62b0 956 #define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */
<> 128:9bcdf88f62b0 957 #define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */
<> 128:9bcdf88f62b0 958 #define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 959 #define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 960 #define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */
<> 128:9bcdf88f62b0 961 #define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */
<> 128:9bcdf88f62b0 962 #define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */
<> 128:9bcdf88f62b0 963 #define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 964 #define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 965 #define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) /**< Channel 6 Request Mask Set */
<> 128:9bcdf88f62b0 966 #define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 /**< Shift value for DMA_CH6REQMASKS */
<> 128:9bcdf88f62b0 967 #define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKS */
<> 128:9bcdf88f62b0 968 #define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 969 #define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 970 #define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) /**< Channel 7 Request Mask Set */
<> 128:9bcdf88f62b0 971 #define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 /**< Shift value for DMA_CH7REQMASKS */
<> 128:9bcdf88f62b0 972 #define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKS */
<> 128:9bcdf88f62b0 973 #define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 974 #define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 975 #define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8) /**< Channel 8 Request Mask Set */
<> 128:9bcdf88f62b0 976 #define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8 /**< Shift value for DMA_CH8REQMASKS */
<> 128:9bcdf88f62b0 977 #define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKS */
<> 128:9bcdf88f62b0 978 #define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 979 #define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 980 #define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9) /**< Channel 9 Request Mask Set */
<> 128:9bcdf88f62b0 981 #define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9 /**< Shift value for DMA_CH9REQMASKS */
<> 128:9bcdf88f62b0 982 #define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKS */
<> 128:9bcdf88f62b0 983 #define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 984 #define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 985 #define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10) /**< Channel 10 Request Mask Set */
<> 128:9bcdf88f62b0 986 #define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10 /**< Shift value for DMA_CH10REQMASKS */
<> 128:9bcdf88f62b0 987 #define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKS */
<> 128:9bcdf88f62b0 988 #define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 989 #define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 990 #define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11) /**< Channel 11 Request Mask Set */
<> 128:9bcdf88f62b0 991 #define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11 /**< Shift value for DMA_CH11REQMASKS */
<> 128:9bcdf88f62b0 992 #define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKS */
<> 128:9bcdf88f62b0 993 #define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 994 #define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 995
<> 128:9bcdf88f62b0 996 /* Bit fields for DMA CHREQMASKC */
<> 128:9bcdf88f62b0 997 #define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 998 #define _DMA_CHREQMASKC_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 999 #define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */
<> 128:9bcdf88f62b0 1000 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */
<> 128:9bcdf88f62b0 1001 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */
<> 128:9bcdf88f62b0 1002 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1003 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1004 #define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */
<> 128:9bcdf88f62b0 1005 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */
<> 128:9bcdf88f62b0 1006 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */
<> 128:9bcdf88f62b0 1007 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1008 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1009 #define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */
<> 128:9bcdf88f62b0 1010 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */
<> 128:9bcdf88f62b0 1011 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */
<> 128:9bcdf88f62b0 1012 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1013 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1014 #define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */
<> 128:9bcdf88f62b0 1015 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */
<> 128:9bcdf88f62b0 1016 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */
<> 128:9bcdf88f62b0 1017 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1018 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1019 #define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */
<> 128:9bcdf88f62b0 1020 #define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */
<> 128:9bcdf88f62b0 1021 #define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */
<> 128:9bcdf88f62b0 1022 #define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1023 #define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1024 #define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */
<> 128:9bcdf88f62b0 1025 #define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */
<> 128:9bcdf88f62b0 1026 #define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */
<> 128:9bcdf88f62b0 1027 #define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1028 #define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1029 #define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) /**< Channel 6 Request Mask Clear */
<> 128:9bcdf88f62b0 1030 #define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 /**< Shift value for DMA_CH6REQMASKC */
<> 128:9bcdf88f62b0 1031 #define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKC */
<> 128:9bcdf88f62b0 1032 #define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1033 #define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1034 #define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) /**< Channel 7 Request Mask Clear */
<> 128:9bcdf88f62b0 1035 #define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 /**< Shift value for DMA_CH7REQMASKC */
<> 128:9bcdf88f62b0 1036 #define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKC */
<> 128:9bcdf88f62b0 1037 #define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1038 #define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1039 #define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8) /**< Channel 8 Request Mask Clear */
<> 128:9bcdf88f62b0 1040 #define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8 /**< Shift value for DMA_CH8REQMASKC */
<> 128:9bcdf88f62b0 1041 #define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKC */
<> 128:9bcdf88f62b0 1042 #define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1043 #define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1044 #define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9) /**< Channel 9 Request Mask Clear */
<> 128:9bcdf88f62b0 1045 #define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9 /**< Shift value for DMA_CH9REQMASKC */
<> 128:9bcdf88f62b0 1046 #define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKC */
<> 128:9bcdf88f62b0 1047 #define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1048 #define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1049 #define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10) /**< Channel 10 Request Mask Clear */
<> 128:9bcdf88f62b0 1050 #define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10 /**< Shift value for DMA_CH10REQMASKC */
<> 128:9bcdf88f62b0 1051 #define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKC */
<> 128:9bcdf88f62b0 1052 #define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1053 #define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1054 #define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11) /**< Channel 11 Request Mask Clear */
<> 128:9bcdf88f62b0 1055 #define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11 /**< Shift value for DMA_CH11REQMASKC */
<> 128:9bcdf88f62b0 1056 #define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKC */
<> 128:9bcdf88f62b0 1057 #define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1058 #define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 1059
<> 128:9bcdf88f62b0 1060 /* Bit fields for DMA CHENS */
<> 128:9bcdf88f62b0 1061 #define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */
<> 128:9bcdf88f62b0 1062 #define _DMA_CHENS_MASK 0x00000FFFUL /**< Mask for DMA_CHENS */
<> 128:9bcdf88f62b0 1063 #define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */
<> 128:9bcdf88f62b0 1064 #define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */
<> 128:9bcdf88f62b0 1065 #define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */
<> 128:9bcdf88f62b0 1066 #define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1067 #define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1068 #define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */
<> 128:9bcdf88f62b0 1069 #define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */
<> 128:9bcdf88f62b0 1070 #define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */
<> 128:9bcdf88f62b0 1071 #define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1072 #define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1073 #define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */
<> 128:9bcdf88f62b0 1074 #define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */
<> 128:9bcdf88f62b0 1075 #define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */
<> 128:9bcdf88f62b0 1076 #define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1077 #define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1078 #define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */
<> 128:9bcdf88f62b0 1079 #define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */
<> 128:9bcdf88f62b0 1080 #define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */
<> 128:9bcdf88f62b0 1081 #define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1082 #define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1083 #define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */
<> 128:9bcdf88f62b0 1084 #define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */
<> 128:9bcdf88f62b0 1085 #define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */
<> 128:9bcdf88f62b0 1086 #define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1087 #define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1088 #define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */
<> 128:9bcdf88f62b0 1089 #define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */
<> 128:9bcdf88f62b0 1090 #define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */
<> 128:9bcdf88f62b0 1091 #define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1092 #define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1093 #define DMA_CHENS_CH6ENS (0x1UL << 6) /**< Channel 6 Enable Set */
<> 128:9bcdf88f62b0 1094 #define _DMA_CHENS_CH6ENS_SHIFT 6 /**< Shift value for DMA_CH6ENS */
<> 128:9bcdf88f62b0 1095 #define _DMA_CHENS_CH6ENS_MASK 0x40UL /**< Bit mask for DMA_CH6ENS */
<> 128:9bcdf88f62b0 1096 #define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1097 #define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1098 #define DMA_CHENS_CH7ENS (0x1UL << 7) /**< Channel 7 Enable Set */
<> 128:9bcdf88f62b0 1099 #define _DMA_CHENS_CH7ENS_SHIFT 7 /**< Shift value for DMA_CH7ENS */
<> 128:9bcdf88f62b0 1100 #define _DMA_CHENS_CH7ENS_MASK 0x80UL /**< Bit mask for DMA_CH7ENS */
<> 128:9bcdf88f62b0 1101 #define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1102 #define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1103 #define DMA_CHENS_CH8ENS (0x1UL << 8) /**< Channel 8 Enable Set */
<> 128:9bcdf88f62b0 1104 #define _DMA_CHENS_CH8ENS_SHIFT 8 /**< Shift value for DMA_CH8ENS */
<> 128:9bcdf88f62b0 1105 #define _DMA_CHENS_CH8ENS_MASK 0x100UL /**< Bit mask for DMA_CH8ENS */
<> 128:9bcdf88f62b0 1106 #define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1107 #define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1108 #define DMA_CHENS_CH9ENS (0x1UL << 9) /**< Channel 9 Enable Set */
<> 128:9bcdf88f62b0 1109 #define _DMA_CHENS_CH9ENS_SHIFT 9 /**< Shift value for DMA_CH9ENS */
<> 128:9bcdf88f62b0 1110 #define _DMA_CHENS_CH9ENS_MASK 0x200UL /**< Bit mask for DMA_CH9ENS */
<> 128:9bcdf88f62b0 1111 #define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1112 #define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1113 #define DMA_CHENS_CH10ENS (0x1UL << 10) /**< Channel 10 Enable Set */
<> 128:9bcdf88f62b0 1114 #define _DMA_CHENS_CH10ENS_SHIFT 10 /**< Shift value for DMA_CH10ENS */
<> 128:9bcdf88f62b0 1115 #define _DMA_CHENS_CH10ENS_MASK 0x400UL /**< Bit mask for DMA_CH10ENS */
<> 128:9bcdf88f62b0 1116 #define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1117 #define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1118 #define DMA_CHENS_CH11ENS (0x1UL << 11) /**< Channel 11 Enable Set */
<> 128:9bcdf88f62b0 1119 #define _DMA_CHENS_CH11ENS_SHIFT 11 /**< Shift value for DMA_CH11ENS */
<> 128:9bcdf88f62b0 1120 #define _DMA_CHENS_CH11ENS_MASK 0x800UL /**< Bit mask for DMA_CH11ENS */
<> 128:9bcdf88f62b0 1121 #define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1122 #define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 1123
<> 128:9bcdf88f62b0 1124 /* Bit fields for DMA CHENC */
<> 128:9bcdf88f62b0 1125 #define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */
<> 128:9bcdf88f62b0 1126 #define _DMA_CHENC_MASK 0x00000FFFUL /**< Mask for DMA_CHENC */
<> 128:9bcdf88f62b0 1127 #define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */
<> 128:9bcdf88f62b0 1128 #define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */
<> 128:9bcdf88f62b0 1129 #define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */
<> 128:9bcdf88f62b0 1130 #define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1131 #define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1132 #define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */
<> 128:9bcdf88f62b0 1133 #define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */
<> 128:9bcdf88f62b0 1134 #define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */
<> 128:9bcdf88f62b0 1135 #define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1136 #define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1137 #define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */
<> 128:9bcdf88f62b0 1138 #define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */
<> 128:9bcdf88f62b0 1139 #define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */
<> 128:9bcdf88f62b0 1140 #define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1141 #define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1142 #define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */
<> 128:9bcdf88f62b0 1143 #define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */
<> 128:9bcdf88f62b0 1144 #define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */
<> 128:9bcdf88f62b0 1145 #define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1146 #define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1147 #define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */
<> 128:9bcdf88f62b0 1148 #define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */
<> 128:9bcdf88f62b0 1149 #define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */
<> 128:9bcdf88f62b0 1150 #define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1151 #define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1152 #define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */
<> 128:9bcdf88f62b0 1153 #define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */
<> 128:9bcdf88f62b0 1154 #define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */
<> 128:9bcdf88f62b0 1155 #define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1156 #define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1157 #define DMA_CHENC_CH6ENC (0x1UL << 6) /**< Channel 6 Enable Clear */
<> 128:9bcdf88f62b0 1158 #define _DMA_CHENC_CH6ENC_SHIFT 6 /**< Shift value for DMA_CH6ENC */
<> 128:9bcdf88f62b0 1159 #define _DMA_CHENC_CH6ENC_MASK 0x40UL /**< Bit mask for DMA_CH6ENC */
<> 128:9bcdf88f62b0 1160 #define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1161 #define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1162 #define DMA_CHENC_CH7ENC (0x1UL << 7) /**< Channel 7 Enable Clear */
<> 128:9bcdf88f62b0 1163 #define _DMA_CHENC_CH7ENC_SHIFT 7 /**< Shift value for DMA_CH7ENC */
<> 128:9bcdf88f62b0 1164 #define _DMA_CHENC_CH7ENC_MASK 0x80UL /**< Bit mask for DMA_CH7ENC */
<> 128:9bcdf88f62b0 1165 #define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1166 #define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1167 #define DMA_CHENC_CH8ENC (0x1UL << 8) /**< Channel 8 Enable Clear */
<> 128:9bcdf88f62b0 1168 #define _DMA_CHENC_CH8ENC_SHIFT 8 /**< Shift value for DMA_CH8ENC */
<> 128:9bcdf88f62b0 1169 #define _DMA_CHENC_CH8ENC_MASK 0x100UL /**< Bit mask for DMA_CH8ENC */
<> 128:9bcdf88f62b0 1170 #define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1171 #define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1172 #define DMA_CHENC_CH9ENC (0x1UL << 9) /**< Channel 9 Enable Clear */
<> 128:9bcdf88f62b0 1173 #define _DMA_CHENC_CH9ENC_SHIFT 9 /**< Shift value for DMA_CH9ENC */
<> 128:9bcdf88f62b0 1174 #define _DMA_CHENC_CH9ENC_MASK 0x200UL /**< Bit mask for DMA_CH9ENC */
<> 128:9bcdf88f62b0 1175 #define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1176 #define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1177 #define DMA_CHENC_CH10ENC (0x1UL << 10) /**< Channel 10 Enable Clear */
<> 128:9bcdf88f62b0 1178 #define _DMA_CHENC_CH10ENC_SHIFT 10 /**< Shift value for DMA_CH10ENC */
<> 128:9bcdf88f62b0 1179 #define _DMA_CHENC_CH10ENC_MASK 0x400UL /**< Bit mask for DMA_CH10ENC */
<> 128:9bcdf88f62b0 1180 #define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1181 #define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1182 #define DMA_CHENC_CH11ENC (0x1UL << 11) /**< Channel 11 Enable Clear */
<> 128:9bcdf88f62b0 1183 #define _DMA_CHENC_CH11ENC_SHIFT 11 /**< Shift value for DMA_CH11ENC */
<> 128:9bcdf88f62b0 1184 #define _DMA_CHENC_CH11ENC_MASK 0x800UL /**< Bit mask for DMA_CH11ENC */
<> 128:9bcdf88f62b0 1185 #define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1186 #define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 1187
<> 128:9bcdf88f62b0 1188 /* Bit fields for DMA CHALTS */
<> 128:9bcdf88f62b0 1189 #define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */
<> 128:9bcdf88f62b0 1190 #define _DMA_CHALTS_MASK 0x00000FFFUL /**< Mask for DMA_CHALTS */
<> 128:9bcdf88f62b0 1191 #define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */
<> 128:9bcdf88f62b0 1192 #define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */
<> 128:9bcdf88f62b0 1193 #define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */
<> 128:9bcdf88f62b0 1194 #define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1195 #define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1196 #define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */
<> 128:9bcdf88f62b0 1197 #define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */
<> 128:9bcdf88f62b0 1198 #define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */
<> 128:9bcdf88f62b0 1199 #define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1200 #define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1201 #define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */
<> 128:9bcdf88f62b0 1202 #define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */
<> 128:9bcdf88f62b0 1203 #define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */
<> 128:9bcdf88f62b0 1204 #define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1205 #define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1206 #define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */
<> 128:9bcdf88f62b0 1207 #define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */
<> 128:9bcdf88f62b0 1208 #define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */
<> 128:9bcdf88f62b0 1209 #define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1210 #define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1211 #define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */
<> 128:9bcdf88f62b0 1212 #define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */
<> 128:9bcdf88f62b0 1213 #define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */
<> 128:9bcdf88f62b0 1214 #define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1215 #define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1216 #define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */
<> 128:9bcdf88f62b0 1217 #define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */
<> 128:9bcdf88f62b0 1218 #define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */
<> 128:9bcdf88f62b0 1219 #define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1220 #define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1221 #define DMA_CHALTS_CH6ALTS (0x1UL << 6) /**< Channel 6 Alternate Structure Set */
<> 128:9bcdf88f62b0 1222 #define _DMA_CHALTS_CH6ALTS_SHIFT 6 /**< Shift value for DMA_CH6ALTS */
<> 128:9bcdf88f62b0 1223 #define _DMA_CHALTS_CH6ALTS_MASK 0x40UL /**< Bit mask for DMA_CH6ALTS */
<> 128:9bcdf88f62b0 1224 #define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1225 #define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1226 #define DMA_CHALTS_CH7ALTS (0x1UL << 7) /**< Channel 7 Alternate Structure Set */
<> 128:9bcdf88f62b0 1227 #define _DMA_CHALTS_CH7ALTS_SHIFT 7 /**< Shift value for DMA_CH7ALTS */
<> 128:9bcdf88f62b0 1228 #define _DMA_CHALTS_CH7ALTS_MASK 0x80UL /**< Bit mask for DMA_CH7ALTS */
<> 128:9bcdf88f62b0 1229 #define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1230 #define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1231 #define DMA_CHALTS_CH8ALTS (0x1UL << 8) /**< Channel 8 Alternate Structure Set */
<> 128:9bcdf88f62b0 1232 #define _DMA_CHALTS_CH8ALTS_SHIFT 8 /**< Shift value for DMA_CH8ALTS */
<> 128:9bcdf88f62b0 1233 #define _DMA_CHALTS_CH8ALTS_MASK 0x100UL /**< Bit mask for DMA_CH8ALTS */
<> 128:9bcdf88f62b0 1234 #define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1235 #define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1236 #define DMA_CHALTS_CH9ALTS (0x1UL << 9) /**< Channel 9 Alternate Structure Set */
<> 128:9bcdf88f62b0 1237 #define _DMA_CHALTS_CH9ALTS_SHIFT 9 /**< Shift value for DMA_CH9ALTS */
<> 128:9bcdf88f62b0 1238 #define _DMA_CHALTS_CH9ALTS_MASK 0x200UL /**< Bit mask for DMA_CH9ALTS */
<> 128:9bcdf88f62b0 1239 #define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1240 #define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1241 #define DMA_CHALTS_CH10ALTS (0x1UL << 10) /**< Channel 10 Alternate Structure Set */
<> 128:9bcdf88f62b0 1242 #define _DMA_CHALTS_CH10ALTS_SHIFT 10 /**< Shift value for DMA_CH10ALTS */
<> 128:9bcdf88f62b0 1243 #define _DMA_CHALTS_CH10ALTS_MASK 0x400UL /**< Bit mask for DMA_CH10ALTS */
<> 128:9bcdf88f62b0 1244 #define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1245 #define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1246 #define DMA_CHALTS_CH11ALTS (0x1UL << 11) /**< Channel 11 Alternate Structure Set */
<> 128:9bcdf88f62b0 1247 #define _DMA_CHALTS_CH11ALTS_SHIFT 11 /**< Shift value for DMA_CH11ALTS */
<> 128:9bcdf88f62b0 1248 #define _DMA_CHALTS_CH11ALTS_MASK 0x800UL /**< Bit mask for DMA_CH11ALTS */
<> 128:9bcdf88f62b0 1249 #define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1250 #define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 1251
<> 128:9bcdf88f62b0 1252 /* Bit fields for DMA CHALTC */
<> 128:9bcdf88f62b0 1253 #define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */
<> 128:9bcdf88f62b0 1254 #define _DMA_CHALTC_MASK 0x00000FFFUL /**< Mask for DMA_CHALTC */
<> 128:9bcdf88f62b0 1255 #define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */
<> 128:9bcdf88f62b0 1256 #define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */
<> 128:9bcdf88f62b0 1257 #define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */
<> 128:9bcdf88f62b0 1258 #define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1259 #define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1260 #define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */
<> 128:9bcdf88f62b0 1261 #define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */
<> 128:9bcdf88f62b0 1262 #define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */
<> 128:9bcdf88f62b0 1263 #define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1264 #define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1265 #define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */
<> 128:9bcdf88f62b0 1266 #define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */
<> 128:9bcdf88f62b0 1267 #define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */
<> 128:9bcdf88f62b0 1268 #define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1269 #define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1270 #define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */
<> 128:9bcdf88f62b0 1271 #define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */
<> 128:9bcdf88f62b0 1272 #define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */
<> 128:9bcdf88f62b0 1273 #define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1274 #define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1275 #define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */
<> 128:9bcdf88f62b0 1276 #define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */
<> 128:9bcdf88f62b0 1277 #define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */
<> 128:9bcdf88f62b0 1278 #define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1279 #define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1280 #define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */
<> 128:9bcdf88f62b0 1281 #define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */
<> 128:9bcdf88f62b0 1282 #define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */
<> 128:9bcdf88f62b0 1283 #define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1284 #define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1285 #define DMA_CHALTC_CH6ALTC (0x1UL << 6) /**< Channel 6 Alternate Clear */
<> 128:9bcdf88f62b0 1286 #define _DMA_CHALTC_CH6ALTC_SHIFT 6 /**< Shift value for DMA_CH6ALTC */
<> 128:9bcdf88f62b0 1287 #define _DMA_CHALTC_CH6ALTC_MASK 0x40UL /**< Bit mask for DMA_CH6ALTC */
<> 128:9bcdf88f62b0 1288 #define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1289 #define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1290 #define DMA_CHALTC_CH7ALTC (0x1UL << 7) /**< Channel 7 Alternate Clear */
<> 128:9bcdf88f62b0 1291 #define _DMA_CHALTC_CH7ALTC_SHIFT 7 /**< Shift value for DMA_CH7ALTC */
<> 128:9bcdf88f62b0 1292 #define _DMA_CHALTC_CH7ALTC_MASK 0x80UL /**< Bit mask for DMA_CH7ALTC */
<> 128:9bcdf88f62b0 1293 #define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1294 #define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1295 #define DMA_CHALTC_CH8ALTC (0x1UL << 8) /**< Channel 8 Alternate Clear */
<> 128:9bcdf88f62b0 1296 #define _DMA_CHALTC_CH8ALTC_SHIFT 8 /**< Shift value for DMA_CH8ALTC */
<> 128:9bcdf88f62b0 1297 #define _DMA_CHALTC_CH8ALTC_MASK 0x100UL /**< Bit mask for DMA_CH8ALTC */
<> 128:9bcdf88f62b0 1298 #define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1299 #define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1300 #define DMA_CHALTC_CH9ALTC (0x1UL << 9) /**< Channel 9 Alternate Clear */
<> 128:9bcdf88f62b0 1301 #define _DMA_CHALTC_CH9ALTC_SHIFT 9 /**< Shift value for DMA_CH9ALTC */
<> 128:9bcdf88f62b0 1302 #define _DMA_CHALTC_CH9ALTC_MASK 0x200UL /**< Bit mask for DMA_CH9ALTC */
<> 128:9bcdf88f62b0 1303 #define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1304 #define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1305 #define DMA_CHALTC_CH10ALTC (0x1UL << 10) /**< Channel 10 Alternate Clear */
<> 128:9bcdf88f62b0 1306 #define _DMA_CHALTC_CH10ALTC_SHIFT 10 /**< Shift value for DMA_CH10ALTC */
<> 128:9bcdf88f62b0 1307 #define _DMA_CHALTC_CH10ALTC_MASK 0x400UL /**< Bit mask for DMA_CH10ALTC */
<> 128:9bcdf88f62b0 1308 #define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1309 #define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1310 #define DMA_CHALTC_CH11ALTC (0x1UL << 11) /**< Channel 11 Alternate Clear */
<> 128:9bcdf88f62b0 1311 #define _DMA_CHALTC_CH11ALTC_SHIFT 11 /**< Shift value for DMA_CH11ALTC */
<> 128:9bcdf88f62b0 1312 #define _DMA_CHALTC_CH11ALTC_MASK 0x800UL /**< Bit mask for DMA_CH11ALTC */
<> 128:9bcdf88f62b0 1313 #define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1314 #define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 1315
<> 128:9bcdf88f62b0 1316 /* Bit fields for DMA CHPRIS */
<> 128:9bcdf88f62b0 1317 #define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1318 #define _DMA_CHPRIS_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1319 #define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */
<> 128:9bcdf88f62b0 1320 #define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */
<> 128:9bcdf88f62b0 1321 #define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */
<> 128:9bcdf88f62b0 1322 #define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1323 #define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1324 #define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */
<> 128:9bcdf88f62b0 1325 #define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */
<> 128:9bcdf88f62b0 1326 #define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */
<> 128:9bcdf88f62b0 1327 #define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1328 #define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1329 #define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */
<> 128:9bcdf88f62b0 1330 #define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */
<> 128:9bcdf88f62b0 1331 #define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */
<> 128:9bcdf88f62b0 1332 #define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1333 #define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1334 #define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */
<> 128:9bcdf88f62b0 1335 #define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */
<> 128:9bcdf88f62b0 1336 #define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */
<> 128:9bcdf88f62b0 1337 #define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1338 #define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1339 #define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */
<> 128:9bcdf88f62b0 1340 #define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */
<> 128:9bcdf88f62b0 1341 #define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */
<> 128:9bcdf88f62b0 1342 #define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1343 #define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1344 #define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */
<> 128:9bcdf88f62b0 1345 #define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */
<> 128:9bcdf88f62b0 1346 #define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */
<> 128:9bcdf88f62b0 1347 #define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1348 #define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1349 #define DMA_CHPRIS_CH6PRIS (0x1UL << 6) /**< Channel 6 High Priority Set */
<> 128:9bcdf88f62b0 1350 #define _DMA_CHPRIS_CH6PRIS_SHIFT 6 /**< Shift value for DMA_CH6PRIS */
<> 128:9bcdf88f62b0 1351 #define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL /**< Bit mask for DMA_CH6PRIS */
<> 128:9bcdf88f62b0 1352 #define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1353 #define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1354 #define DMA_CHPRIS_CH7PRIS (0x1UL << 7) /**< Channel 7 High Priority Set */
<> 128:9bcdf88f62b0 1355 #define _DMA_CHPRIS_CH7PRIS_SHIFT 7 /**< Shift value for DMA_CH7PRIS */
<> 128:9bcdf88f62b0 1356 #define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL /**< Bit mask for DMA_CH7PRIS */
<> 128:9bcdf88f62b0 1357 #define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1358 #define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1359 #define DMA_CHPRIS_CH8PRIS (0x1UL << 8) /**< Channel 8 High Priority Set */
<> 128:9bcdf88f62b0 1360 #define _DMA_CHPRIS_CH8PRIS_SHIFT 8 /**< Shift value for DMA_CH8PRIS */
<> 128:9bcdf88f62b0 1361 #define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL /**< Bit mask for DMA_CH8PRIS */
<> 128:9bcdf88f62b0 1362 #define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1363 #define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1364 #define DMA_CHPRIS_CH9PRIS (0x1UL << 9) /**< Channel 9 High Priority Set */
<> 128:9bcdf88f62b0 1365 #define _DMA_CHPRIS_CH9PRIS_SHIFT 9 /**< Shift value for DMA_CH9PRIS */
<> 128:9bcdf88f62b0 1366 #define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL /**< Bit mask for DMA_CH9PRIS */
<> 128:9bcdf88f62b0 1367 #define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1368 #define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1369 #define DMA_CHPRIS_CH10PRIS (0x1UL << 10) /**< Channel 10 High Priority Set */
<> 128:9bcdf88f62b0 1370 #define _DMA_CHPRIS_CH10PRIS_SHIFT 10 /**< Shift value for DMA_CH10PRIS */
<> 128:9bcdf88f62b0 1371 #define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL /**< Bit mask for DMA_CH10PRIS */
<> 128:9bcdf88f62b0 1372 #define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1373 #define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1374 #define DMA_CHPRIS_CH11PRIS (0x1UL << 11) /**< Channel 11 High Priority Set */
<> 128:9bcdf88f62b0 1375 #define _DMA_CHPRIS_CH11PRIS_SHIFT 11 /**< Shift value for DMA_CH11PRIS */
<> 128:9bcdf88f62b0 1376 #define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL /**< Bit mask for DMA_CH11PRIS */
<> 128:9bcdf88f62b0 1377 #define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1378 #define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 1379
<> 128:9bcdf88f62b0 1380 /* Bit fields for DMA CHPRIC */
<> 128:9bcdf88f62b0 1381 #define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1382 #define _DMA_CHPRIC_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1383 #define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */
<> 128:9bcdf88f62b0 1384 #define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */
<> 128:9bcdf88f62b0 1385 #define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */
<> 128:9bcdf88f62b0 1386 #define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1387 #define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1388 #define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */
<> 128:9bcdf88f62b0 1389 #define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */
<> 128:9bcdf88f62b0 1390 #define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */
<> 128:9bcdf88f62b0 1391 #define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1392 #define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1393 #define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */
<> 128:9bcdf88f62b0 1394 #define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */
<> 128:9bcdf88f62b0 1395 #define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */
<> 128:9bcdf88f62b0 1396 #define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1397 #define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1398 #define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */
<> 128:9bcdf88f62b0 1399 #define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */
<> 128:9bcdf88f62b0 1400 #define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */
<> 128:9bcdf88f62b0 1401 #define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1402 #define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1403 #define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */
<> 128:9bcdf88f62b0 1404 #define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */
<> 128:9bcdf88f62b0 1405 #define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */
<> 128:9bcdf88f62b0 1406 #define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1407 #define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1408 #define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */
<> 128:9bcdf88f62b0 1409 #define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */
<> 128:9bcdf88f62b0 1410 #define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */
<> 128:9bcdf88f62b0 1411 #define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1412 #define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1413 #define DMA_CHPRIC_CH6PRIC (0x1UL << 6) /**< Channel 6 High Priority Clear */
<> 128:9bcdf88f62b0 1414 #define _DMA_CHPRIC_CH6PRIC_SHIFT 6 /**< Shift value for DMA_CH6PRIC */
<> 128:9bcdf88f62b0 1415 #define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL /**< Bit mask for DMA_CH6PRIC */
<> 128:9bcdf88f62b0 1416 #define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1417 #define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1418 #define DMA_CHPRIC_CH7PRIC (0x1UL << 7) /**< Channel 7 High Priority Clear */
<> 128:9bcdf88f62b0 1419 #define _DMA_CHPRIC_CH7PRIC_SHIFT 7 /**< Shift value for DMA_CH7PRIC */
<> 128:9bcdf88f62b0 1420 #define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL /**< Bit mask for DMA_CH7PRIC */
<> 128:9bcdf88f62b0 1421 #define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1422 #define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1423 #define DMA_CHPRIC_CH8PRIC (0x1UL << 8) /**< Channel 8 High Priority Clear */
<> 128:9bcdf88f62b0 1424 #define _DMA_CHPRIC_CH8PRIC_SHIFT 8 /**< Shift value for DMA_CH8PRIC */
<> 128:9bcdf88f62b0 1425 #define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL /**< Bit mask for DMA_CH8PRIC */
<> 128:9bcdf88f62b0 1426 #define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1427 #define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1428 #define DMA_CHPRIC_CH9PRIC (0x1UL << 9) /**< Channel 9 High Priority Clear */
<> 128:9bcdf88f62b0 1429 #define _DMA_CHPRIC_CH9PRIC_SHIFT 9 /**< Shift value for DMA_CH9PRIC */
<> 128:9bcdf88f62b0 1430 #define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL /**< Bit mask for DMA_CH9PRIC */
<> 128:9bcdf88f62b0 1431 #define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1432 #define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1433 #define DMA_CHPRIC_CH10PRIC (0x1UL << 10) /**< Channel 10 High Priority Clear */
<> 128:9bcdf88f62b0 1434 #define _DMA_CHPRIC_CH10PRIC_SHIFT 10 /**< Shift value for DMA_CH10PRIC */
<> 128:9bcdf88f62b0 1435 #define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL /**< Bit mask for DMA_CH10PRIC */
<> 128:9bcdf88f62b0 1436 #define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1437 #define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1438 #define DMA_CHPRIC_CH11PRIC (0x1UL << 11) /**< Channel 11 High Priority Clear */
<> 128:9bcdf88f62b0 1439 #define _DMA_CHPRIC_CH11PRIC_SHIFT 11 /**< Shift value for DMA_CH11PRIC */
<> 128:9bcdf88f62b0 1440 #define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL /**< Bit mask for DMA_CH11PRIC */
<> 128:9bcdf88f62b0 1441 #define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1442 #define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 1443
<> 128:9bcdf88f62b0 1444 /* Bit fields for DMA ERRORC */
<> 128:9bcdf88f62b0 1445 #define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */
<> 128:9bcdf88f62b0 1446 #define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */
<> 128:9bcdf88f62b0 1447 #define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */
<> 128:9bcdf88f62b0 1448 #define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */
<> 128:9bcdf88f62b0 1449 #define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */
<> 128:9bcdf88f62b0 1450 #define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */
<> 128:9bcdf88f62b0 1451 #define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */
<> 128:9bcdf88f62b0 1452
<> 128:9bcdf88f62b0 1453 /* Bit fields for DMA CHREQSTATUS */
<> 128:9bcdf88f62b0 1454 #define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1455 #define _DMA_CHREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1456 #define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */
<> 128:9bcdf88f62b0 1457 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */
<> 128:9bcdf88f62b0 1458 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */
<> 128:9bcdf88f62b0 1459 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1460 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1461 #define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */
<> 128:9bcdf88f62b0 1462 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */
<> 128:9bcdf88f62b0 1463 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */
<> 128:9bcdf88f62b0 1464 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1465 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1466 #define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */
<> 128:9bcdf88f62b0 1467 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */
<> 128:9bcdf88f62b0 1468 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */
<> 128:9bcdf88f62b0 1469 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1470 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1471 #define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */
<> 128:9bcdf88f62b0 1472 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */
<> 128:9bcdf88f62b0 1473 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */
<> 128:9bcdf88f62b0 1474 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1475 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1476 #define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */
<> 128:9bcdf88f62b0 1477 #define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */
<> 128:9bcdf88f62b0 1478 #define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */
<> 128:9bcdf88f62b0 1479 #define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1480 #define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1481 #define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */
<> 128:9bcdf88f62b0 1482 #define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */
<> 128:9bcdf88f62b0 1483 #define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */
<> 128:9bcdf88f62b0 1484 #define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1485 #define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1486 #define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) /**< Channel 6 Request Status */
<> 128:9bcdf88f62b0 1487 #define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6REQSTATUS */
<> 128:9bcdf88f62b0 1488 #define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6REQSTATUS */
<> 128:9bcdf88f62b0 1489 #define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1490 #define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1491 #define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) /**< Channel 7 Request Status */
<> 128:9bcdf88f62b0 1492 #define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7REQSTATUS */
<> 128:9bcdf88f62b0 1493 #define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7REQSTATUS */
<> 128:9bcdf88f62b0 1494 #define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1495 #define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1496 #define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8) /**< Channel 8 Request Status */
<> 128:9bcdf88f62b0 1497 #define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8REQSTATUS */
<> 128:9bcdf88f62b0 1498 #define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8REQSTATUS */
<> 128:9bcdf88f62b0 1499 #define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1500 #define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1501 #define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9) /**< Channel 9 Request Status */
<> 128:9bcdf88f62b0 1502 #define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9REQSTATUS */
<> 128:9bcdf88f62b0 1503 #define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9REQSTATUS */
<> 128:9bcdf88f62b0 1504 #define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1505 #define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1506 #define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10) /**< Channel 10 Request Status */
<> 128:9bcdf88f62b0 1507 #define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10REQSTATUS */
<> 128:9bcdf88f62b0 1508 #define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10REQSTATUS */
<> 128:9bcdf88f62b0 1509 #define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1510 #define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1511 #define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11) /**< Channel 11 Request Status */
<> 128:9bcdf88f62b0 1512 #define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11REQSTATUS */
<> 128:9bcdf88f62b0 1513 #define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11REQSTATUS */
<> 128:9bcdf88f62b0 1514 #define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1515 #define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1516
<> 128:9bcdf88f62b0 1517 /* Bit fields for DMA CHSREQSTATUS */
<> 128:9bcdf88f62b0 1518 #define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1519 #define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1520 #define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */
<> 128:9bcdf88f62b0 1521 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */
<> 128:9bcdf88f62b0 1522 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */
<> 128:9bcdf88f62b0 1523 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1524 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1525 #define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */
<> 128:9bcdf88f62b0 1526 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */
<> 128:9bcdf88f62b0 1527 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */
<> 128:9bcdf88f62b0 1528 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1529 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1530 #define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */
<> 128:9bcdf88f62b0 1531 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */
<> 128:9bcdf88f62b0 1532 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */
<> 128:9bcdf88f62b0 1533 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1534 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1535 #define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */
<> 128:9bcdf88f62b0 1536 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */
<> 128:9bcdf88f62b0 1537 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */
<> 128:9bcdf88f62b0 1538 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1539 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1540 #define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */
<> 128:9bcdf88f62b0 1541 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */
<> 128:9bcdf88f62b0 1542 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */
<> 128:9bcdf88f62b0 1543 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1544 #define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1545 #define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */
<> 128:9bcdf88f62b0 1546 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */
<> 128:9bcdf88f62b0 1547 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */
<> 128:9bcdf88f62b0 1548 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1549 #define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1550 #define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) /**< Channel 6 Single Request Status */
<> 128:9bcdf88f62b0 1551 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6SREQSTATUS */
<> 128:9bcdf88f62b0 1552 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6SREQSTATUS */
<> 128:9bcdf88f62b0 1553 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1554 #define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1555 #define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) /**< Channel 7 Single Request Status */
<> 128:9bcdf88f62b0 1556 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7SREQSTATUS */
<> 128:9bcdf88f62b0 1557 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7SREQSTATUS */
<> 128:9bcdf88f62b0 1558 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1559 #define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1560 #define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8) /**< Channel 8 Single Request Status */
<> 128:9bcdf88f62b0 1561 #define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8SREQSTATUS */
<> 128:9bcdf88f62b0 1562 #define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8SREQSTATUS */
<> 128:9bcdf88f62b0 1563 #define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1564 #define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1565 #define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9) /**< Channel 9 Single Request Status */
<> 128:9bcdf88f62b0 1566 #define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9SREQSTATUS */
<> 128:9bcdf88f62b0 1567 #define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9SREQSTATUS */
<> 128:9bcdf88f62b0 1568 #define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1569 #define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1570 #define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10) /**< Channel 10 Single Request Status */
<> 128:9bcdf88f62b0 1571 #define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10SREQSTATUS */
<> 128:9bcdf88f62b0 1572 #define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10SREQSTATUS */
<> 128:9bcdf88f62b0 1573 #define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1574 #define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1575 #define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11) /**< Channel 11 Single Request Status */
<> 128:9bcdf88f62b0 1576 #define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11SREQSTATUS */
<> 128:9bcdf88f62b0 1577 #define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11SREQSTATUS */
<> 128:9bcdf88f62b0 1578 #define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1579 #define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1580
<> 128:9bcdf88f62b0 1581 /* Bit fields for DMA IF */
<> 128:9bcdf88f62b0 1582 #define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */
<> 128:9bcdf88f62b0 1583 #define _DMA_IF_MASK 0x80000FFFUL /**< Mask for DMA_IF */
<> 128:9bcdf88f62b0 1584 #define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */
<> 128:9bcdf88f62b0 1585 #define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
<> 128:9bcdf88f62b0 1586 #define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
<> 128:9bcdf88f62b0 1587 #define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1588 #define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1589 #define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */
<> 128:9bcdf88f62b0 1590 #define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
<> 128:9bcdf88f62b0 1591 #define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
<> 128:9bcdf88f62b0 1592 #define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1593 #define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1594 #define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */
<> 128:9bcdf88f62b0 1595 #define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
<> 128:9bcdf88f62b0 1596 #define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
<> 128:9bcdf88f62b0 1597 #define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1598 #define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1599 #define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */
<> 128:9bcdf88f62b0 1600 #define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
<> 128:9bcdf88f62b0 1601 #define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
<> 128:9bcdf88f62b0 1602 #define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1603 #define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1604 #define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */
<> 128:9bcdf88f62b0 1605 #define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
<> 128:9bcdf88f62b0 1606 #define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
<> 128:9bcdf88f62b0 1607 #define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1608 #define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1609 #define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */
<> 128:9bcdf88f62b0 1610 #define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
<> 128:9bcdf88f62b0 1611 #define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
<> 128:9bcdf88f62b0 1612 #define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1613 #define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1614 #define DMA_IF_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag */
<> 128:9bcdf88f62b0 1615 #define _DMA_IF_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */
<> 128:9bcdf88f62b0 1616 #define _DMA_IF_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */
<> 128:9bcdf88f62b0 1617 #define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1618 #define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1619 #define DMA_IF_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag */
<> 128:9bcdf88f62b0 1620 #define _DMA_IF_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */
<> 128:9bcdf88f62b0 1621 #define _DMA_IF_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */
<> 128:9bcdf88f62b0 1622 #define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1623 #define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1624 #define DMA_IF_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag */
<> 128:9bcdf88f62b0 1625 #define _DMA_IF_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */
<> 128:9bcdf88f62b0 1626 #define _DMA_IF_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */
<> 128:9bcdf88f62b0 1627 #define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1628 #define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1629 #define DMA_IF_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag */
<> 128:9bcdf88f62b0 1630 #define _DMA_IF_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */
<> 128:9bcdf88f62b0 1631 #define _DMA_IF_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */
<> 128:9bcdf88f62b0 1632 #define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1633 #define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1634 #define DMA_IF_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag */
<> 128:9bcdf88f62b0 1635 #define _DMA_IF_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */
<> 128:9bcdf88f62b0 1636 #define _DMA_IF_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */
<> 128:9bcdf88f62b0 1637 #define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1638 #define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1639 #define DMA_IF_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag */
<> 128:9bcdf88f62b0 1640 #define _DMA_IF_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */
<> 128:9bcdf88f62b0 1641 #define _DMA_IF_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */
<> 128:9bcdf88f62b0 1642 #define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1643 #define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1644 #define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */
<> 128:9bcdf88f62b0 1645 #define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
<> 128:9bcdf88f62b0 1646 #define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
<> 128:9bcdf88f62b0 1647 #define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1648 #define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1649
<> 128:9bcdf88f62b0 1650 /* Bit fields for DMA IFS */
<> 128:9bcdf88f62b0 1651 #define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */
<> 128:9bcdf88f62b0 1652 #define _DMA_IFS_MASK 0x80000FFFUL /**< Mask for DMA_IFS */
<> 128:9bcdf88f62b0 1653 #define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */
<> 128:9bcdf88f62b0 1654 #define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
<> 128:9bcdf88f62b0 1655 #define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
<> 128:9bcdf88f62b0 1656 #define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1657 #define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1658 #define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */
<> 128:9bcdf88f62b0 1659 #define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
<> 128:9bcdf88f62b0 1660 #define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
<> 128:9bcdf88f62b0 1661 #define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1662 #define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1663 #define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */
<> 128:9bcdf88f62b0 1664 #define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
<> 128:9bcdf88f62b0 1665 #define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
<> 128:9bcdf88f62b0 1666 #define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1667 #define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1668 #define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */
<> 128:9bcdf88f62b0 1669 #define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
<> 128:9bcdf88f62b0 1670 #define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
<> 128:9bcdf88f62b0 1671 #define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1672 #define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1673 #define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */
<> 128:9bcdf88f62b0 1674 #define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
<> 128:9bcdf88f62b0 1675 #define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
<> 128:9bcdf88f62b0 1676 #define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1677 #define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1678 #define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */
<> 128:9bcdf88f62b0 1679 #define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
<> 128:9bcdf88f62b0 1680 #define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
<> 128:9bcdf88f62b0 1681 #define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1682 #define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1683 #define DMA_IFS_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Set */
<> 128:9bcdf88f62b0 1684 #define _DMA_IFS_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */
<> 128:9bcdf88f62b0 1685 #define _DMA_IFS_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */
<> 128:9bcdf88f62b0 1686 #define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1687 #define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1688 #define DMA_IFS_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Set */
<> 128:9bcdf88f62b0 1689 #define _DMA_IFS_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */
<> 128:9bcdf88f62b0 1690 #define _DMA_IFS_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */
<> 128:9bcdf88f62b0 1691 #define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1692 #define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1693 #define DMA_IFS_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Set */
<> 128:9bcdf88f62b0 1694 #define _DMA_IFS_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */
<> 128:9bcdf88f62b0 1695 #define _DMA_IFS_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */
<> 128:9bcdf88f62b0 1696 #define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1697 #define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1698 #define DMA_IFS_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Set */
<> 128:9bcdf88f62b0 1699 #define _DMA_IFS_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */
<> 128:9bcdf88f62b0 1700 #define _DMA_IFS_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */
<> 128:9bcdf88f62b0 1701 #define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1702 #define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1703 #define DMA_IFS_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Set */
<> 128:9bcdf88f62b0 1704 #define _DMA_IFS_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */
<> 128:9bcdf88f62b0 1705 #define _DMA_IFS_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */
<> 128:9bcdf88f62b0 1706 #define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1707 #define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1708 #define DMA_IFS_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Set */
<> 128:9bcdf88f62b0 1709 #define _DMA_IFS_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */
<> 128:9bcdf88f62b0 1710 #define _DMA_IFS_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */
<> 128:9bcdf88f62b0 1711 #define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1712 #define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1713 #define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */
<> 128:9bcdf88f62b0 1714 #define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
<> 128:9bcdf88f62b0 1715 #define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
<> 128:9bcdf88f62b0 1716 #define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1717 #define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1718
<> 128:9bcdf88f62b0 1719 /* Bit fields for DMA IFC */
<> 128:9bcdf88f62b0 1720 #define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */
<> 128:9bcdf88f62b0 1721 #define _DMA_IFC_MASK 0x80000FFFUL /**< Mask for DMA_IFC */
<> 128:9bcdf88f62b0 1722 #define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1723 #define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
<> 128:9bcdf88f62b0 1724 #define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
<> 128:9bcdf88f62b0 1725 #define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1726 #define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1727 #define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1728 #define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
<> 128:9bcdf88f62b0 1729 #define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
<> 128:9bcdf88f62b0 1730 #define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1731 #define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1732 #define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1733 #define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
<> 128:9bcdf88f62b0 1734 #define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
<> 128:9bcdf88f62b0 1735 #define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1736 #define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1737 #define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1738 #define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
<> 128:9bcdf88f62b0 1739 #define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
<> 128:9bcdf88f62b0 1740 #define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1741 #define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1742 #define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1743 #define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
<> 128:9bcdf88f62b0 1744 #define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
<> 128:9bcdf88f62b0 1745 #define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1746 #define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1747 #define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1748 #define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
<> 128:9bcdf88f62b0 1749 #define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
<> 128:9bcdf88f62b0 1750 #define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1751 #define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1752 #define DMA_IFC_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1753 #define _DMA_IFC_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */
<> 128:9bcdf88f62b0 1754 #define _DMA_IFC_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */
<> 128:9bcdf88f62b0 1755 #define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1756 #define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1757 #define DMA_IFC_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1758 #define _DMA_IFC_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */
<> 128:9bcdf88f62b0 1759 #define _DMA_IFC_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */
<> 128:9bcdf88f62b0 1760 #define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1761 #define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1762 #define DMA_IFC_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1763 #define _DMA_IFC_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */
<> 128:9bcdf88f62b0 1764 #define _DMA_IFC_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */
<> 128:9bcdf88f62b0 1765 #define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1766 #define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1767 #define DMA_IFC_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1768 #define _DMA_IFC_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */
<> 128:9bcdf88f62b0 1769 #define _DMA_IFC_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */
<> 128:9bcdf88f62b0 1770 #define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1771 #define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1772 #define DMA_IFC_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1773 #define _DMA_IFC_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */
<> 128:9bcdf88f62b0 1774 #define _DMA_IFC_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */
<> 128:9bcdf88f62b0 1775 #define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1776 #define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1777 #define DMA_IFC_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1778 #define _DMA_IFC_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */
<> 128:9bcdf88f62b0 1779 #define _DMA_IFC_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */
<> 128:9bcdf88f62b0 1780 #define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1781 #define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1782 #define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1783 #define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
<> 128:9bcdf88f62b0 1784 #define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
<> 128:9bcdf88f62b0 1785 #define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1786 #define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1787
<> 128:9bcdf88f62b0 1788 /* Bit fields for DMA IEN */
<> 128:9bcdf88f62b0 1789 #define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */
<> 128:9bcdf88f62b0 1790 #define _DMA_IEN_MASK 0x80000FFFUL /**< Mask for DMA_IEN */
<> 128:9bcdf88f62b0 1791 #define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */
<> 128:9bcdf88f62b0 1792 #define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
<> 128:9bcdf88f62b0 1793 #define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
<> 128:9bcdf88f62b0 1794 #define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1795 #define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1796 #define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */
<> 128:9bcdf88f62b0 1797 #define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
<> 128:9bcdf88f62b0 1798 #define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
<> 128:9bcdf88f62b0 1799 #define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1800 #define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1801 #define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */
<> 128:9bcdf88f62b0 1802 #define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
<> 128:9bcdf88f62b0 1803 #define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
<> 128:9bcdf88f62b0 1804 #define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1805 #define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1806 #define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */
<> 128:9bcdf88f62b0 1807 #define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
<> 128:9bcdf88f62b0 1808 #define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
<> 128:9bcdf88f62b0 1809 #define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1810 #define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1811 #define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */
<> 128:9bcdf88f62b0 1812 #define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
<> 128:9bcdf88f62b0 1813 #define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
<> 128:9bcdf88f62b0 1814 #define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1815 #define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1816 #define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */
<> 128:9bcdf88f62b0 1817 #define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
<> 128:9bcdf88f62b0 1818 #define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
<> 128:9bcdf88f62b0 1819 #define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1820 #define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1821 #define DMA_IEN_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Enable */
<> 128:9bcdf88f62b0 1822 #define _DMA_IEN_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */
<> 128:9bcdf88f62b0 1823 #define _DMA_IEN_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */
<> 128:9bcdf88f62b0 1824 #define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1825 #define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1826 #define DMA_IEN_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Enable */
<> 128:9bcdf88f62b0 1827 #define _DMA_IEN_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */
<> 128:9bcdf88f62b0 1828 #define _DMA_IEN_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */
<> 128:9bcdf88f62b0 1829 #define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1830 #define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1831 #define DMA_IEN_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Enable */
<> 128:9bcdf88f62b0 1832 #define _DMA_IEN_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */
<> 128:9bcdf88f62b0 1833 #define _DMA_IEN_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */
<> 128:9bcdf88f62b0 1834 #define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1835 #define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1836 #define DMA_IEN_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Enable */
<> 128:9bcdf88f62b0 1837 #define _DMA_IEN_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */
<> 128:9bcdf88f62b0 1838 #define _DMA_IEN_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */
<> 128:9bcdf88f62b0 1839 #define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1840 #define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1841 #define DMA_IEN_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Enable */
<> 128:9bcdf88f62b0 1842 #define _DMA_IEN_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */
<> 128:9bcdf88f62b0 1843 #define _DMA_IEN_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */
<> 128:9bcdf88f62b0 1844 #define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1845 #define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1846 #define DMA_IEN_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Enable */
<> 128:9bcdf88f62b0 1847 #define _DMA_IEN_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */
<> 128:9bcdf88f62b0 1848 #define _DMA_IEN_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */
<> 128:9bcdf88f62b0 1849 #define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1850 #define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1851 #define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */
<> 128:9bcdf88f62b0 1852 #define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
<> 128:9bcdf88f62b0 1853 #define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
<> 128:9bcdf88f62b0 1854 #define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1855 #define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1856
<> 128:9bcdf88f62b0 1857 /* Bit fields for DMA CTRL */
<> 128:9bcdf88f62b0 1858 #define _DMA_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRL */
<> 128:9bcdf88f62b0 1859 #define _DMA_CTRL_MASK 0x00000003UL /**< Mask for DMA_CTRL */
<> 128:9bcdf88f62b0 1860 #define DMA_CTRL_DESCRECT (0x1UL << 0) /**< Descriptor Specifies Rectangle */
<> 128:9bcdf88f62b0 1861 #define _DMA_CTRL_DESCRECT_SHIFT 0 /**< Shift value for DMA_DESCRECT */
<> 128:9bcdf88f62b0 1862 #define _DMA_CTRL_DESCRECT_MASK 0x1UL /**< Bit mask for DMA_DESCRECT */
<> 128:9bcdf88f62b0 1863 #define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */
<> 128:9bcdf88f62b0 1864 #define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRL */
<> 128:9bcdf88f62b0 1865 #define DMA_CTRL_PRDU (0x1UL << 1) /**< Prevent Rect Descriptor Update */
<> 128:9bcdf88f62b0 1866 #define _DMA_CTRL_PRDU_SHIFT 1 /**< Shift value for DMA_PRDU */
<> 128:9bcdf88f62b0 1867 #define _DMA_CTRL_PRDU_MASK 0x2UL /**< Bit mask for DMA_PRDU */
<> 128:9bcdf88f62b0 1868 #define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */
<> 128:9bcdf88f62b0 1869 #define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CTRL */
<> 128:9bcdf88f62b0 1870
<> 128:9bcdf88f62b0 1871 /* Bit fields for DMA RDS */
<> 128:9bcdf88f62b0 1872 #define _DMA_RDS_RESETVALUE 0x00000000UL /**< Default value for DMA_RDS */
<> 128:9bcdf88f62b0 1873 #define _DMA_RDS_MASK 0x00000FFFUL /**< Mask for DMA_RDS */
<> 128:9bcdf88f62b0 1874 #define DMA_RDS_RDSCH0 (0x1UL << 0) /**< Retain Descriptor State */
<> 128:9bcdf88f62b0 1875 #define _DMA_RDS_RDSCH0_SHIFT 0 /**< Shift value for DMA_RDSCH0 */
<> 128:9bcdf88f62b0 1876 #define _DMA_RDS_RDSCH0_MASK 0x1UL /**< Bit mask for DMA_RDSCH0 */
<> 128:9bcdf88f62b0 1877 #define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1878 #define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1879 #define DMA_RDS_RDSCH1 (0x1UL << 1) /**< Retain Descriptor State */
<> 128:9bcdf88f62b0 1880 #define _DMA_RDS_RDSCH1_SHIFT 1 /**< Shift value for DMA_RDSCH1 */
<> 128:9bcdf88f62b0 1881 #define _DMA_RDS_RDSCH1_MASK 0x2UL /**< Bit mask for DMA_RDSCH1 */
<> 128:9bcdf88f62b0 1882 #define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1883 #define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1884 #define DMA_RDS_RDSCH2 (0x1UL << 2) /**< Retain Descriptor State */
<> 128:9bcdf88f62b0 1885 #define _DMA_RDS_RDSCH2_SHIFT 2 /**< Shift value for DMA_RDSCH2 */
<> 128:9bcdf88f62b0 1886 #define _DMA_RDS_RDSCH2_MASK 0x4UL /**< Bit mask for DMA_RDSCH2 */
<> 128:9bcdf88f62b0 1887 #define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1888 #define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1889 #define DMA_RDS_RDSCH3 (0x1UL << 3) /**< Retain Descriptor State */
<> 128:9bcdf88f62b0 1890 #define _DMA_RDS_RDSCH3_SHIFT 3 /**< Shift value for DMA_RDSCH3 */
<> 128:9bcdf88f62b0 1891 #define _DMA_RDS_RDSCH3_MASK 0x8UL /**< Bit mask for DMA_RDSCH3 */
<> 128:9bcdf88f62b0 1892 #define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1893 #define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1894 #define DMA_RDS_RDSCH4 (0x1UL << 4) /**< Retain Descriptor State */
<> 128:9bcdf88f62b0 1895 #define _DMA_RDS_RDSCH4_SHIFT 4 /**< Shift value for DMA_RDSCH4 */
<> 128:9bcdf88f62b0 1896 #define _DMA_RDS_RDSCH4_MASK 0x10UL /**< Bit mask for DMA_RDSCH4 */
<> 128:9bcdf88f62b0 1897 #define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1898 #define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1899 #define DMA_RDS_RDSCH5 (0x1UL << 5) /**< Retain Descriptor State */
<> 128:9bcdf88f62b0 1900 #define _DMA_RDS_RDSCH5_SHIFT 5 /**< Shift value for DMA_RDSCH5 */
<> 128:9bcdf88f62b0 1901 #define _DMA_RDS_RDSCH5_MASK 0x20UL /**< Bit mask for DMA_RDSCH5 */
<> 128:9bcdf88f62b0 1902 #define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1903 #define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1904 #define DMA_RDS_RDSCH6 (0x1UL << 6) /**< Retain Descriptor State */
<> 128:9bcdf88f62b0 1905 #define _DMA_RDS_RDSCH6_SHIFT 6 /**< Shift value for DMA_RDSCH6 */
<> 128:9bcdf88f62b0 1906 #define _DMA_RDS_RDSCH6_MASK 0x40UL /**< Bit mask for DMA_RDSCH6 */
<> 128:9bcdf88f62b0 1907 #define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1908 #define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1909 #define DMA_RDS_RDSCH7 (0x1UL << 7) /**< Retain Descriptor State */
<> 128:9bcdf88f62b0 1910 #define _DMA_RDS_RDSCH7_SHIFT 7 /**< Shift value for DMA_RDSCH7 */
<> 128:9bcdf88f62b0 1911 #define _DMA_RDS_RDSCH7_MASK 0x80UL /**< Bit mask for DMA_RDSCH7 */
<> 128:9bcdf88f62b0 1912 #define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1913 #define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1914 #define DMA_RDS_RDSCH8 (0x1UL << 8) /**< Retain Descriptor State */
<> 128:9bcdf88f62b0 1915 #define _DMA_RDS_RDSCH8_SHIFT 8 /**< Shift value for DMA_RDSCH8 */
<> 128:9bcdf88f62b0 1916 #define _DMA_RDS_RDSCH8_MASK 0x100UL /**< Bit mask for DMA_RDSCH8 */
<> 128:9bcdf88f62b0 1917 #define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1918 #define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1919 #define DMA_RDS_RDSCH9 (0x1UL << 9) /**< Retain Descriptor State */
<> 128:9bcdf88f62b0 1920 #define _DMA_RDS_RDSCH9_SHIFT 9 /**< Shift value for DMA_RDSCH9 */
<> 128:9bcdf88f62b0 1921 #define _DMA_RDS_RDSCH9_MASK 0x200UL /**< Bit mask for DMA_RDSCH9 */
<> 128:9bcdf88f62b0 1922 #define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1923 #define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1924 #define DMA_RDS_RDSCH10 (0x1UL << 10) /**< Retain Descriptor State */
<> 128:9bcdf88f62b0 1925 #define _DMA_RDS_RDSCH10_SHIFT 10 /**< Shift value for DMA_RDSCH10 */
<> 128:9bcdf88f62b0 1926 #define _DMA_RDS_RDSCH10_MASK 0x400UL /**< Bit mask for DMA_RDSCH10 */
<> 128:9bcdf88f62b0 1927 #define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1928 #define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1929 #define DMA_RDS_RDSCH11 (0x1UL << 11) /**< Retain Descriptor State */
<> 128:9bcdf88f62b0 1930 #define _DMA_RDS_RDSCH11_SHIFT 11 /**< Shift value for DMA_RDSCH11 */
<> 128:9bcdf88f62b0 1931 #define _DMA_RDS_RDSCH11_MASK 0x800UL /**< Bit mask for DMA_RDSCH11 */
<> 128:9bcdf88f62b0 1932 #define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1933 #define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_RDS */
<> 128:9bcdf88f62b0 1934
<> 128:9bcdf88f62b0 1935 /* Bit fields for DMA LOOP0 */
<> 128:9bcdf88f62b0 1936 #define _DMA_LOOP0_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP0 */
<> 128:9bcdf88f62b0 1937 #define _DMA_LOOP0_MASK 0x000103FFUL /**< Mask for DMA_LOOP0 */
<> 128:9bcdf88f62b0 1938 #define _DMA_LOOP0_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */
<> 128:9bcdf88f62b0 1939 #define _DMA_LOOP0_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */
<> 128:9bcdf88f62b0 1940 #define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */
<> 128:9bcdf88f62b0 1941 #define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP0 */
<> 128:9bcdf88f62b0 1942 #define DMA_LOOP0_EN (0x1UL << 16) /**< DMA Channel 0 Loop Enable */
<> 128:9bcdf88f62b0 1943 #define _DMA_LOOP0_EN_SHIFT 16 /**< Shift value for DMA_EN */
<> 128:9bcdf88f62b0 1944 #define _DMA_LOOP0_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */
<> 128:9bcdf88f62b0 1945 #define _DMA_LOOP0_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */
<> 128:9bcdf88f62b0 1946 #define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP0 */
<> 128:9bcdf88f62b0 1947
<> 128:9bcdf88f62b0 1948 /* Bit fields for DMA LOOP1 */
<> 128:9bcdf88f62b0 1949 #define _DMA_LOOP1_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP1 */
<> 128:9bcdf88f62b0 1950 #define _DMA_LOOP1_MASK 0x000103FFUL /**< Mask for DMA_LOOP1 */
<> 128:9bcdf88f62b0 1951 #define _DMA_LOOP1_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */
<> 128:9bcdf88f62b0 1952 #define _DMA_LOOP1_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */
<> 128:9bcdf88f62b0 1953 #define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */
<> 128:9bcdf88f62b0 1954 #define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP1 */
<> 128:9bcdf88f62b0 1955 #define DMA_LOOP1_EN (0x1UL << 16) /**< DMA Channel 1 Loop Enable */
<> 128:9bcdf88f62b0 1956 #define _DMA_LOOP1_EN_SHIFT 16 /**< Shift value for DMA_EN */
<> 128:9bcdf88f62b0 1957 #define _DMA_LOOP1_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */
<> 128:9bcdf88f62b0 1958 #define _DMA_LOOP1_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */
<> 128:9bcdf88f62b0 1959 #define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP1 */
<> 128:9bcdf88f62b0 1960
<> 128:9bcdf88f62b0 1961 /* Bit fields for DMA RECT0 */
<> 128:9bcdf88f62b0 1962 #define _DMA_RECT0_RESETVALUE 0x00000000UL /**< Default value for DMA_RECT0 */
<> 128:9bcdf88f62b0 1963 #define _DMA_RECT0_MASK 0xFFFFFFFFUL /**< Mask for DMA_RECT0 */
<> 128:9bcdf88f62b0 1964 #define _DMA_RECT0_HEIGHT_SHIFT 0 /**< Shift value for DMA_HEIGHT */
<> 128:9bcdf88f62b0 1965 #define _DMA_RECT0_HEIGHT_MASK 0x3FFUL /**< Bit mask for DMA_HEIGHT */
<> 128:9bcdf88f62b0 1966 #define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */
<> 128:9bcdf88f62b0 1967 #define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RECT0 */
<> 128:9bcdf88f62b0 1968 #define _DMA_RECT0_SRCSTRIDE_SHIFT 10 /**< Shift value for DMA_SRCSTRIDE */
<> 128:9bcdf88f62b0 1969 #define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL /**< Bit mask for DMA_SRCSTRIDE */
<> 128:9bcdf88f62b0 1970 #define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */
<> 128:9bcdf88f62b0 1971 #define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RECT0 */
<> 128:9bcdf88f62b0 1972 #define _DMA_RECT0_DSTSTRIDE_SHIFT 21 /**< Shift value for DMA_DSTSTRIDE */
<> 128:9bcdf88f62b0 1973 #define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL /**< Bit mask for DMA_DSTSTRIDE */
<> 128:9bcdf88f62b0 1974 #define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */
<> 128:9bcdf88f62b0 1975 #define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) /**< Shifted mode DEFAULT for DMA_RECT0 */
<> 128:9bcdf88f62b0 1976
<> 128:9bcdf88f62b0 1977 /* Bit fields for DMA CH_CTRL */
<> 128:9bcdf88f62b0 1978 #define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1979 #define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1980 #define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */
<> 128:9bcdf88f62b0 1981 #define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */
<> 128:9bcdf88f62b0 1982 #define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1983 #define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1984 #define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1985 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1986 #define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1987 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1988 #define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1989 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1990 #define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1991 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1992 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1993 #define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1994 #define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1995 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1996 #define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1997 #define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1998 #define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1999 #define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2000 #define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2001 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2002 #define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2003 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2004 #define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2005 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2006 #define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2007 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2008 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2009 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2010 #define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2011 #define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2012 #define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2013 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2014 #define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2015 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2016 #define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2017 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2018 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2019 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2020 #define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2021 #define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2022 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2023 #define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /**< Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2024 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2025 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2026 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2027 #define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2028 #define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2029 #define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2030 #define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /**< Mode USART2TXBLRIGHT for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2031 #define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2032 #define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2033 #define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2034 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2035 #define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2036 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2037 #define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2038 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2039 #define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2040 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2041 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2042 #define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2043 #define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2044 #define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2045 #define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2046 #define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2047 #define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2048 #define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2049 #define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2050 #define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2051 #define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2052 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2053 #define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2054 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2055 #define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2056 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2057 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2058 #define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2059 #define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2060 #define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2061 #define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2062 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2063 #define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2064 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2065 #define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2066 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2067 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2068 #define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2069 #define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2070 #define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2071 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2072 #define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /**< Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2073 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2074 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2075 #define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2076 #define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2077 #define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2078 #define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2079 #define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /**< Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2080 #define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */
<> 128:9bcdf88f62b0 2081 #define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */
<> 128:9bcdf88f62b0 2082 #define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2083 #define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2084 #define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2085 #define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2086 #define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2087 #define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2088 #define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2089 #define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2090 #define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2091 #define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2092 #define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2093 #define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2094 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2095 #define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /**< Mode TIMER3 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2096 #define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2097 #define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2098 #define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /**< Mode LESENSE for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2099 #define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2100 #define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2101 #define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2102 #define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2103 #define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2104 #define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2105 #define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2106 #define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2107 #define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2108 #define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2109 #define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2110 #define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2111 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2112 #define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2113 #define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2114 #define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2115 #define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 2116
<> 128:9bcdf88f62b0 2117 /** @} End of group EFM32LG840F64_DMA */
<> 128:9bcdf88f62b0 2118
<> 128:9bcdf88f62b0 2119
<> 128:9bcdf88f62b0 2120
<> 128:9bcdf88f62b0 2121 /**************************************************************************//**
<> 128:9bcdf88f62b0 2122 * @defgroup EFM32LG840F64_CMU_BitFields EFM32LG840F64_CMU Bit Fields
<> 128:9bcdf88f62b0 2123 * @{
<> 128:9bcdf88f62b0 2124 *****************************************************************************/
<> 128:9bcdf88f62b0 2125
<> 128:9bcdf88f62b0 2126 /* Bit fields for CMU CTRL */
<> 128:9bcdf88f62b0 2127 #define _CMU_CTRL_RESETVALUE 0x000C262CUL /**< Default value for CMU_CTRL */
<> 128:9bcdf88f62b0 2128 #define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */
<> 128:9bcdf88f62b0 2129 #define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */
<> 128:9bcdf88f62b0 2130 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */
<> 128:9bcdf88f62b0 2131 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2132 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */
<> 128:9bcdf88f62b0 2133 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 2134 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 2135 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2136 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */
<> 128:9bcdf88f62b0 2137 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 2138 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 2139 #define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */
<> 128:9bcdf88f62b0 2140 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */
<> 128:9bcdf88f62b0 2141 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 2142 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 2143 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 2144 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2145 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 2146 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 2147 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 2148 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 2149 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2150 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 2151 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */
<> 128:9bcdf88f62b0 2152 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */
<> 128:9bcdf88f62b0 2153 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2154 #define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */
<> 128:9bcdf88f62b0 2155 #define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */
<> 128:9bcdf88f62b0 2156 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2157 #define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */
<> 128:9bcdf88f62b0 2158 #define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */
<> 128:9bcdf88f62b0 2159 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */
<> 128:9bcdf88f62b0 2160 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */
<> 128:9bcdf88f62b0 2161 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */
<> 128:9bcdf88f62b0 2162 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2163 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2164 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */
<> 128:9bcdf88f62b0 2165 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */
<> 128:9bcdf88f62b0 2166 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 2167 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 2168 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 2169 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2170 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 2171 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 2172 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 2173 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 2174 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2175 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 2176 #define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */
<> 128:9bcdf88f62b0 2177 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */
<> 128:9bcdf88f62b0 2178 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2179 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */
<> 128:9bcdf88f62b0 2180 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 2181 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 2182 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2183 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */
<> 128:9bcdf88f62b0 2184 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 2185 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 2186 #define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */
<> 128:9bcdf88f62b0 2187 #define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */
<> 128:9bcdf88f62b0 2188 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */
<> 128:9bcdf88f62b0 2189 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 2190 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2191 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 2192 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 2193 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2194 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 2195 #define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */
<> 128:9bcdf88f62b0 2196 #define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */
<> 128:9bcdf88f62b0 2197 #define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2198 #define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2199 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */
<> 128:9bcdf88f62b0 2200 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */
<> 128:9bcdf88f62b0 2201 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */
<> 128:9bcdf88f62b0 2202 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2203 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2204 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */
<> 128:9bcdf88f62b0 2205 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */
<> 128:9bcdf88f62b0 2206 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 2207 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 2208 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 2209 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2210 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 2211 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 2212 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 2213 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 2214 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2215 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 2216 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */
<> 128:9bcdf88f62b0 2217 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */
<> 128:9bcdf88f62b0 2218 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2219 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */
<> 128:9bcdf88f62b0 2220 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */
<> 128:9bcdf88f62b0 2221 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */
<> 128:9bcdf88f62b0 2222 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */
<> 128:9bcdf88f62b0 2223 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */
<> 128:9bcdf88f62b0 2224 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */
<> 128:9bcdf88f62b0 2225 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */
<> 128:9bcdf88f62b0 2226 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */
<> 128:9bcdf88f62b0 2227 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2228 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */
<> 128:9bcdf88f62b0 2229 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */
<> 128:9bcdf88f62b0 2230 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */
<> 128:9bcdf88f62b0 2231 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */
<> 128:9bcdf88f62b0 2232 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */
<> 128:9bcdf88f62b0 2233 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */
<> 128:9bcdf88f62b0 2234 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */
<> 128:9bcdf88f62b0 2235 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */
<> 128:9bcdf88f62b0 2236 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */
<> 128:9bcdf88f62b0 2237 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */
<> 128:9bcdf88f62b0 2238 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2239 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */
<> 128:9bcdf88f62b0 2240 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */
<> 128:9bcdf88f62b0 2241 #define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 2242 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */
<> 128:9bcdf88f62b0 2243 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */
<> 128:9bcdf88f62b0 2244 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */
<> 128:9bcdf88f62b0 2245 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */
<> 128:9bcdf88f62b0 2246 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */
<> 128:9bcdf88f62b0 2247 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2248 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */
<> 128:9bcdf88f62b0 2249 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */
<> 128:9bcdf88f62b0 2250 #define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 2251 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */
<> 128:9bcdf88f62b0 2252 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */
<> 128:9bcdf88f62b0 2253 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */
<> 128:9bcdf88f62b0 2254 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */
<> 128:9bcdf88f62b0 2255 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
<> 128:9bcdf88f62b0 2256 #define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */
<> 128:9bcdf88f62b0 2257 #define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */
<> 128:9bcdf88f62b0 2258 #define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */
<> 128:9bcdf88f62b0 2259 #define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2260 #define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */
<> 128:9bcdf88f62b0 2261 #define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 2262 #define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2263 #define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */
<> 128:9bcdf88f62b0 2264 #define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 2265 #define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */
<> 128:9bcdf88f62b0 2266 #define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */
<> 128:9bcdf88f62b0 2267 #define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */
<> 128:9bcdf88f62b0 2268 #define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2269 #define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 2270
<> 128:9bcdf88f62b0 2271 /* Bit fields for CMU HFCORECLKDIV */
<> 128:9bcdf88f62b0 2272 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2273 #define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2274 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2275 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2276 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2277 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2278 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2279 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2280 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2281 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2282 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2283 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2284 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2285 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2286 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2287 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2288 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2289 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2290 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2291 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2292 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2293 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2294 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2295 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2296 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2297 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2298 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */
<> 128:9bcdf88f62b0 2299 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */
<> 128:9bcdf88f62b0 2300 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */
<> 128:9bcdf88f62b0 2301 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2302 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2303 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2304 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2305 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2306 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 2307
<> 128:9bcdf88f62b0 2308 /* Bit fields for CMU HFPERCLKDIV */
<> 128:9bcdf88f62b0 2309 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2310 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2311 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2312 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2313 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2314 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2315 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2316 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2317 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2318 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2319 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2320 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2321 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2322 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2323 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2324 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2325 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2326 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2327 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2328 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2329 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2330 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2331 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2332 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2333 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2334 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2335 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */
<> 128:9bcdf88f62b0 2336 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */
<> 128:9bcdf88f62b0 2337 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */
<> 128:9bcdf88f62b0 2338 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2339 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 2340
<> 128:9bcdf88f62b0 2341 /* Bit fields for CMU HFRCOCTRL */
<> 128:9bcdf88f62b0 2342 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 2343 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 2344 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
<> 128:9bcdf88f62b0 2345 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */
<> 128:9bcdf88f62b0 2346 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 2347 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 2348 #define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */
<> 128:9bcdf88f62b0 2349 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */
<> 128:9bcdf88f62b0 2350 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 2351 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 2352 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 2353 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 2354 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 2355 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 2356 #define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 2357 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 2358 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 2359 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 2360 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 2361 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 2362 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 2363 #define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 2364 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */
<> 128:9bcdf88f62b0 2365 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */
<> 128:9bcdf88f62b0 2366 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 2367 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 2368
<> 128:9bcdf88f62b0 2369 /* Bit fields for CMU LFRCOCTRL */
<> 128:9bcdf88f62b0 2370 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */
<> 128:9bcdf88f62b0 2371 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */
<> 128:9bcdf88f62b0 2372 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
<> 128:9bcdf88f62b0 2373 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */
<> 128:9bcdf88f62b0 2374 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
<> 128:9bcdf88f62b0 2375 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
<> 128:9bcdf88f62b0 2376
<> 128:9bcdf88f62b0 2377 /* Bit fields for CMU AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 2378 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 2379 #define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 2380 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
<> 128:9bcdf88f62b0 2381 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */
<> 128:9bcdf88f62b0 2382 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 2383 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 2384 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */
<> 128:9bcdf88f62b0 2385 #define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */
<> 128:9bcdf88f62b0 2386 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 2387 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 2388 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 2389 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 2390 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 2391 #define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 2392 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 2393 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 2394 #define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 2395 #define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 2396 #define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 2397 #define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 2398 #define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 2399 #define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 2400
<> 128:9bcdf88f62b0 2401 /* Bit fields for CMU CALCTRL */
<> 128:9bcdf88f62b0 2402 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2403 #define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2404 #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */
<> 128:9bcdf88f62b0 2405 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */
<> 128:9bcdf88f62b0 2406 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2407 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2408 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2409 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2410 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2411 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2412 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2413 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2414 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2415 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2416 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2417 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2418 #define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */
<> 128:9bcdf88f62b0 2419 #define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */
<> 128:9bcdf88f62b0 2420 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2421 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2422 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2423 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2424 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2425 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2426 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2427 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2428 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2429 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2430 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2431 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2432 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2433 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2434 #define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */
<> 128:9bcdf88f62b0 2435 #define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */
<> 128:9bcdf88f62b0 2436 #define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */
<> 128:9bcdf88f62b0 2437 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2438 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */
<> 128:9bcdf88f62b0 2439
<> 128:9bcdf88f62b0 2440 /* Bit fields for CMU CALCNT */
<> 128:9bcdf88f62b0 2441 #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */
<> 128:9bcdf88f62b0 2442 #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */
<> 128:9bcdf88f62b0 2443 #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */
<> 128:9bcdf88f62b0 2444 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */
<> 128:9bcdf88f62b0 2445 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */
<> 128:9bcdf88f62b0 2446 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */
<> 128:9bcdf88f62b0 2447
<> 128:9bcdf88f62b0 2448 /* Bit fields for CMU OSCENCMD */
<> 128:9bcdf88f62b0 2449 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2450 #define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2451 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */
<> 128:9bcdf88f62b0 2452 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */
<> 128:9bcdf88f62b0 2453 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */
<> 128:9bcdf88f62b0 2454 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2455 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2456 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */
<> 128:9bcdf88f62b0 2457 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */
<> 128:9bcdf88f62b0 2458 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */
<> 128:9bcdf88f62b0 2459 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2460 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2461 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */
<> 128:9bcdf88f62b0 2462 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */
<> 128:9bcdf88f62b0 2463 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */
<> 128:9bcdf88f62b0 2464 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2465 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2466 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */
<> 128:9bcdf88f62b0 2467 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */
<> 128:9bcdf88f62b0 2468 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */
<> 128:9bcdf88f62b0 2469 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2470 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2471 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */
<> 128:9bcdf88f62b0 2472 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */
<> 128:9bcdf88f62b0 2473 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */
<> 128:9bcdf88f62b0 2474 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2475 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2476 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */
<> 128:9bcdf88f62b0 2477 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */
<> 128:9bcdf88f62b0 2478 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */
<> 128:9bcdf88f62b0 2479 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2480 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2481 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */
<> 128:9bcdf88f62b0 2482 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */
<> 128:9bcdf88f62b0 2483 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */
<> 128:9bcdf88f62b0 2484 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2485 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2486 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */
<> 128:9bcdf88f62b0 2487 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */
<> 128:9bcdf88f62b0 2488 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */
<> 128:9bcdf88f62b0 2489 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2490 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2491 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */
<> 128:9bcdf88f62b0 2492 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */
<> 128:9bcdf88f62b0 2493 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */
<> 128:9bcdf88f62b0 2494 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2495 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2496 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */
<> 128:9bcdf88f62b0 2497 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */
<> 128:9bcdf88f62b0 2498 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */
<> 128:9bcdf88f62b0 2499 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2500 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 2501
<> 128:9bcdf88f62b0 2502 /* Bit fields for CMU CMD */
<> 128:9bcdf88f62b0 2503 #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */
<> 128:9bcdf88f62b0 2504 #define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */
<> 128:9bcdf88f62b0 2505 #define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */
<> 128:9bcdf88f62b0 2506 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */
<> 128:9bcdf88f62b0 2507 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
<> 128:9bcdf88f62b0 2508 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */
<> 128:9bcdf88f62b0 2509 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */
<> 128:9bcdf88f62b0 2510 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */
<> 128:9bcdf88f62b0 2511 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */
<> 128:9bcdf88f62b0 2512 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */
<> 128:9bcdf88f62b0 2513 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */
<> 128:9bcdf88f62b0 2514 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */
<> 128:9bcdf88f62b0 2515 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */
<> 128:9bcdf88f62b0 2516 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */
<> 128:9bcdf88f62b0 2517 #define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */
<> 128:9bcdf88f62b0 2518 #define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */
<> 128:9bcdf88f62b0 2519 #define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */
<> 128:9bcdf88f62b0 2520 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
<> 128:9bcdf88f62b0 2521 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */
<> 128:9bcdf88f62b0 2522 #define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */
<> 128:9bcdf88f62b0 2523 #define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */
<> 128:9bcdf88f62b0 2524 #define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */
<> 128:9bcdf88f62b0 2525 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
<> 128:9bcdf88f62b0 2526 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */
<> 128:9bcdf88f62b0 2527
<> 128:9bcdf88f62b0 2528 /* Bit fields for CMU LFCLKSEL */
<> 128:9bcdf88f62b0 2529 #define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2530 #define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2531 #define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */
<> 128:9bcdf88f62b0 2532 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */
<> 128:9bcdf88f62b0 2533 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2534 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2535 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2536 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2537 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2538 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2539 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2540 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2541 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2542 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2543 #define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */
<> 128:9bcdf88f62b0 2544 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */
<> 128:9bcdf88f62b0 2545 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2546 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2547 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2548 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2549 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2550 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2551 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2552 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2553 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2554 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2555 #define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */
<> 128:9bcdf88f62b0 2556 #define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */
<> 128:9bcdf88f62b0 2557 #define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */
<> 128:9bcdf88f62b0 2558 #define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2559 #define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2560 #define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2561 #define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2562 #define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2563 #define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2564 #define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */
<> 128:9bcdf88f62b0 2565 #define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */
<> 128:9bcdf88f62b0 2566 #define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */
<> 128:9bcdf88f62b0 2567 #define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2568 #define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2569 #define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2570 #define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2571 #define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2572 #define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 2573
<> 128:9bcdf88f62b0 2574 /* Bit fields for CMU STATUS */
<> 128:9bcdf88f62b0 2575 #define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */
<> 128:9bcdf88f62b0 2576 #define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */
<> 128:9bcdf88f62b0 2577 #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */
<> 128:9bcdf88f62b0 2578 #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */
<> 128:9bcdf88f62b0 2579 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */
<> 128:9bcdf88f62b0 2580 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2581 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2582 #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */
<> 128:9bcdf88f62b0 2583 #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */
<> 128:9bcdf88f62b0 2584 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */
<> 128:9bcdf88f62b0 2585 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2586 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2587 #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */
<> 128:9bcdf88f62b0 2588 #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */
<> 128:9bcdf88f62b0 2589 #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */
<> 128:9bcdf88f62b0 2590 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2591 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2592 #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */
<> 128:9bcdf88f62b0 2593 #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */
<> 128:9bcdf88f62b0 2594 #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */
<> 128:9bcdf88f62b0 2595 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2596 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2597 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */
<> 128:9bcdf88f62b0 2598 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */
<> 128:9bcdf88f62b0 2599 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */
<> 128:9bcdf88f62b0 2600 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2601 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2602 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */
<> 128:9bcdf88f62b0 2603 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */
<> 128:9bcdf88f62b0 2604 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 128:9bcdf88f62b0 2605 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2606 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2607 #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */
<> 128:9bcdf88f62b0 2608 #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */
<> 128:9bcdf88f62b0 2609 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */
<> 128:9bcdf88f62b0 2610 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2611 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2612 #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */
<> 128:9bcdf88f62b0 2613 #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */
<> 128:9bcdf88f62b0 2614 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */
<> 128:9bcdf88f62b0 2615 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2616 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2617 #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */
<> 128:9bcdf88f62b0 2618 #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */
<> 128:9bcdf88f62b0 2619 #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */
<> 128:9bcdf88f62b0 2620 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2621 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2622 #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */
<> 128:9bcdf88f62b0 2623 #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */
<> 128:9bcdf88f62b0 2624 #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */
<> 128:9bcdf88f62b0 2625 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2626 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2627 #define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */
<> 128:9bcdf88f62b0 2628 #define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */
<> 128:9bcdf88f62b0 2629 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */
<> 128:9bcdf88f62b0 2630 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2631 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2632 #define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */
<> 128:9bcdf88f62b0 2633 #define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */
<> 128:9bcdf88f62b0 2634 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */
<> 128:9bcdf88f62b0 2635 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2636 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2637 #define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */
<> 128:9bcdf88f62b0 2638 #define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */
<> 128:9bcdf88f62b0 2639 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */
<> 128:9bcdf88f62b0 2640 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2641 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2642 #define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */
<> 128:9bcdf88f62b0 2643 #define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */
<> 128:9bcdf88f62b0 2644 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */
<> 128:9bcdf88f62b0 2645 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2646 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2647 #define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */
<> 128:9bcdf88f62b0 2648 #define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */
<> 128:9bcdf88f62b0 2649 #define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */
<> 128:9bcdf88f62b0 2650 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2651 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 2652
<> 128:9bcdf88f62b0 2653 /* Bit fields for CMU IF */
<> 128:9bcdf88f62b0 2654 #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */
<> 128:9bcdf88f62b0 2655 #define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */
<> 128:9bcdf88f62b0 2656 #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */
<> 128:9bcdf88f62b0 2657 #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
<> 128:9bcdf88f62b0 2658 #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
<> 128:9bcdf88f62b0 2659 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 2660 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 2661 #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */
<> 128:9bcdf88f62b0 2662 #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
<> 128:9bcdf88f62b0 2663 #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
<> 128:9bcdf88f62b0 2664 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 2665 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 2666 #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */
<> 128:9bcdf88f62b0 2667 #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
<> 128:9bcdf88f62b0 2668 #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
<> 128:9bcdf88f62b0 2669 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 2670 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 2671 #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */
<> 128:9bcdf88f62b0 2672 #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
<> 128:9bcdf88f62b0 2673 #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
<> 128:9bcdf88f62b0 2674 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 2675 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 2676 #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */
<> 128:9bcdf88f62b0 2677 #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
<> 128:9bcdf88f62b0 2678 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 128:9bcdf88f62b0 2679 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 2680 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 2681 #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */
<> 128:9bcdf88f62b0 2682 #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
<> 128:9bcdf88f62b0 2683 #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
<> 128:9bcdf88f62b0 2684 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 2685 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 2686 #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */
<> 128:9bcdf88f62b0 2687 #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
<> 128:9bcdf88f62b0 2688 #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
<> 128:9bcdf88f62b0 2689 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 2690 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 2691
<> 128:9bcdf88f62b0 2692 /* Bit fields for CMU IFS */
<> 128:9bcdf88f62b0 2693 #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */
<> 128:9bcdf88f62b0 2694 #define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */
<> 128:9bcdf88f62b0 2695 #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */
<> 128:9bcdf88f62b0 2696 #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
<> 128:9bcdf88f62b0 2697 #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
<> 128:9bcdf88f62b0 2698 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 2699 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 2700 #define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */
<> 128:9bcdf88f62b0 2701 #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
<> 128:9bcdf88f62b0 2702 #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
<> 128:9bcdf88f62b0 2703 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 2704 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 2705 #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */
<> 128:9bcdf88f62b0 2706 #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
<> 128:9bcdf88f62b0 2707 #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
<> 128:9bcdf88f62b0 2708 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 2709 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 2710 #define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */
<> 128:9bcdf88f62b0 2711 #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
<> 128:9bcdf88f62b0 2712 #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
<> 128:9bcdf88f62b0 2713 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 2714 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 2715 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */
<> 128:9bcdf88f62b0 2716 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
<> 128:9bcdf88f62b0 2717 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 128:9bcdf88f62b0 2718 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 2719 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 2720 #define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */
<> 128:9bcdf88f62b0 2721 #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
<> 128:9bcdf88f62b0 2722 #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
<> 128:9bcdf88f62b0 2723 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 2724 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 2725 #define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */
<> 128:9bcdf88f62b0 2726 #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
<> 128:9bcdf88f62b0 2727 #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
<> 128:9bcdf88f62b0 2728 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 2729 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 2730
<> 128:9bcdf88f62b0 2731 /* Bit fields for CMU IFC */
<> 128:9bcdf88f62b0 2732 #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */
<> 128:9bcdf88f62b0 2733 #define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */
<> 128:9bcdf88f62b0 2734 #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */
<> 128:9bcdf88f62b0 2735 #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
<> 128:9bcdf88f62b0 2736 #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
<> 128:9bcdf88f62b0 2737 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2738 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2739 #define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */
<> 128:9bcdf88f62b0 2740 #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
<> 128:9bcdf88f62b0 2741 #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
<> 128:9bcdf88f62b0 2742 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2743 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2744 #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */
<> 128:9bcdf88f62b0 2745 #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
<> 128:9bcdf88f62b0 2746 #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
<> 128:9bcdf88f62b0 2747 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2748 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2749 #define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */
<> 128:9bcdf88f62b0 2750 #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
<> 128:9bcdf88f62b0 2751 #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
<> 128:9bcdf88f62b0 2752 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2753 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2754 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */
<> 128:9bcdf88f62b0 2755 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
<> 128:9bcdf88f62b0 2756 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 128:9bcdf88f62b0 2757 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2758 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2759 #define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */
<> 128:9bcdf88f62b0 2760 #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
<> 128:9bcdf88f62b0 2761 #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
<> 128:9bcdf88f62b0 2762 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2763 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2764 #define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */
<> 128:9bcdf88f62b0 2765 #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
<> 128:9bcdf88f62b0 2766 #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
<> 128:9bcdf88f62b0 2767 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2768 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2769
<> 128:9bcdf88f62b0 2770 /* Bit fields for CMU IEN */
<> 128:9bcdf88f62b0 2771 #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */
<> 128:9bcdf88f62b0 2772 #define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */
<> 128:9bcdf88f62b0 2773 #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */
<> 128:9bcdf88f62b0 2774 #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
<> 128:9bcdf88f62b0 2775 #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
<> 128:9bcdf88f62b0 2776 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2777 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2778 #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */
<> 128:9bcdf88f62b0 2779 #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
<> 128:9bcdf88f62b0 2780 #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
<> 128:9bcdf88f62b0 2781 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2782 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2783 #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */
<> 128:9bcdf88f62b0 2784 #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
<> 128:9bcdf88f62b0 2785 #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
<> 128:9bcdf88f62b0 2786 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2787 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2788 #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */
<> 128:9bcdf88f62b0 2789 #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
<> 128:9bcdf88f62b0 2790 #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
<> 128:9bcdf88f62b0 2791 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2792 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2793 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */
<> 128:9bcdf88f62b0 2794 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
<> 128:9bcdf88f62b0 2795 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 128:9bcdf88f62b0 2796 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2797 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2798 #define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */
<> 128:9bcdf88f62b0 2799 #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
<> 128:9bcdf88f62b0 2800 #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
<> 128:9bcdf88f62b0 2801 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2802 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2803 #define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */
<> 128:9bcdf88f62b0 2804 #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
<> 128:9bcdf88f62b0 2805 #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
<> 128:9bcdf88f62b0 2806 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2807 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2808
<> 128:9bcdf88f62b0 2809 /* Bit fields for CMU HFCORECLKEN0 */
<> 128:9bcdf88f62b0 2810 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */
<> 128:9bcdf88f62b0 2811 #define _CMU_HFCORECLKEN0_MASK 0x00000013UL /**< Mask for CMU_HFCORECLKEN0 */
<> 128:9bcdf88f62b0 2812 #define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */
<> 128:9bcdf88f62b0 2813 #define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */
<> 128:9bcdf88f62b0 2814 #define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */
<> 128:9bcdf88f62b0 2815 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 128:9bcdf88f62b0 2816 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 128:9bcdf88f62b0 2817 #define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */
<> 128:9bcdf88f62b0 2818 #define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */
<> 128:9bcdf88f62b0 2819 #define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */
<> 128:9bcdf88f62b0 2820 #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 128:9bcdf88f62b0 2821 #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 128:9bcdf88f62b0 2822 #define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */
<> 128:9bcdf88f62b0 2823 #define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */
<> 128:9bcdf88f62b0 2824 #define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */
<> 128:9bcdf88f62b0 2825 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 128:9bcdf88f62b0 2826 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 128:9bcdf88f62b0 2827
<> 128:9bcdf88f62b0 2828 /* Bit fields for CMU HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2829 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2830 #define _CMU_HFPERCLKEN0_MASK 0x0003FFE7UL /**< Mask for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2831 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */
<> 128:9bcdf88f62b0 2832 #define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */
<> 128:9bcdf88f62b0 2833 #define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */
<> 128:9bcdf88f62b0 2834 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2835 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2836 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */
<> 128:9bcdf88f62b0 2837 #define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */
<> 128:9bcdf88f62b0 2838 #define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */
<> 128:9bcdf88f62b0 2839 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2840 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2841 #define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */
<> 128:9bcdf88f62b0 2842 #define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */
<> 128:9bcdf88f62b0 2843 #define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */
<> 128:9bcdf88f62b0 2844 #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2845 #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2846 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */
<> 128:9bcdf88f62b0 2847 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */
<> 128:9bcdf88f62b0 2848 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */
<> 128:9bcdf88f62b0 2849 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2850 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2851 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */
<> 128:9bcdf88f62b0 2852 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */
<> 128:9bcdf88f62b0 2853 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */
<> 128:9bcdf88f62b0 2854 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2855 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2856 #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */
<> 128:9bcdf88f62b0 2857 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */
<> 128:9bcdf88f62b0 2858 #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */
<> 128:9bcdf88f62b0 2859 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2860 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2861 #define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */
<> 128:9bcdf88f62b0 2862 #define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */
<> 128:9bcdf88f62b0 2863 #define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */
<> 128:9bcdf88f62b0 2864 #define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2865 #define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2866 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */
<> 128:9bcdf88f62b0 2867 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */
<> 128:9bcdf88f62b0 2868 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */
<> 128:9bcdf88f62b0 2869 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2870 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2871 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */
<> 128:9bcdf88f62b0 2872 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */
<> 128:9bcdf88f62b0 2873 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */
<> 128:9bcdf88f62b0 2874 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2875 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2876 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */
<> 128:9bcdf88f62b0 2877 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */
<> 128:9bcdf88f62b0 2878 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */
<> 128:9bcdf88f62b0 2879 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2880 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2881 #define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */
<> 128:9bcdf88f62b0 2882 #define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */
<> 128:9bcdf88f62b0 2883 #define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */
<> 128:9bcdf88f62b0 2884 #define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2885 #define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2886 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */
<> 128:9bcdf88f62b0 2887 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */
<> 128:9bcdf88f62b0 2888 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */
<> 128:9bcdf88f62b0 2889 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2890 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2891 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */
<> 128:9bcdf88f62b0 2892 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */
<> 128:9bcdf88f62b0 2893 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */
<> 128:9bcdf88f62b0 2894 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2895 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2896 #define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */
<> 128:9bcdf88f62b0 2897 #define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */
<> 128:9bcdf88f62b0 2898 #define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */
<> 128:9bcdf88f62b0 2899 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2900 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2901 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */
<> 128:9bcdf88f62b0 2902 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */
<> 128:9bcdf88f62b0 2903 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */
<> 128:9bcdf88f62b0 2904 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2905 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2906 #define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */
<> 128:9bcdf88f62b0 2907 #define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */
<> 128:9bcdf88f62b0 2908 #define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */
<> 128:9bcdf88f62b0 2909 #define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2910 #define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2911
<> 128:9bcdf88f62b0 2912 /* Bit fields for CMU SYNCBUSY */
<> 128:9bcdf88f62b0 2913 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2914 #define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2915 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */
<> 128:9bcdf88f62b0 2916 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */
<> 128:9bcdf88f62b0 2917 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */
<> 128:9bcdf88f62b0 2918 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2919 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2920 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */
<> 128:9bcdf88f62b0 2921 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2922 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2923 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2924 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2925 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */
<> 128:9bcdf88f62b0 2926 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */
<> 128:9bcdf88f62b0 2927 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */
<> 128:9bcdf88f62b0 2928 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2929 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2930 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */
<> 128:9bcdf88f62b0 2931 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 2932 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 2933 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2934 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2935
<> 128:9bcdf88f62b0 2936 /* Bit fields for CMU FREEZE */
<> 128:9bcdf88f62b0 2937 #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */
<> 128:9bcdf88f62b0 2938 #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */
<> 128:9bcdf88f62b0 2939 #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
<> 128:9bcdf88f62b0 2940 #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */
<> 128:9bcdf88f62b0 2941 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */
<> 128:9bcdf88f62b0 2942 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */
<> 128:9bcdf88f62b0 2943 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */
<> 128:9bcdf88f62b0 2944 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */
<> 128:9bcdf88f62b0 2945 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */
<> 128:9bcdf88f62b0 2946 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */
<> 128:9bcdf88f62b0 2947 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */
<> 128:9bcdf88f62b0 2948
<> 128:9bcdf88f62b0 2949 /* Bit fields for CMU LFACLKEN0 */
<> 128:9bcdf88f62b0 2950 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */
<> 128:9bcdf88f62b0 2951 #define _CMU_LFACLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFACLKEN0 */
<> 128:9bcdf88f62b0 2952 #define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */
<> 128:9bcdf88f62b0 2953 #define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */
<> 128:9bcdf88f62b0 2954 #define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */
<> 128:9bcdf88f62b0 2955 #define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
<> 128:9bcdf88f62b0 2956 #define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
<> 128:9bcdf88f62b0 2957 #define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */
<> 128:9bcdf88f62b0 2958 #define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */
<> 128:9bcdf88f62b0 2959 #define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */
<> 128:9bcdf88f62b0 2960 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
<> 128:9bcdf88f62b0 2961 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
<> 128:9bcdf88f62b0 2962 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */
<> 128:9bcdf88f62b0 2963 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */
<> 128:9bcdf88f62b0 2964 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */
<> 128:9bcdf88f62b0 2965 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
<> 128:9bcdf88f62b0 2966 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
<> 128:9bcdf88f62b0 2967 #define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */
<> 128:9bcdf88f62b0 2968 #define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */
<> 128:9bcdf88f62b0 2969 #define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */
<> 128:9bcdf88f62b0 2970 #define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
<> 128:9bcdf88f62b0 2971 #define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
<> 128:9bcdf88f62b0 2972
<> 128:9bcdf88f62b0 2973 /* Bit fields for CMU LFBCLKEN0 */
<> 128:9bcdf88f62b0 2974 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */
<> 128:9bcdf88f62b0 2975 #define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */
<> 128:9bcdf88f62b0 2976 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */
<> 128:9bcdf88f62b0 2977 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
<> 128:9bcdf88f62b0 2978 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */
<> 128:9bcdf88f62b0 2979 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
<> 128:9bcdf88f62b0 2980 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
<> 128:9bcdf88f62b0 2981 #define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */
<> 128:9bcdf88f62b0 2982 #define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */
<> 128:9bcdf88f62b0 2983 #define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */
<> 128:9bcdf88f62b0 2984 #define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
<> 128:9bcdf88f62b0 2985 #define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
<> 128:9bcdf88f62b0 2986
<> 128:9bcdf88f62b0 2987 /* Bit fields for CMU LFAPRESC0 */
<> 128:9bcdf88f62b0 2988 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2989 #define _CMU_LFAPRESC0_MASK 0x00003FF3UL /**< Mask for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2990 #define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */
<> 128:9bcdf88f62b0 2991 #define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */
<> 128:9bcdf88f62b0 2992 #define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2993 #define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2994 #define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2995 #define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2996 #define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2997 #define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2998 #define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2999 #define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3000 #define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */
<> 128:9bcdf88f62b0 3001 #define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */
<> 128:9bcdf88f62b0 3002 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3003 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3004 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3005 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3006 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3007 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3008 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3009 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3010 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3011 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3012 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3013 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3014 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3015 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3016 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3017 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3018 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3019 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3020 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3021 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3022 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3023 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3024 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3025 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3026 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3027 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3028 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3029 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3030 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3031 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3032 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3033 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3034 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */
<> 128:9bcdf88f62b0 3035 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */
<> 128:9bcdf88f62b0 3036 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3037 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3038 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3039 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3040 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3041 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3042 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3043 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3044 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3045 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3046 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3047 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3048 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3049 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3050 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3051 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3052 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3053 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3054 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3055 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3056 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3057 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3058 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3059 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3060 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3061 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3062 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3063 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3064 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3065 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3066 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3067 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3068 #define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */
<> 128:9bcdf88f62b0 3069 #define _CMU_LFAPRESC0_LCD_MASK 0x3000UL /**< Bit mask for CMU_LCD */
<> 128:9bcdf88f62b0 3070 #define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3071 #define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3072 #define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3073 #define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3074 #define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3075 #define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3076 #define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3077 #define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 3078
<> 128:9bcdf88f62b0 3079 /* Bit fields for CMU LFBPRESC0 */
<> 128:9bcdf88f62b0 3080 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 3081 #define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 3082 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
<> 128:9bcdf88f62b0 3083 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */
<> 128:9bcdf88f62b0 3084 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 3085 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 3086 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 3087 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 3088 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 3089 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 3090 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 3091 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 3092 #define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */
<> 128:9bcdf88f62b0 3093 #define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */
<> 128:9bcdf88f62b0 3094 #define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 3095 #define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 3096 #define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 3097 #define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 3098 #define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 3099 #define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 3100 #define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 3101 #define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 3102
<> 128:9bcdf88f62b0 3103 /* Bit fields for CMU PCNTCTRL */
<> 128:9bcdf88f62b0 3104 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3105 #define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3106 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */
<> 128:9bcdf88f62b0 3107 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */
<> 128:9bcdf88f62b0 3108 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */
<> 128:9bcdf88f62b0 3109 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3110 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3111 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */
<> 128:9bcdf88f62b0 3112 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */
<> 128:9bcdf88f62b0 3113 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */
<> 128:9bcdf88f62b0 3114 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3115 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3116 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3117 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3118 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3119 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3120 #define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */
<> 128:9bcdf88f62b0 3121 #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */
<> 128:9bcdf88f62b0 3122 #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */
<> 128:9bcdf88f62b0 3123 #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3124 #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3125 #define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */
<> 128:9bcdf88f62b0 3126 #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */
<> 128:9bcdf88f62b0 3127 #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */
<> 128:9bcdf88f62b0 3128 #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3129 #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3130 #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3131 #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3132 #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3133 #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3134 #define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */
<> 128:9bcdf88f62b0 3135 #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */
<> 128:9bcdf88f62b0 3136 #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */
<> 128:9bcdf88f62b0 3137 #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3138 #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3139 #define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */
<> 128:9bcdf88f62b0 3140 #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */
<> 128:9bcdf88f62b0 3141 #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */
<> 128:9bcdf88f62b0 3142 #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3143 #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3144 #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3145 #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3146 #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3147 #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 3148
<> 128:9bcdf88f62b0 3149 /* Bit fields for CMU LCDCTRL */
<> 128:9bcdf88f62b0 3150 #define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3151 #define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3152 #define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */
<> 128:9bcdf88f62b0 3153 #define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */
<> 128:9bcdf88f62b0 3154 #define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3155 #define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3156 #define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3) /**< Voltage Boost Enable */
<> 128:9bcdf88f62b0 3157 #define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */
<> 128:9bcdf88f62b0 3158 #define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */
<> 128:9bcdf88f62b0 3159 #define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3160 #define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3161 #define _CMU_LCDCTRL_VBFDIV_SHIFT 4 /**< Shift value for CMU_VBFDIV */
<> 128:9bcdf88f62b0 3162 #define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL /**< Bit mask for CMU_VBFDIV */
<> 128:9bcdf88f62b0 3163 #define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3164 #define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3165 #define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3166 #define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3167 #define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3168 #define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3169 #define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3170 #define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3171 #define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3172 #define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3173 #define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3174 #define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3175 #define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3176 #define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3177 #define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3178 #define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3179 #define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3180 #define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LCDCTRL */
<> 128:9bcdf88f62b0 3181
<> 128:9bcdf88f62b0 3182 /* Bit fields for CMU ROUTE */
<> 128:9bcdf88f62b0 3183 #define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */
<> 128:9bcdf88f62b0 3184 #define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */
<> 128:9bcdf88f62b0 3185 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */
<> 128:9bcdf88f62b0 3186 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */
<> 128:9bcdf88f62b0 3187 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */
<> 128:9bcdf88f62b0 3188 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
<> 128:9bcdf88f62b0 3189 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */
<> 128:9bcdf88f62b0 3190 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */
<> 128:9bcdf88f62b0 3191 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */
<> 128:9bcdf88f62b0 3192 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */
<> 128:9bcdf88f62b0 3193 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
<> 128:9bcdf88f62b0 3194 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */
<> 128:9bcdf88f62b0 3195 #define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */
<> 128:9bcdf88f62b0 3196 #define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */
<> 128:9bcdf88f62b0 3197 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */
<> 128:9bcdf88f62b0 3198 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
<> 128:9bcdf88f62b0 3199 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */
<> 128:9bcdf88f62b0 3200 #define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */
<> 128:9bcdf88f62b0 3201 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */
<> 128:9bcdf88f62b0 3202 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */
<> 128:9bcdf88f62b0 3203 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */
<> 128:9bcdf88f62b0 3204 #define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */
<> 128:9bcdf88f62b0 3205
<> 128:9bcdf88f62b0 3206 /* Bit fields for CMU LOCK */
<> 128:9bcdf88f62b0 3207 #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */
<> 128:9bcdf88f62b0 3208 #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */
<> 128:9bcdf88f62b0 3209 #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
<> 128:9bcdf88f62b0 3210 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
<> 128:9bcdf88f62b0 3211 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */
<> 128:9bcdf88f62b0 3212 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
<> 128:9bcdf88f62b0 3213 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */
<> 128:9bcdf88f62b0 3214 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */
<> 128:9bcdf88f62b0 3215 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */
<> 128:9bcdf88f62b0 3216 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
<> 128:9bcdf88f62b0 3217 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
<> 128:9bcdf88f62b0 3218 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
<> 128:9bcdf88f62b0 3219 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
<> 128:9bcdf88f62b0 3220 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
<> 128:9bcdf88f62b0 3221
<> 128:9bcdf88f62b0 3222 /** @} End of group EFM32LG840F64_CMU */
<> 128:9bcdf88f62b0 3223
<> 128:9bcdf88f62b0 3224
<> 128:9bcdf88f62b0 3225
<> 128:9bcdf88f62b0 3226 /**************************************************************************//**
<> 128:9bcdf88f62b0 3227 * @defgroup EFM32LG840F64_PRS_BitFields EFM32LG840F64_PRS Bit Fields
<> 128:9bcdf88f62b0 3228 * @{
<> 128:9bcdf88f62b0 3229 *****************************************************************************/
<> 128:9bcdf88f62b0 3230
<> 128:9bcdf88f62b0 3231 /* Bit fields for PRS SWPULSE */
<> 128:9bcdf88f62b0 3232 #define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3233 #define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3234 #define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */
<> 128:9bcdf88f62b0 3235 #define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */
<> 128:9bcdf88f62b0 3236 #define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */
<> 128:9bcdf88f62b0 3237 #define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3238 #define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3239 #define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */
<> 128:9bcdf88f62b0 3240 #define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */
<> 128:9bcdf88f62b0 3241 #define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */
<> 128:9bcdf88f62b0 3242 #define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3243 #define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3244 #define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */
<> 128:9bcdf88f62b0 3245 #define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */
<> 128:9bcdf88f62b0 3246 #define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */
<> 128:9bcdf88f62b0 3247 #define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3248 #define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3249 #define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */
<> 128:9bcdf88f62b0 3250 #define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */
<> 128:9bcdf88f62b0 3251 #define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */
<> 128:9bcdf88f62b0 3252 #define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3253 #define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3254 #define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */
<> 128:9bcdf88f62b0 3255 #define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */
<> 128:9bcdf88f62b0 3256 #define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */
<> 128:9bcdf88f62b0 3257 #define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3258 #define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3259 #define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */
<> 128:9bcdf88f62b0 3260 #define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */
<> 128:9bcdf88f62b0 3261 #define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */
<> 128:9bcdf88f62b0 3262 #define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3263 #define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3264 #define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */
<> 128:9bcdf88f62b0 3265 #define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */
<> 128:9bcdf88f62b0 3266 #define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */
<> 128:9bcdf88f62b0 3267 #define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3268 #define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3269 #define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */
<> 128:9bcdf88f62b0 3270 #define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */
<> 128:9bcdf88f62b0 3271 #define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */
<> 128:9bcdf88f62b0 3272 #define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3273 #define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3274 #define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */
<> 128:9bcdf88f62b0 3275 #define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */
<> 128:9bcdf88f62b0 3276 #define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */
<> 128:9bcdf88f62b0 3277 #define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3278 #define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3279 #define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */
<> 128:9bcdf88f62b0 3280 #define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */
<> 128:9bcdf88f62b0 3281 #define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */
<> 128:9bcdf88f62b0 3282 #define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3283 #define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3284 #define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */
<> 128:9bcdf88f62b0 3285 #define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */
<> 128:9bcdf88f62b0 3286 #define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */
<> 128:9bcdf88f62b0 3287 #define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3288 #define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3289 #define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */
<> 128:9bcdf88f62b0 3290 #define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */
<> 128:9bcdf88f62b0 3291 #define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */
<> 128:9bcdf88f62b0 3292 #define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3293 #define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 3294
<> 128:9bcdf88f62b0 3295 /* Bit fields for PRS SWLEVEL */
<> 128:9bcdf88f62b0 3296 #define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3297 #define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3298 #define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */
<> 128:9bcdf88f62b0 3299 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */
<> 128:9bcdf88f62b0 3300 #define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */
<> 128:9bcdf88f62b0 3301 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3302 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3303 #define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */
<> 128:9bcdf88f62b0 3304 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */
<> 128:9bcdf88f62b0 3305 #define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */
<> 128:9bcdf88f62b0 3306 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3307 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3308 #define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */
<> 128:9bcdf88f62b0 3309 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */
<> 128:9bcdf88f62b0 3310 #define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */
<> 128:9bcdf88f62b0 3311 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3312 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3313 #define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */
<> 128:9bcdf88f62b0 3314 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */
<> 128:9bcdf88f62b0 3315 #define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */
<> 128:9bcdf88f62b0 3316 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3317 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3318 #define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */
<> 128:9bcdf88f62b0 3319 #define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */
<> 128:9bcdf88f62b0 3320 #define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */
<> 128:9bcdf88f62b0 3321 #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3322 #define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3323 #define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */
<> 128:9bcdf88f62b0 3324 #define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */
<> 128:9bcdf88f62b0 3325 #define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */
<> 128:9bcdf88f62b0 3326 #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3327 #define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3328 #define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */
<> 128:9bcdf88f62b0 3329 #define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */
<> 128:9bcdf88f62b0 3330 #define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */
<> 128:9bcdf88f62b0 3331 #define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3332 #define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3333 #define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */
<> 128:9bcdf88f62b0 3334 #define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */
<> 128:9bcdf88f62b0 3335 #define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */
<> 128:9bcdf88f62b0 3336 #define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3337 #define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3338 #define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */
<> 128:9bcdf88f62b0 3339 #define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */
<> 128:9bcdf88f62b0 3340 #define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */
<> 128:9bcdf88f62b0 3341 #define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3342 #define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3343 #define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */
<> 128:9bcdf88f62b0 3344 #define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */
<> 128:9bcdf88f62b0 3345 #define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */
<> 128:9bcdf88f62b0 3346 #define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3347 #define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3348 #define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */
<> 128:9bcdf88f62b0 3349 #define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */
<> 128:9bcdf88f62b0 3350 #define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */
<> 128:9bcdf88f62b0 3351 #define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3352 #define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3353 #define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */
<> 128:9bcdf88f62b0 3354 #define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */
<> 128:9bcdf88f62b0 3355 #define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */
<> 128:9bcdf88f62b0 3356 #define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3357 #define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 3358
<> 128:9bcdf88f62b0 3359 /* Bit fields for PRS ROUTE */
<> 128:9bcdf88f62b0 3360 #define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */
<> 128:9bcdf88f62b0 3361 #define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */
<> 128:9bcdf88f62b0 3362 #define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */
<> 128:9bcdf88f62b0 3363 #define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */
<> 128:9bcdf88f62b0 3364 #define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */
<> 128:9bcdf88f62b0 3365 #define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
<> 128:9bcdf88f62b0 3366 #define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */
<> 128:9bcdf88f62b0 3367 #define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */
<> 128:9bcdf88f62b0 3368 #define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */
<> 128:9bcdf88f62b0 3369 #define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */
<> 128:9bcdf88f62b0 3370 #define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
<> 128:9bcdf88f62b0 3371 #define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */
<> 128:9bcdf88f62b0 3372 #define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */
<> 128:9bcdf88f62b0 3373 #define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */
<> 128:9bcdf88f62b0 3374 #define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */
<> 128:9bcdf88f62b0 3375 #define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
<> 128:9bcdf88f62b0 3376 #define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */
<> 128:9bcdf88f62b0 3377 #define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */
<> 128:9bcdf88f62b0 3378 #define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */
<> 128:9bcdf88f62b0 3379 #define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */
<> 128:9bcdf88f62b0 3380 #define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
<> 128:9bcdf88f62b0 3381 #define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */
<> 128:9bcdf88f62b0 3382 #define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */
<> 128:9bcdf88f62b0 3383 #define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */
<> 128:9bcdf88f62b0 3384 #define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */
<> 128:9bcdf88f62b0 3385 #define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
<> 128:9bcdf88f62b0 3386 #define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */
<> 128:9bcdf88f62b0 3387 #define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */
<> 128:9bcdf88f62b0 3388 #define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */
<> 128:9bcdf88f62b0 3389 #define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */
<> 128:9bcdf88f62b0 3390
<> 128:9bcdf88f62b0 3391 /* Bit fields for PRS CH_CTRL */
<> 128:9bcdf88f62b0 3392 #define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3393 #define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3394 #define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */
<> 128:9bcdf88f62b0 3395 #define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */
<> 128:9bcdf88f62b0 3396 #define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3397 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3398 #define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3399 #define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3400 #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3401 #define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3402 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3403 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3404 #define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3405 #define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3406 #define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3407 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3408 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3409 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3410 #define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3411 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3412 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3413 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3414 #define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3415 #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3416 #define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3417 #define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3418 #define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3419 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3420 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3421 #define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3422 #define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3423 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3424 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3425 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3426 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3427 #define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3428 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3429 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3430 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3431 #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3432 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3433 #define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3434 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3435 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3436 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3437 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3438 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3439 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3440 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3441 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3442 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3443 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3444 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3445 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3446 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3447 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3448 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3449 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3450 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3451 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3452 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3453 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3454 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3455 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3456 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3457 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3458 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3459 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3460 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3461 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3462 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3463 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3464 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3465 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3466 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3467 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3468 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3469 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3470 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3471 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3472 #define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3473 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3474 #define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3475 #define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3476 #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3477 #define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3478 #define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3479 #define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3480 #define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3481 #define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3482 #define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3483 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3484 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3485 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3486 #define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3487 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3488 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3489 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3490 #define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3491 #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3492 #define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3493 #define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3494 #define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3495 #define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3496 #define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3497 #define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3498 #define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3499 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3500 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3501 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3502 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3503 #define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3504 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3505 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3506 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3507 #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3508 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3509 #define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3510 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3511 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3512 #define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3513 #define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3514 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3515 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3516 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3517 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3518 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3519 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3520 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3521 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3522 #define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3523 #define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3524 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3525 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3526 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3527 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3528 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3529 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3530 #define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3531 #define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3532 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3533 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3534 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3535 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3536 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3537 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3538 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3539 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3540 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3541 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3542 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3543 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3544 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3545 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3546 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3547 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3548 #define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */
<> 128:9bcdf88f62b0 3549 #define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */
<> 128:9bcdf88f62b0 3550 #define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3551 #define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3552 #define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3553 #define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3554 #define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3555 #define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3556 #define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3557 #define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3558 #define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3559 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3560 #define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3561 #define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3562 #define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3563 #define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3564 #define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3565 #define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3566 #define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3567 #define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3568 #define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3569 #define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3570 #define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3571 #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3572 #define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3573 #define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3574 #define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3575 #define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3576 #define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3577 #define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3578 #define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3579 #define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3580 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3581 #define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3582 #define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3583 #define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3584 #define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3585 #define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3586 #define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3587 #define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3588 #define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3589 #define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3590 #define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3591 #define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3592 #define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */
<> 128:9bcdf88f62b0 3593 #define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */
<> 128:9bcdf88f62b0 3594 #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3595 #define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3596 #define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3597 #define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3598 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3599 #define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3600 #define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3601 #define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3602 #define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3603 #define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3604 #define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */
<> 128:9bcdf88f62b0 3605 #define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */
<> 128:9bcdf88f62b0 3606 #define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */
<> 128:9bcdf88f62b0 3607 #define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3608 #define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 3609
<> 128:9bcdf88f62b0 3610 /** @} End of group EFM32LG840F64_PRS */
<> 128:9bcdf88f62b0 3611
<> 128:9bcdf88f62b0 3612
<> 128:9bcdf88f62b0 3613
<> 128:9bcdf88f62b0 3614 /**************************************************************************//**
<> 128:9bcdf88f62b0 3615 * @defgroup EFM32LG840F64_UNLOCK EFM32LG840F64 Unlock Codes
<> 128:9bcdf88f62b0 3616 * @{
<> 128:9bcdf88f62b0 3617 *****************************************************************************/
<> 128:9bcdf88f62b0 3618 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
<> 128:9bcdf88f62b0 3619 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
<> 128:9bcdf88f62b0 3620 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
<> 128:9bcdf88f62b0 3621 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
<> 128:9bcdf88f62b0 3622 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
<> 128:9bcdf88f62b0 3623 #define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
<> 128:9bcdf88f62b0 3624
<> 128:9bcdf88f62b0 3625 /** @} End of group EFM32LG840F64_UNLOCK */
<> 128:9bcdf88f62b0 3626
<> 128:9bcdf88f62b0 3627 /** @} End of group EFM32LG840F64_BitFields */
<> 128:9bcdf88f62b0 3628
<> 128:9bcdf88f62b0 3629 /**************************************************************************//**
<> 128:9bcdf88f62b0 3630 * @defgroup EFM32LG840F64_Alternate_Function EFM32LG840F64 Alternate Function
<> 128:9bcdf88f62b0 3631 * @{
<> 128:9bcdf88f62b0 3632 *****************************************************************************/
<> 128:9bcdf88f62b0 3633
<> 128:9bcdf88f62b0 3634 #include "efm32lg_af_ports.h"
<> 128:9bcdf88f62b0 3635 #include "efm32lg_af_pins.h"
<> 128:9bcdf88f62b0 3636
<> 128:9bcdf88f62b0 3637 /** @} End of group EFM32LG840F64_Alternate_Function */
<> 128:9bcdf88f62b0 3638
<> 128:9bcdf88f62b0 3639 /**************************************************************************//**
<> 128:9bcdf88f62b0 3640 * @brief Set the value of a bit field within a register.
<> 128:9bcdf88f62b0 3641 *
<> 128:9bcdf88f62b0 3642 * @param REG
<> 128:9bcdf88f62b0 3643 * The register to update
<> 128:9bcdf88f62b0 3644 * @param MASK
<> 128:9bcdf88f62b0 3645 * The mask for the bit field to update
<> 128:9bcdf88f62b0 3646 * @param VALUE
<> 128:9bcdf88f62b0 3647 * The value to write to the bit field
<> 128:9bcdf88f62b0 3648 * @param OFFSET
<> 128:9bcdf88f62b0 3649 * The number of bits that the field is offset within the register.
<> 128:9bcdf88f62b0 3650 * 0 (zero) means LSB.
<> 128:9bcdf88f62b0 3651 *****************************************************************************/
<> 128:9bcdf88f62b0 3652 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
<> 128:9bcdf88f62b0 3653 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
<> 128:9bcdf88f62b0 3654
<> 128:9bcdf88f62b0 3655 /** @} End of group EFM32LG840F64 */
<> 128:9bcdf88f62b0 3656
<> 128:9bcdf88f62b0 3657 /** @} End of group Parts */
<> 128:9bcdf88f62b0 3658
<> 128:9bcdf88f62b0 3659 #ifdef __cplusplus
<> 128:9bcdf88f62b0 3660 }
<> 128:9bcdf88f62b0 3661 #endif
<> 128:9bcdf88f62b0 3662 #endif /* EFM32LG840F64_H */