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TARGET_NUCLEO_L486RG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_pwr.h@140:97feb9bacc10, 2017-04-12 (annotated)
- Committer:
- <>
- Date:
- Wed Apr 12 16:07:08 2017 +0100
- Revision:
- 140:97feb9bacc10
- Parent:
- 128:9bcdf88f62b0
- Child:
- 145:64910690c574
Release 140 of the mbed library
Ports for Upcoming Targets
3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841
3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992
Fixes and Changes
3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951
4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021
3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979
3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the https://github.com/ARMmbed/mbed-os/pull/3990
4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003
4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012
4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020
4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065
4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014
4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030
4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109
3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Kojto | 122:f9eeca106725 | 1 | /** |
Kojto | 122:f9eeca106725 | 2 | ****************************************************************************** |
Kojto | 122:f9eeca106725 | 3 | * @file stm32l4xx_ll_pwr.h |
Kojto | 122:f9eeca106725 | 4 | * @author MCD Application Team |
Kojto | 122:f9eeca106725 | 5 | * @version V1.5.1 |
Kojto | 122:f9eeca106725 | 6 | * @date 31-May-2016 |
Kojto | 122:f9eeca106725 | 7 | * @brief Header file of PWR LL module. |
Kojto | 122:f9eeca106725 | 8 | ****************************************************************************** |
Kojto | 122:f9eeca106725 | 9 | * @attention |
Kojto | 122:f9eeca106725 | 10 | * |
Kojto | 122:f9eeca106725 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
Kojto | 122:f9eeca106725 | 12 | * |
Kojto | 122:f9eeca106725 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
Kojto | 122:f9eeca106725 | 14 | * are permitted provided that the following conditions are met: |
Kojto | 122:f9eeca106725 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
Kojto | 122:f9eeca106725 | 16 | * this list of conditions and the following disclaimer. |
Kojto | 122:f9eeca106725 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
Kojto | 122:f9eeca106725 | 18 | * this list of conditions and the following disclaimer in the documentation |
Kojto | 122:f9eeca106725 | 19 | * and/or other materials provided with the distribution. |
Kojto | 122:f9eeca106725 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
Kojto | 122:f9eeca106725 | 21 | * may be used to endorse or promote products derived from this software |
Kojto | 122:f9eeca106725 | 22 | * without specific prior written permission. |
Kojto | 122:f9eeca106725 | 23 | * |
Kojto | 122:f9eeca106725 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
Kojto | 122:f9eeca106725 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
Kojto | 122:f9eeca106725 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
Kojto | 122:f9eeca106725 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
Kojto | 122:f9eeca106725 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
Kojto | 122:f9eeca106725 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
Kojto | 122:f9eeca106725 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
Kojto | 122:f9eeca106725 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
Kojto | 122:f9eeca106725 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
Kojto | 122:f9eeca106725 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Kojto | 122:f9eeca106725 | 34 | * |
Kojto | 122:f9eeca106725 | 35 | ****************************************************************************** |
Kojto | 122:f9eeca106725 | 36 | */ |
Kojto | 122:f9eeca106725 | 37 | |
Kojto | 122:f9eeca106725 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
Kojto | 122:f9eeca106725 | 39 | #ifndef __STM32L4xx_LL_PWR_H |
Kojto | 122:f9eeca106725 | 40 | #define __STM32L4xx_LL_PWR_H |
Kojto | 122:f9eeca106725 | 41 | |
Kojto | 122:f9eeca106725 | 42 | #ifdef __cplusplus |
Kojto | 122:f9eeca106725 | 43 | extern "C" { |
Kojto | 122:f9eeca106725 | 44 | #endif |
Kojto | 122:f9eeca106725 | 45 | |
Kojto | 122:f9eeca106725 | 46 | /* Includes ------------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 47 | #include "stm32l4xx.h" |
Kojto | 122:f9eeca106725 | 48 | |
Kojto | 122:f9eeca106725 | 49 | /** @addtogroup STM32L4xx_LL_Driver |
Kojto | 122:f9eeca106725 | 50 | * @{ |
Kojto | 122:f9eeca106725 | 51 | */ |
Kojto | 122:f9eeca106725 | 52 | |
Kojto | 122:f9eeca106725 | 53 | #if defined(PWR) |
Kojto | 122:f9eeca106725 | 54 | |
Kojto | 122:f9eeca106725 | 55 | /** @defgroup PWR_LL PWR |
Kojto | 122:f9eeca106725 | 56 | * @{ |
Kojto | 122:f9eeca106725 | 57 | */ |
Kojto | 122:f9eeca106725 | 58 | |
Kojto | 122:f9eeca106725 | 59 | /* Private types -------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 60 | /* Private variables ---------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 61 | |
Kojto | 122:f9eeca106725 | 62 | /* Private constants ---------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 63 | |
Kojto | 122:f9eeca106725 | 64 | /* Private macros ------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 65 | |
Kojto | 122:f9eeca106725 | 66 | /* Exported types ------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 67 | /* Exported constants --------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 68 | /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants |
Kojto | 122:f9eeca106725 | 69 | * @{ |
Kojto | 122:f9eeca106725 | 70 | */ |
Kojto | 122:f9eeca106725 | 71 | |
Kojto | 122:f9eeca106725 | 72 | /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines |
Kojto | 122:f9eeca106725 | 73 | * @brief Flags defines which can be used with LL_PWR_WriteReg function |
Kojto | 122:f9eeca106725 | 74 | * @{ |
Kojto | 122:f9eeca106725 | 75 | */ |
Kojto | 122:f9eeca106725 | 76 | #define LL_PWR_SCR_CSBF PWR_SCR_CSBF |
Kojto | 122:f9eeca106725 | 77 | #define LL_PWR_SCR_CWUF PWR_SCR_CWUF |
Kojto | 122:f9eeca106725 | 78 | #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5 |
Kojto | 122:f9eeca106725 | 79 | #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4 |
Kojto | 122:f9eeca106725 | 80 | #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3 |
Kojto | 122:f9eeca106725 | 81 | #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2 |
Kojto | 122:f9eeca106725 | 82 | #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1 |
Kojto | 122:f9eeca106725 | 83 | /** |
Kojto | 122:f9eeca106725 | 84 | * @} |
Kojto | 122:f9eeca106725 | 85 | */ |
Kojto | 122:f9eeca106725 | 86 | |
Kojto | 122:f9eeca106725 | 87 | /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines |
Kojto | 122:f9eeca106725 | 88 | * @brief Flags defines which can be used with LL_PWR_ReadReg function |
Kojto | 122:f9eeca106725 | 89 | * @{ |
Kojto | 122:f9eeca106725 | 90 | */ |
Kojto | 122:f9eeca106725 | 91 | #define LL_PWR_SR1_WUFI PWR_SR1_WUFI |
Kojto | 122:f9eeca106725 | 92 | #define LL_PWR_SR1_SBF PWR_SR1_SBF |
Kojto | 122:f9eeca106725 | 93 | #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5 |
Kojto | 122:f9eeca106725 | 94 | #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4 |
Kojto | 122:f9eeca106725 | 95 | #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3 |
Kojto | 122:f9eeca106725 | 96 | #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2 |
Kojto | 122:f9eeca106725 | 97 | #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1 |
Kojto | 122:f9eeca106725 | 98 | #define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4 |
Kojto | 122:f9eeca106725 | 99 | #define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3 |
Kojto | 122:f9eeca106725 | 100 | #if defined(PWR_SR2_PVMO2) |
Kojto | 122:f9eeca106725 | 101 | #define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2 |
Kojto | 122:f9eeca106725 | 102 | #endif /* PWR_SR2_PVMO2 */ |
Kojto | 122:f9eeca106725 | 103 | #define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1 |
Kojto | 122:f9eeca106725 | 104 | #define LL_PWR_SR2_PVDO PWR_SR2_PVDO |
Kojto | 122:f9eeca106725 | 105 | #define LL_PWR_SR2_VOSF PWR_SR2_VOSF |
Kojto | 122:f9eeca106725 | 106 | #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF |
Kojto | 122:f9eeca106725 | 107 | #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS |
Kojto | 122:f9eeca106725 | 108 | /** |
Kojto | 122:f9eeca106725 | 109 | * @} |
Kojto | 122:f9eeca106725 | 110 | */ |
Kojto | 122:f9eeca106725 | 111 | |
Kojto | 122:f9eeca106725 | 112 | /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE |
Kojto | 122:f9eeca106725 | 113 | * @{ |
Kojto | 122:f9eeca106725 | 114 | */ |
Kojto | 122:f9eeca106725 | 115 | #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0) |
Kojto | 122:f9eeca106725 | 116 | #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1) |
Kojto | 122:f9eeca106725 | 117 | /** |
Kojto | 122:f9eeca106725 | 118 | * @} |
Kojto | 122:f9eeca106725 | 119 | */ |
Kojto | 122:f9eeca106725 | 120 | |
Kojto | 122:f9eeca106725 | 121 | /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR |
Kojto | 122:f9eeca106725 | 122 | * @{ |
Kojto | 122:f9eeca106725 | 123 | */ |
Kojto | 122:f9eeca106725 | 124 | #define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0) |
Kojto | 122:f9eeca106725 | 125 | #define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1) |
Kojto | 122:f9eeca106725 | 126 | #define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_STOP2) |
Kojto | 122:f9eeca106725 | 127 | #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY) |
Kojto | 122:f9eeca106725 | 128 | #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN) |
Kojto | 122:f9eeca106725 | 129 | /** |
Kojto | 122:f9eeca106725 | 130 | * @} |
Kojto | 122:f9eeca106725 | 131 | */ |
Kojto | 122:f9eeca106725 | 132 | |
Kojto | 122:f9eeca106725 | 133 | /** @defgroup PWR_LL_EC_PVM_VDDUSB_1 PVM VDDUSB 1 |
Kojto | 122:f9eeca106725 | 134 | * @{ |
Kojto | 122:f9eeca106725 | 135 | */ |
Kojto | 122:f9eeca106725 | 136 | #if defined(USB_OTG_FS) |
Kojto | 122:f9eeca106725 | 137 | #define LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2V */ |
Kojto | 122:f9eeca106725 | 138 | #endif /* USB_OTG_FS */ |
Kojto | 122:f9eeca106725 | 139 | #if defined(PWR_CR2_PVME2) |
Kojto | 122:f9eeca106725 | 140 | #define LL_PWR_PVM_VDDIO2_0_9V (PWR_CR2_PVME2) /* Monitoring VDDIO2 vs. 0.9V */ |
Kojto | 122:f9eeca106725 | 141 | #endif /* PWR_CR2_PVME2 */ |
Kojto | 122:f9eeca106725 | 142 | #define LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */ |
Kojto | 122:f9eeca106725 | 143 | #define LL_PWR_PVM_VDDA_2_2V (PWR_CR2_PVME4) /* Monitoring VDDA vs. 2.2V */ |
Kojto | 122:f9eeca106725 | 144 | /** |
Kojto | 122:f9eeca106725 | 145 | * @} |
Kojto | 122:f9eeca106725 | 146 | */ |
Kojto | 122:f9eeca106725 | 147 | |
Kojto | 122:f9eeca106725 | 148 | /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL |
Kojto | 122:f9eeca106725 | 149 | * @{ |
Kojto | 122:f9eeca106725 | 150 | */ |
Kojto | 122:f9eeca106725 | 151 | #define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */ |
Kojto | 122:f9eeca106725 | 152 | #define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */ |
Kojto | 122:f9eeca106725 | 153 | #define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */ |
Kojto | 122:f9eeca106725 | 154 | #define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */ |
Kojto | 122:f9eeca106725 | 155 | #define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */ |
Kojto | 122:f9eeca106725 | 156 | #define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */ |
Kojto | 122:f9eeca106725 | 157 | #define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */ |
Kojto | 122:f9eeca106725 | 158 | #define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */ |
Kojto | 122:f9eeca106725 | 159 | /** |
Kojto | 122:f9eeca106725 | 160 | * @} |
Kojto | 122:f9eeca106725 | 161 | */ |
Kojto | 122:f9eeca106725 | 162 | |
Kojto | 122:f9eeca106725 | 163 | /** @defgroup PWR_LL_EC_WAKEUP WAKEUP |
Kojto | 122:f9eeca106725 | 164 | * @{ |
Kojto | 122:f9eeca106725 | 165 | */ |
Kojto | 122:f9eeca106725 | 166 | #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1) |
Kojto | 122:f9eeca106725 | 167 | #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2) |
Kojto | 122:f9eeca106725 | 168 | #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3) |
Kojto | 122:f9eeca106725 | 169 | #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4) |
Kojto | 122:f9eeca106725 | 170 | #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5) |
Kojto | 122:f9eeca106725 | 171 | /** |
Kojto | 122:f9eeca106725 | 172 | * @} |
Kojto | 122:f9eeca106725 | 173 | */ |
Kojto | 122:f9eeca106725 | 174 | |
Kojto | 122:f9eeca106725 | 175 | /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR |
Kojto | 122:f9eeca106725 | 176 | * @{ |
Kojto | 122:f9eeca106725 | 177 | */ |
Kojto | 122:f9eeca106725 | 178 | #define LL_PWR_BATT_CHARG_RESISTOR_5K ((uint32_t)0x00000000) |
Kojto | 122:f9eeca106725 | 179 | #define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS) |
Kojto | 122:f9eeca106725 | 180 | /** |
Kojto | 122:f9eeca106725 | 181 | * @} |
Kojto | 122:f9eeca106725 | 182 | */ |
Kojto | 122:f9eeca106725 | 183 | |
Kojto | 122:f9eeca106725 | 184 | /** @defgroup PWR_LL_EC_GPIO GPIO |
Kojto | 122:f9eeca106725 | 185 | * @{ |
Kojto | 122:f9eeca106725 | 186 | */ |
Kojto | 122:f9eeca106725 | 187 | #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA))) |
Kojto | 122:f9eeca106725 | 188 | #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB))) |
Kojto | 122:f9eeca106725 | 189 | #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC))) |
Kojto | 122:f9eeca106725 | 190 | #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD))) |
Kojto | 122:f9eeca106725 | 191 | #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE))) |
Kojto | 122:f9eeca106725 | 192 | #if defined(GPIOF) |
Kojto | 122:f9eeca106725 | 193 | #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF))) |
Kojto | 122:f9eeca106725 | 194 | #endif /* GPIOF */ |
Kojto | 122:f9eeca106725 | 195 | #if defined(GPIOG) |
Kojto | 122:f9eeca106725 | 196 | #define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG))) |
Kojto | 122:f9eeca106725 | 197 | #endif /* GPIOG */ |
Kojto | 122:f9eeca106725 | 198 | #define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH))) |
Kojto | 122:f9eeca106725 | 199 | /** |
Kojto | 122:f9eeca106725 | 200 | * @} |
Kojto | 122:f9eeca106725 | 201 | */ |
Kojto | 122:f9eeca106725 | 202 | |
Kojto | 122:f9eeca106725 | 203 | /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT |
Kojto | 122:f9eeca106725 | 204 | * @{ |
Kojto | 122:f9eeca106725 | 205 | */ |
Kojto | 122:f9eeca106725 | 206 | #define LL_PWR_GPIO_BIT_0 ((uint32_t)0x00000001) |
Kojto | 122:f9eeca106725 | 207 | #define LL_PWR_GPIO_BIT_1 ((uint32_t)0x00000002) |
Kojto | 122:f9eeca106725 | 208 | #define LL_PWR_GPIO_BIT_2 ((uint32_t)0x00000004) |
Kojto | 122:f9eeca106725 | 209 | #define LL_PWR_GPIO_BIT_3 ((uint32_t)0x00000008) |
Kojto | 122:f9eeca106725 | 210 | #define LL_PWR_GPIO_BIT_4 ((uint32_t)0x00000010) |
Kojto | 122:f9eeca106725 | 211 | #define LL_PWR_GPIO_BIT_5 ((uint32_t)0x00000020) |
Kojto | 122:f9eeca106725 | 212 | #define LL_PWR_GPIO_BIT_6 ((uint32_t)0x00000040) |
Kojto | 122:f9eeca106725 | 213 | #define LL_PWR_GPIO_BIT_7 ((uint32_t)0x00000080) |
Kojto | 122:f9eeca106725 | 214 | #define LL_PWR_GPIO_BIT_8 ((uint32_t)0x00000100) |
Kojto | 122:f9eeca106725 | 215 | #define LL_PWR_GPIO_BIT_9 ((uint32_t)0x00000200) |
Kojto | 122:f9eeca106725 | 216 | #define LL_PWR_GPIO_BIT_10 ((uint32_t)0x00000400) |
Kojto | 122:f9eeca106725 | 217 | #define LL_PWR_GPIO_BIT_11 ((uint32_t)0x00000800) |
Kojto | 122:f9eeca106725 | 218 | #define LL_PWR_GPIO_BIT_12 ((uint32_t)0x00001000) |
Kojto | 122:f9eeca106725 | 219 | #define LL_PWR_GPIO_BIT_13 ((uint32_t)0x00002000) |
Kojto | 122:f9eeca106725 | 220 | #define LL_PWR_GPIO_BIT_14 ((uint32_t)0x00004000) |
Kojto | 122:f9eeca106725 | 221 | #define LL_PWR_GPIO_BIT_15 ((uint32_t)0x00008000) |
Kojto | 122:f9eeca106725 | 222 | /** |
Kojto | 122:f9eeca106725 | 223 | * @} |
Kojto | 122:f9eeca106725 | 224 | */ |
Kojto | 122:f9eeca106725 | 225 | |
Kojto | 122:f9eeca106725 | 226 | /** |
Kojto | 122:f9eeca106725 | 227 | * @} |
Kojto | 122:f9eeca106725 | 228 | */ |
Kojto | 122:f9eeca106725 | 229 | |
Kojto | 122:f9eeca106725 | 230 | /* Exported macro ------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 231 | /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros |
Kojto | 122:f9eeca106725 | 232 | * @{ |
Kojto | 122:f9eeca106725 | 233 | */ |
Kojto | 122:f9eeca106725 | 234 | |
Kojto | 122:f9eeca106725 | 235 | /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros |
Kojto | 122:f9eeca106725 | 236 | * @{ |
Kojto | 122:f9eeca106725 | 237 | */ |
Kojto | 122:f9eeca106725 | 238 | |
Kojto | 122:f9eeca106725 | 239 | /** |
Kojto | 122:f9eeca106725 | 240 | * @brief Write a value in PWR register |
Kojto | 122:f9eeca106725 | 241 | * @param __REG__ Register to be written |
Kojto | 122:f9eeca106725 | 242 | * @param __VALUE__ Value to be written in the register |
Kojto | 122:f9eeca106725 | 243 | * @retval None |
Kojto | 122:f9eeca106725 | 244 | */ |
Kojto | 122:f9eeca106725 | 245 | #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) |
Kojto | 122:f9eeca106725 | 246 | |
Kojto | 122:f9eeca106725 | 247 | /** |
Kojto | 122:f9eeca106725 | 248 | * @brief Read a value in PWR register |
Kojto | 122:f9eeca106725 | 249 | * @param __REG__ Register to be read |
Kojto | 122:f9eeca106725 | 250 | * @retval Register value |
Kojto | 122:f9eeca106725 | 251 | */ |
Kojto | 122:f9eeca106725 | 252 | #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) |
Kojto | 122:f9eeca106725 | 253 | /** |
Kojto | 122:f9eeca106725 | 254 | * @} |
Kojto | 122:f9eeca106725 | 255 | */ |
Kojto | 122:f9eeca106725 | 256 | |
Kojto | 122:f9eeca106725 | 257 | /** |
Kojto | 122:f9eeca106725 | 258 | * @} |
Kojto | 122:f9eeca106725 | 259 | */ |
Kojto | 122:f9eeca106725 | 260 | |
Kojto | 122:f9eeca106725 | 261 | |
Kojto | 122:f9eeca106725 | 262 | /* Exported functions --------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 263 | /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions |
Kojto | 122:f9eeca106725 | 264 | * @{ |
Kojto | 122:f9eeca106725 | 265 | */ |
Kojto | 122:f9eeca106725 | 266 | |
Kojto | 122:f9eeca106725 | 267 | /** @defgroup PWR_LL_EF_Configuration Configuration |
Kojto | 122:f9eeca106725 | 268 | * @{ |
Kojto | 122:f9eeca106725 | 269 | */ |
Kojto | 122:f9eeca106725 | 270 | |
Kojto | 122:f9eeca106725 | 271 | /** |
Kojto | 122:f9eeca106725 | 272 | * @brief Switch the regulator from main mode to low-power mode |
Kojto | 122:f9eeca106725 | 273 | * @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode |
Kojto | 122:f9eeca106725 | 274 | * @retval None |
Kojto | 122:f9eeca106725 | 275 | */ |
Kojto | 122:f9eeca106725 | 276 | __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void) |
Kojto | 122:f9eeca106725 | 277 | { |
Kojto | 122:f9eeca106725 | 278 | SET_BIT(PWR->CR1, PWR_CR1_LPR); |
Kojto | 122:f9eeca106725 | 279 | } |
Kojto | 122:f9eeca106725 | 280 | |
Kojto | 122:f9eeca106725 | 281 | /** |
Kojto | 122:f9eeca106725 | 282 | * @brief Switch the regulator from low-power mode to main mode |
Kojto | 122:f9eeca106725 | 283 | * @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode |
Kojto | 122:f9eeca106725 | 284 | * @retval None |
Kojto | 122:f9eeca106725 | 285 | */ |
Kojto | 122:f9eeca106725 | 286 | __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void) |
Kojto | 122:f9eeca106725 | 287 | { |
Kojto | 122:f9eeca106725 | 288 | CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); |
Kojto | 122:f9eeca106725 | 289 | } |
Kojto | 122:f9eeca106725 | 290 | |
Kojto | 122:f9eeca106725 | 291 | /** |
Kojto | 122:f9eeca106725 | 292 | * @brief Check if the regulator is in low-power mode |
Kojto | 122:f9eeca106725 | 293 | * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode |
Kojto | 122:f9eeca106725 | 294 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 295 | */ |
Kojto | 122:f9eeca106725 | 296 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) |
Kojto | 122:f9eeca106725 | 297 | { |
Kojto | 122:f9eeca106725 | 298 | return (READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)); |
Kojto | 122:f9eeca106725 | 299 | } |
Kojto | 122:f9eeca106725 | 300 | |
Kojto | 122:f9eeca106725 | 301 | /** |
Kojto | 122:f9eeca106725 | 302 | * @brief Switch from run main mode to run low-power mode. |
Kojto | 122:f9eeca106725 | 303 | * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode |
Kojto | 122:f9eeca106725 | 304 | * @retval None |
Kojto | 122:f9eeca106725 | 305 | */ |
Kojto | 122:f9eeca106725 | 306 | __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void) |
Kojto | 122:f9eeca106725 | 307 | { |
Kojto | 122:f9eeca106725 | 308 | LL_PWR_EnableLowPowerRunMode(); |
Kojto | 122:f9eeca106725 | 309 | } |
Kojto | 122:f9eeca106725 | 310 | |
Kojto | 122:f9eeca106725 | 311 | /** |
Kojto | 122:f9eeca106725 | 312 | * @brief Switch from run main mode to low-power mode. |
Kojto | 122:f9eeca106725 | 313 | * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode |
Kojto | 122:f9eeca106725 | 314 | * @retval None |
Kojto | 122:f9eeca106725 | 315 | */ |
Kojto | 122:f9eeca106725 | 316 | __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void) |
Kojto | 122:f9eeca106725 | 317 | { |
Kojto | 122:f9eeca106725 | 318 | LL_PWR_DisableLowPowerRunMode(); |
Kojto | 122:f9eeca106725 | 319 | } |
Kojto | 122:f9eeca106725 | 320 | |
Kojto | 122:f9eeca106725 | 321 | /** |
Kojto | 122:f9eeca106725 | 322 | * @brief Set the main internal regulator output voltage |
Kojto | 122:f9eeca106725 | 323 | * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling |
Kojto | 122:f9eeca106725 | 324 | * @param VoltageScaling This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 325 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 |
Kojto | 122:f9eeca106725 | 326 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 |
Kojto | 122:f9eeca106725 | 327 | * @retval None |
Kojto | 122:f9eeca106725 | 328 | */ |
Kojto | 122:f9eeca106725 | 329 | __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) |
Kojto | 122:f9eeca106725 | 330 | { |
Kojto | 122:f9eeca106725 | 331 | MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); |
Kojto | 122:f9eeca106725 | 332 | } |
Kojto | 122:f9eeca106725 | 333 | |
Kojto | 122:f9eeca106725 | 334 | /** |
Kojto | 122:f9eeca106725 | 335 | * @brief Get the main internal regulator output voltage |
Kojto | 122:f9eeca106725 | 336 | * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling |
Kojto | 122:f9eeca106725 | 337 | * @retval Returned value can be one of the following values: |
Kojto | 122:f9eeca106725 | 338 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 |
Kojto | 122:f9eeca106725 | 339 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 |
Kojto | 122:f9eeca106725 | 340 | */ |
Kojto | 122:f9eeca106725 | 341 | __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) |
Kojto | 122:f9eeca106725 | 342 | { |
Kojto | 122:f9eeca106725 | 343 | return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS)); |
Kojto | 122:f9eeca106725 | 344 | } |
Kojto | 122:f9eeca106725 | 345 | |
Kojto | 122:f9eeca106725 | 346 | /** |
Kojto | 122:f9eeca106725 | 347 | * @brief Enable access to the backup domain |
Kojto | 122:f9eeca106725 | 348 | * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess |
Kojto | 122:f9eeca106725 | 349 | * @retval None |
Kojto | 122:f9eeca106725 | 350 | */ |
Kojto | 122:f9eeca106725 | 351 | __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) |
Kojto | 122:f9eeca106725 | 352 | { |
Kojto | 122:f9eeca106725 | 353 | SET_BIT(PWR->CR1, PWR_CR1_DBP); |
Kojto | 122:f9eeca106725 | 354 | } |
Kojto | 122:f9eeca106725 | 355 | |
Kojto | 122:f9eeca106725 | 356 | /** |
Kojto | 122:f9eeca106725 | 357 | * @brief Disable access to the backup domain |
Kojto | 122:f9eeca106725 | 358 | * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess |
Kojto | 122:f9eeca106725 | 359 | * @retval None |
Kojto | 122:f9eeca106725 | 360 | */ |
Kojto | 122:f9eeca106725 | 361 | __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) |
Kojto | 122:f9eeca106725 | 362 | { |
Kojto | 122:f9eeca106725 | 363 | CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); |
Kojto | 122:f9eeca106725 | 364 | } |
Kojto | 122:f9eeca106725 | 365 | |
Kojto | 122:f9eeca106725 | 366 | /** |
Kojto | 122:f9eeca106725 | 367 | * @brief Check if the backup domain is enabled |
Kojto | 122:f9eeca106725 | 368 | * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess |
Kojto | 122:f9eeca106725 | 369 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 370 | */ |
Kojto | 122:f9eeca106725 | 371 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) |
Kojto | 122:f9eeca106725 | 372 | { |
Kojto | 122:f9eeca106725 | 373 | return (READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)); |
Kojto | 122:f9eeca106725 | 374 | } |
Kojto | 122:f9eeca106725 | 375 | |
Kojto | 122:f9eeca106725 | 376 | /** |
Kojto | 122:f9eeca106725 | 377 | * @brief Set Low-Power mode |
Kojto | 122:f9eeca106725 | 378 | * @rmtoll CR1 LPMS LL_PWR_SetPowerMode |
Kojto | 122:f9eeca106725 | 379 | * @param LowPowerMode This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 380 | * @arg @ref LL_PWR_MODE_STOP0 |
Kojto | 122:f9eeca106725 | 381 | * @arg @ref LL_PWR_MODE_STOP1 |
Kojto | 122:f9eeca106725 | 382 | * @arg @ref LL_PWR_MODE_STOP2 |
Kojto | 122:f9eeca106725 | 383 | * @arg @ref LL_PWR_MODE_STANDBY |
Kojto | 122:f9eeca106725 | 384 | * @arg @ref LL_PWR_MODE_SHUTDOWN |
Kojto | 122:f9eeca106725 | 385 | * @retval None |
Kojto | 122:f9eeca106725 | 386 | */ |
Kojto | 122:f9eeca106725 | 387 | __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode) |
Kojto | 122:f9eeca106725 | 388 | { |
Kojto | 122:f9eeca106725 | 389 | MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode); |
Kojto | 122:f9eeca106725 | 390 | } |
Kojto | 122:f9eeca106725 | 391 | |
Kojto | 122:f9eeca106725 | 392 | /** |
Kojto | 122:f9eeca106725 | 393 | * @brief Get Low-Power mode |
Kojto | 122:f9eeca106725 | 394 | * @rmtoll CR1 LPMS LL_PWR_GetPowerMode |
Kojto | 122:f9eeca106725 | 395 | * @retval Returned value can be one of the following values: |
Kojto | 122:f9eeca106725 | 396 | * @arg @ref LL_PWR_MODE_STOP0 |
Kojto | 122:f9eeca106725 | 397 | * @arg @ref LL_PWR_MODE_STOP1 |
Kojto | 122:f9eeca106725 | 398 | * @arg @ref LL_PWR_MODE_STOP2 |
Kojto | 122:f9eeca106725 | 399 | * @arg @ref LL_PWR_MODE_STANDBY |
Kojto | 122:f9eeca106725 | 400 | * @arg @ref LL_PWR_MODE_SHUTDOWN |
Kojto | 122:f9eeca106725 | 401 | */ |
Kojto | 122:f9eeca106725 | 402 | __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) |
Kojto | 122:f9eeca106725 | 403 | { |
Kojto | 122:f9eeca106725 | 404 | return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS)); |
Kojto | 122:f9eeca106725 | 405 | } |
Kojto | 122:f9eeca106725 | 406 | |
Kojto | 122:f9eeca106725 | 407 | #if defined(USB_OTG_FS) |
Kojto | 122:f9eeca106725 | 408 | /** |
Kojto | 122:f9eeca106725 | 409 | * @brief Enable VDDUSB supply |
Kojto | 122:f9eeca106725 | 410 | * @rmtoll CR2 USV LL_PWR_EnableVddUSB |
Kojto | 122:f9eeca106725 | 411 | * @retval None |
Kojto | 122:f9eeca106725 | 412 | */ |
Kojto | 122:f9eeca106725 | 413 | __STATIC_INLINE void LL_PWR_EnableVddUSB(void) |
Kojto | 122:f9eeca106725 | 414 | { |
Kojto | 122:f9eeca106725 | 415 | SET_BIT(PWR->CR2, PWR_CR2_USV); |
Kojto | 122:f9eeca106725 | 416 | } |
Kojto | 122:f9eeca106725 | 417 | #endif /* USB_OTG_FS */ |
Kojto | 122:f9eeca106725 | 418 | |
Kojto | 122:f9eeca106725 | 419 | #if defined(USB_OTG_FS) |
Kojto | 122:f9eeca106725 | 420 | /** |
Kojto | 122:f9eeca106725 | 421 | * @brief Disable VDDUSB supply |
Kojto | 122:f9eeca106725 | 422 | * @rmtoll CR2 USV LL_PWR_DisableVddUSB |
Kojto | 122:f9eeca106725 | 423 | * @retval None |
Kojto | 122:f9eeca106725 | 424 | */ |
Kojto | 122:f9eeca106725 | 425 | __STATIC_INLINE void LL_PWR_DisableVddUSB(void) |
Kojto | 122:f9eeca106725 | 426 | { |
Kojto | 122:f9eeca106725 | 427 | CLEAR_BIT(PWR->CR2, PWR_CR2_USV); |
Kojto | 122:f9eeca106725 | 428 | } |
Kojto | 122:f9eeca106725 | 429 | #endif /* USB_OTG_FS */ |
Kojto | 122:f9eeca106725 | 430 | |
Kojto | 122:f9eeca106725 | 431 | #if defined(USB_OTG_FS) |
Kojto | 122:f9eeca106725 | 432 | /** |
Kojto | 122:f9eeca106725 | 433 | * @brief Check if VDDUSB supply is enabled |
Kojto | 122:f9eeca106725 | 434 | * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB |
Kojto | 122:f9eeca106725 | 435 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 436 | */ |
Kojto | 122:f9eeca106725 | 437 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) |
Kojto | 122:f9eeca106725 | 438 | { |
Kojto | 122:f9eeca106725 | 439 | return (READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)); |
Kojto | 122:f9eeca106725 | 440 | } |
Kojto | 122:f9eeca106725 | 441 | #endif /* USB_OTG_FS */ |
Kojto | 122:f9eeca106725 | 442 | |
Kojto | 122:f9eeca106725 | 443 | #if defined(PWR_CR2_IOSV) |
Kojto | 122:f9eeca106725 | 444 | /** |
Kojto | 122:f9eeca106725 | 445 | * @brief Enable VDDIO2 supply |
Kojto | 122:f9eeca106725 | 446 | * @rmtoll CR2 IOSV LL_PWR_EnableVddIO2 |
Kojto | 122:f9eeca106725 | 447 | * @retval None |
Kojto | 122:f9eeca106725 | 448 | */ |
Kojto | 122:f9eeca106725 | 449 | __STATIC_INLINE void LL_PWR_EnableVddIO2(void) |
Kojto | 122:f9eeca106725 | 450 | { |
Kojto | 122:f9eeca106725 | 451 | SET_BIT(PWR->CR2, PWR_CR2_IOSV); |
Kojto | 122:f9eeca106725 | 452 | } |
Kojto | 122:f9eeca106725 | 453 | |
Kojto | 122:f9eeca106725 | 454 | /** |
Kojto | 122:f9eeca106725 | 455 | * @brief Disable VDDIO2 supply |
Kojto | 122:f9eeca106725 | 456 | * @rmtoll CR2 IOSV LL_PWR_DisableVddIO2 |
Kojto | 122:f9eeca106725 | 457 | * @retval None |
Kojto | 122:f9eeca106725 | 458 | */ |
Kojto | 122:f9eeca106725 | 459 | __STATIC_INLINE void LL_PWR_DisableVddIO2(void) |
Kojto | 122:f9eeca106725 | 460 | { |
Kojto | 122:f9eeca106725 | 461 | CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV); |
Kojto | 122:f9eeca106725 | 462 | } |
Kojto | 122:f9eeca106725 | 463 | |
Kojto | 122:f9eeca106725 | 464 | /** |
Kojto | 122:f9eeca106725 | 465 | * @brief Check if VDDIO2 supply is enabled |
Kojto | 122:f9eeca106725 | 466 | * @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2 |
Kojto | 122:f9eeca106725 | 467 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 468 | */ |
Kojto | 122:f9eeca106725 | 469 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) |
Kojto | 122:f9eeca106725 | 470 | { |
Kojto | 122:f9eeca106725 | 471 | return (READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)); |
Kojto | 122:f9eeca106725 | 472 | } |
Kojto | 122:f9eeca106725 | 473 | #endif /* PWR_CR2_IOSV */ |
Kojto | 122:f9eeca106725 | 474 | |
Kojto | 122:f9eeca106725 | 475 | /** |
Kojto | 122:f9eeca106725 | 476 | * @brief Enable the Power Voltage Monitoring on a peripheral |
Kojto | 122:f9eeca106725 | 477 | * @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n |
Kojto | 122:f9eeca106725 | 478 | * CR2 PVME2 LL_PWR_EnablePVM\n |
Kojto | 122:f9eeca106725 | 479 | * CR2 PVME3 LL_PWR_EnablePVM\n |
Kojto | 122:f9eeca106725 | 480 | * CR2 PVME4 LL_PWR_EnablePVM |
Kojto | 122:f9eeca106725 | 481 | * @param PeriphVoltage This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 482 | * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) |
Kojto | 122:f9eeca106725 | 483 | * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*) |
Kojto | 122:f9eeca106725 | 484 | * @arg @ref LL_PWR_PVM_VDDA_1_62V |
Kojto | 122:f9eeca106725 | 485 | * @arg @ref LL_PWR_PVM_VDDA_2_2V |
Kojto | 122:f9eeca106725 | 486 | * |
Kojto | 122:f9eeca106725 | 487 | * (*) value not defined in all devices |
Kojto | 122:f9eeca106725 | 488 | * @retval None |
Kojto | 122:f9eeca106725 | 489 | */ |
Kojto | 122:f9eeca106725 | 490 | __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage) |
Kojto | 122:f9eeca106725 | 491 | { |
Kojto | 122:f9eeca106725 | 492 | SET_BIT(PWR->CR2, PeriphVoltage); |
Kojto | 122:f9eeca106725 | 493 | } |
Kojto | 122:f9eeca106725 | 494 | |
Kojto | 122:f9eeca106725 | 495 | /** |
Kojto | 122:f9eeca106725 | 496 | * @brief Disable the Power Voltage Monitoring on a peripheral |
Kojto | 122:f9eeca106725 | 497 | * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n |
Kojto | 122:f9eeca106725 | 498 | * CR2 PVME2 LL_PWR_DisablePVM\n |
Kojto | 122:f9eeca106725 | 499 | * CR2 PVME3 LL_PWR_DisablePVM\n |
Kojto | 122:f9eeca106725 | 500 | * CR2 PVME4 LL_PWR_DisablePVM |
Kojto | 122:f9eeca106725 | 501 | * @param PeriphVoltage This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 502 | * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) |
Kojto | 122:f9eeca106725 | 503 | * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*) |
Kojto | 122:f9eeca106725 | 504 | * @arg @ref LL_PWR_PVM_VDDA_1_62V |
Kojto | 122:f9eeca106725 | 505 | * @arg @ref LL_PWR_PVM_VDDA_2_2V |
Kojto | 122:f9eeca106725 | 506 | * |
Kojto | 122:f9eeca106725 | 507 | * (*) value not defined in all devices |
Kojto | 122:f9eeca106725 | 508 | * @retval None |
Kojto | 122:f9eeca106725 | 509 | */ |
Kojto | 122:f9eeca106725 | 510 | __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) |
Kojto | 122:f9eeca106725 | 511 | { |
Kojto | 122:f9eeca106725 | 512 | CLEAR_BIT(PWR->CR2, PeriphVoltage); |
Kojto | 122:f9eeca106725 | 513 | } |
Kojto | 122:f9eeca106725 | 514 | |
Kojto | 122:f9eeca106725 | 515 | /** |
Kojto | 122:f9eeca106725 | 516 | * @brief Check if Power Voltage Monitoring is enabled on a peripheral |
Kojto | 122:f9eeca106725 | 517 | * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n |
Kojto | 122:f9eeca106725 | 518 | * CR2 PVME2 LL_PWR_IsEnabledPVM\n |
Kojto | 122:f9eeca106725 | 519 | * CR2 PVME3 LL_PWR_IsEnabledPVM\n |
Kojto | 122:f9eeca106725 | 520 | * CR2 PVME4 LL_PWR_IsEnabledPVM |
Kojto | 122:f9eeca106725 | 521 | * @param PeriphVoltage This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 522 | * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) |
Kojto | 122:f9eeca106725 | 523 | * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*) |
Kojto | 122:f9eeca106725 | 524 | * @arg @ref LL_PWR_PVM_VDDA_1_62V |
Kojto | 122:f9eeca106725 | 525 | * @arg @ref LL_PWR_PVM_VDDA_2_2V |
Kojto | 122:f9eeca106725 | 526 | * |
Kojto | 122:f9eeca106725 | 527 | * (*) value not defined in all devices |
Kojto | 122:f9eeca106725 | 528 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 529 | */ |
Kojto | 122:f9eeca106725 | 530 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage) |
Kojto | 122:f9eeca106725 | 531 | { |
Kojto | 122:f9eeca106725 | 532 | return (READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)); |
Kojto | 122:f9eeca106725 | 533 | } |
Kojto | 122:f9eeca106725 | 534 | |
Kojto | 122:f9eeca106725 | 535 | /** |
Kojto | 122:f9eeca106725 | 536 | * @brief Configure the voltage threshold detected by the Power Voltage Detector |
Kojto | 122:f9eeca106725 | 537 | * @rmtoll CR2 PLS LL_PWR_SetPVDLevel |
Kojto | 122:f9eeca106725 | 538 | * @param PVDLevel This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 539 | * @arg @ref LL_PWR_PVDLEVEL_0 |
Kojto | 122:f9eeca106725 | 540 | * @arg @ref LL_PWR_PVDLEVEL_1 |
Kojto | 122:f9eeca106725 | 541 | * @arg @ref LL_PWR_PVDLEVEL_2 |
Kojto | 122:f9eeca106725 | 542 | * @arg @ref LL_PWR_PVDLEVEL_3 |
Kojto | 122:f9eeca106725 | 543 | * @arg @ref LL_PWR_PVDLEVEL_4 |
Kojto | 122:f9eeca106725 | 544 | * @arg @ref LL_PWR_PVDLEVEL_5 |
Kojto | 122:f9eeca106725 | 545 | * @arg @ref LL_PWR_PVDLEVEL_6 |
Kojto | 122:f9eeca106725 | 546 | * @arg @ref LL_PWR_PVDLEVEL_7 |
Kojto | 122:f9eeca106725 | 547 | * @retval None |
Kojto | 122:f9eeca106725 | 548 | */ |
Kojto | 122:f9eeca106725 | 549 | __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) |
Kojto | 122:f9eeca106725 | 550 | { |
Kojto | 122:f9eeca106725 | 551 | MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel); |
Kojto | 122:f9eeca106725 | 552 | } |
Kojto | 122:f9eeca106725 | 553 | |
Kojto | 122:f9eeca106725 | 554 | /** |
Kojto | 122:f9eeca106725 | 555 | * @brief Get the voltage threshold detection |
Kojto | 122:f9eeca106725 | 556 | * @rmtoll CR2 PLS LL_PWR_GetPVDLevel |
Kojto | 122:f9eeca106725 | 557 | * @retval Returned value can be one of the following values: |
Kojto | 122:f9eeca106725 | 558 | * @arg @ref LL_PWR_PVDLEVEL_0 |
Kojto | 122:f9eeca106725 | 559 | * @arg @ref LL_PWR_PVDLEVEL_1 |
Kojto | 122:f9eeca106725 | 560 | * @arg @ref LL_PWR_PVDLEVEL_2 |
Kojto | 122:f9eeca106725 | 561 | * @arg @ref LL_PWR_PVDLEVEL_3 |
Kojto | 122:f9eeca106725 | 562 | * @arg @ref LL_PWR_PVDLEVEL_4 |
Kojto | 122:f9eeca106725 | 563 | * @arg @ref LL_PWR_PVDLEVEL_5 |
Kojto | 122:f9eeca106725 | 564 | * @arg @ref LL_PWR_PVDLEVEL_6 |
Kojto | 122:f9eeca106725 | 565 | * @arg @ref LL_PWR_PVDLEVEL_7 |
Kojto | 122:f9eeca106725 | 566 | */ |
Kojto | 122:f9eeca106725 | 567 | __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) |
Kojto | 122:f9eeca106725 | 568 | { |
Kojto | 122:f9eeca106725 | 569 | return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS)); |
Kojto | 122:f9eeca106725 | 570 | } |
Kojto | 122:f9eeca106725 | 571 | |
Kojto | 122:f9eeca106725 | 572 | /** |
Kojto | 122:f9eeca106725 | 573 | * @brief Enable Power Voltage Detector |
Kojto | 122:f9eeca106725 | 574 | * @rmtoll CR2 PVDE LL_PWR_EnablePVD |
Kojto | 122:f9eeca106725 | 575 | * @retval None |
Kojto | 122:f9eeca106725 | 576 | */ |
Kojto | 122:f9eeca106725 | 577 | __STATIC_INLINE void LL_PWR_EnablePVD(void) |
Kojto | 122:f9eeca106725 | 578 | { |
Kojto | 122:f9eeca106725 | 579 | SET_BIT(PWR->CR2, PWR_CR2_PVDE); |
Kojto | 122:f9eeca106725 | 580 | } |
Kojto | 122:f9eeca106725 | 581 | |
Kojto | 122:f9eeca106725 | 582 | /** |
Kojto | 122:f9eeca106725 | 583 | * @brief Disable Power Voltage Detector |
Kojto | 122:f9eeca106725 | 584 | * @rmtoll CR2 PVDE LL_PWR_DisablePVD |
Kojto | 122:f9eeca106725 | 585 | * @retval None |
Kojto | 122:f9eeca106725 | 586 | */ |
Kojto | 122:f9eeca106725 | 587 | __STATIC_INLINE void LL_PWR_DisablePVD(void) |
Kojto | 122:f9eeca106725 | 588 | { |
Kojto | 122:f9eeca106725 | 589 | CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); |
Kojto | 122:f9eeca106725 | 590 | } |
Kojto | 122:f9eeca106725 | 591 | |
Kojto | 122:f9eeca106725 | 592 | /** |
Kojto | 122:f9eeca106725 | 593 | * @brief Check if Power Voltage Detector is enabled |
Kojto | 122:f9eeca106725 | 594 | * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD |
Kojto | 122:f9eeca106725 | 595 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 596 | */ |
Kojto | 122:f9eeca106725 | 597 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) |
Kojto | 122:f9eeca106725 | 598 | { |
Kojto | 122:f9eeca106725 | 599 | return (READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)); |
Kojto | 122:f9eeca106725 | 600 | } |
Kojto | 122:f9eeca106725 | 601 | |
Kojto | 122:f9eeca106725 | 602 | /** |
Kojto | 122:f9eeca106725 | 603 | * @brief Enable Internal Wake-up line |
Kojto | 122:f9eeca106725 | 604 | * @rmtoll CR3 EIWF LL_PWR_EnableInternWU |
Kojto | 122:f9eeca106725 | 605 | * @retval None |
Kojto | 122:f9eeca106725 | 606 | */ |
Kojto | 122:f9eeca106725 | 607 | __STATIC_INLINE void LL_PWR_EnableInternWU(void) |
Kojto | 122:f9eeca106725 | 608 | { |
Kojto | 122:f9eeca106725 | 609 | SET_BIT(PWR->CR3, PWR_CR3_EIWF); |
Kojto | 122:f9eeca106725 | 610 | } |
Kojto | 122:f9eeca106725 | 611 | |
Kojto | 122:f9eeca106725 | 612 | /** |
Kojto | 122:f9eeca106725 | 613 | * @brief Disable Internal Wake-up line |
Kojto | 122:f9eeca106725 | 614 | * @rmtoll CR3 EIWF LL_PWR_DisableInternWU |
Kojto | 122:f9eeca106725 | 615 | * @retval None |
Kojto | 122:f9eeca106725 | 616 | */ |
Kojto | 122:f9eeca106725 | 617 | __STATIC_INLINE void LL_PWR_DisableInternWU(void) |
Kojto | 122:f9eeca106725 | 618 | { |
Kojto | 122:f9eeca106725 | 619 | CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF); |
Kojto | 122:f9eeca106725 | 620 | } |
Kojto | 122:f9eeca106725 | 621 | |
Kojto | 122:f9eeca106725 | 622 | /** |
Kojto | 122:f9eeca106725 | 623 | * @brief Check if Internal Wake-up line is enabled |
Kojto | 122:f9eeca106725 | 624 | * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU |
Kojto | 122:f9eeca106725 | 625 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 626 | */ |
Kojto | 122:f9eeca106725 | 627 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void) |
Kojto | 122:f9eeca106725 | 628 | { |
Kojto | 122:f9eeca106725 | 629 | return (READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF)); |
Kojto | 122:f9eeca106725 | 630 | } |
Kojto | 122:f9eeca106725 | 631 | |
Kojto | 122:f9eeca106725 | 632 | /** |
Kojto | 122:f9eeca106725 | 633 | * @brief Enable pull-up and pull-down configuration |
Kojto | 122:f9eeca106725 | 634 | * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg |
Kojto | 122:f9eeca106725 | 635 | * @retval None |
Kojto | 122:f9eeca106725 | 636 | */ |
Kojto | 122:f9eeca106725 | 637 | __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void) |
Kojto | 122:f9eeca106725 | 638 | { |
Kojto | 122:f9eeca106725 | 639 | SET_BIT(PWR->CR3, PWR_CR3_APC); |
Kojto | 122:f9eeca106725 | 640 | } |
Kojto | 122:f9eeca106725 | 641 | |
Kojto | 122:f9eeca106725 | 642 | /** |
Kojto | 122:f9eeca106725 | 643 | * @brief Disable pull-up and pull-down configuration |
Kojto | 122:f9eeca106725 | 644 | * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg |
Kojto | 122:f9eeca106725 | 645 | * @retval None |
Kojto | 122:f9eeca106725 | 646 | */ |
Kojto | 122:f9eeca106725 | 647 | __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void) |
Kojto | 122:f9eeca106725 | 648 | { |
Kojto | 122:f9eeca106725 | 649 | CLEAR_BIT(PWR->CR3, PWR_CR3_APC); |
Kojto | 122:f9eeca106725 | 650 | } |
Kojto | 122:f9eeca106725 | 651 | |
Kojto | 122:f9eeca106725 | 652 | /** |
Kojto | 122:f9eeca106725 | 653 | * @brief Check if pull-up and pull-down configuration is enabled |
Kojto | 122:f9eeca106725 | 654 | * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg |
Kojto | 122:f9eeca106725 | 655 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 656 | */ |
Kojto | 122:f9eeca106725 | 657 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void) |
Kojto | 122:f9eeca106725 | 658 | { |
Kojto | 122:f9eeca106725 | 659 | return (READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)); |
Kojto | 122:f9eeca106725 | 660 | } |
Kojto | 122:f9eeca106725 | 661 | |
Kojto | 122:f9eeca106725 | 662 | /** |
Kojto | 122:f9eeca106725 | 663 | * @brief Enable SRAM2 content retention in Standby mode |
Kojto | 122:f9eeca106725 | 664 | * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention |
Kojto | 122:f9eeca106725 | 665 | * @retval None |
Kojto | 122:f9eeca106725 | 666 | */ |
Kojto | 122:f9eeca106725 | 667 | __STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void) |
Kojto | 122:f9eeca106725 | 668 | { |
Kojto | 122:f9eeca106725 | 669 | SET_BIT(PWR->CR3, PWR_CR3_RRS); |
Kojto | 122:f9eeca106725 | 670 | } |
Kojto | 122:f9eeca106725 | 671 | |
Kojto | 122:f9eeca106725 | 672 | /** |
Kojto | 122:f9eeca106725 | 673 | * @brief Disable SRAM2 content retention in Standby mode |
Kojto | 122:f9eeca106725 | 674 | * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention |
Kojto | 122:f9eeca106725 | 675 | * @retval None |
Kojto | 122:f9eeca106725 | 676 | */ |
Kojto | 122:f9eeca106725 | 677 | __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void) |
Kojto | 122:f9eeca106725 | 678 | { |
Kojto | 122:f9eeca106725 | 679 | CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); |
Kojto | 122:f9eeca106725 | 680 | } |
Kojto | 122:f9eeca106725 | 681 | |
Kojto | 122:f9eeca106725 | 682 | /** |
Kojto | 122:f9eeca106725 | 683 | * @brief Check if SRAM2 content retention in Standby mode is enabled |
Kojto | 122:f9eeca106725 | 684 | * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention |
Kojto | 122:f9eeca106725 | 685 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 686 | */ |
Kojto | 122:f9eeca106725 | 687 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void) |
Kojto | 122:f9eeca106725 | 688 | { |
Kojto | 122:f9eeca106725 | 689 | return (READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)); |
Kojto | 122:f9eeca106725 | 690 | } |
Kojto | 122:f9eeca106725 | 691 | |
Kojto | 122:f9eeca106725 | 692 | /** |
Kojto | 122:f9eeca106725 | 693 | * @brief Enable the WakeUp PINx functionality |
Kojto | 122:f9eeca106725 | 694 | * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n |
Kojto | 122:f9eeca106725 | 695 | * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n |
Kojto | 122:f9eeca106725 | 696 | * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n |
Kojto | 122:f9eeca106725 | 697 | * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n |
Kojto | 122:f9eeca106725 | 698 | * CR3 EWUP5 LL_PWR_EnableWakeUpPin |
Kojto | 122:f9eeca106725 | 699 | * @param WakeUpPin This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 700 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
Kojto | 122:f9eeca106725 | 701 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
Kojto | 122:f9eeca106725 | 702 | * @arg @ref LL_PWR_WAKEUP_PIN3 |
Kojto | 122:f9eeca106725 | 703 | * @arg @ref LL_PWR_WAKEUP_PIN4 |
Kojto | 122:f9eeca106725 | 704 | * @arg @ref LL_PWR_WAKEUP_PIN5 |
Kojto | 122:f9eeca106725 | 705 | * @retval None |
Kojto | 122:f9eeca106725 | 706 | */ |
Kojto | 122:f9eeca106725 | 707 | __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) |
Kojto | 122:f9eeca106725 | 708 | { |
Kojto | 122:f9eeca106725 | 709 | SET_BIT(PWR->CR3, WakeUpPin); |
Kojto | 122:f9eeca106725 | 710 | } |
Kojto | 122:f9eeca106725 | 711 | |
Kojto | 122:f9eeca106725 | 712 | /** |
Kojto | 122:f9eeca106725 | 713 | * @brief Disable the WakeUp PINx functionality |
Kojto | 122:f9eeca106725 | 714 | * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n |
Kojto | 122:f9eeca106725 | 715 | * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n |
Kojto | 122:f9eeca106725 | 716 | * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n |
Kojto | 122:f9eeca106725 | 717 | * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n |
Kojto | 122:f9eeca106725 | 718 | * CR3 EWUP5 LL_PWR_DisableWakeUpPin |
Kojto | 122:f9eeca106725 | 719 | * @param WakeUpPin This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 720 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
Kojto | 122:f9eeca106725 | 721 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
Kojto | 122:f9eeca106725 | 722 | * @arg @ref LL_PWR_WAKEUP_PIN3 |
Kojto | 122:f9eeca106725 | 723 | * @arg @ref LL_PWR_WAKEUP_PIN4 |
Kojto | 122:f9eeca106725 | 724 | * @arg @ref LL_PWR_WAKEUP_PIN5 |
Kojto | 122:f9eeca106725 | 725 | * @retval None |
Kojto | 122:f9eeca106725 | 726 | */ |
Kojto | 122:f9eeca106725 | 727 | __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) |
Kojto | 122:f9eeca106725 | 728 | { |
Kojto | 122:f9eeca106725 | 729 | CLEAR_BIT(PWR->CR3, WakeUpPin); |
Kojto | 122:f9eeca106725 | 730 | } |
Kojto | 122:f9eeca106725 | 731 | |
Kojto | 122:f9eeca106725 | 732 | /** |
Kojto | 122:f9eeca106725 | 733 | * @brief Check if the WakeUp PINx functionality is enabled |
Kojto | 122:f9eeca106725 | 734 | * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n |
Kojto | 122:f9eeca106725 | 735 | * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n |
Kojto | 122:f9eeca106725 | 736 | * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n |
Kojto | 122:f9eeca106725 | 737 | * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n |
Kojto | 122:f9eeca106725 | 738 | * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin |
Kojto | 122:f9eeca106725 | 739 | * @param WakeUpPin This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 740 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
Kojto | 122:f9eeca106725 | 741 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
Kojto | 122:f9eeca106725 | 742 | * @arg @ref LL_PWR_WAKEUP_PIN3 |
Kojto | 122:f9eeca106725 | 743 | * @arg @ref LL_PWR_WAKEUP_PIN4 |
Kojto | 122:f9eeca106725 | 744 | * @arg @ref LL_PWR_WAKEUP_PIN5 |
Kojto | 122:f9eeca106725 | 745 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 746 | */ |
Kojto | 122:f9eeca106725 | 747 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) |
Kojto | 122:f9eeca106725 | 748 | { |
Kojto | 122:f9eeca106725 | 749 | return (READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)); |
Kojto | 122:f9eeca106725 | 750 | } |
Kojto | 122:f9eeca106725 | 751 | |
Kojto | 122:f9eeca106725 | 752 | /** |
Kojto | 122:f9eeca106725 | 753 | * @brief Set the resistor impedance |
Kojto | 122:f9eeca106725 | 754 | * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor |
Kojto | 122:f9eeca106725 | 755 | * @param Resistor This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 756 | * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K |
Kojto | 122:f9eeca106725 | 757 | * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K |
Kojto | 122:f9eeca106725 | 758 | * @retval None |
Kojto | 122:f9eeca106725 | 759 | */ |
Kojto | 122:f9eeca106725 | 760 | __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor) |
Kojto | 122:f9eeca106725 | 761 | { |
Kojto | 122:f9eeca106725 | 762 | MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor); |
Kojto | 122:f9eeca106725 | 763 | } |
Kojto | 122:f9eeca106725 | 764 | |
Kojto | 122:f9eeca106725 | 765 | /** |
Kojto | 122:f9eeca106725 | 766 | * @brief Get the resistor impedance |
Kojto | 122:f9eeca106725 | 767 | * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor |
Kojto | 122:f9eeca106725 | 768 | * @retval Returned value can be one of the following values: |
Kojto | 122:f9eeca106725 | 769 | * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K |
Kojto | 122:f9eeca106725 | 770 | * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K |
Kojto | 122:f9eeca106725 | 771 | */ |
Kojto | 122:f9eeca106725 | 772 | __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void) |
Kojto | 122:f9eeca106725 | 773 | { |
Kojto | 122:f9eeca106725 | 774 | return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS)); |
Kojto | 122:f9eeca106725 | 775 | } |
Kojto | 122:f9eeca106725 | 776 | |
Kojto | 122:f9eeca106725 | 777 | /** |
Kojto | 122:f9eeca106725 | 778 | * @brief Enable battery charging |
Kojto | 122:f9eeca106725 | 779 | * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging |
Kojto | 122:f9eeca106725 | 780 | * @retval None |
Kojto | 122:f9eeca106725 | 781 | */ |
Kojto | 122:f9eeca106725 | 782 | __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void) |
Kojto | 122:f9eeca106725 | 783 | { |
Kojto | 122:f9eeca106725 | 784 | SET_BIT(PWR->CR4, PWR_CR4_VBE); |
Kojto | 122:f9eeca106725 | 785 | } |
Kojto | 122:f9eeca106725 | 786 | |
Kojto | 122:f9eeca106725 | 787 | /** |
Kojto | 122:f9eeca106725 | 788 | * @brief Disable battery charging |
Kojto | 122:f9eeca106725 | 789 | * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging |
Kojto | 122:f9eeca106725 | 790 | * @retval None |
Kojto | 122:f9eeca106725 | 791 | */ |
Kojto | 122:f9eeca106725 | 792 | __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void) |
Kojto | 122:f9eeca106725 | 793 | { |
Kojto | 122:f9eeca106725 | 794 | CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); |
Kojto | 122:f9eeca106725 | 795 | } |
Kojto | 122:f9eeca106725 | 796 | |
Kojto | 122:f9eeca106725 | 797 | /** |
Kojto | 122:f9eeca106725 | 798 | * @brief Check if battery charging is enabled |
Kojto | 122:f9eeca106725 | 799 | * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging |
Kojto | 122:f9eeca106725 | 800 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 801 | */ |
Kojto | 122:f9eeca106725 | 802 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) |
Kojto | 122:f9eeca106725 | 803 | { |
Kojto | 122:f9eeca106725 | 804 | return (READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)); |
Kojto | 122:f9eeca106725 | 805 | } |
Kojto | 122:f9eeca106725 | 806 | |
Kojto | 122:f9eeca106725 | 807 | /** |
Kojto | 122:f9eeca106725 | 808 | * @brief Set the Wake-Up pin polarity low for the event detection |
Kojto | 122:f9eeca106725 | 809 | * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n |
Kojto | 122:f9eeca106725 | 810 | * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n |
Kojto | 122:f9eeca106725 | 811 | * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n |
Kojto | 122:f9eeca106725 | 812 | * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n |
Kojto | 122:f9eeca106725 | 813 | * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow |
Kojto | 122:f9eeca106725 | 814 | * @param WakeUpPin This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 815 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
Kojto | 122:f9eeca106725 | 816 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
Kojto | 122:f9eeca106725 | 817 | * @arg @ref LL_PWR_WAKEUP_PIN3 |
Kojto | 122:f9eeca106725 | 818 | * @arg @ref LL_PWR_WAKEUP_PIN4 |
Kojto | 122:f9eeca106725 | 819 | * @arg @ref LL_PWR_WAKEUP_PIN5 |
Kojto | 122:f9eeca106725 | 820 | * @retval None |
Kojto | 122:f9eeca106725 | 821 | */ |
Kojto | 122:f9eeca106725 | 822 | __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) |
Kojto | 122:f9eeca106725 | 823 | { |
Kojto | 122:f9eeca106725 | 824 | SET_BIT(PWR->CR4, WakeUpPin); |
Kojto | 122:f9eeca106725 | 825 | } |
Kojto | 122:f9eeca106725 | 826 | |
Kojto | 122:f9eeca106725 | 827 | /** |
Kojto | 122:f9eeca106725 | 828 | * @brief Set the Wake-Up pin polarity high for the event detection |
Kojto | 122:f9eeca106725 | 829 | * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n |
Kojto | 122:f9eeca106725 | 830 | * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n |
Kojto | 122:f9eeca106725 | 831 | * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n |
Kojto | 122:f9eeca106725 | 832 | * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n |
Kojto | 122:f9eeca106725 | 833 | * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh |
Kojto | 122:f9eeca106725 | 834 | * @param WakeUpPin This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 835 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
Kojto | 122:f9eeca106725 | 836 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
Kojto | 122:f9eeca106725 | 837 | * @arg @ref LL_PWR_WAKEUP_PIN3 |
Kojto | 122:f9eeca106725 | 838 | * @arg @ref LL_PWR_WAKEUP_PIN4 |
Kojto | 122:f9eeca106725 | 839 | * @arg @ref LL_PWR_WAKEUP_PIN5 |
Kojto | 122:f9eeca106725 | 840 | * @retval None |
Kojto | 122:f9eeca106725 | 841 | */ |
Kojto | 122:f9eeca106725 | 842 | __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) |
Kojto | 122:f9eeca106725 | 843 | { |
Kojto | 122:f9eeca106725 | 844 | CLEAR_BIT(PWR->CR4, WakeUpPin); |
Kojto | 122:f9eeca106725 | 845 | } |
Kojto | 122:f9eeca106725 | 846 | |
Kojto | 122:f9eeca106725 | 847 | /** |
Kojto | 122:f9eeca106725 | 848 | * @brief Get the Wake-Up pin polarity for the event detection |
Kojto | 122:f9eeca106725 | 849 | * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n |
Kojto | 122:f9eeca106725 | 850 | * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n |
Kojto | 122:f9eeca106725 | 851 | * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n |
Kojto | 122:f9eeca106725 | 852 | * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n |
Kojto | 122:f9eeca106725 | 853 | * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow |
Kojto | 122:f9eeca106725 | 854 | * @param WakeUpPin This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 855 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
Kojto | 122:f9eeca106725 | 856 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
Kojto | 122:f9eeca106725 | 857 | * @arg @ref LL_PWR_WAKEUP_PIN3 |
Kojto | 122:f9eeca106725 | 858 | * @arg @ref LL_PWR_WAKEUP_PIN4 |
Kojto | 122:f9eeca106725 | 859 | * @arg @ref LL_PWR_WAKEUP_PIN5 |
Kojto | 122:f9eeca106725 | 860 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 861 | */ |
Kojto | 122:f9eeca106725 | 862 | __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) |
Kojto | 122:f9eeca106725 | 863 | { |
Kojto | 122:f9eeca106725 | 864 | return (READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)); |
Kojto | 122:f9eeca106725 | 865 | } |
Kojto | 122:f9eeca106725 | 866 | |
Kojto | 122:f9eeca106725 | 867 | /** |
Kojto | 122:f9eeca106725 | 868 | * @brief Enable GPIO pull-up state in Standby and Shutdown modes |
Kojto | 122:f9eeca106725 | 869 | * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n |
Kojto | 122:f9eeca106725 | 870 | * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n |
Kojto | 122:f9eeca106725 | 871 | * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n |
Kojto | 122:f9eeca106725 | 872 | * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n |
Kojto | 122:f9eeca106725 | 873 | * PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n |
Kojto | 122:f9eeca106725 | 874 | * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp\n |
Kojto | 122:f9eeca106725 | 875 | * PUCRG PU0-15 LL_PWR_EnableGPIOPullUp\n |
Kojto | 122:f9eeca106725 | 876 | * PUCRH PU0-1 LL_PWR_EnableGPIOPullUp |
Kojto | 122:f9eeca106725 | 877 | * @param GPIO This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 878 | * @arg @ref LL_PWR_GPIO_A |
Kojto | 122:f9eeca106725 | 879 | * @arg @ref LL_PWR_GPIO_B |
Kojto | 122:f9eeca106725 | 880 | * @arg @ref LL_PWR_GPIO_C |
Kojto | 122:f9eeca106725 | 881 | * @arg @ref LL_PWR_GPIO_D |
Kojto | 122:f9eeca106725 | 882 | * @arg @ref LL_PWR_GPIO_E |
Kojto | 122:f9eeca106725 | 883 | * @arg @ref LL_PWR_GPIO_F (*) |
Kojto | 122:f9eeca106725 | 884 | * @arg @ref LL_PWR_GPIO_G (*) |
Kojto | 122:f9eeca106725 | 885 | * @arg @ref LL_PWR_GPIO_H |
Kojto | 122:f9eeca106725 | 886 | * |
Kojto | 122:f9eeca106725 | 887 | * (*) value not defined in all devices |
Kojto | 122:f9eeca106725 | 888 | * @param GPIONumber This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 889 | * @arg @ref LL_PWR_GPIO_BIT_0 |
Kojto | 122:f9eeca106725 | 890 | * @arg @ref LL_PWR_GPIO_BIT_1 |
Kojto | 122:f9eeca106725 | 891 | * @arg @ref LL_PWR_GPIO_BIT_2 |
Kojto | 122:f9eeca106725 | 892 | * @arg @ref LL_PWR_GPIO_BIT_3 |
Kojto | 122:f9eeca106725 | 893 | * @arg @ref LL_PWR_GPIO_BIT_4 |
Kojto | 122:f9eeca106725 | 894 | * @arg @ref LL_PWR_GPIO_BIT_5 |
Kojto | 122:f9eeca106725 | 895 | * @arg @ref LL_PWR_GPIO_BIT_6 |
Kojto | 122:f9eeca106725 | 896 | * @arg @ref LL_PWR_GPIO_BIT_7 |
Kojto | 122:f9eeca106725 | 897 | * @arg @ref LL_PWR_GPIO_BIT_8 |
Kojto | 122:f9eeca106725 | 898 | * @arg @ref LL_PWR_GPIO_BIT_9 |
Kojto | 122:f9eeca106725 | 899 | * @arg @ref LL_PWR_GPIO_BIT_10 |
Kojto | 122:f9eeca106725 | 900 | * @arg @ref LL_PWR_GPIO_BIT_11 |
Kojto | 122:f9eeca106725 | 901 | * @arg @ref LL_PWR_GPIO_BIT_12 |
Kojto | 122:f9eeca106725 | 902 | * @arg @ref LL_PWR_GPIO_BIT_13 |
Kojto | 122:f9eeca106725 | 903 | * @arg @ref LL_PWR_GPIO_BIT_14 |
Kojto | 122:f9eeca106725 | 904 | * @arg @ref LL_PWR_GPIO_BIT_15 |
Kojto | 122:f9eeca106725 | 905 | * @retval None |
Kojto | 122:f9eeca106725 | 906 | */ |
Kojto | 122:f9eeca106725 | 907 | __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) |
Kojto | 122:f9eeca106725 | 908 | { |
Kojto | 122:f9eeca106725 | 909 | SET_BIT(*((uint32_t *)GPIO), GPIONumber); |
Kojto | 122:f9eeca106725 | 910 | } |
Kojto | 122:f9eeca106725 | 911 | |
Kojto | 122:f9eeca106725 | 912 | /** |
Kojto | 122:f9eeca106725 | 913 | * @brief Disable GPIO pull-up state in Standby and Shutdown modes |
Kojto | 122:f9eeca106725 | 914 | * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n |
Kojto | 122:f9eeca106725 | 915 | * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n |
Kojto | 122:f9eeca106725 | 916 | * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n |
Kojto | 122:f9eeca106725 | 917 | * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n |
Kojto | 122:f9eeca106725 | 918 | * PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n |
Kojto | 122:f9eeca106725 | 919 | * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp\n |
Kojto | 122:f9eeca106725 | 920 | * PUCRG PU0-15 LL_PWR_DisableGPIOPullUp\n |
Kojto | 122:f9eeca106725 | 921 | * PUCRH PU0-1 LL_PWR_DisableGPIOPullUp |
Kojto | 122:f9eeca106725 | 922 | * @param GPIO This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 923 | * @arg @ref LL_PWR_GPIO_A |
Kojto | 122:f9eeca106725 | 924 | * @arg @ref LL_PWR_GPIO_B |
Kojto | 122:f9eeca106725 | 925 | * @arg @ref LL_PWR_GPIO_C |
Kojto | 122:f9eeca106725 | 926 | * @arg @ref LL_PWR_GPIO_D |
Kojto | 122:f9eeca106725 | 927 | * @arg @ref LL_PWR_GPIO_E |
Kojto | 122:f9eeca106725 | 928 | * @arg @ref LL_PWR_GPIO_F (*) |
Kojto | 122:f9eeca106725 | 929 | * @arg @ref LL_PWR_GPIO_G (*) |
Kojto | 122:f9eeca106725 | 930 | * @arg @ref LL_PWR_GPIO_H |
Kojto | 122:f9eeca106725 | 931 | * |
Kojto | 122:f9eeca106725 | 932 | * (*) value not defined in all devices |
Kojto | 122:f9eeca106725 | 933 | * @param GPIONumber This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 934 | * @arg @ref LL_PWR_GPIO_BIT_0 |
Kojto | 122:f9eeca106725 | 935 | * @arg @ref LL_PWR_GPIO_BIT_1 |
Kojto | 122:f9eeca106725 | 936 | * @arg @ref LL_PWR_GPIO_BIT_2 |
Kojto | 122:f9eeca106725 | 937 | * @arg @ref LL_PWR_GPIO_BIT_3 |
Kojto | 122:f9eeca106725 | 938 | * @arg @ref LL_PWR_GPIO_BIT_4 |
Kojto | 122:f9eeca106725 | 939 | * @arg @ref LL_PWR_GPIO_BIT_5 |
Kojto | 122:f9eeca106725 | 940 | * @arg @ref LL_PWR_GPIO_BIT_6 |
Kojto | 122:f9eeca106725 | 941 | * @arg @ref LL_PWR_GPIO_BIT_7 |
Kojto | 122:f9eeca106725 | 942 | * @arg @ref LL_PWR_GPIO_BIT_8 |
Kojto | 122:f9eeca106725 | 943 | * @arg @ref LL_PWR_GPIO_BIT_9 |
Kojto | 122:f9eeca106725 | 944 | * @arg @ref LL_PWR_GPIO_BIT_10 |
Kojto | 122:f9eeca106725 | 945 | * @arg @ref LL_PWR_GPIO_BIT_11 |
Kojto | 122:f9eeca106725 | 946 | * @arg @ref LL_PWR_GPIO_BIT_12 |
Kojto | 122:f9eeca106725 | 947 | * @arg @ref LL_PWR_GPIO_BIT_13 |
Kojto | 122:f9eeca106725 | 948 | * @arg @ref LL_PWR_GPIO_BIT_14 |
Kojto | 122:f9eeca106725 | 949 | * @arg @ref LL_PWR_GPIO_BIT_15 |
Kojto | 122:f9eeca106725 | 950 | * @retval None |
Kojto | 122:f9eeca106725 | 951 | */ |
Kojto | 122:f9eeca106725 | 952 | __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) |
Kojto | 122:f9eeca106725 | 953 | { |
Kojto | 122:f9eeca106725 | 954 | CLEAR_BIT(*((uint32_t *)GPIO), GPIONumber); |
Kojto | 122:f9eeca106725 | 955 | } |
Kojto | 122:f9eeca106725 | 956 | |
Kojto | 122:f9eeca106725 | 957 | /** |
Kojto | 122:f9eeca106725 | 958 | * @brief Check if GPIO pull-up state is enabled |
Kojto | 122:f9eeca106725 | 959 | * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n |
Kojto | 122:f9eeca106725 | 960 | * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n |
Kojto | 122:f9eeca106725 | 961 | * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n |
Kojto | 122:f9eeca106725 | 962 | * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n |
Kojto | 122:f9eeca106725 | 963 | * PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n |
Kojto | 122:f9eeca106725 | 964 | * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp\n |
Kojto | 122:f9eeca106725 | 965 | * PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp\n |
Kojto | 122:f9eeca106725 | 966 | * PUCRH PU0-1 LL_PWR_IsEnabledGPIOPullUp |
Kojto | 122:f9eeca106725 | 967 | * @param GPIO This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 968 | * @arg @ref LL_PWR_GPIO_A |
Kojto | 122:f9eeca106725 | 969 | * @arg @ref LL_PWR_GPIO_B |
Kojto | 122:f9eeca106725 | 970 | * @arg @ref LL_PWR_GPIO_C |
Kojto | 122:f9eeca106725 | 971 | * @arg @ref LL_PWR_GPIO_D |
Kojto | 122:f9eeca106725 | 972 | * @arg @ref LL_PWR_GPIO_E |
Kojto | 122:f9eeca106725 | 973 | * @arg @ref LL_PWR_GPIO_F (*) |
Kojto | 122:f9eeca106725 | 974 | * @arg @ref LL_PWR_GPIO_G (*) |
Kojto | 122:f9eeca106725 | 975 | * @arg @ref LL_PWR_GPIO_H |
Kojto | 122:f9eeca106725 | 976 | * |
Kojto | 122:f9eeca106725 | 977 | * (*) value not defined in all devices |
Kojto | 122:f9eeca106725 | 978 | * @param GPIONumber This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 979 | * @arg @ref LL_PWR_GPIO_BIT_0 |
Kojto | 122:f9eeca106725 | 980 | * @arg @ref LL_PWR_GPIO_BIT_1 |
Kojto | 122:f9eeca106725 | 981 | * @arg @ref LL_PWR_GPIO_BIT_2 |
Kojto | 122:f9eeca106725 | 982 | * @arg @ref LL_PWR_GPIO_BIT_3 |
Kojto | 122:f9eeca106725 | 983 | * @arg @ref LL_PWR_GPIO_BIT_4 |
Kojto | 122:f9eeca106725 | 984 | * @arg @ref LL_PWR_GPIO_BIT_5 |
Kojto | 122:f9eeca106725 | 985 | * @arg @ref LL_PWR_GPIO_BIT_6 |
Kojto | 122:f9eeca106725 | 986 | * @arg @ref LL_PWR_GPIO_BIT_7 |
Kojto | 122:f9eeca106725 | 987 | * @arg @ref LL_PWR_GPIO_BIT_8 |
Kojto | 122:f9eeca106725 | 988 | * @arg @ref LL_PWR_GPIO_BIT_9 |
Kojto | 122:f9eeca106725 | 989 | * @arg @ref LL_PWR_GPIO_BIT_10 |
Kojto | 122:f9eeca106725 | 990 | * @arg @ref LL_PWR_GPIO_BIT_11 |
Kojto | 122:f9eeca106725 | 991 | * @arg @ref LL_PWR_GPIO_BIT_12 |
Kojto | 122:f9eeca106725 | 992 | * @arg @ref LL_PWR_GPIO_BIT_13 |
Kojto | 122:f9eeca106725 | 993 | * @arg @ref LL_PWR_GPIO_BIT_14 |
Kojto | 122:f9eeca106725 | 994 | * @arg @ref LL_PWR_GPIO_BIT_15 |
Kojto | 122:f9eeca106725 | 995 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 996 | */ |
Kojto | 122:f9eeca106725 | 997 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) |
Kojto | 122:f9eeca106725 | 998 | { |
Kojto | 122:f9eeca106725 | 999 | return (READ_BIT(*((uint32_t *)(GPIO)), GPIONumber) == (GPIONumber)); |
Kojto | 122:f9eeca106725 | 1000 | } |
Kojto | 122:f9eeca106725 | 1001 | |
Kojto | 122:f9eeca106725 | 1002 | /** |
Kojto | 122:f9eeca106725 | 1003 | * @brief Enable GPIO pull-down state in Standby and Shutdown modes |
Kojto | 122:f9eeca106725 | 1004 | * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n |
Kojto | 122:f9eeca106725 | 1005 | * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n |
Kojto | 122:f9eeca106725 | 1006 | * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n |
Kojto | 122:f9eeca106725 | 1007 | * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n |
Kojto | 122:f9eeca106725 | 1008 | * PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n |
Kojto | 122:f9eeca106725 | 1009 | * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown\n |
Kojto | 122:f9eeca106725 | 1010 | * PDCRG PD0-15 LL_PWR_EnableGPIOPullDown\n |
Kojto | 122:f9eeca106725 | 1011 | * PDCRH PD0-1 LL_PWR_EnableGPIOPullDown |
Kojto | 122:f9eeca106725 | 1012 | * @param GPIO This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 1013 | * @arg @ref LL_PWR_GPIO_A |
Kojto | 122:f9eeca106725 | 1014 | * @arg @ref LL_PWR_GPIO_B |
Kojto | 122:f9eeca106725 | 1015 | * @arg @ref LL_PWR_GPIO_C |
Kojto | 122:f9eeca106725 | 1016 | * @arg @ref LL_PWR_GPIO_D |
Kojto | 122:f9eeca106725 | 1017 | * @arg @ref LL_PWR_GPIO_E |
Kojto | 122:f9eeca106725 | 1018 | * @arg @ref LL_PWR_GPIO_F (*) |
Kojto | 122:f9eeca106725 | 1019 | * @arg @ref LL_PWR_GPIO_G (*) |
Kojto | 122:f9eeca106725 | 1020 | * @arg @ref LL_PWR_GPIO_H |
Kojto | 122:f9eeca106725 | 1021 | * |
Kojto | 122:f9eeca106725 | 1022 | * (*) value not defined in all devices |
Kojto | 122:f9eeca106725 | 1023 | * @param GPIONumber This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 1024 | * @arg @ref LL_PWR_GPIO_BIT_0 |
Kojto | 122:f9eeca106725 | 1025 | * @arg @ref LL_PWR_GPIO_BIT_1 |
Kojto | 122:f9eeca106725 | 1026 | * @arg @ref LL_PWR_GPIO_BIT_2 |
Kojto | 122:f9eeca106725 | 1027 | * @arg @ref LL_PWR_GPIO_BIT_3 |
Kojto | 122:f9eeca106725 | 1028 | * @arg @ref LL_PWR_GPIO_BIT_4 |
Kojto | 122:f9eeca106725 | 1029 | * @arg @ref LL_PWR_GPIO_BIT_5 |
Kojto | 122:f9eeca106725 | 1030 | * @arg @ref LL_PWR_GPIO_BIT_6 |
Kojto | 122:f9eeca106725 | 1031 | * @arg @ref LL_PWR_GPIO_BIT_7 |
Kojto | 122:f9eeca106725 | 1032 | * @arg @ref LL_PWR_GPIO_BIT_8 |
Kojto | 122:f9eeca106725 | 1033 | * @arg @ref LL_PWR_GPIO_BIT_9 |
Kojto | 122:f9eeca106725 | 1034 | * @arg @ref LL_PWR_GPIO_BIT_10 |
Kojto | 122:f9eeca106725 | 1035 | * @arg @ref LL_PWR_GPIO_BIT_11 |
Kojto | 122:f9eeca106725 | 1036 | * @arg @ref LL_PWR_GPIO_BIT_12 |
Kojto | 122:f9eeca106725 | 1037 | * @arg @ref LL_PWR_GPIO_BIT_13 |
Kojto | 122:f9eeca106725 | 1038 | * @arg @ref LL_PWR_GPIO_BIT_14 |
Kojto | 122:f9eeca106725 | 1039 | * @arg @ref LL_PWR_GPIO_BIT_15 |
Kojto | 122:f9eeca106725 | 1040 | * @retval None |
Kojto | 122:f9eeca106725 | 1041 | */ |
Kojto | 122:f9eeca106725 | 1042 | __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) |
Kojto | 122:f9eeca106725 | 1043 | { |
Kojto | 122:f9eeca106725 | 1044 | register uint32_t temp = (uint32_t)(GPIO) + 4; |
Kojto | 122:f9eeca106725 | 1045 | SET_BIT(*((uint32_t *)(temp)), GPIONumber); |
Kojto | 122:f9eeca106725 | 1046 | } |
Kojto | 122:f9eeca106725 | 1047 | |
Kojto | 122:f9eeca106725 | 1048 | /** |
Kojto | 122:f9eeca106725 | 1049 | * @brief Disable GPIO pull-down state in Standby and Shutdown modes |
Kojto | 122:f9eeca106725 | 1050 | * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n |
Kojto | 122:f9eeca106725 | 1051 | * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n |
Kojto | 122:f9eeca106725 | 1052 | * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n |
Kojto | 122:f9eeca106725 | 1053 | * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n |
Kojto | 122:f9eeca106725 | 1054 | * PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n |
Kojto | 122:f9eeca106725 | 1055 | * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown\n |
Kojto | 122:f9eeca106725 | 1056 | * PDCRG PD0-15 LL_PWR_DisableGPIOPullDown\n |
Kojto | 122:f9eeca106725 | 1057 | * PDCRH PD0-1 LL_PWR_DisableGPIOPullDown |
Kojto | 122:f9eeca106725 | 1058 | * @param GPIO This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 1059 | * @arg @ref LL_PWR_GPIO_A |
Kojto | 122:f9eeca106725 | 1060 | * @arg @ref LL_PWR_GPIO_B |
Kojto | 122:f9eeca106725 | 1061 | * @arg @ref LL_PWR_GPIO_C |
Kojto | 122:f9eeca106725 | 1062 | * @arg @ref LL_PWR_GPIO_D |
Kojto | 122:f9eeca106725 | 1063 | * @arg @ref LL_PWR_GPIO_E |
Kojto | 122:f9eeca106725 | 1064 | * @arg @ref LL_PWR_GPIO_F (*) |
Kojto | 122:f9eeca106725 | 1065 | * @arg @ref LL_PWR_GPIO_G (*) |
Kojto | 122:f9eeca106725 | 1066 | * @arg @ref LL_PWR_GPIO_H |
Kojto | 122:f9eeca106725 | 1067 | * |
Kojto | 122:f9eeca106725 | 1068 | * (*) value not defined in all devices |
Kojto | 122:f9eeca106725 | 1069 | * @param GPIONumber This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 1070 | * @arg @ref LL_PWR_GPIO_BIT_0 |
Kojto | 122:f9eeca106725 | 1071 | * @arg @ref LL_PWR_GPIO_BIT_1 |
Kojto | 122:f9eeca106725 | 1072 | * @arg @ref LL_PWR_GPIO_BIT_2 |
Kojto | 122:f9eeca106725 | 1073 | * @arg @ref LL_PWR_GPIO_BIT_3 |
Kojto | 122:f9eeca106725 | 1074 | * @arg @ref LL_PWR_GPIO_BIT_4 |
Kojto | 122:f9eeca106725 | 1075 | * @arg @ref LL_PWR_GPIO_BIT_5 |
Kojto | 122:f9eeca106725 | 1076 | * @arg @ref LL_PWR_GPIO_BIT_6 |
Kojto | 122:f9eeca106725 | 1077 | * @arg @ref LL_PWR_GPIO_BIT_7 |
Kojto | 122:f9eeca106725 | 1078 | * @arg @ref LL_PWR_GPIO_BIT_8 |
Kojto | 122:f9eeca106725 | 1079 | * @arg @ref LL_PWR_GPIO_BIT_9 |
Kojto | 122:f9eeca106725 | 1080 | * @arg @ref LL_PWR_GPIO_BIT_10 |
Kojto | 122:f9eeca106725 | 1081 | * @arg @ref LL_PWR_GPIO_BIT_11 |
Kojto | 122:f9eeca106725 | 1082 | * @arg @ref LL_PWR_GPIO_BIT_12 |
Kojto | 122:f9eeca106725 | 1083 | * @arg @ref LL_PWR_GPIO_BIT_13 |
Kojto | 122:f9eeca106725 | 1084 | * @arg @ref LL_PWR_GPIO_BIT_14 |
Kojto | 122:f9eeca106725 | 1085 | * @arg @ref LL_PWR_GPIO_BIT_15 |
Kojto | 122:f9eeca106725 | 1086 | * @retval None |
Kojto | 122:f9eeca106725 | 1087 | */ |
Kojto | 122:f9eeca106725 | 1088 | __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) |
Kojto | 122:f9eeca106725 | 1089 | { |
Kojto | 122:f9eeca106725 | 1090 | register uint32_t temp = (uint32_t)(GPIO) + 4; |
Kojto | 122:f9eeca106725 | 1091 | CLEAR_BIT(*((uint32_t *)(temp)), GPIONumber); |
Kojto | 122:f9eeca106725 | 1092 | } |
Kojto | 122:f9eeca106725 | 1093 | |
Kojto | 122:f9eeca106725 | 1094 | /** |
Kojto | 122:f9eeca106725 | 1095 | * @brief Check if GPIO pull-down state is enabled |
Kojto | 122:f9eeca106725 | 1096 | * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n |
Kojto | 122:f9eeca106725 | 1097 | * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n |
Kojto | 122:f9eeca106725 | 1098 | * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n |
Kojto | 122:f9eeca106725 | 1099 | * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n |
Kojto | 122:f9eeca106725 | 1100 | * PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n |
Kojto | 122:f9eeca106725 | 1101 | * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown\n |
Kojto | 122:f9eeca106725 | 1102 | * PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown\n |
Kojto | 122:f9eeca106725 | 1103 | * PDCRH PD0-1 LL_PWR_IsEnabledGPIOPullDown |
Kojto | 122:f9eeca106725 | 1104 | * @param GPIO This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 1105 | * @arg @ref LL_PWR_GPIO_A |
Kojto | 122:f9eeca106725 | 1106 | * @arg @ref LL_PWR_GPIO_B |
Kojto | 122:f9eeca106725 | 1107 | * @arg @ref LL_PWR_GPIO_C |
Kojto | 122:f9eeca106725 | 1108 | * @arg @ref LL_PWR_GPIO_D |
Kojto | 122:f9eeca106725 | 1109 | * @arg @ref LL_PWR_GPIO_E |
Kojto | 122:f9eeca106725 | 1110 | * @arg @ref LL_PWR_GPIO_F (*) |
Kojto | 122:f9eeca106725 | 1111 | * @arg @ref LL_PWR_GPIO_G (*) |
Kojto | 122:f9eeca106725 | 1112 | * @arg @ref LL_PWR_GPIO_H |
Kojto | 122:f9eeca106725 | 1113 | * |
Kojto | 122:f9eeca106725 | 1114 | * (*) value not defined in all devices |
Kojto | 122:f9eeca106725 | 1115 | * @param GPIONumber This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 1116 | * @arg @ref LL_PWR_GPIO_BIT_0 |
Kojto | 122:f9eeca106725 | 1117 | * @arg @ref LL_PWR_GPIO_BIT_1 |
Kojto | 122:f9eeca106725 | 1118 | * @arg @ref LL_PWR_GPIO_BIT_2 |
Kojto | 122:f9eeca106725 | 1119 | * @arg @ref LL_PWR_GPIO_BIT_3 |
Kojto | 122:f9eeca106725 | 1120 | * @arg @ref LL_PWR_GPIO_BIT_4 |
Kojto | 122:f9eeca106725 | 1121 | * @arg @ref LL_PWR_GPIO_BIT_5 |
Kojto | 122:f9eeca106725 | 1122 | * @arg @ref LL_PWR_GPIO_BIT_6 |
Kojto | 122:f9eeca106725 | 1123 | * @arg @ref LL_PWR_GPIO_BIT_7 |
Kojto | 122:f9eeca106725 | 1124 | * @arg @ref LL_PWR_GPIO_BIT_8 |
Kojto | 122:f9eeca106725 | 1125 | * @arg @ref LL_PWR_GPIO_BIT_9 |
Kojto | 122:f9eeca106725 | 1126 | * @arg @ref LL_PWR_GPIO_BIT_10 |
Kojto | 122:f9eeca106725 | 1127 | * @arg @ref LL_PWR_GPIO_BIT_11 |
Kojto | 122:f9eeca106725 | 1128 | * @arg @ref LL_PWR_GPIO_BIT_12 |
Kojto | 122:f9eeca106725 | 1129 | * @arg @ref LL_PWR_GPIO_BIT_13 |
Kojto | 122:f9eeca106725 | 1130 | * @arg @ref LL_PWR_GPIO_BIT_14 |
Kojto | 122:f9eeca106725 | 1131 | * @arg @ref LL_PWR_GPIO_BIT_15 |
Kojto | 122:f9eeca106725 | 1132 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 1133 | */ |
Kojto | 122:f9eeca106725 | 1134 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) |
Kojto | 122:f9eeca106725 | 1135 | { |
Kojto | 122:f9eeca106725 | 1136 | register uint32_t temp = (uint32_t)(GPIO) + 4; |
Kojto | 122:f9eeca106725 | 1137 | return (READ_BIT(*((uint32_t *)(temp)), GPIONumber) == (GPIONumber)); |
Kojto | 122:f9eeca106725 | 1138 | } |
Kojto | 122:f9eeca106725 | 1139 | |
Kojto | 122:f9eeca106725 | 1140 | /** |
Kojto | 122:f9eeca106725 | 1141 | * @} |
Kojto | 122:f9eeca106725 | 1142 | */ |
Kojto | 122:f9eeca106725 | 1143 | |
Kojto | 122:f9eeca106725 | 1144 | /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management |
Kojto | 122:f9eeca106725 | 1145 | * @{ |
Kojto | 122:f9eeca106725 | 1146 | */ |
Kojto | 122:f9eeca106725 | 1147 | |
Kojto | 122:f9eeca106725 | 1148 | /** |
Kojto | 122:f9eeca106725 | 1149 | * @brief Get Internal Wake-up line Flag |
Kojto | 122:f9eeca106725 | 1150 | * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU |
Kojto | 122:f9eeca106725 | 1151 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 1152 | */ |
Kojto | 122:f9eeca106725 | 1153 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void) |
Kojto | 122:f9eeca106725 | 1154 | { |
Kojto | 122:f9eeca106725 | 1155 | return (READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)); |
Kojto | 122:f9eeca106725 | 1156 | } |
Kojto | 122:f9eeca106725 | 1157 | |
Kojto | 122:f9eeca106725 | 1158 | /** |
Kojto | 122:f9eeca106725 | 1159 | * @brief Get Stand-By Flag |
Kojto | 122:f9eeca106725 | 1160 | * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB |
Kojto | 122:f9eeca106725 | 1161 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 1162 | */ |
Kojto | 122:f9eeca106725 | 1163 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) |
Kojto | 122:f9eeca106725 | 1164 | { |
Kojto | 122:f9eeca106725 | 1165 | return (READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)); |
Kojto | 122:f9eeca106725 | 1166 | } |
Kojto | 122:f9eeca106725 | 1167 | |
Kojto | 122:f9eeca106725 | 1168 | /** |
Kojto | 122:f9eeca106725 | 1169 | * @brief Get Wake-up Flag 5 |
Kojto | 122:f9eeca106725 | 1170 | * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5 |
Kojto | 122:f9eeca106725 | 1171 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 1172 | */ |
Kojto | 122:f9eeca106725 | 1173 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) |
Kojto | 122:f9eeca106725 | 1174 | { |
Kojto | 122:f9eeca106725 | 1175 | return (READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)); |
Kojto | 122:f9eeca106725 | 1176 | } |
Kojto | 122:f9eeca106725 | 1177 | |
Kojto | 122:f9eeca106725 | 1178 | /** |
Kojto | 122:f9eeca106725 | 1179 | * @brief Get Wake-up Flag 4 |
Kojto | 122:f9eeca106725 | 1180 | * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4 |
Kojto | 122:f9eeca106725 | 1181 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 1182 | */ |
Kojto | 122:f9eeca106725 | 1183 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) |
Kojto | 122:f9eeca106725 | 1184 | { |
Kojto | 122:f9eeca106725 | 1185 | return (READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)); |
Kojto | 122:f9eeca106725 | 1186 | } |
Kojto | 122:f9eeca106725 | 1187 | |
Kojto | 122:f9eeca106725 | 1188 | /** |
Kojto | 122:f9eeca106725 | 1189 | * @brief Get Wake-up Flag 3 |
Kojto | 122:f9eeca106725 | 1190 | * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3 |
Kojto | 122:f9eeca106725 | 1191 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 1192 | */ |
Kojto | 122:f9eeca106725 | 1193 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) |
Kojto | 122:f9eeca106725 | 1194 | { |
Kojto | 122:f9eeca106725 | 1195 | return (READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)); |
Kojto | 122:f9eeca106725 | 1196 | } |
Kojto | 122:f9eeca106725 | 1197 | |
Kojto | 122:f9eeca106725 | 1198 | /** |
Kojto | 122:f9eeca106725 | 1199 | * @brief Get Wake-up Flag 2 |
Kojto | 122:f9eeca106725 | 1200 | * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2 |
Kojto | 122:f9eeca106725 | 1201 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 1202 | */ |
Kojto | 122:f9eeca106725 | 1203 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) |
Kojto | 122:f9eeca106725 | 1204 | { |
Kojto | 122:f9eeca106725 | 1205 | return (READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)); |
Kojto | 122:f9eeca106725 | 1206 | } |
Kojto | 122:f9eeca106725 | 1207 | |
Kojto | 122:f9eeca106725 | 1208 | /** |
Kojto | 122:f9eeca106725 | 1209 | * @brief Get Wake-up Flag 1 |
Kojto | 122:f9eeca106725 | 1210 | * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1 |
Kojto | 122:f9eeca106725 | 1211 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 1212 | */ |
Kojto | 122:f9eeca106725 | 1213 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) |
Kojto | 122:f9eeca106725 | 1214 | { |
Kojto | 122:f9eeca106725 | 1215 | return (READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)); |
Kojto | 122:f9eeca106725 | 1216 | } |
Kojto | 122:f9eeca106725 | 1217 | |
Kojto | 122:f9eeca106725 | 1218 | /** |
Kojto | 122:f9eeca106725 | 1219 | * @brief Clear Stand-By Flag |
Kojto | 122:f9eeca106725 | 1220 | * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB |
Kojto | 122:f9eeca106725 | 1221 | * @retval None |
Kojto | 122:f9eeca106725 | 1222 | */ |
Kojto | 122:f9eeca106725 | 1223 | __STATIC_INLINE void LL_PWR_ClearFlag_SB(void) |
Kojto | 122:f9eeca106725 | 1224 | { |
Kojto | 122:f9eeca106725 | 1225 | WRITE_REG(PWR->SCR, PWR_SCR_CSBF); |
Kojto | 122:f9eeca106725 | 1226 | } |
Kojto | 122:f9eeca106725 | 1227 | |
Kojto | 122:f9eeca106725 | 1228 | /** |
Kojto | 122:f9eeca106725 | 1229 | * @brief Clear Wake-up Flags |
Kojto | 122:f9eeca106725 | 1230 | * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU |
Kojto | 122:f9eeca106725 | 1231 | * @retval None |
Kojto | 122:f9eeca106725 | 1232 | */ |
Kojto | 122:f9eeca106725 | 1233 | __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) |
Kojto | 122:f9eeca106725 | 1234 | { |
Kojto | 122:f9eeca106725 | 1235 | WRITE_REG(PWR->SCR, PWR_SCR_CWUF); |
Kojto | 122:f9eeca106725 | 1236 | } |
Kojto | 122:f9eeca106725 | 1237 | |
Kojto | 122:f9eeca106725 | 1238 | /** |
Kojto | 122:f9eeca106725 | 1239 | * @brief Clear Wake-up Flag 5 |
Kojto | 122:f9eeca106725 | 1240 | * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5 |
Kojto | 122:f9eeca106725 | 1241 | * @retval None |
Kojto | 122:f9eeca106725 | 1242 | */ |
Kojto | 122:f9eeca106725 | 1243 | __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) |
Kojto | 122:f9eeca106725 | 1244 | { |
Kojto | 122:f9eeca106725 | 1245 | WRITE_REG(PWR->SCR, PWR_SCR_CWUF5); |
Kojto | 122:f9eeca106725 | 1246 | } |
Kojto | 122:f9eeca106725 | 1247 | |
Kojto | 122:f9eeca106725 | 1248 | /** |
Kojto | 122:f9eeca106725 | 1249 | * @brief Clear Wake-up Flag 4 |
Kojto | 122:f9eeca106725 | 1250 | * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4 |
Kojto | 122:f9eeca106725 | 1251 | * @retval None |
Kojto | 122:f9eeca106725 | 1252 | */ |
Kojto | 122:f9eeca106725 | 1253 | __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) |
Kojto | 122:f9eeca106725 | 1254 | { |
Kojto | 122:f9eeca106725 | 1255 | WRITE_REG(PWR->SCR, PWR_SCR_CWUF4); |
Kojto | 122:f9eeca106725 | 1256 | } |
Kojto | 122:f9eeca106725 | 1257 | |
Kojto | 122:f9eeca106725 | 1258 | /** |
Kojto | 122:f9eeca106725 | 1259 | * @brief Clear Wake-up Flag 3 |
Kojto | 122:f9eeca106725 | 1260 | * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3 |
Kojto | 122:f9eeca106725 | 1261 | * @retval None |
Kojto | 122:f9eeca106725 | 1262 | */ |
Kojto | 122:f9eeca106725 | 1263 | __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) |
Kojto | 122:f9eeca106725 | 1264 | { |
Kojto | 122:f9eeca106725 | 1265 | WRITE_REG(PWR->SCR, PWR_SCR_CWUF3); |
Kojto | 122:f9eeca106725 | 1266 | } |
Kojto | 122:f9eeca106725 | 1267 | |
Kojto | 122:f9eeca106725 | 1268 | /** |
Kojto | 122:f9eeca106725 | 1269 | * @brief Clear Wake-up Flag 2 |
Kojto | 122:f9eeca106725 | 1270 | * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2 |
Kojto | 122:f9eeca106725 | 1271 | * @retval None |
Kojto | 122:f9eeca106725 | 1272 | */ |
Kojto | 122:f9eeca106725 | 1273 | __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) |
Kojto | 122:f9eeca106725 | 1274 | { |
Kojto | 122:f9eeca106725 | 1275 | WRITE_REG(PWR->SCR, PWR_SCR_CWUF2); |
Kojto | 122:f9eeca106725 | 1276 | } |
Kojto | 122:f9eeca106725 | 1277 | |
Kojto | 122:f9eeca106725 | 1278 | /** |
Kojto | 122:f9eeca106725 | 1279 | * @brief Clear Wake-up Flag 1 |
Kojto | 122:f9eeca106725 | 1280 | * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1 |
Kojto | 122:f9eeca106725 | 1281 | * @retval None |
Kojto | 122:f9eeca106725 | 1282 | */ |
Kojto | 122:f9eeca106725 | 1283 | __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) |
Kojto | 122:f9eeca106725 | 1284 | { |
Kojto | 122:f9eeca106725 | 1285 | WRITE_REG(PWR->SCR, PWR_SCR_CWUF1); |
Kojto | 122:f9eeca106725 | 1286 | } |
Kojto | 122:f9eeca106725 | 1287 | |
Kojto | 122:f9eeca106725 | 1288 | /** |
Kojto | 122:f9eeca106725 | 1289 | * @brief Indicate whether VDDA voltage is below or above PVM4 threshold |
Kojto | 122:f9eeca106725 | 1290 | * @rmtoll SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4 |
Kojto | 122:f9eeca106725 | 1291 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 1292 | */ |
Kojto | 122:f9eeca106725 | 1293 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void) |
Kojto | 122:f9eeca106725 | 1294 | { |
Kojto | 122:f9eeca106725 | 1295 | return (READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4)); |
Kojto | 122:f9eeca106725 | 1296 | } |
Kojto | 122:f9eeca106725 | 1297 | |
Kojto | 122:f9eeca106725 | 1298 | /** |
Kojto | 122:f9eeca106725 | 1299 | * @brief Indicate whether VDDA voltage is below or above PVM3 threshold |
Kojto | 122:f9eeca106725 | 1300 | * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3 |
Kojto | 122:f9eeca106725 | 1301 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 1302 | */ |
Kojto | 122:f9eeca106725 | 1303 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void) |
Kojto | 122:f9eeca106725 | 1304 | { |
Kojto | 122:f9eeca106725 | 1305 | return (READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)); |
Kojto | 122:f9eeca106725 | 1306 | } |
Kojto | 122:f9eeca106725 | 1307 | |
Kojto | 122:f9eeca106725 | 1308 | #if defined(PWR_SR2_PVMO2) |
Kojto | 122:f9eeca106725 | 1309 | /** |
Kojto | 122:f9eeca106725 | 1310 | * @brief Indicate whether VDDIO2 voltage is below or above PVM2 threshold |
Kojto | 122:f9eeca106725 | 1311 | * @rmtoll SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2 |
Kojto | 122:f9eeca106725 | 1312 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 1313 | */ |
Kojto | 122:f9eeca106725 | 1314 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void) |
Kojto | 122:f9eeca106725 | 1315 | { |
Kojto | 122:f9eeca106725 | 1316 | return (READ_BIT(PWR->SR2, PWR_SR2_PVMO2) == (PWR_SR2_PVMO2)); |
Kojto | 122:f9eeca106725 | 1317 | } |
Kojto | 122:f9eeca106725 | 1318 | #endif /* PWR_SR2_PVMO2 */ |
Kojto | 122:f9eeca106725 | 1319 | |
Kojto | 122:f9eeca106725 | 1320 | #if defined(USB_OTG_FS) |
Kojto | 122:f9eeca106725 | 1321 | /** |
Kojto | 122:f9eeca106725 | 1322 | * @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold |
Kojto | 122:f9eeca106725 | 1323 | * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1 |
Kojto | 122:f9eeca106725 | 1324 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 1325 | */ |
Kojto | 122:f9eeca106725 | 1326 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void) |
Kojto | 122:f9eeca106725 | 1327 | { |
Kojto | 122:f9eeca106725 | 1328 | return (READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)); |
Kojto | 122:f9eeca106725 | 1329 | } |
Kojto | 122:f9eeca106725 | 1330 | #endif /* USB_OTG_FS */ |
Kojto | 122:f9eeca106725 | 1331 | |
Kojto | 122:f9eeca106725 | 1332 | /** |
Kojto | 122:f9eeca106725 | 1333 | * @brief Indicate whether VDD voltage is below or above the selected PVD threshold |
Kojto | 122:f9eeca106725 | 1334 | * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO |
Kojto | 122:f9eeca106725 | 1335 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 1336 | */ |
Kojto | 122:f9eeca106725 | 1337 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) |
Kojto | 122:f9eeca106725 | 1338 | { |
Kojto | 122:f9eeca106725 | 1339 | return (READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)); |
Kojto | 122:f9eeca106725 | 1340 | } |
Kojto | 122:f9eeca106725 | 1341 | |
Kojto | 122:f9eeca106725 | 1342 | /** |
Kojto | 122:f9eeca106725 | 1343 | * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level |
Kojto | 122:f9eeca106725 | 1344 | * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOSF |
Kojto | 122:f9eeca106725 | 1345 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 1346 | */ |
Kojto | 122:f9eeca106725 | 1347 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOSF(void) |
Kojto | 122:f9eeca106725 | 1348 | { |
Kojto | 122:f9eeca106725 | 1349 | return (READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)); |
Kojto | 122:f9eeca106725 | 1350 | } |
Kojto | 122:f9eeca106725 | 1351 | |
Kojto | 122:f9eeca106725 | 1352 | /** |
Kojto | 122:f9eeca106725 | 1353 | * @brief Indicate whether the regulator is ready in main mode or is in low-power mode |
Kojto | 122:f9eeca106725 | 1354 | * @note: Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing. |
Kojto | 122:f9eeca106725 | 1355 | * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF |
Kojto | 122:f9eeca106725 | 1356 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 1357 | */ |
Kojto | 122:f9eeca106725 | 1358 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void) |
Kojto | 122:f9eeca106725 | 1359 | { |
Kojto | 122:f9eeca106725 | 1360 | return (READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)); |
Kojto | 122:f9eeca106725 | 1361 | } |
Kojto | 122:f9eeca106725 | 1362 | |
Kojto | 122:f9eeca106725 | 1363 | /** |
Kojto | 122:f9eeca106725 | 1364 | * @brief Indicate whether or not the low-power regulator is ready |
Kojto | 122:f9eeca106725 | 1365 | * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS |
Kojto | 122:f9eeca106725 | 1366 | * @retval State of bit (1 or 0). |
Kojto | 122:f9eeca106725 | 1367 | */ |
Kojto | 122:f9eeca106725 | 1368 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void) |
Kojto | 122:f9eeca106725 | 1369 | { |
Kojto | 122:f9eeca106725 | 1370 | return (READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)); |
Kojto | 122:f9eeca106725 | 1371 | } |
Kojto | 122:f9eeca106725 | 1372 | |
Kojto | 122:f9eeca106725 | 1373 | #if defined(USE_FULL_LL_DRIVER) |
Kojto | 122:f9eeca106725 | 1374 | /** @defgroup PWR_LL_EF_Init De-initialization function |
Kojto | 122:f9eeca106725 | 1375 | * @{ |
Kojto | 122:f9eeca106725 | 1376 | */ |
Kojto | 122:f9eeca106725 | 1377 | ErrorStatus LL_PWR_DeInit(void); |
Kojto | 122:f9eeca106725 | 1378 | /** |
Kojto | 122:f9eeca106725 | 1379 | * @} |
Kojto | 122:f9eeca106725 | 1380 | */ |
Kojto | 122:f9eeca106725 | 1381 | #endif /* USE_FULL_LL_DRIVER */ |
Kojto | 122:f9eeca106725 | 1382 | |
Kojto | 122:f9eeca106725 | 1383 | /** |
Kojto | 122:f9eeca106725 | 1384 | * @} |
Kojto | 122:f9eeca106725 | 1385 | */ |
Kojto | 122:f9eeca106725 | 1386 | |
Kojto | 122:f9eeca106725 | 1387 | |
Kojto | 122:f9eeca106725 | 1388 | /** |
Kojto | 122:f9eeca106725 | 1389 | * @} |
Kojto | 122:f9eeca106725 | 1390 | */ |
Kojto | 122:f9eeca106725 | 1391 | |
Kojto | 122:f9eeca106725 | 1392 | /** |
Kojto | 122:f9eeca106725 | 1393 | * @} |
Kojto | 122:f9eeca106725 | 1394 | */ |
Kojto | 122:f9eeca106725 | 1395 | |
Kojto | 122:f9eeca106725 | 1396 | #endif /* defined(PWR) */ |
Kojto | 122:f9eeca106725 | 1397 | |
Kojto | 122:f9eeca106725 | 1398 | /** |
Kojto | 122:f9eeca106725 | 1399 | * @} |
Kojto | 122:f9eeca106725 | 1400 | */ |
Kojto | 122:f9eeca106725 | 1401 | |
Kojto | 122:f9eeca106725 | 1402 | #ifdef __cplusplus |
Kojto | 122:f9eeca106725 | 1403 | } |
Kojto | 122:f9eeca106725 | 1404 | #endif |
Kojto | 122:f9eeca106725 | 1405 | |
Kojto | 122:f9eeca106725 | 1406 | #endif /* __STM32L4xx_LL_PWR_H */ |
Kojto | 122:f9eeca106725 | 1407 | |
Kojto | 122:f9eeca106725 | 1408 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |