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TARGET_NUCLEO_L486RG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:: <>
Date:: Wed Apr 12 16:07:08 2017 +0100
Revision:: 140:97feb9bacc10
Parent:: 128:9bcdf88f62b0
Child:: 145:64910690c574

Release 140 of the mbed library

Ports for Upcoming Targets

3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992

Fixes and Changes

3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	122:f9eeca106725	1	/**
Kojto	122:f9eeca106725	2	******************************************************************************
Kojto	122:f9eeca106725	3	* @file stm32l4xx_ll_dma.h
Kojto	122:f9eeca106725	4	* @author MCD Application Team
Kojto	122:f9eeca106725	5	* @version V1.5.1
Kojto	122:f9eeca106725	6	* @date 31-May-2016
Kojto	122:f9eeca106725	7	* @brief Header file of DMA LL module.
Kojto	122:f9eeca106725	8	******************************************************************************
Kojto	122:f9eeca106725	9	* @attention
Kojto	122:f9eeca106725	10	*
Kojto	122:f9eeca106725	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto	122:f9eeca106725	12	*
Kojto	122:f9eeca106725	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	122:f9eeca106725	14	* are permitted provided that the following conditions are met:
Kojto	122:f9eeca106725	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	122:f9eeca106725	16	* this list of conditions and the following disclaimer.
Kojto	122:f9eeca106725	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	122:f9eeca106725	18	* this list of conditions and the following disclaimer in the documentation
Kojto	122:f9eeca106725	19	* and/or other materials provided with the distribution.
Kojto	122:f9eeca106725	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	122:f9eeca106725	21	* may be used to endorse or promote products derived from this software
Kojto	122:f9eeca106725	22	* without specific prior written permission.
Kojto	122:f9eeca106725	23	*
Kojto	122:f9eeca106725	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	122:f9eeca106725	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	122:f9eeca106725	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	122:f9eeca106725	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	122:f9eeca106725	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	122:f9eeca106725	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	122:f9eeca106725	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	122:f9eeca106725	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	122:f9eeca106725	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	122:f9eeca106725	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	122:f9eeca106725	34	*
Kojto	122:f9eeca106725	35	******************************************************************************
Kojto	122:f9eeca106725	36	*/
Kojto	122:f9eeca106725	37
Kojto	122:f9eeca106725	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	122:f9eeca106725	39	#ifndef __STM32L4xx_LL_DMA_H
Kojto	122:f9eeca106725	40	#define __STM32L4xx_LL_DMA_H
Kojto	122:f9eeca106725	41
Kojto	122:f9eeca106725	42	#ifdef __cplusplus
Kojto	122:f9eeca106725	43	extern "C" {
Kojto	122:f9eeca106725	44	#endif
Kojto	122:f9eeca106725	45
Kojto	122:f9eeca106725	46	/* Includes ------------------------------------------------------------------*/
Kojto	122:f9eeca106725	47	#include "stm32l4xx.h"
Kojto	122:f9eeca106725	48
Kojto	122:f9eeca106725	49	/** @addtogroup STM32L4xx_LL_Driver
Kojto	122:f9eeca106725	50	* @{
Kojto	122:f9eeca106725	51	*/
Kojto	122:f9eeca106725	52
Kojto	122:f9eeca106725	53	#if defined (DMA1) \|\| defined (DMA2)
Kojto	122:f9eeca106725	54
Kojto	122:f9eeca106725	55	/** @defgroup DMA_LL DMA
Kojto	122:f9eeca106725	56	* @{
Kojto	122:f9eeca106725	57	*/
Kojto	122:f9eeca106725	58
Kojto	122:f9eeca106725	59	/* Private types -------------------------------------------------------------*/
Kojto	122:f9eeca106725	60	/* Private variables ---------------------------------------------------------*/
Kojto	122:f9eeca106725	61	/** @defgroup DMA_LL_Private_Variables DMA Private Variables
Kojto	122:f9eeca106725	62	* @{
Kojto	122:f9eeca106725	63	*/
Kojto	122:f9eeca106725	64	/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
Kojto	122:f9eeca106725	65	static const uint8_t CHANNEL_OFFSET_TAB[] =
Kojto	122:f9eeca106725	66	{
Kojto	122:f9eeca106725	67	(uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
Kojto	122:f9eeca106725	68	(uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
Kojto	122:f9eeca106725	69	(uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
Kojto	122:f9eeca106725	70	(uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
Kojto	122:f9eeca106725	71	(uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
Kojto	122:f9eeca106725	72	(uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
Kojto	122:f9eeca106725	73	(uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
Kojto	122:f9eeca106725	74	};
Kojto	122:f9eeca106725	75	/**
Kojto	122:f9eeca106725	76	* @}
Kojto	122:f9eeca106725	77	*/
Kojto	122:f9eeca106725	78
Kojto	122:f9eeca106725	79	/* Private constants ---------------------------------------------------------*/
Kojto	122:f9eeca106725	80	/** @defgroup DMA_LL_Private_Constants DMA Private Constants
Kojto	122:f9eeca106725	81	* @{
Kojto	122:f9eeca106725	82	*/
Kojto	122:f9eeca106725	83	/* Define used to get CSELR register offset */
Kojto	122:f9eeca106725	84	#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
Kojto	122:f9eeca106725	85
Kojto	122:f9eeca106725	86	/* Defines used for the bit position in the register and perform offsets */
Kojto	122:f9eeca106725	87	#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
Kojto	122:f9eeca106725	88	/**
Kojto	122:f9eeca106725	89	* @}
Kojto	122:f9eeca106725	90	*/
Kojto	122:f9eeca106725	91
Kojto	122:f9eeca106725	92	/* Private macros ------------------------------------------------------------*/
Kojto	122:f9eeca106725	93	#if defined(USE_FULL_LL_DRIVER)
Kojto	122:f9eeca106725	94	/** @defgroup DMA_LL_Private_Macros DMA Private Macros
Kojto	122:f9eeca106725	95	* @{
Kojto	122:f9eeca106725	96	*/
Kojto	122:f9eeca106725	97	/**
Kojto	122:f9eeca106725	98	* @}
Kojto	122:f9eeca106725	99	*/
Kojto	122:f9eeca106725	100	#endif /USE_FULL_LL_DRIVER/
Kojto	122:f9eeca106725	101
Kojto	122:f9eeca106725	102	/* Exported types ------------------------------------------------------------*/
Kojto	122:f9eeca106725	103	#if defined(USE_FULL_LL_DRIVER)
Kojto	122:f9eeca106725	104	/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
Kojto	122:f9eeca106725	105	* @{
Kojto	122:f9eeca106725	106	*/
Kojto	122:f9eeca106725	107	typedef struct
Kojto	122:f9eeca106725	108	{
Kojto	122:f9eeca106725	109	uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
Kojto	122:f9eeca106725	110	or as Source base address in case of memory to memory transfer direction.
Kojto	122:f9eeca106725	111
Kojto	122:f9eeca106725	112	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
Kojto	122:f9eeca106725	113
Kojto	122:f9eeca106725	114	uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
Kojto	122:f9eeca106725	115	or as Destination base address in case of memory to memory transfer direction.
Kojto	122:f9eeca106725	116
Kojto	122:f9eeca106725	117	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
Kojto	122:f9eeca106725	118
Kojto	122:f9eeca106725	119	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
Kojto	122:f9eeca106725	120	from memory to memory or from peripheral to memory.
Kojto	122:f9eeca106725	121	This parameter can be a value of @ref DMA_LL_EC_DIRECTION
Kojto	122:f9eeca106725	122
Kojto	122:f9eeca106725	123	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
Kojto	122:f9eeca106725	124
Kojto	122:f9eeca106725	125	uint32_t Mode; /*!< Specifies the normal or circular operation mode.
Kojto	122:f9eeca106725	126	This parameter can be a value of @ref DMA_LL_EC_MODE
Kojto	122:f9eeca106725	127	@note: The circular buffer mode cannot be used if the memory to memory
Kojto	122:f9eeca106725	128	data transfer direction is configured on the selected Channel
Kojto	122:f9eeca106725	129
Kojto	122:f9eeca106725	130	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
Kojto	122:f9eeca106725	131
Kojto	122:f9eeca106725	132	uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
Kojto	122:f9eeca106725	133	is incremented or not.
Kojto	122:f9eeca106725	134	This parameter can be a value of @ref DMA_LL_EC_PERIPH
Kojto	122:f9eeca106725	135
Kojto	122:f9eeca106725	136	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
Kojto	122:f9eeca106725	137
Kojto	122:f9eeca106725	138	uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
Kojto	122:f9eeca106725	139	is incremented or not.
Kojto	122:f9eeca106725	140	This parameter can be a value of @ref DMA_LL_EC_MEMORY
Kojto	122:f9eeca106725	141
Kojto	122:f9eeca106725	142	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
Kojto	122:f9eeca106725	143
Kojto	122:f9eeca106725	144	uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
Kojto	122:f9eeca106725	145	in case of memory to memory transfer direction.
Kojto	122:f9eeca106725	146	This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
Kojto	122:f9eeca106725	147
Kojto	122:f9eeca106725	148	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
Kojto	122:f9eeca106725	149
Kojto	122:f9eeca106725	150	uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
Kojto	122:f9eeca106725	151	in case of memory to memory transfer direction.
Kojto	122:f9eeca106725	152	This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
Kojto	122:f9eeca106725	153
Kojto	122:f9eeca106725	154	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
Kojto	122:f9eeca106725	155
Kojto	122:f9eeca106725	156	uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
Kojto	122:f9eeca106725	157	The data unit is equal to the source buffer configuration set in PeripheralSize
Kojto	122:f9eeca106725	158	or MemorySize parameters depending in the transfer direction.
Kojto	122:f9eeca106725	159	This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
Kojto	122:f9eeca106725	160
Kojto	122:f9eeca106725	161	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
Kojto	122:f9eeca106725	162
Kojto	122:f9eeca106725	163	uint32_t PeriphRequest; /*!< Specifies the peripheral request.
Kojto	122:f9eeca106725	164	This parameter can be a value of @ref DMA_LL_EC_REQUEST
Kojto	122:f9eeca106725	165
Kojto	122:f9eeca106725	166	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
Kojto	122:f9eeca106725	167
Kojto	122:f9eeca106725	168	uint32_t Priority; /*!< Specifies the channel priority level.
Kojto	122:f9eeca106725	169	This parameter can be a value of @ref DMA_LL_EC_PRIORITY
Kojto	122:f9eeca106725	170
Kojto	122:f9eeca106725	171	This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
Kojto	122:f9eeca106725	172
Kojto	122:f9eeca106725	173	} LL_DMA_InitTypeDef;
Kojto	122:f9eeca106725	174	/**
Kojto	122:f9eeca106725	175	* @}
Kojto	122:f9eeca106725	176	*/
Kojto	122:f9eeca106725	177	#endif /USE_FULL_LL_DRIVER/
Kojto	122:f9eeca106725	178
Kojto	122:f9eeca106725	179	/* Exported constants --------------------------------------------------------*/
Kojto	122:f9eeca106725	180	/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
Kojto	122:f9eeca106725	181	* @{
Kojto	122:f9eeca106725	182	*/
Kojto	122:f9eeca106725	183	/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
Kojto	122:f9eeca106725	184	* @brief Flags defines which can be used with LL_DMA_WriteReg function
Kojto	122:f9eeca106725	185	* @{
Kojto	122:f9eeca106725	186	*/
Kojto	122:f9eeca106725	187	#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /!< Channel 1 global flag /
Kojto	122:f9eeca106725	188	#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /!< Channel 1 transfer complete flag /
Kojto	122:f9eeca106725	189	#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /!< Channel 1 half transfer flag /
Kojto	122:f9eeca106725	190	#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /!< Channel 1 transfer error flag /
Kojto	122:f9eeca106725	191	#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /!< Channel 2 global flag /
Kojto	122:f9eeca106725	192	#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /!< Channel 2 transfer complete flag /
Kojto	122:f9eeca106725	193	#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /!< Channel 2 half transfer flag /
Kojto	122:f9eeca106725	194	#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /!< Channel 2 transfer error flag /
Kojto	122:f9eeca106725	195	#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /!< Channel 3 global flag /
Kojto	122:f9eeca106725	196	#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /!< Channel 3 transfer complete flag /
Kojto	122:f9eeca106725	197	#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /!< Channel 3 half transfer flag /
Kojto	122:f9eeca106725	198	#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /!< Channel 3 transfer error flag /
Kojto	122:f9eeca106725	199	#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /!< Channel 4 global flag /
Kojto	122:f9eeca106725	200	#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /!< Channel 4 transfer complete flag /
Kojto	122:f9eeca106725	201	#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /!< Channel 4 half transfer flag /
Kojto	122:f9eeca106725	202	#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /!< Channel 4 transfer error flag /
Kojto	122:f9eeca106725	203	#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /!< Channel 5 global flag /
Kojto	122:f9eeca106725	204	#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /!< Channel 5 transfer complete flag /
Kojto	122:f9eeca106725	205	#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /!< Channel 5 half transfer flag /
Kojto	122:f9eeca106725	206	#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /!< Channel 5 transfer error flag /
Kojto	122:f9eeca106725	207	#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /!< Channel 6 global flag /
Kojto	122:f9eeca106725	208	#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /!< Channel 6 transfer complete flag /
Kojto	122:f9eeca106725	209	#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /!< Channel 6 half transfer flag /
Kojto	122:f9eeca106725	210	#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /!< Channel 6 transfer error flag /
Kojto	122:f9eeca106725	211	#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /!< Channel 7 global flag /
Kojto	122:f9eeca106725	212	#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /!< Channel 7 transfer complete flag /
Kojto	122:f9eeca106725	213	#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /!< Channel 7 half transfer flag /
Kojto	122:f9eeca106725	214	#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /!< Channel 7 transfer error flag /
Kojto	122:f9eeca106725	215	/**
Kojto	122:f9eeca106725	216	* @}
Kojto	122:f9eeca106725	217	*/
Kojto	122:f9eeca106725	218
Kojto	122:f9eeca106725	219	/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
Kojto	122:f9eeca106725	220	* @brief Flags defines which can be used with LL_DMA_ReadReg function
Kojto	122:f9eeca106725	221	* @{
Kojto	122:f9eeca106725	222	*/
Kojto	122:f9eeca106725	223	#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /!< Channel 1 global flag /
Kojto	122:f9eeca106725	224	#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /!< Channel 1 transfer complete flag /
Kojto	122:f9eeca106725	225	#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /!< Channel 1 half transfer flag /
Kojto	122:f9eeca106725	226	#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /!< Channel 1 transfer error flag /
Kojto	122:f9eeca106725	227	#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /!< Channel 2 global flag /
Kojto	122:f9eeca106725	228	#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /!< Channel 2 transfer complete flag /
Kojto	122:f9eeca106725	229	#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /!< Channel 2 half transfer flag /
Kojto	122:f9eeca106725	230	#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /!< Channel 2 transfer error flag /
Kojto	122:f9eeca106725	231	#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /!< Channel 3 global flag /
Kojto	122:f9eeca106725	232	#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /!< Channel 3 transfer complete flag /
Kojto	122:f9eeca106725	233	#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /!< Channel 3 half transfer flag /
Kojto	122:f9eeca106725	234	#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /!< Channel 3 transfer error flag /
Kojto	122:f9eeca106725	235	#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /!< Channel 4 global flag /
Kojto	122:f9eeca106725	236	#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /!< Channel 4 transfer complete flag /
Kojto	122:f9eeca106725	237	#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /!< Channel 4 half transfer flag /
Kojto	122:f9eeca106725	238	#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /!< Channel 4 transfer error flag /
Kojto	122:f9eeca106725	239	#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /!< Channel 5 global flag /
Kojto	122:f9eeca106725	240	#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /!< Channel 5 transfer complete flag /
Kojto	122:f9eeca106725	241	#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /!< Channel 5 half transfer flag /
Kojto	122:f9eeca106725	242	#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /!< Channel 5 transfer error flag /
Kojto	122:f9eeca106725	243	#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /!< Channel 6 global flag /
Kojto	122:f9eeca106725	244	#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /!< Channel 6 transfer complete flag /
Kojto	122:f9eeca106725	245	#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /!< Channel 6 half transfer flag /
Kojto	122:f9eeca106725	246	#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /!< Channel 6 transfer error flag /
Kojto	122:f9eeca106725	247	#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /!< Channel 7 global flag /
Kojto	122:f9eeca106725	248	#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /!< Channel 7 transfer complete flag /
Kojto	122:f9eeca106725	249	#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /!< Channel 7 half transfer flag /
Kojto	122:f9eeca106725	250	#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /!< Channel 7 transfer error flag /
Kojto	122:f9eeca106725	251	/**
Kojto	122:f9eeca106725	252	* @}
Kojto	122:f9eeca106725	253	*/
Kojto	122:f9eeca106725	254
Kojto	122:f9eeca106725	255	/** @defgroup DMA_LL_EC_IT IT Defines
Kojto	122:f9eeca106725	256	* @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
Kojto	122:f9eeca106725	257	* @{
Kojto	122:f9eeca106725	258	*/
Kojto	122:f9eeca106725	259	#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /!< Transfer complete interrupt /
Kojto	122:f9eeca106725	260	#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /!< Half Transfer interrupt /
Kojto	122:f9eeca106725	261	#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /!< Transfer error interrupt /
Kojto	122:f9eeca106725	262	/**
Kojto	122:f9eeca106725	263	* @}
Kojto	122:f9eeca106725	264	*/
Kojto	122:f9eeca106725	265
Kojto	122:f9eeca106725	266	/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
Kojto	122:f9eeca106725	267	* @{
Kojto	122:f9eeca106725	268	*/
Kojto	122:f9eeca106725	269	#define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /!< DMA Channel 1 /
Kojto	122:f9eeca106725	270	#define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /!< DMA Channel 2 /
Kojto	122:f9eeca106725	271	#define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /!< DMA Channel 3 /
Kojto	122:f9eeca106725	272	#define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /!< DMA Channel 4 /
Kojto	122:f9eeca106725	273	#define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /!< DMA Channel 5 /
Kojto	122:f9eeca106725	274	#define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /!< DMA Channel 6 /
Kojto	122:f9eeca106725	275	#define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /!< DMA Channel 7 /
Kojto	122:f9eeca106725	276	#if defined(USE_FULL_LL_DRIVER)
Kojto	122:f9eeca106725	277	#define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). /
Kojto	122:f9eeca106725	278	#endif /USE_FULL_LL_DRIVER/
Kojto	122:f9eeca106725	279	/**
Kojto	122:f9eeca106725	280	* @}
Kojto	122:f9eeca106725	281	*/
Kojto	122:f9eeca106725	282
Kojto	122:f9eeca106725	283	/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
Kojto	122:f9eeca106725	284	* @{
Kojto	122:f9eeca106725	285	*/
Kojto	122:f9eeca106725	286	#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /!< Peripheral to memory direction /
Kojto	122:f9eeca106725	287	#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /!< Memory to peripheral direction /
Kojto	122:f9eeca106725	288	#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /!< Memory to memory direction /
Kojto	122:f9eeca106725	289	/**
Kojto	122:f9eeca106725	290	* @}
Kojto	122:f9eeca106725	291	*/
Kojto	122:f9eeca106725	292
Kojto	122:f9eeca106725	293	/** @defgroup DMA_LL_EC_MODE Transfer mode
Kojto	122:f9eeca106725	294	* @{
Kojto	122:f9eeca106725	295	*/
Kojto	122:f9eeca106725	296	#define LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U) /!< Normal Mode /
Kojto	122:f9eeca106725	297	#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /!< Circular Mode /
Kojto	122:f9eeca106725	298	/**
Kojto	122:f9eeca106725	299	* @}
Kojto	122:f9eeca106725	300	*/
Kojto	122:f9eeca106725	301
Kojto	122:f9eeca106725	302	/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
Kojto	122:f9eeca106725	303	* @{
Kojto	122:f9eeca106725	304	*/
Kojto	122:f9eeca106725	305	#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /!< Peripheral increment mode Enable /
Kojto	122:f9eeca106725	306	#define LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U) /!< Peripheral increment mode Disable /
Kojto	122:f9eeca106725	307	/**
Kojto	122:f9eeca106725	308	* @}
Kojto	122:f9eeca106725	309	*/
Kojto	122:f9eeca106725	310
Kojto	122:f9eeca106725	311	/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
Kojto	122:f9eeca106725	312	* @{
Kojto	122:f9eeca106725	313	*/
Kojto	122:f9eeca106725	314	#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /!< Memory increment mode Enable /
Kojto	122:f9eeca106725	315	#define LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U) /!< Memory increment mode Disable /
Kojto	122:f9eeca106725	316	/**
Kojto	122:f9eeca106725	317	* @}
Kojto	122:f9eeca106725	318	*/
Kojto	122:f9eeca106725	319
Kojto	122:f9eeca106725	320	/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
Kojto	122:f9eeca106725	321	* @{
Kojto	122:f9eeca106725	322	*/
Kojto	122:f9eeca106725	323	#define LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /!< Peripheral data alignment : Byte /
Kojto	122:f9eeca106725	324	#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /!< Peripheral data alignment : HalfWord /
Kojto	122:f9eeca106725	325	#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /!< Peripheral data alignment : Word /
Kojto	122:f9eeca106725	326	/**
Kojto	122:f9eeca106725	327	* @}
Kojto	122:f9eeca106725	328	*/
Kojto	122:f9eeca106725	329
Kojto	122:f9eeca106725	330	/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
Kojto	122:f9eeca106725	331	* @{
Kojto	122:f9eeca106725	332	*/
Kojto	122:f9eeca106725	333	#define LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /!< Memory data alignment : Byte /
Kojto	122:f9eeca106725	334	#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /!< Memory data alignment : HalfWord /
Kojto	122:f9eeca106725	335	#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /!< Memory data alignment : Word /
Kojto	122:f9eeca106725	336	/**
Kojto	122:f9eeca106725	337	* @}
Kojto	122:f9eeca106725	338	*/
Kojto	122:f9eeca106725	339
Kojto	122:f9eeca106725	340	/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
Kojto	122:f9eeca106725	341	* @{
Kojto	122:f9eeca106725	342	*/
Kojto	122:f9eeca106725	343	#define LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /!< Priority level : Low /
Kojto	122:f9eeca106725	344	#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /!< Priority level : Medium /
Kojto	122:f9eeca106725	345	#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /!< Priority level : High /
Kojto	122:f9eeca106725	346	#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /!< Priority level : Very_High /
Kojto	122:f9eeca106725	347	/**
Kojto	122:f9eeca106725	348	* @}
Kojto	122:f9eeca106725	349	*/
Kojto	122:f9eeca106725	350
Kojto	122:f9eeca106725	351	/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
Kojto	122:f9eeca106725	352	* @{
Kojto	122:f9eeca106725	353	*/
Kojto	122:f9eeca106725	354	#define LL_DMA_REQUEST_0 ((uint32_t)0x00000000U) /!< DMA peripheral request 0 /
Kojto	122:f9eeca106725	355	#define LL_DMA_REQUEST_1 ((uint32_t)0x00000001U) /!< DMA peripheral request 1 /
Kojto	122:f9eeca106725	356	#define LL_DMA_REQUEST_2 ((uint32_t)0x00000002U) /!< DMA peripheral request 2 /
Kojto	122:f9eeca106725	357	#define LL_DMA_REQUEST_3 ((uint32_t)0x00000003U) /!< DMA peripheral request 3 /
Kojto	122:f9eeca106725	358	#define LL_DMA_REQUEST_4 ((uint32_t)0x00000004U) /!< DMA peripheral request 4 /
Kojto	122:f9eeca106725	359	#define LL_DMA_REQUEST_5 ((uint32_t)0x00000005U) /!< DMA peripheral request 5 /
Kojto	122:f9eeca106725	360	#define LL_DMA_REQUEST_6 ((uint32_t)0x00000006U) /!< DMA peripheral request 6 /
Kojto	122:f9eeca106725	361	#define LL_DMA_REQUEST_7 ((uint32_t)0x00000007U) /!< DMA peripheral request 7 /
Kojto	122:f9eeca106725	362	/**
Kojto	122:f9eeca106725	363	* @}
Kojto	122:f9eeca106725	364	*/
Kojto	122:f9eeca106725	365
Kojto	122:f9eeca106725	366	/**
Kojto	122:f9eeca106725	367	* @}
Kojto	122:f9eeca106725	368	*/
Kojto	122:f9eeca106725	369
Kojto	122:f9eeca106725	370	/* Exported macro ------------------------------------------------------------*/
Kojto	122:f9eeca106725	371	/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
Kojto	122:f9eeca106725	372	* @{
Kojto	122:f9eeca106725	373	*/
Kojto	122:f9eeca106725	374
Kojto	122:f9eeca106725	375	/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
Kojto	122:f9eeca106725	376	* @{
Kojto	122:f9eeca106725	377	*/
Kojto	122:f9eeca106725	378	/**
Kojto	122:f9eeca106725	379	* @brief Write a value in DMA register
Kojto	122:f9eeca106725	380	* @param __INSTANCE__ DMA Instance
Kojto	122:f9eeca106725	381	* @param __REG__ Register to be written
Kojto	122:f9eeca106725	382	* @param __VALUE__ Value to be written in the register
Kojto	122:f9eeca106725	383	* @retval None
Kojto	122:f9eeca106725	384	*/
Kojto	122:f9eeca106725	385	#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Kojto	122:f9eeca106725	386
Kojto	122:f9eeca106725	387	/**
Kojto	122:f9eeca106725	388	* @brief Read a value in DMA register
Kojto	122:f9eeca106725	389	* @param __INSTANCE__ DMA Instance
Kojto	122:f9eeca106725	390	* @param __REG__ Register to be read
Kojto	122:f9eeca106725	391	* @retval Register value
Kojto	122:f9eeca106725	392	*/
Kojto	122:f9eeca106725	393	#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Kojto	122:f9eeca106725	394	/**
Kojto	122:f9eeca106725	395	* @}
Kojto	122:f9eeca106725	396	*/
Kojto	122:f9eeca106725	397
Kojto	122:f9eeca106725	398	/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
Kojto	122:f9eeca106725	399	* @{
Kojto	122:f9eeca106725	400	*/
Kojto	122:f9eeca106725	401	/**
Kojto	122:f9eeca106725	402	* @brief Convert DMAx_Channely into DMAx
Kojto	122:f9eeca106725	403	* @param __CHANNEL_INSTANCE__ DMAx_Channely
Kojto	122:f9eeca106725	404	* @retval DMAx
Kojto	122:f9eeca106725	405	*/
Kojto	122:f9eeca106725	406	#if defined(DMA2)
Kojto	122:f9eeca106725	407	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
Kojto	122:f9eeca106725	408	(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
Kojto	122:f9eeca106725	409	#else
Kojto	122:f9eeca106725	410	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
Kojto	122:f9eeca106725	411	#endif
Kojto	122:f9eeca106725	412
Kojto	122:f9eeca106725	413	/**
Kojto	122:f9eeca106725	414	* @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
Kojto	122:f9eeca106725	415	* @param __CHANNEL_INSTANCE__ DMAx_Channely
Kojto	122:f9eeca106725	416	* @retval LL_DMA_CHANNEL_y
Kojto	122:f9eeca106725	417	*/
Kojto	122:f9eeca106725	418	#if defined (DMA2)
Kojto	122:f9eeca106725	419	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
Kojto	122:f9eeca106725	420	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
Kojto	122:f9eeca106725	421	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
Kojto	122:f9eeca106725	422	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
Kojto	122:f9eeca106725	423	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
Kojto	122:f9eeca106725	424	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
Kojto	122:f9eeca106725	425	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
Kojto	122:f9eeca106725	426	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
Kojto	122:f9eeca106725	427	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
Kojto	122:f9eeca106725	428	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
Kojto	122:f9eeca106725	429	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
Kojto	122:f9eeca106725	430	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
Kojto	122:f9eeca106725	431	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
Kojto	122:f9eeca106725	432	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
Kojto	122:f9eeca106725	433	LL_DMA_CHANNEL_7)
Kojto	122:f9eeca106725	434	#else
Kojto	122:f9eeca106725	435	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
Kojto	122:f9eeca106725	436	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
Kojto	122:f9eeca106725	437	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
Kojto	122:f9eeca106725	438	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
Kojto	122:f9eeca106725	439	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
Kojto	122:f9eeca106725	440	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
Kojto	122:f9eeca106725	441	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
Kojto	122:f9eeca106725	442	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
Kojto	122:f9eeca106725	443	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
Kojto	122:f9eeca106725	444	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
Kojto	122:f9eeca106725	445	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
Kojto	122:f9eeca106725	446	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
Kojto	122:f9eeca106725	447	LL_DMA_CHANNEL_7)
Kojto	122:f9eeca106725	448	#endif
Kojto	122:f9eeca106725	449	#else
Kojto	122:f9eeca106725	450	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
Kojto	122:f9eeca106725	451	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
Kojto	122:f9eeca106725	452	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
Kojto	122:f9eeca106725	453	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
Kojto	122:f9eeca106725	454	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
Kojto	122:f9eeca106725	455	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
Kojto	122:f9eeca106725	456	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
Kojto	122:f9eeca106725	457	LL_DMA_CHANNEL_7)
Kojto	122:f9eeca106725	458	#endif
Kojto	122:f9eeca106725	459
Kojto	122:f9eeca106725	460	/**
Kojto	122:f9eeca106725	461	* @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
Kojto	122:f9eeca106725	462	* @param __DMA_INSTANCE__ DMAx
Kojto	122:f9eeca106725	463	* @param __CHANNEL__ LL_DMA_CHANNEL_y
Kojto	122:f9eeca106725	464	* @retval DMAx_Channely
Kojto	122:f9eeca106725	465	*/
Kojto	122:f9eeca106725	466	#if defined (DMA2)
Kojto	122:f9eeca106725	467	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
Kojto	122:f9eeca106725	468	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
Kojto	122:f9eeca106725	469	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
Kojto	122:f9eeca106725	470	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
Kojto	122:f9eeca106725	471	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
Kojto	122:f9eeca106725	472	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
Kojto	122:f9eeca106725	473	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
Kojto	122:f9eeca106725	474	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
Kojto	122:f9eeca106725	475	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
Kojto	122:f9eeca106725	476	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
Kojto	122:f9eeca106725	477	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
Kojto	122:f9eeca106725	478	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
Kojto	122:f9eeca106725	479	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
Kojto	122:f9eeca106725	480	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
Kojto	122:f9eeca106725	481	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
Kojto	122:f9eeca106725	482	DMA2_Channel7)
Kojto	122:f9eeca106725	483	#else
Kojto	122:f9eeca106725	484	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
Kojto	122:f9eeca106725	485	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
Kojto	122:f9eeca106725	486	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
Kojto	122:f9eeca106725	487	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
Kojto	122:f9eeca106725	488	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
Kojto	122:f9eeca106725	489	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
Kojto	122:f9eeca106725	490	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
Kojto	122:f9eeca106725	491	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
Kojto	122:f9eeca106725	492	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
Kojto	122:f9eeca106725	493	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
Kojto	122:f9eeca106725	494	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
Kojto	122:f9eeca106725	495	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
Kojto	122:f9eeca106725	496	DMA1_Channel7)
Kojto	122:f9eeca106725	497	#endif
Kojto	122:f9eeca106725	498	#else
Kojto	122:f9eeca106725	499	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
Kojto	122:f9eeca106725	500	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
Kojto	122:f9eeca106725	501	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
Kojto	122:f9eeca106725	502	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
Kojto	122:f9eeca106725	503	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
Kojto	122:f9eeca106725	504	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
Kojto	122:f9eeca106725	505	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
Kojto	122:f9eeca106725	506	DMA1_Channel7)
Kojto	122:f9eeca106725	507	#endif
Kojto	122:f9eeca106725	508
Kojto	122:f9eeca106725	509	/**
Kojto	122:f9eeca106725	510	* @}
Kojto	122:f9eeca106725	511	*/
Kojto	122:f9eeca106725	512
Kojto	122:f9eeca106725	513	/**
Kojto	122:f9eeca106725	514	* @}
Kojto	122:f9eeca106725	515	*/
Kojto	122:f9eeca106725	516
Kojto	122:f9eeca106725	517	/* Exported functions --------------------------------------------------------*/
Kojto	122:f9eeca106725	518	/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
Kojto	122:f9eeca106725	519	* @{
Kojto	122:f9eeca106725	520	*/
Kojto	122:f9eeca106725	521
Kojto	122:f9eeca106725	522	/** @defgroup DMA_LL_EF_Configuration Configuration
Kojto	122:f9eeca106725	523	* @{
Kojto	122:f9eeca106725	524	*/
Kojto	122:f9eeca106725	525	/**
Kojto	122:f9eeca106725	526	* @brief Enable DMA channel.
Kojto	122:f9eeca106725	527	* @rmtoll CCR EN LL_DMA_EnableChannel
Kojto	122:f9eeca106725	528	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	529	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	530	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	531	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	532	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	533	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	534	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	535	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	536	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	537	* @retval None
Kojto	122:f9eeca106725	538	*/
Kojto	122:f9eeca106725	539	__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	540	{
Kojto	122:f9eeca106725	541	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
Kojto	122:f9eeca106725	542	}
Kojto	122:f9eeca106725	543
Kojto	122:f9eeca106725	544	/**
Kojto	122:f9eeca106725	545	* @brief Disable DMA channel.
Kojto	122:f9eeca106725	546	* @rmtoll CCR EN LL_DMA_DisableChannel
Kojto	122:f9eeca106725	547	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	548	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	549	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	550	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	551	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	552	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	553	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	554	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	555	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	556	* @retval None
Kojto	122:f9eeca106725	557	*/
Kojto	122:f9eeca106725	558	__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	559	{
Kojto	122:f9eeca106725	560	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
Kojto	122:f9eeca106725	561	}
Kojto	122:f9eeca106725	562
Kojto	122:f9eeca106725	563	/**
Kojto	122:f9eeca106725	564	* @brief Check if DMA channel is enabled or disabled.
Kojto	122:f9eeca106725	565	* @rmtoll CCR EN LL_DMA_IsEnabledChannel
Kojto	122:f9eeca106725	566	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	567	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	568	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	569	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	570	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	571	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	572	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	573	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	574	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	575	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	576	*/
Kojto	122:f9eeca106725	577	__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	578	{
Kojto	122:f9eeca106725	579	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
Kojto	122:f9eeca106725	580	DMA_CCR_EN) == (DMA_CCR_EN));
Kojto	122:f9eeca106725	581	}
Kojto	122:f9eeca106725	582
Kojto	122:f9eeca106725	583	/**
Kojto	122:f9eeca106725	584	* @brief Configure all parameters link to DMA transfer.
Kojto	122:f9eeca106725	585	* @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
Kojto	122:f9eeca106725	586	* CCR MEM2MEM LL_DMA_ConfigTransfer\n
Kojto	122:f9eeca106725	587	* CCR CIRC LL_DMA_ConfigTransfer\n
Kojto	122:f9eeca106725	588	* CCR PINC LL_DMA_ConfigTransfer\n
Kojto	122:f9eeca106725	589	* CCR MINC LL_DMA_ConfigTransfer\n
Kojto	122:f9eeca106725	590	* CCR PSIZE LL_DMA_ConfigTransfer\n
Kojto	122:f9eeca106725	591	* CCR MSIZE LL_DMA_ConfigTransfer\n
Kojto	122:f9eeca106725	592	* CCR PL LL_DMA_ConfigTransfer
Kojto	122:f9eeca106725	593	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	594	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	595	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	596	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	597	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	598	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	599	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	600	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	601	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	602	* @param Configuration This parameter must be a combination of all the following values:
Kojto	122:f9eeca106725	603	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
Kojto	122:f9eeca106725	604	* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
Kojto	122:f9eeca106725	605	* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
Kojto	122:f9eeca106725	606	* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
Kojto	122:f9eeca106725	607	* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
Kojto	122:f9eeca106725	608	* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
Kojto	122:f9eeca106725	609	* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
Kojto	122:f9eeca106725	610	* @retval None
Kojto	122:f9eeca106725	611	*/
Kojto	122:f9eeca106725	612	__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
Kojto	122:f9eeca106725	613	{
Kojto	122:f9eeca106725	614	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
Kojto	122:f9eeca106725	615	DMA_CCR_DIR \| DMA_CCR_MEM2MEM \| DMA_CCR_CIRC \| DMA_CCR_PINC \| DMA_CCR_MINC \| DMA_CCR_PSIZE \| DMA_CCR_MSIZE \| DMA_CCR_PL,
Kojto	122:f9eeca106725	616	Configuration);
Kojto	122:f9eeca106725	617	}
Kojto	122:f9eeca106725	618
Kojto	122:f9eeca106725	619	/**
Kojto	122:f9eeca106725	620	* @brief Set Data transfer direction (read from peripheral or from memory).
Kojto	122:f9eeca106725	621	* @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
Kojto	122:f9eeca106725	622	* CCR MEM2MEM LL_DMA_SetDataTransferDirection
Kojto	122:f9eeca106725	623	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	624	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	625	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	626	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	627	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	628	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	629	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	630	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	631	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	632	* @param Direction This parameter can be one of the following values:
Kojto	122:f9eeca106725	633	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
Kojto	122:f9eeca106725	634	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
Kojto	122:f9eeca106725	635	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
Kojto	122:f9eeca106725	636	* @retval None
Kojto	122:f9eeca106725	637	*/
Kojto	122:f9eeca106725	638	__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
Kojto	122:f9eeca106725	639	{
Kojto	122:f9eeca106725	640	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
Kojto	122:f9eeca106725	641	DMA_CCR_DIR \| DMA_CCR_MEM2MEM, Direction);
Kojto	122:f9eeca106725	642	}
Kojto	122:f9eeca106725	643
Kojto	122:f9eeca106725	644	/**
Kojto	122:f9eeca106725	645	* @brief Get Data transfer direction (read from peripheral or from memory).
Kojto	122:f9eeca106725	646	* @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
Kojto	122:f9eeca106725	647	* CCR MEM2MEM LL_DMA_GetDataTransferDirection
Kojto	122:f9eeca106725	648	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	649	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	650	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	651	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	652	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	653	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	654	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	655	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	656	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	657	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	658	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
Kojto	122:f9eeca106725	659	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
Kojto	122:f9eeca106725	660	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
Kojto	122:f9eeca106725	661	*/
Kojto	122:f9eeca106725	662	__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	663	{
Kojto	122:f9eeca106725	664	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
Kojto	122:f9eeca106725	665	DMA_CCR_DIR \| DMA_CCR_MEM2MEM));
Kojto	122:f9eeca106725	666	}
Kojto	122:f9eeca106725	667
Kojto	122:f9eeca106725	668	/**
Kojto	122:f9eeca106725	669	* @brief Set DMA mode circular or normal.
Kojto	122:f9eeca106725	670	* @note The circular buffer mode cannot be used if the memory-to-memory
Kojto	122:f9eeca106725	671	* data transfer is configured on the selected Channel.
Kojto	122:f9eeca106725	672	* @rmtoll CCR CIRC LL_DMA_SetMode
Kojto	122:f9eeca106725	673	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	674	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	675	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	676	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	677	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	678	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	679	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	680	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	681	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	682	* @param Mode This parameter can be one of the following values:
Kojto	122:f9eeca106725	683	* @arg @ref LL_DMA_MODE_NORMAL
Kojto	122:f9eeca106725	684	* @arg @ref LL_DMA_MODE_CIRCULAR
Kojto	122:f9eeca106725	685	* @retval None
Kojto	122:f9eeca106725	686	*/
Kojto	122:f9eeca106725	687	__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
Kojto	122:f9eeca106725	688	{
Kojto	122:f9eeca106725	689	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
Kojto	122:f9eeca106725	690	Mode);
Kojto	122:f9eeca106725	691	}
Kojto	122:f9eeca106725	692
Kojto	122:f9eeca106725	693	/**
Kojto	122:f9eeca106725	694	* @brief Get DMA mode circular or normal.
Kojto	122:f9eeca106725	695	* @rmtoll CCR CIRC LL_DMA_GetMode
Kojto	122:f9eeca106725	696	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	697	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	698	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	699	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	700	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	701	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	702	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	703	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	704	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	705	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	706	* @arg @ref LL_DMA_MODE_NORMAL
Kojto	122:f9eeca106725	707	* @arg @ref LL_DMA_MODE_CIRCULAR
Kojto	122:f9eeca106725	708	*/
Kojto	122:f9eeca106725	709	__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	710	{
Kojto	122:f9eeca106725	711	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
Kojto	122:f9eeca106725	712	DMA_CCR_CIRC));
Kojto	122:f9eeca106725	713	}
Kojto	122:f9eeca106725	714
Kojto	122:f9eeca106725	715	/**
Kojto	122:f9eeca106725	716	* @brief Set Peripheral increment mode.
Kojto	122:f9eeca106725	717	* @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
Kojto	122:f9eeca106725	718	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	719	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	720	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	721	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	722	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	723	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	724	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	725	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	726	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	727	* @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
Kojto	122:f9eeca106725	728	* @arg @ref LL_DMA_PERIPH_INCREMENT
Kojto	122:f9eeca106725	729	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
Kojto	122:f9eeca106725	730	* @retval None
Kojto	122:f9eeca106725	731	*/
Kojto	122:f9eeca106725	732	__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
Kojto	122:f9eeca106725	733	{
Kojto	122:f9eeca106725	734	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
Kojto	122:f9eeca106725	735	PeriphOrM2MSrcIncMode);
Kojto	122:f9eeca106725	736	}
Kojto	122:f9eeca106725	737
Kojto	122:f9eeca106725	738	/**
Kojto	122:f9eeca106725	739	* @brief Get Peripheral increment mode.
Kojto	122:f9eeca106725	740	* @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
Kojto	122:f9eeca106725	741	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	742	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	743	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	744	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	745	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	746	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	747	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	748	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	749	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	750	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	751	* @arg @ref LL_DMA_PERIPH_INCREMENT
Kojto	122:f9eeca106725	752	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
Kojto	122:f9eeca106725	753	*/
Kojto	122:f9eeca106725	754	__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	755	{
Kojto	122:f9eeca106725	756	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
Kojto	122:f9eeca106725	757	DMA_CCR_PINC));
Kojto	122:f9eeca106725	758	}
Kojto	122:f9eeca106725	759
Kojto	122:f9eeca106725	760	/**
Kojto	122:f9eeca106725	761	* @brief Set Memory increment mode.
Kojto	122:f9eeca106725	762	* @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
Kojto	122:f9eeca106725	763	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	764	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	765	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	766	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	767	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	768	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	769	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	770	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	771	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	772	* @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
Kojto	122:f9eeca106725	773	* @arg @ref LL_DMA_MEMORY_INCREMENT
Kojto	122:f9eeca106725	774	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
Kojto	122:f9eeca106725	775	* @retval None
Kojto	122:f9eeca106725	776	*/
Kojto	122:f9eeca106725	777	__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
Kojto	122:f9eeca106725	778	{
Kojto	122:f9eeca106725	779	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
Kojto	122:f9eeca106725	780	MemoryOrM2MDstIncMode);
Kojto	122:f9eeca106725	781	}
Kojto	122:f9eeca106725	782
Kojto	122:f9eeca106725	783	/**
Kojto	122:f9eeca106725	784	* @brief Get Memory increment mode.
Kojto	122:f9eeca106725	785	* @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
Kojto	122:f9eeca106725	786	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	787	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	788	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	789	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	790	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	791	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	792	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	793	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	794	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	795	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	796	* @arg @ref LL_DMA_MEMORY_INCREMENT
Kojto	122:f9eeca106725	797	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
Kojto	122:f9eeca106725	798	*/
Kojto	122:f9eeca106725	799	__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	800	{
Kojto	122:f9eeca106725	801	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
Kojto	122:f9eeca106725	802	DMA_CCR_MINC));
Kojto	122:f9eeca106725	803	}
Kojto	122:f9eeca106725	804
Kojto	122:f9eeca106725	805	/**
Kojto	122:f9eeca106725	806	* @brief Set Peripheral size.
Kojto	122:f9eeca106725	807	* @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
Kojto	122:f9eeca106725	808	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	809	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	810	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	811	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	812	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	813	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	814	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	815	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	816	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	817	* @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
Kojto	122:f9eeca106725	818	* @arg @ref LL_DMA_PDATAALIGN_BYTE
Kojto	122:f9eeca106725	819	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
Kojto	122:f9eeca106725	820	* @arg @ref LL_DMA_PDATAALIGN_WORD
Kojto	122:f9eeca106725	821	* @retval None
Kojto	122:f9eeca106725	822	*/
Kojto	122:f9eeca106725	823	__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
Kojto	122:f9eeca106725	824	{
Kojto	122:f9eeca106725	825	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
Kojto	122:f9eeca106725	826	PeriphOrM2MSrcDataSize);
Kojto	122:f9eeca106725	827	}
Kojto	122:f9eeca106725	828
Kojto	122:f9eeca106725	829	/**
Kojto	122:f9eeca106725	830	* @brief Get Peripheral size.
Kojto	122:f9eeca106725	831	* @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
Kojto	122:f9eeca106725	832	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	833	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	834	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	835	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	836	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	837	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	838	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	839	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	840	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	841	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	842	* @arg @ref LL_DMA_PDATAALIGN_BYTE
Kojto	122:f9eeca106725	843	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
Kojto	122:f9eeca106725	844	* @arg @ref LL_DMA_PDATAALIGN_WORD
Kojto	122:f9eeca106725	845	*/
Kojto	122:f9eeca106725	846	__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	847	{
Kojto	122:f9eeca106725	848	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
Kojto	122:f9eeca106725	849	DMA_CCR_PSIZE));
Kojto	122:f9eeca106725	850	}
Kojto	122:f9eeca106725	851
Kojto	122:f9eeca106725	852	/**
Kojto	122:f9eeca106725	853	* @brief Set Memory size.
Kojto	122:f9eeca106725	854	* @rmtoll CCR MSIZE LL_DMA_SetMemorySize
Kojto	122:f9eeca106725	855	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	856	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	857	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	858	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	859	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	860	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	861	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	862	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	863	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	864	* @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
Kojto	122:f9eeca106725	865	* @arg @ref LL_DMA_MDATAALIGN_BYTE
Kojto	122:f9eeca106725	866	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
Kojto	122:f9eeca106725	867	* @arg @ref LL_DMA_MDATAALIGN_WORD
Kojto	122:f9eeca106725	868	* @retval None
Kojto	122:f9eeca106725	869	*/
Kojto	122:f9eeca106725	870	__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
Kojto	122:f9eeca106725	871	{
Kojto	122:f9eeca106725	872	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
Kojto	122:f9eeca106725	873	MemoryOrM2MDstDataSize);
Kojto	122:f9eeca106725	874	}
Kojto	122:f9eeca106725	875
Kojto	122:f9eeca106725	876	/**
Kojto	122:f9eeca106725	877	* @brief Get Memory size.
Kojto	122:f9eeca106725	878	* @rmtoll CCR MSIZE LL_DMA_GetMemorySize
Kojto	122:f9eeca106725	879	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	880	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	881	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	882	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	883	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	884	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	885	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	886	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	887	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	888	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	889	* @arg @ref LL_DMA_MDATAALIGN_BYTE
Kojto	122:f9eeca106725	890	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
Kojto	122:f9eeca106725	891	* @arg @ref LL_DMA_MDATAALIGN_WORD
Kojto	122:f9eeca106725	892	*/
Kojto	122:f9eeca106725	893	__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	894	{
Kojto	122:f9eeca106725	895	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
Kojto	122:f9eeca106725	896	DMA_CCR_MSIZE));
Kojto	122:f9eeca106725	897	}
Kojto	122:f9eeca106725	898
Kojto	122:f9eeca106725	899	/**
Kojto	122:f9eeca106725	900	* @brief Set Channel priority level.
Kojto	122:f9eeca106725	901	* @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
Kojto	122:f9eeca106725	902	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	903	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	904	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	905	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	906	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	907	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	908	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	909	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	910	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	911	* @param Priority This parameter can be one of the following values:
Kojto	122:f9eeca106725	912	* @arg @ref LL_DMA_PRIORITY_LOW
Kojto	122:f9eeca106725	913	* @arg @ref LL_DMA_PRIORITY_MEDIUM
Kojto	122:f9eeca106725	914	* @arg @ref LL_DMA_PRIORITY_HIGH
Kojto	122:f9eeca106725	915	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
Kojto	122:f9eeca106725	916	* @retval None
Kojto	122:f9eeca106725	917	*/
Kojto	122:f9eeca106725	918	__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
Kojto	122:f9eeca106725	919	{
Kojto	122:f9eeca106725	920	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
Kojto	122:f9eeca106725	921	Priority);
Kojto	122:f9eeca106725	922	}
Kojto	122:f9eeca106725	923
Kojto	122:f9eeca106725	924	/**
Kojto	122:f9eeca106725	925	* @brief Get Channel priority level.
Kojto	122:f9eeca106725	926	* @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
Kojto	122:f9eeca106725	927	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	928	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	929	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	930	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	931	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	932	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	933	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	934	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	935	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	936	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	937	* @arg @ref LL_DMA_PRIORITY_LOW
Kojto	122:f9eeca106725	938	* @arg @ref LL_DMA_PRIORITY_MEDIUM
Kojto	122:f9eeca106725	939	* @arg @ref LL_DMA_PRIORITY_HIGH
Kojto	122:f9eeca106725	940	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
Kojto	122:f9eeca106725	941	*/
Kojto	122:f9eeca106725	942	__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	943	{
Kojto	122:f9eeca106725	944	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
Kojto	122:f9eeca106725	945	DMA_CCR_PL));
Kojto	122:f9eeca106725	946	}
Kojto	122:f9eeca106725	947
Kojto	122:f9eeca106725	948	/**
Kojto	122:f9eeca106725	949	* @brief Set Number of data to transfer.
Kojto	122:f9eeca106725	950	* @note This action has no effect if
Kojto	122:f9eeca106725	951	* channel is enabled.
Kojto	122:f9eeca106725	952	* @rmtoll CNDTR NDT LL_DMA_SetDataLength
Kojto	122:f9eeca106725	953	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	954	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	955	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	956	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	957	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	958	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	959	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	960	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	961	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	962	* @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
Kojto	122:f9eeca106725	963	* @retval None
Kojto	122:f9eeca106725	964	*/
Kojto	122:f9eeca106725	965	__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
Kojto	122:f9eeca106725	966	{
Kojto	122:f9eeca106725	967	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
Kojto	122:f9eeca106725	968	DMA_CNDTR_NDT, NbData);
Kojto	122:f9eeca106725	969	}
Kojto	122:f9eeca106725	970
Kojto	122:f9eeca106725	971	/**
Kojto	122:f9eeca106725	972	* @brief Get Number of data to transfer.
Kojto	122:f9eeca106725	973	* @note Once the channel is enabled, the return value indicate the
Kojto	122:f9eeca106725	974	* remaining bytes to be transmitted.
Kojto	122:f9eeca106725	975	* @rmtoll CNDTR NDT LL_DMA_GetDataLength
Kojto	122:f9eeca106725	976	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	977	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	978	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	979	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	980	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	981	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	982	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	983	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	984	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	985	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Kojto	122:f9eeca106725	986	*/
Kojto	122:f9eeca106725	987	__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	988	{
Kojto	122:f9eeca106725	989	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
Kojto	122:f9eeca106725	990	DMA_CNDTR_NDT));
Kojto	122:f9eeca106725	991	}
Kojto	122:f9eeca106725	992
Kojto	122:f9eeca106725	993	/**
Kojto	122:f9eeca106725	994	* @brief Configure the Source and Destination addresses.
Kojto	122:f9eeca106725	995	* @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr)
Kojto	122:f9eeca106725	996	* @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
Kojto	122:f9eeca106725	997	* CMAR MA LL_DMA_ConfigAddresses
Kojto	122:f9eeca106725	998	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	999	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	1000	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	1001	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	1002	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	1003	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	1004	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	1005	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	1006	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	1007	* @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Kojto	122:f9eeca106725	1008	* @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Kojto	122:f9eeca106725	1009	* @param Direction This parameter can be one of the following values:
Kojto	122:f9eeca106725	1010	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
Kojto	122:f9eeca106725	1011	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
Kojto	122:f9eeca106725	1012	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
Kojto	122:f9eeca106725	1013	* @retval None
Kojto	122:f9eeca106725	1014	*/
Kojto	122:f9eeca106725	1015	__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
Kojto	122:f9eeca106725	1016	uint32_t DstAddress, uint32_t Direction)
Kojto	122:f9eeca106725	1017	{
Kojto	122:f9eeca106725	1018	/* Direction Memory to Periph */
Kojto	122:f9eeca106725	1019	if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
Kojto	122:f9eeca106725	1020	{
Kojto	122:f9eeca106725	1021	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
Kojto	122:f9eeca106725	1022	SrcAddress);
Kojto	122:f9eeca106725	1023	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
Kojto	122:f9eeca106725	1024	DstAddress);
Kojto	122:f9eeca106725	1025	}
Kojto	122:f9eeca106725	1026	/* Direction Periph to Memory and Memory to Memory */
Kojto	122:f9eeca106725	1027	else
Kojto	122:f9eeca106725	1028	{
Kojto	122:f9eeca106725	1029	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
Kojto	122:f9eeca106725	1030	SrcAddress);
Kojto	122:f9eeca106725	1031	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
Kojto	122:f9eeca106725	1032	DstAddress);
Kojto	122:f9eeca106725	1033	}
Kojto	122:f9eeca106725	1034	}
Kojto	122:f9eeca106725	1035
Kojto	122:f9eeca106725	1036	/**
Kojto	122:f9eeca106725	1037	* @brief Set the Memory address.
Kojto	122:f9eeca106725	1038	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Kojto	122:f9eeca106725	1039	* @rmtoll CMAR MA LL_DMA_SetMemoryAddress
Kojto	122:f9eeca106725	1040	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1041	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	1042	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	1043	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	1044	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	1045	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	1046	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	1047	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	1048	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	1049	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Kojto	122:f9eeca106725	1050	* @retval None
Kojto	122:f9eeca106725	1051	*/
Kojto	122:f9eeca106725	1052	__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Kojto	122:f9eeca106725	1053	{
Kojto	122:f9eeca106725	1054	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
Kojto	122:f9eeca106725	1055	MemoryAddress);
Kojto	122:f9eeca106725	1056	}
Kojto	122:f9eeca106725	1057
Kojto	122:f9eeca106725	1058	/**
Kojto	122:f9eeca106725	1059	* @brief Set the Peripheral address.
Kojto	122:f9eeca106725	1060	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Kojto	122:f9eeca106725	1061	* @rmtoll CPAR PA LL_DMA_SetPeriphAddress
Kojto	122:f9eeca106725	1062	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1063	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	1064	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	1065	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	1066	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	1067	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	1068	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	1069	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	1070	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	1071	* @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Kojto	122:f9eeca106725	1072	* @retval None
Kojto	122:f9eeca106725	1073	*/
Kojto	122:f9eeca106725	1074	__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
Kojto	122:f9eeca106725	1075	{
Kojto	122:f9eeca106725	1076	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
Kojto	122:f9eeca106725	1077	PeriphAddress);
Kojto	122:f9eeca106725	1078	}
Kojto	122:f9eeca106725	1079
Kojto	122:f9eeca106725	1080	/**
Kojto	122:f9eeca106725	1081	* @brief Get Memory address.
Kojto	122:f9eeca106725	1082	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Kojto	122:f9eeca106725	1083	* @rmtoll CMAR MA LL_DMA_GetMemoryAddress
Kojto	122:f9eeca106725	1084	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1085	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	1086	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	1087	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	1088	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	1089	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	1090	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	1091	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	1092	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	1093	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Kojto	122:f9eeca106725	1094	*/
Kojto	122:f9eeca106725	1095	__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	1096	{
Kojto	122:f9eeca106725	1097	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
Kojto	122:f9eeca106725	1098	DMA_CMAR_MA));
Kojto	122:f9eeca106725	1099	}
Kojto	122:f9eeca106725	1100
Kojto	122:f9eeca106725	1101	/**
Kojto	122:f9eeca106725	1102	* @brief Get Peripheral address.
Kojto	122:f9eeca106725	1103	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Kojto	122:f9eeca106725	1104	* @rmtoll CPAR PA LL_DMA_GetPeriphAddress
Kojto	122:f9eeca106725	1105	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1106	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	1107	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	1108	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	1109	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	1110	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	1111	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	1112	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	1113	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	1114	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Kojto	122:f9eeca106725	1115	*/
Kojto	122:f9eeca106725	1116	__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	1117	{
Kojto	122:f9eeca106725	1118	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
Kojto	122:f9eeca106725	1119	DMA_CPAR_PA));
Kojto	122:f9eeca106725	1120	}
Kojto	122:f9eeca106725	1121
Kojto	122:f9eeca106725	1122	/**
Kojto	122:f9eeca106725	1123	* @brief Set the Memory to Memory Source address.
Kojto	122:f9eeca106725	1124	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Kojto	122:f9eeca106725	1125	* @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
Kojto	122:f9eeca106725	1126	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1127	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	1128	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	1129	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	1130	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	1131	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	1132	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	1133	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	1134	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	1135	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Kojto	122:f9eeca106725	1136	* @retval None
Kojto	122:f9eeca106725	1137	*/
Kojto	122:f9eeca106725	1138	__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Kojto	122:f9eeca106725	1139	{
Kojto	122:f9eeca106725	1140	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
Kojto	122:f9eeca106725	1141	MemoryAddress);
Kojto	122:f9eeca106725	1142	}
Kojto	122:f9eeca106725	1143
Kojto	122:f9eeca106725	1144	/**
Kojto	122:f9eeca106725	1145	* @brief Set the Memory to Memory Destination address.
Kojto	122:f9eeca106725	1146	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Kojto	122:f9eeca106725	1147	* @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
Kojto	122:f9eeca106725	1148	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1149	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	1150	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	1151	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	1152	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	1153	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	1154	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	1155	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	1156	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	1157	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Kojto	122:f9eeca106725	1158	* @retval None
Kojto	122:f9eeca106725	1159	*/
Kojto	122:f9eeca106725	1160	__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Kojto	122:f9eeca106725	1161	{
Kojto	122:f9eeca106725	1162	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
Kojto	122:f9eeca106725	1163	MemoryAddress);
Kojto	122:f9eeca106725	1164	}
Kojto	122:f9eeca106725	1165
Kojto	122:f9eeca106725	1166	/**
Kojto	122:f9eeca106725	1167	* @brief Get the Memory to Memory Source address.
Kojto	122:f9eeca106725	1168	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Kojto	122:f9eeca106725	1169	* @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
Kojto	122:f9eeca106725	1170	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1171	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	1172	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	1173	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	1174	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	1175	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	1176	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	1177	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	1178	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	1179	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Kojto	122:f9eeca106725	1180	*/
Kojto	122:f9eeca106725	1181	__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	1182	{
Kojto	122:f9eeca106725	1183	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
Kojto	122:f9eeca106725	1184	DMA_CPAR_PA));
Kojto	122:f9eeca106725	1185	}
Kojto	122:f9eeca106725	1186
Kojto	122:f9eeca106725	1187	/**
Kojto	122:f9eeca106725	1188	* @brief Get the Memory to Memory Destination address.
Kojto	122:f9eeca106725	1189	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Kojto	122:f9eeca106725	1190	* @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
Kojto	122:f9eeca106725	1191	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1192	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	1193	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	1194	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	1195	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	1196	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	1197	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	1198	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	1199	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	1200	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Kojto	122:f9eeca106725	1201	*/
Kojto	122:f9eeca106725	1202	__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	1203	{
Kojto	122:f9eeca106725	1204	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
Kojto	122:f9eeca106725	1205	DMA_CMAR_MA));
Kojto	122:f9eeca106725	1206	}
Kojto	122:f9eeca106725	1207
Kojto	122:f9eeca106725	1208	/**
Kojto	122:f9eeca106725	1209	* @brief Set DMA request for DMA instance on Channel x.
Kojto	122:f9eeca106725	1210	* @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
Kojto	122:f9eeca106725	1211	* @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
Kojto	122:f9eeca106725	1212	* CSELR C2S LL_DMA_SetPeriphRequest\n
Kojto	122:f9eeca106725	1213	* CSELR C3S LL_DMA_SetPeriphRequest\n
Kojto	122:f9eeca106725	1214	* CSELR C4S LL_DMA_SetPeriphRequest\n
Kojto	122:f9eeca106725	1215	* CSELR C5S LL_DMA_SetPeriphRequest\n
Kojto	122:f9eeca106725	1216	* CSELR C6S LL_DMA_SetPeriphRequest\n
Kojto	122:f9eeca106725	1217	* CSELR C7S LL_DMA_SetPeriphRequest
Kojto	122:f9eeca106725	1218	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1219	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	1220	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	1221	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	1222	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	1223	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	1224	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	1225	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	1226	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	1227	* @param PeriphRequest This parameter can be one of the following values:
Kojto	122:f9eeca106725	1228	* @arg @ref LL_DMA_REQUEST_0
Kojto	122:f9eeca106725	1229	* @arg @ref LL_DMA_REQUEST_1
Kojto	122:f9eeca106725	1230	* @arg @ref LL_DMA_REQUEST_2
Kojto	122:f9eeca106725	1231	* @arg @ref LL_DMA_REQUEST_3
Kojto	122:f9eeca106725	1232	* @arg @ref LL_DMA_REQUEST_4
Kojto	122:f9eeca106725	1233	* @arg @ref LL_DMA_REQUEST_5
Kojto	122:f9eeca106725	1234	* @arg @ref LL_DMA_REQUEST_6
Kojto	122:f9eeca106725	1235	* @arg @ref LL_DMA_REQUEST_7
Kojto	122:f9eeca106725	1236	* @retval None
Kojto	122:f9eeca106725	1237	*/
Kojto	122:f9eeca106725	1238	__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
Kojto	122:f9eeca106725	1239	{
Kojto	122:f9eeca106725	1240	MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
Kojto	122:f9eeca106725	1241	DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);
Kojto	122:f9eeca106725	1242	}
Kojto	122:f9eeca106725	1243
Kojto	122:f9eeca106725	1244	/**
Kojto	122:f9eeca106725	1245	* @brief Get DMA request for DMA instance on Channel x.
Kojto	122:f9eeca106725	1246	* @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
Kojto	122:f9eeca106725	1247	* CSELR C2S LL_DMA_GetPeriphRequest\n
Kojto	122:f9eeca106725	1248	* CSELR C3S LL_DMA_GetPeriphRequest\n
Kojto	122:f9eeca106725	1249	* CSELR C4S LL_DMA_GetPeriphRequest\n
Kojto	122:f9eeca106725	1250	* CSELR C5S LL_DMA_GetPeriphRequest\n
Kojto	122:f9eeca106725	1251	* CSELR C6S LL_DMA_GetPeriphRequest\n
Kojto	122:f9eeca106725	1252	* CSELR C7S LL_DMA_GetPeriphRequest
Kojto	122:f9eeca106725	1253	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1254	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	1255	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	1256	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	1257	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	1258	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	1259	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	1260	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	1261	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	1262	* @retval Returned value can be one of the following values:
Kojto	122:f9eeca106725	1263	* @arg @ref LL_DMA_REQUEST_0
Kojto	122:f9eeca106725	1264	* @arg @ref LL_DMA_REQUEST_1
Kojto	122:f9eeca106725	1265	* @arg @ref LL_DMA_REQUEST_2
Kojto	122:f9eeca106725	1266	* @arg @ref LL_DMA_REQUEST_3
Kojto	122:f9eeca106725	1267	* @arg @ref LL_DMA_REQUEST_4
Kojto	122:f9eeca106725	1268	* @arg @ref LL_DMA_REQUEST_5
Kojto	122:f9eeca106725	1269	* @arg @ref LL_DMA_REQUEST_6
Kojto	122:f9eeca106725	1270	* @arg @ref LL_DMA_REQUEST_7
Kojto	122:f9eeca106725	1271	*/
Kojto	122:f9eeca106725	1272	__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	1273	{
Kojto	122:f9eeca106725	1274	return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
Kojto	122:f9eeca106725	1275	DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS);
Kojto	122:f9eeca106725	1276	}
Kojto	122:f9eeca106725	1277
Kojto	122:f9eeca106725	1278	/**
Kojto	122:f9eeca106725	1279	* @}
Kojto	122:f9eeca106725	1280	*/
Kojto	122:f9eeca106725	1281
Kojto	122:f9eeca106725	1282	/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
Kojto	122:f9eeca106725	1283	* @{
Kojto	122:f9eeca106725	1284	*/
Kojto	122:f9eeca106725	1285
Kojto	122:f9eeca106725	1286	/**
Kojto	122:f9eeca106725	1287	* @brief Get Channel 1 global interrupt flag.
Kojto	122:f9eeca106725	1288	* @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
Kojto	122:f9eeca106725	1289	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1290	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1291	*/
Kojto	122:f9eeca106725	1292	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1293	{
Kojto	122:f9eeca106725	1294	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
Kojto	122:f9eeca106725	1295	}
Kojto	122:f9eeca106725	1296
Kojto	122:f9eeca106725	1297	/**
Kojto	122:f9eeca106725	1298	* @brief Get Channel 2 global interrupt flag.
Kojto	122:f9eeca106725	1299	* @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
Kojto	122:f9eeca106725	1300	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1301	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1302	*/
Kojto	122:f9eeca106725	1303	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1304	{
Kojto	122:f9eeca106725	1305	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
Kojto	122:f9eeca106725	1306	}
Kojto	122:f9eeca106725	1307
Kojto	122:f9eeca106725	1308	/**
Kojto	122:f9eeca106725	1309	* @brief Get Channel 3 global interrupt flag.
Kojto	122:f9eeca106725	1310	* @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
Kojto	122:f9eeca106725	1311	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1312	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1313	*/
Kojto	122:f9eeca106725	1314	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1315	{
Kojto	122:f9eeca106725	1316	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
Kojto	122:f9eeca106725	1317	}
Kojto	122:f9eeca106725	1318
Kojto	122:f9eeca106725	1319	/**
Kojto	122:f9eeca106725	1320	* @brief Get Channel 4 global interrupt flag.
Kojto	122:f9eeca106725	1321	* @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
Kojto	122:f9eeca106725	1322	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1323	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1324	*/
Kojto	122:f9eeca106725	1325	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1326	{
Kojto	122:f9eeca106725	1327	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
Kojto	122:f9eeca106725	1328	}
Kojto	122:f9eeca106725	1329
Kojto	122:f9eeca106725	1330	/**
Kojto	122:f9eeca106725	1331	* @brief Get Channel 5 global interrupt flag.
Kojto	122:f9eeca106725	1332	* @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
Kojto	122:f9eeca106725	1333	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1334	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1335	*/
Kojto	122:f9eeca106725	1336	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1337	{
Kojto	122:f9eeca106725	1338	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
Kojto	122:f9eeca106725	1339	}
Kojto	122:f9eeca106725	1340
Kojto	122:f9eeca106725	1341	/**
Kojto	122:f9eeca106725	1342	* @brief Get Channel 6 global interrupt flag.
Kojto	122:f9eeca106725	1343	* @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
Kojto	122:f9eeca106725	1344	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1345	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1346	*/
Kojto	122:f9eeca106725	1347	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1348	{
Kojto	122:f9eeca106725	1349	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
Kojto	122:f9eeca106725	1350	}
Kojto	122:f9eeca106725	1351
Kojto	122:f9eeca106725	1352	/**
Kojto	122:f9eeca106725	1353	* @brief Get Channel 7 global interrupt flag.
Kojto	122:f9eeca106725	1354	* @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
Kojto	122:f9eeca106725	1355	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1356	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1357	*/
Kojto	122:f9eeca106725	1358	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1359	{
Kojto	122:f9eeca106725	1360	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
Kojto	122:f9eeca106725	1361	}
Kojto	122:f9eeca106725	1362
Kojto	122:f9eeca106725	1363	/**
Kojto	122:f9eeca106725	1364	* @brief Get Channel 1 transfer complete flag.
Kojto	122:f9eeca106725	1365	* @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
Kojto	122:f9eeca106725	1366	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1367	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1368	*/
Kojto	122:f9eeca106725	1369	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1370	{
Kojto	122:f9eeca106725	1371	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
Kojto	122:f9eeca106725	1372	}
Kojto	122:f9eeca106725	1373
Kojto	122:f9eeca106725	1374	/**
Kojto	122:f9eeca106725	1375	* @brief Get Channel 2 transfer complete flag.
Kojto	122:f9eeca106725	1376	* @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
Kojto	122:f9eeca106725	1377	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1378	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1379	*/
Kojto	122:f9eeca106725	1380	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1381	{
Kojto	122:f9eeca106725	1382	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
Kojto	122:f9eeca106725	1383	}
Kojto	122:f9eeca106725	1384
Kojto	122:f9eeca106725	1385	/**
Kojto	122:f9eeca106725	1386	* @brief Get Channel 3 transfer complete flag.
Kojto	122:f9eeca106725	1387	* @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
Kojto	122:f9eeca106725	1388	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1389	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1390	*/
Kojto	122:f9eeca106725	1391	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1392	{
Kojto	122:f9eeca106725	1393	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
Kojto	122:f9eeca106725	1394	}
Kojto	122:f9eeca106725	1395
Kojto	122:f9eeca106725	1396	/**
Kojto	122:f9eeca106725	1397	* @brief Get Channel 4 transfer complete flag.
Kojto	122:f9eeca106725	1398	* @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
Kojto	122:f9eeca106725	1399	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1400	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1401	*/
Kojto	122:f9eeca106725	1402	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1403	{
Kojto	122:f9eeca106725	1404	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
Kojto	122:f9eeca106725	1405	}
Kojto	122:f9eeca106725	1406
Kojto	122:f9eeca106725	1407	/**
Kojto	122:f9eeca106725	1408	* @brief Get Channel 5 transfer complete flag.
Kojto	122:f9eeca106725	1409	* @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
Kojto	122:f9eeca106725	1410	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1411	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1412	*/
Kojto	122:f9eeca106725	1413	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1414	{
Kojto	122:f9eeca106725	1415	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
Kojto	122:f9eeca106725	1416	}
Kojto	122:f9eeca106725	1417
Kojto	122:f9eeca106725	1418	/**
Kojto	122:f9eeca106725	1419	* @brief Get Channel 6 transfer complete flag.
Kojto	122:f9eeca106725	1420	* @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
Kojto	122:f9eeca106725	1421	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1422	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1423	*/
Kojto	122:f9eeca106725	1424	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1425	{
Kojto	122:f9eeca106725	1426	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
Kojto	122:f9eeca106725	1427	}
Kojto	122:f9eeca106725	1428
Kojto	122:f9eeca106725	1429	/**
Kojto	122:f9eeca106725	1430	* @brief Get Channel 7 transfer complete flag.
Kojto	122:f9eeca106725	1431	* @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
Kojto	122:f9eeca106725	1432	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1433	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1434	*/
Kojto	122:f9eeca106725	1435	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1436	{
Kojto	122:f9eeca106725	1437	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
Kojto	122:f9eeca106725	1438	}
Kojto	122:f9eeca106725	1439
Kojto	122:f9eeca106725	1440	/**
Kojto	122:f9eeca106725	1441	* @brief Get Channel 1 half transfer flag.
Kojto	122:f9eeca106725	1442	* @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
Kojto	122:f9eeca106725	1443	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1444	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1445	*/
Kojto	122:f9eeca106725	1446	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1447	{
Kojto	122:f9eeca106725	1448	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
Kojto	122:f9eeca106725	1449	}
Kojto	122:f9eeca106725	1450
Kojto	122:f9eeca106725	1451	/**
Kojto	122:f9eeca106725	1452	* @brief Get Channel 2 half transfer flag.
Kojto	122:f9eeca106725	1453	* @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
Kojto	122:f9eeca106725	1454	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1455	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1456	*/
Kojto	122:f9eeca106725	1457	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1458	{
Kojto	122:f9eeca106725	1459	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
Kojto	122:f9eeca106725	1460	}
Kojto	122:f9eeca106725	1461
Kojto	122:f9eeca106725	1462	/**
Kojto	122:f9eeca106725	1463	* @brief Get Channel 3 half transfer flag.
Kojto	122:f9eeca106725	1464	* @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
Kojto	122:f9eeca106725	1465	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1466	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1467	*/
Kojto	122:f9eeca106725	1468	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1469	{
Kojto	122:f9eeca106725	1470	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
Kojto	122:f9eeca106725	1471	}
Kojto	122:f9eeca106725	1472
Kojto	122:f9eeca106725	1473	/**
Kojto	122:f9eeca106725	1474	* @brief Get Channel 4 half transfer flag.
Kojto	122:f9eeca106725	1475	* @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
Kojto	122:f9eeca106725	1476	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1477	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1478	*/
Kojto	122:f9eeca106725	1479	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1480	{
Kojto	122:f9eeca106725	1481	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
Kojto	122:f9eeca106725	1482	}
Kojto	122:f9eeca106725	1483
Kojto	122:f9eeca106725	1484	/**
Kojto	122:f9eeca106725	1485	* @brief Get Channel 5 half transfer flag.
Kojto	122:f9eeca106725	1486	* @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
Kojto	122:f9eeca106725	1487	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1488	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1489	*/
Kojto	122:f9eeca106725	1490	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1491	{
Kojto	122:f9eeca106725	1492	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
Kojto	122:f9eeca106725	1493	}
Kojto	122:f9eeca106725	1494
Kojto	122:f9eeca106725	1495	/**
Kojto	122:f9eeca106725	1496	* @brief Get Channel 6 half transfer flag.
Kojto	122:f9eeca106725	1497	* @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
Kojto	122:f9eeca106725	1498	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1499	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1500	*/
Kojto	122:f9eeca106725	1501	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1502	{
Kojto	122:f9eeca106725	1503	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
Kojto	122:f9eeca106725	1504	}
Kojto	122:f9eeca106725	1505
Kojto	122:f9eeca106725	1506	/**
Kojto	122:f9eeca106725	1507	* @brief Get Channel 7 half transfer flag.
Kojto	122:f9eeca106725	1508	* @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
Kojto	122:f9eeca106725	1509	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1510	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1511	*/
Kojto	122:f9eeca106725	1512	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1513	{
Kojto	122:f9eeca106725	1514	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
Kojto	122:f9eeca106725	1515	}
Kojto	122:f9eeca106725	1516
Kojto	122:f9eeca106725	1517	/**
Kojto	122:f9eeca106725	1518	* @brief Get Channel 1 transfer error flag.
Kojto	122:f9eeca106725	1519	* @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
Kojto	122:f9eeca106725	1520	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1521	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1522	*/
Kojto	122:f9eeca106725	1523	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1524	{
Kojto	122:f9eeca106725	1525	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
Kojto	122:f9eeca106725	1526	}
Kojto	122:f9eeca106725	1527
Kojto	122:f9eeca106725	1528	/**
Kojto	122:f9eeca106725	1529	* @brief Get Channel 2 transfer error flag.
Kojto	122:f9eeca106725	1530	* @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
Kojto	122:f9eeca106725	1531	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1532	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1533	*/
Kojto	122:f9eeca106725	1534	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1535	{
Kojto	122:f9eeca106725	1536	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
Kojto	122:f9eeca106725	1537	}
Kojto	122:f9eeca106725	1538
Kojto	122:f9eeca106725	1539	/**
Kojto	122:f9eeca106725	1540	* @brief Get Channel 3 transfer error flag.
Kojto	122:f9eeca106725	1541	* @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
Kojto	122:f9eeca106725	1542	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1543	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1544	*/
Kojto	122:f9eeca106725	1545	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1546	{
Kojto	122:f9eeca106725	1547	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
Kojto	122:f9eeca106725	1548	}
Kojto	122:f9eeca106725	1549
Kojto	122:f9eeca106725	1550	/**
Kojto	122:f9eeca106725	1551	* @brief Get Channel 4 transfer error flag.
Kojto	122:f9eeca106725	1552	* @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
Kojto	122:f9eeca106725	1553	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1554	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1555	*/
Kojto	122:f9eeca106725	1556	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1557	{
Kojto	122:f9eeca106725	1558	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
Kojto	122:f9eeca106725	1559	}
Kojto	122:f9eeca106725	1560
Kojto	122:f9eeca106725	1561	/**
Kojto	122:f9eeca106725	1562	* @brief Get Channel 5 transfer error flag.
Kojto	122:f9eeca106725	1563	* @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
Kojto	122:f9eeca106725	1564	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1565	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1566	*/
Kojto	122:f9eeca106725	1567	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1568	{
Kojto	122:f9eeca106725	1569	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
Kojto	122:f9eeca106725	1570	}
Kojto	122:f9eeca106725	1571
Kojto	122:f9eeca106725	1572	/**
Kojto	122:f9eeca106725	1573	* @brief Get Channel 6 transfer error flag.
Kojto	122:f9eeca106725	1574	* @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
Kojto	122:f9eeca106725	1575	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1576	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1577	*/
Kojto	122:f9eeca106725	1578	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1579	{
Kojto	122:f9eeca106725	1580	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
Kojto	122:f9eeca106725	1581	}
Kojto	122:f9eeca106725	1582
Kojto	122:f9eeca106725	1583	/**
Kojto	122:f9eeca106725	1584	* @brief Get Channel 7 transfer error flag.
Kojto	122:f9eeca106725	1585	* @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
Kojto	122:f9eeca106725	1586	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1587	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	1588	*/
Kojto	122:f9eeca106725	1589	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1590	{
Kojto	122:f9eeca106725	1591	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
Kojto	122:f9eeca106725	1592	}
Kojto	122:f9eeca106725	1593
Kojto	122:f9eeca106725	1594	/**
Kojto	122:f9eeca106725	1595	* @brief Clear Channel 1 global interrupt flag.
Kojto	122:f9eeca106725	1596	* @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
Kojto	122:f9eeca106725	1597	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1598	* @retval None
Kojto	122:f9eeca106725	1599	*/
Kojto	122:f9eeca106725	1600	__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1601	{
Kojto	122:f9eeca106725	1602	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1);
Kojto	122:f9eeca106725	1603	}
Kojto	122:f9eeca106725	1604
Kojto	122:f9eeca106725	1605	/**
Kojto	122:f9eeca106725	1606	* @brief Clear Channel 2 global interrupt flag.
Kojto	122:f9eeca106725	1607	* @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
Kojto	122:f9eeca106725	1608	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1609	* @retval None
Kojto	122:f9eeca106725	1610	*/
Kojto	122:f9eeca106725	1611	__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1612	{
Kojto	122:f9eeca106725	1613	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2);
Kojto	122:f9eeca106725	1614	}
Kojto	122:f9eeca106725	1615
Kojto	122:f9eeca106725	1616	/**
Kojto	122:f9eeca106725	1617	* @brief Clear Channel 3 global interrupt flag.
Kojto	122:f9eeca106725	1618	* @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
Kojto	122:f9eeca106725	1619	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1620	* @retval None
Kojto	122:f9eeca106725	1621	*/
Kojto	122:f9eeca106725	1622	__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1623	{
Kojto	122:f9eeca106725	1624	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3);
Kojto	122:f9eeca106725	1625	}
Kojto	122:f9eeca106725	1626
Kojto	122:f9eeca106725	1627	/**
Kojto	122:f9eeca106725	1628	* @brief Clear Channel 4 global interrupt flag.
Kojto	122:f9eeca106725	1629	* @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
Kojto	122:f9eeca106725	1630	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1631	* @retval None
Kojto	122:f9eeca106725	1632	*/
Kojto	122:f9eeca106725	1633	__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1634	{
Kojto	122:f9eeca106725	1635	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4);
Kojto	122:f9eeca106725	1636	}
Kojto	122:f9eeca106725	1637
Kojto	122:f9eeca106725	1638	/**
Kojto	122:f9eeca106725	1639	* @brief Clear Channel 5 global interrupt flag.
Kojto	122:f9eeca106725	1640	* @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
Kojto	122:f9eeca106725	1641	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1642	* @retval None
Kojto	122:f9eeca106725	1643	*/
Kojto	122:f9eeca106725	1644	__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1645	{
Kojto	122:f9eeca106725	1646	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5);
Kojto	122:f9eeca106725	1647	}
Kojto	122:f9eeca106725	1648
Kojto	122:f9eeca106725	1649	/**
Kojto	122:f9eeca106725	1650	* @brief Clear Channel 6 global interrupt flag.
Kojto	122:f9eeca106725	1651	* @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
Kojto	122:f9eeca106725	1652	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1653	* @retval None
Kojto	122:f9eeca106725	1654	*/
Kojto	122:f9eeca106725	1655	__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1656	{
Kojto	122:f9eeca106725	1657	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6);
Kojto	122:f9eeca106725	1658	}
Kojto	122:f9eeca106725	1659
Kojto	122:f9eeca106725	1660	/**
Kojto	122:f9eeca106725	1661	* @brief Clear Channel 7 global interrupt flag.
Kojto	122:f9eeca106725	1662	* @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
Kojto	122:f9eeca106725	1663	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1664	* @retval None
Kojto	122:f9eeca106725	1665	*/
Kojto	122:f9eeca106725	1666	__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1667	{
Kojto	122:f9eeca106725	1668	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7);
Kojto	122:f9eeca106725	1669	}
Kojto	122:f9eeca106725	1670
Kojto	122:f9eeca106725	1671	/**
Kojto	122:f9eeca106725	1672	* @brief Clear Channel 1 transfer complete flag.
Kojto	122:f9eeca106725	1673	* @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
Kojto	122:f9eeca106725	1674	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1675	* @retval None
Kojto	122:f9eeca106725	1676	*/
Kojto	122:f9eeca106725	1677	__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1678	{
Kojto	122:f9eeca106725	1679	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1);
Kojto	122:f9eeca106725	1680	}
Kojto	122:f9eeca106725	1681
Kojto	122:f9eeca106725	1682	/**
Kojto	122:f9eeca106725	1683	* @brief Clear Channel 2 transfer complete flag.
Kojto	122:f9eeca106725	1684	* @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
Kojto	122:f9eeca106725	1685	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1686	* @retval None
Kojto	122:f9eeca106725	1687	*/
Kojto	122:f9eeca106725	1688	__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1689	{
Kojto	122:f9eeca106725	1690	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2);
Kojto	122:f9eeca106725	1691	}
Kojto	122:f9eeca106725	1692
Kojto	122:f9eeca106725	1693	/**
Kojto	122:f9eeca106725	1694	* @brief Clear Channel 3 transfer complete flag.
Kojto	122:f9eeca106725	1695	* @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
Kojto	122:f9eeca106725	1696	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1697	* @retval None
Kojto	122:f9eeca106725	1698	*/
Kojto	122:f9eeca106725	1699	__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1700	{
Kojto	122:f9eeca106725	1701	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3);
Kojto	122:f9eeca106725	1702	}
Kojto	122:f9eeca106725	1703
Kojto	122:f9eeca106725	1704	/**
Kojto	122:f9eeca106725	1705	* @brief Clear Channel 4 transfer complete flag.
Kojto	122:f9eeca106725	1706	* @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
Kojto	122:f9eeca106725	1707	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1708	* @retval None
Kojto	122:f9eeca106725	1709	*/
Kojto	122:f9eeca106725	1710	__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1711	{
Kojto	122:f9eeca106725	1712	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4);
Kojto	122:f9eeca106725	1713	}
Kojto	122:f9eeca106725	1714
Kojto	122:f9eeca106725	1715	/**
Kojto	122:f9eeca106725	1716	* @brief Clear Channel 5 transfer complete flag.
Kojto	122:f9eeca106725	1717	* @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
Kojto	122:f9eeca106725	1718	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1719	* @retval None
Kojto	122:f9eeca106725	1720	*/
Kojto	122:f9eeca106725	1721	__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1722	{
Kojto	122:f9eeca106725	1723	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5);
Kojto	122:f9eeca106725	1724	}
Kojto	122:f9eeca106725	1725
Kojto	122:f9eeca106725	1726	/**
Kojto	122:f9eeca106725	1727	* @brief Clear Channel 6 transfer complete flag.
Kojto	122:f9eeca106725	1728	* @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
Kojto	122:f9eeca106725	1729	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1730	* @retval None
Kojto	122:f9eeca106725	1731	*/
Kojto	122:f9eeca106725	1732	__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1733	{
Kojto	122:f9eeca106725	1734	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6);
Kojto	122:f9eeca106725	1735	}
Kojto	122:f9eeca106725	1736
Kojto	122:f9eeca106725	1737	/**
Kojto	122:f9eeca106725	1738	* @brief Clear Channel 7 transfer complete flag.
Kojto	122:f9eeca106725	1739	* @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
Kojto	122:f9eeca106725	1740	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1741	* @retval None
Kojto	122:f9eeca106725	1742	*/
Kojto	122:f9eeca106725	1743	__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1744	{
Kojto	122:f9eeca106725	1745	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7);
Kojto	122:f9eeca106725	1746	}
Kojto	122:f9eeca106725	1747
Kojto	122:f9eeca106725	1748	/**
Kojto	122:f9eeca106725	1749	* @brief Clear Channel 1 half transfer flag.
Kojto	122:f9eeca106725	1750	* @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
Kojto	122:f9eeca106725	1751	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1752	* @retval None
Kojto	122:f9eeca106725	1753	*/
Kojto	122:f9eeca106725	1754	__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1755	{
Kojto	122:f9eeca106725	1756	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1);
Kojto	122:f9eeca106725	1757	}
Kojto	122:f9eeca106725	1758
Kojto	122:f9eeca106725	1759	/**
Kojto	122:f9eeca106725	1760	* @brief Clear Channel 2 half transfer flag.
Kojto	122:f9eeca106725	1761	* @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
Kojto	122:f9eeca106725	1762	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1763	* @retval None
Kojto	122:f9eeca106725	1764	*/
Kojto	122:f9eeca106725	1765	__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1766	{
Kojto	122:f9eeca106725	1767	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2);
Kojto	122:f9eeca106725	1768	}
Kojto	122:f9eeca106725	1769
Kojto	122:f9eeca106725	1770	/**
Kojto	122:f9eeca106725	1771	* @brief Clear Channel 3 half transfer flag.
Kojto	122:f9eeca106725	1772	* @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
Kojto	122:f9eeca106725	1773	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1774	* @retval None
Kojto	122:f9eeca106725	1775	*/
Kojto	122:f9eeca106725	1776	__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1777	{
Kojto	122:f9eeca106725	1778	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3);
Kojto	122:f9eeca106725	1779	}
Kojto	122:f9eeca106725	1780
Kojto	122:f9eeca106725	1781	/**
Kojto	122:f9eeca106725	1782	* @brief Clear Channel 4 half transfer flag.
Kojto	122:f9eeca106725	1783	* @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
Kojto	122:f9eeca106725	1784	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1785	* @retval None
Kojto	122:f9eeca106725	1786	*/
Kojto	122:f9eeca106725	1787	__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1788	{
Kojto	122:f9eeca106725	1789	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4);
Kojto	122:f9eeca106725	1790	}
Kojto	122:f9eeca106725	1791
Kojto	122:f9eeca106725	1792	/**
Kojto	122:f9eeca106725	1793	* @brief Clear Channel 5 half transfer flag.
Kojto	122:f9eeca106725	1794	* @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
Kojto	122:f9eeca106725	1795	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1796	* @retval None
Kojto	122:f9eeca106725	1797	*/
Kojto	122:f9eeca106725	1798	__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1799	{
Kojto	122:f9eeca106725	1800	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5);
Kojto	122:f9eeca106725	1801	}
Kojto	122:f9eeca106725	1802
Kojto	122:f9eeca106725	1803	/**
Kojto	122:f9eeca106725	1804	* @brief Clear Channel 6 half transfer flag.
Kojto	122:f9eeca106725	1805	* @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
Kojto	122:f9eeca106725	1806	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1807	* @retval None
Kojto	122:f9eeca106725	1808	*/
Kojto	122:f9eeca106725	1809	__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1810	{
Kojto	122:f9eeca106725	1811	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6);
Kojto	122:f9eeca106725	1812	}
Kojto	122:f9eeca106725	1813
Kojto	122:f9eeca106725	1814	/**
Kojto	122:f9eeca106725	1815	* @brief Clear Channel 7 half transfer flag.
Kojto	122:f9eeca106725	1816	* @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
Kojto	122:f9eeca106725	1817	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1818	* @retval None
Kojto	122:f9eeca106725	1819	*/
Kojto	122:f9eeca106725	1820	__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1821	{
Kojto	122:f9eeca106725	1822	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7);
Kojto	122:f9eeca106725	1823	}
Kojto	122:f9eeca106725	1824
Kojto	122:f9eeca106725	1825	/**
Kojto	122:f9eeca106725	1826	* @brief Clear Channel 1 transfer error flag.
Kojto	122:f9eeca106725	1827	* @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
Kojto	122:f9eeca106725	1828	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1829	* @retval None
Kojto	122:f9eeca106725	1830	*/
Kojto	122:f9eeca106725	1831	__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1832	{
Kojto	122:f9eeca106725	1833	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1);
Kojto	122:f9eeca106725	1834	}
Kojto	122:f9eeca106725	1835
Kojto	122:f9eeca106725	1836	/**
Kojto	122:f9eeca106725	1837	* @brief Clear Channel 2 transfer error flag.
Kojto	122:f9eeca106725	1838	* @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
Kojto	122:f9eeca106725	1839	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1840	* @retval None
Kojto	122:f9eeca106725	1841	*/
Kojto	122:f9eeca106725	1842	__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1843	{
Kojto	122:f9eeca106725	1844	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2);
Kojto	122:f9eeca106725	1845	}
Kojto	122:f9eeca106725	1846
Kojto	122:f9eeca106725	1847	/**
Kojto	122:f9eeca106725	1848	* @brief Clear Channel 3 transfer error flag.
Kojto	122:f9eeca106725	1849	* @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
Kojto	122:f9eeca106725	1850	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1851	* @retval None
Kojto	122:f9eeca106725	1852	*/
Kojto	122:f9eeca106725	1853	__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1854	{
Kojto	122:f9eeca106725	1855	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3);
Kojto	122:f9eeca106725	1856	}
Kojto	122:f9eeca106725	1857
Kojto	122:f9eeca106725	1858	/**
Kojto	122:f9eeca106725	1859	* @brief Clear Channel 4 transfer error flag.
Kojto	122:f9eeca106725	1860	* @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
Kojto	122:f9eeca106725	1861	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1862	* @retval None
Kojto	122:f9eeca106725	1863	*/
Kojto	122:f9eeca106725	1864	__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1865	{
Kojto	122:f9eeca106725	1866	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4);
Kojto	122:f9eeca106725	1867	}
Kojto	122:f9eeca106725	1868
Kojto	122:f9eeca106725	1869	/**
Kojto	122:f9eeca106725	1870	* @brief Clear Channel 5 transfer error flag.
Kojto	122:f9eeca106725	1871	* @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
Kojto	122:f9eeca106725	1872	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1873	* @retval None
Kojto	122:f9eeca106725	1874	*/
Kojto	122:f9eeca106725	1875	__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1876	{
Kojto	122:f9eeca106725	1877	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5);
Kojto	122:f9eeca106725	1878	}
Kojto	122:f9eeca106725	1879
Kojto	122:f9eeca106725	1880	/**
Kojto	122:f9eeca106725	1881	* @brief Clear Channel 6 transfer error flag.
Kojto	122:f9eeca106725	1882	* @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
Kojto	122:f9eeca106725	1883	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1884	* @retval None
Kojto	122:f9eeca106725	1885	*/
Kojto	122:f9eeca106725	1886	__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1887	{
Kojto	122:f9eeca106725	1888	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6);
Kojto	122:f9eeca106725	1889	}
Kojto	122:f9eeca106725	1890
Kojto	122:f9eeca106725	1891	/**
Kojto	122:f9eeca106725	1892	* @brief Clear Channel 7 transfer error flag.
Kojto	122:f9eeca106725	1893	* @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
Kojto	122:f9eeca106725	1894	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1895	* @retval None
Kojto	122:f9eeca106725	1896	*/
Kojto	122:f9eeca106725	1897	__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
Kojto	122:f9eeca106725	1898	{
Kojto	122:f9eeca106725	1899	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7);
Kojto	122:f9eeca106725	1900	}
Kojto	122:f9eeca106725	1901
Kojto	122:f9eeca106725	1902	/**
Kojto	122:f9eeca106725	1903	* @}
Kojto	122:f9eeca106725	1904	*/
Kojto	122:f9eeca106725	1905
Kojto	122:f9eeca106725	1906	/** @defgroup DMA_LL_EF_IT_Management IT_Management
Kojto	122:f9eeca106725	1907	* @{
Kojto	122:f9eeca106725	1908	*/
Kojto	122:f9eeca106725	1909	/**
Kojto	122:f9eeca106725	1910	* @brief Enable Transfer complete interrupt.
Kojto	122:f9eeca106725	1911	* @rmtoll CCR TCIE LL_DMA_EnableIT_TC
Kojto	122:f9eeca106725	1912	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1913	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	1914	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	1915	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	1916	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	1917	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	1918	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	1919	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	1920	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	1921	* @retval None
Kojto	122:f9eeca106725	1922	*/
Kojto	122:f9eeca106725	1923	__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	1924	{
Kojto	122:f9eeca106725	1925	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
Kojto	122:f9eeca106725	1926	}
Kojto	122:f9eeca106725	1927
Kojto	122:f9eeca106725	1928	/**
Kojto	122:f9eeca106725	1929	* @brief Enable Half transfer interrupt.
Kojto	122:f9eeca106725	1930	* @rmtoll CCR HTIE LL_DMA_EnableIT_HT
Kojto	122:f9eeca106725	1931	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1932	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	1933	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	1934	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	1935	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	1936	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	1937	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	1938	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	1939	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	1940	* @retval None
Kojto	122:f9eeca106725	1941	*/
Kojto	122:f9eeca106725	1942	__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	1943	{
Kojto	122:f9eeca106725	1944	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
Kojto	122:f9eeca106725	1945	}
Kojto	122:f9eeca106725	1946
Kojto	122:f9eeca106725	1947	/**
Kojto	122:f9eeca106725	1948	* @brief Enable Transfer error interrupt.
Kojto	122:f9eeca106725	1949	* @rmtoll CCR TEIE LL_DMA_EnableIT_TE
Kojto	122:f9eeca106725	1950	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1951	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	1952	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	1953	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	1954	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	1955	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	1956	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	1957	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	1958	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	1959	* @retval None
Kojto	122:f9eeca106725	1960	*/
Kojto	122:f9eeca106725	1961	__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	1962	{
Kojto	122:f9eeca106725	1963	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
Kojto	122:f9eeca106725	1964	}
Kojto	122:f9eeca106725	1965
Kojto	122:f9eeca106725	1966	/**
Kojto	122:f9eeca106725	1967	* @brief Disable Transfer complete interrupt.
Kojto	122:f9eeca106725	1968	* @rmtoll CCR TCIE LL_DMA_DisableIT_TC
Kojto	122:f9eeca106725	1969	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1970	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	1971	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	1972	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	1973	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	1974	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	1975	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	1976	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	1977	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	1978	* @retval None
Kojto	122:f9eeca106725	1979	*/
Kojto	122:f9eeca106725	1980	__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	1981	{
Kojto	122:f9eeca106725	1982	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
Kojto	122:f9eeca106725	1983	}
Kojto	122:f9eeca106725	1984
Kojto	122:f9eeca106725	1985	/**
Kojto	122:f9eeca106725	1986	* @brief Disable Half transfer interrupt.
Kojto	122:f9eeca106725	1987	* @rmtoll CCR HTIE LL_DMA_DisableIT_HT
Kojto	122:f9eeca106725	1988	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	1989	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	1990	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	1991	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	1992	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	1993	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	1994	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	1995	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	1996	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	1997	* @retval None
Kojto	122:f9eeca106725	1998	*/
Kojto	122:f9eeca106725	1999	__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	2000	{
Kojto	122:f9eeca106725	2001	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
Kojto	122:f9eeca106725	2002	}
Kojto	122:f9eeca106725	2003
Kojto	122:f9eeca106725	2004	/**
Kojto	122:f9eeca106725	2005	* @brief Disable Transfer error interrupt.
Kojto	122:f9eeca106725	2006	* @rmtoll CCR TEIE LL_DMA_DisableIT_TE
Kojto	122:f9eeca106725	2007	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	2008	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	2009	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	2010	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	2011	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	2012	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	2013	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	2014	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	2015	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	2016	* @retval None
Kojto	122:f9eeca106725	2017	*/
Kojto	122:f9eeca106725	2018	__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	2019	{
Kojto	122:f9eeca106725	2020	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
Kojto	122:f9eeca106725	2021	}
Kojto	122:f9eeca106725	2022
Kojto	122:f9eeca106725	2023	/**
Kojto	122:f9eeca106725	2024	* @brief Check if Transfer complete Interrupt is enabled.
Kojto	122:f9eeca106725	2025	* @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
Kojto	122:f9eeca106725	2026	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	2027	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	2028	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	2029	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	2030	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	2031	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	2032	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	2033	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	2034	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	2035	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	2036	*/
Kojto	122:f9eeca106725	2037	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	2038	{
Kojto	122:f9eeca106725	2039	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
Kojto	122:f9eeca106725	2040	DMA_CCR_TCIE) == (DMA_CCR_TCIE));
Kojto	122:f9eeca106725	2041	}
Kojto	122:f9eeca106725	2042
Kojto	122:f9eeca106725	2043	/**
Kojto	122:f9eeca106725	2044	* @brief Check if Half transfer Interrupt is enabled.
Kojto	122:f9eeca106725	2045	* @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
Kojto	122:f9eeca106725	2046	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	2047	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	2048	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	2049	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	2050	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	2051	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	2052	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	2053	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	2054	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	2055	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	2056	*/
Kojto	122:f9eeca106725	2057	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	2058	{
Kojto	122:f9eeca106725	2059	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
Kojto	122:f9eeca106725	2060	DMA_CCR_HTIE) == (DMA_CCR_HTIE));
Kojto	122:f9eeca106725	2061	}
Kojto	122:f9eeca106725	2062
Kojto	122:f9eeca106725	2063	/**
Kojto	122:f9eeca106725	2064	* @brief Check if Transfer error Interrupt is enabled.
Kojto	122:f9eeca106725	2065	* @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
Kojto	122:f9eeca106725	2066	* @param DMAx DMAx Instance
Kojto	122:f9eeca106725	2067	* @param Channel This parameter can be one of the following values:
Kojto	122:f9eeca106725	2068	* @arg @ref LL_DMA_CHANNEL_1
Kojto	122:f9eeca106725	2069	* @arg @ref LL_DMA_CHANNEL_2
Kojto	122:f9eeca106725	2070	* @arg @ref LL_DMA_CHANNEL_3
Kojto	122:f9eeca106725	2071	* @arg @ref LL_DMA_CHANNEL_4
Kojto	122:f9eeca106725	2072	* @arg @ref LL_DMA_CHANNEL_5
Kojto	122:f9eeca106725	2073	* @arg @ref LL_DMA_CHANNEL_6
Kojto	122:f9eeca106725	2074	* @arg @ref LL_DMA_CHANNEL_7
Kojto	122:f9eeca106725	2075	* @retval State of bit (1 or 0).
Kojto	122:f9eeca106725	2076	*/
Kojto	122:f9eeca106725	2077	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
Kojto	122:f9eeca106725	2078	{
Kojto	122:f9eeca106725	2079	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
Kojto	122:f9eeca106725	2080	DMA_CCR_TEIE) == (DMA_CCR_TEIE));
Kojto	122:f9eeca106725	2081	}
Kojto	122:f9eeca106725	2082
Kojto	122:f9eeca106725	2083	/**
Kojto	122:f9eeca106725	2084	* @}
Kojto	122:f9eeca106725	2085	*/
Kojto	122:f9eeca106725	2086
Kojto	122:f9eeca106725	2087	#if defined(USE_FULL_LL_DRIVER)
Kojto	122:f9eeca106725	2088	/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
Kojto	122:f9eeca106725	2089	* @{
Kojto	122:f9eeca106725	2090	*/
Kojto	122:f9eeca106725	2091
Kojto	122:f9eeca106725	2092	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Channel, LL_DMA_InitTypeDef DMA_InitStruct);
Kojto	122:f9eeca106725	2093	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
Kojto	122:f9eeca106725	2094	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
Kojto	122:f9eeca106725	2095
Kojto	122:f9eeca106725	2096	/**
Kojto	122:f9eeca106725	2097	* @}
Kojto	122:f9eeca106725	2098	*/
Kojto	122:f9eeca106725	2099	#endif /* USE_FULL_LL_DRIVER */
Kojto	122:f9eeca106725	2100
Kojto	122:f9eeca106725	2101	/**
Kojto	122:f9eeca106725	2102	* @}
Kojto	122:f9eeca106725	2103	*/
Kojto	122:f9eeca106725	2104
Kojto	122:f9eeca106725	2105	/**
Kojto	122:f9eeca106725	2106	* @}
Kojto	122:f9eeca106725	2107	*/
Kojto	122:f9eeca106725	2108
Kojto	122:f9eeca106725	2109	#endif /* DMA1 \|\| DMA2 */
Kojto	122:f9eeca106725	2110
Kojto	122:f9eeca106725	2111	/**
Kojto	122:f9eeca106725	2112	* @}
Kojto	122:f9eeca106725	2113	*/
Kojto	122:f9eeca106725	2114
Kojto	122:f9eeca106725	2115	#ifdef __cplusplus
Kojto	122:f9eeca106725	2116	}
Kojto	122:f9eeca106725	2117	#endif
Kojto	122:f9eeca106725	2118
Kojto	122:f9eeca106725	2119	#endif /* __STM32L4xx_LL_DMA_H */
Kojto	122:f9eeca106725	2120
Kojto	122:f9eeca106725	2121	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/