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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_L486RG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pwr_ex.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
128:9bcdf88f62b0
Child:
145:64910690c574
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 122:f9eeca106725 1 /**
Kojto 122:f9eeca106725 2 ******************************************************************************
Kojto 122:f9eeca106725 3 * @file stm32l4xx_hal_pwr_ex.h
Kojto 122:f9eeca106725 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V1.5.1
Kojto 122:f9eeca106725 6 * @date 31-May-2016
Kojto 122:f9eeca106725 7 * @brief Header file of PWR HAL Extended module.
Kojto 122:f9eeca106725 8 ******************************************************************************
Kojto 122:f9eeca106725 9 * @attention
Kojto 122:f9eeca106725 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 122:f9eeca106725 12 *
Kojto 122:f9eeca106725 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 122:f9eeca106725 14 * are permitted provided that the following conditions are met:
Kojto 122:f9eeca106725 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 122:f9eeca106725 16 * this list of conditions and the following disclaimer.
Kojto 122:f9eeca106725 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 122:f9eeca106725 18 * this list of conditions and the following disclaimer in the documentation
Kojto 122:f9eeca106725 19 * and/or other materials provided with the distribution.
Kojto 122:f9eeca106725 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 122:f9eeca106725 21 * may be used to endorse or promote products derived from this software
Kojto 122:f9eeca106725 22 * without specific prior written permission.
Kojto 122:f9eeca106725 23 *
Kojto 122:f9eeca106725 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 122:f9eeca106725 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 122:f9eeca106725 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 122:f9eeca106725 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 122:f9eeca106725 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 122:f9eeca106725 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 122:f9eeca106725 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 122:f9eeca106725 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 122:f9eeca106725 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 122:f9eeca106725 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 122:f9eeca106725 34 *
Kojto 122:f9eeca106725 35 ******************************************************************************
Kojto 122:f9eeca106725 36 */
Kojto 122:f9eeca106725 37
Kojto 122:f9eeca106725 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 122:f9eeca106725 39 #ifndef __STM32L4xx_HAL_PWR_EX_H
Kojto 122:f9eeca106725 40 #define __STM32L4xx_HAL_PWR_EX_H
Kojto 122:f9eeca106725 41
Kojto 122:f9eeca106725 42 #ifdef __cplusplus
Kojto 122:f9eeca106725 43 extern "C" {
Kojto 122:f9eeca106725 44 #endif
Kojto 122:f9eeca106725 45
Kojto 122:f9eeca106725 46 /* Includes ------------------------------------------------------------------*/
Kojto 122:f9eeca106725 47 #include "stm32l4xx_hal_def.h"
Kojto 122:f9eeca106725 48
Kojto 122:f9eeca106725 49 /** @addtogroup STM32L4xx_HAL_Driver
Kojto 122:f9eeca106725 50 * @{
Kojto 122:f9eeca106725 51 */
Kojto 122:f9eeca106725 52
Kojto 122:f9eeca106725 53 /** @addtogroup PWREx
Kojto 122:f9eeca106725 54 * @{
Kojto 122:f9eeca106725 55 */
Kojto 122:f9eeca106725 56
Kojto 122:f9eeca106725 57
Kojto 122:f9eeca106725 58 /* Exported types ------------------------------------------------------------*/
Kojto 122:f9eeca106725 59
Kojto 122:f9eeca106725 60 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types
Kojto 122:f9eeca106725 61 * @{
Kojto 122:f9eeca106725 62 */
Kojto 122:f9eeca106725 63
Kojto 122:f9eeca106725 64
Kojto 122:f9eeca106725 65 /**
Kojto 122:f9eeca106725 66 * @brief PWR PVM configuration structure definition
Kojto 122:f9eeca106725 67 */
Kojto 122:f9eeca106725 68 typedef struct
Kojto 122:f9eeca106725 69 {
Kojto 122:f9eeca106725 70 uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold.
Kojto 122:f9eeca106725 71 This parameter can be a value of @ref PWREx_PVM_Type.
Kojto 122:f9eeca106725 72 @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported).
Kojto 122:f9eeca106725 73 @if STM32L486xx
Kojto 122:f9eeca106725 74 @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device).
Kojto 122:f9eeca106725 75 @endif
Kojto 122:f9eeca106725 76 @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V.
Kojto 122:f9eeca106725 77 @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */
Kojto 122:f9eeca106725 78
Kojto 122:f9eeca106725 79 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
Kojto 122:f9eeca106725 80 This parameter can be a value of @ref PWREx_PVM_Mode. */
Kojto 122:f9eeca106725 81 }PWR_PVMTypeDef;
Kojto 122:f9eeca106725 82
Kojto 122:f9eeca106725 83 /**
Kojto 122:f9eeca106725 84 * @}
Kojto 122:f9eeca106725 85 */
Kojto 122:f9eeca106725 86
Kojto 122:f9eeca106725 87 /* Exported constants --------------------------------------------------------*/
Kojto 122:f9eeca106725 88
Kojto 122:f9eeca106725 89 /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
Kojto 122:f9eeca106725 90 * @{
Kojto 122:f9eeca106725 91 */
Kojto 122:f9eeca106725 92
Kojto 122:f9eeca106725 93 /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
Kojto 122:f9eeca106725 94 * @{
Kojto 122:f9eeca106725 95 */
Kojto 122:f9eeca106725 96 #define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polariry */
Kojto 122:f9eeca106725 97 /**
Kojto 122:f9eeca106725 98 * @}
Kojto 122:f9eeca106725 99 */
Kojto 122:f9eeca106725 100
Kojto 122:f9eeca106725 101
Kojto 122:f9eeca106725 102 /** @defgroup PWREx_WakeUp_Pins PWR wake-up pins
Kojto 122:f9eeca106725 103 * @{
Kojto 122:f9eeca106725 104 */
Kojto 122:f9eeca106725 105 #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
Kojto 122:f9eeca106725 106 #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
Kojto 122:f9eeca106725 107 #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
Kojto 122:f9eeca106725 108 #define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
Kojto 122:f9eeca106725 109 #define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
Kojto 122:f9eeca106725 110 #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
Kojto 122:f9eeca106725 111 #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
Kojto 122:f9eeca106725 112 #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
Kojto 122:f9eeca106725 113 #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
Kojto 122:f9eeca106725 114 #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
Kojto 122:f9eeca106725 115 #define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
Kojto 122:f9eeca106725 116 #define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
Kojto 122:f9eeca106725 117 #define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
Kojto 122:f9eeca106725 118 #define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */
Kojto 122:f9eeca106725 119 #define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */
Kojto 122:f9eeca106725 120 /**
Kojto 122:f9eeca106725 121 * @}
Kojto 122:f9eeca106725 122 */
Kojto 122:f9eeca106725 123
Kojto 122:f9eeca106725 124 /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
Kojto 122:f9eeca106725 125 * @{
Kojto 122:f9eeca106725 126 */
Kojto 122:f9eeca106725 127 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
Kojto 122:f9eeca106725 128 defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
Kojto 122:f9eeca106725 129 #define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */
Kojto 122:f9eeca106725 130 #endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
Kojto 122:f9eeca106725 131 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
Kojto 122:f9eeca106725 132 #define PWR_PVM_2 PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */
Kojto 122:f9eeca106725 133 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
Kojto 122:f9eeca106725 134 #define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
Kojto 122:f9eeca106725 135 #define PWR_PVM_4 PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V */
Kojto 122:f9eeca106725 136 /**
Kojto 122:f9eeca106725 137 * @}
Kojto 122:f9eeca106725 138 */
Kojto 122:f9eeca106725 139
Kojto 122:f9eeca106725 140 /** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode
Kojto 122:f9eeca106725 141 * @{
Kojto 122:f9eeca106725 142 */
Kojto 122:f9eeca106725 143 #define PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
Kojto 122:f9eeca106725 144 #define PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
Kojto 122:f9eeca106725 145 #define PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
Kojto 122:f9eeca106725 146 #define PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
Kojto 122:f9eeca106725 147 #define PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
Kojto 122:f9eeca106725 148 #define PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
Kojto 122:f9eeca106725 149 #define PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
Kojto 122:f9eeca106725 150 /**
Kojto 122:f9eeca106725 151 * @}
Kojto 122:f9eeca106725 152 */
Kojto 122:f9eeca106725 153
Kojto 122:f9eeca106725 154
Kojto 122:f9eeca106725 155
Kojto 122:f9eeca106725 156 /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale
Kojto 122:f9eeca106725 157 * @{
Kojto 122:f9eeca106725 158 */
Kojto 122:f9eeca106725 159 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 */
Kojto 122:f9eeca106725 160 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */
Kojto 122:f9eeca106725 161 /**
Kojto 122:f9eeca106725 162 * @}
Kojto 122:f9eeca106725 163 */
Kojto 122:f9eeca106725 164
Kojto 122:f9eeca106725 165
Kojto 122:f9eeca106725 166 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
Kojto 122:f9eeca106725 167 * @{
Kojto 122:f9eeca106725 168 */
Kojto 122:f9eeca106725 169 #define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000) /*!< VBAT charging through a 5 kOhms resistor */
Kojto 122:f9eeca106725 170 #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
Kojto 122:f9eeca106725 171 /**
Kojto 122:f9eeca106725 172 * @}
Kojto 122:f9eeca106725 173 */
Kojto 122:f9eeca106725 174
Kojto 122:f9eeca106725 175 /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
Kojto 122:f9eeca106725 176 * @{
Kojto 122:f9eeca106725 177 */
Kojto 122:f9eeca106725 178 #define PWR_BATTERY_CHARGING_DISABLE ((uint32_t)0x00000000)
Kojto 122:f9eeca106725 179 #define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE
Kojto 122:f9eeca106725 180 /**
Kojto 122:f9eeca106725 181 * @}
Kojto 122:f9eeca106725 182 */
Kojto 122:f9eeca106725 183
Kojto 122:f9eeca106725 184 /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
Kojto 122:f9eeca106725 185 * @{
Kojto 122:f9eeca106725 186 */
Kojto 122:f9eeca106725 187 #define PWR_GPIO_BIT_0 PWR_PUCRA_PA0 /*!< GPIO port I/O pin 0 */
Kojto 122:f9eeca106725 188 #define PWR_GPIO_BIT_1 PWR_PUCRA_PA1 /*!< GPIO port I/O pin 1 */
Kojto 122:f9eeca106725 189 #define PWR_GPIO_BIT_2 PWR_PUCRA_PA2 /*!< GPIO port I/O pin 2 */
Kojto 122:f9eeca106725 190 #define PWR_GPIO_BIT_3 PWR_PUCRA_PA3 /*!< GPIO port I/O pin 3 */
Kojto 122:f9eeca106725 191 #define PWR_GPIO_BIT_4 PWR_PUCRA_PA4 /*!< GPIO port I/O pin 4 */
Kojto 122:f9eeca106725 192 #define PWR_GPIO_BIT_5 PWR_PUCRA_PA5 /*!< GPIO port I/O pin 5 */
Kojto 122:f9eeca106725 193 #define PWR_GPIO_BIT_6 PWR_PUCRA_PA6 /*!< GPIO port I/O pin 6 */
Kojto 122:f9eeca106725 194 #define PWR_GPIO_BIT_7 PWR_PUCRA_PA7 /*!< GPIO port I/O pin 7 */
Kojto 122:f9eeca106725 195 #define PWR_GPIO_BIT_8 PWR_PUCRA_PA8 /*!< GPIO port I/O pin 8 */
Kojto 122:f9eeca106725 196 #define PWR_GPIO_BIT_9 PWR_PUCRA_PA9 /*!< GPIO port I/O pin 9 */
Kojto 122:f9eeca106725 197 #define PWR_GPIO_BIT_10 PWR_PUCRA_PA10 /*!< GPIO port I/O pin 10 */
Kojto 122:f9eeca106725 198 #define PWR_GPIO_BIT_11 PWR_PUCRA_PA11 /*!< GPIO port I/O pin 11 */
Kojto 122:f9eeca106725 199 #define PWR_GPIO_BIT_12 PWR_PUCRA_PA12 /*!< GPIO port I/O pin 12 */
Kojto 122:f9eeca106725 200 #define PWR_GPIO_BIT_13 PWR_PUCRA_PA13 /*!< GPIO port I/O pin 13 */
Kojto 122:f9eeca106725 201 #define PWR_GPIO_BIT_14 PWR_PDCRA_PA14 /*!< GPIO port I/O pin 14 */
Kojto 122:f9eeca106725 202 #define PWR_GPIO_BIT_15 PWR_PUCRA_PA15 /*!< GPIO port I/O pin 15 */
Kojto 122:f9eeca106725 203 /**
Kojto 122:f9eeca106725 204 * @}
Kojto 122:f9eeca106725 205 */
Kojto 122:f9eeca106725 206
Kojto 122:f9eeca106725 207 /** @defgroup PWREx_GPIO GPIO port
Kojto 122:f9eeca106725 208 * @{
Kojto 122:f9eeca106725 209 */
Kojto 122:f9eeca106725 210 #define PWR_GPIO_A 0x00000000 /*!< GPIO port A */
Kojto 122:f9eeca106725 211 #define PWR_GPIO_B 0x00000001 /*!< GPIO port B */
Kojto 122:f9eeca106725 212 #define PWR_GPIO_C 0x00000002 /*!< GPIO port C */
Kojto 122:f9eeca106725 213 #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \
Kojto 122:f9eeca106725 214 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
Kojto 122:f9eeca106725 215 #define PWR_GPIO_D 0x00000003 /*!< GPIO port D */
Kojto 122:f9eeca106725 216 #define PWR_GPIO_E 0x00000004 /*!< GPIO port E */
Kojto 122:f9eeca106725 217 #endif
Kojto 122:f9eeca106725 218 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
Kojto 122:f9eeca106725 219 #define PWR_GPIO_F 0x00000005 /*!< GPIO port F */
Kojto 122:f9eeca106725 220 #define PWR_GPIO_G 0x00000006 /*!< GPIO port G */
Kojto 122:f9eeca106725 221 #endif
Kojto 122:f9eeca106725 222 #define PWR_GPIO_H 0x00000007 /*!< GPIO port H */
Kojto 122:f9eeca106725 223 /**
Kojto 122:f9eeca106725 224 * @}
Kojto 122:f9eeca106725 225 */
Kojto 122:f9eeca106725 226
Kojto 122:f9eeca106725 227 /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
Kojto 122:f9eeca106725 228 * @{
Kojto 122:f9eeca106725 229 */
Kojto 122:f9eeca106725 230 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
Kojto 122:f9eeca106725 231 #define PWR_EXTI_LINE_PVM1 ((uint32_t)0x00000008) /*!< External interrupt line 35 Connected to the PVM1 EXTI Line */
Kojto 122:f9eeca106725 232 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
Kojto 122:f9eeca106725 233 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
Kojto 122:f9eeca106725 234 #define PWR_EXTI_LINE_PVM2 ((uint32_t)0x00000010) /*!< External interrupt line 36 Connected to the PVM2 EXTI Line */
Kojto 122:f9eeca106725 235 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
Kojto 122:f9eeca106725 236 #define PWR_EXTI_LINE_PVM3 ((uint32_t)0x00000020) /*!< External interrupt line 37 Connected to the PVM3 EXTI Line */
Kojto 122:f9eeca106725 237 #define PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040) /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */
Kojto 122:f9eeca106725 238 /**
Kojto 122:f9eeca106725 239 * @}
Kojto 122:f9eeca106725 240 */
Kojto 122:f9eeca106725 241
Kojto 122:f9eeca106725 242 /** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines
Kojto 122:f9eeca106725 243 * @{
Kojto 122:f9eeca106725 244 */
Kojto 122:f9eeca106725 245 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
Kojto 122:f9eeca106725 246 #define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008) /*!< Event line 35 Connected to the PVM1 EXTI Line */
Kojto 122:f9eeca106725 247 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
Kojto 122:f9eeca106725 248 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
Kojto 122:f9eeca106725 249 #define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010) /*!< Event line 36 Connected to the PVM2 EXTI Line */
Kojto 122:f9eeca106725 250 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
Kojto 122:f9eeca106725 251 #define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020) /*!< Event line 37 Connected to the PVM3 EXTI Line */
Kojto 122:f9eeca106725 252 #define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040) /*!< Event line 38 Connected to the PVM4 EXTI Line */
Kojto 122:f9eeca106725 253 /**
Kojto 122:f9eeca106725 254 * @}
Kojto 122:f9eeca106725 255 */
Kojto 122:f9eeca106725 256
Kojto 122:f9eeca106725 257 /** @defgroup PWREx_Flag PWR Status Flags
Kojto 122:f9eeca106725 258 * Elements values convention: 0000 0000 0XXY YYYYb
Kojto 122:f9eeca106725 259 * - Y YYYY : Flag position in the XX register (5 bits)
Kojto 122:f9eeca106725 260 * - XX : Status register (2 bits)
Kojto 122:f9eeca106725 261 * - 01: SR1 register
Kojto 122:f9eeca106725 262 * - 10: SR2 register
Kojto 122:f9eeca106725 263 * The only exception is PWR_FLAG_WU, encompassing all
Kojto 122:f9eeca106725 264 * wake-up flags and set to PWR_SR1_WUF.
Kojto 122:f9eeca106725 265 * @{
Kojto 122:f9eeca106725 266 */
Kojto 122:f9eeca106725 267 #define PWR_FLAG_WUF1 ((uint32_t)0x0020) /*!< Wakeup event on wakeup pin 1 */
Kojto 122:f9eeca106725 268 #define PWR_FLAG_WUF2 ((uint32_t)0x0021) /*!< Wakeup event on wakeup pin 2 */
Kojto 122:f9eeca106725 269 #define PWR_FLAG_WUF3 ((uint32_t)0x0022) /*!< Wakeup event on wakeup pin 3 */
Kojto 122:f9eeca106725 270 #define PWR_FLAG_WUF4 ((uint32_t)0x0023) /*!< Wakeup event on wakeup pin 4 */
Kojto 122:f9eeca106725 271 #define PWR_FLAG_WUF5 ((uint32_t)0x0024) /*!< Wakeup event on wakeup pin 5 */
Kojto 122:f9eeca106725 272 #define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */
Kojto 122:f9eeca106725 273 #define PWR_FLAG_SB ((uint32_t)0x0028) /*!< Standby flag */
Kojto 122:f9eeca106725 274 #define PWR_FLAG_WUFI ((uint32_t)0x002F) /*!< Wakeup on internal wakeup line */
Kojto 122:f9eeca106725 275
Kojto 122:f9eeca106725 276 #define PWR_FLAG_REGLPS ((uint32_t)0x0048) /*!< Low-power regulator start flag */
Kojto 122:f9eeca106725 277 #define PWR_FLAG_REGLPF ((uint32_t)0x0049) /*!< Low-power regulator flag */
Kojto 122:f9eeca106725 278 #define PWR_FLAG_VOSF ((uint32_t)0x004A) /*!< Voltage scaling flag */
Kojto 122:f9eeca106725 279 #define PWR_FLAG_PVDO ((uint32_t)0x004B) /*!< Power Voltage Detector output flag */
Kojto 122:f9eeca106725 280 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
Kojto 122:f9eeca106725 281 #define PWR_FLAG_PVMO1 ((uint32_t)0x004C) /*!< Power Voltage Monitoring 1 output flag */
Kojto 122:f9eeca106725 282 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
Kojto 122:f9eeca106725 283 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
Kojto 122:f9eeca106725 284 #define PWR_FLAG_PVMO2 ((uint32_t)0x004D) /*!< Power Voltage Monitoring 2 output flag */
Kojto 122:f9eeca106725 285 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
Kojto 122:f9eeca106725 286 #define PWR_FLAG_PVMO3 ((uint32_t)0x004E) /*!< Power Voltage Monitoring 3 output flag */
Kojto 122:f9eeca106725 287 #define PWR_FLAG_PVMO4 ((uint32_t)0x004F) /*!< Power Voltage Monitoring 4 output flag */
Kojto 122:f9eeca106725 288 /**
Kojto 122:f9eeca106725 289 * @}
Kojto 122:f9eeca106725 290 */
Kojto 122:f9eeca106725 291
Kojto 122:f9eeca106725 292 /**
Kojto 122:f9eeca106725 293 * @}
Kojto 122:f9eeca106725 294 */
Kojto 122:f9eeca106725 295
Kojto 122:f9eeca106725 296 /* Exported macros -----------------------------------------------------------*/
Kojto 122:f9eeca106725 297 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
Kojto 122:f9eeca106725 298 * @{
Kojto 122:f9eeca106725 299 */
Kojto 122:f9eeca106725 300
Kojto 122:f9eeca106725 301 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
Kojto 122:f9eeca106725 302 /**
Kojto 122:f9eeca106725 303 * @brief Enable the PVM1 Extended Interrupt Line.
Kojto 122:f9eeca106725 304 * @retval None
Kojto 122:f9eeca106725 305 */
Kojto 122:f9eeca106725 306 #define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
Kojto 122:f9eeca106725 307
Kojto 122:f9eeca106725 308 /**
Kojto 122:f9eeca106725 309 * @brief Disable the PVM1 Extended Interrupt Line.
Kojto 122:f9eeca106725 310 * @retval None
Kojto 122:f9eeca106725 311 */
Kojto 122:f9eeca106725 312 #define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
Kojto 122:f9eeca106725 313
Kojto 122:f9eeca106725 314 /**
Kojto 122:f9eeca106725 315 * @brief Enable the PVM1 Event Line.
Kojto 122:f9eeca106725 316 * @retval None
Kojto 122:f9eeca106725 317 */
Kojto 122:f9eeca106725 318 #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
Kojto 122:f9eeca106725 319
Kojto 122:f9eeca106725 320 /**
Kojto 122:f9eeca106725 321 * @brief Disable the PVM1 Event Line.
Kojto 122:f9eeca106725 322 * @retval None
Kojto 122:f9eeca106725 323 */
Kojto 122:f9eeca106725 324 #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
Kojto 122:f9eeca106725 325
Kojto 122:f9eeca106725 326 /**
Kojto 122:f9eeca106725 327 * @brief Enable the PVM1 Extended Interrupt Rising Trigger.
Kojto 122:f9eeca106725 328 * @retval None
Kojto 122:f9eeca106725 329 */
Kojto 122:f9eeca106725 330 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
Kojto 122:f9eeca106725 331
Kojto 122:f9eeca106725 332 /**
Kojto 122:f9eeca106725 333 * @brief Disable the PVM1 Extended Interrupt Rising Trigger.
Kojto 122:f9eeca106725 334 * @retval None
Kojto 122:f9eeca106725 335 */
Kojto 122:f9eeca106725 336 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
Kojto 122:f9eeca106725 337
Kojto 122:f9eeca106725 338 /**
Kojto 122:f9eeca106725 339 * @brief Enable the PVM1 Extended Interrupt Falling Trigger.
Kojto 122:f9eeca106725 340 * @retval None
Kojto 122:f9eeca106725 341 */
Kojto 122:f9eeca106725 342 #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
Kojto 122:f9eeca106725 343
Kojto 122:f9eeca106725 344
Kojto 122:f9eeca106725 345 /**
Kojto 122:f9eeca106725 346 * @brief Disable the PVM1 Extended Interrupt Falling Trigger.
Kojto 122:f9eeca106725 347 * @retval None
Kojto 122:f9eeca106725 348 */
Kojto 122:f9eeca106725 349 #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
Kojto 122:f9eeca106725 350
Kojto 122:f9eeca106725 351
Kojto 122:f9eeca106725 352 /**
Kojto 122:f9eeca106725 353 * @brief PVM1 EXTI line configuration: set rising & falling edge trigger.
Kojto 122:f9eeca106725 354 * @retval None
Kojto 122:f9eeca106725 355 */
Kojto 122:f9eeca106725 356 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \
Kojto 122:f9eeca106725 357 do { \
Kojto 122:f9eeca106725 358 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \
Kojto 122:f9eeca106725 359 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \
Kojto 122:f9eeca106725 360 } while(0)
Kojto 122:f9eeca106725 361
Kojto 122:f9eeca106725 362 /**
Kojto 122:f9eeca106725 363 * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
Kojto 122:f9eeca106725 364 * @retval None
Kojto 122:f9eeca106725 365 */
Kojto 122:f9eeca106725 366 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \
Kojto 122:f9eeca106725 367 do { \
Kojto 122:f9eeca106725 368 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \
Kojto 122:f9eeca106725 369 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \
Kojto 122:f9eeca106725 370 } while(0)
Kojto 122:f9eeca106725 371
Kojto 122:f9eeca106725 372 /**
Kojto 122:f9eeca106725 373 * @brief Generate a Software interrupt on selected EXTI line.
Kojto 122:f9eeca106725 374 * @retval None
Kojto 122:f9eeca106725 375 */
Kojto 122:f9eeca106725 376 #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
Kojto 122:f9eeca106725 377
Kojto 122:f9eeca106725 378 /**
Kojto 122:f9eeca106725 379 * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
Kojto 122:f9eeca106725 380 * @retval EXTI PVM1 Line Status.
Kojto 122:f9eeca106725 381 */
Kojto 122:f9eeca106725 382 #define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
Kojto 122:f9eeca106725 383
Kojto 122:f9eeca106725 384 /**
Kojto 122:f9eeca106725 385 * @brief Clear the PVM1 EXTI flag.
Kojto 122:f9eeca106725 386 * @retval None
Kojto 122:f9eeca106725 387 */
Kojto 122:f9eeca106725 388 #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
Kojto 122:f9eeca106725 389
Kojto 122:f9eeca106725 390 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
Kojto 122:f9eeca106725 391
Kojto 122:f9eeca106725 392
Kojto 122:f9eeca106725 393 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
Kojto 122:f9eeca106725 394 /**
Kojto 122:f9eeca106725 395 * @brief Enable the PVM2 Extended Interrupt Line.
Kojto 122:f9eeca106725 396 * @retval None
Kojto 122:f9eeca106725 397 */
Kojto 122:f9eeca106725 398 #define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
Kojto 122:f9eeca106725 399
Kojto 122:f9eeca106725 400 /**
Kojto 122:f9eeca106725 401 * @brief Disable the PVM2 Extended Interrupt Line.
Kojto 122:f9eeca106725 402 * @retval None
Kojto 122:f9eeca106725 403 */
Kojto 122:f9eeca106725 404 #define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
Kojto 122:f9eeca106725 405
Kojto 122:f9eeca106725 406 /**
Kojto 122:f9eeca106725 407 * @brief Enable the PVM2 Event Line.
Kojto 122:f9eeca106725 408 * @retval None
Kojto 122:f9eeca106725 409 */
Kojto 122:f9eeca106725 410 #define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
Kojto 122:f9eeca106725 411
Kojto 122:f9eeca106725 412 /**
Kojto 122:f9eeca106725 413 * @brief Disable the PVM2 Event Line.
Kojto 122:f9eeca106725 414 * @retval None
Kojto 122:f9eeca106725 415 */
Kojto 122:f9eeca106725 416 #define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
Kojto 122:f9eeca106725 417
Kojto 122:f9eeca106725 418 /**
Kojto 122:f9eeca106725 419 * @brief Enable the PVM2 Extended Interrupt Rising Trigger.
Kojto 122:f9eeca106725 420 * @retval None
Kojto 122:f9eeca106725 421 */
Kojto 122:f9eeca106725 422 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
Kojto 122:f9eeca106725 423
Kojto 122:f9eeca106725 424 /**
Kojto 122:f9eeca106725 425 * @brief Disable the PVM2 Extended Interrupt Rising Trigger.
Kojto 122:f9eeca106725 426 * @retval None
Kojto 122:f9eeca106725 427 */
Kojto 122:f9eeca106725 428 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
Kojto 122:f9eeca106725 429
Kojto 122:f9eeca106725 430 /**
Kojto 122:f9eeca106725 431 * @brief Enable the PVM2 Extended Interrupt Falling Trigger.
Kojto 122:f9eeca106725 432 * @retval None
Kojto 122:f9eeca106725 433 */
Kojto 122:f9eeca106725 434 #define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
Kojto 122:f9eeca106725 435
Kojto 122:f9eeca106725 436
Kojto 122:f9eeca106725 437 /**
Kojto 122:f9eeca106725 438 * @brief Disable the PVM2 Extended Interrupt Falling Trigger.
Kojto 122:f9eeca106725 439 * @retval None
Kojto 122:f9eeca106725 440 */
Kojto 122:f9eeca106725 441 #define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
Kojto 122:f9eeca106725 442
Kojto 122:f9eeca106725 443
Kojto 122:f9eeca106725 444 /**
Kojto 122:f9eeca106725 445 * @brief PVM2 EXTI line configuration: set rising & falling edge trigger.
Kojto 122:f9eeca106725 446 * @retval None
Kojto 122:f9eeca106725 447 */
Kojto 122:f9eeca106725 448 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \
Kojto 122:f9eeca106725 449 do { \
Kojto 122:f9eeca106725 450 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \
Kojto 122:f9eeca106725 451 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \
Kojto 122:f9eeca106725 452 } while(0)
Kojto 122:f9eeca106725 453
Kojto 122:f9eeca106725 454 /**
Kojto 122:f9eeca106725 455 * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
Kojto 122:f9eeca106725 456 * @retval None
Kojto 122:f9eeca106725 457 */
Kojto 122:f9eeca106725 458 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \
Kojto 122:f9eeca106725 459 do { \
Kojto 122:f9eeca106725 460 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \
Kojto 122:f9eeca106725 461 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \
Kojto 122:f9eeca106725 462 } while(0)
Kojto 122:f9eeca106725 463
Kojto 122:f9eeca106725 464 /**
Kojto 122:f9eeca106725 465 * @brief Generate a Software interrupt on selected EXTI line.
Kojto 122:f9eeca106725 466 * @retval None
Kojto 122:f9eeca106725 467 */
Kojto 122:f9eeca106725 468 #define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
Kojto 122:f9eeca106725 469
Kojto 122:f9eeca106725 470 /**
Kojto 122:f9eeca106725 471 * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not.
Kojto 122:f9eeca106725 472 * @retval EXTI PVM2 Line Status.
Kojto 122:f9eeca106725 473 */
Kojto 122:f9eeca106725 474 #define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
Kojto 122:f9eeca106725 475
Kojto 122:f9eeca106725 476 /**
Kojto 122:f9eeca106725 477 * @brief Clear the PVM2 EXTI flag.
Kojto 122:f9eeca106725 478 * @retval None
Kojto 122:f9eeca106725 479 */
Kojto 122:f9eeca106725 480 #define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
Kojto 122:f9eeca106725 481
Kojto 122:f9eeca106725 482 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
Kojto 122:f9eeca106725 483
Kojto 122:f9eeca106725 484
Kojto 122:f9eeca106725 485 /**
Kojto 122:f9eeca106725 486 * @brief Enable the PVM3 Extended Interrupt Line.
Kojto 122:f9eeca106725 487 * @retval None
Kojto 122:f9eeca106725 488 */
Kojto 122:f9eeca106725 489 #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
Kojto 122:f9eeca106725 490
Kojto 122:f9eeca106725 491 /**
Kojto 122:f9eeca106725 492 * @brief Disable the PVM3 Extended Interrupt Line.
Kojto 122:f9eeca106725 493 * @retval None
Kojto 122:f9eeca106725 494 */
Kojto 122:f9eeca106725 495 #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
Kojto 122:f9eeca106725 496
Kojto 122:f9eeca106725 497 /**
Kojto 122:f9eeca106725 498 * @brief Enable the PVM3 Event Line.
Kojto 122:f9eeca106725 499 * @retval None
Kojto 122:f9eeca106725 500 */
Kojto 122:f9eeca106725 501 #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
Kojto 122:f9eeca106725 502
Kojto 122:f9eeca106725 503 /**
Kojto 122:f9eeca106725 504 * @brief Disable the PVM3 Event Line.
Kojto 122:f9eeca106725 505 * @retval None
Kojto 122:f9eeca106725 506 */
Kojto 122:f9eeca106725 507 #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
Kojto 122:f9eeca106725 508
Kojto 122:f9eeca106725 509 /**
Kojto 122:f9eeca106725 510 * @brief Enable the PVM3 Extended Interrupt Rising Trigger.
Kojto 122:f9eeca106725 511 * @retval None
Kojto 122:f9eeca106725 512 */
Kojto 122:f9eeca106725 513 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
Kojto 122:f9eeca106725 514
Kojto 122:f9eeca106725 515 /**
Kojto 122:f9eeca106725 516 * @brief Disable the PVM3 Extended Interrupt Rising Trigger.
Kojto 122:f9eeca106725 517 * @retval None
Kojto 122:f9eeca106725 518 */
Kojto 122:f9eeca106725 519 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
Kojto 122:f9eeca106725 520
Kojto 122:f9eeca106725 521 /**
Kojto 122:f9eeca106725 522 * @brief Enable the PVM3 Extended Interrupt Falling Trigger.
Kojto 122:f9eeca106725 523 * @retval None
Kojto 122:f9eeca106725 524 */
Kojto 122:f9eeca106725 525 #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
Kojto 122:f9eeca106725 526
Kojto 122:f9eeca106725 527
Kojto 122:f9eeca106725 528 /**
Kojto 122:f9eeca106725 529 * @brief Disable the PVM3 Extended Interrupt Falling Trigger.
Kojto 122:f9eeca106725 530 * @retval None
Kojto 122:f9eeca106725 531 */
Kojto 122:f9eeca106725 532 #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
Kojto 122:f9eeca106725 533
Kojto 122:f9eeca106725 534
Kojto 122:f9eeca106725 535 /**
Kojto 122:f9eeca106725 536 * @brief PVM3 EXTI line configuration: set rising & falling edge trigger.
Kojto 122:f9eeca106725 537 * @retval None
Kojto 122:f9eeca106725 538 */
Kojto 122:f9eeca106725 539 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \
Kojto 122:f9eeca106725 540 do { \
Kojto 122:f9eeca106725 541 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \
Kojto 122:f9eeca106725 542 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \
Kojto 122:f9eeca106725 543 } while(0)
Kojto 122:f9eeca106725 544
Kojto 122:f9eeca106725 545 /**
Kojto 122:f9eeca106725 546 * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
Kojto 122:f9eeca106725 547 * @retval None
Kojto 122:f9eeca106725 548 */
Kojto 122:f9eeca106725 549 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \
Kojto 122:f9eeca106725 550 do { \
Kojto 122:f9eeca106725 551 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \
Kojto 122:f9eeca106725 552 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \
Kojto 122:f9eeca106725 553 } while(0)
Kojto 122:f9eeca106725 554
Kojto 122:f9eeca106725 555 /**
Kojto 122:f9eeca106725 556 * @brief Generate a Software interrupt on selected EXTI line.
Kojto 122:f9eeca106725 557 * @retval None
Kojto 122:f9eeca106725 558 */
Kojto 122:f9eeca106725 559 #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
Kojto 122:f9eeca106725 560
Kojto 122:f9eeca106725 561 /**
Kojto 122:f9eeca106725 562 * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
Kojto 122:f9eeca106725 563 * @retval EXTI PVM3 Line Status.
Kojto 122:f9eeca106725 564 */
Kojto 122:f9eeca106725 565 #define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
Kojto 122:f9eeca106725 566
Kojto 122:f9eeca106725 567 /**
Kojto 122:f9eeca106725 568 * @brief Clear the PVM3 EXTI flag.
Kojto 122:f9eeca106725 569 * @retval None
Kojto 122:f9eeca106725 570 */
Kojto 122:f9eeca106725 571 #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
Kojto 122:f9eeca106725 572
Kojto 122:f9eeca106725 573
Kojto 122:f9eeca106725 574
Kojto 122:f9eeca106725 575
Kojto 122:f9eeca106725 576 /**
Kojto 122:f9eeca106725 577 * @brief Enable the PVM4 Extended Interrupt Line.
Kojto 122:f9eeca106725 578 * @retval None
Kojto 122:f9eeca106725 579 */
Kojto 122:f9eeca106725 580 #define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
Kojto 122:f9eeca106725 581
Kojto 122:f9eeca106725 582 /**
Kojto 122:f9eeca106725 583 * @brief Disable the PVM4 Extended Interrupt Line.
Kojto 122:f9eeca106725 584 * @retval None
Kojto 122:f9eeca106725 585 */
Kojto 122:f9eeca106725 586 #define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
Kojto 122:f9eeca106725 587
Kojto 122:f9eeca106725 588 /**
Kojto 122:f9eeca106725 589 * @brief Enable the PVM4 Event Line.
Kojto 122:f9eeca106725 590 * @retval None
Kojto 122:f9eeca106725 591 */
Kojto 122:f9eeca106725 592 #define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
Kojto 122:f9eeca106725 593
Kojto 122:f9eeca106725 594 /**
Kojto 122:f9eeca106725 595 * @brief Disable the PVM4 Event Line.
Kojto 122:f9eeca106725 596 * @retval None
Kojto 122:f9eeca106725 597 */
Kojto 122:f9eeca106725 598 #define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
Kojto 122:f9eeca106725 599
Kojto 122:f9eeca106725 600 /**
Kojto 122:f9eeca106725 601 * @brief Enable the PVM4 Extended Interrupt Rising Trigger.
Kojto 122:f9eeca106725 602 * @retval None
Kojto 122:f9eeca106725 603 */
Kojto 122:f9eeca106725 604 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
Kojto 122:f9eeca106725 605
Kojto 122:f9eeca106725 606 /**
Kojto 122:f9eeca106725 607 * @brief Disable the PVM4 Extended Interrupt Rising Trigger.
Kojto 122:f9eeca106725 608 * @retval None
Kojto 122:f9eeca106725 609 */
Kojto 122:f9eeca106725 610 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
Kojto 122:f9eeca106725 611
Kojto 122:f9eeca106725 612 /**
Kojto 122:f9eeca106725 613 * @brief Enable the PVM4 Extended Interrupt Falling Trigger.
Kojto 122:f9eeca106725 614 * @retval None
Kojto 122:f9eeca106725 615 */
Kojto 122:f9eeca106725 616 #define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
Kojto 122:f9eeca106725 617
Kojto 122:f9eeca106725 618
Kojto 122:f9eeca106725 619 /**
Kojto 122:f9eeca106725 620 * @brief Disable the PVM4 Extended Interrupt Falling Trigger.
Kojto 122:f9eeca106725 621 * @retval None
Kojto 122:f9eeca106725 622 */
Kojto 122:f9eeca106725 623 #define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
Kojto 122:f9eeca106725 624
Kojto 122:f9eeca106725 625
Kojto 122:f9eeca106725 626 /**
Kojto 122:f9eeca106725 627 * @brief PVM4 EXTI line configuration: set rising & falling edge trigger.
Kojto 122:f9eeca106725 628 * @retval None
Kojto 122:f9eeca106725 629 */
Kojto 122:f9eeca106725 630 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \
Kojto 122:f9eeca106725 631 do { \
Kojto 122:f9eeca106725 632 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \
Kojto 122:f9eeca106725 633 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \
Kojto 122:f9eeca106725 634 } while(0)
Kojto 122:f9eeca106725 635
Kojto 122:f9eeca106725 636 /**
Kojto 122:f9eeca106725 637 * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
Kojto 122:f9eeca106725 638 * @retval None
Kojto 122:f9eeca106725 639 */
Kojto 122:f9eeca106725 640 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \
Kojto 122:f9eeca106725 641 do { \
Kojto 122:f9eeca106725 642 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \
Kojto 122:f9eeca106725 643 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \
Kojto 122:f9eeca106725 644 } while(0)
Kojto 122:f9eeca106725 645
Kojto 122:f9eeca106725 646 /**
Kojto 122:f9eeca106725 647 * @brief Generate a Software interrupt on selected EXTI line.
Kojto 122:f9eeca106725 648 * @retval None
Kojto 122:f9eeca106725 649 */
Kojto 122:f9eeca106725 650 #define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
Kojto 122:f9eeca106725 651
Kojto 122:f9eeca106725 652 /**
Kojto 122:f9eeca106725 653 * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set.
Kojto 122:f9eeca106725 654 * @retval EXTI PVM4 Line Status.
Kojto 122:f9eeca106725 655 */
Kojto 122:f9eeca106725 656 #define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
Kojto 122:f9eeca106725 657
Kojto 122:f9eeca106725 658 /**
Kojto 122:f9eeca106725 659 * @brief Clear the PVM4 EXTI flag.
Kojto 122:f9eeca106725 660 * @retval None
Kojto 122:f9eeca106725 661 */
Kojto 122:f9eeca106725 662 #define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
Kojto 122:f9eeca106725 663
Kojto 122:f9eeca106725 664
Kojto 122:f9eeca106725 665 /**
Kojto 122:f9eeca106725 666 * @brief Configure the main internal regulator output voltage.
Kojto 122:f9eeca106725 667 * @param __REGULATOR__: specifies the regulator output voltage to achieve
Kojto 122:f9eeca106725 668 * a tradeoff between performance and power consumption.
Kojto 122:f9eeca106725 669 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 670 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
Kojto 122:f9eeca106725 671 * typical output voltage at 1.2 V,
Kojto 122:f9eeca106725 672 * system frequency up to 80 MHz.
Kojto 122:f9eeca106725 673 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
Kojto 122:f9eeca106725 674 * typical output voltage at 1.0 V,
Kojto 122:f9eeca106725 675 * system frequency up to 26 MHz.
Kojto 122:f9eeca106725 676 * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
Kojto 122:f9eeca106725 677 * whether or not VOSF flag is cleared when moving from range 2 to range 1. User
Kojto 122:f9eeca106725 678 * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
Kojto 122:f9eeca106725 679 * @retval None
Kojto 122:f9eeca106725 680 */
Kojto 122:f9eeca106725 681 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
Kojto 122:f9eeca106725 682 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 683 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
Kojto 122:f9eeca106725 684 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 685 tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \
Kojto 122:f9eeca106725 686 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 687 } while(0)
Kojto 122:f9eeca106725 688
Kojto 122:f9eeca106725 689 /**
Kojto 122:f9eeca106725 690 * @}
Kojto 122:f9eeca106725 691 */
Kojto 122:f9eeca106725 692
Kojto 122:f9eeca106725 693 /* Private macros --------------------------------------------------------*/
Kojto 122:f9eeca106725 694 /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
Kojto 122:f9eeca106725 695 * @{
Kojto 122:f9eeca106725 696 */
Kojto 122:f9eeca106725 697
Kojto 122:f9eeca106725 698 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
Kojto 122:f9eeca106725 699 ((PIN) == PWR_WAKEUP_PIN2) || \
Kojto 122:f9eeca106725 700 ((PIN) == PWR_WAKEUP_PIN3) || \
Kojto 122:f9eeca106725 701 ((PIN) == PWR_WAKEUP_PIN4) || \
Kojto 122:f9eeca106725 702 ((PIN) == PWR_WAKEUP_PIN5) || \
Kojto 122:f9eeca106725 703 ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
Kojto 122:f9eeca106725 704 ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
Kojto 122:f9eeca106725 705 ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
Kojto 122:f9eeca106725 706 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
Kojto 122:f9eeca106725 707 ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
Kojto 122:f9eeca106725 708 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \
Kojto 122:f9eeca106725 709 ((PIN) == PWR_WAKEUP_PIN2_LOW) || \
Kojto 122:f9eeca106725 710 ((PIN) == PWR_WAKEUP_PIN3_LOW) || \
Kojto 122:f9eeca106725 711 ((PIN) == PWR_WAKEUP_PIN4_LOW) || \
Kojto 122:f9eeca106725 712 ((PIN) == PWR_WAKEUP_PIN5_LOW))
Kojto 122:f9eeca106725 713
Kojto 122:f9eeca106725 714 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
Kojto 122:f9eeca106725 715 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
Kojto 122:f9eeca106725 716 ((TYPE) == PWR_PVM_2) ||\
Kojto 122:f9eeca106725 717 ((TYPE) == PWR_PVM_3) ||\
Kojto 122:f9eeca106725 718 ((TYPE) == PWR_PVM_4))
Kojto 122:f9eeca106725 719 #elif defined (STM32L471xx)
Kojto 122:f9eeca106725 720 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) ||\
Kojto 122:f9eeca106725 721 ((TYPE) == PWR_PVM_3) ||\
Kojto 122:f9eeca106725 722 ((TYPE) == PWR_PVM_4))
Kojto 122:f9eeca106725 723 #endif
Kojto 122:f9eeca106725 724
Kojto 122:f9eeca106725 725 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
Kojto 122:f9eeca106725 726 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
Kojto 122:f9eeca106725 727 ((TYPE) == PWR_PVM_3) ||\
Kojto 122:f9eeca106725 728 ((TYPE) == PWR_PVM_4))
Kojto 122:f9eeca106725 729 #elif defined (STM32L431xx)
Kojto 122:f9eeca106725 730 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\
Kojto 122:f9eeca106725 731 ((TYPE) == PWR_PVM_4))
Kojto 122:f9eeca106725 732 #endif
Kojto 122:f9eeca106725 733
Kojto 122:f9eeca106725 734 #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\
Kojto 122:f9eeca106725 735 ((MODE) == PWR_PVM_MODE_IT_RISING) ||\
Kojto 122:f9eeca106725 736 ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\
Kojto 122:f9eeca106725 737 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\
Kojto 122:f9eeca106725 738 ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\
Kojto 122:f9eeca106725 739 ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\
Kojto 122:f9eeca106725 740 ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
Kojto 122:f9eeca106725 741
Kojto 122:f9eeca106725 742 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
Kojto 122:f9eeca106725 743 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
Kojto 122:f9eeca106725 744
Kojto 122:f9eeca106725 745 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
Kojto 122:f9eeca106725 746 ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
Kojto 122:f9eeca106725 747
Kojto 122:f9eeca106725 748 #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
Kojto 122:f9eeca106725 749 ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))
Kojto 122:f9eeca106725 750
Kojto 122:f9eeca106725 751 #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
Kojto 122:f9eeca106725 752
Kojto 122:f9eeca106725 753
Kojto 122:f9eeca106725 754 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
Kojto 122:f9eeca106725 755 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
Kojto 122:f9eeca106725 756 ((GPIO) == PWR_GPIO_B) ||\
Kojto 122:f9eeca106725 757 ((GPIO) == PWR_GPIO_C) ||\
Kojto 122:f9eeca106725 758 ((GPIO) == PWR_GPIO_D) ||\
Kojto 122:f9eeca106725 759 ((GPIO) == PWR_GPIO_E) ||\
Kojto 122:f9eeca106725 760 ((GPIO) == PWR_GPIO_F) ||\
Kojto 122:f9eeca106725 761 ((GPIO) == PWR_GPIO_G) ||\
Kojto 122:f9eeca106725 762 ((GPIO) == PWR_GPIO_H))
Kojto 122:f9eeca106725 763 #endif
Kojto 122:f9eeca106725 764 #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx)
Kojto 122:f9eeca106725 765 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
Kojto 122:f9eeca106725 766 ((GPIO) == PWR_GPIO_B) ||\
Kojto 122:f9eeca106725 767 ((GPIO) == PWR_GPIO_C) ||\
Kojto 122:f9eeca106725 768 ((GPIO) == PWR_GPIO_D) ||\
Kojto 122:f9eeca106725 769 ((GPIO) == PWR_GPIO_E) ||\
Kojto 122:f9eeca106725 770 ((GPIO) == PWR_GPIO_H))
Kojto 122:f9eeca106725 771 #elif defined (STM32L432xx) || defined (STM32L442xx)
Kojto 122:f9eeca106725 772 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
Kojto 122:f9eeca106725 773 ((GPIO) == PWR_GPIO_B) ||\
Kojto 122:f9eeca106725 774 ((GPIO) == PWR_GPIO_C) ||\
Kojto 122:f9eeca106725 775 ((GPIO) == PWR_GPIO_H))
Kojto 122:f9eeca106725 776 #endif
Kojto 122:f9eeca106725 777
Kojto 122:f9eeca106725 778
Kojto 122:f9eeca106725 779 /**
Kojto 122:f9eeca106725 780 * @}
Kojto 122:f9eeca106725 781 */
Kojto 122:f9eeca106725 782
Kojto 122:f9eeca106725 783
Kojto 122:f9eeca106725 784 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
Kojto 122:f9eeca106725 785 * @{
Kojto 122:f9eeca106725 786 */
Kojto 122:f9eeca106725 787
Kojto 122:f9eeca106725 788 /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
Kojto 122:f9eeca106725 789 * @{
Kojto 122:f9eeca106725 790 */
Kojto 122:f9eeca106725 791
Kojto 122:f9eeca106725 792
Kojto 122:f9eeca106725 793 /* Peripheral Control functions **********************************************/
Kojto 122:f9eeca106725 794 uint32_t HAL_PWREx_GetVoltageRange(void);
Kojto 122:f9eeca106725 795 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
Kojto 122:f9eeca106725 796 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
Kojto 122:f9eeca106725 797 void HAL_PWREx_DisableBatteryCharging(void);
Kojto 122:f9eeca106725 798 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
Kojto 122:f9eeca106725 799 void HAL_PWREx_EnableVddUSB(void);
Kojto 122:f9eeca106725 800 void HAL_PWREx_DisableVddUSB(void);
Kojto 122:f9eeca106725 801 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
Kojto 122:f9eeca106725 802 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
Kojto 122:f9eeca106725 803 void HAL_PWREx_EnableVddIO2(void);
Kojto 122:f9eeca106725 804 void HAL_PWREx_DisableVddIO2(void);
Kojto 122:f9eeca106725 805 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
Kojto 122:f9eeca106725 806 void HAL_PWREx_EnableInternalWakeUpLine(void);
Kojto 122:f9eeca106725 807 void HAL_PWREx_DisableInternalWakeUpLine(void);
Kojto 122:f9eeca106725 808 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
Kojto 122:f9eeca106725 809 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
Kojto 122:f9eeca106725 810 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
Kojto 122:f9eeca106725 811 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
Kojto 122:f9eeca106725 812 void HAL_PWREx_EnablePullUpPullDownConfig(void);
Kojto 122:f9eeca106725 813 void HAL_PWREx_DisablePullUpPullDownConfig(void);
Kojto 122:f9eeca106725 814 void HAL_PWREx_EnableSRAM2ContentRetention(void);
Kojto 122:f9eeca106725 815 void HAL_PWREx_DisableSRAM2ContentRetention(void);
Kojto 122:f9eeca106725 816 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
Kojto 122:f9eeca106725 817 void HAL_PWREx_EnablePVM1(void);
Kojto 122:f9eeca106725 818 void HAL_PWREx_DisablePVM1(void);
Kojto 122:f9eeca106725 819 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
Kojto 122:f9eeca106725 820 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
Kojto 122:f9eeca106725 821 void HAL_PWREx_EnablePVM2(void);
Kojto 122:f9eeca106725 822 void HAL_PWREx_DisablePVM2(void);
Kojto 122:f9eeca106725 823 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
Kojto 122:f9eeca106725 824 void HAL_PWREx_EnablePVM3(void);
Kojto 122:f9eeca106725 825 void HAL_PWREx_DisablePVM3(void);
Kojto 122:f9eeca106725 826 void HAL_PWREx_EnablePVM4(void);
Kojto 122:f9eeca106725 827 void HAL_PWREx_DisablePVM4(void);
Kojto 122:f9eeca106725 828 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
Kojto 122:f9eeca106725 829
Kojto 122:f9eeca106725 830
Kojto 122:f9eeca106725 831 /* Low Power modes configuration functions ************************************/
Kojto 122:f9eeca106725 832 void HAL_PWREx_EnableLowPowerRunMode(void);
Kojto 122:f9eeca106725 833 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
Kojto 122:f9eeca106725 834 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
Kojto 122:f9eeca106725 835 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
Kojto 122:f9eeca106725 836 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
Kojto 122:f9eeca106725 837 void HAL_PWREx_EnterSHUTDOWNMode(void);
Kojto 122:f9eeca106725 838
Kojto 122:f9eeca106725 839 void HAL_PWREx_PVD_PVM_IRQHandler(void);
Kojto 122:f9eeca106725 840 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
Kojto 122:f9eeca106725 841 void HAL_PWREx_PVM1Callback(void);
Kojto 122:f9eeca106725 842 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
Kojto 122:f9eeca106725 843 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
Kojto 122:f9eeca106725 844 void HAL_PWREx_PVM2Callback(void);
Kojto 122:f9eeca106725 845 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
Kojto 122:f9eeca106725 846 void HAL_PWREx_PVM3Callback(void);
Kojto 122:f9eeca106725 847 void HAL_PWREx_PVM4Callback(void);
Kojto 122:f9eeca106725 848
Kojto 122:f9eeca106725 849
Kojto 122:f9eeca106725 850 /**
Kojto 122:f9eeca106725 851 * @}
Kojto 122:f9eeca106725 852 */
Kojto 122:f9eeca106725 853
Kojto 122:f9eeca106725 854 /**
Kojto 122:f9eeca106725 855 * @}
Kojto 122:f9eeca106725 856 */
Kojto 122:f9eeca106725 857
Kojto 122:f9eeca106725 858 /**
Kojto 122:f9eeca106725 859 * @}
Kojto 122:f9eeca106725 860 */
Kojto 122:f9eeca106725 861
Kojto 122:f9eeca106725 862 /**
Kojto 122:f9eeca106725 863 * @}
Kojto 122:f9eeca106725 864 */
Kojto 122:f9eeca106725 865
Kojto 122:f9eeca106725 866 #ifdef __cplusplus
Kojto 122:f9eeca106725 867 }
Kojto 122:f9eeca106725 868 #endif
Kojto 122:f9eeca106725 869
Kojto 122:f9eeca106725 870
Kojto 122:f9eeca106725 871 #endif /* __STM32L4xx_HAL_PWR_EX_H */
Kojto 122:f9eeca106725 872
Kojto 122:f9eeca106725 873 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/