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TARGET_NUCLEO_L486RG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_cortex.h@140:97feb9bacc10, 2017-04-12 (annotated)
- Committer:
- <>
- Date:
- Wed Apr 12 16:07:08 2017 +0100
- Revision:
- 140:97feb9bacc10
- Parent:
- 128:9bcdf88f62b0
- Child:
- 145:64910690c574
Release 140 of the mbed library
Ports for Upcoming Targets
3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841
3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992
Fixes and Changes
3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951
4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021
3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979
3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the https://github.com/ARMmbed/mbed-os/pull/3990
4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003
4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012
4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020
4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065
4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014
4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030
4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109
3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Kojto | 122:f9eeca106725 | 1 | /** |
Kojto | 122:f9eeca106725 | 2 | ****************************************************************************** |
Kojto | 122:f9eeca106725 | 3 | * @file stm32l4xx_hal_cortex.h |
Kojto | 122:f9eeca106725 | 4 | * @author MCD Application Team |
Kojto | 122:f9eeca106725 | 5 | * @version V1.5.1 |
Kojto | 122:f9eeca106725 | 6 | * @date 31-May-2016 |
Kojto | 122:f9eeca106725 | 7 | * @brief Header file of CORTEX HAL module. |
Kojto | 122:f9eeca106725 | 8 | ****************************************************************************** |
Kojto | 122:f9eeca106725 | 9 | * @attention |
Kojto | 122:f9eeca106725 | 10 | * |
Kojto | 122:f9eeca106725 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
Kojto | 122:f9eeca106725 | 12 | * |
Kojto | 122:f9eeca106725 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
Kojto | 122:f9eeca106725 | 14 | * are permitted provided that the following conditions are met: |
Kojto | 122:f9eeca106725 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
Kojto | 122:f9eeca106725 | 16 | * this list of conditions and the following disclaimer. |
Kojto | 122:f9eeca106725 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
Kojto | 122:f9eeca106725 | 18 | * this list of conditions and the following disclaimer in the documentation |
Kojto | 122:f9eeca106725 | 19 | * and/or other materials provided with the distribution. |
Kojto | 122:f9eeca106725 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
Kojto | 122:f9eeca106725 | 21 | * may be used to endorse or promote products derived from this software |
Kojto | 122:f9eeca106725 | 22 | * without specific prior written permission. |
Kojto | 122:f9eeca106725 | 23 | * |
Kojto | 122:f9eeca106725 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
Kojto | 122:f9eeca106725 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
Kojto | 122:f9eeca106725 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
Kojto | 122:f9eeca106725 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
Kojto | 122:f9eeca106725 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
Kojto | 122:f9eeca106725 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
Kojto | 122:f9eeca106725 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
Kojto | 122:f9eeca106725 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
Kojto | 122:f9eeca106725 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
Kojto | 122:f9eeca106725 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Kojto | 122:f9eeca106725 | 34 | * |
Kojto | 122:f9eeca106725 | 35 | ****************************************************************************** |
Kojto | 122:f9eeca106725 | 36 | */ |
Kojto | 122:f9eeca106725 | 37 | |
Kojto | 122:f9eeca106725 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
Kojto | 122:f9eeca106725 | 39 | #ifndef __STM32L4xx_HAL_CORTEX_H |
Kojto | 122:f9eeca106725 | 40 | #define __STM32L4xx_HAL_CORTEX_H |
Kojto | 122:f9eeca106725 | 41 | |
Kojto | 122:f9eeca106725 | 42 | #ifdef __cplusplus |
Kojto | 122:f9eeca106725 | 43 | extern "C" { |
Kojto | 122:f9eeca106725 | 44 | #endif |
Kojto | 122:f9eeca106725 | 45 | |
Kojto | 122:f9eeca106725 | 46 | /* Includes ------------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 47 | #include "stm32l4xx_hal_def.h" |
Kojto | 122:f9eeca106725 | 48 | |
Kojto | 122:f9eeca106725 | 49 | /** @addtogroup STM32L4xx_HAL_Driver |
Kojto | 122:f9eeca106725 | 50 | * @{ |
Kojto | 122:f9eeca106725 | 51 | */ |
Kojto | 122:f9eeca106725 | 52 | |
Kojto | 122:f9eeca106725 | 53 | /** @defgroup CORTEX CORTEX |
Kojto | 122:f9eeca106725 | 54 | * @{ |
Kojto | 122:f9eeca106725 | 55 | */ |
Kojto | 122:f9eeca106725 | 56 | |
Kojto | 122:f9eeca106725 | 57 | /* Exported types ------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 58 | /** @defgroup CORTEX_Exported_Types CORTEX Exported Types |
Kojto | 122:f9eeca106725 | 59 | * @{ |
Kojto | 122:f9eeca106725 | 60 | */ |
Kojto | 122:f9eeca106725 | 61 | |
Kojto | 122:f9eeca106725 | 62 | #if (__MPU_PRESENT == 1) |
Kojto | 122:f9eeca106725 | 63 | /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition |
Kojto | 122:f9eeca106725 | 64 | * @{ |
Kojto | 122:f9eeca106725 | 65 | */ |
Kojto | 122:f9eeca106725 | 66 | typedef struct |
Kojto | 122:f9eeca106725 | 67 | { |
Kojto | 122:f9eeca106725 | 68 | uint8_t Enable; /*!< Specifies the status of the region. |
Kojto | 122:f9eeca106725 | 69 | This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ |
Kojto | 122:f9eeca106725 | 70 | uint8_t Number; /*!< Specifies the number of the region to protect. |
Kojto | 122:f9eeca106725 | 71 | This parameter can be a value of @ref CORTEX_MPU_Region_Number */ |
Kojto | 122:f9eeca106725 | 72 | uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ |
Kojto | 122:f9eeca106725 | 73 | uint8_t Size; /*!< Specifies the size of the region to protect. |
Kojto | 122:f9eeca106725 | 74 | This parameter can be a value of @ref CORTEX_MPU_Region_Size */ |
Kojto | 122:f9eeca106725 | 75 | uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. |
Kojto | 122:f9eeca106725 | 76 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
Kojto | 122:f9eeca106725 | 77 | uint8_t TypeExtField; /*!< Specifies the TEX field level. |
Kojto | 122:f9eeca106725 | 78 | This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ |
Kojto | 122:f9eeca106725 | 79 | uint8_t AccessPermission; /*!< Specifies the region access permission type. |
Kojto | 122:f9eeca106725 | 80 | This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ |
Kojto | 122:f9eeca106725 | 81 | uint8_t DisableExec; /*!< Specifies the instruction access status. |
Kojto | 122:f9eeca106725 | 82 | This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ |
Kojto | 122:f9eeca106725 | 83 | uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. |
Kojto | 122:f9eeca106725 | 84 | This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ |
Kojto | 122:f9eeca106725 | 85 | uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. |
Kojto | 122:f9eeca106725 | 86 | This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ |
Kojto | 122:f9eeca106725 | 87 | uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. |
Kojto | 122:f9eeca106725 | 88 | This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ |
Kojto | 122:f9eeca106725 | 89 | }MPU_Region_InitTypeDef; |
Kojto | 122:f9eeca106725 | 90 | /** |
Kojto | 122:f9eeca106725 | 91 | * @} |
Kojto | 122:f9eeca106725 | 92 | */ |
Kojto | 122:f9eeca106725 | 93 | #endif /* __MPU_PRESENT */ |
Kojto | 122:f9eeca106725 | 94 | |
Kojto | 122:f9eeca106725 | 95 | /** |
Kojto | 122:f9eeca106725 | 96 | * @} |
Kojto | 122:f9eeca106725 | 97 | */ |
Kojto | 122:f9eeca106725 | 98 | |
Kojto | 122:f9eeca106725 | 99 | /* Exported constants --------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 100 | |
Kojto | 122:f9eeca106725 | 101 | /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants |
Kojto | 122:f9eeca106725 | 102 | * @{ |
Kojto | 122:f9eeca106725 | 103 | */ |
Kojto | 122:f9eeca106725 | 104 | |
Kojto | 122:f9eeca106725 | 105 | /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group |
Kojto | 122:f9eeca106725 | 106 | * @{ |
Kojto | 122:f9eeca106725 | 107 | */ |
Kojto | 122:f9eeca106725 | 108 | #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority, |
Kojto | 122:f9eeca106725 | 109 | 4 bits for subpriority */ |
Kojto | 122:f9eeca106725 | 110 | #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority, |
Kojto | 122:f9eeca106725 | 111 | 3 bits for subpriority */ |
Kojto | 122:f9eeca106725 | 112 | #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority, |
Kojto | 122:f9eeca106725 | 113 | 2 bits for subpriority */ |
Kojto | 122:f9eeca106725 | 114 | #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority, |
Kojto | 122:f9eeca106725 | 115 | 1 bit for subpriority */ |
Kojto | 122:f9eeca106725 | 116 | #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority, |
Kojto | 122:f9eeca106725 | 117 | 0 bit for subpriority */ |
Kojto | 122:f9eeca106725 | 118 | /** |
Kojto | 122:f9eeca106725 | 119 | * @} |
Kojto | 122:f9eeca106725 | 120 | */ |
Kojto | 122:f9eeca106725 | 121 | |
Kojto | 122:f9eeca106725 | 122 | /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source |
Kojto | 122:f9eeca106725 | 123 | * @{ |
Kojto | 122:f9eeca106725 | 124 | */ |
Kojto | 122:f9eeca106725 | 125 | #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) |
Kojto | 122:f9eeca106725 | 126 | #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) |
Kojto | 122:f9eeca106725 | 127 | /** |
Kojto | 122:f9eeca106725 | 128 | * @} |
Kojto | 122:f9eeca106725 | 129 | */ |
Kojto | 122:f9eeca106725 | 130 | |
Kojto | 122:f9eeca106725 | 131 | #if (__MPU_PRESENT == 1) |
Kojto | 122:f9eeca106725 | 132 | /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control |
Kojto | 122:f9eeca106725 | 133 | * @{ |
Kojto | 122:f9eeca106725 | 134 | */ |
Kojto | 122:f9eeca106725 | 135 | #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) |
Kojto | 122:f9eeca106725 | 136 | #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) |
Kojto | 122:f9eeca106725 | 137 | #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) |
Kojto | 122:f9eeca106725 | 138 | #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) |
Kojto | 122:f9eeca106725 | 139 | /** |
Kojto | 122:f9eeca106725 | 140 | * @} |
Kojto | 122:f9eeca106725 | 141 | */ |
Kojto | 122:f9eeca106725 | 142 | |
Kojto | 122:f9eeca106725 | 143 | /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable |
Kojto | 122:f9eeca106725 | 144 | * @{ |
Kojto | 122:f9eeca106725 | 145 | */ |
Kojto | 122:f9eeca106725 | 146 | #define MPU_REGION_ENABLE ((uint8_t)0x01) |
Kojto | 122:f9eeca106725 | 147 | #define MPU_REGION_DISABLE ((uint8_t)0x00) |
Kojto | 122:f9eeca106725 | 148 | /** |
Kojto | 122:f9eeca106725 | 149 | * @} |
Kojto | 122:f9eeca106725 | 150 | */ |
Kojto | 122:f9eeca106725 | 151 | |
Kojto | 122:f9eeca106725 | 152 | /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access |
Kojto | 122:f9eeca106725 | 153 | * @{ |
Kojto | 122:f9eeca106725 | 154 | */ |
Kojto | 122:f9eeca106725 | 155 | #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) |
Kojto | 122:f9eeca106725 | 156 | #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) |
Kojto | 122:f9eeca106725 | 157 | /** |
Kojto | 122:f9eeca106725 | 158 | * @} |
Kojto | 122:f9eeca106725 | 159 | */ |
Kojto | 122:f9eeca106725 | 160 | |
Kojto | 122:f9eeca106725 | 161 | /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable |
Kojto | 122:f9eeca106725 | 162 | * @{ |
Kojto | 122:f9eeca106725 | 163 | */ |
Kojto | 122:f9eeca106725 | 164 | #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) |
Kojto | 122:f9eeca106725 | 165 | #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) |
Kojto | 122:f9eeca106725 | 166 | /** |
Kojto | 122:f9eeca106725 | 167 | * @} |
Kojto | 122:f9eeca106725 | 168 | */ |
Kojto | 122:f9eeca106725 | 169 | |
Kojto | 122:f9eeca106725 | 170 | /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable |
Kojto | 122:f9eeca106725 | 171 | * @{ |
Kojto | 122:f9eeca106725 | 172 | */ |
Kojto | 122:f9eeca106725 | 173 | #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) |
Kojto | 122:f9eeca106725 | 174 | #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) |
Kojto | 122:f9eeca106725 | 175 | /** |
Kojto | 122:f9eeca106725 | 176 | * @} |
Kojto | 122:f9eeca106725 | 177 | */ |
Kojto | 122:f9eeca106725 | 178 | |
Kojto | 122:f9eeca106725 | 179 | /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable |
Kojto | 122:f9eeca106725 | 180 | * @{ |
Kojto | 122:f9eeca106725 | 181 | */ |
Kojto | 122:f9eeca106725 | 182 | #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) |
Kojto | 122:f9eeca106725 | 183 | #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) |
Kojto | 122:f9eeca106725 | 184 | /** |
Kojto | 122:f9eeca106725 | 185 | * @} |
Kojto | 122:f9eeca106725 | 186 | */ |
Kojto | 122:f9eeca106725 | 187 | |
Kojto | 122:f9eeca106725 | 188 | /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels |
Kojto | 122:f9eeca106725 | 189 | * @{ |
Kojto | 122:f9eeca106725 | 190 | */ |
Kojto | 122:f9eeca106725 | 191 | #define MPU_TEX_LEVEL0 ((uint8_t)0x00) |
Kojto | 122:f9eeca106725 | 192 | #define MPU_TEX_LEVEL1 ((uint8_t)0x01) |
Kojto | 122:f9eeca106725 | 193 | #define MPU_TEX_LEVEL2 ((uint8_t)0x02) |
Kojto | 122:f9eeca106725 | 194 | /** |
Kojto | 122:f9eeca106725 | 195 | * @} |
Kojto | 122:f9eeca106725 | 196 | */ |
Kojto | 122:f9eeca106725 | 197 | |
Kojto | 122:f9eeca106725 | 198 | /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size |
Kojto | 122:f9eeca106725 | 199 | * @{ |
Kojto | 122:f9eeca106725 | 200 | */ |
Kojto | 122:f9eeca106725 | 201 | #define MPU_REGION_SIZE_32B ((uint8_t)0x04) |
Kojto | 122:f9eeca106725 | 202 | #define MPU_REGION_SIZE_64B ((uint8_t)0x05) |
Kojto | 122:f9eeca106725 | 203 | #define MPU_REGION_SIZE_128B ((uint8_t)0x06) |
Kojto | 122:f9eeca106725 | 204 | #define MPU_REGION_SIZE_256B ((uint8_t)0x07) |
Kojto | 122:f9eeca106725 | 205 | #define MPU_REGION_SIZE_512B ((uint8_t)0x08) |
Kojto | 122:f9eeca106725 | 206 | #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) |
Kojto | 122:f9eeca106725 | 207 | #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) |
Kojto | 122:f9eeca106725 | 208 | #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) |
Kojto | 122:f9eeca106725 | 209 | #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) |
Kojto | 122:f9eeca106725 | 210 | #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) |
Kojto | 122:f9eeca106725 | 211 | #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) |
Kojto | 122:f9eeca106725 | 212 | #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) |
Kojto | 122:f9eeca106725 | 213 | #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) |
Kojto | 122:f9eeca106725 | 214 | #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) |
Kojto | 122:f9eeca106725 | 215 | #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) |
Kojto | 122:f9eeca106725 | 216 | #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) |
Kojto | 122:f9eeca106725 | 217 | #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) |
Kojto | 122:f9eeca106725 | 218 | #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) |
Kojto | 122:f9eeca106725 | 219 | #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) |
Kojto | 122:f9eeca106725 | 220 | #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) |
Kojto | 122:f9eeca106725 | 221 | #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) |
Kojto | 122:f9eeca106725 | 222 | #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) |
Kojto | 122:f9eeca106725 | 223 | #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) |
Kojto | 122:f9eeca106725 | 224 | #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) |
Kojto | 122:f9eeca106725 | 225 | #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) |
Kojto | 122:f9eeca106725 | 226 | #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) |
Kojto | 122:f9eeca106725 | 227 | #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) |
Kojto | 122:f9eeca106725 | 228 | #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) |
Kojto | 122:f9eeca106725 | 229 | /** |
Kojto | 122:f9eeca106725 | 230 | * @} |
Kojto | 122:f9eeca106725 | 231 | */ |
Kojto | 122:f9eeca106725 | 232 | |
Kojto | 122:f9eeca106725 | 233 | /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes |
Kojto | 122:f9eeca106725 | 234 | * @{ |
Kojto | 122:f9eeca106725 | 235 | */ |
Kojto | 122:f9eeca106725 | 236 | #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) |
Kojto | 122:f9eeca106725 | 237 | #define MPU_REGION_PRIV_RW ((uint8_t)0x01) |
Kojto | 122:f9eeca106725 | 238 | #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) |
Kojto | 122:f9eeca106725 | 239 | #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) |
Kojto | 122:f9eeca106725 | 240 | #define MPU_REGION_PRIV_RO ((uint8_t)0x05) |
Kojto | 122:f9eeca106725 | 241 | #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) |
Kojto | 122:f9eeca106725 | 242 | /** |
Kojto | 122:f9eeca106725 | 243 | * @} |
Kojto | 122:f9eeca106725 | 244 | */ |
Kojto | 122:f9eeca106725 | 245 | |
Kojto | 122:f9eeca106725 | 246 | /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number |
Kojto | 122:f9eeca106725 | 247 | * @{ |
Kojto | 122:f9eeca106725 | 248 | */ |
Kojto | 122:f9eeca106725 | 249 | #define MPU_REGION_NUMBER0 ((uint8_t)0x00) |
Kojto | 122:f9eeca106725 | 250 | #define MPU_REGION_NUMBER1 ((uint8_t)0x01) |
Kojto | 122:f9eeca106725 | 251 | #define MPU_REGION_NUMBER2 ((uint8_t)0x02) |
Kojto | 122:f9eeca106725 | 252 | #define MPU_REGION_NUMBER3 ((uint8_t)0x03) |
Kojto | 122:f9eeca106725 | 253 | #define MPU_REGION_NUMBER4 ((uint8_t)0x04) |
Kojto | 122:f9eeca106725 | 254 | #define MPU_REGION_NUMBER5 ((uint8_t)0x05) |
Kojto | 122:f9eeca106725 | 255 | #define MPU_REGION_NUMBER6 ((uint8_t)0x06) |
Kojto | 122:f9eeca106725 | 256 | #define MPU_REGION_NUMBER7 ((uint8_t)0x07) |
Kojto | 122:f9eeca106725 | 257 | /** |
Kojto | 122:f9eeca106725 | 258 | * @} |
Kojto | 122:f9eeca106725 | 259 | */ |
Kojto | 122:f9eeca106725 | 260 | #endif /* __MPU_PRESENT */ |
Kojto | 122:f9eeca106725 | 261 | |
Kojto | 122:f9eeca106725 | 262 | /** |
Kojto | 122:f9eeca106725 | 263 | * @} |
Kojto | 122:f9eeca106725 | 264 | */ |
Kojto | 122:f9eeca106725 | 265 | |
Kojto | 122:f9eeca106725 | 266 | /* Exported macros -----------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 267 | /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros |
Kojto | 122:f9eeca106725 | 268 | * @{ |
Kojto | 122:f9eeca106725 | 269 | */ |
Kojto | 122:f9eeca106725 | 270 | |
Kojto | 122:f9eeca106725 | 271 | /** |
Kojto | 122:f9eeca106725 | 272 | * @} |
Kojto | 122:f9eeca106725 | 273 | */ |
Kojto | 122:f9eeca106725 | 274 | |
Kojto | 122:f9eeca106725 | 275 | /* Exported functions --------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 276 | /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions |
Kojto | 122:f9eeca106725 | 277 | * @{ |
Kojto | 122:f9eeca106725 | 278 | */ |
Kojto | 122:f9eeca106725 | 279 | |
Kojto | 122:f9eeca106725 | 280 | /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions |
Kojto | 122:f9eeca106725 | 281 | * @brief Initialization and Configuration functions |
Kojto | 122:f9eeca106725 | 282 | * @{ |
Kojto | 122:f9eeca106725 | 283 | */ |
Kojto | 122:f9eeca106725 | 284 | /* Initialization and Configuration functions *****************************/ |
Kojto | 122:f9eeca106725 | 285 | void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); |
Kojto | 122:f9eeca106725 | 286 | void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); |
Kojto | 122:f9eeca106725 | 287 | void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); |
Kojto | 122:f9eeca106725 | 288 | void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); |
Kojto | 122:f9eeca106725 | 289 | void HAL_NVIC_SystemReset(void); |
Kojto | 122:f9eeca106725 | 290 | uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); |
Kojto | 122:f9eeca106725 | 291 | |
Kojto | 122:f9eeca106725 | 292 | #if (__MPU_PRESENT == 1) |
Kojto | 122:f9eeca106725 | 293 | /** |
Kojto | 122:f9eeca106725 | 294 | * @brief Disable the MPU. |
Kojto | 122:f9eeca106725 | 295 | * @retval None |
Kojto | 122:f9eeca106725 | 296 | */ |
Kojto | 122:f9eeca106725 | 297 | __STATIC_INLINE void HAL_MPU_Disable(void) |
Kojto | 122:f9eeca106725 | 298 | { |
Kojto | 122:f9eeca106725 | 299 | /* Disable fault exceptions */ |
Kojto | 122:f9eeca106725 | 300 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; |
Kojto | 122:f9eeca106725 | 301 | |
Kojto | 122:f9eeca106725 | 302 | /* Disable the MPU */ |
Kojto | 122:f9eeca106725 | 303 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; |
Kojto | 122:f9eeca106725 | 304 | } |
Kojto | 122:f9eeca106725 | 305 | |
Kojto | 122:f9eeca106725 | 306 | /** |
Kojto | 122:f9eeca106725 | 307 | * @brief Enable the MPU. |
Kojto | 122:f9eeca106725 | 308 | * @param MPU_Control: Specifies the control mode of the MPU during hard fault, |
Kojto | 122:f9eeca106725 | 309 | * NMI, FAULTMASK and privileged accessto the default memory |
Kojto | 122:f9eeca106725 | 310 | * This parameter can be one of the following values: |
Kojto | 122:f9eeca106725 | 311 | * @arg MPU_HFNMI_PRIVDEF_NONE |
Kojto | 122:f9eeca106725 | 312 | * @arg MPU_HARDFAULT_NMI |
Kojto | 122:f9eeca106725 | 313 | * @arg MPU_PRIVILEGED_DEFAULT |
Kojto | 122:f9eeca106725 | 314 | * @arg MPU_HFNMI_PRIVDEF |
Kojto | 122:f9eeca106725 | 315 | * @retval None |
Kojto | 122:f9eeca106725 | 316 | */ |
Kojto | 122:f9eeca106725 | 317 | __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control) |
Kojto | 122:f9eeca106725 | 318 | { |
Kojto | 122:f9eeca106725 | 319 | /* Enable the MPU */ |
Kojto | 122:f9eeca106725 | 320 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; |
Kojto | 122:f9eeca106725 | 321 | |
Kojto | 122:f9eeca106725 | 322 | /* Enable fault exceptions */ |
Kojto | 122:f9eeca106725 | 323 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; |
Kojto | 122:f9eeca106725 | 324 | } |
Kojto | 122:f9eeca106725 | 325 | #endif /* __MPU_PRESENT */ |
Kojto | 122:f9eeca106725 | 326 | /** |
Kojto | 122:f9eeca106725 | 327 | * @} |
Kojto | 122:f9eeca106725 | 328 | */ |
Kojto | 122:f9eeca106725 | 329 | |
Kojto | 122:f9eeca106725 | 330 | /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions |
Kojto | 122:f9eeca106725 | 331 | * @brief Cortex control functions |
Kojto | 122:f9eeca106725 | 332 | * @{ |
Kojto | 122:f9eeca106725 | 333 | */ |
Kojto | 122:f9eeca106725 | 334 | /* Peripheral Control functions ***********************************************/ |
Kojto | 122:f9eeca106725 | 335 | uint32_t HAL_NVIC_GetPriorityGrouping(void); |
Kojto | 122:f9eeca106725 | 336 | void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); |
Kojto | 122:f9eeca106725 | 337 | uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); |
Kojto | 122:f9eeca106725 | 338 | void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); |
Kojto | 122:f9eeca106725 | 339 | void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); |
Kojto | 122:f9eeca106725 | 340 | uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); |
Kojto | 122:f9eeca106725 | 341 | void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); |
Kojto | 122:f9eeca106725 | 342 | void HAL_SYSTICK_IRQHandler(void); |
Kojto | 122:f9eeca106725 | 343 | void HAL_SYSTICK_Callback(void); |
Kojto | 122:f9eeca106725 | 344 | |
Kojto | 122:f9eeca106725 | 345 | #if (__MPU_PRESENT == 1) |
Kojto | 122:f9eeca106725 | 346 | void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); |
Kojto | 122:f9eeca106725 | 347 | #endif /* __MPU_PRESENT */ |
Kojto | 122:f9eeca106725 | 348 | /** |
Kojto | 122:f9eeca106725 | 349 | * @} |
Kojto | 122:f9eeca106725 | 350 | */ |
Kojto | 122:f9eeca106725 | 351 | |
Kojto | 122:f9eeca106725 | 352 | /** |
Kojto | 122:f9eeca106725 | 353 | * @} |
Kojto | 122:f9eeca106725 | 354 | */ |
Kojto | 122:f9eeca106725 | 355 | |
Kojto | 122:f9eeca106725 | 356 | /* Private types -------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 357 | /* Private variables ---------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 358 | /* Private constants ---------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 359 | /* Private macros ------------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 360 | /** @defgroup CORTEX_Private_Macros CORTEX Private Macros |
Kojto | 122:f9eeca106725 | 361 | * @{ |
Kojto | 122:f9eeca106725 | 362 | */ |
Kojto | 122:f9eeca106725 | 363 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ |
Kojto | 122:f9eeca106725 | 364 | ((GROUP) == NVIC_PRIORITYGROUP_1) || \ |
Kojto | 122:f9eeca106725 | 365 | ((GROUP) == NVIC_PRIORITYGROUP_2) || \ |
Kojto | 122:f9eeca106725 | 366 | ((GROUP) == NVIC_PRIORITYGROUP_3) || \ |
Kojto | 122:f9eeca106725 | 367 | ((GROUP) == NVIC_PRIORITYGROUP_4)) |
Kojto | 122:f9eeca106725 | 368 | |
Kojto | 122:f9eeca106725 | 369 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) |
Kojto | 122:f9eeca106725 | 370 | |
Kojto | 122:f9eeca106725 | 371 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) |
Kojto | 122:f9eeca106725 | 372 | |
Kojto | 122:f9eeca106725 | 373 | #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) |
Kojto | 122:f9eeca106725 | 374 | |
Kojto | 122:f9eeca106725 | 375 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ |
Kojto | 122:f9eeca106725 | 376 | ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) |
Kojto | 122:f9eeca106725 | 377 | |
Kojto | 122:f9eeca106725 | 378 | #if (__MPU_PRESENT == 1) |
Kojto | 122:f9eeca106725 | 379 | #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ |
Kojto | 122:f9eeca106725 | 380 | ((STATE) == MPU_REGION_DISABLE)) |
Kojto | 122:f9eeca106725 | 381 | |
Kojto | 122:f9eeca106725 | 382 | #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ |
Kojto | 122:f9eeca106725 | 383 | ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) |
Kojto | 122:f9eeca106725 | 384 | |
Kojto | 122:f9eeca106725 | 385 | #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ |
Kojto | 122:f9eeca106725 | 386 | ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) |
Kojto | 122:f9eeca106725 | 387 | |
Kojto | 122:f9eeca106725 | 388 | #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ |
Kojto | 122:f9eeca106725 | 389 | ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) |
Kojto | 122:f9eeca106725 | 390 | |
Kojto | 122:f9eeca106725 | 391 | #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ |
Kojto | 122:f9eeca106725 | 392 | ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) |
Kojto | 122:f9eeca106725 | 393 | |
Kojto | 122:f9eeca106725 | 394 | #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ |
Kojto | 122:f9eeca106725 | 395 | ((TYPE) == MPU_TEX_LEVEL1) || \ |
Kojto | 122:f9eeca106725 | 396 | ((TYPE) == MPU_TEX_LEVEL2)) |
Kojto | 122:f9eeca106725 | 397 | |
Kojto | 122:f9eeca106725 | 398 | #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ |
Kojto | 122:f9eeca106725 | 399 | ((TYPE) == MPU_REGION_PRIV_RW) || \ |
Kojto | 122:f9eeca106725 | 400 | ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ |
Kojto | 122:f9eeca106725 | 401 | ((TYPE) == MPU_REGION_FULL_ACCESS) || \ |
Kojto | 122:f9eeca106725 | 402 | ((TYPE) == MPU_REGION_PRIV_RO) || \ |
Kojto | 122:f9eeca106725 | 403 | ((TYPE) == MPU_REGION_PRIV_RO_URO)) |
Kojto | 122:f9eeca106725 | 404 | |
Kojto | 122:f9eeca106725 | 405 | #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ |
Kojto | 122:f9eeca106725 | 406 | ((NUMBER) == MPU_REGION_NUMBER1) || \ |
Kojto | 122:f9eeca106725 | 407 | ((NUMBER) == MPU_REGION_NUMBER2) || \ |
Kojto | 122:f9eeca106725 | 408 | ((NUMBER) == MPU_REGION_NUMBER3) || \ |
Kojto | 122:f9eeca106725 | 409 | ((NUMBER) == MPU_REGION_NUMBER4) || \ |
Kojto | 122:f9eeca106725 | 410 | ((NUMBER) == MPU_REGION_NUMBER5) || \ |
Kojto | 122:f9eeca106725 | 411 | ((NUMBER) == MPU_REGION_NUMBER6) || \ |
Kojto | 122:f9eeca106725 | 412 | ((NUMBER) == MPU_REGION_NUMBER7)) |
Kojto | 122:f9eeca106725 | 413 | |
Kojto | 122:f9eeca106725 | 414 | #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ |
Kojto | 122:f9eeca106725 | 415 | ((SIZE) == MPU_REGION_SIZE_64B) || \ |
Kojto | 122:f9eeca106725 | 416 | ((SIZE) == MPU_REGION_SIZE_128B) || \ |
Kojto | 122:f9eeca106725 | 417 | ((SIZE) == MPU_REGION_SIZE_256B) || \ |
Kojto | 122:f9eeca106725 | 418 | ((SIZE) == MPU_REGION_SIZE_512B) || \ |
Kojto | 122:f9eeca106725 | 419 | ((SIZE) == MPU_REGION_SIZE_1KB) || \ |
Kojto | 122:f9eeca106725 | 420 | ((SIZE) == MPU_REGION_SIZE_2KB) || \ |
Kojto | 122:f9eeca106725 | 421 | ((SIZE) == MPU_REGION_SIZE_4KB) || \ |
Kojto | 122:f9eeca106725 | 422 | ((SIZE) == MPU_REGION_SIZE_8KB) || \ |
Kojto | 122:f9eeca106725 | 423 | ((SIZE) == MPU_REGION_SIZE_16KB) || \ |
Kojto | 122:f9eeca106725 | 424 | ((SIZE) == MPU_REGION_SIZE_32KB) || \ |
Kojto | 122:f9eeca106725 | 425 | ((SIZE) == MPU_REGION_SIZE_64KB) || \ |
Kojto | 122:f9eeca106725 | 426 | ((SIZE) == MPU_REGION_SIZE_128KB) || \ |
Kojto | 122:f9eeca106725 | 427 | ((SIZE) == MPU_REGION_SIZE_256KB) || \ |
Kojto | 122:f9eeca106725 | 428 | ((SIZE) == MPU_REGION_SIZE_512KB) || \ |
Kojto | 122:f9eeca106725 | 429 | ((SIZE) == MPU_REGION_SIZE_1MB) || \ |
Kojto | 122:f9eeca106725 | 430 | ((SIZE) == MPU_REGION_SIZE_2MB) || \ |
Kojto | 122:f9eeca106725 | 431 | ((SIZE) == MPU_REGION_SIZE_4MB) || \ |
Kojto | 122:f9eeca106725 | 432 | ((SIZE) == MPU_REGION_SIZE_8MB) || \ |
Kojto | 122:f9eeca106725 | 433 | ((SIZE) == MPU_REGION_SIZE_16MB) || \ |
Kojto | 122:f9eeca106725 | 434 | ((SIZE) == MPU_REGION_SIZE_32MB) || \ |
Kojto | 122:f9eeca106725 | 435 | ((SIZE) == MPU_REGION_SIZE_64MB) || \ |
Kojto | 122:f9eeca106725 | 436 | ((SIZE) == MPU_REGION_SIZE_128MB) || \ |
Kojto | 122:f9eeca106725 | 437 | ((SIZE) == MPU_REGION_SIZE_256MB) || \ |
Kojto | 122:f9eeca106725 | 438 | ((SIZE) == MPU_REGION_SIZE_512MB) || \ |
Kojto | 122:f9eeca106725 | 439 | ((SIZE) == MPU_REGION_SIZE_1GB) || \ |
Kojto | 122:f9eeca106725 | 440 | ((SIZE) == MPU_REGION_SIZE_2GB) || \ |
Kojto | 122:f9eeca106725 | 441 | ((SIZE) == MPU_REGION_SIZE_4GB)) |
Kojto | 122:f9eeca106725 | 442 | |
Kojto | 122:f9eeca106725 | 443 | #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) |
Kojto | 122:f9eeca106725 | 444 | #endif /* __MPU_PRESENT */ |
Kojto | 122:f9eeca106725 | 445 | |
Kojto | 122:f9eeca106725 | 446 | /** |
Kojto | 122:f9eeca106725 | 447 | * @} |
Kojto | 122:f9eeca106725 | 448 | */ |
Kojto | 122:f9eeca106725 | 449 | |
Kojto | 122:f9eeca106725 | 450 | /* Private functions ---------------------------------------------------------*/ |
Kojto | 122:f9eeca106725 | 451 | |
Kojto | 122:f9eeca106725 | 452 | /** |
Kojto | 122:f9eeca106725 | 453 | * @} |
Kojto | 122:f9eeca106725 | 454 | */ |
Kojto | 122:f9eeca106725 | 455 | |
Kojto | 122:f9eeca106725 | 456 | /** |
Kojto | 122:f9eeca106725 | 457 | * @} |
Kojto | 122:f9eeca106725 | 458 | */ |
Kojto | 122:f9eeca106725 | 459 | |
Kojto | 122:f9eeca106725 | 460 | #ifdef __cplusplus |
Kojto | 122:f9eeca106725 | 461 | } |
Kojto | 122:f9eeca106725 | 462 | #endif |
Kojto | 122:f9eeca106725 | 463 | |
Kojto | 122:f9eeca106725 | 464 | #endif /* __STM32L4xx_HAL_CORTEX_H */ |
Kojto | 122:f9eeca106725 | 465 | |
Kojto | 122:f9eeca106725 | 466 | |
Kojto | 122:f9eeca106725 | 467 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |