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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_L486RG/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l486xx.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
136:ef9c61f8c49f
Child:
145:64910690c574
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l486xx.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @version V1.1.1
<> 128:9bcdf88f62b0 6 * @date 29-April-2016
<> 128:9bcdf88f62b0 7 * @brief CMSIS STM32L486xx Device Peripheral Access Layer Header File.
<> 128:9bcdf88f62b0 8 *
<> 128:9bcdf88f62b0 9 * This file contains:
<> 128:9bcdf88f62b0 10 * - Data structures and the address mapping for all peripherals
<> 128:9bcdf88f62b0 11 * - Peripheral's registers declarations and bits definition
<> 128:9bcdf88f62b0 12 * - Macros to access peripheral’s registers hardware
<> 128:9bcdf88f62b0 13 *
<> 128:9bcdf88f62b0 14 ******************************************************************************
<> 128:9bcdf88f62b0 15 * @attention
<> 128:9bcdf88f62b0 16 *
<> 128:9bcdf88f62b0 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 18 *
<> 128:9bcdf88f62b0 19 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 20 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 21 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 22 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 24 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 25 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 27 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 28 * without specific prior written permission.
<> 128:9bcdf88f62b0 29 *
<> 128:9bcdf88f62b0 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 40 *
<> 128:9bcdf88f62b0 41 ******************************************************************************
<> 128:9bcdf88f62b0 42 */
<> 128:9bcdf88f62b0 43
<> 128:9bcdf88f62b0 44 /** @addtogroup CMSIS_Device
<> 128:9bcdf88f62b0 45 * @{
<> 128:9bcdf88f62b0 46 */
<> 128:9bcdf88f62b0 47
<> 128:9bcdf88f62b0 48 /** @addtogroup stm32l486xx
<> 128:9bcdf88f62b0 49 * @{
<> 128:9bcdf88f62b0 50 */
<> 128:9bcdf88f62b0 51
<> 128:9bcdf88f62b0 52 #ifndef __STM32L486xx_H
<> 128:9bcdf88f62b0 53 #define __STM32L486xx_H
<> 128:9bcdf88f62b0 54
<> 128:9bcdf88f62b0 55 #ifdef __cplusplus
<> 128:9bcdf88f62b0 56 extern "C" {
<> 128:9bcdf88f62b0 57 #endif /* __cplusplus */
<> 128:9bcdf88f62b0 58
<> 128:9bcdf88f62b0 59 /** @addtogroup Configuration_section_for_CMSIS
<> 128:9bcdf88f62b0 60 * @{
<> 128:9bcdf88f62b0 61 */
<> 128:9bcdf88f62b0 62
<> 128:9bcdf88f62b0 63 /**
<> 128:9bcdf88f62b0 64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
<> 128:9bcdf88f62b0 65 */
<> 128:9bcdf88f62b0 66 #define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
<> 128:9bcdf88f62b0 67 #define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
<> 128:9bcdf88f62b0 68 #define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
<> 128:9bcdf88f62b0 69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
<> 128:9bcdf88f62b0 70 #define __FPU_PRESENT 1 /*!< FPU present */
<> 128:9bcdf88f62b0 71
<> 128:9bcdf88f62b0 72 /**
<> 128:9bcdf88f62b0 73 * @}
<> 128:9bcdf88f62b0 74 */
<> 128:9bcdf88f62b0 75
<> 128:9bcdf88f62b0 76 /** @addtogroup Peripheral_interrupt_number_definition
<> 128:9bcdf88f62b0 77 * @{
<> 128:9bcdf88f62b0 78 */
<> 128:9bcdf88f62b0 79
<> 128:9bcdf88f62b0 80 /**
<> 128:9bcdf88f62b0 81 * @brief STM32L4XX Interrupt Number Definition, according to the selected device
<> 128:9bcdf88f62b0 82 * in @ref Library_configuration_section
<> 128:9bcdf88f62b0 83 */
<> 128:9bcdf88f62b0 84 typedef enum
<> 128:9bcdf88f62b0 85 {
<> 128:9bcdf88f62b0 86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
<> 128:9bcdf88f62b0 87 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
<> 128:9bcdf88f62b0 88 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
<> 128:9bcdf88f62b0 89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
<> 128:9bcdf88f62b0 90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
<> 128:9bcdf88f62b0 91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
<> 128:9bcdf88f62b0 92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
<> 128:9bcdf88f62b0 93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
<> 128:9bcdf88f62b0 94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
<> 128:9bcdf88f62b0 95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
<> 128:9bcdf88f62b0 96 /****** STM32 specific Interrupt Numbers **********************************************************************/
<> 128:9bcdf88f62b0 97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
<> 128:9bcdf88f62b0 98 PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
<> 128:9bcdf88f62b0 99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
<> 128:9bcdf88f62b0 100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
<> 128:9bcdf88f62b0 101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
<> 128:9bcdf88f62b0 102 RCC_IRQn = 5, /*!< RCC global Interrupt */
<> 128:9bcdf88f62b0 103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
<> 128:9bcdf88f62b0 104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
<> 128:9bcdf88f62b0 105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
<> 128:9bcdf88f62b0 106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
<> 128:9bcdf88f62b0 107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
<> 128:9bcdf88f62b0 108 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
<> 128:9bcdf88f62b0 109 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
<> 128:9bcdf88f62b0 110 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
<> 128:9bcdf88f62b0 111 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
<> 128:9bcdf88f62b0 112 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
<> 128:9bcdf88f62b0 113 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
<> 128:9bcdf88f62b0 114 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
<> 128:9bcdf88f62b0 115 ADC1_2_IRQn = 18, /*!< ADC1, ADC2 SAR global Interrupts */
<> 128:9bcdf88f62b0 116 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
<> 128:9bcdf88f62b0 117 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
<> 128:9bcdf88f62b0 118 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
<> 128:9bcdf88f62b0 119 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
<> 128:9bcdf88f62b0 120 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
<> 128:9bcdf88f62b0 121 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */
<> 128:9bcdf88f62b0 122 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
<> 128:9bcdf88f62b0 123 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
<> 128:9bcdf88f62b0 124 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
<> 128:9bcdf88f62b0 125 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
<> 128:9bcdf88f62b0 126 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
<> 128:9bcdf88f62b0 127 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
<> 128:9bcdf88f62b0 128 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
<> 128:9bcdf88f62b0 129 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
<> 128:9bcdf88f62b0 130 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
<> 128:9bcdf88f62b0 131 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
<> 128:9bcdf88f62b0 132 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
<> 128:9bcdf88f62b0 133 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
<> 128:9bcdf88f62b0 134 USART1_IRQn = 37, /*!< USART1 global Interrupt */
<> 128:9bcdf88f62b0 135 USART2_IRQn = 38, /*!< USART2 global Interrupt */
<> 128:9bcdf88f62b0 136 USART3_IRQn = 39, /*!< USART3 global Interrupt */
<> 128:9bcdf88f62b0 137 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
<> 128:9bcdf88f62b0 138 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
<> 128:9bcdf88f62b0 139 DFSDM1_FLT3_IRQn = 42, /*!< DFSDM1 Filter 3 global Interrupt */
<> 128:9bcdf88f62b0 140 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
<> 128:9bcdf88f62b0 141 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
<> 128:9bcdf88f62b0 142 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
<> 128:9bcdf88f62b0 143 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
<> 128:9bcdf88f62b0 144 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
<> 128:9bcdf88f62b0 145 FMC_IRQn = 48, /*!< FMC global Interrupt */
<> 128:9bcdf88f62b0 146 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
<> 128:9bcdf88f62b0 147 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
<> 128:9bcdf88f62b0 148 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
<> 128:9bcdf88f62b0 149 UART4_IRQn = 52, /*!< UART4 global Interrupt */
<> 128:9bcdf88f62b0 150 UART5_IRQn = 53, /*!< UART5 global Interrupt */
<> 128:9bcdf88f62b0 151 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
<> 128:9bcdf88f62b0 152 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
<> 128:9bcdf88f62b0 153 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
<> 128:9bcdf88f62b0 154 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
<> 128:9bcdf88f62b0 155 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
<> 128:9bcdf88f62b0 156 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
<> 128:9bcdf88f62b0 157 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
<> 128:9bcdf88f62b0 158 DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
<> 128:9bcdf88f62b0 159 DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
<> 128:9bcdf88f62b0 160 DFSDM1_FLT2_IRQn = 63, /*!< DFSDM1 Filter 2 global Interrupt */
<> 128:9bcdf88f62b0 161 COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */
<> 128:9bcdf88f62b0 162 LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */
<> 128:9bcdf88f62b0 163 LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */
<> 128:9bcdf88f62b0 164 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
<> 128:9bcdf88f62b0 165 DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */
<> 128:9bcdf88f62b0 166 DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */
<> 128:9bcdf88f62b0 167 LPUART1_IRQn = 70, /*!< LP UART1 interrupt */
<> 128:9bcdf88f62b0 168 QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */
<> 128:9bcdf88f62b0 169 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
<> 128:9bcdf88f62b0 170 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
<> 128:9bcdf88f62b0 171 SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */
<> 128:9bcdf88f62b0 172 SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */
<> 128:9bcdf88f62b0 173 SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */
<> 128:9bcdf88f62b0 174 TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */
<> 128:9bcdf88f62b0 175 LCD_IRQn = 78, /*!< LCD global interrupt */
<> 128:9bcdf88f62b0 176 AES_IRQn = 79, /*!< AES global interrupt */
<> 128:9bcdf88f62b0 177 RNG_IRQn = 80, /*!< RNG global interrupt */
<> 128:9bcdf88f62b0 178 FPU_IRQn = 81 /*!< FPU global interrupt */
<> 128:9bcdf88f62b0 179 } IRQn_Type;
<> 128:9bcdf88f62b0 180
<> 128:9bcdf88f62b0 181 /**
<> 128:9bcdf88f62b0 182 * @}
<> 128:9bcdf88f62b0 183 */
<> 128:9bcdf88f62b0 184
<> 128:9bcdf88f62b0 185 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
<> 128:9bcdf88f62b0 186 #include "system_stm32l4xx.h"
<> 128:9bcdf88f62b0 187 #include <stdint.h>
<> 128:9bcdf88f62b0 188
<> 128:9bcdf88f62b0 189 /** @addtogroup Peripheral_registers_structures
<> 128:9bcdf88f62b0 190 * @{
<> 128:9bcdf88f62b0 191 */
<> 128:9bcdf88f62b0 192
<> 128:9bcdf88f62b0 193 /**
<> 128:9bcdf88f62b0 194 * @brief Analog to Digital Converter
<> 128:9bcdf88f62b0 195 */
<> 128:9bcdf88f62b0 196
<> 128:9bcdf88f62b0 197 typedef struct
<> 128:9bcdf88f62b0 198 {
<> 128:9bcdf88f62b0 199 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 200 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 201 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 202 __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
<> 128:9bcdf88f62b0 203 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
<> 128:9bcdf88f62b0 204 __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
<> 128:9bcdf88f62b0 205 __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
<> 128:9bcdf88f62b0 206 uint32_t RESERVED1; /*!< Reserved, 0x1C */
<> 128:9bcdf88f62b0 207 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 208 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 209 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
<> 128:9bcdf88f62b0 210 uint32_t RESERVED2; /*!< Reserved, 0x2C */
<> 128:9bcdf88f62b0 211 __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
<> 128:9bcdf88f62b0 212 __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
<> 128:9bcdf88f62b0 213 __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
<> 128:9bcdf88f62b0 214 __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
<> 128:9bcdf88f62b0 215 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
<> 128:9bcdf88f62b0 216 uint32_t RESERVED3; /*!< Reserved, 0x44 */
<> 128:9bcdf88f62b0 217 uint32_t RESERVED4; /*!< Reserved, 0x48 */
<> 128:9bcdf88f62b0 218 __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
<> 128:9bcdf88f62b0 219 uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
<> 128:9bcdf88f62b0 220 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
<> 128:9bcdf88f62b0 221 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
<> 128:9bcdf88f62b0 222 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
<> 128:9bcdf88f62b0 223 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
<> 128:9bcdf88f62b0 224 uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
<> 128:9bcdf88f62b0 225 __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
<> 128:9bcdf88f62b0 226 __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
<> 128:9bcdf88f62b0 227 __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
<> 128:9bcdf88f62b0 228 __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
<> 128:9bcdf88f62b0 229 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
<> 128:9bcdf88f62b0 230 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
<> 128:9bcdf88f62b0 231 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
<> 128:9bcdf88f62b0 232 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
<> 128:9bcdf88f62b0 233 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
<> 128:9bcdf88f62b0 234 __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
<> 128:9bcdf88f62b0 235 __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
<> 128:9bcdf88f62b0 236
<> 128:9bcdf88f62b0 237 } ADC_TypeDef;
<> 128:9bcdf88f62b0 238
<> 128:9bcdf88f62b0 239 typedef struct
<> 128:9bcdf88f62b0 240 {
<> 128:9bcdf88f62b0 241 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
<> 128:9bcdf88f62b0 242 uint32_t RESERVED; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
<> 128:9bcdf88f62b0 243 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
<> 128:9bcdf88f62b0 244 __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: ADC1 base address + 0x30C */
<> 128:9bcdf88f62b0 245 } ADC_Common_TypeDef;
<> 128:9bcdf88f62b0 246
<> 128:9bcdf88f62b0 247
<> 128:9bcdf88f62b0 248 /**
<> 128:9bcdf88f62b0 249 * @brief Controller Area Network TxMailBox
<> 128:9bcdf88f62b0 250 */
<> 128:9bcdf88f62b0 251
<> 128:9bcdf88f62b0 252 typedef struct
<> 128:9bcdf88f62b0 253 {
<> 128:9bcdf88f62b0 254 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
<> 128:9bcdf88f62b0 255 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
<> 128:9bcdf88f62b0 256 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
<> 128:9bcdf88f62b0 257 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
<> 128:9bcdf88f62b0 258 } CAN_TxMailBox_TypeDef;
<> 128:9bcdf88f62b0 259
<> 128:9bcdf88f62b0 260 /**
<> 128:9bcdf88f62b0 261 * @brief Controller Area Network FIFOMailBox
<> 128:9bcdf88f62b0 262 */
<> 128:9bcdf88f62b0 263
<> 128:9bcdf88f62b0 264 typedef struct
<> 128:9bcdf88f62b0 265 {
<> 128:9bcdf88f62b0 266 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
<> 128:9bcdf88f62b0 267 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
<> 128:9bcdf88f62b0 268 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
<> 128:9bcdf88f62b0 269 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
<> 128:9bcdf88f62b0 270 } CAN_FIFOMailBox_TypeDef;
<> 128:9bcdf88f62b0 271
<> 128:9bcdf88f62b0 272 /**
<> 128:9bcdf88f62b0 273 * @brief Controller Area Network FilterRegister
<> 128:9bcdf88f62b0 274 */
<> 128:9bcdf88f62b0 275
<> 128:9bcdf88f62b0 276 typedef struct
<> 128:9bcdf88f62b0 277 {
<> 128:9bcdf88f62b0 278 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
<> 128:9bcdf88f62b0 279 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
<> 128:9bcdf88f62b0 280 } CAN_FilterRegister_TypeDef;
<> 128:9bcdf88f62b0 281
<> 128:9bcdf88f62b0 282 /**
<> 128:9bcdf88f62b0 283 * @brief Controller Area Network
<> 128:9bcdf88f62b0 284 */
<> 128:9bcdf88f62b0 285
<> 128:9bcdf88f62b0 286 typedef struct
<> 128:9bcdf88f62b0 287 {
<> 128:9bcdf88f62b0 288 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 289 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 290 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 291 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 292 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 293 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 294 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 295 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
<> 128:9bcdf88f62b0 296 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
<> 128:9bcdf88f62b0 297 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
<> 128:9bcdf88f62b0 298 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
<> 128:9bcdf88f62b0 299 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
<> 128:9bcdf88f62b0 300 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
<> 128:9bcdf88f62b0 301 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
<> 128:9bcdf88f62b0 302 uint32_t RESERVED2; /*!< Reserved, 0x208 */
<> 128:9bcdf88f62b0 303 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
<> 128:9bcdf88f62b0 304 uint32_t RESERVED3; /*!< Reserved, 0x210 */
<> 128:9bcdf88f62b0 305 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
<> 128:9bcdf88f62b0 306 uint32_t RESERVED4; /*!< Reserved, 0x218 */
<> 128:9bcdf88f62b0 307 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
<> 128:9bcdf88f62b0 308 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
<> 128:9bcdf88f62b0 309 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
<> 128:9bcdf88f62b0 310 } CAN_TypeDef;
<> 128:9bcdf88f62b0 311
<> 128:9bcdf88f62b0 312
<> 128:9bcdf88f62b0 313 /**
<> 128:9bcdf88f62b0 314 * @brief Comparator
<> 128:9bcdf88f62b0 315 */
<> 128:9bcdf88f62b0 316
<> 128:9bcdf88f62b0 317 typedef struct
<> 128:9bcdf88f62b0 318 {
<> 128:9bcdf88f62b0 319 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 320 } COMP_TypeDef;
<> 128:9bcdf88f62b0 321
<> 128:9bcdf88f62b0 322 typedef struct
<> 128:9bcdf88f62b0 323 {
<> 128:9bcdf88f62b0 324 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
<> 128:9bcdf88f62b0 325 } COMP_Common_TypeDef;
<> 128:9bcdf88f62b0 326
<> 128:9bcdf88f62b0 327 /**
<> 128:9bcdf88f62b0 328 * @brief CRC calculation unit
<> 128:9bcdf88f62b0 329 */
<> 128:9bcdf88f62b0 330
<> 128:9bcdf88f62b0 331 typedef struct
<> 128:9bcdf88f62b0 332 {
<> 128:9bcdf88f62b0 333 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 334 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 335 uint8_t RESERVED0; /*!< Reserved, 0x05 */
<> 128:9bcdf88f62b0 336 uint16_t RESERVED1; /*!< Reserved, 0x06 */
<> 128:9bcdf88f62b0 337 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 338 uint32_t RESERVED2; /*!< Reserved, 0x0C */
<> 128:9bcdf88f62b0 339 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 340 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 341 } CRC_TypeDef;
<> 128:9bcdf88f62b0 342
<> 128:9bcdf88f62b0 343 /**
<> 128:9bcdf88f62b0 344 * @brief Digital to Analog Converter
<> 128:9bcdf88f62b0 345 */
<> 128:9bcdf88f62b0 346
<> 128:9bcdf88f62b0 347 typedef struct
<> 128:9bcdf88f62b0 348 {
<> 128:9bcdf88f62b0 349 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 350 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 351 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 352 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 353 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 354 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 355 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 356 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
<> 128:9bcdf88f62b0 357 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 358 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 359 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
<> 128:9bcdf88f62b0 360 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
<> 128:9bcdf88f62b0 361 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
<> 128:9bcdf88f62b0 362 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
<> 128:9bcdf88f62b0 363 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
<> 128:9bcdf88f62b0 364 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
<> 128:9bcdf88f62b0 365 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
<> 128:9bcdf88f62b0 366 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
<> 128:9bcdf88f62b0 367 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
<> 128:9bcdf88f62b0 368 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
<> 128:9bcdf88f62b0 369 } DAC_TypeDef;
<> 128:9bcdf88f62b0 370
<> 128:9bcdf88f62b0 371 /**
<> 128:9bcdf88f62b0 372 * @brief DFSDM module registers
<> 128:9bcdf88f62b0 373 */
<> 128:9bcdf88f62b0 374 typedef struct
<> 128:9bcdf88f62b0 375 {
<> 128:9bcdf88f62b0 376 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
<> 128:9bcdf88f62b0 377 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
<> 128:9bcdf88f62b0 378 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
<> 128:9bcdf88f62b0 379 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
<> 128:9bcdf88f62b0 380 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
<> 128:9bcdf88f62b0 381 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
<> 128:9bcdf88f62b0 382 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
<> 128:9bcdf88f62b0 383 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
<> 128:9bcdf88f62b0 384 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
<> 128:9bcdf88f62b0 385 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
<> 128:9bcdf88f62b0 386 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
<> 128:9bcdf88f62b0 387 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
<> 128:9bcdf88f62b0 388 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
<> 128:9bcdf88f62b0 389 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
<> 128:9bcdf88f62b0 390 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
<> 128:9bcdf88f62b0 391 } DFSDM_Filter_TypeDef;
<> 128:9bcdf88f62b0 392
<> 128:9bcdf88f62b0 393 /**
<> 128:9bcdf88f62b0 394 * @brief DFSDM channel configuration registers
<> 128:9bcdf88f62b0 395 */
<> 128:9bcdf88f62b0 396 typedef struct
<> 128:9bcdf88f62b0 397 {
<> 128:9bcdf88f62b0 398 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
<> 128:9bcdf88f62b0 399 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
<> 128:9bcdf88f62b0 400 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
<> 128:9bcdf88f62b0 401 short circuit detector register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 402 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 403 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 404 } DFSDM_Channel_TypeDef;
<> 128:9bcdf88f62b0 405
<> 128:9bcdf88f62b0 406 /**
<> 128:9bcdf88f62b0 407 * @brief Debug MCU
<> 128:9bcdf88f62b0 408 */
<> 128:9bcdf88f62b0 409
<> 128:9bcdf88f62b0 410 typedef struct
<> 128:9bcdf88f62b0 411 {
<> 128:9bcdf88f62b0 412 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
<> 128:9bcdf88f62b0 413 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 414 __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
<> 128:9bcdf88f62b0 415 __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
<> 128:9bcdf88f62b0 416 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 417 } DBGMCU_TypeDef;
<> 128:9bcdf88f62b0 418
<> 128:9bcdf88f62b0 419
<> 128:9bcdf88f62b0 420 /**
<> 128:9bcdf88f62b0 421 * @brief DMA Controller
<> 128:9bcdf88f62b0 422 */
<> 128:9bcdf88f62b0 423
<> 128:9bcdf88f62b0 424 typedef struct
<> 128:9bcdf88f62b0 425 {
<> 128:9bcdf88f62b0 426 __IO uint32_t CCR; /*!< DMA channel x configuration register */
<> 128:9bcdf88f62b0 427 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
<> 128:9bcdf88f62b0 428 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
<> 128:9bcdf88f62b0 429 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
<> 128:9bcdf88f62b0 430 } DMA_Channel_TypeDef;
<> 128:9bcdf88f62b0 431
<> 128:9bcdf88f62b0 432 typedef struct
<> 128:9bcdf88f62b0 433 {
<> 128:9bcdf88f62b0 434 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 435 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 436 } DMA_TypeDef;
<> 128:9bcdf88f62b0 437
<> 128:9bcdf88f62b0 438 typedef struct
<> 128:9bcdf88f62b0 439 {
<> 128:9bcdf88f62b0 440 __IO uint32_t CSELR; /*!< DMA channel selection register */
<> 128:9bcdf88f62b0 441 } DMA_Request_TypeDef;
<> 128:9bcdf88f62b0 442
<> 128:9bcdf88f62b0 443 /* Legacy define */
<> 128:9bcdf88f62b0 444 #define DMA_request_TypeDef DMA_Request_TypeDef
<> 128:9bcdf88f62b0 445
<> 128:9bcdf88f62b0 446
<> 128:9bcdf88f62b0 447 /**
<> 128:9bcdf88f62b0 448 * @brief External Interrupt/Event Controller
<> 128:9bcdf88f62b0 449 */
<> 128:9bcdf88f62b0 450
<> 128:9bcdf88f62b0 451 typedef struct
<> 128:9bcdf88f62b0 452 {
<> 128:9bcdf88f62b0 453 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
<> 128:9bcdf88f62b0 454 __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
<> 128:9bcdf88f62b0 455 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
<> 128:9bcdf88f62b0 456 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
<> 128:9bcdf88f62b0 457 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
<> 128:9bcdf88f62b0 458 __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
<> 128:9bcdf88f62b0 459 uint32_t RESERVED1; /*!< Reserved, 0x18 */
<> 128:9bcdf88f62b0 460 uint32_t RESERVED2; /*!< Reserved, 0x1C */
<> 128:9bcdf88f62b0 461 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
<> 128:9bcdf88f62b0 462 __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
<> 128:9bcdf88f62b0 463 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
<> 128:9bcdf88f62b0 464 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
<> 128:9bcdf88f62b0 465 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
<> 128:9bcdf88f62b0 466 __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
<> 128:9bcdf88f62b0 467 } EXTI_TypeDef;
<> 128:9bcdf88f62b0 468
<> 128:9bcdf88f62b0 469
<> 128:9bcdf88f62b0 470 /**
<> 128:9bcdf88f62b0 471 * @brief Firewall
<> 128:9bcdf88f62b0 472 */
<> 128:9bcdf88f62b0 473
<> 128:9bcdf88f62b0 474 typedef struct
<> 128:9bcdf88f62b0 475 {
<> 128:9bcdf88f62b0 476 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 477 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 478 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 479 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 480 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 481 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 482 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */
<> 128:9bcdf88f62b0 483 uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
<> 128:9bcdf88f62b0 484 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 485 } FIREWALL_TypeDef;
<> 128:9bcdf88f62b0 486
<> 128:9bcdf88f62b0 487
<> 128:9bcdf88f62b0 488 /**
<> 128:9bcdf88f62b0 489 * @brief FLASH Registers
<> 128:9bcdf88f62b0 490 */
<> 128:9bcdf88f62b0 491
<> 128:9bcdf88f62b0 492 typedef struct
<> 128:9bcdf88f62b0 493 {
<> 128:9bcdf88f62b0 494 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 495 __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 496 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 497 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 498 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 499 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 500 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 501 __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
<> 128:9bcdf88f62b0 502 __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 503 __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 504 __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
<> 128:9bcdf88f62b0 505 __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
<> 128:9bcdf88f62b0 506 __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
<> 128:9bcdf88f62b0 507 uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */
<> 128:9bcdf88f62b0 508 __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
<> 128:9bcdf88f62b0 509 __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
<> 128:9bcdf88f62b0 510 __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
<> 128:9bcdf88f62b0 511 __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */
<> 128:9bcdf88f62b0 512 } FLASH_TypeDef;
<> 128:9bcdf88f62b0 513
<> 128:9bcdf88f62b0 514
<> 128:9bcdf88f62b0 515 /**
<> 128:9bcdf88f62b0 516 * @brief Flexible Memory Controller
<> 128:9bcdf88f62b0 517 */
<> 128:9bcdf88f62b0 518
<> 128:9bcdf88f62b0 519 typedef struct
<> 128:9bcdf88f62b0 520 {
<> 128:9bcdf88f62b0 521 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
<> 128:9bcdf88f62b0 522 } FMC_Bank1_TypeDef;
<> 128:9bcdf88f62b0 523
<> 128:9bcdf88f62b0 524 /**
<> 128:9bcdf88f62b0 525 * @brief Flexible Memory Controller Bank1E
<> 128:9bcdf88f62b0 526 */
<> 128:9bcdf88f62b0 527
<> 128:9bcdf88f62b0 528 typedef struct
<> 128:9bcdf88f62b0 529 {
<> 128:9bcdf88f62b0 530 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
<> 128:9bcdf88f62b0 531 } FMC_Bank1E_TypeDef;
<> 128:9bcdf88f62b0 532
<> 128:9bcdf88f62b0 533 /**
<> 128:9bcdf88f62b0 534 * @brief Flexible Memory Controller Bank3
<> 128:9bcdf88f62b0 535 */
<> 128:9bcdf88f62b0 536
<> 128:9bcdf88f62b0 537 typedef struct
<> 128:9bcdf88f62b0 538 {
<> 128:9bcdf88f62b0 539 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
<> 128:9bcdf88f62b0 540 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
<> 128:9bcdf88f62b0 541 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
<> 128:9bcdf88f62b0 542 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
<> 128:9bcdf88f62b0 543 uint32_t RESERVED0; /*!< Reserved, 0x90 */
<> 128:9bcdf88f62b0 544 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
<> 128:9bcdf88f62b0 545 } FMC_Bank3_TypeDef;
<> 128:9bcdf88f62b0 546
<> 128:9bcdf88f62b0 547 /**
<> 128:9bcdf88f62b0 548 * @brief General Purpose I/O
<> 128:9bcdf88f62b0 549 */
<> 128:9bcdf88f62b0 550
<> 128:9bcdf88f62b0 551 typedef struct
<> 128:9bcdf88f62b0 552 {
<> 128:9bcdf88f62b0 553 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 554 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 555 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 556 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 557 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 558 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 559 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 560 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
<> 128:9bcdf88f62b0 561 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
<> 128:9bcdf88f62b0 562 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
<> 128:9bcdf88f62b0 563 __IO uint32_t ASCR; /*!< GPIO analog switch control register, Address offset: 0x2C */
<> 128:9bcdf88f62b0 564
<> 128:9bcdf88f62b0 565 } GPIO_TypeDef;
<> 128:9bcdf88f62b0 566
<> 128:9bcdf88f62b0 567
<> 128:9bcdf88f62b0 568 /**
<> 128:9bcdf88f62b0 569 * @brief Inter-integrated Circuit Interface
<> 128:9bcdf88f62b0 570 */
<> 128:9bcdf88f62b0 571
<> 128:9bcdf88f62b0 572 typedef struct
<> 128:9bcdf88f62b0 573 {
<> 128:9bcdf88f62b0 574 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
<> 128:9bcdf88f62b0 575 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
<> 128:9bcdf88f62b0 576 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 577 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 578 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 579 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 580 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 581 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
<> 128:9bcdf88f62b0 582 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 583 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 584 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
<> 128:9bcdf88f62b0 585 } I2C_TypeDef;
<> 128:9bcdf88f62b0 586
<> 128:9bcdf88f62b0 587 /**
<> 128:9bcdf88f62b0 588 * @brief Independent WATCHDOG
<> 128:9bcdf88f62b0 589 */
<> 128:9bcdf88f62b0 590
<> 128:9bcdf88f62b0 591 typedef struct
<> 128:9bcdf88f62b0 592 {
<> 128:9bcdf88f62b0 593 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 594 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 595 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 596 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 597 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 598 } IWDG_TypeDef;
<> 128:9bcdf88f62b0 599
<> 128:9bcdf88f62b0 600 /**
<> 128:9bcdf88f62b0 601 * @brief LCD
<> 128:9bcdf88f62b0 602 */
<> 128:9bcdf88f62b0 603
<> 128:9bcdf88f62b0 604 typedef struct
<> 128:9bcdf88f62b0 605 {
<> 128:9bcdf88f62b0 606 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 607 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 608 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 609 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 610 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
<> 128:9bcdf88f62b0 611 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
<> 128:9bcdf88f62b0 612 } LCD_TypeDef;
<> 128:9bcdf88f62b0 613
<> 128:9bcdf88f62b0 614 /**
<> 128:9bcdf88f62b0 615 * @brief LPTIMER
<> 128:9bcdf88f62b0 616 */
<> 128:9bcdf88f62b0 617 typedef struct
<> 128:9bcdf88f62b0 618 {
<> 128:9bcdf88f62b0 619 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 620 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 621 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 622 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 623 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 624 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 625 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 626 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
<> 128:9bcdf88f62b0 627 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 628 } LPTIM_TypeDef;
<> 128:9bcdf88f62b0 629
<> 128:9bcdf88f62b0 630 /**
<> 128:9bcdf88f62b0 631 * @brief Operational Amplifier (OPAMP)
<> 128:9bcdf88f62b0 632 */
<> 128:9bcdf88f62b0 633
<> 128:9bcdf88f62b0 634 typedef struct
<> 128:9bcdf88f62b0 635 {
<> 128:9bcdf88f62b0 636 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 637 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
<> 128:9bcdf88f62b0 638 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
<> 128:9bcdf88f62b0 639 } OPAMP_TypeDef;
<> 128:9bcdf88f62b0 640
<> 128:9bcdf88f62b0 641 typedef struct
<> 128:9bcdf88f62b0 642 {
<> 128:9bcdf88f62b0 643 __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
<> 128:9bcdf88f62b0 644 } OPAMP_Common_TypeDef;
<> 128:9bcdf88f62b0 645
<> 128:9bcdf88f62b0 646 /**
<> 128:9bcdf88f62b0 647 * @brief Power Control
<> 128:9bcdf88f62b0 648 */
<> 128:9bcdf88f62b0 649
<> 128:9bcdf88f62b0 650 typedef struct
<> 128:9bcdf88f62b0 651 {
<> 128:9bcdf88f62b0 652 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
<> 128:9bcdf88f62b0 653 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
<> 128:9bcdf88f62b0 654 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
<> 128:9bcdf88f62b0 655 __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
<> 128:9bcdf88f62b0 656 __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
<> 128:9bcdf88f62b0 657 __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
<> 128:9bcdf88f62b0 658 __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 659 uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
<> 128:9bcdf88f62b0 660 __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
<> 128:9bcdf88f62b0 661 __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
<> 128:9bcdf88f62b0 662 __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
<> 128:9bcdf88f62b0 663 __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
<> 128:9bcdf88f62b0 664 __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
<> 128:9bcdf88f62b0 665 __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
<> 128:9bcdf88f62b0 666 __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
<> 128:9bcdf88f62b0 667 __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
<> 128:9bcdf88f62b0 668 __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
<> 128:9bcdf88f62b0 669 __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
<> 128:9bcdf88f62b0 670 __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
<> 128:9bcdf88f62b0 671 __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
<> 128:9bcdf88f62b0 672 __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
<> 128:9bcdf88f62b0 673 __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
<> 128:9bcdf88f62b0 674 __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */
<> 128:9bcdf88f62b0 675 __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
<> 128:9bcdf88f62b0 676 } PWR_TypeDef;
<> 128:9bcdf88f62b0 677
<> 128:9bcdf88f62b0 678
<> 128:9bcdf88f62b0 679 /**
<> 128:9bcdf88f62b0 680 * @brief QUAD Serial Peripheral Interface
<> 128:9bcdf88f62b0 681 */
<> 128:9bcdf88f62b0 682
<> 128:9bcdf88f62b0 683 typedef struct
<> 128:9bcdf88f62b0 684 {
<> 128:9bcdf88f62b0 685 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 686 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 687 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 688 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 689 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 690 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 691 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 692 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
<> 128:9bcdf88f62b0 693 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 694 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 695 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
<> 128:9bcdf88f62b0 696 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
<> 128:9bcdf88f62b0 697 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
<> 128:9bcdf88f62b0 698 } QUADSPI_TypeDef;
<> 128:9bcdf88f62b0 699
<> 128:9bcdf88f62b0 700
<> 128:9bcdf88f62b0 701 /**
<> 128:9bcdf88f62b0 702 * @brief Reset and Clock Control
<> 128:9bcdf88f62b0 703 */
<> 128:9bcdf88f62b0 704
<> 128:9bcdf88f62b0 705 typedef struct
<> 128:9bcdf88f62b0 706 {
<> 128:9bcdf88f62b0 707 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 708 __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 709 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 710 __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 711 __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 712 __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 713 __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 714 __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
<> 128:9bcdf88f62b0 715 __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 716 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */
<> 128:9bcdf88f62b0 717 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
<> 128:9bcdf88f62b0 718 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
<> 128:9bcdf88f62b0 719 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
<> 128:9bcdf88f62b0 720 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
<> 128:9bcdf88f62b0 721 __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
<> 128:9bcdf88f62b0 722 __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
<> 128:9bcdf88f62b0 723 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
<> 128:9bcdf88f62b0 724 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */
<> 128:9bcdf88f62b0 725 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
<> 128:9bcdf88f62b0 726 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
<> 128:9bcdf88f62b0 727 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
<> 128:9bcdf88f62b0 728 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */
<> 128:9bcdf88f62b0 729 __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
<> 128:9bcdf88f62b0 730 __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
<> 128:9bcdf88f62b0 731 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
<> 128:9bcdf88f62b0 732 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */
<> 128:9bcdf88f62b0 733 __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
<> 128:9bcdf88f62b0 734 __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
<> 128:9bcdf88f62b0 735 __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
<> 128:9bcdf88f62b0 736 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */
<> 128:9bcdf88f62b0 737 __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
<> 128:9bcdf88f62b0 738 __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
<> 128:9bcdf88f62b0 739 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
<> 128:9bcdf88f62b0 740 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */
<> 128:9bcdf88f62b0 741 __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
<> 128:9bcdf88f62b0 742 __IO uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */
<> 128:9bcdf88f62b0 743 __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
<> 128:9bcdf88f62b0 744 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
<> 128:9bcdf88f62b0 745 } RCC_TypeDef;
<> 128:9bcdf88f62b0 746
<> 128:9bcdf88f62b0 747 /**
<> 128:9bcdf88f62b0 748 * @brief Real-Time Clock
<> 128:9bcdf88f62b0 749 */
<> 128:9bcdf88f62b0 750
<> 128:9bcdf88f62b0 751 typedef struct
<> 128:9bcdf88f62b0 752 {
<> 128:9bcdf88f62b0 753 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 754 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 755 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 756 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 757 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 758 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 759 uint32_t reserved; /*!< Reserved */
<> 128:9bcdf88f62b0 760 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
<> 128:9bcdf88f62b0 761 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 762 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 763 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
<> 128:9bcdf88f62b0 764 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
<> 128:9bcdf88f62b0 765 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
<> 128:9bcdf88f62b0 766 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
<> 128:9bcdf88f62b0 767 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
<> 128:9bcdf88f62b0 768 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
<> 128:9bcdf88f62b0 769 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
<> 128:9bcdf88f62b0 770 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
<> 128:9bcdf88f62b0 771 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
<> 128:9bcdf88f62b0 772 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
<> 128:9bcdf88f62b0 773 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
<> 128:9bcdf88f62b0 774 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
<> 128:9bcdf88f62b0 775 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
<> 128:9bcdf88f62b0 776 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
<> 128:9bcdf88f62b0 777 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
<> 128:9bcdf88f62b0 778 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
<> 128:9bcdf88f62b0 779 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
<> 128:9bcdf88f62b0 780 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
<> 128:9bcdf88f62b0 781 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
<> 128:9bcdf88f62b0 782 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
<> 128:9bcdf88f62b0 783 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
<> 128:9bcdf88f62b0 784 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
<> 128:9bcdf88f62b0 785 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
<> 128:9bcdf88f62b0 786 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
<> 128:9bcdf88f62b0 787 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
<> 128:9bcdf88f62b0 788 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
<> 128:9bcdf88f62b0 789 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
<> 128:9bcdf88f62b0 790 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
<> 128:9bcdf88f62b0 791 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
<> 128:9bcdf88f62b0 792 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
<> 128:9bcdf88f62b0 793 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
<> 128:9bcdf88f62b0 794 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
<> 128:9bcdf88f62b0 795 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
<> 128:9bcdf88f62b0 796 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
<> 128:9bcdf88f62b0 797 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
<> 128:9bcdf88f62b0 798 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
<> 128:9bcdf88f62b0 799 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
<> 128:9bcdf88f62b0 800 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
<> 128:9bcdf88f62b0 801 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
<> 128:9bcdf88f62b0 802 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
<> 128:9bcdf88f62b0 803 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
<> 128:9bcdf88f62b0 804 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
<> 128:9bcdf88f62b0 805 } RTC_TypeDef;
<> 128:9bcdf88f62b0 806
<> 128:9bcdf88f62b0 807
<> 128:9bcdf88f62b0 808 /**
<> 128:9bcdf88f62b0 809 * @brief Serial Audio Interface
<> 128:9bcdf88f62b0 810 */
<> 128:9bcdf88f62b0 811
<> 128:9bcdf88f62b0 812 typedef struct
<> 128:9bcdf88f62b0 813 {
<> 128:9bcdf88f62b0 814 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 815 } SAI_TypeDef;
<> 128:9bcdf88f62b0 816
<> 128:9bcdf88f62b0 817 typedef struct
<> 128:9bcdf88f62b0 818 {
<> 128:9bcdf88f62b0 819 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
<> 128:9bcdf88f62b0 820 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
<> 128:9bcdf88f62b0 821 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 822 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 823 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 824 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 825 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
<> 128:9bcdf88f62b0 826 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 827 } SAI_Block_TypeDef;
<> 128:9bcdf88f62b0 828
<> 128:9bcdf88f62b0 829
<> 128:9bcdf88f62b0 830 /**
<> 128:9bcdf88f62b0 831 * @brief Secure digital input/output Interface
<> 128:9bcdf88f62b0 832 */
<> 128:9bcdf88f62b0 833
<> 128:9bcdf88f62b0 834 typedef struct
<> 128:9bcdf88f62b0 835 {
<> 128:9bcdf88f62b0 836 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 837 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 838 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 839 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 840 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 841 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 842 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 843 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
<> 128:9bcdf88f62b0 844 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 845 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 846 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
<> 128:9bcdf88f62b0 847 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
<> 128:9bcdf88f62b0 848 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
<> 128:9bcdf88f62b0 849 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
<> 128:9bcdf88f62b0 850 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
<> 128:9bcdf88f62b0 851 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
<> 128:9bcdf88f62b0 852 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
<> 128:9bcdf88f62b0 853 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
<> 128:9bcdf88f62b0 854 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
<> 128:9bcdf88f62b0 855 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
<> 128:9bcdf88f62b0 856 } SDMMC_TypeDef;
<> 128:9bcdf88f62b0 857
<> 128:9bcdf88f62b0 858
<> 128:9bcdf88f62b0 859 /**
<> 128:9bcdf88f62b0 860 * @brief Serial Peripheral Interface
<> 128:9bcdf88f62b0 861 */
<> 128:9bcdf88f62b0 862
<> 128:9bcdf88f62b0 863 typedef struct
<> 128:9bcdf88f62b0 864 {
<> 128:9bcdf88f62b0 865 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
<> 128:9bcdf88f62b0 866 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
<> 128:9bcdf88f62b0 867 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 868 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 869 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 870 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 871 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 872 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
<> 128:9bcdf88f62b0 873 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
<> 128:9bcdf88f62b0 874 } SPI_TypeDef;
<> 128:9bcdf88f62b0 875
<> 128:9bcdf88f62b0 876
<> 128:9bcdf88f62b0 877 /**
<> 128:9bcdf88f62b0 878 * @brief Single Wire Protocol Master Interface SPWMI
<> 128:9bcdf88f62b0 879 */
<> 128:9bcdf88f62b0 880
<> 128:9bcdf88f62b0 881 typedef struct
<> 128:9bcdf88f62b0 882 {
<> 128:9bcdf88f62b0 883 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 884 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 885 uint32_t RESERVED1; /*!< Reserved, 0x08 */
<> 128:9bcdf88f62b0 886 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 887 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 888 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 889 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 890 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
<> 128:9bcdf88f62b0 891 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 892 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 893 } SWPMI_TypeDef;
<> 128:9bcdf88f62b0 894
<> 128:9bcdf88f62b0 895
<> 128:9bcdf88f62b0 896 /**
<> 128:9bcdf88f62b0 897 * @brief System configuration controller
<> 128:9bcdf88f62b0 898 */
<> 128:9bcdf88f62b0 899
<> 128:9bcdf88f62b0 900 typedef struct
<> 128:9bcdf88f62b0 901 {
<> 128:9bcdf88f62b0 902 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 903 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
<> 128:9bcdf88f62b0 904 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
<> 128:9bcdf88f62b0 905 __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 906 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
<> 128:9bcdf88f62b0 907 __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 908 __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 909 } SYSCFG_TypeDef;
<> 128:9bcdf88f62b0 910
<> 128:9bcdf88f62b0 911
<> 128:9bcdf88f62b0 912 /**
<> 128:9bcdf88f62b0 913 * @brief TIM
<> 128:9bcdf88f62b0 914 */
<> 128:9bcdf88f62b0 915
<> 128:9bcdf88f62b0 916 typedef struct
<> 128:9bcdf88f62b0 917 {
<> 128:9bcdf88f62b0 918 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
<> 128:9bcdf88f62b0 919 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
<> 128:9bcdf88f62b0 920 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 921 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 922 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 923 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 924 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
<> 128:9bcdf88f62b0 925 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
<> 128:9bcdf88f62b0 926 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 927 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 928 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
<> 128:9bcdf88f62b0 929 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
<> 128:9bcdf88f62b0 930 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
<> 128:9bcdf88f62b0 931 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
<> 128:9bcdf88f62b0 932 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
<> 128:9bcdf88f62b0 933 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
<> 128:9bcdf88f62b0 934 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
<> 128:9bcdf88f62b0 935 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
<> 128:9bcdf88f62b0 936 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
<> 128:9bcdf88f62b0 937 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
<> 128:9bcdf88f62b0 938 __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */
<> 128:9bcdf88f62b0 939 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
<> 128:9bcdf88f62b0 940 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
<> 128:9bcdf88f62b0 941 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
<> 128:9bcdf88f62b0 942 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */
<> 128:9bcdf88f62b0 943 __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */
<> 128:9bcdf88f62b0 944 } TIM_TypeDef;
<> 128:9bcdf88f62b0 945
<> 128:9bcdf88f62b0 946
<> 128:9bcdf88f62b0 947 /**
<> 128:9bcdf88f62b0 948 * @brief Touch Sensing Controller (TSC)
<> 128:9bcdf88f62b0 949 */
<> 128:9bcdf88f62b0 950
<> 128:9bcdf88f62b0 951 typedef struct
<> 128:9bcdf88f62b0 952 {
<> 128:9bcdf88f62b0 953 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 954 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 955 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 956 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 957 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 958 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
<> 128:9bcdf88f62b0 959 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 960 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
<> 128:9bcdf88f62b0 961 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 962 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
<> 128:9bcdf88f62b0 963 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
<> 128:9bcdf88f62b0 964 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
<> 128:9bcdf88f62b0 965 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
<> 128:9bcdf88f62b0 966 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
<> 128:9bcdf88f62b0 967 } TSC_TypeDef;
<> 128:9bcdf88f62b0 968
<> 128:9bcdf88f62b0 969 /**
<> 128:9bcdf88f62b0 970 * @brief Universal Synchronous Asynchronous Receiver Transmitter
<> 128:9bcdf88f62b0 971 */
<> 128:9bcdf88f62b0 972
<> 128:9bcdf88f62b0 973 typedef struct
<> 128:9bcdf88f62b0 974 {
<> 128:9bcdf88f62b0 975 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
<> 128:9bcdf88f62b0 976 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
<> 128:9bcdf88f62b0 977 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
<> 128:9bcdf88f62b0 978 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 979 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
<> 128:9bcdf88f62b0 980 uint16_t RESERVED2; /*!< Reserved, 0x12 */
<> 128:9bcdf88f62b0 981 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
<> 128:9bcdf88f62b0 982 __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
<> 128:9bcdf88f62b0 983 uint16_t RESERVED3; /*!< Reserved, 0x1A */
<> 128:9bcdf88f62b0 984 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
<> 128:9bcdf88f62b0 985 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
<> 128:9bcdf88f62b0 986 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
<> 128:9bcdf88f62b0 987 uint16_t RESERVED4; /*!< Reserved, 0x26 */
<> 128:9bcdf88f62b0 988 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
<> 128:9bcdf88f62b0 989 uint16_t RESERVED5; /*!< Reserved, 0x2A */
<> 128:9bcdf88f62b0 990 } USART_TypeDef;
<> 128:9bcdf88f62b0 991
<> 128:9bcdf88f62b0 992 /**
<> 128:9bcdf88f62b0 993 * @brief VREFBUF
<> 128:9bcdf88f62b0 994 */
<> 128:9bcdf88f62b0 995
<> 128:9bcdf88f62b0 996 typedef struct
<> 128:9bcdf88f62b0 997 {
<> 128:9bcdf88f62b0 998 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 999 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 1000 } VREFBUF_TypeDef;
<> 128:9bcdf88f62b0 1001
<> 128:9bcdf88f62b0 1002 /**
<> 128:9bcdf88f62b0 1003 * @brief Window WATCHDOG
<> 128:9bcdf88f62b0 1004 */
<> 128:9bcdf88f62b0 1005
<> 128:9bcdf88f62b0 1006 typedef struct
<> 128:9bcdf88f62b0 1007 {
<> 128:9bcdf88f62b0 1008 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 1009 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 1010 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 1011 } WWDG_TypeDef;
<> 128:9bcdf88f62b0 1012
<> 128:9bcdf88f62b0 1013 /**
<> 128:9bcdf88f62b0 1014 * @brief AES hardware accelerator
<> 128:9bcdf88f62b0 1015 */
<> 128:9bcdf88f62b0 1016
<> 128:9bcdf88f62b0 1017 typedef struct
<> 128:9bcdf88f62b0 1018 {
<> 128:9bcdf88f62b0 1019 __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 1020 __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 1021 __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 1022 __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
<> 128:9bcdf88f62b0 1023 __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
<> 128:9bcdf88f62b0 1024 __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
<> 128:9bcdf88f62b0 1025 __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
<> 128:9bcdf88f62b0 1026 __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
<> 128:9bcdf88f62b0 1027 __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
<> 128:9bcdf88f62b0 1028 __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
<> 128:9bcdf88f62b0 1029 __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
<> 128:9bcdf88f62b0 1030 __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
<> 128:9bcdf88f62b0 1031 __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */
<> 128:9bcdf88f62b0 1032 __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */
<> 128:9bcdf88f62b0 1033 __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */
<> 128:9bcdf88f62b0 1034 __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */
<> 128:9bcdf88f62b0 1035 __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */
<> 128:9bcdf88f62b0 1036 __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */
<> 128:9bcdf88f62b0 1037 __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */
<> 128:9bcdf88f62b0 1038 __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */
<> 128:9bcdf88f62b0 1039 __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */
<> 128:9bcdf88f62b0 1040 __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */
<> 128:9bcdf88f62b0 1041 __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */
<> 128:9bcdf88f62b0 1042 __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */
<> 128:9bcdf88f62b0 1043 } AES_TypeDef;
<> 128:9bcdf88f62b0 1044
<> 128:9bcdf88f62b0 1045 /**
<> 128:9bcdf88f62b0 1046 * @brief RNG
<> 128:9bcdf88f62b0 1047 */
<> 128:9bcdf88f62b0 1048
<> 128:9bcdf88f62b0 1049 typedef struct
<> 128:9bcdf88f62b0 1050 {
<> 128:9bcdf88f62b0 1051 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
<> 128:9bcdf88f62b0 1052 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
<> 128:9bcdf88f62b0 1053 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
<> 128:9bcdf88f62b0 1054 } RNG_TypeDef;
<> 128:9bcdf88f62b0 1055
<> 128:9bcdf88f62b0 1056 /**
<> 128:9bcdf88f62b0 1057 * @brief USB_OTG_Core_register
<> 128:9bcdf88f62b0 1058 */
<> 128:9bcdf88f62b0 1059 typedef struct
<> 128:9bcdf88f62b0 1060 {
<> 128:9bcdf88f62b0 1061 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
<> 128:9bcdf88f62b0 1062 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
<> 128:9bcdf88f62b0 1063 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
<> 128:9bcdf88f62b0 1064 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
<> 128:9bcdf88f62b0 1065 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
<> 128:9bcdf88f62b0 1066 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
<> 128:9bcdf88f62b0 1067 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
<> 128:9bcdf88f62b0 1068 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
<> 128:9bcdf88f62b0 1069 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
<> 128:9bcdf88f62b0 1070 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
<> 128:9bcdf88f62b0 1071 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
<> 128:9bcdf88f62b0 1072 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
<> 128:9bcdf88f62b0 1073 uint32_t Reserved30[2]; /* Reserved 030h*/
<> 128:9bcdf88f62b0 1074 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
<> 128:9bcdf88f62b0 1075 __IO uint32_t CID; /* User ID Register 03Ch*/
<> 128:9bcdf88f62b0 1076 uint32_t Reserved5[3]; /* Reserved 040h-048h*/
<> 128:9bcdf88f62b0 1077 __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/
<> 128:9bcdf88f62b0 1078 uint32_t Reserved6; /* Reserved 050h*/
<> 128:9bcdf88f62b0 1079 __IO uint32_t GLPMCFG; /* LPM Register 054h*/
<> 128:9bcdf88f62b0 1080 __IO uint32_t GPWRDN; /* Power Down Register 058h*/
<> 128:9bcdf88f62b0 1081 __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/
<> 128:9bcdf88f62b0 1082 __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/
<> 128:9bcdf88f62b0 1083 uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/
<> 128:9bcdf88f62b0 1084 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
<> 128:9bcdf88f62b0 1085 __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */
<> 128:9bcdf88f62b0 1086 } USB_OTG_GlobalTypeDef;
<> 128:9bcdf88f62b0 1087
<> 128:9bcdf88f62b0 1088 /**
<> 128:9bcdf88f62b0 1089 * @brief USB_OTG_device_Registers
<> 128:9bcdf88f62b0 1090 */
<> 128:9bcdf88f62b0 1091 typedef struct
<> 128:9bcdf88f62b0 1092 {
<> 128:9bcdf88f62b0 1093 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
<> 128:9bcdf88f62b0 1094 __IO uint32_t DCTL; /* dev Control Register 804h*/
<> 128:9bcdf88f62b0 1095 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
<> 128:9bcdf88f62b0 1096 uint32_t Reserved0C; /* Reserved 80Ch*/
<> 128:9bcdf88f62b0 1097 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
<> 128:9bcdf88f62b0 1098 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
<> 128:9bcdf88f62b0 1099 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
<> 128:9bcdf88f62b0 1100 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
<> 128:9bcdf88f62b0 1101 uint32_t Reserved20; /* Reserved 820h*/
<> 128:9bcdf88f62b0 1102 uint32_t Reserved9; /* Reserved 824h*/
<> 128:9bcdf88f62b0 1103 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
<> 128:9bcdf88f62b0 1104 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
<> 128:9bcdf88f62b0 1105 __IO uint32_t DTHRCTL; /* dev thr 830h*/
<> 128:9bcdf88f62b0 1106 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
<> 128:9bcdf88f62b0 1107 __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
<> 128:9bcdf88f62b0 1108 __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
<> 128:9bcdf88f62b0 1109 uint32_t Reserved40; /* dedicated EP mask 840h*/
<> 128:9bcdf88f62b0 1110 __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
<> 128:9bcdf88f62b0 1111 uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
<> 128:9bcdf88f62b0 1112 __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
<> 128:9bcdf88f62b0 1113 } USB_OTG_DeviceTypeDef;
<> 128:9bcdf88f62b0 1114
<> 128:9bcdf88f62b0 1115 /**
<> 128:9bcdf88f62b0 1116 * @brief USB_OTG_IN_Endpoint-Specific_Register
<> 128:9bcdf88f62b0 1117 */
<> 128:9bcdf88f62b0 1118 typedef struct
<> 128:9bcdf88f62b0 1119 {
<> 128:9bcdf88f62b0 1120 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
<> 128:9bcdf88f62b0 1121 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
<> 128:9bcdf88f62b0 1122 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
<> 128:9bcdf88f62b0 1123 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
<> 128:9bcdf88f62b0 1124 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
<> 128:9bcdf88f62b0 1125 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
<> 128:9bcdf88f62b0 1126 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
<> 128:9bcdf88f62b0 1127 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
<> 128:9bcdf88f62b0 1128 } USB_OTG_INEndpointTypeDef;
<> 128:9bcdf88f62b0 1129
<> 128:9bcdf88f62b0 1130 /**
<> 128:9bcdf88f62b0 1131 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
<> 128:9bcdf88f62b0 1132 */
<> 128:9bcdf88f62b0 1133 typedef struct
<> 128:9bcdf88f62b0 1134 {
<> 128:9bcdf88f62b0 1135 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
<> 128:9bcdf88f62b0 1136 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
<> 128:9bcdf88f62b0 1137 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
<> 128:9bcdf88f62b0 1138 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
<> 128:9bcdf88f62b0 1139 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
<> 128:9bcdf88f62b0 1140 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
<> 128:9bcdf88f62b0 1141 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
<> 128:9bcdf88f62b0 1142 } USB_OTG_OUTEndpointTypeDef;
<> 128:9bcdf88f62b0 1143
<> 128:9bcdf88f62b0 1144 /**
<> 128:9bcdf88f62b0 1145 * @brief USB_OTG_Host_Mode_Register_Structures
<> 128:9bcdf88f62b0 1146 */
<> 128:9bcdf88f62b0 1147 typedef struct
<> 128:9bcdf88f62b0 1148 {
<> 128:9bcdf88f62b0 1149 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
<> 128:9bcdf88f62b0 1150 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
<> 128:9bcdf88f62b0 1151 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
<> 128:9bcdf88f62b0 1152 uint32_t Reserved40C; /* Reserved 40Ch*/
<> 128:9bcdf88f62b0 1153 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
<> 128:9bcdf88f62b0 1154 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
<> 128:9bcdf88f62b0 1155 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
<> 128:9bcdf88f62b0 1156 } USB_OTG_HostTypeDef;
<> 128:9bcdf88f62b0 1157
<> 128:9bcdf88f62b0 1158 /**
<> 128:9bcdf88f62b0 1159 * @brief USB_OTG_Host_Channel_Specific_Registers
<> 128:9bcdf88f62b0 1160 */
<> 128:9bcdf88f62b0 1161 typedef struct
<> 128:9bcdf88f62b0 1162 {
<> 128:9bcdf88f62b0 1163 __IO uint32_t HCCHAR;
<> 128:9bcdf88f62b0 1164 __IO uint32_t HCSPLT;
<> 128:9bcdf88f62b0 1165 __IO uint32_t HCINT;
<> 128:9bcdf88f62b0 1166 __IO uint32_t HCINTMSK;
<> 128:9bcdf88f62b0 1167 __IO uint32_t HCTSIZ;
<> 128:9bcdf88f62b0 1168 __IO uint32_t HCDMA;
<> 128:9bcdf88f62b0 1169 uint32_t Reserved[2];
<> 128:9bcdf88f62b0 1170 } USB_OTG_HostChannelTypeDef;
<> 128:9bcdf88f62b0 1171
<> 128:9bcdf88f62b0 1172 /**
<> 128:9bcdf88f62b0 1173 * @}
<> 128:9bcdf88f62b0 1174 */
<> 128:9bcdf88f62b0 1175
<> 128:9bcdf88f62b0 1176 /** @addtogroup Peripheral_memory_map
<> 128:9bcdf88f62b0 1177 * @{
<> 128:9bcdf88f62b0 1178 */
<> 128:9bcdf88f62b0 1179 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
<> 128:9bcdf88f62b0 1180 #define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 96 KB) base address */
<> 128:9bcdf88f62b0 1181 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
<> 128:9bcdf88f62b0 1182 #define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */
<> 128:9bcdf88f62b0 1183 #define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address */
<> 128:9bcdf88f62b0 1184 #define QSPI_BASE ((uint32_t)0x90000000U) /*!< QSPI memories accessible over AHB base address */
<> 128:9bcdf88f62b0 1185 #define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
<> 128:9bcdf88f62b0 1186 #define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
<> 128:9bcdf88f62b0 1187 #define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
<> 128:9bcdf88f62b0 1188 #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
<> 128:9bcdf88f62b0 1189 #define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
<> 128:9bcdf88f62b0 1190
<> 128:9bcdf88f62b0 1191 /* Legacy defines */
<> 128:9bcdf88f62b0 1192 #define SRAM_BASE SRAM1_BASE
<> 128:9bcdf88f62b0 1193 #define SRAM_BB_BASE SRAM1_BB_BASE
<> 128:9bcdf88f62b0 1194
<> 128:9bcdf88f62b0 1195 #define SRAM1_SIZE_MAX ((uint32_t)0x00018000U) /*!< maximum SRAM1 size (up to 96 KBytes) */
<> 128:9bcdf88f62b0 1196 #define SRAM2_SIZE ((uint32_t)0x00008000U) /*!< SRAM2 size (32 KBytes) */
<> 128:9bcdf88f62b0 1197
<> 128:9bcdf88f62b0 1198 /*!< Peripheral memory map */
<> 128:9bcdf88f62b0 1199 #define APB1PERIPH_BASE PERIPH_BASE
<> 128:9bcdf88f62b0 1200 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
<> 128:9bcdf88f62b0 1201 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
<> 128:9bcdf88f62b0 1202 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U)
<> 128:9bcdf88f62b0 1203
<> 128:9bcdf88f62b0 1204 #define FMC_BANK1 FMC_BASE
<> 128:9bcdf88f62b0 1205 #define FMC_BANK1_1 FMC_BANK1
<> 128:9bcdf88f62b0 1206 #define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U)
<> 128:9bcdf88f62b0 1207 #define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U)
<> 128:9bcdf88f62b0 1208 #define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U)
<> 128:9bcdf88f62b0 1209 #define FMC_BANK3 (FMC_BASE + 0x20000000U)
<> 128:9bcdf88f62b0 1210
<> 128:9bcdf88f62b0 1211 /*!< APB1 peripherals */
<> 128:9bcdf88f62b0 1212 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
<> 128:9bcdf88f62b0 1213 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
<> 128:9bcdf88f62b0 1214 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
<> 128:9bcdf88f62b0 1215 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
<> 128:9bcdf88f62b0 1216 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
<> 128:9bcdf88f62b0 1217 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
<> 128:9bcdf88f62b0 1218 #define LCD_BASE (APB1PERIPH_BASE + 0x2400U)
<> 128:9bcdf88f62b0 1219 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
<> 128:9bcdf88f62b0 1220 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
<> 128:9bcdf88f62b0 1221 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
<> 128:9bcdf88f62b0 1222 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
<> 128:9bcdf88f62b0 1223 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
<> 128:9bcdf88f62b0 1224 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
<> 128:9bcdf88f62b0 1225 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
<> 128:9bcdf88f62b0 1226 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
<> 128:9bcdf88f62b0 1227 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
<> 128:9bcdf88f62b0 1228 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
<> 128:9bcdf88f62b0 1229 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
<> 128:9bcdf88f62b0 1230 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
<> 128:9bcdf88f62b0 1231 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
<> 128:9bcdf88f62b0 1232 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
<> 128:9bcdf88f62b0 1233 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
<> 128:9bcdf88f62b0 1234 #define DAC1_BASE (APB1PERIPH_BASE + 0x7400U)
<> 128:9bcdf88f62b0 1235 #define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U)
<> 128:9bcdf88f62b0 1236 #define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U)
<> 128:9bcdf88f62b0 1237 #define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U)
<> 128:9bcdf88f62b0 1238 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U)
<> 128:9bcdf88f62b0 1239 #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U)
<> 128:9bcdf88f62b0 1240 #define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U)
<> 128:9bcdf88f62b0 1241 #define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U)
<> 128:9bcdf88f62b0 1242
<> 128:9bcdf88f62b0 1243
<> 128:9bcdf88f62b0 1244 /*!< APB2 peripherals */
<> 128:9bcdf88f62b0 1245 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U)
<> 128:9bcdf88f62b0 1246 #define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U)
<> 128:9bcdf88f62b0 1247 #define COMP1_BASE (APB2PERIPH_BASE + 0x0200U)
<> 128:9bcdf88f62b0 1248 #define COMP2_BASE (APB2PERIPH_BASE + 0x0204U)
<> 128:9bcdf88f62b0 1249 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400U)
<> 128:9bcdf88f62b0 1250 #define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U)
<> 128:9bcdf88f62b0 1251 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U)
<> 128:9bcdf88f62b0 1252 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U)
<> 128:9bcdf88f62b0 1253 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
<> 128:9bcdf88f62b0 1254 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400U)
<> 128:9bcdf88f62b0 1255 #define USART1_BASE (APB2PERIPH_BASE + 0x3800U)
<> 128:9bcdf88f62b0 1256 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000U)
<> 128:9bcdf88f62b0 1257 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400U)
<> 128:9bcdf88f62b0 1258 #define TIM17_BASE (APB2PERIPH_BASE + 0x4800U)
<> 128:9bcdf88f62b0 1259 #define SAI1_BASE (APB2PERIPH_BASE + 0x5400U)
<> 128:9bcdf88f62b0 1260 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
<> 128:9bcdf88f62b0 1261 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
<> 128:9bcdf88f62b0 1262 #define SAI2_BASE (APB2PERIPH_BASE + 0x5800U)
<> 128:9bcdf88f62b0 1263 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
<> 128:9bcdf88f62b0 1264 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
<> 128:9bcdf88f62b0 1265 #define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
<> 128:9bcdf88f62b0 1266 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
<> 128:9bcdf88f62b0 1267 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
<> 128:9bcdf88f62b0 1268 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40)
<> 128:9bcdf88f62b0 1269 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60)
<> 128:9bcdf88f62b0 1270 #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80)
<> 128:9bcdf88f62b0 1271 #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0)
<> 128:9bcdf88f62b0 1272 #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0)
<> 128:9bcdf88f62b0 1273 #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0)
<> 128:9bcdf88f62b0 1274 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100)
<> 128:9bcdf88f62b0 1275 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180)
<> 128:9bcdf88f62b0 1276 #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200)
<> 128:9bcdf88f62b0 1277 #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280)
<> 128:9bcdf88f62b0 1278
<> 128:9bcdf88f62b0 1279 /*!< AHB1 peripherals */
<> 128:9bcdf88f62b0 1280 #define DMA1_BASE (AHB1PERIPH_BASE)
<> 128:9bcdf88f62b0 1281 #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U)
<> 128:9bcdf88f62b0 1282 #define RCC_BASE (AHB1PERIPH_BASE + 0x1000U)
<> 128:9bcdf88f62b0 1283 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U)
<> 128:9bcdf88f62b0 1284 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
<> 128:9bcdf88f62b0 1285 #define TSC_BASE (AHB1PERIPH_BASE + 0x4000U)
<> 128:9bcdf88f62b0 1286
<> 128:9bcdf88f62b0 1287
<> 128:9bcdf88f62b0 1288 #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U)
<> 128:9bcdf88f62b0 1289 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU)
<> 128:9bcdf88f62b0 1290 #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U)
<> 128:9bcdf88f62b0 1291 #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U)
<> 128:9bcdf88f62b0 1292 #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U)
<> 128:9bcdf88f62b0 1293 #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU)
<> 128:9bcdf88f62b0 1294 #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U)
<> 128:9bcdf88f62b0 1295 #define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U)
<> 128:9bcdf88f62b0 1296
<> 128:9bcdf88f62b0 1297
<> 128:9bcdf88f62b0 1298 #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U)
<> 128:9bcdf88f62b0 1299 #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU)
<> 128:9bcdf88f62b0 1300 #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U)
<> 128:9bcdf88f62b0 1301 #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U)
<> 128:9bcdf88f62b0 1302 #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U)
<> 128:9bcdf88f62b0 1303 #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU)
<> 128:9bcdf88f62b0 1304 #define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U)
<> 128:9bcdf88f62b0 1305 #define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U)
<> 128:9bcdf88f62b0 1306
<> 128:9bcdf88f62b0 1307
<> 128:9bcdf88f62b0 1308 /*!< AHB2 peripherals */
<> 128:9bcdf88f62b0 1309 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U)
<> 128:9bcdf88f62b0 1310 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U)
<> 128:9bcdf88f62b0 1311 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U)
<> 128:9bcdf88f62b0 1312 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U)
<> 128:9bcdf88f62b0 1313 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U)
<> 128:9bcdf88f62b0 1314 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U)
<> 128:9bcdf88f62b0 1315 #define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U)
<> 128:9bcdf88f62b0 1316 #define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U)
<> 128:9bcdf88f62b0 1317
<> 128:9bcdf88f62b0 1318 #define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000U)
<> 128:9bcdf88f62b0 1319
<> 128:9bcdf88f62b0 1320 #define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U)
<> 128:9bcdf88f62b0 1321 #define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100U)
<> 128:9bcdf88f62b0 1322 #define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200U)
<> 128:9bcdf88f62b0 1323 #define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U)
<> 128:9bcdf88f62b0 1324
<> 128:9bcdf88f62b0 1325
<> 128:9bcdf88f62b0 1326 #define AES_BASE (AHB2PERIPH_BASE + 0x08060000U)
<> 128:9bcdf88f62b0 1327 #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U)
<> 128:9bcdf88f62b0 1328
<> 128:9bcdf88f62b0 1329
<> 128:9bcdf88f62b0 1330 /*!< FMC Banks registers base address */
<> 128:9bcdf88f62b0 1331 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
<> 128:9bcdf88f62b0 1332 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
<> 128:9bcdf88f62b0 1333 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
<> 128:9bcdf88f62b0 1334
<> 128:9bcdf88f62b0 1335 /* Debug MCU registers base address */
<> 128:9bcdf88f62b0 1336 #define DBGMCU_BASE ((uint32_t)0xE0042000U)
<> 128:9bcdf88f62b0 1337
<> 128:9bcdf88f62b0 1338 /*!< USB registers base address */
<> 128:9bcdf88f62b0 1339 #define USB_OTG_FS_PERIPH_BASE ((uint32_t)0x50000000U)
<> 128:9bcdf88f62b0 1340
<> 128:9bcdf88f62b0 1341 #define USB_OTG_GLOBAL_BASE ((uint32_t)0x00000000U)
<> 128:9bcdf88f62b0 1342 #define USB_OTG_DEVICE_BASE ((uint32_t)0x00000800U)
<> 128:9bcdf88f62b0 1343 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t)0x00000900U)
<> 128:9bcdf88f62b0 1344 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t)0x00000B00U)
<> 128:9bcdf88f62b0 1345 #define USB_OTG_EP_REG_SIZE ((uint32_t)0x00000020U)
<> 128:9bcdf88f62b0 1346 #define USB_OTG_HOST_BASE ((uint32_t)0x00000400U)
<> 128:9bcdf88f62b0 1347 #define USB_OTG_HOST_PORT_BASE ((uint32_t)0x00000440U)
<> 128:9bcdf88f62b0 1348 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t)0x00000500U)
<> 128:9bcdf88f62b0 1349 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t)0x00000020U)
<> 128:9bcdf88f62b0 1350 #define USB_OTG_PCGCCTL_BASE ((uint32_t)0x00000E00U)
<> 128:9bcdf88f62b0 1351 #define USB_OTG_FIFO_BASE ((uint32_t)0x00001000U)
<> 128:9bcdf88f62b0 1352 #define USB_OTG_FIFO_SIZE ((uint32_t)0x00001000U)
<> 128:9bcdf88f62b0 1353
<> 128:9bcdf88f62b0 1354
<> 128:9bcdf88f62b0 1355 #define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */
<> 128:9bcdf88f62b0 1356 #define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */
<> 128:9bcdf88f62b0 1357 #define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */
<> 128:9bcdf88f62b0 1358 /**
<> 128:9bcdf88f62b0 1359 * @}
<> 128:9bcdf88f62b0 1360 */
<> 128:9bcdf88f62b0 1361
<> 128:9bcdf88f62b0 1362 /** @addtogroup Peripheral_declaration
<> 128:9bcdf88f62b0 1363 * @{
<> 128:9bcdf88f62b0 1364 */
<> 128:9bcdf88f62b0 1365 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
<> 128:9bcdf88f62b0 1366 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
<> 128:9bcdf88f62b0 1367 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
<> 128:9bcdf88f62b0 1368 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
<> 128:9bcdf88f62b0 1369 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
<> 128:9bcdf88f62b0 1370 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
<> 128:9bcdf88f62b0 1371 #define LCD ((LCD_TypeDef *) LCD_BASE)
<> 128:9bcdf88f62b0 1372 #define RTC ((RTC_TypeDef *) RTC_BASE)
<> 128:9bcdf88f62b0 1373 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
<> 128:9bcdf88f62b0 1374 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
<> 128:9bcdf88f62b0 1375 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
<> 128:9bcdf88f62b0 1376 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
<> 128:9bcdf88f62b0 1377 #define USART2 ((USART_TypeDef *) USART2_BASE)
<> 128:9bcdf88f62b0 1378 #define USART3 ((USART_TypeDef *) USART3_BASE)
<> 128:9bcdf88f62b0 1379 #define UART4 ((USART_TypeDef *) UART4_BASE)
<> 128:9bcdf88f62b0 1380 #define UART5 ((USART_TypeDef *) UART5_BASE)
<> 128:9bcdf88f62b0 1381 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
<> 128:9bcdf88f62b0 1382 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
<> 128:9bcdf88f62b0 1383 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
<> 128:9bcdf88f62b0 1384 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
<> 128:9bcdf88f62b0 1385 #define PWR ((PWR_TypeDef *) PWR_BASE)
<> 128:9bcdf88f62b0 1386 #define DAC ((DAC_TypeDef *) DAC1_BASE)
<> 128:9bcdf88f62b0 1387 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
<> 128:9bcdf88f62b0 1388 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
<> 128:9bcdf88f62b0 1389 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
<> 128:9bcdf88f62b0 1390 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
<> 128:9bcdf88f62b0 1391 #define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
<> 128:9bcdf88f62b0 1392 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
<> 128:9bcdf88f62b0 1393 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
<> 128:9bcdf88f62b0 1394 #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
<> 128:9bcdf88f62b0 1395 #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
<> 128:9bcdf88f62b0 1396
<> 128:9bcdf88f62b0 1397 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
<> 128:9bcdf88f62b0 1398 #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
<> 128:9bcdf88f62b0 1399 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
<> 128:9bcdf88f62b0 1400 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
<> 128:9bcdf88f62b0 1401 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
<> 128:9bcdf88f62b0 1402 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
<> 128:9bcdf88f62b0 1403 #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
<> 128:9bcdf88f62b0 1404 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
<> 128:9bcdf88f62b0 1405 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
<> 128:9bcdf88f62b0 1406 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
<> 128:9bcdf88f62b0 1407 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
<> 128:9bcdf88f62b0 1408 #define USART1 ((USART_TypeDef *) USART1_BASE)
<> 128:9bcdf88f62b0 1409 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
<> 128:9bcdf88f62b0 1410 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
<> 128:9bcdf88f62b0 1411 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
<> 128:9bcdf88f62b0 1412 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
<> 128:9bcdf88f62b0 1413 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
<> 128:9bcdf88f62b0 1414 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
<> 128:9bcdf88f62b0 1415 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
<> 128:9bcdf88f62b0 1416 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
<> 128:9bcdf88f62b0 1417 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
<> 128:9bcdf88f62b0 1418 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
<> 128:9bcdf88f62b0 1419 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
<> 128:9bcdf88f62b0 1420 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
<> 128:9bcdf88f62b0 1421 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
<> 128:9bcdf88f62b0 1422 #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
<> 128:9bcdf88f62b0 1423 #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
<> 128:9bcdf88f62b0 1424 #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
<> 128:9bcdf88f62b0 1425 #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
<> 128:9bcdf88f62b0 1426 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
<> 128:9bcdf88f62b0 1427 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
<> 128:9bcdf88f62b0 1428 #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
<> 128:9bcdf88f62b0 1429 #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
<> 128:9bcdf88f62b0 1430 /* Aliases to keep compatibility after DFSDM renaming */
<> 128:9bcdf88f62b0 1431 #define DFSDM_Channel0 DFSDM1_Channel0
<> 128:9bcdf88f62b0 1432 #define DFSDM_Channel1 DFSDM1_Channel1
<> 128:9bcdf88f62b0 1433 #define DFSDM_Channel2 DFSDM1_Channel2
<> 128:9bcdf88f62b0 1434 #define DFSDM_Channel3 DFSDM1_Channel3
<> 128:9bcdf88f62b0 1435 #define DFSDM_Channel4 DFSDM1_Channel4
<> 128:9bcdf88f62b0 1436 #define DFSDM_Channel5 DFSDM1_Channel5
<> 128:9bcdf88f62b0 1437 #define DFSDM_Channel6 DFSDM1_Channel6
<> 128:9bcdf88f62b0 1438 #define DFSDM_Channel7 DFSDM1_Channel7
<> 128:9bcdf88f62b0 1439 #define DFSDM_Filter0 DFSDM1_Filter0
<> 128:9bcdf88f62b0 1440 #define DFSDM_Filter1 DFSDM1_Filter1
<> 128:9bcdf88f62b0 1441 #define DFSDM_Filter2 DFSDM1_Filter2
<> 128:9bcdf88f62b0 1442 #define DFSDM_Filter3 DFSDM1_Filter3
<> 128:9bcdf88f62b0 1443 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
<> 128:9bcdf88f62b0 1444 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
<> 128:9bcdf88f62b0 1445 #define RCC ((RCC_TypeDef *) RCC_BASE)
<> 128:9bcdf88f62b0 1446 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
<> 128:9bcdf88f62b0 1447 #define CRC ((CRC_TypeDef *) CRC_BASE)
<> 128:9bcdf88f62b0 1448 #define TSC ((TSC_TypeDef *) TSC_BASE)
<> 128:9bcdf88f62b0 1449
<> 128:9bcdf88f62b0 1450 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
<> 128:9bcdf88f62b0 1451 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
<> 128:9bcdf88f62b0 1452 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
<> 128:9bcdf88f62b0 1453 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
<> 128:9bcdf88f62b0 1454 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
<> 128:9bcdf88f62b0 1455 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
<> 128:9bcdf88f62b0 1456 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
<> 128:9bcdf88f62b0 1457 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
<> 128:9bcdf88f62b0 1458 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
<> 128:9bcdf88f62b0 1459 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
<> 128:9bcdf88f62b0 1460 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
<> 128:9bcdf88f62b0 1461 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
<> 128:9bcdf88f62b0 1462 #define AES ((AES_TypeDef *) AES_BASE)
<> 128:9bcdf88f62b0 1463 #define RNG ((RNG_TypeDef *) RNG_BASE)
<> 128:9bcdf88f62b0 1464
<> 128:9bcdf88f62b0 1465
<> 128:9bcdf88f62b0 1466 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
<> 128:9bcdf88f62b0 1467 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
<> 128:9bcdf88f62b0 1468 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
<> 128:9bcdf88f62b0 1469 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
<> 128:9bcdf88f62b0 1470 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
<> 128:9bcdf88f62b0 1471 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
<> 128:9bcdf88f62b0 1472 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
<> 128:9bcdf88f62b0 1473 #define DMA1_CSELR ((DMA_request_TypeDef *) DMA1_CSELR_BASE)
<> 128:9bcdf88f62b0 1474
<> 128:9bcdf88f62b0 1475
<> 128:9bcdf88f62b0 1476 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
<> 128:9bcdf88f62b0 1477 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
<> 128:9bcdf88f62b0 1478 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
<> 128:9bcdf88f62b0 1479 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
<> 128:9bcdf88f62b0 1480 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
<> 128:9bcdf88f62b0 1481 #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
<> 128:9bcdf88f62b0 1482 #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
<> 128:9bcdf88f62b0 1483 #define DMA2_CSELR ((DMA_request_TypeDef *) DMA2_CSELR_BASE)
<> 128:9bcdf88f62b0 1484
<> 128:9bcdf88f62b0 1485
<> 128:9bcdf88f62b0 1486 #define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
<> 128:9bcdf88f62b0 1487 #define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
<> 128:9bcdf88f62b0 1488 #define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
<> 128:9bcdf88f62b0 1489
<> 128:9bcdf88f62b0 1490 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
<> 128:9bcdf88f62b0 1491
<> 128:9bcdf88f62b0 1492 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
<> 128:9bcdf88f62b0 1493
<> 128:9bcdf88f62b0 1494 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
<> 128:9bcdf88f62b0 1495 /**
<> 128:9bcdf88f62b0 1496 * @}
<> 128:9bcdf88f62b0 1497 */
<> 128:9bcdf88f62b0 1498
<> 128:9bcdf88f62b0 1499 /** @addtogroup Exported_constants
<> 128:9bcdf88f62b0 1500 * @{
<> 128:9bcdf88f62b0 1501 */
<> 128:9bcdf88f62b0 1502
<> 128:9bcdf88f62b0 1503 /** @addtogroup Peripheral_Registers_Bits_Definition
<> 128:9bcdf88f62b0 1504 * @{
<> 128:9bcdf88f62b0 1505 */
<> 128:9bcdf88f62b0 1506
<> 128:9bcdf88f62b0 1507 /******************************************************************************/
<> 128:9bcdf88f62b0 1508 /* Peripheral Registers_Bits_Definition */
<> 128:9bcdf88f62b0 1509 /******************************************************************************/
<> 128:9bcdf88f62b0 1510
<> 128:9bcdf88f62b0 1511 /******************************************************************************/
<> 128:9bcdf88f62b0 1512 /* */
<> 128:9bcdf88f62b0 1513 /* Analog to Digital Converter */
<> 128:9bcdf88f62b0 1514 /* */
<> 128:9bcdf88f62b0 1515 /******************************************************************************/
<> 128:9bcdf88f62b0 1516
<> 128:9bcdf88f62b0 1517 /*
<> 128:9bcdf88f62b0 1518 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
<> 128:9bcdf88f62b0 1519 */
<> 128:9bcdf88f62b0 1520 #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
<> 128:9bcdf88f62b0 1521
<> 128:9bcdf88f62b0 1522 /******************** Bit definition for ADC_ISR register *******************/
<> 128:9bcdf88f62b0 1523 #define ADC_ISR_ADRDY_Pos (0U)
<> 128:9bcdf88f62b0 1524 #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 1525 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
<> 128:9bcdf88f62b0 1526 #define ADC_ISR_EOSMP_Pos (1U)
<> 128:9bcdf88f62b0 1527 #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 1528 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
<> 128:9bcdf88f62b0 1529 #define ADC_ISR_EOC_Pos (2U)
<> 128:9bcdf88f62b0 1530 #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 1531 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
<> 128:9bcdf88f62b0 1532 #define ADC_ISR_EOS_Pos (3U)
<> 128:9bcdf88f62b0 1533 #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 1534 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
<> 128:9bcdf88f62b0 1535 #define ADC_ISR_OVR_Pos (4U)
<> 128:9bcdf88f62b0 1536 #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 1537 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
<> 128:9bcdf88f62b0 1538 #define ADC_ISR_JEOC_Pos (5U)
<> 128:9bcdf88f62b0 1539 #define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 1540 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
<> 128:9bcdf88f62b0 1541 #define ADC_ISR_JEOS_Pos (6U)
<> 128:9bcdf88f62b0 1542 #define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 1543 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
<> 128:9bcdf88f62b0 1544 #define ADC_ISR_AWD1_Pos (7U)
<> 128:9bcdf88f62b0 1545 #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 1546 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
<> 128:9bcdf88f62b0 1547 #define ADC_ISR_AWD2_Pos (8U)
<> 128:9bcdf88f62b0 1548 #define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 1549 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
<> 128:9bcdf88f62b0 1550 #define ADC_ISR_AWD3_Pos (9U)
<> 128:9bcdf88f62b0 1551 #define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 1552 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
<> 128:9bcdf88f62b0 1553 #define ADC_ISR_JQOVF_Pos (10U)
<> 128:9bcdf88f62b0 1554 #define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 1555 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
<> 128:9bcdf88f62b0 1556
<> 128:9bcdf88f62b0 1557 /******************** Bit definition for ADC_IER register *******************/
<> 128:9bcdf88f62b0 1558 #define ADC_IER_ADRDYIE_Pos (0U)
<> 128:9bcdf88f62b0 1559 #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 1560 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
<> 128:9bcdf88f62b0 1561 #define ADC_IER_EOSMPIE_Pos (1U)
<> 128:9bcdf88f62b0 1562 #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 1563 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
<> 128:9bcdf88f62b0 1564 #define ADC_IER_EOCIE_Pos (2U)
<> 128:9bcdf88f62b0 1565 #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 1566 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
<> 128:9bcdf88f62b0 1567 #define ADC_IER_EOSIE_Pos (3U)
<> 128:9bcdf88f62b0 1568 #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 1569 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
<> 128:9bcdf88f62b0 1570 #define ADC_IER_OVRIE_Pos (4U)
<> 128:9bcdf88f62b0 1571 #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 1572 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
<> 128:9bcdf88f62b0 1573 #define ADC_IER_JEOCIE_Pos (5U)
<> 128:9bcdf88f62b0 1574 #define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 1575 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
<> 128:9bcdf88f62b0 1576 #define ADC_IER_JEOSIE_Pos (6U)
<> 128:9bcdf88f62b0 1577 #define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 1578 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
<> 128:9bcdf88f62b0 1579 #define ADC_IER_AWD1IE_Pos (7U)
<> 128:9bcdf88f62b0 1580 #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 1581 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
<> 128:9bcdf88f62b0 1582 #define ADC_IER_AWD2IE_Pos (8U)
<> 128:9bcdf88f62b0 1583 #define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 1584 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
<> 128:9bcdf88f62b0 1585 #define ADC_IER_AWD3IE_Pos (9U)
<> 128:9bcdf88f62b0 1586 #define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 1587 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
<> 128:9bcdf88f62b0 1588 #define ADC_IER_JQOVFIE_Pos (10U)
<> 128:9bcdf88f62b0 1589 #define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 1590 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
<> 128:9bcdf88f62b0 1591
<> 128:9bcdf88f62b0 1592 /* Legacy defines */
<> 128:9bcdf88f62b0 1593 #define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
<> 128:9bcdf88f62b0 1594 #define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
<> 128:9bcdf88f62b0 1595 #define ADC_IER_EOC (ADC_IER_EOCIE)
<> 128:9bcdf88f62b0 1596 #define ADC_IER_EOS (ADC_IER_EOSIE)
<> 128:9bcdf88f62b0 1597 #define ADC_IER_OVR (ADC_IER_OVRIE)
<> 128:9bcdf88f62b0 1598 #define ADC_IER_JEOC (ADC_IER_JEOCIE)
<> 128:9bcdf88f62b0 1599 #define ADC_IER_JEOS (ADC_IER_JEOSIE)
<> 128:9bcdf88f62b0 1600 #define ADC_IER_AWD1 (ADC_IER_AWD1IE)
<> 128:9bcdf88f62b0 1601 #define ADC_IER_AWD2 (ADC_IER_AWD2IE)
<> 128:9bcdf88f62b0 1602 #define ADC_IER_AWD3 (ADC_IER_AWD3IE)
<> 128:9bcdf88f62b0 1603 #define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
<> 128:9bcdf88f62b0 1604
<> 128:9bcdf88f62b0 1605 /******************** Bit definition for ADC_CR register ********************/
<> 128:9bcdf88f62b0 1606 #define ADC_CR_ADEN_Pos (0U)
<> 128:9bcdf88f62b0 1607 #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 1608 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
<> 128:9bcdf88f62b0 1609 #define ADC_CR_ADDIS_Pos (1U)
<> 128:9bcdf88f62b0 1610 #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 1611 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
<> 128:9bcdf88f62b0 1612 #define ADC_CR_ADSTART_Pos (2U)
<> 128:9bcdf88f62b0 1613 #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 1614 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
<> 128:9bcdf88f62b0 1615 #define ADC_CR_JADSTART_Pos (3U)
<> 128:9bcdf88f62b0 1616 #define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 1617 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
<> 128:9bcdf88f62b0 1618 #define ADC_CR_ADSTP_Pos (4U)
<> 128:9bcdf88f62b0 1619 #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 1620 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
<> 128:9bcdf88f62b0 1621 #define ADC_CR_JADSTP_Pos (5U)
<> 128:9bcdf88f62b0 1622 #define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 1623 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
<> 128:9bcdf88f62b0 1624 #define ADC_CR_ADVREGEN_Pos (28U)
<> 128:9bcdf88f62b0 1625 #define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 1626 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
<> 128:9bcdf88f62b0 1627 #define ADC_CR_DEEPPWD_Pos (29U)
<> 128:9bcdf88f62b0 1628 #define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 1629 #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
<> 128:9bcdf88f62b0 1630 #define ADC_CR_ADCALDIF_Pos (30U)
<> 128:9bcdf88f62b0 1631 #define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 1632 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
<> 128:9bcdf88f62b0 1633 #define ADC_CR_ADCAL_Pos (31U)
<> 128:9bcdf88f62b0 1634 #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 1635 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
<> 128:9bcdf88f62b0 1636
<> 128:9bcdf88f62b0 1637 /******************** Bit definition for ADC_CFGR register ******************/
<> 128:9bcdf88f62b0 1638 #define ADC_CFGR_DMAEN_Pos (0U)
<> 128:9bcdf88f62b0 1639 #define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 1640 #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
<> 128:9bcdf88f62b0 1641 #define ADC_CFGR_DMACFG_Pos (1U)
<> 128:9bcdf88f62b0 1642 #define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 1643 #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
<> 128:9bcdf88f62b0 1644
<> 128:9bcdf88f62b0 1645 #define ADC_CFGR_RES_Pos (3U)
<> 128:9bcdf88f62b0 1646 #define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
<> 128:9bcdf88f62b0 1647 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
<> 128:9bcdf88f62b0 1648 #define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 1649 #define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 1650
<> 128:9bcdf88f62b0 1651 #define ADC_CFGR_ALIGN_Pos (5U)
<> 128:9bcdf88f62b0 1652 #define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 1653 #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
<> 128:9bcdf88f62b0 1654
<> 128:9bcdf88f62b0 1655 #define ADC_CFGR_EXTSEL_Pos (6U)
<> 128:9bcdf88f62b0 1656 #define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
<> 128:9bcdf88f62b0 1657 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
<> 128:9bcdf88f62b0 1658 #define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 1659 #define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 1660 #define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 1661 #define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 1662
<> 128:9bcdf88f62b0 1663 #define ADC_CFGR_EXTEN_Pos (10U)
<> 128:9bcdf88f62b0 1664 #define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
<> 128:9bcdf88f62b0 1665 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
<> 128:9bcdf88f62b0 1666 #define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 1667 #define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 1668
<> 128:9bcdf88f62b0 1669 #define ADC_CFGR_OVRMOD_Pos (12U)
<> 128:9bcdf88f62b0 1670 #define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 1671 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
<> 128:9bcdf88f62b0 1672 #define ADC_CFGR_CONT_Pos (13U)
<> 128:9bcdf88f62b0 1673 #define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 1674 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
<> 128:9bcdf88f62b0 1675 #define ADC_CFGR_AUTDLY_Pos (14U)
<> 128:9bcdf88f62b0 1676 #define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 1677 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
<> 128:9bcdf88f62b0 1678
<> 128:9bcdf88f62b0 1679 #define ADC_CFGR_DISCEN_Pos (16U)
<> 128:9bcdf88f62b0 1680 #define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 1681 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
<> 128:9bcdf88f62b0 1682
<> 128:9bcdf88f62b0 1683 #define ADC_CFGR_DISCNUM_Pos (17U)
<> 128:9bcdf88f62b0 1684 #define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
<> 128:9bcdf88f62b0 1685 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
<> 128:9bcdf88f62b0 1686 #define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 1687 #define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 1688 #define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 1689
<> 128:9bcdf88f62b0 1690 #define ADC_CFGR_JDISCEN_Pos (20U)
<> 128:9bcdf88f62b0 1691 #define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 1692 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
<> 128:9bcdf88f62b0 1693 #define ADC_CFGR_JQM_Pos (21U)
<> 128:9bcdf88f62b0 1694 #define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 1695 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
<> 128:9bcdf88f62b0 1696 #define ADC_CFGR_AWD1SGL_Pos (22U)
<> 128:9bcdf88f62b0 1697 #define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 1698 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
<> 128:9bcdf88f62b0 1699 #define ADC_CFGR_AWD1EN_Pos (23U)
<> 128:9bcdf88f62b0 1700 #define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 1701 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
<> 128:9bcdf88f62b0 1702 #define ADC_CFGR_JAWD1EN_Pos (24U)
<> 128:9bcdf88f62b0 1703 #define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 1704 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
<> 128:9bcdf88f62b0 1705 #define ADC_CFGR_JAUTO_Pos (25U)
<> 128:9bcdf88f62b0 1706 #define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 1707 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
<> 128:9bcdf88f62b0 1708
<> 128:9bcdf88f62b0 1709 #define ADC_CFGR_AWD1CH_Pos (26U)
<> 128:9bcdf88f62b0 1710 #define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
<> 128:9bcdf88f62b0 1711 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
<> 128:9bcdf88f62b0 1712 #define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 1713 #define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 1714 #define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 1715 #define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 1716 #define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 1717
<> 128:9bcdf88f62b0 1718 #define ADC_CFGR_JQDIS_Pos (31U)
<> 128:9bcdf88f62b0 1719 #define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 1720 #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
<> 128:9bcdf88f62b0 1721
<> 128:9bcdf88f62b0 1722 /******************** Bit definition for ADC_CFGR2 register *****************/
<> 128:9bcdf88f62b0 1723 #define ADC_CFGR2_ROVSE_Pos (0U)
<> 128:9bcdf88f62b0 1724 #define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 1725 #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
<> 128:9bcdf88f62b0 1726 #define ADC_CFGR2_JOVSE_Pos (1U)
<> 128:9bcdf88f62b0 1727 #define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 1728 #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
<> 128:9bcdf88f62b0 1729
<> 128:9bcdf88f62b0 1730 #define ADC_CFGR2_OVSR_Pos (2U)
<> 128:9bcdf88f62b0 1731 #define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
<> 128:9bcdf88f62b0 1732 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
<> 128:9bcdf88f62b0 1733 #define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 1734 #define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 1735 #define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 1736
<> 128:9bcdf88f62b0 1737 #define ADC_CFGR2_OVSS_Pos (5U)
<> 128:9bcdf88f62b0 1738 #define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
<> 128:9bcdf88f62b0 1739 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
<> 128:9bcdf88f62b0 1740 #define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 1741 #define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 1742 #define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 1743 #define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 1744
<> 128:9bcdf88f62b0 1745 #define ADC_CFGR2_TROVS_Pos (9U)
<> 128:9bcdf88f62b0 1746 #define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 1747 #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
<> 128:9bcdf88f62b0 1748 #define ADC_CFGR2_ROVSM_Pos (10U)
<> 128:9bcdf88f62b0 1749 #define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 1750 #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
<> 128:9bcdf88f62b0 1751
<> 128:9bcdf88f62b0 1752 /******************** Bit definition for ADC_SMPR1 register *****************/
<> 128:9bcdf88f62b0 1753 #define ADC_SMPR1_SMP0_Pos (0U)
<> 128:9bcdf88f62b0 1754 #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
<> 128:9bcdf88f62b0 1755 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
<> 128:9bcdf88f62b0 1756 #define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 1757 #define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 1758 #define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 1759
<> 128:9bcdf88f62b0 1760 #define ADC_SMPR1_SMP1_Pos (3U)
<> 128:9bcdf88f62b0 1761 #define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
<> 128:9bcdf88f62b0 1762 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
<> 128:9bcdf88f62b0 1763 #define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 1764 #define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 1765 #define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 1766
<> 128:9bcdf88f62b0 1767 #define ADC_SMPR1_SMP2_Pos (6U)
<> 128:9bcdf88f62b0 1768 #define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
<> 128:9bcdf88f62b0 1769 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
<> 128:9bcdf88f62b0 1770 #define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 1771 #define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 1772 #define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 1773
<> 128:9bcdf88f62b0 1774 #define ADC_SMPR1_SMP3_Pos (9U)
<> 128:9bcdf88f62b0 1775 #define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
<> 128:9bcdf88f62b0 1776 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
<> 128:9bcdf88f62b0 1777 #define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 1778 #define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 1779 #define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 1780
<> 128:9bcdf88f62b0 1781 #define ADC_SMPR1_SMP4_Pos (12U)
<> 128:9bcdf88f62b0 1782 #define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
<> 128:9bcdf88f62b0 1783 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
<> 128:9bcdf88f62b0 1784 #define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 1785 #define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 1786 #define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 1787
<> 128:9bcdf88f62b0 1788 #define ADC_SMPR1_SMP5_Pos (15U)
<> 128:9bcdf88f62b0 1789 #define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
<> 128:9bcdf88f62b0 1790 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
<> 128:9bcdf88f62b0 1791 #define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 1792 #define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 1793 #define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 1794
<> 128:9bcdf88f62b0 1795 #define ADC_SMPR1_SMP6_Pos (18U)
<> 128:9bcdf88f62b0 1796 #define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
<> 128:9bcdf88f62b0 1797 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
<> 128:9bcdf88f62b0 1798 #define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 1799 #define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 1800 #define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 1801
<> 128:9bcdf88f62b0 1802 #define ADC_SMPR1_SMP7_Pos (21U)
<> 128:9bcdf88f62b0 1803 #define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
<> 128:9bcdf88f62b0 1804 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
<> 128:9bcdf88f62b0 1805 #define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 1806 #define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 1807 #define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 1808
<> 128:9bcdf88f62b0 1809 #define ADC_SMPR1_SMP8_Pos (24U)
<> 128:9bcdf88f62b0 1810 #define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
<> 128:9bcdf88f62b0 1811 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
<> 128:9bcdf88f62b0 1812 #define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 1813 #define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 1814 #define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 1815
<> 128:9bcdf88f62b0 1816 #define ADC_SMPR1_SMP9_Pos (27U)
<> 128:9bcdf88f62b0 1817 #define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
<> 128:9bcdf88f62b0 1818 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
<> 128:9bcdf88f62b0 1819 #define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 1820 #define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 1821 #define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 1822
<> 128:9bcdf88f62b0 1823 /******************** Bit definition for ADC_SMPR2 register *****************/
<> 128:9bcdf88f62b0 1824 #define ADC_SMPR2_SMP10_Pos (0U)
<> 128:9bcdf88f62b0 1825 #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
<> 128:9bcdf88f62b0 1826 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
<> 128:9bcdf88f62b0 1827 #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 1828 #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 1829 #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 1830
<> 128:9bcdf88f62b0 1831 #define ADC_SMPR2_SMP11_Pos (3U)
<> 128:9bcdf88f62b0 1832 #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
<> 128:9bcdf88f62b0 1833 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
<> 128:9bcdf88f62b0 1834 #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 1835 #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 1836 #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 1837
<> 128:9bcdf88f62b0 1838 #define ADC_SMPR2_SMP12_Pos (6U)
<> 128:9bcdf88f62b0 1839 #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
<> 128:9bcdf88f62b0 1840 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
<> 128:9bcdf88f62b0 1841 #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 1842 #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 1843 #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 1844
<> 128:9bcdf88f62b0 1845 #define ADC_SMPR2_SMP13_Pos (9U)
<> 128:9bcdf88f62b0 1846 #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
<> 128:9bcdf88f62b0 1847 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
<> 128:9bcdf88f62b0 1848 #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 1849 #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 1850 #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 1851
<> 128:9bcdf88f62b0 1852 #define ADC_SMPR2_SMP14_Pos (12U)
<> 128:9bcdf88f62b0 1853 #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
<> 128:9bcdf88f62b0 1854 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
<> 128:9bcdf88f62b0 1855 #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 1856 #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 1857 #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 1858
<> 128:9bcdf88f62b0 1859 #define ADC_SMPR2_SMP15_Pos (15U)
<> 128:9bcdf88f62b0 1860 #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
<> 128:9bcdf88f62b0 1861 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
<> 128:9bcdf88f62b0 1862 #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 1863 #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 1864 #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 1865
<> 128:9bcdf88f62b0 1866 #define ADC_SMPR2_SMP16_Pos (18U)
<> 128:9bcdf88f62b0 1867 #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
<> 128:9bcdf88f62b0 1868 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
<> 128:9bcdf88f62b0 1869 #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 1870 #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 1871 #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 1872
<> 128:9bcdf88f62b0 1873 #define ADC_SMPR2_SMP17_Pos (21U)
<> 128:9bcdf88f62b0 1874 #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
<> 128:9bcdf88f62b0 1875 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
<> 128:9bcdf88f62b0 1876 #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 1877 #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 1878 #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 1879
<> 128:9bcdf88f62b0 1880 #define ADC_SMPR2_SMP18_Pos (24U)
<> 128:9bcdf88f62b0 1881 #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
<> 128:9bcdf88f62b0 1882 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
<> 128:9bcdf88f62b0 1883 #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 1884 #define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 1885 #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 1886
<> 128:9bcdf88f62b0 1887 /******************** Bit definition for ADC_TR1 register *******************/
<> 128:9bcdf88f62b0 1888 #define ADC_TR1_LT1_Pos (0U)
<> 128:9bcdf88f62b0 1889 #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
<> 128:9bcdf88f62b0 1890 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
<> 128:9bcdf88f62b0 1891 #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 1892 #define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 1893 #define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 1894 #define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 1895 #define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 1896 #define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 1897 #define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 1898 #define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 1899 #define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 1900 #define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 1901 #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 1902 #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 1903
<> 128:9bcdf88f62b0 1904 #define ADC_TR1_HT1_Pos (16U)
<> 128:9bcdf88f62b0 1905 #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
<> 128:9bcdf88f62b0 1906 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
<> 128:9bcdf88f62b0 1907 #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 1908 #define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 1909 #define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 1910 #define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 1911 #define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 1912 #define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 1913 #define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 1914 #define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 1915 #define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 1916 #define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 1917 #define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 1918 #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 1919
<> 128:9bcdf88f62b0 1920 /******************** Bit definition for ADC_TR2 register *******************/
<> 128:9bcdf88f62b0 1921 #define ADC_TR2_LT2_Pos (0U)
<> 128:9bcdf88f62b0 1922 #define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 1923 #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
<> 128:9bcdf88f62b0 1924 #define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 1925 #define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 1926 #define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 1927 #define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 1928 #define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 1929 #define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 1930 #define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 1931 #define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 1932
<> 128:9bcdf88f62b0 1933 #define ADC_TR2_HT2_Pos (16U)
<> 128:9bcdf88f62b0 1934 #define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 1935 #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
<> 128:9bcdf88f62b0 1936 #define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 1937 #define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 1938 #define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 1939 #define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 1940 #define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 1941 #define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 1942 #define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 1943 #define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 1944
<> 128:9bcdf88f62b0 1945 /******************** Bit definition for ADC_TR3 register *******************/
<> 128:9bcdf88f62b0 1946 #define ADC_TR3_LT3_Pos (0U)
<> 128:9bcdf88f62b0 1947 #define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 1948 #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
<> 128:9bcdf88f62b0 1949 #define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 1950 #define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 1951 #define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 1952 #define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 1953 #define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 1954 #define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 1955 #define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 1956 #define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 1957
<> 128:9bcdf88f62b0 1958 #define ADC_TR3_HT3_Pos (16U)
<> 128:9bcdf88f62b0 1959 #define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 1960 #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
<> 128:9bcdf88f62b0 1961 #define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 1962 #define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 1963 #define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 1964 #define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 1965 #define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 1966 #define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 1967 #define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 1968 #define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 1969
<> 128:9bcdf88f62b0 1970 /******************** Bit definition for ADC_SQR1 register ******************/
<> 128:9bcdf88f62b0 1971 #define ADC_SQR1_L_Pos (0U)
<> 128:9bcdf88f62b0 1972 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 1973 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
<> 128:9bcdf88f62b0 1974 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 1975 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 1976 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 1977 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 1978
<> 128:9bcdf88f62b0 1979 #define ADC_SQR1_SQ1_Pos (6U)
<> 128:9bcdf88f62b0 1980 #define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
<> 128:9bcdf88f62b0 1981 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
<> 128:9bcdf88f62b0 1982 #define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 1983 #define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 1984 #define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 1985 #define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 1986 #define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 1987
<> 128:9bcdf88f62b0 1988 #define ADC_SQR1_SQ2_Pos (12U)
<> 128:9bcdf88f62b0 1989 #define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
<> 128:9bcdf88f62b0 1990 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
<> 128:9bcdf88f62b0 1991 #define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 1992 #define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 1993 #define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 1994 #define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 1995 #define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 1996
<> 128:9bcdf88f62b0 1997 #define ADC_SQR1_SQ3_Pos (18U)
<> 128:9bcdf88f62b0 1998 #define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
<> 128:9bcdf88f62b0 1999 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
<> 128:9bcdf88f62b0 2000 #define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 2001 #define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 2002 #define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 2003 #define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 2004 #define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 2005
<> 128:9bcdf88f62b0 2006 #define ADC_SQR1_SQ4_Pos (24U)
<> 128:9bcdf88f62b0 2007 #define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
<> 128:9bcdf88f62b0 2008 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
<> 128:9bcdf88f62b0 2009 #define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 2010 #define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 2011 #define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 2012 #define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 2013 #define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 2014
<> 128:9bcdf88f62b0 2015 /******************** Bit definition for ADC_SQR2 register ******************/
<> 128:9bcdf88f62b0 2016 #define ADC_SQR2_SQ5_Pos (0U)
<> 128:9bcdf88f62b0 2017 #define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
<> 128:9bcdf88f62b0 2018 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
<> 128:9bcdf88f62b0 2019 #define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2020 #define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2021 #define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2022 #define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2023 #define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2024
<> 128:9bcdf88f62b0 2025 #define ADC_SQR2_SQ6_Pos (6U)
<> 128:9bcdf88f62b0 2026 #define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
<> 128:9bcdf88f62b0 2027 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
<> 128:9bcdf88f62b0 2028 #define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2029 #define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 2030 #define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2031 #define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2032 #define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2033
<> 128:9bcdf88f62b0 2034 #define ADC_SQR2_SQ7_Pos (12U)
<> 128:9bcdf88f62b0 2035 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
<> 128:9bcdf88f62b0 2036 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
<> 128:9bcdf88f62b0 2037 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 2038 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 2039 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 2040 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 2041 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 2042
<> 128:9bcdf88f62b0 2043 #define ADC_SQR2_SQ8_Pos (18U)
<> 128:9bcdf88f62b0 2044 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
<> 128:9bcdf88f62b0 2045 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
<> 128:9bcdf88f62b0 2046 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 2047 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 2048 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 2049 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 2050 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 2051
<> 128:9bcdf88f62b0 2052 #define ADC_SQR2_SQ9_Pos (24U)
<> 128:9bcdf88f62b0 2053 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
<> 128:9bcdf88f62b0 2054 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
<> 128:9bcdf88f62b0 2055 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 2056 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 2057 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 2058 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 2059 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 2060
<> 128:9bcdf88f62b0 2061 /******************** Bit definition for ADC_SQR3 register ******************/
<> 128:9bcdf88f62b0 2062 #define ADC_SQR3_SQ10_Pos (0U)
<> 128:9bcdf88f62b0 2063 #define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
<> 128:9bcdf88f62b0 2064 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
<> 128:9bcdf88f62b0 2065 #define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2066 #define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2067 #define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2068 #define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2069 #define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2070
<> 128:9bcdf88f62b0 2071 #define ADC_SQR3_SQ11_Pos (6U)
<> 128:9bcdf88f62b0 2072 #define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
<> 128:9bcdf88f62b0 2073 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
<> 128:9bcdf88f62b0 2074 #define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2075 #define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 2076 #define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2077 #define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2078 #define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2079
<> 128:9bcdf88f62b0 2080 #define ADC_SQR3_SQ12_Pos (12U)
<> 128:9bcdf88f62b0 2081 #define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
<> 128:9bcdf88f62b0 2082 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
<> 128:9bcdf88f62b0 2083 #define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 2084 #define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 2085 #define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 2086 #define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 2087 #define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 2088
<> 128:9bcdf88f62b0 2089 #define ADC_SQR3_SQ13_Pos (18U)
<> 128:9bcdf88f62b0 2090 #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
<> 128:9bcdf88f62b0 2091 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
<> 128:9bcdf88f62b0 2092 #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 2093 #define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 2094 #define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 2095 #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 2096 #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 2097
<> 128:9bcdf88f62b0 2098 #define ADC_SQR3_SQ14_Pos (24U)
<> 128:9bcdf88f62b0 2099 #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
<> 128:9bcdf88f62b0 2100 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
<> 128:9bcdf88f62b0 2101 #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 2102 #define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 2103 #define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 2104 #define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 2105 #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 2106
<> 128:9bcdf88f62b0 2107 /******************** Bit definition for ADC_SQR4 register ******************/
<> 128:9bcdf88f62b0 2108 #define ADC_SQR4_SQ15_Pos (0U)
<> 128:9bcdf88f62b0 2109 #define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
<> 128:9bcdf88f62b0 2110 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
<> 128:9bcdf88f62b0 2111 #define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2112 #define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2113 #define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2114 #define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2115 #define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2116
<> 128:9bcdf88f62b0 2117 #define ADC_SQR4_SQ16_Pos (6U)
<> 128:9bcdf88f62b0 2118 #define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
<> 128:9bcdf88f62b0 2119 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
<> 128:9bcdf88f62b0 2120 #define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2121 #define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 2122 #define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2123 #define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2124 #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2125
<> 128:9bcdf88f62b0 2126 /******************** Bit definition for ADC_DR register ********************/
<> 128:9bcdf88f62b0 2127 #define ADC_DR_RDATA_Pos (0U)
<> 128:9bcdf88f62b0 2128 #define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 2129 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
<> 128:9bcdf88f62b0 2130 #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2131 #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2132 #define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2133 #define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2134 #define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2135 #define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 2136 #define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2137 #define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 2138 #define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2139 #define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2140 #define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2141 #define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 2142 #define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 2143 #define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 2144 #define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 2145 #define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 2146
<> 128:9bcdf88f62b0 2147 /******************** Bit definition for ADC_JSQR register ******************/
<> 128:9bcdf88f62b0 2148 #define ADC_JSQR_JL_Pos (0U)
<> 128:9bcdf88f62b0 2149 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 2150 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
<> 128:9bcdf88f62b0 2151 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2152 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2153
<> 128:9bcdf88f62b0 2154 #define ADC_JSQR_JEXTSEL_Pos (2U)
<> 128:9bcdf88f62b0 2155 #define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
<> 128:9bcdf88f62b0 2156 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
<> 128:9bcdf88f62b0 2157 #define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2158 #define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2159 #define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2160 #define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 2161
<> 128:9bcdf88f62b0 2162 #define ADC_JSQR_JEXTEN_Pos (6U)
<> 128:9bcdf88f62b0 2163 #define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
<> 128:9bcdf88f62b0 2164 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
<> 128:9bcdf88f62b0 2165 #define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2166 #define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 2167
<> 128:9bcdf88f62b0 2168 #define ADC_JSQR_JSQ1_Pos (8U)
<> 128:9bcdf88f62b0 2169 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
<> 128:9bcdf88f62b0 2170 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
<> 128:9bcdf88f62b0 2171 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2172 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2173 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2174 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 2175 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 2176
<> 128:9bcdf88f62b0 2177 #define ADC_JSQR_JSQ2_Pos (14U)
<> 128:9bcdf88f62b0 2178 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
<> 128:9bcdf88f62b0 2179 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
<> 128:9bcdf88f62b0 2180 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 2181 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 2182 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 2183 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 2184 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 2185
<> 128:9bcdf88f62b0 2186 #define ADC_JSQR_JSQ3_Pos (20U)
<> 128:9bcdf88f62b0 2187 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
<> 128:9bcdf88f62b0 2188 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
<> 128:9bcdf88f62b0 2189 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 2190 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 2191 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 2192 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 2193 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 2194
<> 128:9bcdf88f62b0 2195 #define ADC_JSQR_JSQ4_Pos (26U)
<> 128:9bcdf88f62b0 2196 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
<> 128:9bcdf88f62b0 2197 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
<> 128:9bcdf88f62b0 2198 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 2199 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 2200 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 2201 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 2202 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 2203
<> 128:9bcdf88f62b0 2204
<> 128:9bcdf88f62b0 2205 /******************** Bit definition for ADC_OFR1 register ******************/
<> 128:9bcdf88f62b0 2206 #define ADC_OFR1_OFFSET1_Pos (0U)
<> 128:9bcdf88f62b0 2207 #define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
<> 128:9bcdf88f62b0 2208 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
<> 128:9bcdf88f62b0 2209 #define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2210 #define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2211 #define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2212 #define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2213 #define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2214 #define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 2215 #define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2216 #define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 2217 #define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2218 #define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2219 #define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2220 #define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 2221
<> 128:9bcdf88f62b0 2222 #define ADC_OFR1_OFFSET1_CH_Pos (26U)
<> 128:9bcdf88f62b0 2223 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
<> 128:9bcdf88f62b0 2224 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
<> 128:9bcdf88f62b0 2225 #define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 2226 #define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 2227 #define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 2228 #define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 2229 #define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 2230
<> 128:9bcdf88f62b0 2231 #define ADC_OFR1_OFFSET1_EN_Pos (31U)
<> 128:9bcdf88f62b0 2232 #define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 2233 #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
<> 128:9bcdf88f62b0 2234
<> 128:9bcdf88f62b0 2235 /******************** Bit definition for ADC_OFR2 register ******************/
<> 128:9bcdf88f62b0 2236 #define ADC_OFR2_OFFSET2_Pos (0U)
<> 128:9bcdf88f62b0 2237 #define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
<> 128:9bcdf88f62b0 2238 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
<> 128:9bcdf88f62b0 2239 #define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2240 #define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2241 #define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2242 #define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2243 #define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2244 #define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 2245 #define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2246 #define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 2247 #define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2248 #define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2249 #define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2250 #define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 2251
<> 128:9bcdf88f62b0 2252 #define ADC_OFR2_OFFSET2_CH_Pos (26U)
<> 128:9bcdf88f62b0 2253 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
<> 128:9bcdf88f62b0 2254 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
<> 128:9bcdf88f62b0 2255 #define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 2256 #define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 2257 #define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 2258 #define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 2259 #define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 2260
<> 128:9bcdf88f62b0 2261 #define ADC_OFR2_OFFSET2_EN_Pos (31U)
<> 128:9bcdf88f62b0 2262 #define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 2263 #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
<> 128:9bcdf88f62b0 2264
<> 128:9bcdf88f62b0 2265 /******************** Bit definition for ADC_OFR3 register ******************/
<> 128:9bcdf88f62b0 2266 #define ADC_OFR3_OFFSET3_Pos (0U)
<> 128:9bcdf88f62b0 2267 #define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
<> 128:9bcdf88f62b0 2268 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
<> 128:9bcdf88f62b0 2269 #define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2270 #define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2271 #define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2272 #define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2273 #define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2274 #define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 2275 #define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2276 #define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 2277 #define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2278 #define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2279 #define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2280 #define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 2281
<> 128:9bcdf88f62b0 2282 #define ADC_OFR3_OFFSET3_CH_Pos (26U)
<> 128:9bcdf88f62b0 2283 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
<> 128:9bcdf88f62b0 2284 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
<> 128:9bcdf88f62b0 2285 #define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 2286 #define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 2287 #define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 2288 #define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 2289 #define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 2290
<> 128:9bcdf88f62b0 2291 #define ADC_OFR3_OFFSET3_EN_Pos (31U)
<> 128:9bcdf88f62b0 2292 #define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 2293 #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
<> 128:9bcdf88f62b0 2294
<> 128:9bcdf88f62b0 2295 /******************** Bit definition for ADC_OFR4 register ******************/
<> 128:9bcdf88f62b0 2296 #define ADC_OFR4_OFFSET4_Pos (0U)
<> 128:9bcdf88f62b0 2297 #define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
<> 128:9bcdf88f62b0 2298 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
<> 128:9bcdf88f62b0 2299 #define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2300 #define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2301 #define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2302 #define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2303 #define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2304 #define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 2305 #define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2306 #define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 2307 #define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2308 #define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2309 #define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2310 #define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 2311
<> 128:9bcdf88f62b0 2312 #define ADC_OFR4_OFFSET4_CH_Pos (26U)
<> 128:9bcdf88f62b0 2313 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
<> 128:9bcdf88f62b0 2314 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
<> 128:9bcdf88f62b0 2315 #define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 2316 #define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 2317 #define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 2318 #define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 2319 #define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 2320
<> 128:9bcdf88f62b0 2321 #define ADC_OFR4_OFFSET4_EN_Pos (31U)
<> 128:9bcdf88f62b0 2322 #define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 2323 #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
<> 128:9bcdf88f62b0 2324
<> 128:9bcdf88f62b0 2325 /******************** Bit definition for ADC_JDR1 register ******************/
<> 128:9bcdf88f62b0 2326 #define ADC_JDR1_JDATA_Pos (0U)
<> 128:9bcdf88f62b0 2327 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 2328 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
<> 128:9bcdf88f62b0 2329 #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2330 #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2331 #define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2332 #define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2333 #define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2334 #define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 2335 #define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2336 #define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 2337 #define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2338 #define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2339 #define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2340 #define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 2341 #define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 2342 #define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 2343 #define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 2344 #define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 2345
<> 128:9bcdf88f62b0 2346 /******************** Bit definition for ADC_JDR2 register ******************/
<> 128:9bcdf88f62b0 2347 #define ADC_JDR2_JDATA_Pos (0U)
<> 128:9bcdf88f62b0 2348 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 2349 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
<> 128:9bcdf88f62b0 2350 #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2351 #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2352 #define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2353 #define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2354 #define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2355 #define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 2356 #define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2357 #define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 2358 #define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2359 #define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2360 #define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2361 #define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 2362 #define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 2363 #define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 2364 #define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 2365 #define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 2366
<> 128:9bcdf88f62b0 2367 /******************** Bit definition for ADC_JDR3 register ******************/
<> 128:9bcdf88f62b0 2368 #define ADC_JDR3_JDATA_Pos (0U)
<> 128:9bcdf88f62b0 2369 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 2370 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
<> 128:9bcdf88f62b0 2371 #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2372 #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2373 #define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2374 #define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2375 #define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2376 #define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 2377 #define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2378 #define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 2379 #define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2380 #define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2381 #define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2382 #define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 2383 #define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 2384 #define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 2385 #define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 2386 #define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 2387
<> 128:9bcdf88f62b0 2388 /******************** Bit definition for ADC_JDR4 register ******************/
<> 128:9bcdf88f62b0 2389 #define ADC_JDR4_JDATA_Pos (0U)
<> 128:9bcdf88f62b0 2390 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 2391 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
<> 128:9bcdf88f62b0 2392 #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2393 #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2394 #define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2395 #define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2396 #define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2397 #define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 2398 #define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2399 #define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 2400 #define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2401 #define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2402 #define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2403 #define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 2404 #define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 2405 #define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 2406 #define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 2407 #define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 2408
<> 128:9bcdf88f62b0 2409 /******************** Bit definition for ADC_AWD2CR register ****************/
<> 128:9bcdf88f62b0 2410 #define ADC_AWD2CR_AWD2CH_Pos (0U)
<> 128:9bcdf88f62b0 2411 #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
<> 128:9bcdf88f62b0 2412 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
<> 128:9bcdf88f62b0 2413 #define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2414 #define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2415 #define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2416 #define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2417 #define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2418 #define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 2419 #define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2420 #define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 2421 #define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2422 #define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2423 #define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2424 #define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 2425 #define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 2426 #define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 2427 #define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 2428 #define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 2429 #define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 2430 #define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 2431 #define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 2432
<> 128:9bcdf88f62b0 2433 /******************** Bit definition for ADC_AWD3CR register ****************/
<> 128:9bcdf88f62b0 2434 #define ADC_AWD3CR_AWD3CH_Pos (0U)
<> 128:9bcdf88f62b0 2435 #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
<> 128:9bcdf88f62b0 2436 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
<> 128:9bcdf88f62b0 2437 #define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2438 #define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2439 #define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2440 #define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2441 #define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2442 #define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 2443 #define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2444 #define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 2445 #define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2446 #define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2447 #define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2448 #define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 2449 #define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 2450 #define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 2451 #define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 2452 #define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 2453 #define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 2454 #define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 2455 #define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 2456
<> 128:9bcdf88f62b0 2457 /******************** Bit definition for ADC_DIFSEL register ****************/
<> 128:9bcdf88f62b0 2458 #define ADC_DIFSEL_DIFSEL_Pos (0U)
<> 128:9bcdf88f62b0 2459 #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
<> 128:9bcdf88f62b0 2460 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
<> 128:9bcdf88f62b0 2461 #define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2462 #define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2463 #define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2464 #define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2465 #define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2466 #define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 2467 #define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2468 #define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 2469 #define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2470 #define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2471 #define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2472 #define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 2473 #define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 2474 #define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 2475 #define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 2476 #define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 2477 #define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 2478 #define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 2479 #define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 2480
<> 128:9bcdf88f62b0 2481 /******************** Bit definition for ADC_CALFACT register ***************/
<> 128:9bcdf88f62b0 2482 #define ADC_CALFACT_CALFACT_S_Pos (0U)
<> 128:9bcdf88f62b0 2483 #define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
<> 128:9bcdf88f62b0 2484 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
<> 128:9bcdf88f62b0 2485 #define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2486 #define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2487 #define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2488 #define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2489 #define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2490 #define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 2491 #define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2492
<> 128:9bcdf88f62b0 2493 #define ADC_CALFACT_CALFACT_D_Pos (16U)
<> 128:9bcdf88f62b0 2494 #define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
<> 128:9bcdf88f62b0 2495 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
<> 128:9bcdf88f62b0 2496 #define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 2497 #define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 2498 #define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 2499 #define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 2500 #define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 2501 #define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 2502 #define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 2503
<> 128:9bcdf88f62b0 2504 /************************* ADC Common registers *****************************/
<> 128:9bcdf88f62b0 2505 /******************** Bit definition for ADC_CSR register *******************/
<> 128:9bcdf88f62b0 2506 #define ADC_CSR_ADRDY_MST_Pos (0U)
<> 128:9bcdf88f62b0 2507 #define ADC_CSR_ADRDY_MST_Msk (0x1U << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2508 #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
<> 128:9bcdf88f62b0 2509 #define ADC_CSR_EOSMP_MST_Pos (1U)
<> 128:9bcdf88f62b0 2510 #define ADC_CSR_EOSMP_MST_Msk (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2511 #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
<> 128:9bcdf88f62b0 2512 #define ADC_CSR_EOC_MST_Pos (2U)
<> 128:9bcdf88f62b0 2513 #define ADC_CSR_EOC_MST_Msk (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2514 #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
<> 128:9bcdf88f62b0 2515 #define ADC_CSR_EOS_MST_Pos (3U)
<> 128:9bcdf88f62b0 2516 #define ADC_CSR_EOS_MST_Msk (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2517 #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
<> 128:9bcdf88f62b0 2518 #define ADC_CSR_OVR_MST_Pos (4U)
<> 128:9bcdf88f62b0 2519 #define ADC_CSR_OVR_MST_Msk (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2520 #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
<> 128:9bcdf88f62b0 2521 #define ADC_CSR_JEOC_MST_Pos (5U)
<> 128:9bcdf88f62b0 2522 #define ADC_CSR_JEOC_MST_Msk (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 2523 #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
<> 128:9bcdf88f62b0 2524 #define ADC_CSR_JEOS_MST_Pos (6U)
<> 128:9bcdf88f62b0 2525 #define ADC_CSR_JEOS_MST_Msk (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2526 #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
<> 128:9bcdf88f62b0 2527 #define ADC_CSR_AWD1_MST_Pos (7U)
<> 128:9bcdf88f62b0 2528 #define ADC_CSR_AWD1_MST_Msk (0x1U << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 2529 #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
<> 128:9bcdf88f62b0 2530 #define ADC_CSR_AWD2_MST_Pos (8U)
<> 128:9bcdf88f62b0 2531 #define ADC_CSR_AWD2_MST_Msk (0x1U << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2532 #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
<> 128:9bcdf88f62b0 2533 #define ADC_CSR_AWD3_MST_Pos (9U)
<> 128:9bcdf88f62b0 2534 #define ADC_CSR_AWD3_MST_Msk (0x1U << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2535 #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
<> 128:9bcdf88f62b0 2536 #define ADC_CSR_JQOVF_MST_Pos (10U)
<> 128:9bcdf88f62b0 2537 #define ADC_CSR_JQOVF_MST_Msk (0x1U << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2538 #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */
<> 128:9bcdf88f62b0 2539
<> 128:9bcdf88f62b0 2540 #define ADC_CSR_ADRDY_SLV_Pos (16U)
<> 128:9bcdf88f62b0 2541 #define ADC_CSR_ADRDY_SLV_Msk (0x1U << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 2542 #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
<> 128:9bcdf88f62b0 2543 #define ADC_CSR_EOSMP_SLV_Pos (17U)
<> 128:9bcdf88f62b0 2544 #define ADC_CSR_EOSMP_SLV_Msk (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 2545 #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
<> 128:9bcdf88f62b0 2546 #define ADC_CSR_EOC_SLV_Pos (18U)
<> 128:9bcdf88f62b0 2547 #define ADC_CSR_EOC_SLV_Msk (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 2548 #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
<> 128:9bcdf88f62b0 2549 #define ADC_CSR_EOS_SLV_Pos (19U)
<> 128:9bcdf88f62b0 2550 #define ADC_CSR_EOS_SLV_Msk (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 2551 #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
<> 128:9bcdf88f62b0 2552 #define ADC_CSR_OVR_SLV_Pos (20U)
<> 128:9bcdf88f62b0 2553 #define ADC_CSR_OVR_SLV_Msk (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 2554 #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
<> 128:9bcdf88f62b0 2555 #define ADC_CSR_JEOC_SLV_Pos (21U)
<> 128:9bcdf88f62b0 2556 #define ADC_CSR_JEOC_SLV_Msk (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 2557 #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
<> 128:9bcdf88f62b0 2558 #define ADC_CSR_JEOS_SLV_Pos (22U)
<> 128:9bcdf88f62b0 2559 #define ADC_CSR_JEOS_SLV_Msk (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 2560 #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
<> 128:9bcdf88f62b0 2561 #define ADC_CSR_AWD1_SLV_Pos (23U)
<> 128:9bcdf88f62b0 2562 #define ADC_CSR_AWD1_SLV_Msk (0x1U << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 2563 #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
<> 128:9bcdf88f62b0 2564 #define ADC_CSR_AWD2_SLV_Pos (24U)
<> 128:9bcdf88f62b0 2565 #define ADC_CSR_AWD2_SLV_Msk (0x1U << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 2566 #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
<> 128:9bcdf88f62b0 2567 #define ADC_CSR_AWD3_SLV_Pos (25U)
<> 128:9bcdf88f62b0 2568 #define ADC_CSR_AWD3_SLV_Msk (0x1U << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 2569 #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
<> 128:9bcdf88f62b0 2570 #define ADC_CSR_JQOVF_SLV_Pos (26U)
<> 128:9bcdf88f62b0 2571 #define ADC_CSR_JQOVF_SLV_Msk (0x1U << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 2572 #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */
<> 128:9bcdf88f62b0 2573
<> 128:9bcdf88f62b0 2574 /******************** Bit definition for ADC_CCR register *******************/
<> 128:9bcdf88f62b0 2575 #define ADC_CCR_DUAL_Pos (0U)
<> 128:9bcdf88f62b0 2576 #define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
<> 128:9bcdf88f62b0 2577 #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
<> 128:9bcdf88f62b0 2578 #define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2579 #define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2580 #define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2581 #define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2582 #define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2583
<> 128:9bcdf88f62b0 2584 #define ADC_CCR_DELAY_Pos (8U)
<> 128:9bcdf88f62b0 2585 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
<> 128:9bcdf88f62b0 2586 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
<> 128:9bcdf88f62b0 2587 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2588 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2589 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2590 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 2591
<> 128:9bcdf88f62b0 2592 #define ADC_CCR_DMACFG_Pos (13U)
<> 128:9bcdf88f62b0 2593 #define ADC_CCR_DMACFG_Msk (0x1U << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 2594 #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
<> 128:9bcdf88f62b0 2595
<> 128:9bcdf88f62b0 2596 #define ADC_CCR_MDMA_Pos (14U)
<> 128:9bcdf88f62b0 2597 #define ADC_CCR_MDMA_Msk (0x3U << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
<> 128:9bcdf88f62b0 2598 #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
<> 128:9bcdf88f62b0 2599 #define ADC_CCR_MDMA_0 (0x1U << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 2600 #define ADC_CCR_MDMA_1 (0x2U << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 2601
<> 128:9bcdf88f62b0 2602 #define ADC_CCR_CKMODE_Pos (16U)
<> 128:9bcdf88f62b0 2603 #define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
<> 128:9bcdf88f62b0 2604 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
<> 128:9bcdf88f62b0 2605 #define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 2606 #define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 2607
<> 128:9bcdf88f62b0 2608 #define ADC_CCR_PRESC_Pos (18U)
<> 128:9bcdf88f62b0 2609 #define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
<> 128:9bcdf88f62b0 2610 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
<> 128:9bcdf88f62b0 2611 #define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 2612 #define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 2613 #define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 2614 #define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 2615
<> 128:9bcdf88f62b0 2616 #define ADC_CCR_VREFEN_Pos (22U)
<> 128:9bcdf88f62b0 2617 #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 2618 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
<> 128:9bcdf88f62b0 2619 #define ADC_CCR_TSEN_Pos (23U)
<> 128:9bcdf88f62b0 2620 #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 2621 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
<> 128:9bcdf88f62b0 2622 #define ADC_CCR_VBATEN_Pos (24U)
<> 128:9bcdf88f62b0 2623 #define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 2624 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
<> 128:9bcdf88f62b0 2625
<> 128:9bcdf88f62b0 2626 /******************** Bit definition for ADC_CDR register *******************/
<> 128:9bcdf88f62b0 2627 #define ADC_CDR_RDATA_MST_Pos (0U)
<> 128:9bcdf88f62b0 2628 #define ADC_CDR_RDATA_MST_Msk (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 2629 #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
<> 128:9bcdf88f62b0 2630 #define ADC_CDR_RDATA_MST_0 (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2631 #define ADC_CDR_RDATA_MST_1 (0x0002U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2632 #define ADC_CDR_RDATA_MST_2 (0x0004U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2633 #define ADC_CDR_RDATA_MST_3 (0x0008U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2634 #define ADC_CDR_RDATA_MST_4 (0x0010U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2635 #define ADC_CDR_RDATA_MST_5 (0x0020U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 2636 #define ADC_CDR_RDATA_MST_6 (0x0040U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2637 #define ADC_CDR_RDATA_MST_7 (0x0080U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 2638 #define ADC_CDR_RDATA_MST_8 (0x0100U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2639 #define ADC_CDR_RDATA_MST_9 (0x0200U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2640 #define ADC_CDR_RDATA_MST_10 (0x0400U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2641 #define ADC_CDR_RDATA_MST_11 (0x0800U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 2642 #define ADC_CDR_RDATA_MST_12 (0x1000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 2643 #define ADC_CDR_RDATA_MST_13 (0x2000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 2644 #define ADC_CDR_RDATA_MST_14 (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 2645 #define ADC_CDR_RDATA_MST_15 (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 2646
<> 128:9bcdf88f62b0 2647 #define ADC_CDR_RDATA_SLV_Pos (16U)
<> 128:9bcdf88f62b0 2648 #define ADC_CDR_RDATA_SLV_Msk (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
<> 128:9bcdf88f62b0 2649 #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
<> 128:9bcdf88f62b0 2650 #define ADC_CDR_RDATA_SLV_0 (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 2651 #define ADC_CDR_RDATA_SLV_1 (0x0002U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 2652 #define ADC_CDR_RDATA_SLV_2 (0x0004U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 2653 #define ADC_CDR_RDATA_SLV_3 (0x0008U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 2654 #define ADC_CDR_RDATA_SLV_4 (0x0010U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 2655 #define ADC_CDR_RDATA_SLV_5 (0x0020U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 2656 #define ADC_CDR_RDATA_SLV_6 (0x0040U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 2657 #define ADC_CDR_RDATA_SLV_7 (0x0080U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 2658 #define ADC_CDR_RDATA_SLV_8 (0x0100U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 2659 #define ADC_CDR_RDATA_SLV_9 (0x0200U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 2660 #define ADC_CDR_RDATA_SLV_10 (0x0400U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 2661 #define ADC_CDR_RDATA_SLV_11 (0x0800U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 2662 #define ADC_CDR_RDATA_SLV_12 (0x1000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 2663 #define ADC_CDR_RDATA_SLV_13 (0x2000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 2664 #define ADC_CDR_RDATA_SLV_14 (0x4000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 2665 #define ADC_CDR_RDATA_SLV_15 (0x8000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 2666
<> 128:9bcdf88f62b0 2667 /******************************************************************************/
<> 128:9bcdf88f62b0 2668 /* */
<> 128:9bcdf88f62b0 2669 /* Controller Area Network */
<> 128:9bcdf88f62b0 2670 /* */
<> 128:9bcdf88f62b0 2671 /******************************************************************************/
<> 128:9bcdf88f62b0 2672 /******************* Bit definition for CAN_MCR register ********************/
<> 128:9bcdf88f62b0 2673 #define CAN_MCR_INRQ_Pos (0U)
<> 128:9bcdf88f62b0 2674 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2675 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
<> 128:9bcdf88f62b0 2676 #define CAN_MCR_SLEEP_Pos (1U)
<> 128:9bcdf88f62b0 2677 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2678 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
<> 128:9bcdf88f62b0 2679 #define CAN_MCR_TXFP_Pos (2U)
<> 128:9bcdf88f62b0 2680 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2681 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
<> 128:9bcdf88f62b0 2682 #define CAN_MCR_RFLM_Pos (3U)
<> 128:9bcdf88f62b0 2683 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2684 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
<> 128:9bcdf88f62b0 2685 #define CAN_MCR_NART_Pos (4U)
<> 128:9bcdf88f62b0 2686 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2687 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
<> 128:9bcdf88f62b0 2688 #define CAN_MCR_AWUM_Pos (5U)
<> 128:9bcdf88f62b0 2689 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 2690 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
<> 128:9bcdf88f62b0 2691 #define CAN_MCR_ABOM_Pos (6U)
<> 128:9bcdf88f62b0 2692 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2693 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
<> 128:9bcdf88f62b0 2694 #define CAN_MCR_TTCM_Pos (7U)
<> 128:9bcdf88f62b0 2695 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 2696 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
<> 128:9bcdf88f62b0 2697 #define CAN_MCR_RESET_Pos (15U)
<> 128:9bcdf88f62b0 2698 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 2699 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
<> 128:9bcdf88f62b0 2700
<> 128:9bcdf88f62b0 2701 /******************* Bit definition for CAN_MSR register ********************/
<> 128:9bcdf88f62b0 2702 #define CAN_MSR_INAK_Pos (0U)
<> 128:9bcdf88f62b0 2703 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2704 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
<> 128:9bcdf88f62b0 2705 #define CAN_MSR_SLAK_Pos (1U)
<> 128:9bcdf88f62b0 2706 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2707 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
<> 128:9bcdf88f62b0 2708 #define CAN_MSR_ERRI_Pos (2U)
<> 128:9bcdf88f62b0 2709 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2710 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
<> 128:9bcdf88f62b0 2711 #define CAN_MSR_WKUI_Pos (3U)
<> 128:9bcdf88f62b0 2712 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2713 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
<> 128:9bcdf88f62b0 2714 #define CAN_MSR_SLAKI_Pos (4U)
<> 128:9bcdf88f62b0 2715 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2716 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
<> 128:9bcdf88f62b0 2717 #define CAN_MSR_TXM_Pos (8U)
<> 128:9bcdf88f62b0 2718 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2719 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
<> 128:9bcdf88f62b0 2720 #define CAN_MSR_RXM_Pos (9U)
<> 128:9bcdf88f62b0 2721 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2722 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
<> 128:9bcdf88f62b0 2723 #define CAN_MSR_SAMP_Pos (10U)
<> 128:9bcdf88f62b0 2724 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2725 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
<> 128:9bcdf88f62b0 2726 #define CAN_MSR_RX_Pos (11U)
<> 128:9bcdf88f62b0 2727 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 2728 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
<> 128:9bcdf88f62b0 2729
<> 128:9bcdf88f62b0 2730 /******************* Bit definition for CAN_TSR register ********************/
<> 128:9bcdf88f62b0 2731 #define CAN_TSR_RQCP0_Pos (0U)
<> 128:9bcdf88f62b0 2732 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2733 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
<> 128:9bcdf88f62b0 2734 #define CAN_TSR_TXOK0_Pos (1U)
<> 128:9bcdf88f62b0 2735 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2736 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
<> 128:9bcdf88f62b0 2737 #define CAN_TSR_ALST0_Pos (2U)
<> 128:9bcdf88f62b0 2738 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2739 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
<> 128:9bcdf88f62b0 2740 #define CAN_TSR_TERR0_Pos (3U)
<> 128:9bcdf88f62b0 2741 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2742 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
<> 128:9bcdf88f62b0 2743 #define CAN_TSR_ABRQ0_Pos (7U)
<> 128:9bcdf88f62b0 2744 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 2745 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
<> 128:9bcdf88f62b0 2746 #define CAN_TSR_RQCP1_Pos (8U)
<> 128:9bcdf88f62b0 2747 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2748 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
<> 128:9bcdf88f62b0 2749 #define CAN_TSR_TXOK1_Pos (9U)
<> 128:9bcdf88f62b0 2750 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2751 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
<> 128:9bcdf88f62b0 2752 #define CAN_TSR_ALST1_Pos (10U)
<> 128:9bcdf88f62b0 2753 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2754 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
<> 128:9bcdf88f62b0 2755 #define CAN_TSR_TERR1_Pos (11U)
<> 128:9bcdf88f62b0 2756 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 2757 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
<> 128:9bcdf88f62b0 2758 #define CAN_TSR_ABRQ1_Pos (15U)
<> 128:9bcdf88f62b0 2759 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 2760 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
<> 128:9bcdf88f62b0 2761 #define CAN_TSR_RQCP2_Pos (16U)
<> 128:9bcdf88f62b0 2762 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 2763 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
<> 128:9bcdf88f62b0 2764 #define CAN_TSR_TXOK2_Pos (17U)
<> 128:9bcdf88f62b0 2765 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 2766 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
<> 128:9bcdf88f62b0 2767 #define CAN_TSR_ALST2_Pos (18U)
<> 128:9bcdf88f62b0 2768 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 2769 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
<> 128:9bcdf88f62b0 2770 #define CAN_TSR_TERR2_Pos (19U)
<> 128:9bcdf88f62b0 2771 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 2772 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
<> 128:9bcdf88f62b0 2773 #define CAN_TSR_ABRQ2_Pos (23U)
<> 128:9bcdf88f62b0 2774 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 2775 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
<> 128:9bcdf88f62b0 2776 #define CAN_TSR_CODE_Pos (24U)
<> 128:9bcdf88f62b0 2777 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
<> 128:9bcdf88f62b0 2778 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
<> 128:9bcdf88f62b0 2779
<> 128:9bcdf88f62b0 2780 #define CAN_TSR_TME_Pos (26U)
<> 128:9bcdf88f62b0 2781 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
<> 128:9bcdf88f62b0 2782 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
<> 128:9bcdf88f62b0 2783 #define CAN_TSR_TME0_Pos (26U)
<> 128:9bcdf88f62b0 2784 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 2785 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
<> 128:9bcdf88f62b0 2786 #define CAN_TSR_TME1_Pos (27U)
<> 128:9bcdf88f62b0 2787 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 2788 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
<> 128:9bcdf88f62b0 2789 #define CAN_TSR_TME2_Pos (28U)
<> 128:9bcdf88f62b0 2790 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 2791 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
<> 128:9bcdf88f62b0 2792
<> 128:9bcdf88f62b0 2793 #define CAN_TSR_LOW_Pos (29U)
<> 128:9bcdf88f62b0 2794 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
<> 128:9bcdf88f62b0 2795 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
<> 128:9bcdf88f62b0 2796 #define CAN_TSR_LOW0_Pos (29U)
<> 128:9bcdf88f62b0 2797 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 2798 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
<> 128:9bcdf88f62b0 2799 #define CAN_TSR_LOW1_Pos (30U)
<> 128:9bcdf88f62b0 2800 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 2801 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
<> 128:9bcdf88f62b0 2802 #define CAN_TSR_LOW2_Pos (31U)
<> 128:9bcdf88f62b0 2803 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 2804 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
<> 128:9bcdf88f62b0 2805
<> 128:9bcdf88f62b0 2806 /******************* Bit definition for CAN_RF0R register *******************/
<> 128:9bcdf88f62b0 2807 #define CAN_RF0R_FMP0_Pos (0U)
<> 128:9bcdf88f62b0 2808 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 2809 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
<> 128:9bcdf88f62b0 2810 #define CAN_RF0R_FULL0_Pos (3U)
<> 128:9bcdf88f62b0 2811 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2812 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
<> 128:9bcdf88f62b0 2813 #define CAN_RF0R_FOVR0_Pos (4U)
<> 128:9bcdf88f62b0 2814 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2815 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
<> 128:9bcdf88f62b0 2816 #define CAN_RF0R_RFOM0_Pos (5U)
<> 128:9bcdf88f62b0 2817 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 2818 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
<> 128:9bcdf88f62b0 2819
<> 128:9bcdf88f62b0 2820 /******************* Bit definition for CAN_RF1R register *******************/
<> 128:9bcdf88f62b0 2821 #define CAN_RF1R_FMP1_Pos (0U)
<> 128:9bcdf88f62b0 2822 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 2823 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
<> 128:9bcdf88f62b0 2824 #define CAN_RF1R_FULL1_Pos (3U)
<> 128:9bcdf88f62b0 2825 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2826 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
<> 128:9bcdf88f62b0 2827 #define CAN_RF1R_FOVR1_Pos (4U)
<> 128:9bcdf88f62b0 2828 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2829 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
<> 128:9bcdf88f62b0 2830 #define CAN_RF1R_RFOM1_Pos (5U)
<> 128:9bcdf88f62b0 2831 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 2832 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
<> 128:9bcdf88f62b0 2833
<> 128:9bcdf88f62b0 2834 /******************** Bit definition for CAN_IER register *******************/
<> 128:9bcdf88f62b0 2835 #define CAN_IER_TMEIE_Pos (0U)
<> 128:9bcdf88f62b0 2836 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2837 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
<> 128:9bcdf88f62b0 2838 #define CAN_IER_FMPIE0_Pos (1U)
<> 128:9bcdf88f62b0 2839 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2840 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
<> 128:9bcdf88f62b0 2841 #define CAN_IER_FFIE0_Pos (2U)
<> 128:9bcdf88f62b0 2842 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2843 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
<> 128:9bcdf88f62b0 2844 #define CAN_IER_FOVIE0_Pos (3U)
<> 128:9bcdf88f62b0 2845 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 2846 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
<> 128:9bcdf88f62b0 2847 #define CAN_IER_FMPIE1_Pos (4U)
<> 128:9bcdf88f62b0 2848 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2849 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
<> 128:9bcdf88f62b0 2850 #define CAN_IER_FFIE1_Pos (5U)
<> 128:9bcdf88f62b0 2851 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 2852 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
<> 128:9bcdf88f62b0 2853 #define CAN_IER_FOVIE1_Pos (6U)
<> 128:9bcdf88f62b0 2854 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2855 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
<> 128:9bcdf88f62b0 2856 #define CAN_IER_EWGIE_Pos (8U)
<> 128:9bcdf88f62b0 2857 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2858 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
<> 128:9bcdf88f62b0 2859 #define CAN_IER_EPVIE_Pos (9U)
<> 128:9bcdf88f62b0 2860 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 2861 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
<> 128:9bcdf88f62b0 2862 #define CAN_IER_BOFIE_Pos (10U)
<> 128:9bcdf88f62b0 2863 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 2864 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
<> 128:9bcdf88f62b0 2865 #define CAN_IER_LECIE_Pos (11U)
<> 128:9bcdf88f62b0 2866 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 2867 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
<> 128:9bcdf88f62b0 2868 #define CAN_IER_ERRIE_Pos (15U)
<> 128:9bcdf88f62b0 2869 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 2870 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
<> 128:9bcdf88f62b0 2871 #define CAN_IER_WKUIE_Pos (16U)
<> 128:9bcdf88f62b0 2872 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 2873 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
<> 128:9bcdf88f62b0 2874 #define CAN_IER_SLKIE_Pos (17U)
<> 128:9bcdf88f62b0 2875 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 2876 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
<> 128:9bcdf88f62b0 2877
<> 128:9bcdf88f62b0 2878 /******************** Bit definition for CAN_ESR register *******************/
<> 128:9bcdf88f62b0 2879 #define CAN_ESR_EWGF_Pos (0U)
<> 128:9bcdf88f62b0 2880 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2881 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
<> 128:9bcdf88f62b0 2882 #define CAN_ESR_EPVF_Pos (1U)
<> 128:9bcdf88f62b0 2883 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2884 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
<> 128:9bcdf88f62b0 2885 #define CAN_ESR_BOFF_Pos (2U)
<> 128:9bcdf88f62b0 2886 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2887 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
<> 128:9bcdf88f62b0 2888
<> 128:9bcdf88f62b0 2889 #define CAN_ESR_LEC_Pos (4U)
<> 128:9bcdf88f62b0 2890 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
<> 128:9bcdf88f62b0 2891 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
<> 128:9bcdf88f62b0 2892 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 2893 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 2894 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 2895
<> 128:9bcdf88f62b0 2896 #define CAN_ESR_TEC_Pos (16U)
<> 128:9bcdf88f62b0 2897 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 2898 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
<> 128:9bcdf88f62b0 2899 #define CAN_ESR_REC_Pos (24U)
<> 128:9bcdf88f62b0 2900 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
<> 128:9bcdf88f62b0 2901 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
<> 128:9bcdf88f62b0 2902
<> 128:9bcdf88f62b0 2903 /******************* Bit definition for CAN_BTR register ********************/
<> 128:9bcdf88f62b0 2904 #define CAN_BTR_BRP_Pos (0U)
<> 128:9bcdf88f62b0 2905 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
<> 128:9bcdf88f62b0 2906 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
<> 128:9bcdf88f62b0 2907 #define CAN_BTR_TS1_Pos (16U)
<> 128:9bcdf88f62b0 2908 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
<> 128:9bcdf88f62b0 2909 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
<> 128:9bcdf88f62b0 2910 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 2911 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 2912 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 2913 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 2914 #define CAN_BTR_TS2_Pos (20U)
<> 128:9bcdf88f62b0 2915 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
<> 128:9bcdf88f62b0 2916 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
<> 128:9bcdf88f62b0 2917 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 2918 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 2919 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 2920 #define CAN_BTR_SJW_Pos (24U)
<> 128:9bcdf88f62b0 2921 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
<> 128:9bcdf88f62b0 2922 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
<> 128:9bcdf88f62b0 2923 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 2924 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 2925 #define CAN_BTR_LBKM_Pos (30U)
<> 128:9bcdf88f62b0 2926 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 2927 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
<> 128:9bcdf88f62b0 2928 #define CAN_BTR_SILM_Pos (31U)
<> 128:9bcdf88f62b0 2929 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 2930 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
<> 128:9bcdf88f62b0 2931
<> 128:9bcdf88f62b0 2932 /*!<Mailbox registers */
<> 128:9bcdf88f62b0 2933 /****************** Bit definition for CAN_TI0R register ********************/
<> 128:9bcdf88f62b0 2934 #define CAN_TI0R_TXRQ_Pos (0U)
<> 128:9bcdf88f62b0 2935 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2936 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
<> 128:9bcdf88f62b0 2937 #define CAN_TI0R_RTR_Pos (1U)
<> 128:9bcdf88f62b0 2938 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2939 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
<> 128:9bcdf88f62b0 2940 #define CAN_TI0R_IDE_Pos (2U)
<> 128:9bcdf88f62b0 2941 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2942 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
<> 128:9bcdf88f62b0 2943 #define CAN_TI0R_EXID_Pos (3U)
<> 128:9bcdf88f62b0 2944 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
<> 128:9bcdf88f62b0 2945 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
<> 128:9bcdf88f62b0 2946 #define CAN_TI0R_STID_Pos (21U)
<> 128:9bcdf88f62b0 2947 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
<> 128:9bcdf88f62b0 2948 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 128:9bcdf88f62b0 2949
<> 128:9bcdf88f62b0 2950 /****************** Bit definition for CAN_TDT0R register *******************/
<> 128:9bcdf88f62b0 2951 #define CAN_TDT0R_DLC_Pos (0U)
<> 128:9bcdf88f62b0 2952 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 2953 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
<> 128:9bcdf88f62b0 2954 #define CAN_TDT0R_TGT_Pos (8U)
<> 128:9bcdf88f62b0 2955 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 2956 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
<> 128:9bcdf88f62b0 2957 #define CAN_TDT0R_TIME_Pos (16U)
<> 128:9bcdf88f62b0 2958 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
<> 128:9bcdf88f62b0 2959 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
<> 128:9bcdf88f62b0 2960
<> 128:9bcdf88f62b0 2961 /****************** Bit definition for CAN_TDL0R register *******************/
<> 128:9bcdf88f62b0 2962 #define CAN_TDL0R_DATA0_Pos (0U)
<> 128:9bcdf88f62b0 2963 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 2964 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
<> 128:9bcdf88f62b0 2965 #define CAN_TDL0R_DATA1_Pos (8U)
<> 128:9bcdf88f62b0 2966 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 2967 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
<> 128:9bcdf88f62b0 2968 #define CAN_TDL0R_DATA2_Pos (16U)
<> 128:9bcdf88f62b0 2969 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 2970 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
<> 128:9bcdf88f62b0 2971 #define CAN_TDL0R_DATA3_Pos (24U)
<> 128:9bcdf88f62b0 2972 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
<> 128:9bcdf88f62b0 2973 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
<> 128:9bcdf88f62b0 2974
<> 128:9bcdf88f62b0 2975 /****************** Bit definition for CAN_TDH0R register *******************/
<> 128:9bcdf88f62b0 2976 #define CAN_TDH0R_DATA4_Pos (0U)
<> 128:9bcdf88f62b0 2977 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 2978 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
<> 128:9bcdf88f62b0 2979 #define CAN_TDH0R_DATA5_Pos (8U)
<> 128:9bcdf88f62b0 2980 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 2981 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
<> 128:9bcdf88f62b0 2982 #define CAN_TDH0R_DATA6_Pos (16U)
<> 128:9bcdf88f62b0 2983 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 2984 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
<> 128:9bcdf88f62b0 2985 #define CAN_TDH0R_DATA7_Pos (24U)
<> 128:9bcdf88f62b0 2986 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
<> 128:9bcdf88f62b0 2987 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
<> 128:9bcdf88f62b0 2988
<> 128:9bcdf88f62b0 2989 /******************* Bit definition for CAN_TI1R register *******************/
<> 128:9bcdf88f62b0 2990 #define CAN_TI1R_TXRQ_Pos (0U)
<> 128:9bcdf88f62b0 2991 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 2992 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
<> 128:9bcdf88f62b0 2993 #define CAN_TI1R_RTR_Pos (1U)
<> 128:9bcdf88f62b0 2994 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 2995 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
<> 128:9bcdf88f62b0 2996 #define CAN_TI1R_IDE_Pos (2U)
<> 128:9bcdf88f62b0 2997 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 2998 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
<> 128:9bcdf88f62b0 2999 #define CAN_TI1R_EXID_Pos (3U)
<> 128:9bcdf88f62b0 3000 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
<> 128:9bcdf88f62b0 3001 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
<> 128:9bcdf88f62b0 3002 #define CAN_TI1R_STID_Pos (21U)
<> 128:9bcdf88f62b0 3003 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
<> 128:9bcdf88f62b0 3004 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 128:9bcdf88f62b0 3005
<> 128:9bcdf88f62b0 3006 /******************* Bit definition for CAN_TDT1R register ******************/
<> 128:9bcdf88f62b0 3007 #define CAN_TDT1R_DLC_Pos (0U)
<> 128:9bcdf88f62b0 3008 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 3009 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
<> 128:9bcdf88f62b0 3010 #define CAN_TDT1R_TGT_Pos (8U)
<> 128:9bcdf88f62b0 3011 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 3012 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
<> 128:9bcdf88f62b0 3013 #define CAN_TDT1R_TIME_Pos (16U)
<> 128:9bcdf88f62b0 3014 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
<> 128:9bcdf88f62b0 3015 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
<> 128:9bcdf88f62b0 3016
<> 128:9bcdf88f62b0 3017 /******************* Bit definition for CAN_TDL1R register ******************/
<> 128:9bcdf88f62b0 3018 #define CAN_TDL1R_DATA0_Pos (0U)
<> 128:9bcdf88f62b0 3019 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 3020 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
<> 128:9bcdf88f62b0 3021 #define CAN_TDL1R_DATA1_Pos (8U)
<> 128:9bcdf88f62b0 3022 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 3023 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
<> 128:9bcdf88f62b0 3024 #define CAN_TDL1R_DATA2_Pos (16U)
<> 128:9bcdf88f62b0 3025 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 3026 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
<> 128:9bcdf88f62b0 3027 #define CAN_TDL1R_DATA3_Pos (24U)
<> 128:9bcdf88f62b0 3028 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
<> 128:9bcdf88f62b0 3029 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
<> 128:9bcdf88f62b0 3030
<> 128:9bcdf88f62b0 3031 /******************* Bit definition for CAN_TDH1R register ******************/
<> 128:9bcdf88f62b0 3032 #define CAN_TDH1R_DATA4_Pos (0U)
<> 128:9bcdf88f62b0 3033 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 3034 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
<> 128:9bcdf88f62b0 3035 #define CAN_TDH1R_DATA5_Pos (8U)
<> 128:9bcdf88f62b0 3036 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 3037 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
<> 128:9bcdf88f62b0 3038 #define CAN_TDH1R_DATA6_Pos (16U)
<> 128:9bcdf88f62b0 3039 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 3040 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
<> 128:9bcdf88f62b0 3041 #define CAN_TDH1R_DATA7_Pos (24U)
<> 128:9bcdf88f62b0 3042 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
<> 128:9bcdf88f62b0 3043 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
<> 128:9bcdf88f62b0 3044
<> 128:9bcdf88f62b0 3045 /******************* Bit definition for CAN_TI2R register *******************/
<> 128:9bcdf88f62b0 3046 #define CAN_TI2R_TXRQ_Pos (0U)
<> 128:9bcdf88f62b0 3047 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 3048 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
<> 128:9bcdf88f62b0 3049 #define CAN_TI2R_RTR_Pos (1U)
<> 128:9bcdf88f62b0 3050 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 3051 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
<> 128:9bcdf88f62b0 3052 #define CAN_TI2R_IDE_Pos (2U)
<> 128:9bcdf88f62b0 3053 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 3054 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
<> 128:9bcdf88f62b0 3055 #define CAN_TI2R_EXID_Pos (3U)
<> 128:9bcdf88f62b0 3056 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
<> 128:9bcdf88f62b0 3057 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
<> 128:9bcdf88f62b0 3058 #define CAN_TI2R_STID_Pos (21U)
<> 128:9bcdf88f62b0 3059 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
<> 128:9bcdf88f62b0 3060 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 128:9bcdf88f62b0 3061
<> 128:9bcdf88f62b0 3062 /******************* Bit definition for CAN_TDT2R register ******************/
<> 128:9bcdf88f62b0 3063 #define CAN_TDT2R_DLC_Pos (0U)
<> 128:9bcdf88f62b0 3064 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 3065 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
<> 128:9bcdf88f62b0 3066 #define CAN_TDT2R_TGT_Pos (8U)
<> 128:9bcdf88f62b0 3067 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 3068 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
<> 128:9bcdf88f62b0 3069 #define CAN_TDT2R_TIME_Pos (16U)
<> 128:9bcdf88f62b0 3070 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
<> 128:9bcdf88f62b0 3071 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
<> 128:9bcdf88f62b0 3072
<> 128:9bcdf88f62b0 3073 /******************* Bit definition for CAN_TDL2R register ******************/
<> 128:9bcdf88f62b0 3074 #define CAN_TDL2R_DATA0_Pos (0U)
<> 128:9bcdf88f62b0 3075 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 3076 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
<> 128:9bcdf88f62b0 3077 #define CAN_TDL2R_DATA1_Pos (8U)
<> 128:9bcdf88f62b0 3078 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 3079 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
<> 128:9bcdf88f62b0 3080 #define CAN_TDL2R_DATA2_Pos (16U)
<> 128:9bcdf88f62b0 3081 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 3082 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
<> 128:9bcdf88f62b0 3083 #define CAN_TDL2R_DATA3_Pos (24U)
<> 128:9bcdf88f62b0 3084 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
<> 128:9bcdf88f62b0 3085 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
<> 128:9bcdf88f62b0 3086
<> 128:9bcdf88f62b0 3087 /******************* Bit definition for CAN_TDH2R register ******************/
<> 128:9bcdf88f62b0 3088 #define CAN_TDH2R_DATA4_Pos (0U)
<> 128:9bcdf88f62b0 3089 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 3090 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
<> 128:9bcdf88f62b0 3091 #define CAN_TDH2R_DATA5_Pos (8U)
<> 128:9bcdf88f62b0 3092 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 3093 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
<> 128:9bcdf88f62b0 3094 #define CAN_TDH2R_DATA6_Pos (16U)
<> 128:9bcdf88f62b0 3095 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 3096 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
<> 128:9bcdf88f62b0 3097 #define CAN_TDH2R_DATA7_Pos (24U)
<> 128:9bcdf88f62b0 3098 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
<> 128:9bcdf88f62b0 3099 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
<> 128:9bcdf88f62b0 3100
<> 128:9bcdf88f62b0 3101 /******************* Bit definition for CAN_RI0R register *******************/
<> 128:9bcdf88f62b0 3102 #define CAN_RI0R_RTR_Pos (1U)
<> 128:9bcdf88f62b0 3103 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 3104 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
<> 128:9bcdf88f62b0 3105 #define CAN_RI0R_IDE_Pos (2U)
<> 128:9bcdf88f62b0 3106 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 3107 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
<> 128:9bcdf88f62b0 3108 #define CAN_RI0R_EXID_Pos (3U)
<> 128:9bcdf88f62b0 3109 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
<> 128:9bcdf88f62b0 3110 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
<> 128:9bcdf88f62b0 3111 #define CAN_RI0R_STID_Pos (21U)
<> 128:9bcdf88f62b0 3112 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
<> 128:9bcdf88f62b0 3113 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 128:9bcdf88f62b0 3114
<> 128:9bcdf88f62b0 3115 /******************* Bit definition for CAN_RDT0R register ******************/
<> 128:9bcdf88f62b0 3116 #define CAN_RDT0R_DLC_Pos (0U)
<> 128:9bcdf88f62b0 3117 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 3118 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
<> 128:9bcdf88f62b0 3119 #define CAN_RDT0R_FMI_Pos (8U)
<> 128:9bcdf88f62b0 3120 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 3121 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
<> 128:9bcdf88f62b0 3122 #define CAN_RDT0R_TIME_Pos (16U)
<> 128:9bcdf88f62b0 3123 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
<> 128:9bcdf88f62b0 3124 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
<> 128:9bcdf88f62b0 3125
<> 128:9bcdf88f62b0 3126 /******************* Bit definition for CAN_RDL0R register ******************/
<> 128:9bcdf88f62b0 3127 #define CAN_RDL0R_DATA0_Pos (0U)
<> 128:9bcdf88f62b0 3128 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 3129 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
<> 128:9bcdf88f62b0 3130 #define CAN_RDL0R_DATA1_Pos (8U)
<> 128:9bcdf88f62b0 3131 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 3132 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
<> 128:9bcdf88f62b0 3133 #define CAN_RDL0R_DATA2_Pos (16U)
<> 128:9bcdf88f62b0 3134 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 3135 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
<> 128:9bcdf88f62b0 3136 #define CAN_RDL0R_DATA3_Pos (24U)
<> 128:9bcdf88f62b0 3137 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
<> 128:9bcdf88f62b0 3138 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
<> 128:9bcdf88f62b0 3139
<> 128:9bcdf88f62b0 3140 /******************* Bit definition for CAN_RDH0R register ******************/
<> 128:9bcdf88f62b0 3141 #define CAN_RDH0R_DATA4_Pos (0U)
<> 128:9bcdf88f62b0 3142 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 3143 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
<> 128:9bcdf88f62b0 3144 #define CAN_RDH0R_DATA5_Pos (8U)
<> 128:9bcdf88f62b0 3145 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 3146 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
<> 128:9bcdf88f62b0 3147 #define CAN_RDH0R_DATA6_Pos (16U)
<> 128:9bcdf88f62b0 3148 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 3149 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
<> 128:9bcdf88f62b0 3150 #define CAN_RDH0R_DATA7_Pos (24U)
<> 128:9bcdf88f62b0 3151 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
<> 128:9bcdf88f62b0 3152 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
<> 128:9bcdf88f62b0 3153
<> 128:9bcdf88f62b0 3154 /******************* Bit definition for CAN_RI1R register *******************/
<> 128:9bcdf88f62b0 3155 #define CAN_RI1R_RTR_Pos (1U)
<> 128:9bcdf88f62b0 3156 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 3157 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
<> 128:9bcdf88f62b0 3158 #define CAN_RI1R_IDE_Pos (2U)
<> 128:9bcdf88f62b0 3159 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 3160 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
<> 128:9bcdf88f62b0 3161 #define CAN_RI1R_EXID_Pos (3U)
<> 128:9bcdf88f62b0 3162 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
<> 128:9bcdf88f62b0 3163 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
<> 128:9bcdf88f62b0 3164 #define CAN_RI1R_STID_Pos (21U)
<> 128:9bcdf88f62b0 3165 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
<> 128:9bcdf88f62b0 3166 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 128:9bcdf88f62b0 3167
<> 128:9bcdf88f62b0 3168 /******************* Bit definition for CAN_RDT1R register ******************/
<> 128:9bcdf88f62b0 3169 #define CAN_RDT1R_DLC_Pos (0U)
<> 128:9bcdf88f62b0 3170 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 3171 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
<> 128:9bcdf88f62b0 3172 #define CAN_RDT1R_FMI_Pos (8U)
<> 128:9bcdf88f62b0 3173 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 3174 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
<> 128:9bcdf88f62b0 3175 #define CAN_RDT1R_TIME_Pos (16U)
<> 128:9bcdf88f62b0 3176 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
<> 128:9bcdf88f62b0 3177 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
<> 128:9bcdf88f62b0 3178
<> 128:9bcdf88f62b0 3179 /******************* Bit definition for CAN_RDL1R register ******************/
<> 128:9bcdf88f62b0 3180 #define CAN_RDL1R_DATA0_Pos (0U)
<> 128:9bcdf88f62b0 3181 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 3182 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
<> 128:9bcdf88f62b0 3183 #define CAN_RDL1R_DATA1_Pos (8U)
<> 128:9bcdf88f62b0 3184 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 3185 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
<> 128:9bcdf88f62b0 3186 #define CAN_RDL1R_DATA2_Pos (16U)
<> 128:9bcdf88f62b0 3187 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 3188 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
<> 128:9bcdf88f62b0 3189 #define CAN_RDL1R_DATA3_Pos (24U)
<> 128:9bcdf88f62b0 3190 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
<> 128:9bcdf88f62b0 3191 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
<> 128:9bcdf88f62b0 3192
<> 128:9bcdf88f62b0 3193 /******************* Bit definition for CAN_RDH1R register ******************/
<> 128:9bcdf88f62b0 3194 #define CAN_RDH1R_DATA4_Pos (0U)
<> 128:9bcdf88f62b0 3195 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 3196 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
<> 128:9bcdf88f62b0 3197 #define CAN_RDH1R_DATA5_Pos (8U)
<> 128:9bcdf88f62b0 3198 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 3199 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
<> 128:9bcdf88f62b0 3200 #define CAN_RDH1R_DATA6_Pos (16U)
<> 128:9bcdf88f62b0 3201 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 3202 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
<> 128:9bcdf88f62b0 3203 #define CAN_RDH1R_DATA7_Pos (24U)
<> 128:9bcdf88f62b0 3204 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
<> 128:9bcdf88f62b0 3205 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
<> 128:9bcdf88f62b0 3206
<> 128:9bcdf88f62b0 3207 /*!<CAN filter registers */
<> 128:9bcdf88f62b0 3208 /******************* Bit definition for CAN_FMR register ********************/
<> 128:9bcdf88f62b0 3209 #define CAN_FMR_FINIT_Pos (0U)
<> 128:9bcdf88f62b0 3210 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 3211 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
<> 128:9bcdf88f62b0 3212
<> 128:9bcdf88f62b0 3213 /******************* Bit definition for CAN_FM1R register *******************/
<> 128:9bcdf88f62b0 3214 #define CAN_FM1R_FBM_Pos (0U)
<> 128:9bcdf88f62b0 3215 #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
<> 128:9bcdf88f62b0 3216 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
<> 128:9bcdf88f62b0 3217 #define CAN_FM1R_FBM0_Pos (0U)
<> 128:9bcdf88f62b0 3218 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 3219 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
<> 128:9bcdf88f62b0 3220 #define CAN_FM1R_FBM1_Pos (1U)
<> 128:9bcdf88f62b0 3221 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 3222 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
<> 128:9bcdf88f62b0 3223 #define CAN_FM1R_FBM2_Pos (2U)
<> 128:9bcdf88f62b0 3224 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 3225 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
<> 128:9bcdf88f62b0 3226 #define CAN_FM1R_FBM3_Pos (3U)
<> 128:9bcdf88f62b0 3227 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 3228 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
<> 128:9bcdf88f62b0 3229 #define CAN_FM1R_FBM4_Pos (4U)
<> 128:9bcdf88f62b0 3230 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 3231 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
<> 128:9bcdf88f62b0 3232 #define CAN_FM1R_FBM5_Pos (5U)
<> 128:9bcdf88f62b0 3233 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 3234 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
<> 128:9bcdf88f62b0 3235 #define CAN_FM1R_FBM6_Pos (6U)
<> 128:9bcdf88f62b0 3236 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 3237 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
<> 128:9bcdf88f62b0 3238 #define CAN_FM1R_FBM7_Pos (7U)
<> 128:9bcdf88f62b0 3239 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 3240 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
<> 128:9bcdf88f62b0 3241 #define CAN_FM1R_FBM8_Pos (8U)
<> 128:9bcdf88f62b0 3242 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 3243 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
<> 128:9bcdf88f62b0 3244 #define CAN_FM1R_FBM9_Pos (9U)
<> 128:9bcdf88f62b0 3245 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 3246 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
<> 128:9bcdf88f62b0 3247 #define CAN_FM1R_FBM10_Pos (10U)
<> 128:9bcdf88f62b0 3248 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 3249 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
<> 128:9bcdf88f62b0 3250 #define CAN_FM1R_FBM11_Pos (11U)
<> 128:9bcdf88f62b0 3251 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 3252 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
<> 128:9bcdf88f62b0 3253 #define CAN_FM1R_FBM12_Pos (12U)
<> 128:9bcdf88f62b0 3254 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 3255 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
<> 128:9bcdf88f62b0 3256 #define CAN_FM1R_FBM13_Pos (13U)
<> 128:9bcdf88f62b0 3257 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 3258 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
<> 128:9bcdf88f62b0 3259
<> 128:9bcdf88f62b0 3260 /******************* Bit definition for CAN_FS1R register *******************/
<> 128:9bcdf88f62b0 3261 #define CAN_FS1R_FSC_Pos (0U)
<> 128:9bcdf88f62b0 3262 #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
<> 128:9bcdf88f62b0 3263 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
<> 128:9bcdf88f62b0 3264 #define CAN_FS1R_FSC0_Pos (0U)
<> 128:9bcdf88f62b0 3265 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 3266 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
<> 128:9bcdf88f62b0 3267 #define CAN_FS1R_FSC1_Pos (1U)
<> 128:9bcdf88f62b0 3268 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 3269 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
<> 128:9bcdf88f62b0 3270 #define CAN_FS1R_FSC2_Pos (2U)
<> 128:9bcdf88f62b0 3271 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 3272 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
<> 128:9bcdf88f62b0 3273 #define CAN_FS1R_FSC3_Pos (3U)
<> 128:9bcdf88f62b0 3274 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 3275 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
<> 128:9bcdf88f62b0 3276 #define CAN_FS1R_FSC4_Pos (4U)
<> 128:9bcdf88f62b0 3277 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 3278 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
<> 128:9bcdf88f62b0 3279 #define CAN_FS1R_FSC5_Pos (5U)
<> 128:9bcdf88f62b0 3280 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 3281 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
<> 128:9bcdf88f62b0 3282 #define CAN_FS1R_FSC6_Pos (6U)
<> 128:9bcdf88f62b0 3283 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 3284 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
<> 128:9bcdf88f62b0 3285 #define CAN_FS1R_FSC7_Pos (7U)
<> 128:9bcdf88f62b0 3286 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 3287 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
<> 128:9bcdf88f62b0 3288 #define CAN_FS1R_FSC8_Pos (8U)
<> 128:9bcdf88f62b0 3289 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 3290 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
<> 128:9bcdf88f62b0 3291 #define CAN_FS1R_FSC9_Pos (9U)
<> 128:9bcdf88f62b0 3292 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 3293 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
<> 128:9bcdf88f62b0 3294 #define CAN_FS1R_FSC10_Pos (10U)
<> 128:9bcdf88f62b0 3295 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 3296 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
<> 128:9bcdf88f62b0 3297 #define CAN_FS1R_FSC11_Pos (11U)
<> 128:9bcdf88f62b0 3298 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 3299 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
<> 128:9bcdf88f62b0 3300 #define CAN_FS1R_FSC12_Pos (12U)
<> 128:9bcdf88f62b0 3301 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 3302 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
<> 128:9bcdf88f62b0 3303 #define CAN_FS1R_FSC13_Pos (13U)
<> 128:9bcdf88f62b0 3304 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 3305 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
<> 128:9bcdf88f62b0 3306
<> 128:9bcdf88f62b0 3307 /****************** Bit definition for CAN_FFA1R register *******************/
<> 128:9bcdf88f62b0 3308 #define CAN_FFA1R_FFA_Pos (0U)
<> 128:9bcdf88f62b0 3309 #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
<> 128:9bcdf88f62b0 3310 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
<> 128:9bcdf88f62b0 3311 #define CAN_FFA1R_FFA0_Pos (0U)
<> 128:9bcdf88f62b0 3312 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 3313 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
<> 128:9bcdf88f62b0 3314 #define CAN_FFA1R_FFA1_Pos (1U)
<> 128:9bcdf88f62b0 3315 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 3316 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
<> 128:9bcdf88f62b0 3317 #define CAN_FFA1R_FFA2_Pos (2U)
<> 128:9bcdf88f62b0 3318 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 3319 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
<> 128:9bcdf88f62b0 3320 #define CAN_FFA1R_FFA3_Pos (3U)
<> 128:9bcdf88f62b0 3321 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 3322 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
<> 128:9bcdf88f62b0 3323 #define CAN_FFA1R_FFA4_Pos (4U)
<> 128:9bcdf88f62b0 3324 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 3325 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
<> 128:9bcdf88f62b0 3326 #define CAN_FFA1R_FFA5_Pos (5U)
<> 128:9bcdf88f62b0 3327 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 3328 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
<> 128:9bcdf88f62b0 3329 #define CAN_FFA1R_FFA6_Pos (6U)
<> 128:9bcdf88f62b0 3330 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 3331 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
<> 128:9bcdf88f62b0 3332 #define CAN_FFA1R_FFA7_Pos (7U)
<> 128:9bcdf88f62b0 3333 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 3334 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
<> 128:9bcdf88f62b0 3335 #define CAN_FFA1R_FFA8_Pos (8U)
<> 128:9bcdf88f62b0 3336 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 3337 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
<> 128:9bcdf88f62b0 3338 #define CAN_FFA1R_FFA9_Pos (9U)
<> 128:9bcdf88f62b0 3339 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 3340 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
<> 128:9bcdf88f62b0 3341 #define CAN_FFA1R_FFA10_Pos (10U)
<> 128:9bcdf88f62b0 3342 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 3343 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
<> 128:9bcdf88f62b0 3344 #define CAN_FFA1R_FFA11_Pos (11U)
<> 128:9bcdf88f62b0 3345 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 3346 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
<> 128:9bcdf88f62b0 3347 #define CAN_FFA1R_FFA12_Pos (12U)
<> 128:9bcdf88f62b0 3348 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 3349 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
<> 128:9bcdf88f62b0 3350 #define CAN_FFA1R_FFA13_Pos (13U)
<> 128:9bcdf88f62b0 3351 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 3352 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
<> 128:9bcdf88f62b0 3353
<> 128:9bcdf88f62b0 3354 /******************* Bit definition for CAN_FA1R register *******************/
<> 128:9bcdf88f62b0 3355 #define CAN_FA1R_FACT_Pos (0U)
<> 128:9bcdf88f62b0 3356 #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
<> 128:9bcdf88f62b0 3357 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
<> 128:9bcdf88f62b0 3358 #define CAN_FA1R_FACT0_Pos (0U)
<> 128:9bcdf88f62b0 3359 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 3360 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
<> 128:9bcdf88f62b0 3361 #define CAN_FA1R_FACT1_Pos (1U)
<> 128:9bcdf88f62b0 3362 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 3363 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
<> 128:9bcdf88f62b0 3364 #define CAN_FA1R_FACT2_Pos (2U)
<> 128:9bcdf88f62b0 3365 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 3366 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
<> 128:9bcdf88f62b0 3367 #define CAN_FA1R_FACT3_Pos (3U)
<> 128:9bcdf88f62b0 3368 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 3369 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
<> 128:9bcdf88f62b0 3370 #define CAN_FA1R_FACT4_Pos (4U)
<> 128:9bcdf88f62b0 3371 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 3372 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
<> 128:9bcdf88f62b0 3373 #define CAN_FA1R_FACT5_Pos (5U)
<> 128:9bcdf88f62b0 3374 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 3375 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
<> 128:9bcdf88f62b0 3376 #define CAN_FA1R_FACT6_Pos (6U)
<> 128:9bcdf88f62b0 3377 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 3378 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
<> 128:9bcdf88f62b0 3379 #define CAN_FA1R_FACT7_Pos (7U)
<> 128:9bcdf88f62b0 3380 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 3381 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
<> 128:9bcdf88f62b0 3382 #define CAN_FA1R_FACT8_Pos (8U)
<> 128:9bcdf88f62b0 3383 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 3384 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
<> 128:9bcdf88f62b0 3385 #define CAN_FA1R_FACT9_Pos (9U)
<> 128:9bcdf88f62b0 3386 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 3387 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
<> 128:9bcdf88f62b0 3388 #define CAN_FA1R_FACT10_Pos (10U)
<> 128:9bcdf88f62b0 3389 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 3390 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
<> 128:9bcdf88f62b0 3391 #define CAN_FA1R_FACT11_Pos (11U)
<> 128:9bcdf88f62b0 3392 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 3393 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
<> 128:9bcdf88f62b0 3394 #define CAN_FA1R_FACT12_Pos (12U)
<> 128:9bcdf88f62b0 3395 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 3396 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
<> 128:9bcdf88f62b0 3397 #define CAN_FA1R_FACT13_Pos (13U)
<> 128:9bcdf88f62b0 3398 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 3399 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
<> 128:9bcdf88f62b0 3400
<> 128:9bcdf88f62b0 3401 /******************* Bit definition for CAN_F0R1 register *******************/
<> 128:9bcdf88f62b0 3402 #define CAN_F0R1_FB0_Pos (0U)
<> 128:9bcdf88f62b0 3403 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 3404 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 3405 #define CAN_F0R1_FB1_Pos (1U)
<> 128:9bcdf88f62b0 3406 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 3407 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 3408 #define CAN_F0R1_FB2_Pos (2U)
<> 128:9bcdf88f62b0 3409 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 3410 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 3411 #define CAN_F0R1_FB3_Pos (3U)
<> 128:9bcdf88f62b0 3412 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 3413 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 3414 #define CAN_F0R1_FB4_Pos (4U)
<> 128:9bcdf88f62b0 3415 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 3416 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 3417 #define CAN_F0R1_FB5_Pos (5U)
<> 128:9bcdf88f62b0 3418 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 3419 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 3420 #define CAN_F0R1_FB6_Pos (6U)
<> 128:9bcdf88f62b0 3421 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 3422 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 3423 #define CAN_F0R1_FB7_Pos (7U)
<> 128:9bcdf88f62b0 3424 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 3425 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 3426 #define CAN_F0R1_FB8_Pos (8U)
<> 128:9bcdf88f62b0 3427 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 3428 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 3429 #define CAN_F0R1_FB9_Pos (9U)
<> 128:9bcdf88f62b0 3430 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 3431 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 3432 #define CAN_F0R1_FB10_Pos (10U)
<> 128:9bcdf88f62b0 3433 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 3434 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 3435 #define CAN_F0R1_FB11_Pos (11U)
<> 128:9bcdf88f62b0 3436 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 3437 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 3438 #define CAN_F0R1_FB12_Pos (12U)
<> 128:9bcdf88f62b0 3439 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 3440 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 3441 #define CAN_F0R1_FB13_Pos (13U)
<> 128:9bcdf88f62b0 3442 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 3443 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 3444 #define CAN_F0R1_FB14_Pos (14U)
<> 128:9bcdf88f62b0 3445 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 3446 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 3447 #define CAN_F0R1_FB15_Pos (15U)
<> 128:9bcdf88f62b0 3448 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 3449 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 3450 #define CAN_F0R1_FB16_Pos (16U)
<> 128:9bcdf88f62b0 3451 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 3452 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 3453 #define CAN_F0R1_FB17_Pos (17U)
<> 128:9bcdf88f62b0 3454 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 3455 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 3456 #define CAN_F0R1_FB18_Pos (18U)
<> 128:9bcdf88f62b0 3457 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 3458 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 3459 #define CAN_F0R1_FB19_Pos (19U)
<> 128:9bcdf88f62b0 3460 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 3461 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 3462 #define CAN_F0R1_FB20_Pos (20U)
<> 128:9bcdf88f62b0 3463 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 3464 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 3465 #define CAN_F0R1_FB21_Pos (21U)
<> 128:9bcdf88f62b0 3466 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 3467 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 3468 #define CAN_F0R1_FB22_Pos (22U)
<> 128:9bcdf88f62b0 3469 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 3470 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 3471 #define CAN_F0R1_FB23_Pos (23U)
<> 128:9bcdf88f62b0 3472 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 3473 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 3474 #define CAN_F0R1_FB24_Pos (24U)
<> 128:9bcdf88f62b0 3475 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 3476 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 3477 #define CAN_F0R1_FB25_Pos (25U)
<> 128:9bcdf88f62b0 3478 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 3479 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 3480 #define CAN_F0R1_FB26_Pos (26U)
<> 128:9bcdf88f62b0 3481 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 3482 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 3483 #define CAN_F0R1_FB27_Pos (27U)
<> 128:9bcdf88f62b0 3484 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 3485 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 3486 #define CAN_F0R1_FB28_Pos (28U)
<> 128:9bcdf88f62b0 3487 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 3488 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 3489 #define CAN_F0R1_FB29_Pos (29U)
<> 128:9bcdf88f62b0 3490 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 3491 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 3492 #define CAN_F0R1_FB30_Pos (30U)
<> 128:9bcdf88f62b0 3493 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 3494 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 3495 #define CAN_F0R1_FB31_Pos (31U)
<> 128:9bcdf88f62b0 3496 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 3497 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 3498
<> 128:9bcdf88f62b0 3499 /******************* Bit definition for CAN_F1R1 register *******************/
<> 128:9bcdf88f62b0 3500 #define CAN_F1R1_FB0_Pos (0U)
<> 128:9bcdf88f62b0 3501 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 3502 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 3503 #define CAN_F1R1_FB1_Pos (1U)
<> 128:9bcdf88f62b0 3504 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 3505 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 3506 #define CAN_F1R1_FB2_Pos (2U)
<> 128:9bcdf88f62b0 3507 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 3508 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 3509 #define CAN_F1R1_FB3_Pos (3U)
<> 128:9bcdf88f62b0 3510 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 3511 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 3512 #define CAN_F1R1_FB4_Pos (4U)
<> 128:9bcdf88f62b0 3513 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 3514 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 3515 #define CAN_F1R1_FB5_Pos (5U)
<> 128:9bcdf88f62b0 3516 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 3517 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 3518 #define CAN_F1R1_FB6_Pos (6U)
<> 128:9bcdf88f62b0 3519 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 3520 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 3521 #define CAN_F1R1_FB7_Pos (7U)
<> 128:9bcdf88f62b0 3522 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 3523 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 3524 #define CAN_F1R1_FB8_Pos (8U)
<> 128:9bcdf88f62b0 3525 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 3526 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 3527 #define CAN_F1R1_FB9_Pos (9U)
<> 128:9bcdf88f62b0 3528 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 3529 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 3530 #define CAN_F1R1_FB10_Pos (10U)
<> 128:9bcdf88f62b0 3531 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 3532 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 3533 #define CAN_F1R1_FB11_Pos (11U)
<> 128:9bcdf88f62b0 3534 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 3535 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 3536 #define CAN_F1R1_FB12_Pos (12U)
<> 128:9bcdf88f62b0 3537 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 3538 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 3539 #define CAN_F1R1_FB13_Pos (13U)
<> 128:9bcdf88f62b0 3540 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 3541 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 3542 #define CAN_F1R1_FB14_Pos (14U)
<> 128:9bcdf88f62b0 3543 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 3544 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 3545 #define CAN_F1R1_FB15_Pos (15U)
<> 128:9bcdf88f62b0 3546 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 3547 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 3548 #define CAN_F1R1_FB16_Pos (16U)
<> 128:9bcdf88f62b0 3549 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 3550 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 3551 #define CAN_F1R1_FB17_Pos (17U)
<> 128:9bcdf88f62b0 3552 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 3553 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 3554 #define CAN_F1R1_FB18_Pos (18U)
<> 128:9bcdf88f62b0 3555 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 3556 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 3557 #define CAN_F1R1_FB19_Pos (19U)
<> 128:9bcdf88f62b0 3558 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 3559 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 3560 #define CAN_F1R1_FB20_Pos (20U)
<> 128:9bcdf88f62b0 3561 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 3562 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 3563 #define CAN_F1R1_FB21_Pos (21U)
<> 128:9bcdf88f62b0 3564 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 3565 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 3566 #define CAN_F1R1_FB22_Pos (22U)
<> 128:9bcdf88f62b0 3567 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 3568 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 3569 #define CAN_F1R1_FB23_Pos (23U)
<> 128:9bcdf88f62b0 3570 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 3571 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 3572 #define CAN_F1R1_FB24_Pos (24U)
<> 128:9bcdf88f62b0 3573 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 3574 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 3575 #define CAN_F1R1_FB25_Pos (25U)
<> 128:9bcdf88f62b0 3576 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 3577 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 3578 #define CAN_F1R1_FB26_Pos (26U)
<> 128:9bcdf88f62b0 3579 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 3580 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 3581 #define CAN_F1R1_FB27_Pos (27U)
<> 128:9bcdf88f62b0 3582 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 3583 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 3584 #define CAN_F1R1_FB28_Pos (28U)
<> 128:9bcdf88f62b0 3585 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 3586 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 3587 #define CAN_F1R1_FB29_Pos (29U)
<> 128:9bcdf88f62b0 3588 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 3589 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 3590 #define CAN_F1R1_FB30_Pos (30U)
<> 128:9bcdf88f62b0 3591 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 3592 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 3593 #define CAN_F1R1_FB31_Pos (31U)
<> 128:9bcdf88f62b0 3594 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 3595 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 3596
<> 128:9bcdf88f62b0 3597 /******************* Bit definition for CAN_F2R1 register *******************/
<> 128:9bcdf88f62b0 3598 #define CAN_F2R1_FB0_Pos (0U)
<> 128:9bcdf88f62b0 3599 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 3600 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 3601 #define CAN_F2R1_FB1_Pos (1U)
<> 128:9bcdf88f62b0 3602 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 3603 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 3604 #define CAN_F2R1_FB2_Pos (2U)
<> 128:9bcdf88f62b0 3605 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 3606 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 3607 #define CAN_F2R1_FB3_Pos (3U)
<> 128:9bcdf88f62b0 3608 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 3609 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 3610 #define CAN_F2R1_FB4_Pos (4U)
<> 128:9bcdf88f62b0 3611 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 3612 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 3613 #define CAN_F2R1_FB5_Pos (5U)
<> 128:9bcdf88f62b0 3614 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 3615 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 3616 #define CAN_F2R1_FB6_Pos (6U)
<> 128:9bcdf88f62b0 3617 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 3618 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 3619 #define CAN_F2R1_FB7_Pos (7U)
<> 128:9bcdf88f62b0 3620 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 3621 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 3622 #define CAN_F2R1_FB8_Pos (8U)
<> 128:9bcdf88f62b0 3623 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 3624 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 3625 #define CAN_F2R1_FB9_Pos (9U)
<> 128:9bcdf88f62b0 3626 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 3627 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 3628 #define CAN_F2R1_FB10_Pos (10U)
<> 128:9bcdf88f62b0 3629 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 3630 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 3631 #define CAN_F2R1_FB11_Pos (11U)
<> 128:9bcdf88f62b0 3632 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 3633 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 3634 #define CAN_F2R1_FB12_Pos (12U)
<> 128:9bcdf88f62b0 3635 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 3636 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 3637 #define CAN_F2R1_FB13_Pos (13U)
<> 128:9bcdf88f62b0 3638 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 3639 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 3640 #define CAN_F2R1_FB14_Pos (14U)
<> 128:9bcdf88f62b0 3641 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 3642 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 3643 #define CAN_F2R1_FB15_Pos (15U)
<> 128:9bcdf88f62b0 3644 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 3645 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 3646 #define CAN_F2R1_FB16_Pos (16U)
<> 128:9bcdf88f62b0 3647 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 3648 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 3649 #define CAN_F2R1_FB17_Pos (17U)
<> 128:9bcdf88f62b0 3650 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 3651 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 3652 #define CAN_F2R1_FB18_Pos (18U)
<> 128:9bcdf88f62b0 3653 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 3654 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 3655 #define CAN_F2R1_FB19_Pos (19U)
<> 128:9bcdf88f62b0 3656 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 3657 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 3658 #define CAN_F2R1_FB20_Pos (20U)
<> 128:9bcdf88f62b0 3659 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 3660 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 3661 #define CAN_F2R1_FB21_Pos (21U)
<> 128:9bcdf88f62b0 3662 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 3663 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 3664 #define CAN_F2R1_FB22_Pos (22U)
<> 128:9bcdf88f62b0 3665 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 3666 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 3667 #define CAN_F2R1_FB23_Pos (23U)
<> 128:9bcdf88f62b0 3668 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 3669 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 3670 #define CAN_F2R1_FB24_Pos (24U)
<> 128:9bcdf88f62b0 3671 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 3672 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 3673 #define CAN_F2R1_FB25_Pos (25U)
<> 128:9bcdf88f62b0 3674 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 3675 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 3676 #define CAN_F2R1_FB26_Pos (26U)
<> 128:9bcdf88f62b0 3677 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 3678 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 3679 #define CAN_F2R1_FB27_Pos (27U)
<> 128:9bcdf88f62b0 3680 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 3681 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 3682 #define CAN_F2R1_FB28_Pos (28U)
<> 128:9bcdf88f62b0 3683 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 3684 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 3685 #define CAN_F2R1_FB29_Pos (29U)
<> 128:9bcdf88f62b0 3686 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 3687 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 3688 #define CAN_F2R1_FB30_Pos (30U)
<> 128:9bcdf88f62b0 3689 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 3690 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 3691 #define CAN_F2R1_FB31_Pos (31U)
<> 128:9bcdf88f62b0 3692 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 3693 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 3694
<> 128:9bcdf88f62b0 3695 /******************* Bit definition for CAN_F3R1 register *******************/
<> 128:9bcdf88f62b0 3696 #define CAN_F3R1_FB0_Pos (0U)
<> 128:9bcdf88f62b0 3697 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 3698 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 3699 #define CAN_F3R1_FB1_Pos (1U)
<> 128:9bcdf88f62b0 3700 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 3701 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 3702 #define CAN_F3R1_FB2_Pos (2U)
<> 128:9bcdf88f62b0 3703 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 3704 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 3705 #define CAN_F3R1_FB3_Pos (3U)
<> 128:9bcdf88f62b0 3706 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 3707 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 3708 #define CAN_F3R1_FB4_Pos (4U)
<> 128:9bcdf88f62b0 3709 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 3710 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 3711 #define CAN_F3R1_FB5_Pos (5U)
<> 128:9bcdf88f62b0 3712 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 3713 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 3714 #define CAN_F3R1_FB6_Pos (6U)
<> 128:9bcdf88f62b0 3715 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 3716 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 3717 #define CAN_F3R1_FB7_Pos (7U)
<> 128:9bcdf88f62b0 3718 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 3719 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 3720 #define CAN_F3R1_FB8_Pos (8U)
<> 128:9bcdf88f62b0 3721 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 3722 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 3723 #define CAN_F3R1_FB9_Pos (9U)
<> 128:9bcdf88f62b0 3724 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 3725 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 3726 #define CAN_F3R1_FB10_Pos (10U)
<> 128:9bcdf88f62b0 3727 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 3728 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 3729 #define CAN_F3R1_FB11_Pos (11U)
<> 128:9bcdf88f62b0 3730 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 3731 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 3732 #define CAN_F3R1_FB12_Pos (12U)
<> 128:9bcdf88f62b0 3733 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 3734 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 3735 #define CAN_F3R1_FB13_Pos (13U)
<> 128:9bcdf88f62b0 3736 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 3737 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 3738 #define CAN_F3R1_FB14_Pos (14U)
<> 128:9bcdf88f62b0 3739 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 3740 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 3741 #define CAN_F3R1_FB15_Pos (15U)
<> 128:9bcdf88f62b0 3742 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 3743 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 3744 #define CAN_F3R1_FB16_Pos (16U)
<> 128:9bcdf88f62b0 3745 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 3746 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 3747 #define CAN_F3R1_FB17_Pos (17U)
<> 128:9bcdf88f62b0 3748 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 3749 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 3750 #define CAN_F3R1_FB18_Pos (18U)
<> 128:9bcdf88f62b0 3751 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 3752 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 3753 #define CAN_F3R1_FB19_Pos (19U)
<> 128:9bcdf88f62b0 3754 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 3755 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 3756 #define CAN_F3R1_FB20_Pos (20U)
<> 128:9bcdf88f62b0 3757 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 3758 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 3759 #define CAN_F3R1_FB21_Pos (21U)
<> 128:9bcdf88f62b0 3760 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 3761 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 3762 #define CAN_F3R1_FB22_Pos (22U)
<> 128:9bcdf88f62b0 3763 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 3764 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 3765 #define CAN_F3R1_FB23_Pos (23U)
<> 128:9bcdf88f62b0 3766 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 3767 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 3768 #define CAN_F3R1_FB24_Pos (24U)
<> 128:9bcdf88f62b0 3769 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 3770 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 3771 #define CAN_F3R1_FB25_Pos (25U)
<> 128:9bcdf88f62b0 3772 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 3773 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 3774 #define CAN_F3R1_FB26_Pos (26U)
<> 128:9bcdf88f62b0 3775 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 3776 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 3777 #define CAN_F3R1_FB27_Pos (27U)
<> 128:9bcdf88f62b0 3778 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 3779 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 3780 #define CAN_F3R1_FB28_Pos (28U)
<> 128:9bcdf88f62b0 3781 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 3782 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 3783 #define CAN_F3R1_FB29_Pos (29U)
<> 128:9bcdf88f62b0 3784 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 3785 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 3786 #define CAN_F3R1_FB30_Pos (30U)
<> 128:9bcdf88f62b0 3787 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 3788 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 3789 #define CAN_F3R1_FB31_Pos (31U)
<> 128:9bcdf88f62b0 3790 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 3791 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 3792
<> 128:9bcdf88f62b0 3793 /******************* Bit definition for CAN_F4R1 register *******************/
<> 128:9bcdf88f62b0 3794 #define CAN_F4R1_FB0_Pos (0U)
<> 128:9bcdf88f62b0 3795 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 3796 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 3797 #define CAN_F4R1_FB1_Pos (1U)
<> 128:9bcdf88f62b0 3798 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 3799 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 3800 #define CAN_F4R1_FB2_Pos (2U)
<> 128:9bcdf88f62b0 3801 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 3802 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 3803 #define CAN_F4R1_FB3_Pos (3U)
<> 128:9bcdf88f62b0 3804 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 3805 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 3806 #define CAN_F4R1_FB4_Pos (4U)
<> 128:9bcdf88f62b0 3807 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 3808 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 3809 #define CAN_F4R1_FB5_Pos (5U)
<> 128:9bcdf88f62b0 3810 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 3811 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 3812 #define CAN_F4R1_FB6_Pos (6U)
<> 128:9bcdf88f62b0 3813 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 3814 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 3815 #define CAN_F4R1_FB7_Pos (7U)
<> 128:9bcdf88f62b0 3816 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 3817 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 3818 #define CAN_F4R1_FB8_Pos (8U)
<> 128:9bcdf88f62b0 3819 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 3820 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 3821 #define CAN_F4R1_FB9_Pos (9U)
<> 128:9bcdf88f62b0 3822 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 3823 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 3824 #define CAN_F4R1_FB10_Pos (10U)
<> 128:9bcdf88f62b0 3825 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 3826 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 3827 #define CAN_F4R1_FB11_Pos (11U)
<> 128:9bcdf88f62b0 3828 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 3829 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 3830 #define CAN_F4R1_FB12_Pos (12U)
<> 128:9bcdf88f62b0 3831 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 3832 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 3833 #define CAN_F4R1_FB13_Pos (13U)
<> 128:9bcdf88f62b0 3834 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 3835 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 3836 #define CAN_F4R1_FB14_Pos (14U)
<> 128:9bcdf88f62b0 3837 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 3838 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 3839 #define CAN_F4R1_FB15_Pos (15U)
<> 128:9bcdf88f62b0 3840 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 3841 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 3842 #define CAN_F4R1_FB16_Pos (16U)
<> 128:9bcdf88f62b0 3843 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 3844 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 3845 #define CAN_F4R1_FB17_Pos (17U)
<> 128:9bcdf88f62b0 3846 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 3847 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 3848 #define CAN_F4R1_FB18_Pos (18U)
<> 128:9bcdf88f62b0 3849 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 3850 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 3851 #define CAN_F4R1_FB19_Pos (19U)
<> 128:9bcdf88f62b0 3852 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 3853 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 3854 #define CAN_F4R1_FB20_Pos (20U)
<> 128:9bcdf88f62b0 3855 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 3856 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 3857 #define CAN_F4R1_FB21_Pos (21U)
<> 128:9bcdf88f62b0 3858 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 3859 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 3860 #define CAN_F4R1_FB22_Pos (22U)
<> 128:9bcdf88f62b0 3861 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 3862 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 3863 #define CAN_F4R1_FB23_Pos (23U)
<> 128:9bcdf88f62b0 3864 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 3865 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 3866 #define CAN_F4R1_FB24_Pos (24U)
<> 128:9bcdf88f62b0 3867 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 3868 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 3869 #define CAN_F4R1_FB25_Pos (25U)
<> 128:9bcdf88f62b0 3870 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 3871 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 3872 #define CAN_F4R1_FB26_Pos (26U)
<> 128:9bcdf88f62b0 3873 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 3874 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 3875 #define CAN_F4R1_FB27_Pos (27U)
<> 128:9bcdf88f62b0 3876 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 3877 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 3878 #define CAN_F4R1_FB28_Pos (28U)
<> 128:9bcdf88f62b0 3879 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 3880 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 3881 #define CAN_F4R1_FB29_Pos (29U)
<> 128:9bcdf88f62b0 3882 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 3883 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 3884 #define CAN_F4R1_FB30_Pos (30U)
<> 128:9bcdf88f62b0 3885 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 3886 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 3887 #define CAN_F4R1_FB31_Pos (31U)
<> 128:9bcdf88f62b0 3888 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 3889 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 3890
<> 128:9bcdf88f62b0 3891 /******************* Bit definition for CAN_F5R1 register *******************/
<> 128:9bcdf88f62b0 3892 #define CAN_F5R1_FB0_Pos (0U)
<> 128:9bcdf88f62b0 3893 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 3894 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 3895 #define CAN_F5R1_FB1_Pos (1U)
<> 128:9bcdf88f62b0 3896 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 3897 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 3898 #define CAN_F5R1_FB2_Pos (2U)
<> 128:9bcdf88f62b0 3899 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 3900 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 3901 #define CAN_F5R1_FB3_Pos (3U)
<> 128:9bcdf88f62b0 3902 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 3903 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 3904 #define CAN_F5R1_FB4_Pos (4U)
<> 128:9bcdf88f62b0 3905 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 3906 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 3907 #define CAN_F5R1_FB5_Pos (5U)
<> 128:9bcdf88f62b0 3908 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 3909 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 3910 #define CAN_F5R1_FB6_Pos (6U)
<> 128:9bcdf88f62b0 3911 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 3912 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 3913 #define CAN_F5R1_FB7_Pos (7U)
<> 128:9bcdf88f62b0 3914 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 3915 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 3916 #define CAN_F5R1_FB8_Pos (8U)
<> 128:9bcdf88f62b0 3917 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 3918 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 3919 #define CAN_F5R1_FB9_Pos (9U)
<> 128:9bcdf88f62b0 3920 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 3921 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 3922 #define CAN_F5R1_FB10_Pos (10U)
<> 128:9bcdf88f62b0 3923 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 3924 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 3925 #define CAN_F5R1_FB11_Pos (11U)
<> 128:9bcdf88f62b0 3926 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 3927 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 3928 #define CAN_F5R1_FB12_Pos (12U)
<> 128:9bcdf88f62b0 3929 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 3930 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 3931 #define CAN_F5R1_FB13_Pos (13U)
<> 128:9bcdf88f62b0 3932 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 3933 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 3934 #define CAN_F5R1_FB14_Pos (14U)
<> 128:9bcdf88f62b0 3935 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 3936 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 3937 #define CAN_F5R1_FB15_Pos (15U)
<> 128:9bcdf88f62b0 3938 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 3939 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 3940 #define CAN_F5R1_FB16_Pos (16U)
<> 128:9bcdf88f62b0 3941 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 3942 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 3943 #define CAN_F5R1_FB17_Pos (17U)
<> 128:9bcdf88f62b0 3944 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 3945 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 3946 #define CAN_F5R1_FB18_Pos (18U)
<> 128:9bcdf88f62b0 3947 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 3948 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 3949 #define CAN_F5R1_FB19_Pos (19U)
<> 128:9bcdf88f62b0 3950 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 3951 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 3952 #define CAN_F5R1_FB20_Pos (20U)
<> 128:9bcdf88f62b0 3953 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 3954 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 3955 #define CAN_F5R1_FB21_Pos (21U)
<> 128:9bcdf88f62b0 3956 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 3957 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 3958 #define CAN_F5R1_FB22_Pos (22U)
<> 128:9bcdf88f62b0 3959 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 3960 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 3961 #define CAN_F5R1_FB23_Pos (23U)
<> 128:9bcdf88f62b0 3962 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 3963 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 3964 #define CAN_F5R1_FB24_Pos (24U)
<> 128:9bcdf88f62b0 3965 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 3966 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 3967 #define CAN_F5R1_FB25_Pos (25U)
<> 128:9bcdf88f62b0 3968 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 3969 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 3970 #define CAN_F5R1_FB26_Pos (26U)
<> 128:9bcdf88f62b0 3971 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 3972 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 3973 #define CAN_F5R1_FB27_Pos (27U)
<> 128:9bcdf88f62b0 3974 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 3975 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 3976 #define CAN_F5R1_FB28_Pos (28U)
<> 128:9bcdf88f62b0 3977 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 3978 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 3979 #define CAN_F5R1_FB29_Pos (29U)
<> 128:9bcdf88f62b0 3980 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 3981 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 3982 #define CAN_F5R1_FB30_Pos (30U)
<> 128:9bcdf88f62b0 3983 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 3984 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 3985 #define CAN_F5R1_FB31_Pos (31U)
<> 128:9bcdf88f62b0 3986 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 3987 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 3988
<> 128:9bcdf88f62b0 3989 /******************* Bit definition for CAN_F6R1 register *******************/
<> 128:9bcdf88f62b0 3990 #define CAN_F6R1_FB0_Pos (0U)
<> 128:9bcdf88f62b0 3991 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 3992 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 3993 #define CAN_F6R1_FB1_Pos (1U)
<> 128:9bcdf88f62b0 3994 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 3995 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 3996 #define CAN_F6R1_FB2_Pos (2U)
<> 128:9bcdf88f62b0 3997 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 3998 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 3999 #define CAN_F6R1_FB3_Pos (3U)
<> 128:9bcdf88f62b0 4000 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 4001 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 4002 #define CAN_F6R1_FB4_Pos (4U)
<> 128:9bcdf88f62b0 4003 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 4004 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 4005 #define CAN_F6R1_FB5_Pos (5U)
<> 128:9bcdf88f62b0 4006 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 4007 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 4008 #define CAN_F6R1_FB6_Pos (6U)
<> 128:9bcdf88f62b0 4009 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 4010 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 4011 #define CAN_F6R1_FB7_Pos (7U)
<> 128:9bcdf88f62b0 4012 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 4013 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 4014 #define CAN_F6R1_FB8_Pos (8U)
<> 128:9bcdf88f62b0 4015 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 4016 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 4017 #define CAN_F6R1_FB9_Pos (9U)
<> 128:9bcdf88f62b0 4018 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 4019 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 4020 #define CAN_F6R1_FB10_Pos (10U)
<> 128:9bcdf88f62b0 4021 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 4022 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 4023 #define CAN_F6R1_FB11_Pos (11U)
<> 128:9bcdf88f62b0 4024 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 4025 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 4026 #define CAN_F6R1_FB12_Pos (12U)
<> 128:9bcdf88f62b0 4027 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 4028 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 4029 #define CAN_F6R1_FB13_Pos (13U)
<> 128:9bcdf88f62b0 4030 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 4031 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 4032 #define CAN_F6R1_FB14_Pos (14U)
<> 128:9bcdf88f62b0 4033 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 4034 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 4035 #define CAN_F6R1_FB15_Pos (15U)
<> 128:9bcdf88f62b0 4036 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 4037 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 4038 #define CAN_F6R1_FB16_Pos (16U)
<> 128:9bcdf88f62b0 4039 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 4040 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 4041 #define CAN_F6R1_FB17_Pos (17U)
<> 128:9bcdf88f62b0 4042 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 4043 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 4044 #define CAN_F6R1_FB18_Pos (18U)
<> 128:9bcdf88f62b0 4045 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 4046 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 4047 #define CAN_F6R1_FB19_Pos (19U)
<> 128:9bcdf88f62b0 4048 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 4049 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 4050 #define CAN_F6R1_FB20_Pos (20U)
<> 128:9bcdf88f62b0 4051 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 4052 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 4053 #define CAN_F6R1_FB21_Pos (21U)
<> 128:9bcdf88f62b0 4054 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 4055 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 4056 #define CAN_F6R1_FB22_Pos (22U)
<> 128:9bcdf88f62b0 4057 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 4058 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 4059 #define CAN_F6R1_FB23_Pos (23U)
<> 128:9bcdf88f62b0 4060 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 4061 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 4062 #define CAN_F6R1_FB24_Pos (24U)
<> 128:9bcdf88f62b0 4063 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 4064 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 4065 #define CAN_F6R1_FB25_Pos (25U)
<> 128:9bcdf88f62b0 4066 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 4067 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 4068 #define CAN_F6R1_FB26_Pos (26U)
<> 128:9bcdf88f62b0 4069 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 4070 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 4071 #define CAN_F6R1_FB27_Pos (27U)
<> 128:9bcdf88f62b0 4072 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 4073 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 4074 #define CAN_F6R1_FB28_Pos (28U)
<> 128:9bcdf88f62b0 4075 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 4076 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 4077 #define CAN_F6R1_FB29_Pos (29U)
<> 128:9bcdf88f62b0 4078 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 4079 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 4080 #define CAN_F6R1_FB30_Pos (30U)
<> 128:9bcdf88f62b0 4081 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 4082 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 4083 #define CAN_F6R1_FB31_Pos (31U)
<> 128:9bcdf88f62b0 4084 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 4085 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 4086
<> 128:9bcdf88f62b0 4087 /******************* Bit definition for CAN_F7R1 register *******************/
<> 128:9bcdf88f62b0 4088 #define CAN_F7R1_FB0_Pos (0U)
<> 128:9bcdf88f62b0 4089 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 4090 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 4091 #define CAN_F7R1_FB1_Pos (1U)
<> 128:9bcdf88f62b0 4092 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 4093 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 4094 #define CAN_F7R1_FB2_Pos (2U)
<> 128:9bcdf88f62b0 4095 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 4096 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 4097 #define CAN_F7R1_FB3_Pos (3U)
<> 128:9bcdf88f62b0 4098 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 4099 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 4100 #define CAN_F7R1_FB4_Pos (4U)
<> 128:9bcdf88f62b0 4101 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 4102 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 4103 #define CAN_F7R1_FB5_Pos (5U)
<> 128:9bcdf88f62b0 4104 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 4105 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 4106 #define CAN_F7R1_FB6_Pos (6U)
<> 128:9bcdf88f62b0 4107 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 4108 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 4109 #define CAN_F7R1_FB7_Pos (7U)
<> 128:9bcdf88f62b0 4110 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 4111 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 4112 #define CAN_F7R1_FB8_Pos (8U)
<> 128:9bcdf88f62b0 4113 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 4114 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 4115 #define CAN_F7R1_FB9_Pos (9U)
<> 128:9bcdf88f62b0 4116 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 4117 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 4118 #define CAN_F7R1_FB10_Pos (10U)
<> 128:9bcdf88f62b0 4119 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 4120 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 4121 #define CAN_F7R1_FB11_Pos (11U)
<> 128:9bcdf88f62b0 4122 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 4123 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 4124 #define CAN_F7R1_FB12_Pos (12U)
<> 128:9bcdf88f62b0 4125 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 4126 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 4127 #define CAN_F7R1_FB13_Pos (13U)
<> 128:9bcdf88f62b0 4128 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 4129 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 4130 #define CAN_F7R1_FB14_Pos (14U)
<> 128:9bcdf88f62b0 4131 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 4132 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 4133 #define CAN_F7R1_FB15_Pos (15U)
<> 128:9bcdf88f62b0 4134 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 4135 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 4136 #define CAN_F7R1_FB16_Pos (16U)
<> 128:9bcdf88f62b0 4137 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 4138 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 4139 #define CAN_F7R1_FB17_Pos (17U)
<> 128:9bcdf88f62b0 4140 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 4141 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 4142 #define CAN_F7R1_FB18_Pos (18U)
<> 128:9bcdf88f62b0 4143 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 4144 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 4145 #define CAN_F7R1_FB19_Pos (19U)
<> 128:9bcdf88f62b0 4146 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 4147 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 4148 #define CAN_F7R1_FB20_Pos (20U)
<> 128:9bcdf88f62b0 4149 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 4150 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 4151 #define CAN_F7R1_FB21_Pos (21U)
<> 128:9bcdf88f62b0 4152 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 4153 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 4154 #define CAN_F7R1_FB22_Pos (22U)
<> 128:9bcdf88f62b0 4155 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 4156 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 4157 #define CAN_F7R1_FB23_Pos (23U)
<> 128:9bcdf88f62b0 4158 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 4159 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 4160 #define CAN_F7R1_FB24_Pos (24U)
<> 128:9bcdf88f62b0 4161 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 4162 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 4163 #define CAN_F7R1_FB25_Pos (25U)
<> 128:9bcdf88f62b0 4164 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 4165 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 4166 #define CAN_F7R1_FB26_Pos (26U)
<> 128:9bcdf88f62b0 4167 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 4168 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 4169 #define CAN_F7R1_FB27_Pos (27U)
<> 128:9bcdf88f62b0 4170 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 4171 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 4172 #define CAN_F7R1_FB28_Pos (28U)
<> 128:9bcdf88f62b0 4173 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 4174 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 4175 #define CAN_F7R1_FB29_Pos (29U)
<> 128:9bcdf88f62b0 4176 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 4177 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 4178 #define CAN_F7R1_FB30_Pos (30U)
<> 128:9bcdf88f62b0 4179 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 4180 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 4181 #define CAN_F7R1_FB31_Pos (31U)
<> 128:9bcdf88f62b0 4182 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 4183 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 4184
<> 128:9bcdf88f62b0 4185 /******************* Bit definition for CAN_F8R1 register *******************/
<> 128:9bcdf88f62b0 4186 #define CAN_F8R1_FB0_Pos (0U)
<> 128:9bcdf88f62b0 4187 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 4188 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 4189 #define CAN_F8R1_FB1_Pos (1U)
<> 128:9bcdf88f62b0 4190 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 4191 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 4192 #define CAN_F8R1_FB2_Pos (2U)
<> 128:9bcdf88f62b0 4193 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 4194 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 4195 #define CAN_F8R1_FB3_Pos (3U)
<> 128:9bcdf88f62b0 4196 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 4197 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 4198 #define CAN_F8R1_FB4_Pos (4U)
<> 128:9bcdf88f62b0 4199 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 4200 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 4201 #define CAN_F8R1_FB5_Pos (5U)
<> 128:9bcdf88f62b0 4202 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 4203 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 4204 #define CAN_F8R1_FB6_Pos (6U)
<> 128:9bcdf88f62b0 4205 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 4206 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 4207 #define CAN_F8R1_FB7_Pos (7U)
<> 128:9bcdf88f62b0 4208 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 4209 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 4210 #define CAN_F8R1_FB8_Pos (8U)
<> 128:9bcdf88f62b0 4211 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 4212 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 4213 #define CAN_F8R1_FB9_Pos (9U)
<> 128:9bcdf88f62b0 4214 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 4215 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 4216 #define CAN_F8R1_FB10_Pos (10U)
<> 128:9bcdf88f62b0 4217 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 4218 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 4219 #define CAN_F8R1_FB11_Pos (11U)
<> 128:9bcdf88f62b0 4220 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 4221 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 4222 #define CAN_F8R1_FB12_Pos (12U)
<> 128:9bcdf88f62b0 4223 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 4224 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 4225 #define CAN_F8R1_FB13_Pos (13U)
<> 128:9bcdf88f62b0 4226 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 4227 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 4228 #define CAN_F8R1_FB14_Pos (14U)
<> 128:9bcdf88f62b0 4229 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 4230 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 4231 #define CAN_F8R1_FB15_Pos (15U)
<> 128:9bcdf88f62b0 4232 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 4233 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 4234 #define CAN_F8R1_FB16_Pos (16U)
<> 128:9bcdf88f62b0 4235 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 4236 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 4237 #define CAN_F8R1_FB17_Pos (17U)
<> 128:9bcdf88f62b0 4238 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 4239 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 4240 #define CAN_F8R1_FB18_Pos (18U)
<> 128:9bcdf88f62b0 4241 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 4242 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 4243 #define CAN_F8R1_FB19_Pos (19U)
<> 128:9bcdf88f62b0 4244 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 4245 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 4246 #define CAN_F8R1_FB20_Pos (20U)
<> 128:9bcdf88f62b0 4247 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 4248 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 4249 #define CAN_F8R1_FB21_Pos (21U)
<> 128:9bcdf88f62b0 4250 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 4251 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 4252 #define CAN_F8R1_FB22_Pos (22U)
<> 128:9bcdf88f62b0 4253 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 4254 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 4255 #define CAN_F8R1_FB23_Pos (23U)
<> 128:9bcdf88f62b0 4256 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 4257 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 4258 #define CAN_F8R1_FB24_Pos (24U)
<> 128:9bcdf88f62b0 4259 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 4260 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 4261 #define CAN_F8R1_FB25_Pos (25U)
<> 128:9bcdf88f62b0 4262 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 4263 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 4264 #define CAN_F8R1_FB26_Pos (26U)
<> 128:9bcdf88f62b0 4265 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 4266 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 4267 #define CAN_F8R1_FB27_Pos (27U)
<> 128:9bcdf88f62b0 4268 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 4269 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 4270 #define CAN_F8R1_FB28_Pos (28U)
<> 128:9bcdf88f62b0 4271 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 4272 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 4273 #define CAN_F8R1_FB29_Pos (29U)
<> 128:9bcdf88f62b0 4274 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 4275 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 4276 #define CAN_F8R1_FB30_Pos (30U)
<> 128:9bcdf88f62b0 4277 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 4278 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 4279 #define CAN_F8R1_FB31_Pos (31U)
<> 128:9bcdf88f62b0 4280 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 4281 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 4282
<> 128:9bcdf88f62b0 4283 /******************* Bit definition for CAN_F9R1 register *******************/
<> 128:9bcdf88f62b0 4284 #define CAN_F9R1_FB0_Pos (0U)
<> 128:9bcdf88f62b0 4285 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 4286 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 4287 #define CAN_F9R1_FB1_Pos (1U)
<> 128:9bcdf88f62b0 4288 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 4289 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 4290 #define CAN_F9R1_FB2_Pos (2U)
<> 128:9bcdf88f62b0 4291 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 4292 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 4293 #define CAN_F9R1_FB3_Pos (3U)
<> 128:9bcdf88f62b0 4294 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 4295 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 4296 #define CAN_F9R1_FB4_Pos (4U)
<> 128:9bcdf88f62b0 4297 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 4298 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 4299 #define CAN_F9R1_FB5_Pos (5U)
<> 128:9bcdf88f62b0 4300 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 4301 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 4302 #define CAN_F9R1_FB6_Pos (6U)
<> 128:9bcdf88f62b0 4303 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 4304 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 4305 #define CAN_F9R1_FB7_Pos (7U)
<> 128:9bcdf88f62b0 4306 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 4307 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 4308 #define CAN_F9R1_FB8_Pos (8U)
<> 128:9bcdf88f62b0 4309 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 4310 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 4311 #define CAN_F9R1_FB9_Pos (9U)
<> 128:9bcdf88f62b0 4312 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 4313 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 4314 #define CAN_F9R1_FB10_Pos (10U)
<> 128:9bcdf88f62b0 4315 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 4316 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 4317 #define CAN_F9R1_FB11_Pos (11U)
<> 128:9bcdf88f62b0 4318 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 4319 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 4320 #define CAN_F9R1_FB12_Pos (12U)
<> 128:9bcdf88f62b0 4321 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 4322 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 4323 #define CAN_F9R1_FB13_Pos (13U)
<> 128:9bcdf88f62b0 4324 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 4325 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 4326 #define CAN_F9R1_FB14_Pos (14U)
<> 128:9bcdf88f62b0 4327 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 4328 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 4329 #define CAN_F9R1_FB15_Pos (15U)
<> 128:9bcdf88f62b0 4330 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 4331 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 4332 #define CAN_F9R1_FB16_Pos (16U)
<> 128:9bcdf88f62b0 4333 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 4334 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 4335 #define CAN_F9R1_FB17_Pos (17U)
<> 128:9bcdf88f62b0 4336 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 4337 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 4338 #define CAN_F9R1_FB18_Pos (18U)
<> 128:9bcdf88f62b0 4339 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 4340 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 4341 #define CAN_F9R1_FB19_Pos (19U)
<> 128:9bcdf88f62b0 4342 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 4343 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 4344 #define CAN_F9R1_FB20_Pos (20U)
<> 128:9bcdf88f62b0 4345 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 4346 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 4347 #define CAN_F9R1_FB21_Pos (21U)
<> 128:9bcdf88f62b0 4348 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 4349 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 4350 #define CAN_F9R1_FB22_Pos (22U)
<> 128:9bcdf88f62b0 4351 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 4352 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 4353 #define CAN_F9R1_FB23_Pos (23U)
<> 128:9bcdf88f62b0 4354 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 4355 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 4356 #define CAN_F9R1_FB24_Pos (24U)
<> 128:9bcdf88f62b0 4357 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 4358 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 4359 #define CAN_F9R1_FB25_Pos (25U)
<> 128:9bcdf88f62b0 4360 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 4361 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 4362 #define CAN_F9R1_FB26_Pos (26U)
<> 128:9bcdf88f62b0 4363 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 4364 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 4365 #define CAN_F9R1_FB27_Pos (27U)
<> 128:9bcdf88f62b0 4366 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 4367 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 4368 #define CAN_F9R1_FB28_Pos (28U)
<> 128:9bcdf88f62b0 4369 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 4370 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 4371 #define CAN_F9R1_FB29_Pos (29U)
<> 128:9bcdf88f62b0 4372 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 4373 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 4374 #define CAN_F9R1_FB30_Pos (30U)
<> 128:9bcdf88f62b0 4375 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 4376 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 4377 #define CAN_F9R1_FB31_Pos (31U)
<> 128:9bcdf88f62b0 4378 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 4379 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 4380
<> 128:9bcdf88f62b0 4381 /******************* Bit definition for CAN_F10R1 register ******************/
<> 128:9bcdf88f62b0 4382 #define CAN_F10R1_FB0_Pos (0U)
<> 128:9bcdf88f62b0 4383 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 4384 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 4385 #define CAN_F10R1_FB1_Pos (1U)
<> 128:9bcdf88f62b0 4386 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 4387 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 4388 #define CAN_F10R1_FB2_Pos (2U)
<> 128:9bcdf88f62b0 4389 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 4390 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 4391 #define CAN_F10R1_FB3_Pos (3U)
<> 128:9bcdf88f62b0 4392 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 4393 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 4394 #define CAN_F10R1_FB4_Pos (4U)
<> 128:9bcdf88f62b0 4395 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 4396 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 4397 #define CAN_F10R1_FB5_Pos (5U)
<> 128:9bcdf88f62b0 4398 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 4399 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 4400 #define CAN_F10R1_FB6_Pos (6U)
<> 128:9bcdf88f62b0 4401 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 4402 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 4403 #define CAN_F10R1_FB7_Pos (7U)
<> 128:9bcdf88f62b0 4404 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 4405 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 4406 #define CAN_F10R1_FB8_Pos (8U)
<> 128:9bcdf88f62b0 4407 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 4408 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 4409 #define CAN_F10R1_FB9_Pos (9U)
<> 128:9bcdf88f62b0 4410 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 4411 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 4412 #define CAN_F10R1_FB10_Pos (10U)
<> 128:9bcdf88f62b0 4413 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 4414 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 4415 #define CAN_F10R1_FB11_Pos (11U)
<> 128:9bcdf88f62b0 4416 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 4417 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 4418 #define CAN_F10R1_FB12_Pos (12U)
<> 128:9bcdf88f62b0 4419 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 4420 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 4421 #define CAN_F10R1_FB13_Pos (13U)
<> 128:9bcdf88f62b0 4422 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 4423 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 4424 #define CAN_F10R1_FB14_Pos (14U)
<> 128:9bcdf88f62b0 4425 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 4426 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 4427 #define CAN_F10R1_FB15_Pos (15U)
<> 128:9bcdf88f62b0 4428 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 4429 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 4430 #define CAN_F10R1_FB16_Pos (16U)
<> 128:9bcdf88f62b0 4431 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 4432 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 4433 #define CAN_F10R1_FB17_Pos (17U)
<> 128:9bcdf88f62b0 4434 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 4435 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 4436 #define CAN_F10R1_FB18_Pos (18U)
<> 128:9bcdf88f62b0 4437 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 4438 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 4439 #define CAN_F10R1_FB19_Pos (19U)
<> 128:9bcdf88f62b0 4440 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 4441 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 4442 #define CAN_F10R1_FB20_Pos (20U)
<> 128:9bcdf88f62b0 4443 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 4444 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 4445 #define CAN_F10R1_FB21_Pos (21U)
<> 128:9bcdf88f62b0 4446 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 4447 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 4448 #define CAN_F10R1_FB22_Pos (22U)
<> 128:9bcdf88f62b0 4449 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 4450 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 4451 #define CAN_F10R1_FB23_Pos (23U)
<> 128:9bcdf88f62b0 4452 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 4453 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 4454 #define CAN_F10R1_FB24_Pos (24U)
<> 128:9bcdf88f62b0 4455 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 4456 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 4457 #define CAN_F10R1_FB25_Pos (25U)
<> 128:9bcdf88f62b0 4458 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 4459 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 4460 #define CAN_F10R1_FB26_Pos (26U)
<> 128:9bcdf88f62b0 4461 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 4462 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 4463 #define CAN_F10R1_FB27_Pos (27U)
<> 128:9bcdf88f62b0 4464 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 4465 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 4466 #define CAN_F10R1_FB28_Pos (28U)
<> 128:9bcdf88f62b0 4467 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 4468 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 4469 #define CAN_F10R1_FB29_Pos (29U)
<> 128:9bcdf88f62b0 4470 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 4471 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 4472 #define CAN_F10R1_FB30_Pos (30U)
<> 128:9bcdf88f62b0 4473 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 4474 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 4475 #define CAN_F10R1_FB31_Pos (31U)
<> 128:9bcdf88f62b0 4476 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 4477 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 4478
<> 128:9bcdf88f62b0 4479 /******************* Bit definition for CAN_F11R1 register ******************/
<> 128:9bcdf88f62b0 4480 #define CAN_F11R1_FB0_Pos (0U)
<> 128:9bcdf88f62b0 4481 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 4482 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 4483 #define CAN_F11R1_FB1_Pos (1U)
<> 128:9bcdf88f62b0 4484 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 4485 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 4486 #define CAN_F11R1_FB2_Pos (2U)
<> 128:9bcdf88f62b0 4487 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 4488 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 4489 #define CAN_F11R1_FB3_Pos (3U)
<> 128:9bcdf88f62b0 4490 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 4491 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 4492 #define CAN_F11R1_FB4_Pos (4U)
<> 128:9bcdf88f62b0 4493 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 4494 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 4495 #define CAN_F11R1_FB5_Pos (5U)
<> 128:9bcdf88f62b0 4496 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 4497 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 4498 #define CAN_F11R1_FB6_Pos (6U)
<> 128:9bcdf88f62b0 4499 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 4500 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 4501 #define CAN_F11R1_FB7_Pos (7U)
<> 128:9bcdf88f62b0 4502 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 4503 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 4504 #define CAN_F11R1_FB8_Pos (8U)
<> 128:9bcdf88f62b0 4505 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 4506 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 4507 #define CAN_F11R1_FB9_Pos (9U)
<> 128:9bcdf88f62b0 4508 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 4509 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 4510 #define CAN_F11R1_FB10_Pos (10U)
<> 128:9bcdf88f62b0 4511 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 4512 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 4513 #define CAN_F11R1_FB11_Pos (11U)
<> 128:9bcdf88f62b0 4514 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 4515 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 4516 #define CAN_F11R1_FB12_Pos (12U)
<> 128:9bcdf88f62b0 4517 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 4518 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 4519 #define CAN_F11R1_FB13_Pos (13U)
<> 128:9bcdf88f62b0 4520 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 4521 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 4522 #define CAN_F11R1_FB14_Pos (14U)
<> 128:9bcdf88f62b0 4523 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 4524 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 4525 #define CAN_F11R1_FB15_Pos (15U)
<> 128:9bcdf88f62b0 4526 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 4527 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 4528 #define CAN_F11R1_FB16_Pos (16U)
<> 128:9bcdf88f62b0 4529 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 4530 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 4531 #define CAN_F11R1_FB17_Pos (17U)
<> 128:9bcdf88f62b0 4532 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 4533 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 4534 #define CAN_F11R1_FB18_Pos (18U)
<> 128:9bcdf88f62b0 4535 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 4536 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 4537 #define CAN_F11R1_FB19_Pos (19U)
<> 128:9bcdf88f62b0 4538 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 4539 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 4540 #define CAN_F11R1_FB20_Pos (20U)
<> 128:9bcdf88f62b0 4541 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 4542 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 4543 #define CAN_F11R1_FB21_Pos (21U)
<> 128:9bcdf88f62b0 4544 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 4545 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 4546 #define CAN_F11R1_FB22_Pos (22U)
<> 128:9bcdf88f62b0 4547 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 4548 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 4549 #define CAN_F11R1_FB23_Pos (23U)
<> 128:9bcdf88f62b0 4550 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 4551 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 4552 #define CAN_F11R1_FB24_Pos (24U)
<> 128:9bcdf88f62b0 4553 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 4554 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 4555 #define CAN_F11R1_FB25_Pos (25U)
<> 128:9bcdf88f62b0 4556 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 4557 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 4558 #define CAN_F11R1_FB26_Pos (26U)
<> 128:9bcdf88f62b0 4559 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 4560 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 4561 #define CAN_F11R1_FB27_Pos (27U)
<> 128:9bcdf88f62b0 4562 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 4563 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 4564 #define CAN_F11R1_FB28_Pos (28U)
<> 128:9bcdf88f62b0 4565 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 4566 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 4567 #define CAN_F11R1_FB29_Pos (29U)
<> 128:9bcdf88f62b0 4568 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 4569 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 4570 #define CAN_F11R1_FB30_Pos (30U)
<> 128:9bcdf88f62b0 4571 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 4572 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 4573 #define CAN_F11R1_FB31_Pos (31U)
<> 128:9bcdf88f62b0 4574 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 4575 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 4576
<> 128:9bcdf88f62b0 4577 /******************* Bit definition for CAN_F12R1 register ******************/
<> 128:9bcdf88f62b0 4578 #define CAN_F12R1_FB0_Pos (0U)
<> 128:9bcdf88f62b0 4579 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 4580 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 4581 #define CAN_F12R1_FB1_Pos (1U)
<> 128:9bcdf88f62b0 4582 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 4583 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 4584 #define CAN_F12R1_FB2_Pos (2U)
<> 128:9bcdf88f62b0 4585 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 4586 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 4587 #define CAN_F12R1_FB3_Pos (3U)
<> 128:9bcdf88f62b0 4588 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 4589 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 4590 #define CAN_F12R1_FB4_Pos (4U)
<> 128:9bcdf88f62b0 4591 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 4592 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 4593 #define CAN_F12R1_FB5_Pos (5U)
<> 128:9bcdf88f62b0 4594 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 4595 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 4596 #define CAN_F12R1_FB6_Pos (6U)
<> 128:9bcdf88f62b0 4597 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 4598 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 4599 #define CAN_F12R1_FB7_Pos (7U)
<> 128:9bcdf88f62b0 4600 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 4601 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 4602 #define CAN_F12R1_FB8_Pos (8U)
<> 128:9bcdf88f62b0 4603 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 4604 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 4605 #define CAN_F12R1_FB9_Pos (9U)
<> 128:9bcdf88f62b0 4606 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 4607 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 4608 #define CAN_F12R1_FB10_Pos (10U)
<> 128:9bcdf88f62b0 4609 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 4610 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 4611 #define CAN_F12R1_FB11_Pos (11U)
<> 128:9bcdf88f62b0 4612 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 4613 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 4614 #define CAN_F12R1_FB12_Pos (12U)
<> 128:9bcdf88f62b0 4615 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 4616 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 4617 #define CAN_F12R1_FB13_Pos (13U)
<> 128:9bcdf88f62b0 4618 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 4619 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 4620 #define CAN_F12R1_FB14_Pos (14U)
<> 128:9bcdf88f62b0 4621 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 4622 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 4623 #define CAN_F12R1_FB15_Pos (15U)
<> 128:9bcdf88f62b0 4624 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 4625 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 4626 #define CAN_F12R1_FB16_Pos (16U)
<> 128:9bcdf88f62b0 4627 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 4628 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 4629 #define CAN_F12R1_FB17_Pos (17U)
<> 128:9bcdf88f62b0 4630 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 4631 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 4632 #define CAN_F12R1_FB18_Pos (18U)
<> 128:9bcdf88f62b0 4633 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 4634 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 4635 #define CAN_F12R1_FB19_Pos (19U)
<> 128:9bcdf88f62b0 4636 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 4637 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 4638 #define CAN_F12R1_FB20_Pos (20U)
<> 128:9bcdf88f62b0 4639 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 4640 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 4641 #define CAN_F12R1_FB21_Pos (21U)
<> 128:9bcdf88f62b0 4642 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 4643 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 4644 #define CAN_F12R1_FB22_Pos (22U)
<> 128:9bcdf88f62b0 4645 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 4646 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 4647 #define CAN_F12R1_FB23_Pos (23U)
<> 128:9bcdf88f62b0 4648 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 4649 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 4650 #define CAN_F12R1_FB24_Pos (24U)
<> 128:9bcdf88f62b0 4651 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 4652 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 4653 #define CAN_F12R1_FB25_Pos (25U)
<> 128:9bcdf88f62b0 4654 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 4655 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 4656 #define CAN_F12R1_FB26_Pos (26U)
<> 128:9bcdf88f62b0 4657 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 4658 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 4659 #define CAN_F12R1_FB27_Pos (27U)
<> 128:9bcdf88f62b0 4660 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 4661 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 4662 #define CAN_F12R1_FB28_Pos (28U)
<> 128:9bcdf88f62b0 4663 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 4664 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 4665 #define CAN_F12R1_FB29_Pos (29U)
<> 128:9bcdf88f62b0 4666 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 4667 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 4668 #define CAN_F12R1_FB30_Pos (30U)
<> 128:9bcdf88f62b0 4669 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 4670 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 4671 #define CAN_F12R1_FB31_Pos (31U)
<> 128:9bcdf88f62b0 4672 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 4673 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 4674
<> 128:9bcdf88f62b0 4675 /******************* Bit definition for CAN_F13R1 register ******************/
<> 128:9bcdf88f62b0 4676 #define CAN_F13R1_FB0_Pos (0U)
<> 128:9bcdf88f62b0 4677 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 4678 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 4679 #define CAN_F13R1_FB1_Pos (1U)
<> 128:9bcdf88f62b0 4680 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 4681 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 4682 #define CAN_F13R1_FB2_Pos (2U)
<> 128:9bcdf88f62b0 4683 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 4684 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 4685 #define CAN_F13R1_FB3_Pos (3U)
<> 128:9bcdf88f62b0 4686 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 4687 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 4688 #define CAN_F13R1_FB4_Pos (4U)
<> 128:9bcdf88f62b0 4689 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 4690 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 4691 #define CAN_F13R1_FB5_Pos (5U)
<> 128:9bcdf88f62b0 4692 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 4693 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 4694 #define CAN_F13R1_FB6_Pos (6U)
<> 128:9bcdf88f62b0 4695 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 4696 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 4697 #define CAN_F13R1_FB7_Pos (7U)
<> 128:9bcdf88f62b0 4698 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 4699 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 4700 #define CAN_F13R1_FB8_Pos (8U)
<> 128:9bcdf88f62b0 4701 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 4702 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 4703 #define CAN_F13R1_FB9_Pos (9U)
<> 128:9bcdf88f62b0 4704 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 4705 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 4706 #define CAN_F13R1_FB10_Pos (10U)
<> 128:9bcdf88f62b0 4707 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 4708 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 4709 #define CAN_F13R1_FB11_Pos (11U)
<> 128:9bcdf88f62b0 4710 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 4711 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 4712 #define CAN_F13R1_FB12_Pos (12U)
<> 128:9bcdf88f62b0 4713 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 4714 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 4715 #define CAN_F13R1_FB13_Pos (13U)
<> 128:9bcdf88f62b0 4716 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 4717 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 4718 #define CAN_F13R1_FB14_Pos (14U)
<> 128:9bcdf88f62b0 4719 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 4720 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 4721 #define CAN_F13R1_FB15_Pos (15U)
<> 128:9bcdf88f62b0 4722 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 4723 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 4724 #define CAN_F13R1_FB16_Pos (16U)
<> 128:9bcdf88f62b0 4725 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 4726 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 4727 #define CAN_F13R1_FB17_Pos (17U)
<> 128:9bcdf88f62b0 4728 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 4729 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 4730 #define CAN_F13R1_FB18_Pos (18U)
<> 128:9bcdf88f62b0 4731 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 4732 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 4733 #define CAN_F13R1_FB19_Pos (19U)
<> 128:9bcdf88f62b0 4734 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 4735 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 4736 #define CAN_F13R1_FB20_Pos (20U)
<> 128:9bcdf88f62b0 4737 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 4738 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 4739 #define CAN_F13R1_FB21_Pos (21U)
<> 128:9bcdf88f62b0 4740 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 4741 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 4742 #define CAN_F13R1_FB22_Pos (22U)
<> 128:9bcdf88f62b0 4743 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 4744 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 4745 #define CAN_F13R1_FB23_Pos (23U)
<> 128:9bcdf88f62b0 4746 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 4747 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 4748 #define CAN_F13R1_FB24_Pos (24U)
<> 128:9bcdf88f62b0 4749 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 4750 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 4751 #define CAN_F13R1_FB25_Pos (25U)
<> 128:9bcdf88f62b0 4752 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 4753 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 4754 #define CAN_F13R1_FB26_Pos (26U)
<> 128:9bcdf88f62b0 4755 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 4756 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 4757 #define CAN_F13R1_FB27_Pos (27U)
<> 128:9bcdf88f62b0 4758 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 4759 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 4760 #define CAN_F13R1_FB28_Pos (28U)
<> 128:9bcdf88f62b0 4761 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 4762 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 4763 #define CAN_F13R1_FB29_Pos (29U)
<> 128:9bcdf88f62b0 4764 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 4765 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 4766 #define CAN_F13R1_FB30_Pos (30U)
<> 128:9bcdf88f62b0 4767 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 4768 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 4769 #define CAN_F13R1_FB31_Pos (31U)
<> 128:9bcdf88f62b0 4770 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 4771 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 4772
<> 128:9bcdf88f62b0 4773 /******************* Bit definition for CAN_F0R2 register *******************/
<> 128:9bcdf88f62b0 4774 #define CAN_F0R2_FB0_Pos (0U)
<> 128:9bcdf88f62b0 4775 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 4776 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 4777 #define CAN_F0R2_FB1_Pos (1U)
<> 128:9bcdf88f62b0 4778 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 4779 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 4780 #define CAN_F0R2_FB2_Pos (2U)
<> 128:9bcdf88f62b0 4781 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 4782 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 4783 #define CAN_F0R2_FB3_Pos (3U)
<> 128:9bcdf88f62b0 4784 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 4785 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 4786 #define CAN_F0R2_FB4_Pos (4U)
<> 128:9bcdf88f62b0 4787 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 4788 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 4789 #define CAN_F0R2_FB5_Pos (5U)
<> 128:9bcdf88f62b0 4790 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 4791 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 4792 #define CAN_F0R2_FB6_Pos (6U)
<> 128:9bcdf88f62b0 4793 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 4794 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 4795 #define CAN_F0R2_FB7_Pos (7U)
<> 128:9bcdf88f62b0 4796 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 4797 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 4798 #define CAN_F0R2_FB8_Pos (8U)
<> 128:9bcdf88f62b0 4799 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 4800 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 4801 #define CAN_F0R2_FB9_Pos (9U)
<> 128:9bcdf88f62b0 4802 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 4803 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 4804 #define CAN_F0R2_FB10_Pos (10U)
<> 128:9bcdf88f62b0 4805 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 4806 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 4807 #define CAN_F0R2_FB11_Pos (11U)
<> 128:9bcdf88f62b0 4808 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 4809 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 4810 #define CAN_F0R2_FB12_Pos (12U)
<> 128:9bcdf88f62b0 4811 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 4812 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 4813 #define CAN_F0R2_FB13_Pos (13U)
<> 128:9bcdf88f62b0 4814 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 4815 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 4816 #define CAN_F0R2_FB14_Pos (14U)
<> 128:9bcdf88f62b0 4817 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 4818 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 4819 #define CAN_F0R2_FB15_Pos (15U)
<> 128:9bcdf88f62b0 4820 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 4821 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 4822 #define CAN_F0R2_FB16_Pos (16U)
<> 128:9bcdf88f62b0 4823 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 4824 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 4825 #define CAN_F0R2_FB17_Pos (17U)
<> 128:9bcdf88f62b0 4826 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 4827 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 4828 #define CAN_F0R2_FB18_Pos (18U)
<> 128:9bcdf88f62b0 4829 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 4830 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 4831 #define CAN_F0R2_FB19_Pos (19U)
<> 128:9bcdf88f62b0 4832 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 4833 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 4834 #define CAN_F0R2_FB20_Pos (20U)
<> 128:9bcdf88f62b0 4835 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 4836 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 4837 #define CAN_F0R2_FB21_Pos (21U)
<> 128:9bcdf88f62b0 4838 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 4839 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 4840 #define CAN_F0R2_FB22_Pos (22U)
<> 128:9bcdf88f62b0 4841 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 4842 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 4843 #define CAN_F0R2_FB23_Pos (23U)
<> 128:9bcdf88f62b0 4844 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 4845 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 4846 #define CAN_F0R2_FB24_Pos (24U)
<> 128:9bcdf88f62b0 4847 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 4848 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 4849 #define CAN_F0R2_FB25_Pos (25U)
<> 128:9bcdf88f62b0 4850 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 4851 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 4852 #define CAN_F0R2_FB26_Pos (26U)
<> 128:9bcdf88f62b0 4853 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 4854 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 4855 #define CAN_F0R2_FB27_Pos (27U)
<> 128:9bcdf88f62b0 4856 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 4857 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 4858 #define CAN_F0R2_FB28_Pos (28U)
<> 128:9bcdf88f62b0 4859 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 4860 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 4861 #define CAN_F0R2_FB29_Pos (29U)
<> 128:9bcdf88f62b0 4862 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 4863 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 4864 #define CAN_F0R2_FB30_Pos (30U)
<> 128:9bcdf88f62b0 4865 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 4866 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 4867 #define CAN_F0R2_FB31_Pos (31U)
<> 128:9bcdf88f62b0 4868 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 4869 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 4870
<> 128:9bcdf88f62b0 4871 /******************* Bit definition for CAN_F1R2 register *******************/
<> 128:9bcdf88f62b0 4872 #define CAN_F1R2_FB0_Pos (0U)
<> 128:9bcdf88f62b0 4873 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 4874 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 4875 #define CAN_F1R2_FB1_Pos (1U)
<> 128:9bcdf88f62b0 4876 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 4877 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 4878 #define CAN_F1R2_FB2_Pos (2U)
<> 128:9bcdf88f62b0 4879 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 4880 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 4881 #define CAN_F1R2_FB3_Pos (3U)
<> 128:9bcdf88f62b0 4882 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 4883 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 4884 #define CAN_F1R2_FB4_Pos (4U)
<> 128:9bcdf88f62b0 4885 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 4886 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 4887 #define CAN_F1R2_FB5_Pos (5U)
<> 128:9bcdf88f62b0 4888 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 4889 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 4890 #define CAN_F1R2_FB6_Pos (6U)
<> 128:9bcdf88f62b0 4891 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 4892 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 4893 #define CAN_F1R2_FB7_Pos (7U)
<> 128:9bcdf88f62b0 4894 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 4895 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 4896 #define CAN_F1R2_FB8_Pos (8U)
<> 128:9bcdf88f62b0 4897 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 4898 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 4899 #define CAN_F1R2_FB9_Pos (9U)
<> 128:9bcdf88f62b0 4900 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 4901 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 4902 #define CAN_F1R2_FB10_Pos (10U)
<> 128:9bcdf88f62b0 4903 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 4904 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 4905 #define CAN_F1R2_FB11_Pos (11U)
<> 128:9bcdf88f62b0 4906 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 4907 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 4908 #define CAN_F1R2_FB12_Pos (12U)
<> 128:9bcdf88f62b0 4909 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 4910 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 4911 #define CAN_F1R2_FB13_Pos (13U)
<> 128:9bcdf88f62b0 4912 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 4913 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 4914 #define CAN_F1R2_FB14_Pos (14U)
<> 128:9bcdf88f62b0 4915 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 4916 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 4917 #define CAN_F1R2_FB15_Pos (15U)
<> 128:9bcdf88f62b0 4918 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 4919 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 4920 #define CAN_F1R2_FB16_Pos (16U)
<> 128:9bcdf88f62b0 4921 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 4922 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 4923 #define CAN_F1R2_FB17_Pos (17U)
<> 128:9bcdf88f62b0 4924 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 4925 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 4926 #define CAN_F1R2_FB18_Pos (18U)
<> 128:9bcdf88f62b0 4927 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 4928 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 4929 #define CAN_F1R2_FB19_Pos (19U)
<> 128:9bcdf88f62b0 4930 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 4931 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 4932 #define CAN_F1R2_FB20_Pos (20U)
<> 128:9bcdf88f62b0 4933 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 4934 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 4935 #define CAN_F1R2_FB21_Pos (21U)
<> 128:9bcdf88f62b0 4936 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 4937 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 4938 #define CAN_F1R2_FB22_Pos (22U)
<> 128:9bcdf88f62b0 4939 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 4940 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 4941 #define CAN_F1R2_FB23_Pos (23U)
<> 128:9bcdf88f62b0 4942 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 4943 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 4944 #define CAN_F1R2_FB24_Pos (24U)
<> 128:9bcdf88f62b0 4945 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 4946 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 4947 #define CAN_F1R2_FB25_Pos (25U)
<> 128:9bcdf88f62b0 4948 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 4949 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 4950 #define CAN_F1R2_FB26_Pos (26U)
<> 128:9bcdf88f62b0 4951 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 4952 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 4953 #define CAN_F1R2_FB27_Pos (27U)
<> 128:9bcdf88f62b0 4954 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 4955 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 4956 #define CAN_F1R2_FB28_Pos (28U)
<> 128:9bcdf88f62b0 4957 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 4958 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 4959 #define CAN_F1R2_FB29_Pos (29U)
<> 128:9bcdf88f62b0 4960 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 4961 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 4962 #define CAN_F1R2_FB30_Pos (30U)
<> 128:9bcdf88f62b0 4963 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 4964 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 4965 #define CAN_F1R2_FB31_Pos (31U)
<> 128:9bcdf88f62b0 4966 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 4967 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 4968
<> 128:9bcdf88f62b0 4969 /******************* Bit definition for CAN_F2R2 register *******************/
<> 128:9bcdf88f62b0 4970 #define CAN_F2R2_FB0_Pos (0U)
<> 128:9bcdf88f62b0 4971 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 4972 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 4973 #define CAN_F2R2_FB1_Pos (1U)
<> 128:9bcdf88f62b0 4974 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 4975 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 4976 #define CAN_F2R2_FB2_Pos (2U)
<> 128:9bcdf88f62b0 4977 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 4978 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 4979 #define CAN_F2R2_FB3_Pos (3U)
<> 128:9bcdf88f62b0 4980 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 4981 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 4982 #define CAN_F2R2_FB4_Pos (4U)
<> 128:9bcdf88f62b0 4983 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 4984 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 4985 #define CAN_F2R2_FB5_Pos (5U)
<> 128:9bcdf88f62b0 4986 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 4987 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 4988 #define CAN_F2R2_FB6_Pos (6U)
<> 128:9bcdf88f62b0 4989 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 4990 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 4991 #define CAN_F2R2_FB7_Pos (7U)
<> 128:9bcdf88f62b0 4992 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 4993 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 4994 #define CAN_F2R2_FB8_Pos (8U)
<> 128:9bcdf88f62b0 4995 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 4996 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 4997 #define CAN_F2R2_FB9_Pos (9U)
<> 128:9bcdf88f62b0 4998 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 4999 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 5000 #define CAN_F2R2_FB10_Pos (10U)
<> 128:9bcdf88f62b0 5001 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 5002 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 5003 #define CAN_F2R2_FB11_Pos (11U)
<> 128:9bcdf88f62b0 5004 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 5005 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 5006 #define CAN_F2R2_FB12_Pos (12U)
<> 128:9bcdf88f62b0 5007 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 5008 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 5009 #define CAN_F2R2_FB13_Pos (13U)
<> 128:9bcdf88f62b0 5010 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 5011 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 5012 #define CAN_F2R2_FB14_Pos (14U)
<> 128:9bcdf88f62b0 5013 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 5014 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 5015 #define CAN_F2R2_FB15_Pos (15U)
<> 128:9bcdf88f62b0 5016 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 5017 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 5018 #define CAN_F2R2_FB16_Pos (16U)
<> 128:9bcdf88f62b0 5019 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 5020 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 5021 #define CAN_F2R2_FB17_Pos (17U)
<> 128:9bcdf88f62b0 5022 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 5023 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 5024 #define CAN_F2R2_FB18_Pos (18U)
<> 128:9bcdf88f62b0 5025 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 5026 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 5027 #define CAN_F2R2_FB19_Pos (19U)
<> 128:9bcdf88f62b0 5028 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 5029 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 5030 #define CAN_F2R2_FB20_Pos (20U)
<> 128:9bcdf88f62b0 5031 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 5032 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 5033 #define CAN_F2R2_FB21_Pos (21U)
<> 128:9bcdf88f62b0 5034 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 5035 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 5036 #define CAN_F2R2_FB22_Pos (22U)
<> 128:9bcdf88f62b0 5037 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 5038 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 5039 #define CAN_F2R2_FB23_Pos (23U)
<> 128:9bcdf88f62b0 5040 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 5041 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 5042 #define CAN_F2R2_FB24_Pos (24U)
<> 128:9bcdf88f62b0 5043 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 5044 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 5045 #define CAN_F2R2_FB25_Pos (25U)
<> 128:9bcdf88f62b0 5046 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 5047 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 5048 #define CAN_F2R2_FB26_Pos (26U)
<> 128:9bcdf88f62b0 5049 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 5050 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 5051 #define CAN_F2R2_FB27_Pos (27U)
<> 128:9bcdf88f62b0 5052 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 5053 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 5054 #define CAN_F2R2_FB28_Pos (28U)
<> 128:9bcdf88f62b0 5055 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 5056 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 5057 #define CAN_F2R2_FB29_Pos (29U)
<> 128:9bcdf88f62b0 5058 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 5059 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 5060 #define CAN_F2R2_FB30_Pos (30U)
<> 128:9bcdf88f62b0 5061 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 5062 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 5063 #define CAN_F2R2_FB31_Pos (31U)
<> 128:9bcdf88f62b0 5064 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 5065 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 5066
<> 128:9bcdf88f62b0 5067 /******************* Bit definition for CAN_F3R2 register *******************/
<> 128:9bcdf88f62b0 5068 #define CAN_F3R2_FB0_Pos (0U)
<> 128:9bcdf88f62b0 5069 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 5070 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 5071 #define CAN_F3R2_FB1_Pos (1U)
<> 128:9bcdf88f62b0 5072 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 5073 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 5074 #define CAN_F3R2_FB2_Pos (2U)
<> 128:9bcdf88f62b0 5075 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 5076 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 5077 #define CAN_F3R2_FB3_Pos (3U)
<> 128:9bcdf88f62b0 5078 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 5079 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 5080 #define CAN_F3R2_FB4_Pos (4U)
<> 128:9bcdf88f62b0 5081 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 5082 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 5083 #define CAN_F3R2_FB5_Pos (5U)
<> 128:9bcdf88f62b0 5084 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 5085 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 5086 #define CAN_F3R2_FB6_Pos (6U)
<> 128:9bcdf88f62b0 5087 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 5088 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 5089 #define CAN_F3R2_FB7_Pos (7U)
<> 128:9bcdf88f62b0 5090 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 5091 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 5092 #define CAN_F3R2_FB8_Pos (8U)
<> 128:9bcdf88f62b0 5093 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 5094 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 5095 #define CAN_F3R2_FB9_Pos (9U)
<> 128:9bcdf88f62b0 5096 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 5097 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 5098 #define CAN_F3R2_FB10_Pos (10U)
<> 128:9bcdf88f62b0 5099 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 5100 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 5101 #define CAN_F3R2_FB11_Pos (11U)
<> 128:9bcdf88f62b0 5102 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 5103 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 5104 #define CAN_F3R2_FB12_Pos (12U)
<> 128:9bcdf88f62b0 5105 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 5106 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 5107 #define CAN_F3R2_FB13_Pos (13U)
<> 128:9bcdf88f62b0 5108 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 5109 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 5110 #define CAN_F3R2_FB14_Pos (14U)
<> 128:9bcdf88f62b0 5111 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 5112 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 5113 #define CAN_F3R2_FB15_Pos (15U)
<> 128:9bcdf88f62b0 5114 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 5115 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 5116 #define CAN_F3R2_FB16_Pos (16U)
<> 128:9bcdf88f62b0 5117 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 5118 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 5119 #define CAN_F3R2_FB17_Pos (17U)
<> 128:9bcdf88f62b0 5120 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 5121 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 5122 #define CAN_F3R2_FB18_Pos (18U)
<> 128:9bcdf88f62b0 5123 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 5124 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 5125 #define CAN_F3R2_FB19_Pos (19U)
<> 128:9bcdf88f62b0 5126 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 5127 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 5128 #define CAN_F3R2_FB20_Pos (20U)
<> 128:9bcdf88f62b0 5129 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 5130 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 5131 #define CAN_F3R2_FB21_Pos (21U)
<> 128:9bcdf88f62b0 5132 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 5133 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 5134 #define CAN_F3R2_FB22_Pos (22U)
<> 128:9bcdf88f62b0 5135 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 5136 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 5137 #define CAN_F3R2_FB23_Pos (23U)
<> 128:9bcdf88f62b0 5138 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 5139 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 5140 #define CAN_F3R2_FB24_Pos (24U)
<> 128:9bcdf88f62b0 5141 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 5142 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 5143 #define CAN_F3R2_FB25_Pos (25U)
<> 128:9bcdf88f62b0 5144 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 5145 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 5146 #define CAN_F3R2_FB26_Pos (26U)
<> 128:9bcdf88f62b0 5147 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 5148 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 5149 #define CAN_F3R2_FB27_Pos (27U)
<> 128:9bcdf88f62b0 5150 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 5151 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 5152 #define CAN_F3R2_FB28_Pos (28U)
<> 128:9bcdf88f62b0 5153 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 5154 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 5155 #define CAN_F3R2_FB29_Pos (29U)
<> 128:9bcdf88f62b0 5156 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 5157 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 5158 #define CAN_F3R2_FB30_Pos (30U)
<> 128:9bcdf88f62b0 5159 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 5160 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 5161 #define CAN_F3R2_FB31_Pos (31U)
<> 128:9bcdf88f62b0 5162 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 5163 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 5164
<> 128:9bcdf88f62b0 5165 /******************* Bit definition for CAN_F4R2 register *******************/
<> 128:9bcdf88f62b0 5166 #define CAN_F4R2_FB0_Pos (0U)
<> 128:9bcdf88f62b0 5167 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 5168 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 5169 #define CAN_F4R2_FB1_Pos (1U)
<> 128:9bcdf88f62b0 5170 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 5171 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 5172 #define CAN_F4R2_FB2_Pos (2U)
<> 128:9bcdf88f62b0 5173 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 5174 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 5175 #define CAN_F4R2_FB3_Pos (3U)
<> 128:9bcdf88f62b0 5176 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 5177 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 5178 #define CAN_F4R2_FB4_Pos (4U)
<> 128:9bcdf88f62b0 5179 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 5180 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 5181 #define CAN_F4R2_FB5_Pos (5U)
<> 128:9bcdf88f62b0 5182 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 5183 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 5184 #define CAN_F4R2_FB6_Pos (6U)
<> 128:9bcdf88f62b0 5185 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 5186 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 5187 #define CAN_F4R2_FB7_Pos (7U)
<> 128:9bcdf88f62b0 5188 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 5189 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 5190 #define CAN_F4R2_FB8_Pos (8U)
<> 128:9bcdf88f62b0 5191 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 5192 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 5193 #define CAN_F4R2_FB9_Pos (9U)
<> 128:9bcdf88f62b0 5194 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 5195 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 5196 #define CAN_F4R2_FB10_Pos (10U)
<> 128:9bcdf88f62b0 5197 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 5198 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 5199 #define CAN_F4R2_FB11_Pos (11U)
<> 128:9bcdf88f62b0 5200 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 5201 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 5202 #define CAN_F4R2_FB12_Pos (12U)
<> 128:9bcdf88f62b0 5203 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 5204 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 5205 #define CAN_F4R2_FB13_Pos (13U)
<> 128:9bcdf88f62b0 5206 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 5207 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 5208 #define CAN_F4R2_FB14_Pos (14U)
<> 128:9bcdf88f62b0 5209 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 5210 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 5211 #define CAN_F4R2_FB15_Pos (15U)
<> 128:9bcdf88f62b0 5212 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 5213 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 5214 #define CAN_F4R2_FB16_Pos (16U)
<> 128:9bcdf88f62b0 5215 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 5216 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 5217 #define CAN_F4R2_FB17_Pos (17U)
<> 128:9bcdf88f62b0 5218 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 5219 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 5220 #define CAN_F4R2_FB18_Pos (18U)
<> 128:9bcdf88f62b0 5221 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 5222 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 5223 #define CAN_F4R2_FB19_Pos (19U)
<> 128:9bcdf88f62b0 5224 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 5225 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 5226 #define CAN_F4R2_FB20_Pos (20U)
<> 128:9bcdf88f62b0 5227 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 5228 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 5229 #define CAN_F4R2_FB21_Pos (21U)
<> 128:9bcdf88f62b0 5230 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 5231 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 5232 #define CAN_F4R2_FB22_Pos (22U)
<> 128:9bcdf88f62b0 5233 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 5234 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 5235 #define CAN_F4R2_FB23_Pos (23U)
<> 128:9bcdf88f62b0 5236 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 5237 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 5238 #define CAN_F4R2_FB24_Pos (24U)
<> 128:9bcdf88f62b0 5239 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 5240 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 5241 #define CAN_F4R2_FB25_Pos (25U)
<> 128:9bcdf88f62b0 5242 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 5243 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 5244 #define CAN_F4R2_FB26_Pos (26U)
<> 128:9bcdf88f62b0 5245 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 5246 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 5247 #define CAN_F4R2_FB27_Pos (27U)
<> 128:9bcdf88f62b0 5248 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 5249 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 5250 #define CAN_F4R2_FB28_Pos (28U)
<> 128:9bcdf88f62b0 5251 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 5252 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 5253 #define CAN_F4R2_FB29_Pos (29U)
<> 128:9bcdf88f62b0 5254 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 5255 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 5256 #define CAN_F4R2_FB30_Pos (30U)
<> 128:9bcdf88f62b0 5257 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 5258 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 5259 #define CAN_F4R2_FB31_Pos (31U)
<> 128:9bcdf88f62b0 5260 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 5261 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 5262
<> 128:9bcdf88f62b0 5263 /******************* Bit definition for CAN_F5R2 register *******************/
<> 128:9bcdf88f62b0 5264 #define CAN_F5R2_FB0_Pos (0U)
<> 128:9bcdf88f62b0 5265 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 5266 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 5267 #define CAN_F5R2_FB1_Pos (1U)
<> 128:9bcdf88f62b0 5268 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 5269 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 5270 #define CAN_F5R2_FB2_Pos (2U)
<> 128:9bcdf88f62b0 5271 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 5272 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 5273 #define CAN_F5R2_FB3_Pos (3U)
<> 128:9bcdf88f62b0 5274 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 5275 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 5276 #define CAN_F5R2_FB4_Pos (4U)
<> 128:9bcdf88f62b0 5277 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 5278 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 5279 #define CAN_F5R2_FB5_Pos (5U)
<> 128:9bcdf88f62b0 5280 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 5281 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 5282 #define CAN_F5R2_FB6_Pos (6U)
<> 128:9bcdf88f62b0 5283 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 5284 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 5285 #define CAN_F5R2_FB7_Pos (7U)
<> 128:9bcdf88f62b0 5286 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 5287 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 5288 #define CAN_F5R2_FB8_Pos (8U)
<> 128:9bcdf88f62b0 5289 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 5290 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 5291 #define CAN_F5R2_FB9_Pos (9U)
<> 128:9bcdf88f62b0 5292 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 5293 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 5294 #define CAN_F5R2_FB10_Pos (10U)
<> 128:9bcdf88f62b0 5295 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 5296 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 5297 #define CAN_F5R2_FB11_Pos (11U)
<> 128:9bcdf88f62b0 5298 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 5299 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 5300 #define CAN_F5R2_FB12_Pos (12U)
<> 128:9bcdf88f62b0 5301 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 5302 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 5303 #define CAN_F5R2_FB13_Pos (13U)
<> 128:9bcdf88f62b0 5304 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 5305 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 5306 #define CAN_F5R2_FB14_Pos (14U)
<> 128:9bcdf88f62b0 5307 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 5308 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 5309 #define CAN_F5R2_FB15_Pos (15U)
<> 128:9bcdf88f62b0 5310 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 5311 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 5312 #define CAN_F5R2_FB16_Pos (16U)
<> 128:9bcdf88f62b0 5313 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 5314 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 5315 #define CAN_F5R2_FB17_Pos (17U)
<> 128:9bcdf88f62b0 5316 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 5317 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 5318 #define CAN_F5R2_FB18_Pos (18U)
<> 128:9bcdf88f62b0 5319 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 5320 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 5321 #define CAN_F5R2_FB19_Pos (19U)
<> 128:9bcdf88f62b0 5322 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 5323 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 5324 #define CAN_F5R2_FB20_Pos (20U)
<> 128:9bcdf88f62b0 5325 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 5326 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 5327 #define CAN_F5R2_FB21_Pos (21U)
<> 128:9bcdf88f62b0 5328 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 5329 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 5330 #define CAN_F5R2_FB22_Pos (22U)
<> 128:9bcdf88f62b0 5331 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 5332 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 5333 #define CAN_F5R2_FB23_Pos (23U)
<> 128:9bcdf88f62b0 5334 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 5335 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 5336 #define CAN_F5R2_FB24_Pos (24U)
<> 128:9bcdf88f62b0 5337 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 5338 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 5339 #define CAN_F5R2_FB25_Pos (25U)
<> 128:9bcdf88f62b0 5340 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 5341 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 5342 #define CAN_F5R2_FB26_Pos (26U)
<> 128:9bcdf88f62b0 5343 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 5344 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 5345 #define CAN_F5R2_FB27_Pos (27U)
<> 128:9bcdf88f62b0 5346 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 5347 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 5348 #define CAN_F5R2_FB28_Pos (28U)
<> 128:9bcdf88f62b0 5349 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 5350 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 5351 #define CAN_F5R2_FB29_Pos (29U)
<> 128:9bcdf88f62b0 5352 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 5353 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 5354 #define CAN_F5R2_FB30_Pos (30U)
<> 128:9bcdf88f62b0 5355 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 5356 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 5357 #define CAN_F5R2_FB31_Pos (31U)
<> 128:9bcdf88f62b0 5358 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 5359 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 5360
<> 128:9bcdf88f62b0 5361 /******************* Bit definition for CAN_F6R2 register *******************/
<> 128:9bcdf88f62b0 5362 #define CAN_F6R2_FB0_Pos (0U)
<> 128:9bcdf88f62b0 5363 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 5364 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 5365 #define CAN_F6R2_FB1_Pos (1U)
<> 128:9bcdf88f62b0 5366 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 5367 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 5368 #define CAN_F6R2_FB2_Pos (2U)
<> 128:9bcdf88f62b0 5369 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 5370 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 5371 #define CAN_F6R2_FB3_Pos (3U)
<> 128:9bcdf88f62b0 5372 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 5373 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 5374 #define CAN_F6R2_FB4_Pos (4U)
<> 128:9bcdf88f62b0 5375 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 5376 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 5377 #define CAN_F6R2_FB5_Pos (5U)
<> 128:9bcdf88f62b0 5378 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 5379 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 5380 #define CAN_F6R2_FB6_Pos (6U)
<> 128:9bcdf88f62b0 5381 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 5382 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 5383 #define CAN_F6R2_FB7_Pos (7U)
<> 128:9bcdf88f62b0 5384 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 5385 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 5386 #define CAN_F6R2_FB8_Pos (8U)
<> 128:9bcdf88f62b0 5387 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 5388 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 5389 #define CAN_F6R2_FB9_Pos (9U)
<> 128:9bcdf88f62b0 5390 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 5391 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 5392 #define CAN_F6R2_FB10_Pos (10U)
<> 128:9bcdf88f62b0 5393 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 5394 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 5395 #define CAN_F6R2_FB11_Pos (11U)
<> 128:9bcdf88f62b0 5396 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 5397 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 5398 #define CAN_F6R2_FB12_Pos (12U)
<> 128:9bcdf88f62b0 5399 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 5400 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 5401 #define CAN_F6R2_FB13_Pos (13U)
<> 128:9bcdf88f62b0 5402 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 5403 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 5404 #define CAN_F6R2_FB14_Pos (14U)
<> 128:9bcdf88f62b0 5405 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 5406 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 5407 #define CAN_F6R2_FB15_Pos (15U)
<> 128:9bcdf88f62b0 5408 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 5409 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 5410 #define CAN_F6R2_FB16_Pos (16U)
<> 128:9bcdf88f62b0 5411 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 5412 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 5413 #define CAN_F6R2_FB17_Pos (17U)
<> 128:9bcdf88f62b0 5414 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 5415 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 5416 #define CAN_F6R2_FB18_Pos (18U)
<> 128:9bcdf88f62b0 5417 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 5418 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 5419 #define CAN_F6R2_FB19_Pos (19U)
<> 128:9bcdf88f62b0 5420 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 5421 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 5422 #define CAN_F6R2_FB20_Pos (20U)
<> 128:9bcdf88f62b0 5423 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 5424 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 5425 #define CAN_F6R2_FB21_Pos (21U)
<> 128:9bcdf88f62b0 5426 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 5427 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 5428 #define CAN_F6R2_FB22_Pos (22U)
<> 128:9bcdf88f62b0 5429 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 5430 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 5431 #define CAN_F6R2_FB23_Pos (23U)
<> 128:9bcdf88f62b0 5432 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 5433 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 5434 #define CAN_F6R2_FB24_Pos (24U)
<> 128:9bcdf88f62b0 5435 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 5436 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 5437 #define CAN_F6R2_FB25_Pos (25U)
<> 128:9bcdf88f62b0 5438 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 5439 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 5440 #define CAN_F6R2_FB26_Pos (26U)
<> 128:9bcdf88f62b0 5441 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 5442 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 5443 #define CAN_F6R2_FB27_Pos (27U)
<> 128:9bcdf88f62b0 5444 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 5445 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 5446 #define CAN_F6R2_FB28_Pos (28U)
<> 128:9bcdf88f62b0 5447 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 5448 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 5449 #define CAN_F6R2_FB29_Pos (29U)
<> 128:9bcdf88f62b0 5450 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 5451 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 5452 #define CAN_F6R2_FB30_Pos (30U)
<> 128:9bcdf88f62b0 5453 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 5454 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 5455 #define CAN_F6R2_FB31_Pos (31U)
<> 128:9bcdf88f62b0 5456 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 5457 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 5458
<> 128:9bcdf88f62b0 5459 /******************* Bit definition for CAN_F7R2 register *******************/
<> 128:9bcdf88f62b0 5460 #define CAN_F7R2_FB0_Pos (0U)
<> 128:9bcdf88f62b0 5461 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 5462 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 5463 #define CAN_F7R2_FB1_Pos (1U)
<> 128:9bcdf88f62b0 5464 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 5465 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 5466 #define CAN_F7R2_FB2_Pos (2U)
<> 128:9bcdf88f62b0 5467 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 5468 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 5469 #define CAN_F7R2_FB3_Pos (3U)
<> 128:9bcdf88f62b0 5470 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 5471 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 5472 #define CAN_F7R2_FB4_Pos (4U)
<> 128:9bcdf88f62b0 5473 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 5474 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 5475 #define CAN_F7R2_FB5_Pos (5U)
<> 128:9bcdf88f62b0 5476 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 5477 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 5478 #define CAN_F7R2_FB6_Pos (6U)
<> 128:9bcdf88f62b0 5479 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 5480 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 5481 #define CAN_F7R2_FB7_Pos (7U)
<> 128:9bcdf88f62b0 5482 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 5483 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 5484 #define CAN_F7R2_FB8_Pos (8U)
<> 128:9bcdf88f62b0 5485 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 5486 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 5487 #define CAN_F7R2_FB9_Pos (9U)
<> 128:9bcdf88f62b0 5488 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 5489 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 5490 #define CAN_F7R2_FB10_Pos (10U)
<> 128:9bcdf88f62b0 5491 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 5492 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 5493 #define CAN_F7R2_FB11_Pos (11U)
<> 128:9bcdf88f62b0 5494 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 5495 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 5496 #define CAN_F7R2_FB12_Pos (12U)
<> 128:9bcdf88f62b0 5497 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 5498 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 5499 #define CAN_F7R2_FB13_Pos (13U)
<> 128:9bcdf88f62b0 5500 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 5501 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 5502 #define CAN_F7R2_FB14_Pos (14U)
<> 128:9bcdf88f62b0 5503 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 5504 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 5505 #define CAN_F7R2_FB15_Pos (15U)
<> 128:9bcdf88f62b0 5506 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 5507 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 5508 #define CAN_F7R2_FB16_Pos (16U)
<> 128:9bcdf88f62b0 5509 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 5510 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 5511 #define CAN_F7R2_FB17_Pos (17U)
<> 128:9bcdf88f62b0 5512 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 5513 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 5514 #define CAN_F7R2_FB18_Pos (18U)
<> 128:9bcdf88f62b0 5515 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 5516 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 5517 #define CAN_F7R2_FB19_Pos (19U)
<> 128:9bcdf88f62b0 5518 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 5519 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 5520 #define CAN_F7R2_FB20_Pos (20U)
<> 128:9bcdf88f62b0 5521 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 5522 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 5523 #define CAN_F7R2_FB21_Pos (21U)
<> 128:9bcdf88f62b0 5524 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 5525 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 5526 #define CAN_F7R2_FB22_Pos (22U)
<> 128:9bcdf88f62b0 5527 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 5528 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 5529 #define CAN_F7R2_FB23_Pos (23U)
<> 128:9bcdf88f62b0 5530 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 5531 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 5532 #define CAN_F7R2_FB24_Pos (24U)
<> 128:9bcdf88f62b0 5533 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 5534 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 5535 #define CAN_F7R2_FB25_Pos (25U)
<> 128:9bcdf88f62b0 5536 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 5537 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 5538 #define CAN_F7R2_FB26_Pos (26U)
<> 128:9bcdf88f62b0 5539 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 5540 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 5541 #define CAN_F7R2_FB27_Pos (27U)
<> 128:9bcdf88f62b0 5542 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 5543 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 5544 #define CAN_F7R2_FB28_Pos (28U)
<> 128:9bcdf88f62b0 5545 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 5546 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 5547 #define CAN_F7R2_FB29_Pos (29U)
<> 128:9bcdf88f62b0 5548 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 5549 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 5550 #define CAN_F7R2_FB30_Pos (30U)
<> 128:9bcdf88f62b0 5551 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 5552 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 5553 #define CAN_F7R2_FB31_Pos (31U)
<> 128:9bcdf88f62b0 5554 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 5555 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 5556
<> 128:9bcdf88f62b0 5557 /******************* Bit definition for CAN_F8R2 register *******************/
<> 128:9bcdf88f62b0 5558 #define CAN_F8R2_FB0_Pos (0U)
<> 128:9bcdf88f62b0 5559 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 5560 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 5561 #define CAN_F8R2_FB1_Pos (1U)
<> 128:9bcdf88f62b0 5562 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 5563 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 5564 #define CAN_F8R2_FB2_Pos (2U)
<> 128:9bcdf88f62b0 5565 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 5566 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 5567 #define CAN_F8R2_FB3_Pos (3U)
<> 128:9bcdf88f62b0 5568 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 5569 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 5570 #define CAN_F8R2_FB4_Pos (4U)
<> 128:9bcdf88f62b0 5571 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 5572 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 5573 #define CAN_F8R2_FB5_Pos (5U)
<> 128:9bcdf88f62b0 5574 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 5575 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 5576 #define CAN_F8R2_FB6_Pos (6U)
<> 128:9bcdf88f62b0 5577 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 5578 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 5579 #define CAN_F8R2_FB7_Pos (7U)
<> 128:9bcdf88f62b0 5580 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 5581 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 5582 #define CAN_F8R2_FB8_Pos (8U)
<> 128:9bcdf88f62b0 5583 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 5584 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 5585 #define CAN_F8R2_FB9_Pos (9U)
<> 128:9bcdf88f62b0 5586 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 5587 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 5588 #define CAN_F8R2_FB10_Pos (10U)
<> 128:9bcdf88f62b0 5589 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 5590 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 5591 #define CAN_F8R2_FB11_Pos (11U)
<> 128:9bcdf88f62b0 5592 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 5593 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 5594 #define CAN_F8R2_FB12_Pos (12U)
<> 128:9bcdf88f62b0 5595 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 5596 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 5597 #define CAN_F8R2_FB13_Pos (13U)
<> 128:9bcdf88f62b0 5598 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 5599 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 5600 #define CAN_F8R2_FB14_Pos (14U)
<> 128:9bcdf88f62b0 5601 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 5602 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 5603 #define CAN_F8R2_FB15_Pos (15U)
<> 128:9bcdf88f62b0 5604 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 5605 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 5606 #define CAN_F8R2_FB16_Pos (16U)
<> 128:9bcdf88f62b0 5607 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 5608 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 5609 #define CAN_F8R2_FB17_Pos (17U)
<> 128:9bcdf88f62b0 5610 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 5611 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 5612 #define CAN_F8R2_FB18_Pos (18U)
<> 128:9bcdf88f62b0 5613 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 5614 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 5615 #define CAN_F8R2_FB19_Pos (19U)
<> 128:9bcdf88f62b0 5616 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 5617 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 5618 #define CAN_F8R2_FB20_Pos (20U)
<> 128:9bcdf88f62b0 5619 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 5620 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 5621 #define CAN_F8R2_FB21_Pos (21U)
<> 128:9bcdf88f62b0 5622 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 5623 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 5624 #define CAN_F8R2_FB22_Pos (22U)
<> 128:9bcdf88f62b0 5625 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 5626 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 5627 #define CAN_F8R2_FB23_Pos (23U)
<> 128:9bcdf88f62b0 5628 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 5629 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 5630 #define CAN_F8R2_FB24_Pos (24U)
<> 128:9bcdf88f62b0 5631 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 5632 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 5633 #define CAN_F8R2_FB25_Pos (25U)
<> 128:9bcdf88f62b0 5634 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 5635 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 5636 #define CAN_F8R2_FB26_Pos (26U)
<> 128:9bcdf88f62b0 5637 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 5638 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 5639 #define CAN_F8R2_FB27_Pos (27U)
<> 128:9bcdf88f62b0 5640 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 5641 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 5642 #define CAN_F8R2_FB28_Pos (28U)
<> 128:9bcdf88f62b0 5643 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 5644 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 5645 #define CAN_F8R2_FB29_Pos (29U)
<> 128:9bcdf88f62b0 5646 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 5647 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 5648 #define CAN_F8R2_FB30_Pos (30U)
<> 128:9bcdf88f62b0 5649 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 5650 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 5651 #define CAN_F8R2_FB31_Pos (31U)
<> 128:9bcdf88f62b0 5652 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 5653 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 5654
<> 128:9bcdf88f62b0 5655 /******************* Bit definition for CAN_F9R2 register *******************/
<> 128:9bcdf88f62b0 5656 #define CAN_F9R2_FB0_Pos (0U)
<> 128:9bcdf88f62b0 5657 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 5658 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 5659 #define CAN_F9R2_FB1_Pos (1U)
<> 128:9bcdf88f62b0 5660 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 5661 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 5662 #define CAN_F9R2_FB2_Pos (2U)
<> 128:9bcdf88f62b0 5663 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 5664 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 5665 #define CAN_F9R2_FB3_Pos (3U)
<> 128:9bcdf88f62b0 5666 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 5667 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 5668 #define CAN_F9R2_FB4_Pos (4U)
<> 128:9bcdf88f62b0 5669 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 5670 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 5671 #define CAN_F9R2_FB5_Pos (5U)
<> 128:9bcdf88f62b0 5672 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 5673 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 5674 #define CAN_F9R2_FB6_Pos (6U)
<> 128:9bcdf88f62b0 5675 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 5676 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 5677 #define CAN_F9R2_FB7_Pos (7U)
<> 128:9bcdf88f62b0 5678 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 5679 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 5680 #define CAN_F9R2_FB8_Pos (8U)
<> 128:9bcdf88f62b0 5681 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 5682 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 5683 #define CAN_F9R2_FB9_Pos (9U)
<> 128:9bcdf88f62b0 5684 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 5685 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 5686 #define CAN_F9R2_FB10_Pos (10U)
<> 128:9bcdf88f62b0 5687 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 5688 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 5689 #define CAN_F9R2_FB11_Pos (11U)
<> 128:9bcdf88f62b0 5690 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 5691 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 5692 #define CAN_F9R2_FB12_Pos (12U)
<> 128:9bcdf88f62b0 5693 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 5694 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 5695 #define CAN_F9R2_FB13_Pos (13U)
<> 128:9bcdf88f62b0 5696 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 5697 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 5698 #define CAN_F9R2_FB14_Pos (14U)
<> 128:9bcdf88f62b0 5699 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 5700 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 5701 #define CAN_F9R2_FB15_Pos (15U)
<> 128:9bcdf88f62b0 5702 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 5703 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 5704 #define CAN_F9R2_FB16_Pos (16U)
<> 128:9bcdf88f62b0 5705 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 5706 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 5707 #define CAN_F9R2_FB17_Pos (17U)
<> 128:9bcdf88f62b0 5708 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 5709 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 5710 #define CAN_F9R2_FB18_Pos (18U)
<> 128:9bcdf88f62b0 5711 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 5712 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 5713 #define CAN_F9R2_FB19_Pos (19U)
<> 128:9bcdf88f62b0 5714 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 5715 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 5716 #define CAN_F9R2_FB20_Pos (20U)
<> 128:9bcdf88f62b0 5717 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 5718 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 5719 #define CAN_F9R2_FB21_Pos (21U)
<> 128:9bcdf88f62b0 5720 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 5721 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 5722 #define CAN_F9R2_FB22_Pos (22U)
<> 128:9bcdf88f62b0 5723 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 5724 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 5725 #define CAN_F9R2_FB23_Pos (23U)
<> 128:9bcdf88f62b0 5726 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 5727 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 5728 #define CAN_F9R2_FB24_Pos (24U)
<> 128:9bcdf88f62b0 5729 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 5730 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 5731 #define CAN_F9R2_FB25_Pos (25U)
<> 128:9bcdf88f62b0 5732 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 5733 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 5734 #define CAN_F9R2_FB26_Pos (26U)
<> 128:9bcdf88f62b0 5735 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 5736 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 5737 #define CAN_F9R2_FB27_Pos (27U)
<> 128:9bcdf88f62b0 5738 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 5739 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 5740 #define CAN_F9R2_FB28_Pos (28U)
<> 128:9bcdf88f62b0 5741 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 5742 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 5743 #define CAN_F9R2_FB29_Pos (29U)
<> 128:9bcdf88f62b0 5744 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 5745 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 5746 #define CAN_F9R2_FB30_Pos (30U)
<> 128:9bcdf88f62b0 5747 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 5748 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 5749 #define CAN_F9R2_FB31_Pos (31U)
<> 128:9bcdf88f62b0 5750 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 5751 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 5752
<> 128:9bcdf88f62b0 5753 /******************* Bit definition for CAN_F10R2 register ******************/
<> 128:9bcdf88f62b0 5754 #define CAN_F10R2_FB0_Pos (0U)
<> 128:9bcdf88f62b0 5755 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 5756 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 5757 #define CAN_F10R2_FB1_Pos (1U)
<> 128:9bcdf88f62b0 5758 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 5759 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 5760 #define CAN_F10R2_FB2_Pos (2U)
<> 128:9bcdf88f62b0 5761 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 5762 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 5763 #define CAN_F10R2_FB3_Pos (3U)
<> 128:9bcdf88f62b0 5764 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 5765 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 5766 #define CAN_F10R2_FB4_Pos (4U)
<> 128:9bcdf88f62b0 5767 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 5768 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 5769 #define CAN_F10R2_FB5_Pos (5U)
<> 128:9bcdf88f62b0 5770 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 5771 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 5772 #define CAN_F10R2_FB6_Pos (6U)
<> 128:9bcdf88f62b0 5773 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 5774 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 5775 #define CAN_F10R2_FB7_Pos (7U)
<> 128:9bcdf88f62b0 5776 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 5777 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 5778 #define CAN_F10R2_FB8_Pos (8U)
<> 128:9bcdf88f62b0 5779 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 5780 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 5781 #define CAN_F10R2_FB9_Pos (9U)
<> 128:9bcdf88f62b0 5782 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 5783 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 5784 #define CAN_F10R2_FB10_Pos (10U)
<> 128:9bcdf88f62b0 5785 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 5786 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 5787 #define CAN_F10R2_FB11_Pos (11U)
<> 128:9bcdf88f62b0 5788 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 5789 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 5790 #define CAN_F10R2_FB12_Pos (12U)
<> 128:9bcdf88f62b0 5791 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 5792 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 5793 #define CAN_F10R2_FB13_Pos (13U)
<> 128:9bcdf88f62b0 5794 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 5795 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 5796 #define CAN_F10R2_FB14_Pos (14U)
<> 128:9bcdf88f62b0 5797 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 5798 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 5799 #define CAN_F10R2_FB15_Pos (15U)
<> 128:9bcdf88f62b0 5800 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 5801 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 5802 #define CAN_F10R2_FB16_Pos (16U)
<> 128:9bcdf88f62b0 5803 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 5804 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 5805 #define CAN_F10R2_FB17_Pos (17U)
<> 128:9bcdf88f62b0 5806 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 5807 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 5808 #define CAN_F10R2_FB18_Pos (18U)
<> 128:9bcdf88f62b0 5809 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 5810 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 5811 #define CAN_F10R2_FB19_Pos (19U)
<> 128:9bcdf88f62b0 5812 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 5813 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 5814 #define CAN_F10R2_FB20_Pos (20U)
<> 128:9bcdf88f62b0 5815 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 5816 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 5817 #define CAN_F10R2_FB21_Pos (21U)
<> 128:9bcdf88f62b0 5818 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 5819 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 5820 #define CAN_F10R2_FB22_Pos (22U)
<> 128:9bcdf88f62b0 5821 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 5822 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 5823 #define CAN_F10R2_FB23_Pos (23U)
<> 128:9bcdf88f62b0 5824 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 5825 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 5826 #define CAN_F10R2_FB24_Pos (24U)
<> 128:9bcdf88f62b0 5827 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 5828 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 5829 #define CAN_F10R2_FB25_Pos (25U)
<> 128:9bcdf88f62b0 5830 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 5831 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 5832 #define CAN_F10R2_FB26_Pos (26U)
<> 128:9bcdf88f62b0 5833 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 5834 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 5835 #define CAN_F10R2_FB27_Pos (27U)
<> 128:9bcdf88f62b0 5836 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 5837 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 5838 #define CAN_F10R2_FB28_Pos (28U)
<> 128:9bcdf88f62b0 5839 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 5840 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 5841 #define CAN_F10R2_FB29_Pos (29U)
<> 128:9bcdf88f62b0 5842 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 5843 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 5844 #define CAN_F10R2_FB30_Pos (30U)
<> 128:9bcdf88f62b0 5845 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 5846 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 5847 #define CAN_F10R2_FB31_Pos (31U)
<> 128:9bcdf88f62b0 5848 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 5849 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 5850
<> 128:9bcdf88f62b0 5851 /******************* Bit definition for CAN_F11R2 register ******************/
<> 128:9bcdf88f62b0 5852 #define CAN_F11R2_FB0_Pos (0U)
<> 128:9bcdf88f62b0 5853 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 5854 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 5855 #define CAN_F11R2_FB1_Pos (1U)
<> 128:9bcdf88f62b0 5856 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 5857 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 5858 #define CAN_F11R2_FB2_Pos (2U)
<> 128:9bcdf88f62b0 5859 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 5860 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 5861 #define CAN_F11R2_FB3_Pos (3U)
<> 128:9bcdf88f62b0 5862 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 5863 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 5864 #define CAN_F11R2_FB4_Pos (4U)
<> 128:9bcdf88f62b0 5865 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 5866 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 5867 #define CAN_F11R2_FB5_Pos (5U)
<> 128:9bcdf88f62b0 5868 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 5869 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 5870 #define CAN_F11R2_FB6_Pos (6U)
<> 128:9bcdf88f62b0 5871 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 5872 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 5873 #define CAN_F11R2_FB7_Pos (7U)
<> 128:9bcdf88f62b0 5874 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 5875 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 5876 #define CAN_F11R2_FB8_Pos (8U)
<> 128:9bcdf88f62b0 5877 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 5878 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 5879 #define CAN_F11R2_FB9_Pos (9U)
<> 128:9bcdf88f62b0 5880 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 5881 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 5882 #define CAN_F11R2_FB10_Pos (10U)
<> 128:9bcdf88f62b0 5883 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 5884 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 5885 #define CAN_F11R2_FB11_Pos (11U)
<> 128:9bcdf88f62b0 5886 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 5887 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 5888 #define CAN_F11R2_FB12_Pos (12U)
<> 128:9bcdf88f62b0 5889 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 5890 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 5891 #define CAN_F11R2_FB13_Pos (13U)
<> 128:9bcdf88f62b0 5892 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 5893 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 5894 #define CAN_F11R2_FB14_Pos (14U)
<> 128:9bcdf88f62b0 5895 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 5896 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 5897 #define CAN_F11R2_FB15_Pos (15U)
<> 128:9bcdf88f62b0 5898 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 5899 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 5900 #define CAN_F11R2_FB16_Pos (16U)
<> 128:9bcdf88f62b0 5901 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 5902 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 5903 #define CAN_F11R2_FB17_Pos (17U)
<> 128:9bcdf88f62b0 5904 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 5905 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 5906 #define CAN_F11R2_FB18_Pos (18U)
<> 128:9bcdf88f62b0 5907 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 5908 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 5909 #define CAN_F11R2_FB19_Pos (19U)
<> 128:9bcdf88f62b0 5910 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 5911 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 5912 #define CAN_F11R2_FB20_Pos (20U)
<> 128:9bcdf88f62b0 5913 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 5914 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 5915 #define CAN_F11R2_FB21_Pos (21U)
<> 128:9bcdf88f62b0 5916 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 5917 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 5918 #define CAN_F11R2_FB22_Pos (22U)
<> 128:9bcdf88f62b0 5919 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 5920 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 5921 #define CAN_F11R2_FB23_Pos (23U)
<> 128:9bcdf88f62b0 5922 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 5923 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 5924 #define CAN_F11R2_FB24_Pos (24U)
<> 128:9bcdf88f62b0 5925 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 5926 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 5927 #define CAN_F11R2_FB25_Pos (25U)
<> 128:9bcdf88f62b0 5928 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 5929 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 5930 #define CAN_F11R2_FB26_Pos (26U)
<> 128:9bcdf88f62b0 5931 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 5932 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 5933 #define CAN_F11R2_FB27_Pos (27U)
<> 128:9bcdf88f62b0 5934 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 5935 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 5936 #define CAN_F11R2_FB28_Pos (28U)
<> 128:9bcdf88f62b0 5937 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 5938 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 5939 #define CAN_F11R2_FB29_Pos (29U)
<> 128:9bcdf88f62b0 5940 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 5941 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 5942 #define CAN_F11R2_FB30_Pos (30U)
<> 128:9bcdf88f62b0 5943 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 5944 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 5945 #define CAN_F11R2_FB31_Pos (31U)
<> 128:9bcdf88f62b0 5946 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 5947 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 5948
<> 128:9bcdf88f62b0 5949 /******************* Bit definition for CAN_F12R2 register ******************/
<> 128:9bcdf88f62b0 5950 #define CAN_F12R2_FB0_Pos (0U)
<> 128:9bcdf88f62b0 5951 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 5952 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 5953 #define CAN_F12R2_FB1_Pos (1U)
<> 128:9bcdf88f62b0 5954 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 5955 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 5956 #define CAN_F12R2_FB2_Pos (2U)
<> 128:9bcdf88f62b0 5957 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 5958 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 5959 #define CAN_F12R2_FB3_Pos (3U)
<> 128:9bcdf88f62b0 5960 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 5961 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 5962 #define CAN_F12R2_FB4_Pos (4U)
<> 128:9bcdf88f62b0 5963 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 5964 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 5965 #define CAN_F12R2_FB5_Pos (5U)
<> 128:9bcdf88f62b0 5966 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 5967 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 5968 #define CAN_F12R2_FB6_Pos (6U)
<> 128:9bcdf88f62b0 5969 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 5970 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 5971 #define CAN_F12R2_FB7_Pos (7U)
<> 128:9bcdf88f62b0 5972 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 5973 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 5974 #define CAN_F12R2_FB8_Pos (8U)
<> 128:9bcdf88f62b0 5975 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 5976 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 5977 #define CAN_F12R2_FB9_Pos (9U)
<> 128:9bcdf88f62b0 5978 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 5979 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 5980 #define CAN_F12R2_FB10_Pos (10U)
<> 128:9bcdf88f62b0 5981 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 5982 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 5983 #define CAN_F12R2_FB11_Pos (11U)
<> 128:9bcdf88f62b0 5984 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 5985 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 5986 #define CAN_F12R2_FB12_Pos (12U)
<> 128:9bcdf88f62b0 5987 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 5988 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 5989 #define CAN_F12R2_FB13_Pos (13U)
<> 128:9bcdf88f62b0 5990 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 5991 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 5992 #define CAN_F12R2_FB14_Pos (14U)
<> 128:9bcdf88f62b0 5993 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 5994 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 5995 #define CAN_F12R2_FB15_Pos (15U)
<> 128:9bcdf88f62b0 5996 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 5997 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 5998 #define CAN_F12R2_FB16_Pos (16U)
<> 128:9bcdf88f62b0 5999 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 6000 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 6001 #define CAN_F12R2_FB17_Pos (17U)
<> 128:9bcdf88f62b0 6002 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 6003 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 6004 #define CAN_F12R2_FB18_Pos (18U)
<> 128:9bcdf88f62b0 6005 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 6006 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 6007 #define CAN_F12R2_FB19_Pos (19U)
<> 128:9bcdf88f62b0 6008 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 6009 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 6010 #define CAN_F12R2_FB20_Pos (20U)
<> 128:9bcdf88f62b0 6011 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 6012 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 6013 #define CAN_F12R2_FB21_Pos (21U)
<> 128:9bcdf88f62b0 6014 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 6015 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 6016 #define CAN_F12R2_FB22_Pos (22U)
<> 128:9bcdf88f62b0 6017 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 6018 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 6019 #define CAN_F12R2_FB23_Pos (23U)
<> 128:9bcdf88f62b0 6020 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 6021 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 6022 #define CAN_F12R2_FB24_Pos (24U)
<> 128:9bcdf88f62b0 6023 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 6024 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 6025 #define CAN_F12R2_FB25_Pos (25U)
<> 128:9bcdf88f62b0 6026 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 6027 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 6028 #define CAN_F12R2_FB26_Pos (26U)
<> 128:9bcdf88f62b0 6029 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 6030 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 6031 #define CAN_F12R2_FB27_Pos (27U)
<> 128:9bcdf88f62b0 6032 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 6033 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 6034 #define CAN_F12R2_FB28_Pos (28U)
<> 128:9bcdf88f62b0 6035 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 6036 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 6037 #define CAN_F12R2_FB29_Pos (29U)
<> 128:9bcdf88f62b0 6038 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 6039 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 6040 #define CAN_F12R2_FB30_Pos (30U)
<> 128:9bcdf88f62b0 6041 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 6042 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 6043 #define CAN_F12R2_FB31_Pos (31U)
<> 128:9bcdf88f62b0 6044 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 6045 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 6046
<> 128:9bcdf88f62b0 6047 /******************* Bit definition for CAN_F13R2 register ******************/
<> 128:9bcdf88f62b0 6048 #define CAN_F13R2_FB0_Pos (0U)
<> 128:9bcdf88f62b0 6049 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 6050 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
<> 128:9bcdf88f62b0 6051 #define CAN_F13R2_FB1_Pos (1U)
<> 128:9bcdf88f62b0 6052 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 6053 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
<> 128:9bcdf88f62b0 6054 #define CAN_F13R2_FB2_Pos (2U)
<> 128:9bcdf88f62b0 6055 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 6056 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
<> 128:9bcdf88f62b0 6057 #define CAN_F13R2_FB3_Pos (3U)
<> 128:9bcdf88f62b0 6058 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 6059 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
<> 128:9bcdf88f62b0 6060 #define CAN_F13R2_FB4_Pos (4U)
<> 128:9bcdf88f62b0 6061 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 6062 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
<> 128:9bcdf88f62b0 6063 #define CAN_F13R2_FB5_Pos (5U)
<> 128:9bcdf88f62b0 6064 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 6065 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
<> 128:9bcdf88f62b0 6066 #define CAN_F13R2_FB6_Pos (6U)
<> 128:9bcdf88f62b0 6067 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 6068 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
<> 128:9bcdf88f62b0 6069 #define CAN_F13R2_FB7_Pos (7U)
<> 128:9bcdf88f62b0 6070 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 6071 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
<> 128:9bcdf88f62b0 6072 #define CAN_F13R2_FB8_Pos (8U)
<> 128:9bcdf88f62b0 6073 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 6074 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
<> 128:9bcdf88f62b0 6075 #define CAN_F13R2_FB9_Pos (9U)
<> 128:9bcdf88f62b0 6076 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 6077 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
<> 128:9bcdf88f62b0 6078 #define CAN_F13R2_FB10_Pos (10U)
<> 128:9bcdf88f62b0 6079 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 6080 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
<> 128:9bcdf88f62b0 6081 #define CAN_F13R2_FB11_Pos (11U)
<> 128:9bcdf88f62b0 6082 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 6083 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
<> 128:9bcdf88f62b0 6084 #define CAN_F13R2_FB12_Pos (12U)
<> 128:9bcdf88f62b0 6085 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 6086 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
<> 128:9bcdf88f62b0 6087 #define CAN_F13R2_FB13_Pos (13U)
<> 128:9bcdf88f62b0 6088 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 6089 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
<> 128:9bcdf88f62b0 6090 #define CAN_F13R2_FB14_Pos (14U)
<> 128:9bcdf88f62b0 6091 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 6092 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
<> 128:9bcdf88f62b0 6093 #define CAN_F13R2_FB15_Pos (15U)
<> 128:9bcdf88f62b0 6094 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 6095 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
<> 128:9bcdf88f62b0 6096 #define CAN_F13R2_FB16_Pos (16U)
<> 128:9bcdf88f62b0 6097 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 6098 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
<> 128:9bcdf88f62b0 6099 #define CAN_F13R2_FB17_Pos (17U)
<> 128:9bcdf88f62b0 6100 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 6101 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
<> 128:9bcdf88f62b0 6102 #define CAN_F13R2_FB18_Pos (18U)
<> 128:9bcdf88f62b0 6103 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 6104 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
<> 128:9bcdf88f62b0 6105 #define CAN_F13R2_FB19_Pos (19U)
<> 128:9bcdf88f62b0 6106 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 6107 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
<> 128:9bcdf88f62b0 6108 #define CAN_F13R2_FB20_Pos (20U)
<> 128:9bcdf88f62b0 6109 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 6110 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
<> 128:9bcdf88f62b0 6111 #define CAN_F13R2_FB21_Pos (21U)
<> 128:9bcdf88f62b0 6112 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 6113 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
<> 128:9bcdf88f62b0 6114 #define CAN_F13R2_FB22_Pos (22U)
<> 128:9bcdf88f62b0 6115 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 6116 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
<> 128:9bcdf88f62b0 6117 #define CAN_F13R2_FB23_Pos (23U)
<> 128:9bcdf88f62b0 6118 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 6119 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
<> 128:9bcdf88f62b0 6120 #define CAN_F13R2_FB24_Pos (24U)
<> 128:9bcdf88f62b0 6121 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 6122 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
<> 128:9bcdf88f62b0 6123 #define CAN_F13R2_FB25_Pos (25U)
<> 128:9bcdf88f62b0 6124 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 6125 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
<> 128:9bcdf88f62b0 6126 #define CAN_F13R2_FB26_Pos (26U)
<> 128:9bcdf88f62b0 6127 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 6128 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
<> 128:9bcdf88f62b0 6129 #define CAN_F13R2_FB27_Pos (27U)
<> 128:9bcdf88f62b0 6130 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 6131 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
<> 128:9bcdf88f62b0 6132 #define CAN_F13R2_FB28_Pos (28U)
<> 128:9bcdf88f62b0 6133 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 6134 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
<> 128:9bcdf88f62b0 6135 #define CAN_F13R2_FB29_Pos (29U)
<> 128:9bcdf88f62b0 6136 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 6137 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
<> 128:9bcdf88f62b0 6138 #define CAN_F13R2_FB30_Pos (30U)
<> 128:9bcdf88f62b0 6139 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 6140 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
<> 128:9bcdf88f62b0 6141 #define CAN_F13R2_FB31_Pos (31U)
<> 128:9bcdf88f62b0 6142 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 6143 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
<> 128:9bcdf88f62b0 6144
<> 128:9bcdf88f62b0 6145 /******************************************************************************/
<> 128:9bcdf88f62b0 6146 /* */
<> 128:9bcdf88f62b0 6147 /* CRC calculation unit */
<> 128:9bcdf88f62b0 6148 /* */
<> 128:9bcdf88f62b0 6149 /******************************************************************************/
<> 128:9bcdf88f62b0 6150 /******************* Bit definition for CRC_DR register *********************/
<> 128:9bcdf88f62b0 6151 #define CRC_DR_DR_Pos (0U)
<> 128:9bcdf88f62b0 6152 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6153 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
<> 128:9bcdf88f62b0 6154
<> 128:9bcdf88f62b0 6155 /******************* Bit definition for CRC_IDR register ********************/
<> 128:9bcdf88f62b0 6156 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
<> 128:9bcdf88f62b0 6157
<> 128:9bcdf88f62b0 6158 /******************** Bit definition for CRC_CR register ********************/
<> 128:9bcdf88f62b0 6159 #define CRC_CR_RESET_Pos (0U)
<> 128:9bcdf88f62b0 6160 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 6161 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
<> 128:9bcdf88f62b0 6162 #define CRC_CR_POLYSIZE_Pos (3U)
<> 128:9bcdf88f62b0 6163 #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
<> 128:9bcdf88f62b0 6164 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
<> 128:9bcdf88f62b0 6165 #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 6166 #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 6167 #define CRC_CR_REV_IN_Pos (5U)
<> 128:9bcdf88f62b0 6168 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
<> 128:9bcdf88f62b0 6169 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
<> 128:9bcdf88f62b0 6170 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 6171 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 6172 #define CRC_CR_REV_OUT_Pos (7U)
<> 128:9bcdf88f62b0 6173 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 6174 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
<> 128:9bcdf88f62b0 6175
<> 128:9bcdf88f62b0 6176 /******************* Bit definition for CRC_INIT register *******************/
<> 128:9bcdf88f62b0 6177 #define CRC_INIT_INIT_Pos (0U)
<> 128:9bcdf88f62b0 6178 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6179 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
<> 128:9bcdf88f62b0 6180
<> 128:9bcdf88f62b0 6181 /******************* Bit definition for CRC_POL register ********************/
<> 128:9bcdf88f62b0 6182 #define CRC_POL_POL_Pos (0U)
<> 128:9bcdf88f62b0 6183 #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6184 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
<> 128:9bcdf88f62b0 6185
<> 128:9bcdf88f62b0 6186 /******************************************************************************/
<> 128:9bcdf88f62b0 6187 /* */
<> 128:9bcdf88f62b0 6188 /* Advanced Encryption Standard (AES) */
<> 128:9bcdf88f62b0 6189 /* */
<> 128:9bcdf88f62b0 6190 /******************************************************************************/
<> 128:9bcdf88f62b0 6191 /******************* Bit definition for AES_CR register *********************/
<> 128:9bcdf88f62b0 6192 #define AES_CR_EN_Pos (0U)
<> 128:9bcdf88f62b0 6193 #define AES_CR_EN_Msk (0x1U << AES_CR_EN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 6194 #define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */
<> 128:9bcdf88f62b0 6195 #define AES_CR_DATATYPE_Pos (1U)
<> 128:9bcdf88f62b0 6196 #define AES_CR_DATATYPE_Msk (0x3U << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */
<> 128:9bcdf88f62b0 6197 #define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */
<> 128:9bcdf88f62b0 6198 #define AES_CR_DATATYPE_0 (0x1U << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 6199 #define AES_CR_DATATYPE_1 (0x2U << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 6200
<> 128:9bcdf88f62b0 6201 #define AES_CR_MODE_Pos (3U)
<> 128:9bcdf88f62b0 6202 #define AES_CR_MODE_Msk (0x3U << AES_CR_MODE_Pos) /*!< 0x00000018 */
<> 128:9bcdf88f62b0 6203 #define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */
<> 128:9bcdf88f62b0 6204 #define AES_CR_MODE_0 (0x1U << AES_CR_MODE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 6205 #define AES_CR_MODE_1 (0x2U << AES_CR_MODE_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 6206
<> 128:9bcdf88f62b0 6207 #define AES_CR_CHMOD_Pos (5U)
<> 128:9bcdf88f62b0 6208 #define AES_CR_CHMOD_Msk (0x803U << AES_CR_CHMOD_Pos) /*!< 0x00010060 */
<> 128:9bcdf88f62b0 6209 #define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */
<> 128:9bcdf88f62b0 6210 #define AES_CR_CHMOD_0 (0x001U << AES_CR_CHMOD_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 6211 #define AES_CR_CHMOD_1 (0x002U << AES_CR_CHMOD_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 6212 #define AES_CR_CHMOD_2 (0x800U << AES_CR_CHMOD_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 6213
<> 128:9bcdf88f62b0 6214 #define AES_CR_CCFC_Pos (7U)
<> 128:9bcdf88f62b0 6215 #define AES_CR_CCFC_Msk (0x1U << AES_CR_CCFC_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 6216 #define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */
<> 128:9bcdf88f62b0 6217 #define AES_CR_ERRC_Pos (8U)
<> 128:9bcdf88f62b0 6218 #define AES_CR_ERRC_Msk (0x1U << AES_CR_ERRC_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 6219 #define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */
<> 128:9bcdf88f62b0 6220 #define AES_CR_CCFIE_Pos (9U)
<> 128:9bcdf88f62b0 6221 #define AES_CR_CCFIE_Msk (0x1U << AES_CR_CCFIE_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 6222 #define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */
<> 128:9bcdf88f62b0 6223 #define AES_CR_ERRIE_Pos (10U)
<> 128:9bcdf88f62b0 6224 #define AES_CR_ERRIE_Msk (0x1U << AES_CR_ERRIE_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 6225 #define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */
<> 128:9bcdf88f62b0 6226 #define AES_CR_DMAINEN_Pos (11U)
<> 128:9bcdf88f62b0 6227 #define AES_CR_DMAINEN_Msk (0x1U << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 6228 #define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */
<> 128:9bcdf88f62b0 6229 #define AES_CR_DMAOUTEN_Pos (12U)
<> 128:9bcdf88f62b0 6230 #define AES_CR_DMAOUTEN_Msk (0x1U << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 6231 #define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */
<> 128:9bcdf88f62b0 6232
<> 128:9bcdf88f62b0 6233 #define AES_CR_GCMPH_Pos (13U)
<> 128:9bcdf88f62b0 6234 #define AES_CR_GCMPH_Msk (0x3U << AES_CR_GCMPH_Pos) /*!< 0x00006000 */
<> 128:9bcdf88f62b0 6235 #define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */
<> 128:9bcdf88f62b0 6236 #define AES_CR_GCMPH_0 (0x1U << AES_CR_GCMPH_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 6237 #define AES_CR_GCMPH_1 (0x2U << AES_CR_GCMPH_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 6238
<> 128:9bcdf88f62b0 6239 #define AES_CR_KEYSIZE_Pos (18U)
<> 128:9bcdf88f62b0 6240 #define AES_CR_KEYSIZE_Msk (0x1U << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 6241 #define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */
<> 128:9bcdf88f62b0 6242
<> 128:9bcdf88f62b0 6243 /******************* Bit definition for AES_SR register *********************/
<> 128:9bcdf88f62b0 6244 #define AES_SR_CCF_Pos (0U)
<> 128:9bcdf88f62b0 6245 #define AES_SR_CCF_Msk (0x1U << AES_SR_CCF_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 6246 #define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */
<> 128:9bcdf88f62b0 6247 #define AES_SR_RDERR_Pos (1U)
<> 128:9bcdf88f62b0 6248 #define AES_SR_RDERR_Msk (0x1U << AES_SR_RDERR_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 6249 #define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */
<> 128:9bcdf88f62b0 6250 #define AES_SR_WRERR_Pos (2U)
<> 128:9bcdf88f62b0 6251 #define AES_SR_WRERR_Msk (0x1U << AES_SR_WRERR_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 6252 #define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */
<> 128:9bcdf88f62b0 6253 #define AES_SR_BUSY_Pos (3U)
<> 128:9bcdf88f62b0 6254 #define AES_SR_BUSY_Msk (0x1U << AES_SR_BUSY_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 6255 #define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */
<> 128:9bcdf88f62b0 6256
<> 128:9bcdf88f62b0 6257 /******************* Bit definition for AES_DINR register *******************/
<> 128:9bcdf88f62b0 6258 #define AES_DINR_Pos (0U)
<> 128:9bcdf88f62b0 6259 #define AES_DINR_Msk (0xFFFFFFFFU << AES_DINR_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6260 #define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */
<> 128:9bcdf88f62b0 6261
<> 128:9bcdf88f62b0 6262 /******************* Bit definition for AES_DOUTR register ******************/
<> 128:9bcdf88f62b0 6263 #define AES_DOUTR_Pos (0U)
<> 128:9bcdf88f62b0 6264 #define AES_DOUTR_Msk (0xFFFFFFFFU << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6265 #define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */
<> 128:9bcdf88f62b0 6266
<> 128:9bcdf88f62b0 6267 /******************* Bit definition for AES_KEYR0 register ******************/
<> 128:9bcdf88f62b0 6268 #define AES_KEYR0_Pos (0U)
<> 128:9bcdf88f62b0 6269 #define AES_KEYR0_Msk (0xFFFFFFFFU << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6270 #define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */
<> 128:9bcdf88f62b0 6271
<> 128:9bcdf88f62b0 6272 /******************* Bit definition for AES_KEYR1 register ******************/
<> 128:9bcdf88f62b0 6273 #define AES_KEYR1_Pos (0U)
<> 128:9bcdf88f62b0 6274 #define AES_KEYR1_Msk (0xFFFFFFFFU << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6275 #define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */
<> 128:9bcdf88f62b0 6276
<> 128:9bcdf88f62b0 6277 /******************* Bit definition for AES_KEYR2 register ******************/
<> 128:9bcdf88f62b0 6278 #define AES_KEYR2_Pos (0U)
<> 128:9bcdf88f62b0 6279 #define AES_KEYR2_Msk (0xFFFFFFFFU << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6280 #define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */
<> 128:9bcdf88f62b0 6281
<> 128:9bcdf88f62b0 6282 /******************* Bit definition for AES_KEYR3 register ******************/
<> 128:9bcdf88f62b0 6283 #define AES_KEYR3_Pos (0U)
<> 128:9bcdf88f62b0 6284 #define AES_KEYR3_Msk (0xFFFFFFFFU << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6285 #define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */
<> 128:9bcdf88f62b0 6286
<> 128:9bcdf88f62b0 6287 /******************* Bit definition for AES_KEYR4 register ******************/
<> 128:9bcdf88f62b0 6288 #define AES_KEYR4_Pos (0U)
<> 128:9bcdf88f62b0 6289 #define AES_KEYR4_Msk (0xFFFFFFFFU << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6290 #define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */
<> 128:9bcdf88f62b0 6291
<> 128:9bcdf88f62b0 6292 /******************* Bit definition for AES_KEYR5 register ******************/
<> 128:9bcdf88f62b0 6293 #define AES_KEYR5_Pos (0U)
<> 128:9bcdf88f62b0 6294 #define AES_KEYR5_Msk (0xFFFFFFFFU << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6295 #define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */
<> 128:9bcdf88f62b0 6296
<> 128:9bcdf88f62b0 6297 /******************* Bit definition for AES_KEYR6 register ******************/
<> 128:9bcdf88f62b0 6298 #define AES_KEYR6_Pos (0U)
<> 128:9bcdf88f62b0 6299 #define AES_KEYR6_Msk (0xFFFFFFFFU << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6300 #define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */
<> 128:9bcdf88f62b0 6301
<> 128:9bcdf88f62b0 6302 /******************* Bit definition for AES_KEYR7 register ******************/
<> 128:9bcdf88f62b0 6303 #define AES_KEYR7_Pos (0U)
<> 128:9bcdf88f62b0 6304 #define AES_KEYR7_Msk (0xFFFFFFFFU << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6305 #define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */
<> 128:9bcdf88f62b0 6306
<> 128:9bcdf88f62b0 6307 /******************* Bit definition for AES_IVR0 register ******************/
<> 128:9bcdf88f62b0 6308 #define AES_IVR0_Pos (0U)
<> 128:9bcdf88f62b0 6309 #define AES_IVR0_Msk (0xFFFFFFFFU << AES_IVR0_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6310 #define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */
<> 128:9bcdf88f62b0 6311
<> 128:9bcdf88f62b0 6312 /******************* Bit definition for AES_IVR1 register ******************/
<> 128:9bcdf88f62b0 6313 #define AES_IVR1_Pos (0U)
<> 128:9bcdf88f62b0 6314 #define AES_IVR1_Msk (0xFFFFFFFFU << AES_IVR1_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6315 #define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */
<> 128:9bcdf88f62b0 6316
<> 128:9bcdf88f62b0 6317 /******************* Bit definition for AES_IVR2 register ******************/
<> 128:9bcdf88f62b0 6318 #define AES_IVR2_Pos (0U)
<> 128:9bcdf88f62b0 6319 #define AES_IVR2_Msk (0xFFFFFFFFU << AES_IVR2_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6320 #define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */
<> 128:9bcdf88f62b0 6321
<> 128:9bcdf88f62b0 6322 /******************* Bit definition for AES_IVR3 register ******************/
<> 128:9bcdf88f62b0 6323 #define AES_IVR3_Pos (0U)
<> 128:9bcdf88f62b0 6324 #define AES_IVR3_Msk (0xFFFFFFFFU << AES_IVR3_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6325 #define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */
<> 128:9bcdf88f62b0 6326
<> 128:9bcdf88f62b0 6327 /******************* Bit definition for AES_SUSP0R register ******************/
<> 128:9bcdf88f62b0 6328 #define AES_SUSP0R_Pos (0U)
<> 128:9bcdf88f62b0 6329 #define AES_SUSP0R_Msk (0xFFFFFFFFU << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6330 #define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */
<> 128:9bcdf88f62b0 6331
<> 128:9bcdf88f62b0 6332 /******************* Bit definition for AES_SUSP1R register ******************/
<> 128:9bcdf88f62b0 6333 #define AES_SUSP1R_Pos (0U)
<> 128:9bcdf88f62b0 6334 #define AES_SUSP1R_Msk (0xFFFFFFFFU << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6335 #define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */
<> 128:9bcdf88f62b0 6336
<> 128:9bcdf88f62b0 6337 /******************* Bit definition for AES_SUSP2R register ******************/
<> 128:9bcdf88f62b0 6338 #define AES_SUSP2R_Pos (0U)
<> 128:9bcdf88f62b0 6339 #define AES_SUSP2R_Msk (0xFFFFFFFFU << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6340 #define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */
<> 128:9bcdf88f62b0 6341
<> 128:9bcdf88f62b0 6342 /******************* Bit definition for AES_SUSP3R register ******************/
<> 128:9bcdf88f62b0 6343 #define AES_SUSP3R_Pos (0U)
<> 128:9bcdf88f62b0 6344 #define AES_SUSP3R_Msk (0xFFFFFFFFU << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6345 #define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */
<> 128:9bcdf88f62b0 6346
<> 128:9bcdf88f62b0 6347 /******************* Bit definition for AES_SUSP4R register ******************/
<> 128:9bcdf88f62b0 6348 #define AES_SUSP4R_Pos (0U)
<> 128:9bcdf88f62b0 6349 #define AES_SUSP4R_Msk (0xFFFFFFFFU << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6350 #define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */
<> 128:9bcdf88f62b0 6351
<> 128:9bcdf88f62b0 6352 /******************* Bit definition for AES_SUSP5R register ******************/
<> 128:9bcdf88f62b0 6353 #define AES_SUSP5R_Pos (0U)
<> 128:9bcdf88f62b0 6354 #define AES_SUSP5R_Msk (0xFFFFFFFFU << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6355 #define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */
<> 128:9bcdf88f62b0 6356
<> 128:9bcdf88f62b0 6357 /******************* Bit definition for AES_SUSP6R register ******************/
<> 128:9bcdf88f62b0 6358 #define AES_SUSP6R_Pos (0U)
<> 128:9bcdf88f62b0 6359 #define AES_SUSP6R_Msk (0xFFFFFFFFU << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6360 #define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */
<> 128:9bcdf88f62b0 6361
<> 128:9bcdf88f62b0 6362 /******************* Bit definition for AES_SUSP7R register ******************/
<> 128:9bcdf88f62b0 6363 #define AES_SUSP7R_Pos (0U)
<> 128:9bcdf88f62b0 6364 #define AES_SUSP7R_Msk (0xFFFFFFFFU << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 6365 #define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */
<> 128:9bcdf88f62b0 6366
<> 128:9bcdf88f62b0 6367 /******************************************************************************/
<> 128:9bcdf88f62b0 6368 /* */
<> 128:9bcdf88f62b0 6369 /* Digital to Analog Converter */
<> 128:9bcdf88f62b0 6370 /* */
<> 128:9bcdf88f62b0 6371 /******************************************************************************/
<> 128:9bcdf88f62b0 6372 /******************** Bit definition for DAC_CR register ********************/
<> 128:9bcdf88f62b0 6373 #define DAC_CR_EN1_Pos (0U)
<> 128:9bcdf88f62b0 6374 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 6375 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
<> 128:9bcdf88f62b0 6376 #define DAC_CR_TEN1_Pos (2U)
<> 128:9bcdf88f62b0 6377 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 6378 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
<> 128:9bcdf88f62b0 6379
<> 128:9bcdf88f62b0 6380 #define DAC_CR_TSEL1_Pos (3U)
<> 128:9bcdf88f62b0 6381 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
<> 128:9bcdf88f62b0 6382 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
<> 128:9bcdf88f62b0 6383 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 6384 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 6385 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 6386
<> 128:9bcdf88f62b0 6387 #define DAC_CR_WAVE1_Pos (6U)
<> 128:9bcdf88f62b0 6388 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
<> 128:9bcdf88f62b0 6389 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
<> 128:9bcdf88f62b0 6390 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 6391 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 6392
<> 128:9bcdf88f62b0 6393 #define DAC_CR_MAMP1_Pos (8U)
<> 128:9bcdf88f62b0 6394 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
<> 128:9bcdf88f62b0 6395 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
<> 128:9bcdf88f62b0 6396 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 6397 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 6398 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 6399 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 6400
<> 128:9bcdf88f62b0 6401 #define DAC_CR_DMAEN1_Pos (12U)
<> 128:9bcdf88f62b0 6402 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 6403 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
<> 128:9bcdf88f62b0 6404 #define DAC_CR_DMAUDRIE1_Pos (13U)
<> 128:9bcdf88f62b0 6405 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 6406 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
<> 128:9bcdf88f62b0 6407 #define DAC_CR_CEN1_Pos (14U)
<> 128:9bcdf88f62b0 6408 #define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 6409 #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
<> 128:9bcdf88f62b0 6410
<> 128:9bcdf88f62b0 6411 #define DAC_CR_EN2_Pos (16U)
<> 128:9bcdf88f62b0 6412 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 6413 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
<> 128:9bcdf88f62b0 6414 #define DAC_CR_TEN2_Pos (18U)
<> 128:9bcdf88f62b0 6415 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 6416 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
<> 128:9bcdf88f62b0 6417
<> 128:9bcdf88f62b0 6418 #define DAC_CR_TSEL2_Pos (19U)
<> 128:9bcdf88f62b0 6419 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
<> 128:9bcdf88f62b0 6420 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
<> 128:9bcdf88f62b0 6421 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 6422 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 6423 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 6424
<> 128:9bcdf88f62b0 6425 #define DAC_CR_WAVE2_Pos (22U)
<> 128:9bcdf88f62b0 6426 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
<> 128:9bcdf88f62b0 6427 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
<> 128:9bcdf88f62b0 6428 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 6429 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 6430
<> 128:9bcdf88f62b0 6431 #define DAC_CR_MAMP2_Pos (24U)
<> 128:9bcdf88f62b0 6432 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
<> 128:9bcdf88f62b0 6433 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
<> 128:9bcdf88f62b0 6434 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 6435 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 6436 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 6437 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 6438
<> 128:9bcdf88f62b0 6439 #define DAC_CR_DMAEN2_Pos (28U)
<> 128:9bcdf88f62b0 6440 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 6441 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
<> 128:9bcdf88f62b0 6442 #define DAC_CR_DMAUDRIE2_Pos (29U)
<> 128:9bcdf88f62b0 6443 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 6444 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
<> 128:9bcdf88f62b0 6445 #define DAC_CR_CEN2_Pos (30U)
<> 128:9bcdf88f62b0 6446 #define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 6447 #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
<> 128:9bcdf88f62b0 6448
<> 128:9bcdf88f62b0 6449 /***************** Bit definition for DAC_SWTRIGR register ******************/
<> 128:9bcdf88f62b0 6450 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
<> 128:9bcdf88f62b0 6451 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 6452 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
<> 128:9bcdf88f62b0 6453 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
<> 128:9bcdf88f62b0 6454 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 6455 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
<> 128:9bcdf88f62b0 6456
<> 128:9bcdf88f62b0 6457 /***************** Bit definition for DAC_DHR12R1 register ******************/
<> 128:9bcdf88f62b0 6458 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
<> 128:9bcdf88f62b0 6459 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
<> 128:9bcdf88f62b0 6460 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
<> 128:9bcdf88f62b0 6461
<> 128:9bcdf88f62b0 6462 /***************** Bit definition for DAC_DHR12L1 register ******************/
<> 128:9bcdf88f62b0 6463 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
<> 128:9bcdf88f62b0 6464 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
<> 128:9bcdf88f62b0 6465 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
<> 128:9bcdf88f62b0 6466
<> 128:9bcdf88f62b0 6467 /****************** Bit definition for DAC_DHR8R1 register ******************/
<> 128:9bcdf88f62b0 6468 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
<> 128:9bcdf88f62b0 6469 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 6470 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
<> 128:9bcdf88f62b0 6471
<> 128:9bcdf88f62b0 6472 /***************** Bit definition for DAC_DHR12R2 register ******************/
<> 128:9bcdf88f62b0 6473 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
<> 128:9bcdf88f62b0 6474 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
<> 128:9bcdf88f62b0 6475 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
<> 128:9bcdf88f62b0 6476
<> 128:9bcdf88f62b0 6477 /***************** Bit definition for DAC_DHR12L2 register ******************/
<> 128:9bcdf88f62b0 6478 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
<> 128:9bcdf88f62b0 6479 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
<> 128:9bcdf88f62b0 6480 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
<> 128:9bcdf88f62b0 6481
<> 128:9bcdf88f62b0 6482 /****************** Bit definition for DAC_DHR8R2 register ******************/
<> 128:9bcdf88f62b0 6483 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
<> 128:9bcdf88f62b0 6484 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 6485 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
<> 128:9bcdf88f62b0 6486
<> 128:9bcdf88f62b0 6487 /***************** Bit definition for DAC_DHR12RD register ******************/
<> 128:9bcdf88f62b0 6488 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
<> 128:9bcdf88f62b0 6489 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
<> 128:9bcdf88f62b0 6490 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
<> 128:9bcdf88f62b0 6491 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
<> 128:9bcdf88f62b0 6492 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
<> 128:9bcdf88f62b0 6493 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
<> 128:9bcdf88f62b0 6494
<> 128:9bcdf88f62b0 6495 /***************** Bit definition for DAC_DHR12LD register ******************/
<> 128:9bcdf88f62b0 6496 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
<> 128:9bcdf88f62b0 6497 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
<> 128:9bcdf88f62b0 6498 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
<> 128:9bcdf88f62b0 6499 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
<> 128:9bcdf88f62b0 6500 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
<> 128:9bcdf88f62b0 6501 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
<> 128:9bcdf88f62b0 6502
<> 128:9bcdf88f62b0 6503 /****************** Bit definition for DAC_DHR8RD register ******************/
<> 128:9bcdf88f62b0 6504 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
<> 128:9bcdf88f62b0 6505 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 6506 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
<> 128:9bcdf88f62b0 6507 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
<> 128:9bcdf88f62b0 6508 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 6509 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
<> 128:9bcdf88f62b0 6510
<> 128:9bcdf88f62b0 6511 /******************* Bit definition for DAC_DOR1 register *******************/
<> 128:9bcdf88f62b0 6512 #define DAC_DOR1_DACC1DOR_Pos (0U)
<> 128:9bcdf88f62b0 6513 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
<> 128:9bcdf88f62b0 6514 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
<> 128:9bcdf88f62b0 6515
<> 128:9bcdf88f62b0 6516 /******************* Bit definition for DAC_DOR2 register *******************/
<> 128:9bcdf88f62b0 6517 #define DAC_DOR2_DACC2DOR_Pos (0U)
<> 128:9bcdf88f62b0 6518 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
<> 128:9bcdf88f62b0 6519 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
<> 128:9bcdf88f62b0 6520
<> 128:9bcdf88f62b0 6521 /******************** Bit definition for DAC_SR register ********************/
<> 128:9bcdf88f62b0 6522 #define DAC_SR_DMAUDR1_Pos (13U)
<> 128:9bcdf88f62b0 6523 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 6524 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
<> 128:9bcdf88f62b0 6525 #define DAC_SR_CAL_FLAG1_Pos (14U)
<> 128:9bcdf88f62b0 6526 #define DAC_SR_CAL_FLAG1_Msk (0x1U << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 6527 #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
<> 128:9bcdf88f62b0 6528 #define DAC_SR_BWST1_Pos (15U)
<> 128:9bcdf88f62b0 6529 #define DAC_SR_BWST1_Msk (0x4001U << DAC_SR_BWST1_Pos) /*!< 0x20008000 */
<> 128:9bcdf88f62b0 6530 #define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
<> 128:9bcdf88f62b0 6531
<> 128:9bcdf88f62b0 6532 #define DAC_SR_DMAUDR2_Pos (29U)
<> 128:9bcdf88f62b0 6533 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 6534 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
<> 128:9bcdf88f62b0 6535 #define DAC_SR_CAL_FLAG2_Pos (30U)
<> 128:9bcdf88f62b0 6536 #define DAC_SR_CAL_FLAG2_Msk (0x1U << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 6537 #define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
<> 128:9bcdf88f62b0 6538 #define DAC_SR_BWST2_Pos (31U)
<> 128:9bcdf88f62b0 6539 #define DAC_SR_BWST2_Msk (0x1U << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 6540 #define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
<> 128:9bcdf88f62b0 6541
<> 128:9bcdf88f62b0 6542 /******************* Bit definition for DAC_CCR register ********************/
<> 128:9bcdf88f62b0 6543 #define DAC_CCR_OTRIM1_Pos (0U)
<> 128:9bcdf88f62b0 6544 #define DAC_CCR_OTRIM1_Msk (0x1FU << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
<> 128:9bcdf88f62b0 6545 #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
<> 128:9bcdf88f62b0 6546 #define DAC_CCR_OTRIM2_Pos (16U)
<> 128:9bcdf88f62b0 6547 #define DAC_CCR_OTRIM2_Msk (0x1FU << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
<> 128:9bcdf88f62b0 6548 #define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
<> 128:9bcdf88f62b0 6549
<> 128:9bcdf88f62b0 6550 /******************* Bit definition for DAC_MCR register *******************/
<> 128:9bcdf88f62b0 6551 #define DAC_MCR_MODE1_Pos (0U)
<> 128:9bcdf88f62b0 6552 #define DAC_MCR_MODE1_Msk (0x7U << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
<> 128:9bcdf88f62b0 6553 #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
<> 128:9bcdf88f62b0 6554 #define DAC_MCR_MODE1_0 (0x1U << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 6555 #define DAC_MCR_MODE1_1 (0x2U << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 6556 #define DAC_MCR_MODE1_2 (0x4U << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 6557
<> 128:9bcdf88f62b0 6558 #define DAC_MCR_MODE2_Pos (16U)
<> 128:9bcdf88f62b0 6559 #define DAC_MCR_MODE2_Msk (0x7U << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
<> 128:9bcdf88f62b0 6560 #define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
<> 128:9bcdf88f62b0 6561 #define DAC_MCR_MODE2_0 (0x1U << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 6562 #define DAC_MCR_MODE2_1 (0x2U << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 6563 #define DAC_MCR_MODE2_2 (0x4U << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 6564
<> 128:9bcdf88f62b0 6565 /****************** Bit definition for DAC_SHSR1 register ******************/
<> 128:9bcdf88f62b0 6566 #define DAC_SHSR1_TSAMPLE1_Pos (0U)
<> 128:9bcdf88f62b0 6567 #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
<> 128:9bcdf88f62b0 6568 #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
<> 128:9bcdf88f62b0 6569
<> 128:9bcdf88f62b0 6570 /****************** Bit definition for DAC_SHSR2 register ******************/
<> 128:9bcdf88f62b0 6571 #define DAC_SHSR2_TSAMPLE2_Pos (0U)
<> 128:9bcdf88f62b0 6572 #define DAC_SHSR2_TSAMPLE2_Msk (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
<> 128:9bcdf88f62b0 6573 #define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
<> 128:9bcdf88f62b0 6574
<> 128:9bcdf88f62b0 6575 /****************** Bit definition for DAC_SHHR register ******************/
<> 128:9bcdf88f62b0 6576 #define DAC_SHHR_THOLD1_Pos (0U)
<> 128:9bcdf88f62b0 6577 #define DAC_SHHR_THOLD1_Msk (0x3FFU << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
<> 128:9bcdf88f62b0 6578 #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
<> 128:9bcdf88f62b0 6579 #define DAC_SHHR_THOLD2_Pos (16U)
<> 128:9bcdf88f62b0 6580 #define DAC_SHHR_THOLD2_Msk (0x3FFU << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
<> 128:9bcdf88f62b0 6581 #define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
<> 128:9bcdf88f62b0 6582
<> 128:9bcdf88f62b0 6583 /****************** Bit definition for DAC_SHRR register ******************/
<> 128:9bcdf88f62b0 6584 #define DAC_SHRR_TREFRESH1_Pos (0U)
<> 128:9bcdf88f62b0 6585 #define DAC_SHRR_TREFRESH1_Msk (0xFFU << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 6586 #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
<> 128:9bcdf88f62b0 6587 #define DAC_SHRR_TREFRESH2_Pos (16U)
<> 128:9bcdf88f62b0 6588 #define DAC_SHRR_TREFRESH2_Msk (0xFFU << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 6589 #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
<> 128:9bcdf88f62b0 6590
<> 128:9bcdf88f62b0 6591 /******************************************************************************/
<> 128:9bcdf88f62b0 6592 /* */
<> 128:9bcdf88f62b0 6593 /* Digital Filter for Sigma Delta Modulators */
<> 128:9bcdf88f62b0 6594 /* */
<> 128:9bcdf88f62b0 6595 /******************************************************************************/
<> 128:9bcdf88f62b0 6596
<> 128:9bcdf88f62b0 6597 /**************** DFSDM channel configuration registers ********************/
<> 128:9bcdf88f62b0 6598
<> 128:9bcdf88f62b0 6599 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
<> 128:9bcdf88f62b0 6600 #define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
<> 128:9bcdf88f62b0 6601 #define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 6602 #define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
<> 128:9bcdf88f62b0 6603 #define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
<> 128:9bcdf88f62b0 6604 #define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 6605 #define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
<> 128:9bcdf88f62b0 6606 #define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
<> 128:9bcdf88f62b0 6607 #define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 6608 #define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
<> 128:9bcdf88f62b0 6609 #define DFSDM_CHCFGR1_DATPACK_Pos (14U)
<> 128:9bcdf88f62b0 6610 #define DFSDM_CHCFGR1_DATPACK_Msk (0x3U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
<> 128:9bcdf88f62b0 6611 #define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
<> 128:9bcdf88f62b0 6612 #define DFSDM_CHCFGR1_DATPACK_1 (0x2U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 6613 #define DFSDM_CHCFGR1_DATPACK_0 (0x1U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 6614 #define DFSDM_CHCFGR1_DATMPX_Pos (12U)
<> 128:9bcdf88f62b0 6615 #define DFSDM_CHCFGR1_DATMPX_Msk (0x3U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
<> 128:9bcdf88f62b0 6616 #define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
<> 128:9bcdf88f62b0 6617 #define DFSDM_CHCFGR1_DATMPX_1 (0x2U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 6618 #define DFSDM_CHCFGR1_DATMPX_0 (0x1U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 6619 #define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
<> 128:9bcdf88f62b0 6620 #define DFSDM_CHCFGR1_CHINSEL_Msk (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 6621 #define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
<> 128:9bcdf88f62b0 6622 #define DFSDM_CHCFGR1_CHEN_Pos (7U)
<> 128:9bcdf88f62b0 6623 #define DFSDM_CHCFGR1_CHEN_Msk (0x1U << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 6624 #define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
<> 128:9bcdf88f62b0 6625 #define DFSDM_CHCFGR1_CKABEN_Pos (6U)
<> 128:9bcdf88f62b0 6626 #define DFSDM_CHCFGR1_CKABEN_Msk (0x1U << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 6627 #define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
<> 128:9bcdf88f62b0 6628 #define DFSDM_CHCFGR1_SCDEN_Pos (5U)
<> 128:9bcdf88f62b0 6629 #define DFSDM_CHCFGR1_SCDEN_Msk (0x1U << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 6630 #define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
<> 128:9bcdf88f62b0 6631 #define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
<> 128:9bcdf88f62b0 6632 #define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
<> 128:9bcdf88f62b0 6633 #define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
<> 128:9bcdf88f62b0 6634 #define DFSDM_CHCFGR1_SPICKSEL_1 (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 6635 #define DFSDM_CHCFGR1_SPICKSEL_0 (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 6636 #define DFSDM_CHCFGR1_SITP_Pos (0U)
<> 128:9bcdf88f62b0 6637 #define DFSDM_CHCFGR1_SITP_Msk (0x3U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 6638 #define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
<> 128:9bcdf88f62b0 6639 #define DFSDM_CHCFGR1_SITP_1 (0x2U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 6640 #define DFSDM_CHCFGR1_SITP_0 (0x1U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 6641
<> 128:9bcdf88f62b0 6642 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
<> 128:9bcdf88f62b0 6643 #define DFSDM_CHCFGR2_OFFSET_Pos (8U)
<> 128:9bcdf88f62b0 6644 #define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
<> 128:9bcdf88f62b0 6645 #define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
<> 128:9bcdf88f62b0 6646 #define DFSDM_CHCFGR2_DTRBS_Pos (3U)
<> 128:9bcdf88f62b0 6647 #define DFSDM_CHCFGR2_DTRBS_Msk (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
<> 128:9bcdf88f62b0 6648 #define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
<> 128:9bcdf88f62b0 6649
<> 128:9bcdf88f62b0 6650 /**************** Bit definition for DFSDM_CHAWSCDR register *****************/
<> 128:9bcdf88f62b0 6651 #define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
<> 128:9bcdf88f62b0 6652 #define DFSDM_CHAWSCDR_AWFORD_Msk (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
<> 128:9bcdf88f62b0 6653 #define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
<> 128:9bcdf88f62b0 6654 #define DFSDM_CHAWSCDR_AWFORD_1 (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 6655 #define DFSDM_CHAWSCDR_AWFORD_0 (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 6656 #define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
<> 128:9bcdf88f62b0 6657 #define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
<> 128:9bcdf88f62b0 6658 #define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
<> 128:9bcdf88f62b0 6659 #define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
<> 128:9bcdf88f62b0 6660 #define DFSDM_CHAWSCDR_BKSCD_Msk (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
<> 128:9bcdf88f62b0 6661 #define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
<> 128:9bcdf88f62b0 6662 #define DFSDM_CHAWSCDR_SCDT_Pos (0U)
<> 128:9bcdf88f62b0 6663 #define DFSDM_CHAWSCDR_SCDT_Msk (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 6664 #define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
<> 128:9bcdf88f62b0 6665
<> 128:9bcdf88f62b0 6666 /**************** Bit definition for DFSDM_CHWDATR register *******************/
<> 128:9bcdf88f62b0 6667 #define DFSDM_CHWDATR_WDATA_Pos (0U)
<> 128:9bcdf88f62b0 6668 #define DFSDM_CHWDATR_WDATA_Msk (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 6669 #define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
<> 128:9bcdf88f62b0 6670
<> 128:9bcdf88f62b0 6671 /**************** Bit definition for DFSDM_CHDATINR register *****************/
<> 128:9bcdf88f62b0 6672 #define DFSDM_CHDATINR_INDAT0_Pos (0U)
<> 128:9bcdf88f62b0 6673 #define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 6674 #define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
<> 128:9bcdf88f62b0 6675 #define DFSDM_CHDATINR_INDAT1_Pos (16U)
<> 128:9bcdf88f62b0 6676 #define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
<> 128:9bcdf88f62b0 6677 #define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
<> 128:9bcdf88f62b0 6678
<> 128:9bcdf88f62b0 6679 /************************ DFSDM module registers ****************************/
<> 128:9bcdf88f62b0 6680
<> 128:9bcdf88f62b0 6681 /***************** Bit definition for DFSDM_FLTCR1 register *******************/
<> 128:9bcdf88f62b0 6682 #define DFSDM_FLTCR1_AWFSEL_Pos (30U)
<> 128:9bcdf88f62b0 6683 #define DFSDM_FLTCR1_AWFSEL_Msk (0x1U << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 6684 #define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
<> 128:9bcdf88f62b0 6685 #define DFSDM_FLTCR1_FAST_Pos (29U)
<> 128:9bcdf88f62b0 6686 #define DFSDM_FLTCR1_FAST_Msk (0x1U << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 6687 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
<> 128:9bcdf88f62b0 6688 #define DFSDM_FLTCR1_RCH_Pos (24U)
<> 128:9bcdf88f62b0 6689 #define DFSDM_FLTCR1_RCH_Msk (0x7U << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
<> 128:9bcdf88f62b0 6690 #define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
<> 128:9bcdf88f62b0 6691 #define DFSDM_FLTCR1_RDMAEN_Pos (21U)
<> 128:9bcdf88f62b0 6692 #define DFSDM_FLTCR1_RDMAEN_Msk (0x1U << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 6693 #define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
<> 128:9bcdf88f62b0 6694 #define DFSDM_FLTCR1_RSYNC_Pos (19U)
<> 128:9bcdf88f62b0 6695 #define DFSDM_FLTCR1_RSYNC_Msk (0x1U << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 6696 #define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
<> 128:9bcdf88f62b0 6697 #define DFSDM_FLTCR1_RCONT_Pos (18U)
<> 128:9bcdf88f62b0 6698 #define DFSDM_FLTCR1_RCONT_Msk (0x1U << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 6699 #define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
<> 128:9bcdf88f62b0 6700 #define DFSDM_FLTCR1_RSWSTART_Pos (17U)
<> 128:9bcdf88f62b0 6701 #define DFSDM_FLTCR1_RSWSTART_Msk (0x1U << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 6702 #define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
<> 128:9bcdf88f62b0 6703 #define DFSDM_FLTCR1_JEXTEN_Pos (13U)
<> 128:9bcdf88f62b0 6704 #define DFSDM_FLTCR1_JEXTEN_Msk (0x3U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
<> 128:9bcdf88f62b0 6705 #define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
<> 128:9bcdf88f62b0 6706 #define DFSDM_FLTCR1_JEXTEN_1 (0x2U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 6707 #define DFSDM_FLTCR1_JEXTEN_0 (0x1U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 6708 #define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
<> 128:9bcdf88f62b0 6709 #define DFSDM_FLTCR1_JEXTSEL_Msk (0x7U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000700 */
<> 128:9bcdf88f62b0 6710 #define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
<> 128:9bcdf88f62b0 6711 #define DFSDM_FLTCR1_JEXTSEL_2 (0x4U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 6712 #define DFSDM_FLTCR1_JEXTSEL_1 (0x2U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 6713 #define DFSDM_FLTCR1_JEXTSEL_0 (0x1U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 6714 #define DFSDM_FLTCR1_JDMAEN_Pos (5U)
<> 128:9bcdf88f62b0 6715 #define DFSDM_FLTCR1_JDMAEN_Msk (0x1U << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 6716 #define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
<> 128:9bcdf88f62b0 6717 #define DFSDM_FLTCR1_JSCAN_Pos (4U)
<> 128:9bcdf88f62b0 6718 #define DFSDM_FLTCR1_JSCAN_Msk (0x1U << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 6719 #define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
<> 128:9bcdf88f62b0 6720 #define DFSDM_FLTCR1_JSYNC_Pos (3U)
<> 128:9bcdf88f62b0 6721 #define DFSDM_FLTCR1_JSYNC_Msk (0x1U << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 6722 #define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
<> 128:9bcdf88f62b0 6723 #define DFSDM_FLTCR1_JSWSTART_Pos (1U)
<> 128:9bcdf88f62b0 6724 #define DFSDM_FLTCR1_JSWSTART_Msk (0x1U << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 6725 #define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
<> 128:9bcdf88f62b0 6726 #define DFSDM_FLTCR1_DFEN_Pos (0U)
<> 128:9bcdf88f62b0 6727 #define DFSDM_FLTCR1_DFEN_Msk (0x1U << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 6728 #define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
<> 128:9bcdf88f62b0 6729
<> 128:9bcdf88f62b0 6730 /***************** Bit definition for DFSDM_FLTCR2 register *******************/
<> 128:9bcdf88f62b0 6731 #define DFSDM_FLTCR2_AWDCH_Pos (16U)
<> 128:9bcdf88f62b0 6732 #define DFSDM_FLTCR2_AWDCH_Msk (0xFFU << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 6733 #define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
<> 128:9bcdf88f62b0 6734 #define DFSDM_FLTCR2_EXCH_Pos (8U)
<> 128:9bcdf88f62b0 6735 #define DFSDM_FLTCR2_EXCH_Msk (0xFFU << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 6736 #define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
<> 128:9bcdf88f62b0 6737 #define DFSDM_FLTCR2_CKABIE_Pos (6U)
<> 128:9bcdf88f62b0 6738 #define DFSDM_FLTCR2_CKABIE_Msk (0x1U << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 6739 #define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
<> 128:9bcdf88f62b0 6740 #define DFSDM_FLTCR2_SCDIE_Pos (5U)
<> 128:9bcdf88f62b0 6741 #define DFSDM_FLTCR2_SCDIE_Msk (0x1U << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 6742 #define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
<> 128:9bcdf88f62b0 6743 #define DFSDM_FLTCR2_AWDIE_Pos (4U)
<> 128:9bcdf88f62b0 6744 #define DFSDM_FLTCR2_AWDIE_Msk (0x1U << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 6745 #define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
<> 128:9bcdf88f62b0 6746 #define DFSDM_FLTCR2_ROVRIE_Pos (3U)
<> 128:9bcdf88f62b0 6747 #define DFSDM_FLTCR2_ROVRIE_Msk (0x1U << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 6748 #define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
<> 128:9bcdf88f62b0 6749 #define DFSDM_FLTCR2_JOVRIE_Pos (2U)
<> 128:9bcdf88f62b0 6750 #define DFSDM_FLTCR2_JOVRIE_Msk (0x1U << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 6751 #define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
<> 128:9bcdf88f62b0 6752 #define DFSDM_FLTCR2_REOCIE_Pos (1U)
<> 128:9bcdf88f62b0 6753 #define DFSDM_FLTCR2_REOCIE_Msk (0x1U << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 6754 #define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
<> 128:9bcdf88f62b0 6755 #define DFSDM_FLTCR2_JEOCIE_Pos (0U)
<> 128:9bcdf88f62b0 6756 #define DFSDM_FLTCR2_JEOCIE_Msk (0x1U << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 6757 #define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
<> 128:9bcdf88f62b0 6758
<> 128:9bcdf88f62b0 6759 /***************** Bit definition for DFSDM_FLTISR register *******************/
<> 128:9bcdf88f62b0 6760 #define DFSDM_FLTISR_SCDF_Pos (24U)
<> 128:9bcdf88f62b0 6761 #define DFSDM_FLTISR_SCDF_Msk (0xFFU << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
<> 128:9bcdf88f62b0 6762 #define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
<> 128:9bcdf88f62b0 6763 #define DFSDM_FLTISR_CKABF_Pos (16U)
<> 128:9bcdf88f62b0 6764 #define DFSDM_FLTISR_CKABF_Msk (0xFFU << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 6765 #define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
<> 128:9bcdf88f62b0 6766 #define DFSDM_FLTISR_RCIP_Pos (14U)
<> 128:9bcdf88f62b0 6767 #define DFSDM_FLTISR_RCIP_Msk (0x1U << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 6768 #define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
<> 128:9bcdf88f62b0 6769 #define DFSDM_FLTISR_JCIP_Pos (13U)
<> 128:9bcdf88f62b0 6770 #define DFSDM_FLTISR_JCIP_Msk (0x1U << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 6771 #define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
<> 128:9bcdf88f62b0 6772 #define DFSDM_FLTISR_AWDF_Pos (4U)
<> 128:9bcdf88f62b0 6773 #define DFSDM_FLTISR_AWDF_Msk (0x1U << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 6774 #define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
<> 128:9bcdf88f62b0 6775 #define DFSDM_FLTISR_ROVRF_Pos (3U)
<> 128:9bcdf88f62b0 6776 #define DFSDM_FLTISR_ROVRF_Msk (0x1U << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 6777 #define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
<> 128:9bcdf88f62b0 6778 #define DFSDM_FLTISR_JOVRF_Pos (2U)
<> 128:9bcdf88f62b0 6779 #define DFSDM_FLTISR_JOVRF_Msk (0x1U << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 6780 #define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
<> 128:9bcdf88f62b0 6781 #define DFSDM_FLTISR_REOCF_Pos (1U)
<> 128:9bcdf88f62b0 6782 #define DFSDM_FLTISR_REOCF_Msk (0x1U << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 6783 #define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
<> 128:9bcdf88f62b0 6784 #define DFSDM_FLTISR_JEOCF_Pos (0U)
<> 128:9bcdf88f62b0 6785 #define DFSDM_FLTISR_JEOCF_Msk (0x1U << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 6786 #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
<> 128:9bcdf88f62b0 6787
<> 128:9bcdf88f62b0 6788 /***************** Bit definition for DFSDM_FLTICR register *******************/
<> 128:9bcdf88f62b0 6789 #define DFSDM_FLTICR_CLRSCSDF_Pos (24U)
<> 128:9bcdf88f62b0 6790 #define DFSDM_FLTICR_CLRSCSDF_Msk (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos) /*!< 0xFF000000 */
<> 128:9bcdf88f62b0 6791 #define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCSDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
<> 128:9bcdf88f62b0 6792 #define DFSDM_FLTICR_CLRCKABF_Pos (16U)
<> 128:9bcdf88f62b0 6793 #define DFSDM_FLTICR_CLRCKABF_Msk (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 6794 #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
<> 128:9bcdf88f62b0 6795 #define DFSDM_FLTICR_CLRROVRF_Pos (3U)
<> 128:9bcdf88f62b0 6796 #define DFSDM_FLTICR_CLRROVRF_Msk (0x1U << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 6797 #define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
<> 128:9bcdf88f62b0 6798 #define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
<> 128:9bcdf88f62b0 6799 #define DFSDM_FLTICR_CLRJOVRF_Msk (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 6800 #define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
<> 128:9bcdf88f62b0 6801
<> 128:9bcdf88f62b0 6802 /**************** Bit definition for DFSDM_FLTJCHGR register ******************/
<> 128:9bcdf88f62b0 6803 #define DFSDM_FLTJCHGR_JCHG_Pos (0U)
<> 128:9bcdf88f62b0 6804 #define DFSDM_FLTJCHGR_JCHG_Msk (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 6805 #define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
<> 128:9bcdf88f62b0 6806
<> 128:9bcdf88f62b0 6807 /***************** Bit definition for DFSDM_FLTFCR register *******************/
<> 128:9bcdf88f62b0 6808 #define DFSDM_FLTFCR_FORD_Pos (29U)
<> 128:9bcdf88f62b0 6809 #define DFSDM_FLTFCR_FORD_Msk (0x7U << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
<> 128:9bcdf88f62b0 6810 #define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
<> 128:9bcdf88f62b0 6811 #define DFSDM_FLTFCR_FORD_2 (0x4U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 6812 #define DFSDM_FLTFCR_FORD_1 (0x2U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 6813 #define DFSDM_FLTFCR_FORD_0 (0x1U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 6814 #define DFSDM_FLTFCR_FOSR_Pos (16U)
<> 128:9bcdf88f62b0 6815 #define DFSDM_FLTFCR_FOSR_Msk (0x3FFU << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
<> 128:9bcdf88f62b0 6816 #define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
<> 128:9bcdf88f62b0 6817 #define DFSDM_FLTFCR_IOSR_Pos (0U)
<> 128:9bcdf88f62b0 6818 #define DFSDM_FLTFCR_IOSR_Msk (0xFFU << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 6819 #define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
<> 128:9bcdf88f62b0 6820
<> 128:9bcdf88f62b0 6821 /*************** Bit definition for DFSDM_FLTJDATAR register *****************/
<> 128:9bcdf88f62b0 6822 #define DFSDM_FLTJDATAR_JDATA_Pos (8U)
<> 128:9bcdf88f62b0 6823 #define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
<> 128:9bcdf88f62b0 6824 #define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
<> 128:9bcdf88f62b0 6825 #define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
<> 128:9bcdf88f62b0 6826 #define DFSDM_FLTJDATAR_JDATACH_Msk (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
<> 128:9bcdf88f62b0 6827 #define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
<> 128:9bcdf88f62b0 6828
<> 128:9bcdf88f62b0 6829 /*************** Bit definition for DFSDM_FLTRDATAR register *****************/
<> 128:9bcdf88f62b0 6830 #define DFSDM_FLTRDATAR_RDATA_Pos (8U)
<> 128:9bcdf88f62b0 6831 #define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
<> 128:9bcdf88f62b0 6832 #define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
<> 128:9bcdf88f62b0 6833 #define DFSDM_FLTRDATAR_RPEND_Pos (4U)
<> 128:9bcdf88f62b0 6834 #define DFSDM_FLTRDATAR_RPEND_Msk (0x1U << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 6835 #define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
<> 128:9bcdf88f62b0 6836 #define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
<> 128:9bcdf88f62b0 6837 #define DFSDM_FLTRDATAR_RDATACH_Msk (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
<> 128:9bcdf88f62b0 6838 #define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
<> 128:9bcdf88f62b0 6839
<> 128:9bcdf88f62b0 6840 /*************** Bit definition for DFSDM_FLTAWHTR register ******************/
<> 128:9bcdf88f62b0 6841 #define DFSDM_FLTAWHTR_AWHT_Pos (8U)
<> 128:9bcdf88f62b0 6842 #define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
<> 128:9bcdf88f62b0 6843 #define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
<> 128:9bcdf88f62b0 6844 #define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
<> 128:9bcdf88f62b0 6845 #define DFSDM_FLTAWHTR_BKAWH_Msk (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 6846 #define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
<> 128:9bcdf88f62b0 6847
<> 128:9bcdf88f62b0 6848 /*************** Bit definition for DFSDM_FLTAWLTR register ******************/
<> 128:9bcdf88f62b0 6849 #define DFSDM_FLTAWLTR_AWLT_Pos (8U)
<> 128:9bcdf88f62b0 6850 #define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
<> 128:9bcdf88f62b0 6851 #define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
<> 128:9bcdf88f62b0 6852 #define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
<> 128:9bcdf88f62b0 6853 #define DFSDM_FLTAWLTR_BKAWL_Msk (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 6854 #define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
<> 128:9bcdf88f62b0 6855
<> 128:9bcdf88f62b0 6856 /*************** Bit definition for DFSDM_FLTAWSR register *******************/
<> 128:9bcdf88f62b0 6857 #define DFSDM_FLTAWSR_AWHTF_Pos (8U)
<> 128:9bcdf88f62b0 6858 #define DFSDM_FLTAWSR_AWHTF_Msk (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 6859 #define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
<> 128:9bcdf88f62b0 6860 #define DFSDM_FLTAWSR_AWLTF_Pos (0U)
<> 128:9bcdf88f62b0 6861 #define DFSDM_FLTAWSR_AWLTF_Msk (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 6862 #define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
<> 128:9bcdf88f62b0 6863
<> 128:9bcdf88f62b0 6864 /*************** Bit definition for DFSDM_FLTAWCFR register ******************/
<> 128:9bcdf88f62b0 6865 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
<> 128:9bcdf88f62b0 6866 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 6867 #define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
<> 128:9bcdf88f62b0 6868 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
<> 128:9bcdf88f62b0 6869 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 6870 #define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
<> 128:9bcdf88f62b0 6871
<> 128:9bcdf88f62b0 6872 /*************** Bit definition for DFSDM_FLTEXMAX register ******************/
<> 128:9bcdf88f62b0 6873 #define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
<> 128:9bcdf88f62b0 6874 #define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
<> 128:9bcdf88f62b0 6875 #define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
<> 128:9bcdf88f62b0 6876 #define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
<> 128:9bcdf88f62b0 6877 #define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
<> 128:9bcdf88f62b0 6878 #define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
<> 128:9bcdf88f62b0 6879
<> 128:9bcdf88f62b0 6880 /*************** Bit definition for DFSDM_FLTEXMIN register ******************/
<> 128:9bcdf88f62b0 6881 #define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
<> 128:9bcdf88f62b0 6882 #define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
<> 128:9bcdf88f62b0 6883 #define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
<> 128:9bcdf88f62b0 6884 #define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
<> 128:9bcdf88f62b0 6885 #define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
<> 128:9bcdf88f62b0 6886 #define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
<> 128:9bcdf88f62b0 6887
<> 128:9bcdf88f62b0 6888 /*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
<> 128:9bcdf88f62b0 6889 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
<> 128:9bcdf88f62b0 6890 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
<> 128:9bcdf88f62b0 6891 #define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
<> 128:9bcdf88f62b0 6892
<> 128:9bcdf88f62b0 6893 /******************************************************************************/
<> 128:9bcdf88f62b0 6894 /* */
<> 128:9bcdf88f62b0 6895 /* DMA Controller (DMA) */
<> 128:9bcdf88f62b0 6896 /* */
<> 128:9bcdf88f62b0 6897 /******************************************************************************/
<> 128:9bcdf88f62b0 6898
<> 128:9bcdf88f62b0 6899 /******************* Bit definition for DMA_ISR register ********************/
<> 128:9bcdf88f62b0 6900 #define DMA_ISR_GIF1_Pos (0U)
<> 128:9bcdf88f62b0 6901 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 6902 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
<> 128:9bcdf88f62b0 6903 #define DMA_ISR_TCIF1_Pos (1U)
<> 128:9bcdf88f62b0 6904 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 6905 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
<> 128:9bcdf88f62b0 6906 #define DMA_ISR_HTIF1_Pos (2U)
<> 128:9bcdf88f62b0 6907 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 6908 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
<> 128:9bcdf88f62b0 6909 #define DMA_ISR_TEIF1_Pos (3U)
<> 128:9bcdf88f62b0 6910 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 6911 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
<> 128:9bcdf88f62b0 6912 #define DMA_ISR_GIF2_Pos (4U)
<> 128:9bcdf88f62b0 6913 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 6914 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
<> 128:9bcdf88f62b0 6915 #define DMA_ISR_TCIF2_Pos (5U)
<> 128:9bcdf88f62b0 6916 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 6917 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
<> 128:9bcdf88f62b0 6918 #define DMA_ISR_HTIF2_Pos (6U)
<> 128:9bcdf88f62b0 6919 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 6920 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
<> 128:9bcdf88f62b0 6921 #define DMA_ISR_TEIF2_Pos (7U)
<> 128:9bcdf88f62b0 6922 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 6923 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
<> 128:9bcdf88f62b0 6924 #define DMA_ISR_GIF3_Pos (8U)
<> 128:9bcdf88f62b0 6925 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 6926 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
<> 128:9bcdf88f62b0 6927 #define DMA_ISR_TCIF3_Pos (9U)
<> 128:9bcdf88f62b0 6928 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 6929 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
<> 128:9bcdf88f62b0 6930 #define DMA_ISR_HTIF3_Pos (10U)
<> 128:9bcdf88f62b0 6931 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 6932 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
<> 128:9bcdf88f62b0 6933 #define DMA_ISR_TEIF3_Pos (11U)
<> 128:9bcdf88f62b0 6934 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 6935 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
<> 128:9bcdf88f62b0 6936 #define DMA_ISR_GIF4_Pos (12U)
<> 128:9bcdf88f62b0 6937 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 6938 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
<> 128:9bcdf88f62b0 6939 #define DMA_ISR_TCIF4_Pos (13U)
<> 128:9bcdf88f62b0 6940 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 6941 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
<> 128:9bcdf88f62b0 6942 #define DMA_ISR_HTIF4_Pos (14U)
<> 128:9bcdf88f62b0 6943 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 6944 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
<> 128:9bcdf88f62b0 6945 #define DMA_ISR_TEIF4_Pos (15U)
<> 128:9bcdf88f62b0 6946 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 6947 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
<> 128:9bcdf88f62b0 6948 #define DMA_ISR_GIF5_Pos (16U)
<> 128:9bcdf88f62b0 6949 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 6950 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
<> 128:9bcdf88f62b0 6951 #define DMA_ISR_TCIF5_Pos (17U)
<> 128:9bcdf88f62b0 6952 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 6953 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
<> 128:9bcdf88f62b0 6954 #define DMA_ISR_HTIF5_Pos (18U)
<> 128:9bcdf88f62b0 6955 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 6956 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
<> 128:9bcdf88f62b0 6957 #define DMA_ISR_TEIF5_Pos (19U)
<> 128:9bcdf88f62b0 6958 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 6959 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
<> 128:9bcdf88f62b0 6960 #define DMA_ISR_GIF6_Pos (20U)
<> 128:9bcdf88f62b0 6961 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 6962 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
<> 128:9bcdf88f62b0 6963 #define DMA_ISR_TCIF6_Pos (21U)
<> 128:9bcdf88f62b0 6964 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 6965 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
<> 128:9bcdf88f62b0 6966 #define DMA_ISR_HTIF6_Pos (22U)
<> 128:9bcdf88f62b0 6967 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 6968 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
<> 128:9bcdf88f62b0 6969 #define DMA_ISR_TEIF6_Pos (23U)
<> 128:9bcdf88f62b0 6970 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 6971 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
<> 128:9bcdf88f62b0 6972 #define DMA_ISR_GIF7_Pos (24U)
<> 128:9bcdf88f62b0 6973 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 6974 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
<> 128:9bcdf88f62b0 6975 #define DMA_ISR_TCIF7_Pos (25U)
<> 128:9bcdf88f62b0 6976 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 6977 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
<> 128:9bcdf88f62b0 6978 #define DMA_ISR_HTIF7_Pos (26U)
<> 128:9bcdf88f62b0 6979 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 6980 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
<> 128:9bcdf88f62b0 6981 #define DMA_ISR_TEIF7_Pos (27U)
<> 128:9bcdf88f62b0 6982 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 6983 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
<> 128:9bcdf88f62b0 6984
<> 128:9bcdf88f62b0 6985 /******************* Bit definition for DMA_IFCR register *******************/
<> 128:9bcdf88f62b0 6986 #define DMA_IFCR_CGIF1_Pos (0U)
<> 128:9bcdf88f62b0 6987 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 6988 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
<> 128:9bcdf88f62b0 6989 #define DMA_IFCR_CTCIF1_Pos (1U)
<> 128:9bcdf88f62b0 6990 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 6991 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
<> 128:9bcdf88f62b0 6992 #define DMA_IFCR_CHTIF1_Pos (2U)
<> 128:9bcdf88f62b0 6993 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 6994 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
<> 128:9bcdf88f62b0 6995 #define DMA_IFCR_CTEIF1_Pos (3U)
<> 128:9bcdf88f62b0 6996 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 6997 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
<> 128:9bcdf88f62b0 6998 #define DMA_IFCR_CGIF2_Pos (4U)
<> 128:9bcdf88f62b0 6999 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 7000 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
<> 128:9bcdf88f62b0 7001 #define DMA_IFCR_CTCIF2_Pos (5U)
<> 128:9bcdf88f62b0 7002 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 7003 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
<> 128:9bcdf88f62b0 7004 #define DMA_IFCR_CHTIF2_Pos (6U)
<> 128:9bcdf88f62b0 7005 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 7006 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
<> 128:9bcdf88f62b0 7007 #define DMA_IFCR_CTEIF2_Pos (7U)
<> 128:9bcdf88f62b0 7008 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 7009 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
<> 128:9bcdf88f62b0 7010 #define DMA_IFCR_CGIF3_Pos (8U)
<> 128:9bcdf88f62b0 7011 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 7012 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
<> 128:9bcdf88f62b0 7013 #define DMA_IFCR_CTCIF3_Pos (9U)
<> 128:9bcdf88f62b0 7014 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 7015 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
<> 128:9bcdf88f62b0 7016 #define DMA_IFCR_CHTIF3_Pos (10U)
<> 128:9bcdf88f62b0 7017 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 7018 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
<> 128:9bcdf88f62b0 7019 #define DMA_IFCR_CTEIF3_Pos (11U)
<> 128:9bcdf88f62b0 7020 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 7021 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
<> 128:9bcdf88f62b0 7022 #define DMA_IFCR_CGIF4_Pos (12U)
<> 128:9bcdf88f62b0 7023 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 7024 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
<> 128:9bcdf88f62b0 7025 #define DMA_IFCR_CTCIF4_Pos (13U)
<> 128:9bcdf88f62b0 7026 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 7027 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
<> 128:9bcdf88f62b0 7028 #define DMA_IFCR_CHTIF4_Pos (14U)
<> 128:9bcdf88f62b0 7029 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 7030 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
<> 128:9bcdf88f62b0 7031 #define DMA_IFCR_CTEIF4_Pos (15U)
<> 128:9bcdf88f62b0 7032 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 7033 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
<> 128:9bcdf88f62b0 7034 #define DMA_IFCR_CGIF5_Pos (16U)
<> 128:9bcdf88f62b0 7035 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 7036 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
<> 128:9bcdf88f62b0 7037 #define DMA_IFCR_CTCIF5_Pos (17U)
<> 128:9bcdf88f62b0 7038 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 7039 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
<> 128:9bcdf88f62b0 7040 #define DMA_IFCR_CHTIF5_Pos (18U)
<> 128:9bcdf88f62b0 7041 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 7042 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
<> 128:9bcdf88f62b0 7043 #define DMA_IFCR_CTEIF5_Pos (19U)
<> 128:9bcdf88f62b0 7044 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 7045 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
<> 128:9bcdf88f62b0 7046 #define DMA_IFCR_CGIF6_Pos (20U)
<> 128:9bcdf88f62b0 7047 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 7048 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
<> 128:9bcdf88f62b0 7049 #define DMA_IFCR_CTCIF6_Pos (21U)
<> 128:9bcdf88f62b0 7050 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 7051 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
<> 128:9bcdf88f62b0 7052 #define DMA_IFCR_CHTIF6_Pos (22U)
<> 128:9bcdf88f62b0 7053 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 7054 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
<> 128:9bcdf88f62b0 7055 #define DMA_IFCR_CTEIF6_Pos (23U)
<> 128:9bcdf88f62b0 7056 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 7057 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
<> 128:9bcdf88f62b0 7058 #define DMA_IFCR_CGIF7_Pos (24U)
<> 128:9bcdf88f62b0 7059 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 7060 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
<> 128:9bcdf88f62b0 7061 #define DMA_IFCR_CTCIF7_Pos (25U)
<> 128:9bcdf88f62b0 7062 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 7063 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
<> 128:9bcdf88f62b0 7064 #define DMA_IFCR_CHTIF7_Pos (26U)
<> 128:9bcdf88f62b0 7065 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 7066 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
<> 128:9bcdf88f62b0 7067 #define DMA_IFCR_CTEIF7_Pos (27U)
<> 128:9bcdf88f62b0 7068 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 7069 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
<> 128:9bcdf88f62b0 7070
<> 128:9bcdf88f62b0 7071 /******************* Bit definition for DMA_CCR register ********************/
<> 128:9bcdf88f62b0 7072 #define DMA_CCR_EN_Pos (0U)
<> 128:9bcdf88f62b0 7073 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 7074 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
<> 128:9bcdf88f62b0 7075 #define DMA_CCR_TCIE_Pos (1U)
<> 128:9bcdf88f62b0 7076 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 7077 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
<> 128:9bcdf88f62b0 7078 #define DMA_CCR_HTIE_Pos (2U)
<> 128:9bcdf88f62b0 7079 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 7080 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
<> 128:9bcdf88f62b0 7081 #define DMA_CCR_TEIE_Pos (3U)
<> 128:9bcdf88f62b0 7082 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 7083 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
<> 128:9bcdf88f62b0 7084 #define DMA_CCR_DIR_Pos (4U)
<> 128:9bcdf88f62b0 7085 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 7086 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
<> 128:9bcdf88f62b0 7087 #define DMA_CCR_CIRC_Pos (5U)
<> 128:9bcdf88f62b0 7088 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 7089 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
<> 128:9bcdf88f62b0 7090 #define DMA_CCR_PINC_Pos (6U)
<> 128:9bcdf88f62b0 7091 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 7092 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
<> 128:9bcdf88f62b0 7093 #define DMA_CCR_MINC_Pos (7U)
<> 128:9bcdf88f62b0 7094 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 7095 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
<> 128:9bcdf88f62b0 7096
<> 128:9bcdf88f62b0 7097 #define DMA_CCR_PSIZE_Pos (8U)
<> 128:9bcdf88f62b0 7098 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
<> 128:9bcdf88f62b0 7099 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
<> 128:9bcdf88f62b0 7100 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 7101 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 7102
<> 128:9bcdf88f62b0 7103 #define DMA_CCR_MSIZE_Pos (10U)
<> 128:9bcdf88f62b0 7104 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
<> 128:9bcdf88f62b0 7105 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
<> 128:9bcdf88f62b0 7106 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 7107 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 7108
<> 128:9bcdf88f62b0 7109 #define DMA_CCR_PL_Pos (12U)
<> 128:9bcdf88f62b0 7110 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
<> 128:9bcdf88f62b0 7111 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
<> 128:9bcdf88f62b0 7112 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 7113 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 7114
<> 128:9bcdf88f62b0 7115 #define DMA_CCR_MEM2MEM_Pos (14U)
<> 128:9bcdf88f62b0 7116 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 7117 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
<> 128:9bcdf88f62b0 7118
<> 128:9bcdf88f62b0 7119 /****************** Bit definition for DMA_CNDTR register *******************/
<> 128:9bcdf88f62b0 7120 #define DMA_CNDTR_NDT_Pos (0U)
<> 128:9bcdf88f62b0 7121 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 7122 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
<> 128:9bcdf88f62b0 7123
<> 128:9bcdf88f62b0 7124 /****************** Bit definition for DMA_CPAR register ********************/
<> 128:9bcdf88f62b0 7125 #define DMA_CPAR_PA_Pos (0U)
<> 128:9bcdf88f62b0 7126 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 7127 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
<> 128:9bcdf88f62b0 7128
<> 128:9bcdf88f62b0 7129 /****************** Bit definition for DMA_CMAR register ********************/
<> 128:9bcdf88f62b0 7130 #define DMA_CMAR_MA_Pos (0U)
<> 128:9bcdf88f62b0 7131 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 7132 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
<> 128:9bcdf88f62b0 7133
<> 128:9bcdf88f62b0 7134
<> 128:9bcdf88f62b0 7135 /******************* Bit definition for DMA_CSELR register *******************/
<> 128:9bcdf88f62b0 7136 #define DMA_CSELR_C1S_Pos (0U)
<> 128:9bcdf88f62b0 7137 #define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 7138 #define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
<> 128:9bcdf88f62b0 7139 #define DMA_CSELR_C2S_Pos (4U)
<> 128:9bcdf88f62b0 7140 #define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
<> 128:9bcdf88f62b0 7141 #define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
<> 128:9bcdf88f62b0 7142 #define DMA_CSELR_C3S_Pos (8U)
<> 128:9bcdf88f62b0 7143 #define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
<> 128:9bcdf88f62b0 7144 #define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
<> 128:9bcdf88f62b0 7145 #define DMA_CSELR_C4S_Pos (12U)
<> 128:9bcdf88f62b0 7146 #define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
<> 128:9bcdf88f62b0 7147 #define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
<> 128:9bcdf88f62b0 7148 #define DMA_CSELR_C5S_Pos (16U)
<> 128:9bcdf88f62b0 7149 #define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
<> 128:9bcdf88f62b0 7150 #define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
<> 128:9bcdf88f62b0 7151 #define DMA_CSELR_C6S_Pos (20U)
<> 128:9bcdf88f62b0 7152 #define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
<> 128:9bcdf88f62b0 7153 #define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
<> 128:9bcdf88f62b0 7154 #define DMA_CSELR_C7S_Pos (24U)
<> 128:9bcdf88f62b0 7155 #define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
<> 128:9bcdf88f62b0 7156 #define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
<> 128:9bcdf88f62b0 7157
<> 128:9bcdf88f62b0 7158 /******************************************************************************/
<> 128:9bcdf88f62b0 7159 /* */
<> 128:9bcdf88f62b0 7160 /* External Interrupt/Event Controller */
<> 128:9bcdf88f62b0 7161 /* */
<> 128:9bcdf88f62b0 7162 /******************************************************************************/
<> 128:9bcdf88f62b0 7163 /******************* Bit definition for EXTI_IMR1 register ******************/
<> 128:9bcdf88f62b0 7164 #define EXTI_IMR1_IM0_Pos (0U)
<> 128:9bcdf88f62b0 7165 #define EXTI_IMR1_IM0_Msk (0x1U << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 7166 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
<> 128:9bcdf88f62b0 7167 #define EXTI_IMR1_IM1_Pos (1U)
<> 128:9bcdf88f62b0 7168 #define EXTI_IMR1_IM1_Msk (0x1U << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 7169 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
<> 128:9bcdf88f62b0 7170 #define EXTI_IMR1_IM2_Pos (2U)
<> 128:9bcdf88f62b0 7171 #define EXTI_IMR1_IM2_Msk (0x1U << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 7172 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
<> 128:9bcdf88f62b0 7173 #define EXTI_IMR1_IM3_Pos (3U)
<> 128:9bcdf88f62b0 7174 #define EXTI_IMR1_IM3_Msk (0x1U << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 7175 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
<> 128:9bcdf88f62b0 7176 #define EXTI_IMR1_IM4_Pos (4U)
<> 128:9bcdf88f62b0 7177 #define EXTI_IMR1_IM4_Msk (0x1U << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 7178 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
<> 128:9bcdf88f62b0 7179 #define EXTI_IMR1_IM5_Pos (5U)
<> 128:9bcdf88f62b0 7180 #define EXTI_IMR1_IM5_Msk (0x1U << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 7181 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
<> 128:9bcdf88f62b0 7182 #define EXTI_IMR1_IM6_Pos (6U)
<> 128:9bcdf88f62b0 7183 #define EXTI_IMR1_IM6_Msk (0x1U << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 7184 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
<> 128:9bcdf88f62b0 7185 #define EXTI_IMR1_IM7_Pos (7U)
<> 128:9bcdf88f62b0 7186 #define EXTI_IMR1_IM7_Msk (0x1U << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 7187 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
<> 128:9bcdf88f62b0 7188 #define EXTI_IMR1_IM8_Pos (8U)
<> 128:9bcdf88f62b0 7189 #define EXTI_IMR1_IM8_Msk (0x1U << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 7190 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
<> 128:9bcdf88f62b0 7191 #define EXTI_IMR1_IM9_Pos (9U)
<> 128:9bcdf88f62b0 7192 #define EXTI_IMR1_IM9_Msk (0x1U << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 7193 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
<> 128:9bcdf88f62b0 7194 #define EXTI_IMR1_IM10_Pos (10U)
<> 128:9bcdf88f62b0 7195 #define EXTI_IMR1_IM10_Msk (0x1U << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 7196 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
<> 128:9bcdf88f62b0 7197 #define EXTI_IMR1_IM11_Pos (11U)
<> 128:9bcdf88f62b0 7198 #define EXTI_IMR1_IM11_Msk (0x1U << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 7199 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
<> 128:9bcdf88f62b0 7200 #define EXTI_IMR1_IM12_Pos (12U)
<> 128:9bcdf88f62b0 7201 #define EXTI_IMR1_IM12_Msk (0x1U << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 7202 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
<> 128:9bcdf88f62b0 7203 #define EXTI_IMR1_IM13_Pos (13U)
<> 128:9bcdf88f62b0 7204 #define EXTI_IMR1_IM13_Msk (0x1U << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 7205 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
<> 128:9bcdf88f62b0 7206 #define EXTI_IMR1_IM14_Pos (14U)
<> 128:9bcdf88f62b0 7207 #define EXTI_IMR1_IM14_Msk (0x1U << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 7208 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
<> 128:9bcdf88f62b0 7209 #define EXTI_IMR1_IM15_Pos (15U)
<> 128:9bcdf88f62b0 7210 #define EXTI_IMR1_IM15_Msk (0x1U << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 7211 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
<> 128:9bcdf88f62b0 7212 #define EXTI_IMR1_IM16_Pos (16U)
<> 128:9bcdf88f62b0 7213 #define EXTI_IMR1_IM16_Msk (0x1U << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 7214 #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
<> 128:9bcdf88f62b0 7215 #define EXTI_IMR1_IM17_Pos (17U)
<> 128:9bcdf88f62b0 7216 #define EXTI_IMR1_IM17_Msk (0x1U << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 7217 #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
<> 128:9bcdf88f62b0 7218 #define EXTI_IMR1_IM18_Pos (18U)
<> 128:9bcdf88f62b0 7219 #define EXTI_IMR1_IM18_Msk (0x1U << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 7220 #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
<> 128:9bcdf88f62b0 7221 #define EXTI_IMR1_IM19_Pos (19U)
<> 128:9bcdf88f62b0 7222 #define EXTI_IMR1_IM19_Msk (0x1U << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 7223 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
<> 128:9bcdf88f62b0 7224 #define EXTI_IMR1_IM20_Pos (20U)
<> 128:9bcdf88f62b0 7225 #define EXTI_IMR1_IM20_Msk (0x1U << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 7226 #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
<> 128:9bcdf88f62b0 7227 #define EXTI_IMR1_IM21_Pos (21U)
<> 128:9bcdf88f62b0 7228 #define EXTI_IMR1_IM21_Msk (0x1U << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 7229 #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
<> 128:9bcdf88f62b0 7230 #define EXTI_IMR1_IM22_Pos (22U)
<> 128:9bcdf88f62b0 7231 #define EXTI_IMR1_IM22_Msk (0x1U << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 7232 #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
<> 128:9bcdf88f62b0 7233 #define EXTI_IMR1_IM23_Pos (23U)
<> 128:9bcdf88f62b0 7234 #define EXTI_IMR1_IM23_Msk (0x1U << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 7235 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
<> 128:9bcdf88f62b0 7236 #define EXTI_IMR1_IM24_Pos (24U)
<> 128:9bcdf88f62b0 7237 #define EXTI_IMR1_IM24_Msk (0x1U << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 7238 #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
<> 128:9bcdf88f62b0 7239 #define EXTI_IMR1_IM25_Pos (25U)
<> 128:9bcdf88f62b0 7240 #define EXTI_IMR1_IM25_Msk (0x1U << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 7241 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
<> 128:9bcdf88f62b0 7242 #define EXTI_IMR1_IM26_Pos (26U)
<> 128:9bcdf88f62b0 7243 #define EXTI_IMR1_IM26_Msk (0x1U << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 7244 #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
<> 128:9bcdf88f62b0 7245 #define EXTI_IMR1_IM27_Pos (27U)
<> 128:9bcdf88f62b0 7246 #define EXTI_IMR1_IM27_Msk (0x1U << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 7247 #define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
<> 128:9bcdf88f62b0 7248 #define EXTI_IMR1_IM28_Pos (28U)
<> 128:9bcdf88f62b0 7249 #define EXTI_IMR1_IM28_Msk (0x1U << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 7250 #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
<> 128:9bcdf88f62b0 7251 #define EXTI_IMR1_IM29_Pos (29U)
<> 128:9bcdf88f62b0 7252 #define EXTI_IMR1_IM29_Msk (0x1U << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 7253 #define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
<> 128:9bcdf88f62b0 7254 #define EXTI_IMR1_IM30_Pos (30U)
<> 128:9bcdf88f62b0 7255 #define EXTI_IMR1_IM30_Msk (0x1U << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 7256 #define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
<> 128:9bcdf88f62b0 7257 #define EXTI_IMR1_IM31_Pos (31U)
<> 128:9bcdf88f62b0 7258 #define EXTI_IMR1_IM31_Msk (0x1U << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 7259 #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
<> 128:9bcdf88f62b0 7260 #define EXTI_IMR1_IM_Pos (0U)
<> 128:9bcdf88f62b0 7261 #define EXTI_IMR1_IM_Msk (0xFFFFFFFFU << EXTI_IMR1_IM_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 7262 #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
<> 128:9bcdf88f62b0 7263
<> 128:9bcdf88f62b0 7264 /******************* Bit definition for EXTI_EMR1 register ******************/
<> 128:9bcdf88f62b0 7265 #define EXTI_EMR1_EM0_Pos (0U)
<> 128:9bcdf88f62b0 7266 #define EXTI_EMR1_EM0_Msk (0x1U << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 7267 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
<> 128:9bcdf88f62b0 7268 #define EXTI_EMR1_EM1_Pos (1U)
<> 128:9bcdf88f62b0 7269 #define EXTI_EMR1_EM1_Msk (0x1U << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 7270 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
<> 128:9bcdf88f62b0 7271 #define EXTI_EMR1_EM2_Pos (2U)
<> 128:9bcdf88f62b0 7272 #define EXTI_EMR1_EM2_Msk (0x1U << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 7273 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
<> 128:9bcdf88f62b0 7274 #define EXTI_EMR1_EM3_Pos (3U)
<> 128:9bcdf88f62b0 7275 #define EXTI_EMR1_EM3_Msk (0x1U << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 7276 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
<> 128:9bcdf88f62b0 7277 #define EXTI_EMR1_EM4_Pos (4U)
<> 128:9bcdf88f62b0 7278 #define EXTI_EMR1_EM4_Msk (0x1U << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 7279 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
<> 128:9bcdf88f62b0 7280 #define EXTI_EMR1_EM5_Pos (5U)
<> 128:9bcdf88f62b0 7281 #define EXTI_EMR1_EM5_Msk (0x1U << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 7282 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
<> 128:9bcdf88f62b0 7283 #define EXTI_EMR1_EM6_Pos (6U)
<> 128:9bcdf88f62b0 7284 #define EXTI_EMR1_EM6_Msk (0x1U << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 7285 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
<> 128:9bcdf88f62b0 7286 #define EXTI_EMR1_EM7_Pos (7U)
<> 128:9bcdf88f62b0 7287 #define EXTI_EMR1_EM7_Msk (0x1U << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 7288 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
<> 128:9bcdf88f62b0 7289 #define EXTI_EMR1_EM8_Pos (8U)
<> 128:9bcdf88f62b0 7290 #define EXTI_EMR1_EM8_Msk (0x1U << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 7291 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
<> 128:9bcdf88f62b0 7292 #define EXTI_EMR1_EM9_Pos (9U)
<> 128:9bcdf88f62b0 7293 #define EXTI_EMR1_EM9_Msk (0x1U << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 7294 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
<> 128:9bcdf88f62b0 7295 #define EXTI_EMR1_EM10_Pos (10U)
<> 128:9bcdf88f62b0 7296 #define EXTI_EMR1_EM10_Msk (0x1U << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 7297 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
<> 128:9bcdf88f62b0 7298 #define EXTI_EMR1_EM11_Pos (11U)
<> 128:9bcdf88f62b0 7299 #define EXTI_EMR1_EM11_Msk (0x1U << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 7300 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
<> 128:9bcdf88f62b0 7301 #define EXTI_EMR1_EM12_Pos (12U)
<> 128:9bcdf88f62b0 7302 #define EXTI_EMR1_EM12_Msk (0x1U << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 7303 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
<> 128:9bcdf88f62b0 7304 #define EXTI_EMR1_EM13_Pos (13U)
<> 128:9bcdf88f62b0 7305 #define EXTI_EMR1_EM13_Msk (0x1U << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 7306 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
<> 128:9bcdf88f62b0 7307 #define EXTI_EMR1_EM14_Pos (14U)
<> 128:9bcdf88f62b0 7308 #define EXTI_EMR1_EM14_Msk (0x1U << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 7309 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
<> 128:9bcdf88f62b0 7310 #define EXTI_EMR1_EM15_Pos (15U)
<> 128:9bcdf88f62b0 7311 #define EXTI_EMR1_EM15_Msk (0x1U << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 7312 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
<> 128:9bcdf88f62b0 7313 #define EXTI_EMR1_EM16_Pos (16U)
<> 128:9bcdf88f62b0 7314 #define EXTI_EMR1_EM16_Msk (0x1U << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 7315 #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
<> 128:9bcdf88f62b0 7316 #define EXTI_EMR1_EM17_Pos (17U)
<> 128:9bcdf88f62b0 7317 #define EXTI_EMR1_EM17_Msk (0x1U << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 7318 #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
<> 128:9bcdf88f62b0 7319 #define EXTI_EMR1_EM18_Pos (18U)
<> 128:9bcdf88f62b0 7320 #define EXTI_EMR1_EM18_Msk (0x1U << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 7321 #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
<> 128:9bcdf88f62b0 7322 #define EXTI_EMR1_EM19_Pos (19U)
<> 128:9bcdf88f62b0 7323 #define EXTI_EMR1_EM19_Msk (0x1U << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 7324 #define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
<> 128:9bcdf88f62b0 7325 #define EXTI_EMR1_EM20_Pos (20U)
<> 128:9bcdf88f62b0 7326 #define EXTI_EMR1_EM20_Msk (0x1U << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 7327 #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
<> 128:9bcdf88f62b0 7328 #define EXTI_EMR1_EM21_Pos (21U)
<> 128:9bcdf88f62b0 7329 #define EXTI_EMR1_EM21_Msk (0x1U << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 7330 #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
<> 128:9bcdf88f62b0 7331 #define EXTI_EMR1_EM22_Pos (22U)
<> 128:9bcdf88f62b0 7332 #define EXTI_EMR1_EM22_Msk (0x1U << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 7333 #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
<> 128:9bcdf88f62b0 7334 #define EXTI_EMR1_EM23_Pos (23U)
<> 128:9bcdf88f62b0 7335 #define EXTI_EMR1_EM23_Msk (0x1U << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 7336 #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
<> 128:9bcdf88f62b0 7337 #define EXTI_EMR1_EM24_Pos (24U)
<> 128:9bcdf88f62b0 7338 #define EXTI_EMR1_EM24_Msk (0x1U << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 7339 #define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
<> 128:9bcdf88f62b0 7340 #define EXTI_EMR1_EM25_Pos (25U)
<> 128:9bcdf88f62b0 7341 #define EXTI_EMR1_EM25_Msk (0x1U << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 7342 #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
<> 128:9bcdf88f62b0 7343 #define EXTI_EMR1_EM26_Pos (26U)
<> 128:9bcdf88f62b0 7344 #define EXTI_EMR1_EM26_Msk (0x1U << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 7345 #define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
<> 128:9bcdf88f62b0 7346 #define EXTI_EMR1_EM27_Pos (27U)
<> 128:9bcdf88f62b0 7347 #define EXTI_EMR1_EM27_Msk (0x1U << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 7348 #define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
<> 128:9bcdf88f62b0 7349 #define EXTI_EMR1_EM28_Pos (28U)
<> 128:9bcdf88f62b0 7350 #define EXTI_EMR1_EM28_Msk (0x1U << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 7351 #define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
<> 128:9bcdf88f62b0 7352 #define EXTI_EMR1_EM29_Pos (29U)
<> 128:9bcdf88f62b0 7353 #define EXTI_EMR1_EM29_Msk (0x1U << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 7354 #define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
<> 128:9bcdf88f62b0 7355 #define EXTI_EMR1_EM30_Pos (30U)
<> 128:9bcdf88f62b0 7356 #define EXTI_EMR1_EM30_Msk (0x1U << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 7357 #define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
<> 128:9bcdf88f62b0 7358 #define EXTI_EMR1_EM31_Pos (31U)
<> 128:9bcdf88f62b0 7359 #define EXTI_EMR1_EM31_Msk (0x1U << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 7360 #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
<> 128:9bcdf88f62b0 7361
<> 128:9bcdf88f62b0 7362 /****************** Bit definition for EXTI_RTSR1 register ******************/
<> 128:9bcdf88f62b0 7363 #define EXTI_RTSR1_RT0_Pos (0U)
<> 128:9bcdf88f62b0 7364 #define EXTI_RTSR1_RT0_Msk (0x1U << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 7365 #define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
<> 128:9bcdf88f62b0 7366 #define EXTI_RTSR1_RT1_Pos (1U)
<> 128:9bcdf88f62b0 7367 #define EXTI_RTSR1_RT1_Msk (0x1U << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 7368 #define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
<> 128:9bcdf88f62b0 7369 #define EXTI_RTSR1_RT2_Pos (2U)
<> 128:9bcdf88f62b0 7370 #define EXTI_RTSR1_RT2_Msk (0x1U << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 7371 #define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
<> 128:9bcdf88f62b0 7372 #define EXTI_RTSR1_RT3_Pos (3U)
<> 128:9bcdf88f62b0 7373 #define EXTI_RTSR1_RT3_Msk (0x1U << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 7374 #define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
<> 128:9bcdf88f62b0 7375 #define EXTI_RTSR1_RT4_Pos (4U)
<> 128:9bcdf88f62b0 7376 #define EXTI_RTSR1_RT4_Msk (0x1U << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 7377 #define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
<> 128:9bcdf88f62b0 7378 #define EXTI_RTSR1_RT5_Pos (5U)
<> 128:9bcdf88f62b0 7379 #define EXTI_RTSR1_RT5_Msk (0x1U << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 7380 #define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
<> 128:9bcdf88f62b0 7381 #define EXTI_RTSR1_RT6_Pos (6U)
<> 128:9bcdf88f62b0 7382 #define EXTI_RTSR1_RT6_Msk (0x1U << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 7383 #define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
<> 128:9bcdf88f62b0 7384 #define EXTI_RTSR1_RT7_Pos (7U)
<> 128:9bcdf88f62b0 7385 #define EXTI_RTSR1_RT7_Msk (0x1U << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 7386 #define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
<> 128:9bcdf88f62b0 7387 #define EXTI_RTSR1_RT8_Pos (8U)
<> 128:9bcdf88f62b0 7388 #define EXTI_RTSR1_RT8_Msk (0x1U << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 7389 #define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
<> 128:9bcdf88f62b0 7390 #define EXTI_RTSR1_RT9_Pos (9U)
<> 128:9bcdf88f62b0 7391 #define EXTI_RTSR1_RT9_Msk (0x1U << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 7392 #define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
<> 128:9bcdf88f62b0 7393 #define EXTI_RTSR1_RT10_Pos (10U)
<> 128:9bcdf88f62b0 7394 #define EXTI_RTSR1_RT10_Msk (0x1U << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 7395 #define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
<> 128:9bcdf88f62b0 7396 #define EXTI_RTSR1_RT11_Pos (11U)
<> 128:9bcdf88f62b0 7397 #define EXTI_RTSR1_RT11_Msk (0x1U << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 7398 #define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
<> 128:9bcdf88f62b0 7399 #define EXTI_RTSR1_RT12_Pos (12U)
<> 128:9bcdf88f62b0 7400 #define EXTI_RTSR1_RT12_Msk (0x1U << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 7401 #define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
<> 128:9bcdf88f62b0 7402 #define EXTI_RTSR1_RT13_Pos (13U)
<> 128:9bcdf88f62b0 7403 #define EXTI_RTSR1_RT13_Msk (0x1U << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 7404 #define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
<> 128:9bcdf88f62b0 7405 #define EXTI_RTSR1_RT14_Pos (14U)
<> 128:9bcdf88f62b0 7406 #define EXTI_RTSR1_RT14_Msk (0x1U << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 7407 #define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
<> 128:9bcdf88f62b0 7408 #define EXTI_RTSR1_RT15_Pos (15U)
<> 128:9bcdf88f62b0 7409 #define EXTI_RTSR1_RT15_Msk (0x1U << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 7410 #define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
<> 128:9bcdf88f62b0 7411 #define EXTI_RTSR1_RT16_Pos (16U)
<> 128:9bcdf88f62b0 7412 #define EXTI_RTSR1_RT16_Msk (0x1U << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 7413 #define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
<> 128:9bcdf88f62b0 7414 #define EXTI_RTSR1_RT18_Pos (18U)
<> 128:9bcdf88f62b0 7415 #define EXTI_RTSR1_RT18_Msk (0x1U << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 7416 #define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */
<> 128:9bcdf88f62b0 7417 #define EXTI_RTSR1_RT19_Pos (19U)
<> 128:9bcdf88f62b0 7418 #define EXTI_RTSR1_RT19_Msk (0x1U << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 7419 #define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
<> 128:9bcdf88f62b0 7420 #define EXTI_RTSR1_RT20_Pos (20U)
<> 128:9bcdf88f62b0 7421 #define EXTI_RTSR1_RT20_Msk (0x1U << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 7422 #define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
<> 128:9bcdf88f62b0 7423 #define EXTI_RTSR1_RT21_Pos (21U)
<> 128:9bcdf88f62b0 7424 #define EXTI_RTSR1_RT21_Msk (0x1U << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 7425 #define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
<> 128:9bcdf88f62b0 7426 #define EXTI_RTSR1_RT22_Pos (22U)
<> 128:9bcdf88f62b0 7427 #define EXTI_RTSR1_RT22_Msk (0x1U << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 7428 #define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
<> 128:9bcdf88f62b0 7429
<> 128:9bcdf88f62b0 7430 /****************** Bit definition for EXTI_FTSR1 register ******************/
<> 128:9bcdf88f62b0 7431 #define EXTI_FTSR1_FT0_Pos (0U)
<> 128:9bcdf88f62b0 7432 #define EXTI_FTSR1_FT0_Msk (0x1U << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 7433 #define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
<> 128:9bcdf88f62b0 7434 #define EXTI_FTSR1_FT1_Pos (1U)
<> 128:9bcdf88f62b0 7435 #define EXTI_FTSR1_FT1_Msk (0x1U << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 7436 #define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
<> 128:9bcdf88f62b0 7437 #define EXTI_FTSR1_FT2_Pos (2U)
<> 128:9bcdf88f62b0 7438 #define EXTI_FTSR1_FT2_Msk (0x1U << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 7439 #define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
<> 128:9bcdf88f62b0 7440 #define EXTI_FTSR1_FT3_Pos (3U)
<> 128:9bcdf88f62b0 7441 #define EXTI_FTSR1_FT3_Msk (0x1U << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 7442 #define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
<> 128:9bcdf88f62b0 7443 #define EXTI_FTSR1_FT4_Pos (4U)
<> 128:9bcdf88f62b0 7444 #define EXTI_FTSR1_FT4_Msk (0x1U << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 7445 #define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
<> 128:9bcdf88f62b0 7446 #define EXTI_FTSR1_FT5_Pos (5U)
<> 128:9bcdf88f62b0 7447 #define EXTI_FTSR1_FT5_Msk (0x1U << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 7448 #define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
<> 128:9bcdf88f62b0 7449 #define EXTI_FTSR1_FT6_Pos (6U)
<> 128:9bcdf88f62b0 7450 #define EXTI_FTSR1_FT6_Msk (0x1U << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 7451 #define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
<> 128:9bcdf88f62b0 7452 #define EXTI_FTSR1_FT7_Pos (7U)
<> 128:9bcdf88f62b0 7453 #define EXTI_FTSR1_FT7_Msk (0x1U << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 7454 #define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
<> 128:9bcdf88f62b0 7455 #define EXTI_FTSR1_FT8_Pos (8U)
<> 128:9bcdf88f62b0 7456 #define EXTI_FTSR1_FT8_Msk (0x1U << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 7457 #define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
<> 128:9bcdf88f62b0 7458 #define EXTI_FTSR1_FT9_Pos (9U)
<> 128:9bcdf88f62b0 7459 #define EXTI_FTSR1_FT9_Msk (0x1U << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 7460 #define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
<> 128:9bcdf88f62b0 7461 #define EXTI_FTSR1_FT10_Pos (10U)
<> 128:9bcdf88f62b0 7462 #define EXTI_FTSR1_FT10_Msk (0x1U << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 7463 #define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
<> 128:9bcdf88f62b0 7464 #define EXTI_FTSR1_FT11_Pos (11U)
<> 128:9bcdf88f62b0 7465 #define EXTI_FTSR1_FT11_Msk (0x1U << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 7466 #define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
<> 128:9bcdf88f62b0 7467 #define EXTI_FTSR1_FT12_Pos (12U)
<> 128:9bcdf88f62b0 7468 #define EXTI_FTSR1_FT12_Msk (0x1U << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 7469 #define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
<> 128:9bcdf88f62b0 7470 #define EXTI_FTSR1_FT13_Pos (13U)
<> 128:9bcdf88f62b0 7471 #define EXTI_FTSR1_FT13_Msk (0x1U << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 7472 #define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
<> 128:9bcdf88f62b0 7473 #define EXTI_FTSR1_FT14_Pos (14U)
<> 128:9bcdf88f62b0 7474 #define EXTI_FTSR1_FT14_Msk (0x1U << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 7475 #define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
<> 128:9bcdf88f62b0 7476 #define EXTI_FTSR1_FT15_Pos (15U)
<> 128:9bcdf88f62b0 7477 #define EXTI_FTSR1_FT15_Msk (0x1U << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 7478 #define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
<> 128:9bcdf88f62b0 7479 #define EXTI_FTSR1_FT16_Pos (16U)
<> 128:9bcdf88f62b0 7480 #define EXTI_FTSR1_FT16_Msk (0x1U << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 7481 #define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
<> 128:9bcdf88f62b0 7482 #define EXTI_FTSR1_FT18_Pos (18U)
<> 128:9bcdf88f62b0 7483 #define EXTI_FTSR1_FT18_Msk (0x1U << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 7484 #define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */
<> 128:9bcdf88f62b0 7485 #define EXTI_FTSR1_FT19_Pos (19U)
<> 128:9bcdf88f62b0 7486 #define EXTI_FTSR1_FT19_Msk (0x1U << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 7487 #define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
<> 128:9bcdf88f62b0 7488 #define EXTI_FTSR1_FT20_Pos (20U)
<> 128:9bcdf88f62b0 7489 #define EXTI_FTSR1_FT20_Msk (0x1U << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 7490 #define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
<> 128:9bcdf88f62b0 7491 #define EXTI_FTSR1_FT21_Pos (21U)
<> 128:9bcdf88f62b0 7492 #define EXTI_FTSR1_FT21_Msk (0x1U << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 7493 #define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
<> 128:9bcdf88f62b0 7494 #define EXTI_FTSR1_FT22_Pos (22U)
<> 128:9bcdf88f62b0 7495 #define EXTI_FTSR1_FT22_Msk (0x1U << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 7496 #define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
<> 128:9bcdf88f62b0 7497
<> 128:9bcdf88f62b0 7498 /****************** Bit definition for EXTI_SWIER1 register *****************/
<> 128:9bcdf88f62b0 7499 #define EXTI_SWIER1_SWI0_Pos (0U)
<> 128:9bcdf88f62b0 7500 #define EXTI_SWIER1_SWI0_Msk (0x1U << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 7501 #define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
<> 128:9bcdf88f62b0 7502 #define EXTI_SWIER1_SWI1_Pos (1U)
<> 128:9bcdf88f62b0 7503 #define EXTI_SWIER1_SWI1_Msk (0x1U << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 7504 #define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
<> 128:9bcdf88f62b0 7505 #define EXTI_SWIER1_SWI2_Pos (2U)
<> 128:9bcdf88f62b0 7506 #define EXTI_SWIER1_SWI2_Msk (0x1U << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 7507 #define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
<> 128:9bcdf88f62b0 7508 #define EXTI_SWIER1_SWI3_Pos (3U)
<> 128:9bcdf88f62b0 7509 #define EXTI_SWIER1_SWI3_Msk (0x1U << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 7510 #define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
<> 128:9bcdf88f62b0 7511 #define EXTI_SWIER1_SWI4_Pos (4U)
<> 128:9bcdf88f62b0 7512 #define EXTI_SWIER1_SWI4_Msk (0x1U << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 7513 #define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
<> 128:9bcdf88f62b0 7514 #define EXTI_SWIER1_SWI5_Pos (5U)
<> 128:9bcdf88f62b0 7515 #define EXTI_SWIER1_SWI5_Msk (0x1U << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 7516 #define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
<> 128:9bcdf88f62b0 7517 #define EXTI_SWIER1_SWI6_Pos (6U)
<> 128:9bcdf88f62b0 7518 #define EXTI_SWIER1_SWI6_Msk (0x1U << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 7519 #define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
<> 128:9bcdf88f62b0 7520 #define EXTI_SWIER1_SWI7_Pos (7U)
<> 128:9bcdf88f62b0 7521 #define EXTI_SWIER1_SWI7_Msk (0x1U << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 7522 #define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
<> 128:9bcdf88f62b0 7523 #define EXTI_SWIER1_SWI8_Pos (8U)
<> 128:9bcdf88f62b0 7524 #define EXTI_SWIER1_SWI8_Msk (0x1U << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 7525 #define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
<> 128:9bcdf88f62b0 7526 #define EXTI_SWIER1_SWI9_Pos (9U)
<> 128:9bcdf88f62b0 7527 #define EXTI_SWIER1_SWI9_Msk (0x1U << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 7528 #define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
<> 128:9bcdf88f62b0 7529 #define EXTI_SWIER1_SWI10_Pos (10U)
<> 128:9bcdf88f62b0 7530 #define EXTI_SWIER1_SWI10_Msk (0x1U << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 7531 #define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
<> 128:9bcdf88f62b0 7532 #define EXTI_SWIER1_SWI11_Pos (11U)
<> 128:9bcdf88f62b0 7533 #define EXTI_SWIER1_SWI11_Msk (0x1U << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 7534 #define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
<> 128:9bcdf88f62b0 7535 #define EXTI_SWIER1_SWI12_Pos (12U)
<> 128:9bcdf88f62b0 7536 #define EXTI_SWIER1_SWI12_Msk (0x1U << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 7537 #define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
<> 128:9bcdf88f62b0 7538 #define EXTI_SWIER1_SWI13_Pos (13U)
<> 128:9bcdf88f62b0 7539 #define EXTI_SWIER1_SWI13_Msk (0x1U << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 7540 #define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
<> 128:9bcdf88f62b0 7541 #define EXTI_SWIER1_SWI14_Pos (14U)
<> 128:9bcdf88f62b0 7542 #define EXTI_SWIER1_SWI14_Msk (0x1U << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 7543 #define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
<> 128:9bcdf88f62b0 7544 #define EXTI_SWIER1_SWI15_Pos (15U)
<> 128:9bcdf88f62b0 7545 #define EXTI_SWIER1_SWI15_Msk (0x1U << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 7546 #define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
<> 128:9bcdf88f62b0 7547 #define EXTI_SWIER1_SWI16_Pos (16U)
<> 128:9bcdf88f62b0 7548 #define EXTI_SWIER1_SWI16_Msk (0x1U << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 7549 #define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
<> 128:9bcdf88f62b0 7550 #define EXTI_SWIER1_SWI18_Pos (18U)
<> 128:9bcdf88f62b0 7551 #define EXTI_SWIER1_SWI18_Msk (0x1U << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 7552 #define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */
<> 128:9bcdf88f62b0 7553 #define EXTI_SWIER1_SWI19_Pos (19U)
<> 128:9bcdf88f62b0 7554 #define EXTI_SWIER1_SWI19_Msk (0x1U << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 7555 #define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
<> 128:9bcdf88f62b0 7556 #define EXTI_SWIER1_SWI20_Pos (20U)
<> 128:9bcdf88f62b0 7557 #define EXTI_SWIER1_SWI20_Msk (0x1U << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 7558 #define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
<> 128:9bcdf88f62b0 7559 #define EXTI_SWIER1_SWI21_Pos (21U)
<> 128:9bcdf88f62b0 7560 #define EXTI_SWIER1_SWI21_Msk (0x1U << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 7561 #define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
<> 128:9bcdf88f62b0 7562 #define EXTI_SWIER1_SWI22_Pos (22U)
<> 128:9bcdf88f62b0 7563 #define EXTI_SWIER1_SWI22_Msk (0x1U << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 7564 #define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
<> 128:9bcdf88f62b0 7565
<> 128:9bcdf88f62b0 7566 /******************* Bit definition for EXTI_PR1 register *******************/
<> 128:9bcdf88f62b0 7567 #define EXTI_PR1_PIF0_Pos (0U)
<> 128:9bcdf88f62b0 7568 #define EXTI_PR1_PIF0_Msk (0x1U << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 7569 #define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
<> 128:9bcdf88f62b0 7570 #define EXTI_PR1_PIF1_Pos (1U)
<> 128:9bcdf88f62b0 7571 #define EXTI_PR1_PIF1_Msk (0x1U << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 7572 #define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
<> 128:9bcdf88f62b0 7573 #define EXTI_PR1_PIF2_Pos (2U)
<> 128:9bcdf88f62b0 7574 #define EXTI_PR1_PIF2_Msk (0x1U << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 7575 #define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
<> 128:9bcdf88f62b0 7576 #define EXTI_PR1_PIF3_Pos (3U)
<> 128:9bcdf88f62b0 7577 #define EXTI_PR1_PIF3_Msk (0x1U << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 7578 #define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
<> 128:9bcdf88f62b0 7579 #define EXTI_PR1_PIF4_Pos (4U)
<> 128:9bcdf88f62b0 7580 #define EXTI_PR1_PIF4_Msk (0x1U << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 7581 #define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
<> 128:9bcdf88f62b0 7582 #define EXTI_PR1_PIF5_Pos (5U)
<> 128:9bcdf88f62b0 7583 #define EXTI_PR1_PIF5_Msk (0x1U << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 7584 #define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
<> 128:9bcdf88f62b0 7585 #define EXTI_PR1_PIF6_Pos (6U)
<> 128:9bcdf88f62b0 7586 #define EXTI_PR1_PIF6_Msk (0x1U << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 7587 #define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
<> 128:9bcdf88f62b0 7588 #define EXTI_PR1_PIF7_Pos (7U)
<> 128:9bcdf88f62b0 7589 #define EXTI_PR1_PIF7_Msk (0x1U << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 7590 #define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
<> 128:9bcdf88f62b0 7591 #define EXTI_PR1_PIF8_Pos (8U)
<> 128:9bcdf88f62b0 7592 #define EXTI_PR1_PIF8_Msk (0x1U << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 7593 #define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
<> 128:9bcdf88f62b0 7594 #define EXTI_PR1_PIF9_Pos (9U)
<> 128:9bcdf88f62b0 7595 #define EXTI_PR1_PIF9_Msk (0x1U << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 7596 #define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
<> 128:9bcdf88f62b0 7597 #define EXTI_PR1_PIF10_Pos (10U)
<> 128:9bcdf88f62b0 7598 #define EXTI_PR1_PIF10_Msk (0x1U << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 7599 #define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
<> 128:9bcdf88f62b0 7600 #define EXTI_PR1_PIF11_Pos (11U)
<> 128:9bcdf88f62b0 7601 #define EXTI_PR1_PIF11_Msk (0x1U << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 7602 #define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
<> 128:9bcdf88f62b0 7603 #define EXTI_PR1_PIF12_Pos (12U)
<> 128:9bcdf88f62b0 7604 #define EXTI_PR1_PIF12_Msk (0x1U << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 7605 #define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
<> 128:9bcdf88f62b0 7606 #define EXTI_PR1_PIF13_Pos (13U)
<> 128:9bcdf88f62b0 7607 #define EXTI_PR1_PIF13_Msk (0x1U << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 7608 #define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
<> 128:9bcdf88f62b0 7609 #define EXTI_PR1_PIF14_Pos (14U)
<> 128:9bcdf88f62b0 7610 #define EXTI_PR1_PIF14_Msk (0x1U << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 7611 #define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
<> 128:9bcdf88f62b0 7612 #define EXTI_PR1_PIF15_Pos (15U)
<> 128:9bcdf88f62b0 7613 #define EXTI_PR1_PIF15_Msk (0x1U << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 7614 #define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
<> 128:9bcdf88f62b0 7615 #define EXTI_PR1_PIF16_Pos (16U)
<> 128:9bcdf88f62b0 7616 #define EXTI_PR1_PIF16_Msk (0x1U << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 7617 #define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
<> 128:9bcdf88f62b0 7618 #define EXTI_PR1_PIF18_Pos (18U)
<> 128:9bcdf88f62b0 7619 #define EXTI_PR1_PIF18_Msk (0x1U << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 7620 #define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */
<> 128:9bcdf88f62b0 7621 #define EXTI_PR1_PIF19_Pos (19U)
<> 128:9bcdf88f62b0 7622 #define EXTI_PR1_PIF19_Msk (0x1U << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 7623 #define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
<> 128:9bcdf88f62b0 7624 #define EXTI_PR1_PIF20_Pos (20U)
<> 128:9bcdf88f62b0 7625 #define EXTI_PR1_PIF20_Msk (0x1U << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 7626 #define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
<> 128:9bcdf88f62b0 7627 #define EXTI_PR1_PIF21_Pos (21U)
<> 128:9bcdf88f62b0 7628 #define EXTI_PR1_PIF21_Msk (0x1U << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 7629 #define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
<> 128:9bcdf88f62b0 7630 #define EXTI_PR1_PIF22_Pos (22U)
<> 128:9bcdf88f62b0 7631 #define EXTI_PR1_PIF22_Msk (0x1U << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 7632 #define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
<> 128:9bcdf88f62b0 7633
<> 128:9bcdf88f62b0 7634 /******************* Bit definition for EXTI_IMR2 register ******************/
<> 128:9bcdf88f62b0 7635 #define EXTI_IMR2_IM32_Pos (0U)
<> 128:9bcdf88f62b0 7636 #define EXTI_IMR2_IM32_Msk (0x1U << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 7637 #define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
<> 128:9bcdf88f62b0 7638 #define EXTI_IMR2_IM33_Pos (1U)
<> 128:9bcdf88f62b0 7639 #define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 7640 #define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
<> 128:9bcdf88f62b0 7641 #define EXTI_IMR2_IM34_Pos (2U)
<> 128:9bcdf88f62b0 7642 #define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 7643 #define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
<> 128:9bcdf88f62b0 7644 #define EXTI_IMR2_IM35_Pos (3U)
<> 128:9bcdf88f62b0 7645 #define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 7646 #define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
<> 128:9bcdf88f62b0 7647 #define EXTI_IMR2_IM36_Pos (4U)
<> 128:9bcdf88f62b0 7648 #define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 7649 #define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
<> 128:9bcdf88f62b0 7650 #define EXTI_IMR2_IM37_Pos (5U)
<> 128:9bcdf88f62b0 7651 #define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 7652 #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
<> 128:9bcdf88f62b0 7653 #define EXTI_IMR2_IM38_Pos (6U)
<> 128:9bcdf88f62b0 7654 #define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 7655 #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
<> 128:9bcdf88f62b0 7656 #define EXTI_IMR2_IM39_Pos (7U)
<> 128:9bcdf88f62b0 7657 #define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 7658 #define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
<> 128:9bcdf88f62b0 7659 #define EXTI_IMR2_IM_Pos (0U)
<> 128:9bcdf88f62b0 7660 #define EXTI_IMR2_IM_Msk (0xFFU << EXTI_IMR2_IM_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 7661 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
<> 128:9bcdf88f62b0 7662
<> 128:9bcdf88f62b0 7663 /******************* Bit definition for EXTI_EMR2 register ******************/
<> 128:9bcdf88f62b0 7664 #define EXTI_EMR2_EM32_Pos (0U)
<> 128:9bcdf88f62b0 7665 #define EXTI_EMR2_EM32_Msk (0x1U << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 7666 #define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */
<> 128:9bcdf88f62b0 7667 #define EXTI_EMR2_EM33_Pos (1U)
<> 128:9bcdf88f62b0 7668 #define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 7669 #define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
<> 128:9bcdf88f62b0 7670 #define EXTI_EMR2_EM34_Pos (2U)
<> 128:9bcdf88f62b0 7671 #define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 7672 #define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
<> 128:9bcdf88f62b0 7673 #define EXTI_EMR2_EM35_Pos (3U)
<> 128:9bcdf88f62b0 7674 #define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 7675 #define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
<> 128:9bcdf88f62b0 7676 #define EXTI_EMR2_EM36_Pos (4U)
<> 128:9bcdf88f62b0 7677 #define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 7678 #define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
<> 128:9bcdf88f62b0 7679 #define EXTI_EMR2_EM37_Pos (5U)
<> 128:9bcdf88f62b0 7680 #define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 7681 #define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
<> 128:9bcdf88f62b0 7682 #define EXTI_EMR2_EM38_Pos (6U)
<> 128:9bcdf88f62b0 7683 #define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 7684 #define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
<> 128:9bcdf88f62b0 7685 #define EXTI_EMR2_EM39_Pos (7U)
<> 128:9bcdf88f62b0 7686 #define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 7687 #define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
<> 128:9bcdf88f62b0 7688
<> 128:9bcdf88f62b0 7689 /****************** Bit definition for EXTI_RTSR2 register ******************/
<> 128:9bcdf88f62b0 7690 #define EXTI_RTSR2_RT35_Pos (3U)
<> 128:9bcdf88f62b0 7691 #define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 7692 #define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
<> 128:9bcdf88f62b0 7693 #define EXTI_RTSR2_RT36_Pos (4U)
<> 128:9bcdf88f62b0 7694 #define EXTI_RTSR2_RT36_Msk (0x1U << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 7695 #define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of line 36 */
<> 128:9bcdf88f62b0 7696 #define EXTI_RTSR2_RT37_Pos (5U)
<> 128:9bcdf88f62b0 7697 #define EXTI_RTSR2_RT37_Msk (0x1U << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 7698 #define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */
<> 128:9bcdf88f62b0 7699 #define EXTI_RTSR2_RT38_Pos (6U)
<> 128:9bcdf88f62b0 7700 #define EXTI_RTSR2_RT38_Msk (0x1U << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 7701 #define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
<> 128:9bcdf88f62b0 7702
<> 128:9bcdf88f62b0 7703 /****************** Bit definition for EXTI_FTSR2 register ******************/
<> 128:9bcdf88f62b0 7704 #define EXTI_FTSR2_FT35_Pos (3U)
<> 128:9bcdf88f62b0 7705 #define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 7706 #define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
<> 128:9bcdf88f62b0 7707 #define EXTI_FTSR2_FT36_Pos (4U)
<> 128:9bcdf88f62b0 7708 #define EXTI_FTSR2_FT36_Msk (0x1U << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 7709 #define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of line 36 */
<> 128:9bcdf88f62b0 7710 #define EXTI_FTSR2_FT37_Pos (5U)
<> 128:9bcdf88f62b0 7711 #define EXTI_FTSR2_FT37_Msk (0x1U << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 7712 #define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */
<> 128:9bcdf88f62b0 7713 #define EXTI_FTSR2_FT38_Pos (6U)
<> 128:9bcdf88f62b0 7714 #define EXTI_FTSR2_FT38_Msk (0x1U << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 7715 #define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 38 */
<> 128:9bcdf88f62b0 7716
<> 128:9bcdf88f62b0 7717 /****************** Bit definition for EXTI_SWIER2 register *****************/
<> 128:9bcdf88f62b0 7718 #define EXTI_SWIER2_SWI35_Pos (3U)
<> 128:9bcdf88f62b0 7719 #define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 7720 #define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
<> 128:9bcdf88f62b0 7721 #define EXTI_SWIER2_SWI36_Pos (4U)
<> 128:9bcdf88f62b0 7722 #define EXTI_SWIER2_SWI36_Msk (0x1U << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 7723 #define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on line 36 */
<> 128:9bcdf88f62b0 7724 #define EXTI_SWIER2_SWI37_Pos (5U)
<> 128:9bcdf88f62b0 7725 #define EXTI_SWIER2_SWI37_Msk (0x1U << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 7726 #define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
<> 128:9bcdf88f62b0 7727 #define EXTI_SWIER2_SWI38_Pos (6U)
<> 128:9bcdf88f62b0 7728 #define EXTI_SWIER2_SWI38_Msk (0x1U << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 7729 #define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
<> 128:9bcdf88f62b0 7730
<> 128:9bcdf88f62b0 7731 /******************* Bit definition for EXTI_PR2 register *******************/
<> 128:9bcdf88f62b0 7732 #define EXTI_PR2_PIF35_Pos (3U)
<> 128:9bcdf88f62b0 7733 #define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 7734 #define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
<> 128:9bcdf88f62b0 7735 #define EXTI_PR2_PIF36_Pos (4U)
<> 128:9bcdf88f62b0 7736 #define EXTI_PR2_PIF36_Msk (0x1U << EXTI_PR2_PIF36_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 7737 #define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk /*!< Pending bit for line 36 */
<> 128:9bcdf88f62b0 7738 #define EXTI_PR2_PIF37_Pos (5U)
<> 128:9bcdf88f62b0 7739 #define EXTI_PR2_PIF37_Msk (0x1U << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 7740 #define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */
<> 128:9bcdf88f62b0 7741 #define EXTI_PR2_PIF38_Pos (6U)
<> 128:9bcdf88f62b0 7742 #define EXTI_PR2_PIF38_Msk (0x1U << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 7743 #define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
<> 128:9bcdf88f62b0 7744
<> 128:9bcdf88f62b0 7745
<> 128:9bcdf88f62b0 7746 /******************************************************************************/
<> 128:9bcdf88f62b0 7747 /* */
<> 128:9bcdf88f62b0 7748 /* FLASH */
<> 128:9bcdf88f62b0 7749 /* */
<> 128:9bcdf88f62b0 7750 /******************************************************************************/
<> 128:9bcdf88f62b0 7751 /******************* Bits definition for FLASH_ACR register *****************/
<> 128:9bcdf88f62b0 7752 #define FLASH_ACR_LATENCY_Pos (0U)
<> 128:9bcdf88f62b0 7753 #define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
<> 128:9bcdf88f62b0 7754 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
<> 128:9bcdf88f62b0 7755 #define FLASH_ACR_LATENCY_0WS (0x00000000U)
<> 128:9bcdf88f62b0 7756 #define FLASH_ACR_LATENCY_1WS (0x00000001U)
<> 128:9bcdf88f62b0 7757 #define FLASH_ACR_LATENCY_2WS (0x00000002U)
<> 128:9bcdf88f62b0 7758 #define FLASH_ACR_LATENCY_3WS (0x00000003U)
<> 128:9bcdf88f62b0 7759 #define FLASH_ACR_LATENCY_4WS (0x00000004U)
<> 128:9bcdf88f62b0 7760 #define FLASH_ACR_PRFTEN_Pos (8U)
<> 128:9bcdf88f62b0 7761 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 7762 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
<> 128:9bcdf88f62b0 7763 #define FLASH_ACR_ICEN_Pos (9U)
<> 128:9bcdf88f62b0 7764 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 7765 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
<> 128:9bcdf88f62b0 7766 #define FLASH_ACR_DCEN_Pos (10U)
<> 128:9bcdf88f62b0 7767 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 7768 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
<> 128:9bcdf88f62b0 7769 #define FLASH_ACR_ICRST_Pos (11U)
<> 128:9bcdf88f62b0 7770 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 7771 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
<> 128:9bcdf88f62b0 7772 #define FLASH_ACR_DCRST_Pos (12U)
<> 128:9bcdf88f62b0 7773 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 7774 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
<> 128:9bcdf88f62b0 7775 #define FLASH_ACR_RUN_PD_Pos (13U)
<> 128:9bcdf88f62b0 7776 #define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 7777 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
<> 128:9bcdf88f62b0 7778 #define FLASH_ACR_SLEEP_PD_Pos (14U)
<> 128:9bcdf88f62b0 7779 #define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 7780 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
<> 128:9bcdf88f62b0 7781
<> 128:9bcdf88f62b0 7782 /******************* Bits definition for FLASH_SR register ******************/
<> 128:9bcdf88f62b0 7783 #define FLASH_SR_EOP_Pos (0U)
<> 128:9bcdf88f62b0 7784 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 7785 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
<> 128:9bcdf88f62b0 7786 #define FLASH_SR_OPERR_Pos (1U)
<> 128:9bcdf88f62b0 7787 #define FLASH_SR_OPERR_Msk (0x1U << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 7788 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
<> 128:9bcdf88f62b0 7789 #define FLASH_SR_PROGERR_Pos (3U)
<> 128:9bcdf88f62b0 7790 #define FLASH_SR_PROGERR_Msk (0x1U << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 7791 #define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
<> 128:9bcdf88f62b0 7792 #define FLASH_SR_WRPERR_Pos (4U)
<> 128:9bcdf88f62b0 7793 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 7794 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
<> 128:9bcdf88f62b0 7795 #define FLASH_SR_PGAERR_Pos (5U)
<> 128:9bcdf88f62b0 7796 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 7797 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
<> 128:9bcdf88f62b0 7798 #define FLASH_SR_SIZERR_Pos (6U)
<> 128:9bcdf88f62b0 7799 #define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 7800 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
<> 128:9bcdf88f62b0 7801 #define FLASH_SR_PGSERR_Pos (7U)
<> 128:9bcdf88f62b0 7802 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 7803 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
<> 128:9bcdf88f62b0 7804 #define FLASH_SR_MISERR_Pos (8U)
<> 128:9bcdf88f62b0 7805 #define FLASH_SR_MISERR_Msk (0x1U << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 7806 #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
<> 128:9bcdf88f62b0 7807 #define FLASH_SR_FASTERR_Pos (9U)
<> 128:9bcdf88f62b0 7808 #define FLASH_SR_FASTERR_Msk (0x1U << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 7809 #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
<> 128:9bcdf88f62b0 7810 #define FLASH_SR_RDERR_Pos (14U)
<> 128:9bcdf88f62b0 7811 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 7812 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
<> 128:9bcdf88f62b0 7813 #define FLASH_SR_OPTVERR_Pos (15U)
<> 128:9bcdf88f62b0 7814 #define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 7815 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
<> 128:9bcdf88f62b0 7816 #define FLASH_SR_BSY_Pos (16U)
<> 128:9bcdf88f62b0 7817 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 7818 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
<> 128:9bcdf88f62b0 7819
<> 128:9bcdf88f62b0 7820 /******************* Bits definition for FLASH_CR register ******************/
<> 128:9bcdf88f62b0 7821 #define FLASH_CR_PG_Pos (0U)
<> 128:9bcdf88f62b0 7822 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 7823 #define FLASH_CR_PG FLASH_CR_PG_Msk
<> 128:9bcdf88f62b0 7824 #define FLASH_CR_PER_Pos (1U)
<> 128:9bcdf88f62b0 7825 #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 7826 #define FLASH_CR_PER FLASH_CR_PER_Msk
<> 128:9bcdf88f62b0 7827 #define FLASH_CR_MER1_Pos (2U)
<> 128:9bcdf88f62b0 7828 #define FLASH_CR_MER1_Msk (0x1U << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 7829 #define FLASH_CR_MER1 FLASH_CR_MER1_Msk
<> 128:9bcdf88f62b0 7830 #define FLASH_CR_PNB_Pos (3U)
<> 128:9bcdf88f62b0 7831 #define FLASH_CR_PNB_Msk (0xFFU << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */
<> 128:9bcdf88f62b0 7832 #define FLASH_CR_PNB FLASH_CR_PNB_Msk
<> 128:9bcdf88f62b0 7833 #define FLASH_CR_BKER_Pos (11U)
<> 128:9bcdf88f62b0 7834 #define FLASH_CR_BKER_Msk (0x1U << FLASH_CR_BKER_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 7835 #define FLASH_CR_BKER FLASH_CR_BKER_Msk
<> 128:9bcdf88f62b0 7836 #define FLASH_CR_MER2_Pos (15U)
<> 128:9bcdf88f62b0 7837 #define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 7838 #define FLASH_CR_MER2 FLASH_CR_MER2_Msk
<> 128:9bcdf88f62b0 7839 #define FLASH_CR_STRT_Pos (16U)
<> 128:9bcdf88f62b0 7840 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 7841 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
<> 128:9bcdf88f62b0 7842 #define FLASH_CR_OPTSTRT_Pos (17U)
<> 128:9bcdf88f62b0 7843 #define FLASH_CR_OPTSTRT_Msk (0x1U << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 7844 #define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
<> 128:9bcdf88f62b0 7845 #define FLASH_CR_FSTPG_Pos (18U)
<> 128:9bcdf88f62b0 7846 #define FLASH_CR_FSTPG_Msk (0x1U << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 7847 #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
<> 128:9bcdf88f62b0 7848 #define FLASH_CR_EOPIE_Pos (24U)
<> 128:9bcdf88f62b0 7849 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 7850 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
<> 128:9bcdf88f62b0 7851 #define FLASH_CR_ERRIE_Pos (25U)
<> 128:9bcdf88f62b0 7852 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 7853 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
<> 128:9bcdf88f62b0 7854 #define FLASH_CR_RDERRIE_Pos (26U)
<> 128:9bcdf88f62b0 7855 #define FLASH_CR_RDERRIE_Msk (0x1U << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 7856 #define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
<> 128:9bcdf88f62b0 7857 #define FLASH_CR_OBL_LAUNCH_Pos (27U)
<> 128:9bcdf88f62b0 7858 #define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 7859 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
<> 128:9bcdf88f62b0 7860 #define FLASH_CR_OPTLOCK_Pos (30U)
<> 128:9bcdf88f62b0 7861 #define FLASH_CR_OPTLOCK_Msk (0x1U << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 7862 #define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
<> 128:9bcdf88f62b0 7863 #define FLASH_CR_LOCK_Pos (31U)
<> 128:9bcdf88f62b0 7864 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 7865 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
<> 128:9bcdf88f62b0 7866
<> 128:9bcdf88f62b0 7867 /******************* Bits definition for FLASH_ECCR register ***************/
<> 128:9bcdf88f62b0 7868 #define FLASH_ECCR_ADDR_ECC_Pos (0U)
<> 128:9bcdf88f62b0 7869 #define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
<> 128:9bcdf88f62b0 7870 #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
<> 128:9bcdf88f62b0 7871 #define FLASH_ECCR_BK_ECC_Pos (19U)
<> 128:9bcdf88f62b0 7872 #define FLASH_ECCR_BK_ECC_Msk (0x1U << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 7873 #define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk
<> 128:9bcdf88f62b0 7874 #define FLASH_ECCR_SYSF_ECC_Pos (20U)
<> 128:9bcdf88f62b0 7875 #define FLASH_ECCR_SYSF_ECC_Msk (0x1U << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 7876 #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
<> 128:9bcdf88f62b0 7877 #define FLASH_ECCR_ECCIE_Pos (24U)
<> 128:9bcdf88f62b0 7878 #define FLASH_ECCR_ECCIE_Msk (0x1U << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 7879 #define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
<> 128:9bcdf88f62b0 7880 #define FLASH_ECCR_ECCC_Pos (30U)
<> 128:9bcdf88f62b0 7881 #define FLASH_ECCR_ECCC_Msk (0x1U << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 7882 #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
<> 128:9bcdf88f62b0 7883 #define FLASH_ECCR_ECCD_Pos (31U)
<> 128:9bcdf88f62b0 7884 #define FLASH_ECCR_ECCD_Msk (0x1U << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 7885 #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
<> 128:9bcdf88f62b0 7886
<> 128:9bcdf88f62b0 7887 /******************* Bits definition for FLASH_OPTR register ***************/
<> 128:9bcdf88f62b0 7888 #define FLASH_OPTR_RDP_Pos (0U)
<> 128:9bcdf88f62b0 7889 #define FLASH_OPTR_RDP_Msk (0xFFU << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 7890 #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
<> 128:9bcdf88f62b0 7891 #define FLASH_OPTR_BOR_LEV_Pos (8U)
<> 128:9bcdf88f62b0 7892 #define FLASH_OPTR_BOR_LEV_Msk (0x7U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
<> 128:9bcdf88f62b0 7893 #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
<> 128:9bcdf88f62b0 7894 #define FLASH_OPTR_BOR_LEV_0 (0x0U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
<> 128:9bcdf88f62b0 7895 #define FLASH_OPTR_BOR_LEV_1 (0x1U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 7896 #define FLASH_OPTR_BOR_LEV_2 (0x2U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 7897 #define FLASH_OPTR_BOR_LEV_3 (0x3U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
<> 128:9bcdf88f62b0 7898 #define FLASH_OPTR_BOR_LEV_4 (0x4U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 7899 #define FLASH_OPTR_nRST_STOP_Pos (12U)
<> 128:9bcdf88f62b0 7900 #define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 7901 #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
<> 128:9bcdf88f62b0 7902 #define FLASH_OPTR_nRST_STDBY_Pos (13U)
<> 128:9bcdf88f62b0 7903 #define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 7904 #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
<> 128:9bcdf88f62b0 7905 #define FLASH_OPTR_nRST_SHDW_Pos (14U)
<> 128:9bcdf88f62b0 7906 #define FLASH_OPTR_nRST_SHDW_Msk (0x1U << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 7907 #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
<> 128:9bcdf88f62b0 7908 #define FLASH_OPTR_IWDG_SW_Pos (16U)
<> 128:9bcdf88f62b0 7909 #define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 7910 #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
<> 128:9bcdf88f62b0 7911 #define FLASH_OPTR_IWDG_STOP_Pos (17U)
<> 128:9bcdf88f62b0 7912 #define FLASH_OPTR_IWDG_STOP_Msk (0x1U << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 7913 #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
<> 128:9bcdf88f62b0 7914 #define FLASH_OPTR_IWDG_STDBY_Pos (18U)
<> 128:9bcdf88f62b0 7915 #define FLASH_OPTR_IWDG_STDBY_Msk (0x1U << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 7916 #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
<> 128:9bcdf88f62b0 7917 #define FLASH_OPTR_WWDG_SW_Pos (19U)
<> 128:9bcdf88f62b0 7918 #define FLASH_OPTR_WWDG_SW_Msk (0x1U << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 7919 #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
<> 128:9bcdf88f62b0 7920 #define FLASH_OPTR_BFB2_Pos (20U)
<> 128:9bcdf88f62b0 7921 #define FLASH_OPTR_BFB2_Msk (0x1U << FLASH_OPTR_BFB2_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 7922 #define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk
<> 128:9bcdf88f62b0 7923 #define FLASH_OPTR_DUALBANK_Pos (21U)
<> 128:9bcdf88f62b0 7924 #define FLASH_OPTR_DUALBANK_Msk (0x1U << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 7925 #define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk
<> 128:9bcdf88f62b0 7926 #define FLASH_OPTR_nBOOT1_Pos (23U)
<> 128:9bcdf88f62b0 7927 #define FLASH_OPTR_nBOOT1_Msk (0x1U << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 7928 #define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
<> 128:9bcdf88f62b0 7929 #define FLASH_OPTR_SRAM2_PE_Pos (24U)
<> 128:9bcdf88f62b0 7930 #define FLASH_OPTR_SRAM2_PE_Msk (0x1U << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 7931 #define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk
<> 128:9bcdf88f62b0 7932 #define FLASH_OPTR_SRAM2_RST_Pos (25U)
<> 128:9bcdf88f62b0 7933 #define FLASH_OPTR_SRAM2_RST_Msk (0x1U << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 7934 #define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk
<> 128:9bcdf88f62b0 7935
<> 128:9bcdf88f62b0 7936 /****************** Bits definition for FLASH_PCROP1SR register **********/
<> 128:9bcdf88f62b0 7937 #define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
<> 128:9bcdf88f62b0 7938 #define FLASH_PCROP1SR_PCROP1_STRT_Msk (0xFFFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 7939 #define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
<> 128:9bcdf88f62b0 7940
<> 128:9bcdf88f62b0 7941 /****************** Bits definition for FLASH_PCROP1ER register ***********/
<> 128:9bcdf88f62b0 7942 #define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
<> 128:9bcdf88f62b0 7943 #define FLASH_PCROP1ER_PCROP1_END_Msk (0xFFFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 7944 #define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
<> 128:9bcdf88f62b0 7945 #define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
<> 128:9bcdf88f62b0 7946 #define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 7947 #define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
<> 128:9bcdf88f62b0 7948
<> 128:9bcdf88f62b0 7949 /****************** Bits definition for FLASH_WRP1AR register ***************/
<> 128:9bcdf88f62b0 7950 #define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
<> 128:9bcdf88f62b0 7951 #define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 7952 #define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
<> 128:9bcdf88f62b0 7953 #define FLASH_WRP1AR_WRP1A_END_Pos (16U)
<> 128:9bcdf88f62b0 7954 #define FLASH_WRP1AR_WRP1A_END_Msk (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 7955 #define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
<> 128:9bcdf88f62b0 7956
<> 128:9bcdf88f62b0 7957 /****************** Bits definition for FLASH_WRPB1R register ***************/
<> 128:9bcdf88f62b0 7958 #define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
<> 128:9bcdf88f62b0 7959 #define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 7960 #define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
<> 128:9bcdf88f62b0 7961 #define FLASH_WRP1BR_WRP1B_END_Pos (16U)
<> 128:9bcdf88f62b0 7962 #define FLASH_WRP1BR_WRP1B_END_Msk (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 7963 #define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
<> 128:9bcdf88f62b0 7964
<> 128:9bcdf88f62b0 7965 /****************** Bits definition for FLASH_PCROP2SR register **********/
<> 128:9bcdf88f62b0 7966 #define FLASH_PCROP2SR_PCROP2_STRT_Pos (0U)
<> 128:9bcdf88f62b0 7967 #define FLASH_PCROP2SR_PCROP2_STRT_Msk (0xFFFFU << FLASH_PCROP2SR_PCROP2_STRT_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 7968 #define FLASH_PCROP2SR_PCROP2_STRT FLASH_PCROP2SR_PCROP2_STRT_Msk
<> 128:9bcdf88f62b0 7969
<> 128:9bcdf88f62b0 7970 /****************** Bits definition for FLASH_PCROP2ER register ***********/
<> 128:9bcdf88f62b0 7971 #define FLASH_PCROP2ER_PCROP2_END_Pos (0U)
<> 128:9bcdf88f62b0 7972 #define FLASH_PCROP2ER_PCROP2_END_Msk (0xFFFFU << FLASH_PCROP2ER_PCROP2_END_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 7973 #define FLASH_PCROP2ER_PCROP2_END FLASH_PCROP2ER_PCROP2_END_Msk
<> 128:9bcdf88f62b0 7974
<> 128:9bcdf88f62b0 7975 /****************** Bits definition for FLASH_WRP2AR register ***************/
<> 128:9bcdf88f62b0 7976 #define FLASH_WRP2AR_WRP2A_STRT_Pos (0U)
<> 128:9bcdf88f62b0 7977 #define FLASH_WRP2AR_WRP2A_STRT_Msk (0xFFU << FLASH_WRP2AR_WRP2A_STRT_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 7978 #define FLASH_WRP2AR_WRP2A_STRT FLASH_WRP2AR_WRP2A_STRT_Msk
<> 128:9bcdf88f62b0 7979 #define FLASH_WRP2AR_WRP2A_END_Pos (16U)
<> 128:9bcdf88f62b0 7980 #define FLASH_WRP2AR_WRP2A_END_Msk (0xFFU << FLASH_WRP2AR_WRP2A_END_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 7981 #define FLASH_WRP2AR_WRP2A_END FLASH_WRP2AR_WRP2A_END_Msk
<> 128:9bcdf88f62b0 7982
<> 128:9bcdf88f62b0 7983 /****************** Bits definition for FLASH_WRP2BR register ***************/
<> 128:9bcdf88f62b0 7984 #define FLASH_WRP2BR_WRP2B_STRT_Pos (0U)
<> 128:9bcdf88f62b0 7985 #define FLASH_WRP2BR_WRP2B_STRT_Msk (0xFFU << FLASH_WRP2BR_WRP2B_STRT_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 7986 #define FLASH_WRP2BR_WRP2B_STRT FLASH_WRP2BR_WRP2B_STRT_Msk
<> 128:9bcdf88f62b0 7987 #define FLASH_WRP2BR_WRP2B_END_Pos (16U)
<> 128:9bcdf88f62b0 7988 #define FLASH_WRP2BR_WRP2B_END_Msk (0xFFU << FLASH_WRP2BR_WRP2B_END_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 7989 #define FLASH_WRP2BR_WRP2B_END FLASH_WRP2BR_WRP2B_END_Msk
<> 128:9bcdf88f62b0 7990
<> 128:9bcdf88f62b0 7991
<> 128:9bcdf88f62b0 7992 /******************************************************************************/
<> 128:9bcdf88f62b0 7993 /* */
<> 128:9bcdf88f62b0 7994 /* Flexible Memory Controller */
<> 128:9bcdf88f62b0 7995 /* */
<> 128:9bcdf88f62b0 7996 /******************************************************************************/
<> 128:9bcdf88f62b0 7997 /****************** Bit definition for FMC_BCR1 register *******************/
<> 128:9bcdf88f62b0 7998 #define FMC_BCR1_CCLKEN_Pos (20U)
<> 128:9bcdf88f62b0 7999 #define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 8000 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
<> 128:9bcdf88f62b0 8001
<> 128:9bcdf88f62b0 8002 /****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
<> 128:9bcdf88f62b0 8003 #define FMC_BCRx_MBKEN_Pos (0U)
<> 128:9bcdf88f62b0 8004 #define FMC_BCRx_MBKEN_Msk (0x1U << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 8005 #define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
<> 128:9bcdf88f62b0 8006 #define FMC_BCRx_MUXEN_Pos (1U)
<> 128:9bcdf88f62b0 8007 #define FMC_BCRx_MUXEN_Msk (0x1U << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 8008 #define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
<> 128:9bcdf88f62b0 8009
<> 128:9bcdf88f62b0 8010 #define FMC_BCRx_MTYP_Pos (2U)
<> 128:9bcdf88f62b0 8011 #define FMC_BCRx_MTYP_Msk (0x3U << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
<> 128:9bcdf88f62b0 8012 #define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
<> 128:9bcdf88f62b0 8013 #define FMC_BCRx_MTYP_0 (0x1U << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 8014 #define FMC_BCRx_MTYP_1 (0x2U << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 8015
<> 128:9bcdf88f62b0 8016 #define FMC_BCRx_MWID_Pos (4U)
<> 128:9bcdf88f62b0 8017 #define FMC_BCRx_MWID_Msk (0x3U << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
<> 128:9bcdf88f62b0 8018 #define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
<> 128:9bcdf88f62b0 8019 #define FMC_BCRx_MWID_0 (0x1U << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 8020 #define FMC_BCRx_MWID_1 (0x2U << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 8021
<> 128:9bcdf88f62b0 8022 #define FMC_BCRx_FACCEN_Pos (6U)
<> 128:9bcdf88f62b0 8023 #define FMC_BCRx_FACCEN_Msk (0x1U << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 8024 #define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
<> 128:9bcdf88f62b0 8025 #define FMC_BCRx_BURSTEN_Pos (8U)
<> 128:9bcdf88f62b0 8026 #define FMC_BCRx_BURSTEN_Msk (0x1U << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 8027 #define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
<> 128:9bcdf88f62b0 8028 #define FMC_BCRx_WAITPOL_Pos (9U)
<> 128:9bcdf88f62b0 8029 #define FMC_BCRx_WAITPOL_Msk (0x1U << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 8030 #define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
<> 128:9bcdf88f62b0 8031 #define FMC_BCRx_WAITCFG_Pos (11U)
<> 128:9bcdf88f62b0 8032 #define FMC_BCRx_WAITCFG_Msk (0x1U << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 8033 #define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
<> 128:9bcdf88f62b0 8034 #define FMC_BCRx_WREN_Pos (12U)
<> 128:9bcdf88f62b0 8035 #define FMC_BCRx_WREN_Msk (0x1U << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 8036 #define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
<> 128:9bcdf88f62b0 8037 #define FMC_BCRx_WAITEN_Pos (13U)
<> 128:9bcdf88f62b0 8038 #define FMC_BCRx_WAITEN_Msk (0x1U << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 8039 #define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
<> 128:9bcdf88f62b0 8040 #define FMC_BCRx_EXTMOD_Pos (14U)
<> 128:9bcdf88f62b0 8041 #define FMC_BCRx_EXTMOD_Msk (0x1U << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 8042 #define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
<> 128:9bcdf88f62b0 8043 #define FMC_BCRx_ASYNCWAIT_Pos (15U)
<> 128:9bcdf88f62b0 8044 #define FMC_BCRx_ASYNCWAIT_Msk (0x1U << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 8045 #define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
<> 128:9bcdf88f62b0 8046
<> 128:9bcdf88f62b0 8047 #define FMC_BCRx_CPSIZE_Pos (16U)
<> 128:9bcdf88f62b0 8048 #define FMC_BCRx_CPSIZE_Msk (0x7U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
<> 128:9bcdf88f62b0 8049 #define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<CRAM page size */
<> 128:9bcdf88f62b0 8050 #define FMC_BCRx_CPSIZE_0 (0x1U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 8051 #define FMC_BCRx_CPSIZE_1 (0x2U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 8052 #define FMC_BCRx_CPSIZE_2 (0x4U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 8053
<> 128:9bcdf88f62b0 8054 #define FMC_BCRx_CBURSTRW_Pos (19U)
<> 128:9bcdf88f62b0 8055 #define FMC_BCRx_CBURSTRW_Msk (0x1U << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 8056 #define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
<> 128:9bcdf88f62b0 8057
<> 128:9bcdf88f62b0 8058 /****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
<> 128:9bcdf88f62b0 8059 #define FMC_BTRx_ADDSET_Pos (0U)
<> 128:9bcdf88f62b0 8060 #define FMC_BTRx_ADDSET_Msk (0xFU << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 8061 #define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 128:9bcdf88f62b0 8062 #define FMC_BTRx_ADDSET_0 (0x1U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 8063 #define FMC_BTRx_ADDSET_1 (0x2U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 8064 #define FMC_BTRx_ADDSET_2 (0x4U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 8065 #define FMC_BTRx_ADDSET_3 (0x8U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 8066
<> 128:9bcdf88f62b0 8067 #define FMC_BTRx_ADDHLD_Pos (4U)
<> 128:9bcdf88f62b0 8068 #define FMC_BTRx_ADDHLD_Msk (0xFU << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
<> 128:9bcdf88f62b0 8069 #define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 128:9bcdf88f62b0 8070 #define FMC_BTRx_ADDHLD_0 (0x1U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 8071 #define FMC_BTRx_ADDHLD_1 (0x2U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 8072 #define FMC_BTRx_ADDHLD_2 (0x4U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 8073 #define FMC_BTRx_ADDHLD_3 (0x8U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 8074
<> 128:9bcdf88f62b0 8075 #define FMC_BTRx_DATAST_Pos (8U)
<> 128:9bcdf88f62b0 8076 #define FMC_BTRx_DATAST_Msk (0xFFU << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 8077 #define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
<> 128:9bcdf88f62b0 8078 #define FMC_BTRx_DATAST_0 (0x01U << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 8079 #define FMC_BTRx_DATAST_1 (0x02U << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 8080 #define FMC_BTRx_DATAST_2 (0x04U << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 8081 #define FMC_BTRx_DATAST_3 (0x08U << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 8082 #define FMC_BTRx_DATAST_4 (0x10U << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 8083 #define FMC_BTRx_DATAST_5 (0x20U << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 8084 #define FMC_BTRx_DATAST_6 (0x40U << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 8085 #define FMC_BTRx_DATAST_7 (0x80U << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 8086
<> 128:9bcdf88f62b0 8087 #define FMC_BTRx_BUSTURN_Pos (16U)
<> 128:9bcdf88f62b0 8088 #define FMC_BTRx_BUSTURN_Msk (0xFU << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
<> 128:9bcdf88f62b0 8089 #define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 128:9bcdf88f62b0 8090 #define FMC_BTRx_BUSTURN_0 (0x1U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 8091 #define FMC_BTRx_BUSTURN_1 (0x2U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 8092 #define FMC_BTRx_BUSTURN_2 (0x4U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 8093 #define FMC_BTRx_BUSTURN_3 (0x8U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 8094
<> 128:9bcdf88f62b0 8095 #define FMC_BTRx_CLKDIV_Pos (20U)
<> 128:9bcdf88f62b0 8096 #define FMC_BTRx_CLKDIV_Msk (0xFU << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
<> 128:9bcdf88f62b0 8097 #define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 128:9bcdf88f62b0 8098 #define FMC_BTRx_CLKDIV_0 (0x1U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 8099 #define FMC_BTRx_CLKDIV_1 (0x2U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 8100 #define FMC_BTRx_CLKDIV_2 (0x4U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 8101 #define FMC_BTRx_CLKDIV_3 (0x8U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 8102
<> 128:9bcdf88f62b0 8103 #define FMC_BTRx_DATLAT_Pos (24U)
<> 128:9bcdf88f62b0 8104 #define FMC_BTRx_DATLAT_Msk (0xFU << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
<> 128:9bcdf88f62b0 8105 #define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
<> 128:9bcdf88f62b0 8106 #define FMC_BTRx_DATLAT_0 (0x1U << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 8107 #define FMC_BTRx_DATLAT_1 (0x2U << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 8108 #define FMC_BTRx_DATLAT_2 (0x4U << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 8109 #define FMC_BTRx_DATLAT_3 (0x8U << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 8110
<> 128:9bcdf88f62b0 8111 #define FMC_BTRx_ACCMOD_Pos (28U)
<> 128:9bcdf88f62b0 8112 #define FMC_BTRx_ACCMOD_Msk (0x3U << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
<> 128:9bcdf88f62b0 8113 #define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
<> 128:9bcdf88f62b0 8114 #define FMC_BTRx_ACCMOD_0 (0x1U << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 8115 #define FMC_BTRx_ACCMOD_1 (0x2U << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 8116
<> 128:9bcdf88f62b0 8117 /****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
<> 128:9bcdf88f62b0 8118 #define FMC_BWTRx_ADDSET_Pos (0U)
<> 128:9bcdf88f62b0 8119 #define FMC_BWTRx_ADDSET_Msk (0xFU << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 8120 #define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 128:9bcdf88f62b0 8121 #define FMC_BWTRx_ADDSET_0 (0x1U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 8122 #define FMC_BWTRx_ADDSET_1 (0x2U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 8123 #define FMC_BWTRx_ADDSET_2 (0x4U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 8124 #define FMC_BWTRx_ADDSET_3 (0x8U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 8125
<> 128:9bcdf88f62b0 8126 #define FMC_BWTRx_ADDHLD_Pos (4U)
<> 128:9bcdf88f62b0 8127 #define FMC_BWTRx_ADDHLD_Msk (0xFU << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
<> 128:9bcdf88f62b0 8128 #define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 128:9bcdf88f62b0 8129 #define FMC_BWTRx_ADDHLD_0 (0x1U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 8130 #define FMC_BWTRx_ADDHLD_1 (0x2U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 8131 #define FMC_BWTRx_ADDHLD_2 (0x4U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 8132 #define FMC_BWTRx_ADDHLD_3 (0x8U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 8133
<> 128:9bcdf88f62b0 8134 #define FMC_BWTRx_DATAST_Pos (8U)
<> 128:9bcdf88f62b0 8135 #define FMC_BWTRx_DATAST_Msk (0xFFU << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 8136 #define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
<> 128:9bcdf88f62b0 8137 #define FMC_BWTRx_DATAST_0 (0x01U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 8138 #define FMC_BWTRx_DATAST_1 (0x02U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 8139 #define FMC_BWTRx_DATAST_2 (0x04U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 8140 #define FMC_BWTRx_DATAST_3 (0x08U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 8141 #define FMC_BWTRx_DATAST_4 (0x10U << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 8142 #define FMC_BWTRx_DATAST_5 (0x20U << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 8143 #define FMC_BWTRx_DATAST_6 (0x40U << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 8144 #define FMC_BWTRx_DATAST_7 (0x80U << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 8145
<> 128:9bcdf88f62b0 8146 #define FMC_BWTRx_BUSTURN_Pos (16U)
<> 128:9bcdf88f62b0 8147 #define FMC_BWTRx_BUSTURN_Msk (0xFU << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
<> 128:9bcdf88f62b0 8148 #define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 128:9bcdf88f62b0 8149 #define FMC_BWTRx_BUSTURN_0 (0x1U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 8150 #define FMC_BWTRx_BUSTURN_1 (0x2U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 8151 #define FMC_BWTRx_BUSTURN_2 (0x4U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 8152 #define FMC_BWTRx_BUSTURN_3 (0x8U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 8153
<> 128:9bcdf88f62b0 8154 #define FMC_BWTRx_ACCMOD_Pos (28U)
<> 128:9bcdf88f62b0 8155 #define FMC_BWTRx_ACCMOD_Msk (0x3U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
<> 128:9bcdf88f62b0 8156 #define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
<> 128:9bcdf88f62b0 8157 #define FMC_BWTRx_ACCMOD_0 (0x1U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 8158 #define FMC_BWTRx_ACCMOD_1 (0x2U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 8159
<> 128:9bcdf88f62b0 8160 /****************** Bit definition for FMC_PCR register ********************/
<> 128:9bcdf88f62b0 8161 #define FMC_PCR_PWAITEN_Pos (1U)
<> 128:9bcdf88f62b0 8162 #define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 8163 #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
<> 128:9bcdf88f62b0 8164 #define FMC_PCR_PBKEN_Pos (2U)
<> 128:9bcdf88f62b0 8165 #define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 8166 #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
<> 128:9bcdf88f62b0 8167 #define FMC_PCR_PTYP_Pos (3U)
<> 128:9bcdf88f62b0 8168 #define FMC_PCR_PTYP_Msk (0x1U << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 8169 #define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
<> 128:9bcdf88f62b0 8170
<> 128:9bcdf88f62b0 8171 #define FMC_PCR_PWID_Pos (4U)
<> 128:9bcdf88f62b0 8172 #define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
<> 128:9bcdf88f62b0 8173 #define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
<> 128:9bcdf88f62b0 8174 #define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 8175 #define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 8176
<> 128:9bcdf88f62b0 8177 #define FMC_PCR_ECCEN_Pos (6U)
<> 128:9bcdf88f62b0 8178 #define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 8179 #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
<> 128:9bcdf88f62b0 8180
<> 128:9bcdf88f62b0 8181 #define FMC_PCR_TCLR_Pos (9U)
<> 128:9bcdf88f62b0 8182 #define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
<> 128:9bcdf88f62b0 8183 #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
<> 128:9bcdf88f62b0 8184 #define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 8185 #define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 8186 #define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 8187 #define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 8188
<> 128:9bcdf88f62b0 8189 #define FMC_PCR_TAR_Pos (13U)
<> 128:9bcdf88f62b0 8190 #define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
<> 128:9bcdf88f62b0 8191 #define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
<> 128:9bcdf88f62b0 8192 #define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 8193 #define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 8194 #define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 8195 #define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 8196
<> 128:9bcdf88f62b0 8197 #define FMC_PCR_ECCPS_Pos (17U)
<> 128:9bcdf88f62b0 8198 #define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
<> 128:9bcdf88f62b0 8199 #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
<> 128:9bcdf88f62b0 8200 #define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 8201 #define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 8202 #define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 8203
<> 128:9bcdf88f62b0 8204 /******************* Bit definition for FMC_SR register ********************/
<> 128:9bcdf88f62b0 8205 #define FMC_SR_IRS_Pos (0U)
<> 128:9bcdf88f62b0 8206 #define FMC_SR_IRS_Msk (0x1U << FMC_SR_IRS_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 8207 #define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
<> 128:9bcdf88f62b0 8208 #define FMC_SR_ILS_Pos (1U)
<> 128:9bcdf88f62b0 8209 #define FMC_SR_ILS_Msk (0x1U << FMC_SR_ILS_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 8210 #define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
<> 128:9bcdf88f62b0 8211 #define FMC_SR_IFS_Pos (2U)
<> 128:9bcdf88f62b0 8212 #define FMC_SR_IFS_Msk (0x1U << FMC_SR_IFS_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 8213 #define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
<> 128:9bcdf88f62b0 8214 #define FMC_SR_IREN_Pos (3U)
<> 128:9bcdf88f62b0 8215 #define FMC_SR_IREN_Msk (0x1U << FMC_SR_IREN_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 8216 #define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
<> 128:9bcdf88f62b0 8217 #define FMC_SR_ILEN_Pos (4U)
<> 128:9bcdf88f62b0 8218 #define FMC_SR_ILEN_Msk (0x1U << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 8219 #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
<> 128:9bcdf88f62b0 8220 #define FMC_SR_IFEN_Pos (5U)
<> 128:9bcdf88f62b0 8221 #define FMC_SR_IFEN_Msk (0x1U << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 8222 #define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
<> 128:9bcdf88f62b0 8223 #define FMC_SR_FEMPT_Pos (6U)
<> 128:9bcdf88f62b0 8224 #define FMC_SR_FEMPT_Msk (0x1U << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 8225 #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
<> 128:9bcdf88f62b0 8226
<> 128:9bcdf88f62b0 8227 /****************** Bit definition for FMC_PMEM register ******************/
<> 128:9bcdf88f62b0 8228 #define FMC_PMEM_MEMSET_Pos (0U)
<> 128:9bcdf88f62b0 8229 #define FMC_PMEM_MEMSET_Msk (0xFFU << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 8230 #define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */
<> 128:9bcdf88f62b0 8231 #define FMC_PMEM_MEMSET_0 (0x01U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 8232 #define FMC_PMEM_MEMSET_1 (0x02U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 8233 #define FMC_PMEM_MEMSET_2 (0x04U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 8234 #define FMC_PMEM_MEMSET_3 (0x08U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 8235 #define FMC_PMEM_MEMSET_4 (0x10U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 8236 #define FMC_PMEM_MEMSET_5 (0x20U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 8237 #define FMC_PMEM_MEMSET_6 (0x40U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 8238 #define FMC_PMEM_MEMSET_7 (0x80U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 8239
<> 128:9bcdf88f62b0 8240 #define FMC_PMEM_MEMWAIT_Pos (8U)
<> 128:9bcdf88f62b0 8241 #define FMC_PMEM_MEMWAIT_Msk (0xFFU << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 8242 #define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */
<> 128:9bcdf88f62b0 8243 #define FMC_PMEM_MEMWAIT_0 (0x01U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 8244 #define FMC_PMEM_MEMWAIT_1 (0x02U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 8245 #define FMC_PMEM_MEMWAIT_2 (0x04U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 8246 #define FMC_PMEM_MEMWAIT_3 (0x08U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 8247 #define FMC_PMEM_MEMWAIT_4 (0x10U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 8248 #define FMC_PMEM_MEMWAIT_5 (0x20U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 8249 #define FMC_PMEM_MEMWAIT_6 (0x40U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 8250 #define FMC_PMEM_MEMWAIT_7 (0x80U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 8251
<> 128:9bcdf88f62b0 8252 #define FMC_PMEM_MEMHOLD_Pos (16U)
<> 128:9bcdf88f62b0 8253 #define FMC_PMEM_MEMHOLD_Msk (0xFFU << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 8254 #define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */
<> 128:9bcdf88f62b0 8255 #define FMC_PMEM_MEMHOLD_0 (0x01U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 8256 #define FMC_PMEM_MEMHOLD_1 (0x02U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 8257 #define FMC_PMEM_MEMHOLD_2 (0x04U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 8258 #define FMC_PMEM_MEMHOLD_3 (0x08U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 8259 #define FMC_PMEM_MEMHOLD_4 (0x10U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 8260 #define FMC_PMEM_MEMHOLD_5 (0x20U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 8261 #define FMC_PMEM_MEMHOLD_6 (0x40U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 8262 #define FMC_PMEM_MEMHOLD_7 (0x80U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 8263
<> 128:9bcdf88f62b0 8264 #define FMC_PMEM_MEMHIZ_Pos (24U)
<> 128:9bcdf88f62b0 8265 #define FMC_PMEM_MEMHIZ_Msk (0xFFU << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */
<> 128:9bcdf88f62b0 8266 #define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
<> 128:9bcdf88f62b0 8267 #define FMC_PMEM_MEMHIZ_0 (0x01U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 8268 #define FMC_PMEM_MEMHIZ_1 (0x02U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 8269 #define FMC_PMEM_MEMHIZ_2 (0x04U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 8270 #define FMC_PMEM_MEMHIZ_3 (0x08U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 8271 #define FMC_PMEM_MEMHIZ_4 (0x10U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 8272 #define FMC_PMEM_MEMHIZ_5 (0x20U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 8273 #define FMC_PMEM_MEMHIZ_6 (0x40U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 8274 #define FMC_PMEM_MEMHIZ_7 (0x80U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 8275
<> 128:9bcdf88f62b0 8276 /****************** Bit definition for FMC_PATT register *******************/
<> 128:9bcdf88f62b0 8277 #define FMC_PATT_ATTSET_Pos (0U)
<> 128:9bcdf88f62b0 8278 #define FMC_PATT_ATTSET_Msk (0xFFU << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 8279 #define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */
<> 128:9bcdf88f62b0 8280 #define FMC_PATT_ATTSET_0 (0x01U << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 8281 #define FMC_PATT_ATTSET_1 (0x02U << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 8282 #define FMC_PATT_ATTSET_2 (0x04U << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 8283 #define FMC_PATT_ATTSET_3 (0x08U << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 8284 #define FMC_PATT_ATTSET_4 (0x10U << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 8285 #define FMC_PATT_ATTSET_5 (0x20U << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 8286 #define FMC_PATT_ATTSET_6 (0x40U << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 8287 #define FMC_PATT_ATTSET_7 (0x80U << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 8288
<> 128:9bcdf88f62b0 8289 #define FMC_PATT_ATTWAIT_Pos (8U)
<> 128:9bcdf88f62b0 8290 #define FMC_PATT_ATTWAIT_Msk (0xFFU << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 8291 #define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
<> 128:9bcdf88f62b0 8292 #define FMC_PATT_ATTWAIT_0 (0x01U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 8293 #define FMC_PATT_ATTWAIT_1 (0x02U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 8294 #define FMC_PATT_ATTWAIT_2 (0x04U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 8295 #define FMC_PATT_ATTWAIT_3 (0x08U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 8296 #define FMC_PATT_ATTWAIT_4 (0x10U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 8297 #define FMC_PATT_ATTWAIT_5 (0x20U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 8298 #define FMC_PATT_ATTWAIT_6 (0x40U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 8299 #define FMC_PATT_ATTWAIT_7 (0x80U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 8300
<> 128:9bcdf88f62b0 8301 #define FMC_PATT_ATTHOLD_Pos (16U)
<> 128:9bcdf88f62b0 8302 #define FMC_PATT_ATTHOLD_Msk (0xFFU << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 8303 #define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
<> 128:9bcdf88f62b0 8304 #define FMC_PATT_ATTHOLD_0 (0x01U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 8305 #define FMC_PATT_ATTHOLD_1 (0x02U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 8306 #define FMC_PATT_ATTHOLD_2 (0x04U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 8307 #define FMC_PATT_ATTHOLD_3 (0x08U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 8308 #define FMC_PATT_ATTHOLD_4 (0x10U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 8309 #define FMC_PATT_ATTHOLD_5 (0x20U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 8310 #define FMC_PATT_ATTHOLD_6 (0x40U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 8311 #define FMC_PATT_ATTHOLD_7 (0x80U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 8312
<> 128:9bcdf88f62b0 8313 #define FMC_PATT_ATTHIZ_Pos (24U)
<> 128:9bcdf88f62b0 8314 #define FMC_PATT_ATTHIZ_Msk (0xFFU << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */
<> 128:9bcdf88f62b0 8315 #define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
<> 128:9bcdf88f62b0 8316 #define FMC_PATT_ATTHIZ_0 (0x01U << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 8317 #define FMC_PATT_ATTHIZ_1 (0x02U << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 8318 #define FMC_PATT_ATTHIZ_2 (0x04U << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 8319 #define FMC_PATT_ATTHIZ_3 (0x08U << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 8320 #define FMC_PATT_ATTHIZ_4 (0x10U << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 8321 #define FMC_PATT_ATTHIZ_5 (0x20U << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 8322 #define FMC_PATT_ATTHIZ_6 (0x40U << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 8323 #define FMC_PATT_ATTHIZ_7 (0x80U << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 8324
<> 128:9bcdf88f62b0 8325 /****************** Bit definition for FMC_ECCR register *******************/
<> 128:9bcdf88f62b0 8326 #define FMC_ECCR_ECC_Pos (0U)
<> 128:9bcdf88f62b0 8327 #define FMC_ECCR_ECC_Msk (0xFFFFFFFFU << FMC_ECCR_ECC_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 8328 #define FMC_ECCR_ECC FMC_ECCR_ECC_Msk /*!<ECC result */
<> 128:9bcdf88f62b0 8329
<> 128:9bcdf88f62b0 8330 /******************************************************************************/
<> 128:9bcdf88f62b0 8331 /* */
<> 128:9bcdf88f62b0 8332 /* General Purpose IOs (GPIO) */
<> 128:9bcdf88f62b0 8333 /* */
<> 128:9bcdf88f62b0 8334 /******************************************************************************/
<> 128:9bcdf88f62b0 8335 /****************** Bits definition for GPIO_MODER register *****************/
<> 128:9bcdf88f62b0 8336 #define GPIO_MODER_MODE0_Pos (0U)
<> 128:9bcdf88f62b0 8337 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 8338 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
<> 128:9bcdf88f62b0 8339 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 8340 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 8341 #define GPIO_MODER_MODE1_Pos (2U)
<> 128:9bcdf88f62b0 8342 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
<> 128:9bcdf88f62b0 8343 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
<> 128:9bcdf88f62b0 8344 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 8345 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 8346 #define GPIO_MODER_MODE2_Pos (4U)
<> 128:9bcdf88f62b0 8347 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
<> 128:9bcdf88f62b0 8348 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
<> 128:9bcdf88f62b0 8349 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 8350 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 8351 #define GPIO_MODER_MODE3_Pos (6U)
<> 128:9bcdf88f62b0 8352 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
<> 128:9bcdf88f62b0 8353 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
<> 128:9bcdf88f62b0 8354 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 8355 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 8356 #define GPIO_MODER_MODE4_Pos (8U)
<> 128:9bcdf88f62b0 8357 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
<> 128:9bcdf88f62b0 8358 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
<> 128:9bcdf88f62b0 8359 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 8360 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 8361 #define GPIO_MODER_MODE5_Pos (10U)
<> 128:9bcdf88f62b0 8362 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
<> 128:9bcdf88f62b0 8363 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
<> 128:9bcdf88f62b0 8364 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 8365 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 8366 #define GPIO_MODER_MODE6_Pos (12U)
<> 128:9bcdf88f62b0 8367 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
<> 128:9bcdf88f62b0 8368 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
<> 128:9bcdf88f62b0 8369 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 8370 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 8371 #define GPIO_MODER_MODE7_Pos (14U)
<> 128:9bcdf88f62b0 8372 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
<> 128:9bcdf88f62b0 8373 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
<> 128:9bcdf88f62b0 8374 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 8375 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 8376 #define GPIO_MODER_MODE8_Pos (16U)
<> 128:9bcdf88f62b0 8377 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
<> 128:9bcdf88f62b0 8378 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
<> 128:9bcdf88f62b0 8379 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 8380 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 8381 #define GPIO_MODER_MODE9_Pos (18U)
<> 128:9bcdf88f62b0 8382 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
<> 128:9bcdf88f62b0 8383 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
<> 128:9bcdf88f62b0 8384 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 8385 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 8386 #define GPIO_MODER_MODE10_Pos (20U)
<> 128:9bcdf88f62b0 8387 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
<> 128:9bcdf88f62b0 8388 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
<> 128:9bcdf88f62b0 8389 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 8390 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 8391 #define GPIO_MODER_MODE11_Pos (22U)
<> 128:9bcdf88f62b0 8392 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
<> 128:9bcdf88f62b0 8393 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
<> 128:9bcdf88f62b0 8394 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 8395 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 8396 #define GPIO_MODER_MODE12_Pos (24U)
<> 128:9bcdf88f62b0 8397 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
<> 128:9bcdf88f62b0 8398 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
<> 128:9bcdf88f62b0 8399 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 8400 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 8401 #define GPIO_MODER_MODE13_Pos (26U)
<> 128:9bcdf88f62b0 8402 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
<> 128:9bcdf88f62b0 8403 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
<> 128:9bcdf88f62b0 8404 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 8405 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 8406 #define GPIO_MODER_MODE14_Pos (28U)
<> 128:9bcdf88f62b0 8407 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
<> 128:9bcdf88f62b0 8408 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
<> 128:9bcdf88f62b0 8409 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 8410 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 8411 #define GPIO_MODER_MODE15_Pos (30U)
<> 128:9bcdf88f62b0 8412 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
<> 128:9bcdf88f62b0 8413 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
<> 128:9bcdf88f62b0 8414 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 8415 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 8416
<> 128:9bcdf88f62b0 8417 /* Legacy defines */
<> 128:9bcdf88f62b0 8418 #define GPIO_MODER_MODER0 GPIO_MODER_MODE0
<> 128:9bcdf88f62b0 8419 #define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
<> 128:9bcdf88f62b0 8420 #define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
<> 128:9bcdf88f62b0 8421 #define GPIO_MODER_MODER1 GPIO_MODER_MODE1
<> 128:9bcdf88f62b0 8422 #define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
<> 128:9bcdf88f62b0 8423 #define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
<> 128:9bcdf88f62b0 8424 #define GPIO_MODER_MODER2 GPIO_MODER_MODE2
<> 128:9bcdf88f62b0 8425 #define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
<> 128:9bcdf88f62b0 8426 #define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
<> 128:9bcdf88f62b0 8427 #define GPIO_MODER_MODER3 GPIO_MODER_MODE3
<> 128:9bcdf88f62b0 8428 #define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
<> 128:9bcdf88f62b0 8429 #define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
<> 128:9bcdf88f62b0 8430 #define GPIO_MODER_MODER4 GPIO_MODER_MODE4
<> 128:9bcdf88f62b0 8431 #define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
<> 128:9bcdf88f62b0 8432 #define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
<> 128:9bcdf88f62b0 8433 #define GPIO_MODER_MODER5 GPIO_MODER_MODE5
<> 128:9bcdf88f62b0 8434 #define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
<> 128:9bcdf88f62b0 8435 #define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
<> 128:9bcdf88f62b0 8436 #define GPIO_MODER_MODER6 GPIO_MODER_MODE6
<> 128:9bcdf88f62b0 8437 #define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
<> 128:9bcdf88f62b0 8438 #define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
<> 128:9bcdf88f62b0 8439 #define GPIO_MODER_MODER7 GPIO_MODER_MODE7
<> 128:9bcdf88f62b0 8440 #define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
<> 128:9bcdf88f62b0 8441 #define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
<> 128:9bcdf88f62b0 8442 #define GPIO_MODER_MODER8 GPIO_MODER_MODE8
<> 128:9bcdf88f62b0 8443 #define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
<> 128:9bcdf88f62b0 8444 #define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
<> 128:9bcdf88f62b0 8445 #define GPIO_MODER_MODER9 GPIO_MODER_MODE9
<> 128:9bcdf88f62b0 8446 #define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
<> 128:9bcdf88f62b0 8447 #define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
<> 128:9bcdf88f62b0 8448 #define GPIO_MODER_MODER10 GPIO_MODER_MODE10
<> 128:9bcdf88f62b0 8449 #define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
<> 128:9bcdf88f62b0 8450 #define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
<> 128:9bcdf88f62b0 8451 #define GPIO_MODER_MODER11 GPIO_MODER_MODE11
<> 128:9bcdf88f62b0 8452 #define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
<> 128:9bcdf88f62b0 8453 #define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
<> 128:9bcdf88f62b0 8454 #define GPIO_MODER_MODER12 GPIO_MODER_MODE12
<> 128:9bcdf88f62b0 8455 #define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
<> 128:9bcdf88f62b0 8456 #define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
<> 128:9bcdf88f62b0 8457 #define GPIO_MODER_MODER13 GPIO_MODER_MODE13
<> 128:9bcdf88f62b0 8458 #define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
<> 128:9bcdf88f62b0 8459 #define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
<> 128:9bcdf88f62b0 8460 #define GPIO_MODER_MODER14 GPIO_MODER_MODE14
<> 128:9bcdf88f62b0 8461 #define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
<> 128:9bcdf88f62b0 8462 #define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
<> 128:9bcdf88f62b0 8463 #define GPIO_MODER_MODER15 GPIO_MODER_MODE15
<> 128:9bcdf88f62b0 8464 #define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
<> 128:9bcdf88f62b0 8465 #define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
<> 128:9bcdf88f62b0 8466
<> 128:9bcdf88f62b0 8467 /****************** Bits definition for GPIO_OTYPER register ****************/
<> 128:9bcdf88f62b0 8468 #define GPIO_OTYPER_OT0_Pos (0U)
<> 128:9bcdf88f62b0 8469 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 8470 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
<> 128:9bcdf88f62b0 8471 #define GPIO_OTYPER_OT1_Pos (1U)
<> 128:9bcdf88f62b0 8472 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 8473 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
<> 128:9bcdf88f62b0 8474 #define GPIO_OTYPER_OT2_Pos (2U)
<> 128:9bcdf88f62b0 8475 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 8476 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
<> 128:9bcdf88f62b0 8477 #define GPIO_OTYPER_OT3_Pos (3U)
<> 128:9bcdf88f62b0 8478 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 8479 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
<> 128:9bcdf88f62b0 8480 #define GPIO_OTYPER_OT4_Pos (4U)
<> 128:9bcdf88f62b0 8481 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 8482 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
<> 128:9bcdf88f62b0 8483 #define GPIO_OTYPER_OT5_Pos (5U)
<> 128:9bcdf88f62b0 8484 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 8485 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
<> 128:9bcdf88f62b0 8486 #define GPIO_OTYPER_OT6_Pos (6U)
<> 128:9bcdf88f62b0 8487 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 8488 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
<> 128:9bcdf88f62b0 8489 #define GPIO_OTYPER_OT7_Pos (7U)
<> 128:9bcdf88f62b0 8490 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 8491 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
<> 128:9bcdf88f62b0 8492 #define GPIO_OTYPER_OT8_Pos (8U)
<> 128:9bcdf88f62b0 8493 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 8494 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
<> 128:9bcdf88f62b0 8495 #define GPIO_OTYPER_OT9_Pos (9U)
<> 128:9bcdf88f62b0 8496 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 8497 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
<> 128:9bcdf88f62b0 8498 #define GPIO_OTYPER_OT10_Pos (10U)
<> 128:9bcdf88f62b0 8499 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 8500 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
<> 128:9bcdf88f62b0 8501 #define GPIO_OTYPER_OT11_Pos (11U)
<> 128:9bcdf88f62b0 8502 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 8503 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
<> 128:9bcdf88f62b0 8504 #define GPIO_OTYPER_OT12_Pos (12U)
<> 128:9bcdf88f62b0 8505 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 8506 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
<> 128:9bcdf88f62b0 8507 #define GPIO_OTYPER_OT13_Pos (13U)
<> 128:9bcdf88f62b0 8508 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 8509 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
<> 128:9bcdf88f62b0 8510 #define GPIO_OTYPER_OT14_Pos (14U)
<> 128:9bcdf88f62b0 8511 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 8512 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
<> 128:9bcdf88f62b0 8513 #define GPIO_OTYPER_OT15_Pos (15U)
<> 128:9bcdf88f62b0 8514 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 8515 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
<> 128:9bcdf88f62b0 8516
<> 128:9bcdf88f62b0 8517 /* Legacy defines */
<> 128:9bcdf88f62b0 8518 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
<> 128:9bcdf88f62b0 8519 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
<> 128:9bcdf88f62b0 8520 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
<> 128:9bcdf88f62b0 8521 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
<> 128:9bcdf88f62b0 8522 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
<> 128:9bcdf88f62b0 8523 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
<> 128:9bcdf88f62b0 8524 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
<> 128:9bcdf88f62b0 8525 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
<> 128:9bcdf88f62b0 8526 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
<> 128:9bcdf88f62b0 8527 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
<> 128:9bcdf88f62b0 8528 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
<> 128:9bcdf88f62b0 8529 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
<> 128:9bcdf88f62b0 8530 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
<> 128:9bcdf88f62b0 8531 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
<> 128:9bcdf88f62b0 8532 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
<> 128:9bcdf88f62b0 8533 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
<> 128:9bcdf88f62b0 8534
<> 128:9bcdf88f62b0 8535 /****************** Bits definition for GPIO_OSPEEDR register ***************/
<> 128:9bcdf88f62b0 8536 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
<> 128:9bcdf88f62b0 8537 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 8538 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
<> 128:9bcdf88f62b0 8539 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 8540 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 8541 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
<> 128:9bcdf88f62b0 8542 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
<> 128:9bcdf88f62b0 8543 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
<> 128:9bcdf88f62b0 8544 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 8545 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 8546 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
<> 128:9bcdf88f62b0 8547 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
<> 128:9bcdf88f62b0 8548 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
<> 128:9bcdf88f62b0 8549 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 8550 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 8551 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
<> 128:9bcdf88f62b0 8552 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
<> 128:9bcdf88f62b0 8553 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
<> 128:9bcdf88f62b0 8554 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 8555 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 8556 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
<> 128:9bcdf88f62b0 8557 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
<> 128:9bcdf88f62b0 8558 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
<> 128:9bcdf88f62b0 8559 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 8560 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 8561 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
<> 128:9bcdf88f62b0 8562 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
<> 128:9bcdf88f62b0 8563 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
<> 128:9bcdf88f62b0 8564 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 8565 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 8566 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
<> 128:9bcdf88f62b0 8567 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
<> 128:9bcdf88f62b0 8568 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
<> 128:9bcdf88f62b0 8569 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 8570 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 8571 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
<> 128:9bcdf88f62b0 8572 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
<> 128:9bcdf88f62b0 8573 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
<> 128:9bcdf88f62b0 8574 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 8575 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 8576 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
<> 128:9bcdf88f62b0 8577 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
<> 128:9bcdf88f62b0 8578 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
<> 128:9bcdf88f62b0 8579 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 8580 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 8581 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
<> 128:9bcdf88f62b0 8582 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
<> 128:9bcdf88f62b0 8583 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
<> 128:9bcdf88f62b0 8584 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 8585 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 8586 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
<> 128:9bcdf88f62b0 8587 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
<> 128:9bcdf88f62b0 8588 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
<> 128:9bcdf88f62b0 8589 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 8590 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 8591 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
<> 128:9bcdf88f62b0 8592 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
<> 128:9bcdf88f62b0 8593 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
<> 128:9bcdf88f62b0 8594 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 8595 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 8596 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
<> 128:9bcdf88f62b0 8597 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
<> 128:9bcdf88f62b0 8598 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
<> 128:9bcdf88f62b0 8599 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 8600 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 8601 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
<> 128:9bcdf88f62b0 8602 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
<> 128:9bcdf88f62b0 8603 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
<> 128:9bcdf88f62b0 8604 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 8605 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 8606 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
<> 128:9bcdf88f62b0 8607 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
<> 128:9bcdf88f62b0 8608 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
<> 128:9bcdf88f62b0 8609 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 8610 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 8611 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
<> 128:9bcdf88f62b0 8612 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
<> 128:9bcdf88f62b0 8613 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
<> 128:9bcdf88f62b0 8614 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 8615 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 8616
<> 128:9bcdf88f62b0 8617 /* Legacy defines */
<> 128:9bcdf88f62b0 8618 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
<> 128:9bcdf88f62b0 8619 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
<> 128:9bcdf88f62b0 8620 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
<> 128:9bcdf88f62b0 8621 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
<> 128:9bcdf88f62b0 8622 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
<> 128:9bcdf88f62b0 8623 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
<> 128:9bcdf88f62b0 8624 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
<> 128:9bcdf88f62b0 8625 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
<> 128:9bcdf88f62b0 8626 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
<> 128:9bcdf88f62b0 8627 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
<> 128:9bcdf88f62b0 8628 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
<> 128:9bcdf88f62b0 8629 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
<> 128:9bcdf88f62b0 8630 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
<> 128:9bcdf88f62b0 8631 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
<> 128:9bcdf88f62b0 8632 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
<> 128:9bcdf88f62b0 8633 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
<> 128:9bcdf88f62b0 8634 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
<> 128:9bcdf88f62b0 8635 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
<> 128:9bcdf88f62b0 8636 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
<> 128:9bcdf88f62b0 8637 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
<> 128:9bcdf88f62b0 8638 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
<> 128:9bcdf88f62b0 8639 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
<> 128:9bcdf88f62b0 8640 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
<> 128:9bcdf88f62b0 8641 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
<> 128:9bcdf88f62b0 8642 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
<> 128:9bcdf88f62b0 8643 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
<> 128:9bcdf88f62b0 8644 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
<> 128:9bcdf88f62b0 8645 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
<> 128:9bcdf88f62b0 8646 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
<> 128:9bcdf88f62b0 8647 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
<> 128:9bcdf88f62b0 8648 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
<> 128:9bcdf88f62b0 8649 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
<> 128:9bcdf88f62b0 8650 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
<> 128:9bcdf88f62b0 8651 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
<> 128:9bcdf88f62b0 8652 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
<> 128:9bcdf88f62b0 8653 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
<> 128:9bcdf88f62b0 8654 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
<> 128:9bcdf88f62b0 8655 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
<> 128:9bcdf88f62b0 8656 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
<> 128:9bcdf88f62b0 8657 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
<> 128:9bcdf88f62b0 8658 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
<> 128:9bcdf88f62b0 8659 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
<> 128:9bcdf88f62b0 8660 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
<> 128:9bcdf88f62b0 8661 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
<> 128:9bcdf88f62b0 8662 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
<> 128:9bcdf88f62b0 8663 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
<> 128:9bcdf88f62b0 8664 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
<> 128:9bcdf88f62b0 8665 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
<> 128:9bcdf88f62b0 8666
<> 128:9bcdf88f62b0 8667 /****************** Bits definition for GPIO_PUPDR register *****************/
<> 128:9bcdf88f62b0 8668 #define GPIO_PUPDR_PUPD0_Pos (0U)
<> 128:9bcdf88f62b0 8669 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 8670 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
<> 128:9bcdf88f62b0 8671 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 8672 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 8673 #define GPIO_PUPDR_PUPD1_Pos (2U)
<> 128:9bcdf88f62b0 8674 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
<> 128:9bcdf88f62b0 8675 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
<> 128:9bcdf88f62b0 8676 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 8677 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 8678 #define GPIO_PUPDR_PUPD2_Pos (4U)
<> 128:9bcdf88f62b0 8679 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
<> 128:9bcdf88f62b0 8680 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
<> 128:9bcdf88f62b0 8681 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 8682 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 8683 #define GPIO_PUPDR_PUPD3_Pos (6U)
<> 128:9bcdf88f62b0 8684 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
<> 128:9bcdf88f62b0 8685 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
<> 128:9bcdf88f62b0 8686 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 8687 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 8688 #define GPIO_PUPDR_PUPD4_Pos (8U)
<> 128:9bcdf88f62b0 8689 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
<> 128:9bcdf88f62b0 8690 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
<> 128:9bcdf88f62b0 8691 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 8692 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 8693 #define GPIO_PUPDR_PUPD5_Pos (10U)
<> 128:9bcdf88f62b0 8694 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
<> 128:9bcdf88f62b0 8695 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
<> 128:9bcdf88f62b0 8696 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 8697 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 8698 #define GPIO_PUPDR_PUPD6_Pos (12U)
<> 128:9bcdf88f62b0 8699 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
<> 128:9bcdf88f62b0 8700 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
<> 128:9bcdf88f62b0 8701 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 8702 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 8703 #define GPIO_PUPDR_PUPD7_Pos (14U)
<> 128:9bcdf88f62b0 8704 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
<> 128:9bcdf88f62b0 8705 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
<> 128:9bcdf88f62b0 8706 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 8707 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 8708 #define GPIO_PUPDR_PUPD8_Pos (16U)
<> 128:9bcdf88f62b0 8709 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
<> 128:9bcdf88f62b0 8710 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
<> 128:9bcdf88f62b0 8711 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 8712 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 8713 #define GPIO_PUPDR_PUPD9_Pos (18U)
<> 128:9bcdf88f62b0 8714 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
<> 128:9bcdf88f62b0 8715 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
<> 128:9bcdf88f62b0 8716 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 8717 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 8718 #define GPIO_PUPDR_PUPD10_Pos (20U)
<> 128:9bcdf88f62b0 8719 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
<> 128:9bcdf88f62b0 8720 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
<> 128:9bcdf88f62b0 8721 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 8722 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 8723 #define GPIO_PUPDR_PUPD11_Pos (22U)
<> 128:9bcdf88f62b0 8724 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
<> 128:9bcdf88f62b0 8725 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
<> 128:9bcdf88f62b0 8726 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 8727 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 8728 #define GPIO_PUPDR_PUPD12_Pos (24U)
<> 128:9bcdf88f62b0 8729 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
<> 128:9bcdf88f62b0 8730 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
<> 128:9bcdf88f62b0 8731 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 8732 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 8733 #define GPIO_PUPDR_PUPD13_Pos (26U)
<> 128:9bcdf88f62b0 8734 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
<> 128:9bcdf88f62b0 8735 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
<> 128:9bcdf88f62b0 8736 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 8737 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 8738 #define GPIO_PUPDR_PUPD14_Pos (28U)
<> 128:9bcdf88f62b0 8739 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
<> 128:9bcdf88f62b0 8740 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
<> 128:9bcdf88f62b0 8741 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 8742 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 8743 #define GPIO_PUPDR_PUPD15_Pos (30U)
<> 128:9bcdf88f62b0 8744 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
<> 128:9bcdf88f62b0 8745 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
<> 128:9bcdf88f62b0 8746 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 8747 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 8748
<> 128:9bcdf88f62b0 8749 /* Legacy defines */
<> 128:9bcdf88f62b0 8750 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
<> 128:9bcdf88f62b0 8751 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
<> 128:9bcdf88f62b0 8752 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
<> 128:9bcdf88f62b0 8753 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
<> 128:9bcdf88f62b0 8754 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
<> 128:9bcdf88f62b0 8755 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
<> 128:9bcdf88f62b0 8756 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
<> 128:9bcdf88f62b0 8757 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
<> 128:9bcdf88f62b0 8758 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
<> 128:9bcdf88f62b0 8759 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
<> 128:9bcdf88f62b0 8760 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
<> 128:9bcdf88f62b0 8761 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
<> 128:9bcdf88f62b0 8762 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
<> 128:9bcdf88f62b0 8763 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
<> 128:9bcdf88f62b0 8764 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
<> 128:9bcdf88f62b0 8765 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
<> 128:9bcdf88f62b0 8766 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
<> 128:9bcdf88f62b0 8767 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
<> 128:9bcdf88f62b0 8768 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
<> 128:9bcdf88f62b0 8769 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
<> 128:9bcdf88f62b0 8770 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
<> 128:9bcdf88f62b0 8771 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
<> 128:9bcdf88f62b0 8772 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
<> 128:9bcdf88f62b0 8773 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
<> 128:9bcdf88f62b0 8774 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
<> 128:9bcdf88f62b0 8775 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
<> 128:9bcdf88f62b0 8776 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
<> 128:9bcdf88f62b0 8777 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
<> 128:9bcdf88f62b0 8778 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
<> 128:9bcdf88f62b0 8779 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
<> 128:9bcdf88f62b0 8780 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
<> 128:9bcdf88f62b0 8781 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
<> 128:9bcdf88f62b0 8782 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
<> 128:9bcdf88f62b0 8783 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
<> 128:9bcdf88f62b0 8784 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
<> 128:9bcdf88f62b0 8785 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
<> 128:9bcdf88f62b0 8786 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
<> 128:9bcdf88f62b0 8787 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
<> 128:9bcdf88f62b0 8788 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
<> 128:9bcdf88f62b0 8789 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
<> 128:9bcdf88f62b0 8790 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
<> 128:9bcdf88f62b0 8791 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
<> 128:9bcdf88f62b0 8792 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
<> 128:9bcdf88f62b0 8793 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
<> 128:9bcdf88f62b0 8794 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
<> 128:9bcdf88f62b0 8795 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
<> 128:9bcdf88f62b0 8796 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
<> 128:9bcdf88f62b0 8797 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
<> 128:9bcdf88f62b0 8798
<> 128:9bcdf88f62b0 8799 /****************** Bits definition for GPIO_IDR register *******************/
<> 128:9bcdf88f62b0 8800 #define GPIO_IDR_ID0_Pos (0U)
<> 128:9bcdf88f62b0 8801 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 8802 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
<> 128:9bcdf88f62b0 8803 #define GPIO_IDR_ID1_Pos (1U)
<> 128:9bcdf88f62b0 8804 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 8805 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
<> 128:9bcdf88f62b0 8806 #define GPIO_IDR_ID2_Pos (2U)
<> 128:9bcdf88f62b0 8807 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 8808 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
<> 128:9bcdf88f62b0 8809 #define GPIO_IDR_ID3_Pos (3U)
<> 128:9bcdf88f62b0 8810 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 8811 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
<> 128:9bcdf88f62b0 8812 #define GPIO_IDR_ID4_Pos (4U)
<> 128:9bcdf88f62b0 8813 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 8814 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
<> 128:9bcdf88f62b0 8815 #define GPIO_IDR_ID5_Pos (5U)
<> 128:9bcdf88f62b0 8816 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 8817 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
<> 128:9bcdf88f62b0 8818 #define GPIO_IDR_ID6_Pos (6U)
<> 128:9bcdf88f62b0 8819 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 8820 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
<> 128:9bcdf88f62b0 8821 #define GPIO_IDR_ID7_Pos (7U)
<> 128:9bcdf88f62b0 8822 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 8823 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
<> 128:9bcdf88f62b0 8824 #define GPIO_IDR_ID8_Pos (8U)
<> 128:9bcdf88f62b0 8825 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 8826 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
<> 128:9bcdf88f62b0 8827 #define GPIO_IDR_ID9_Pos (9U)
<> 128:9bcdf88f62b0 8828 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 8829 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
<> 128:9bcdf88f62b0 8830 #define GPIO_IDR_ID10_Pos (10U)
<> 128:9bcdf88f62b0 8831 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 8832 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
<> 128:9bcdf88f62b0 8833 #define GPIO_IDR_ID11_Pos (11U)
<> 128:9bcdf88f62b0 8834 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 8835 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
<> 128:9bcdf88f62b0 8836 #define GPIO_IDR_ID12_Pos (12U)
<> 128:9bcdf88f62b0 8837 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 8838 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
<> 128:9bcdf88f62b0 8839 #define GPIO_IDR_ID13_Pos (13U)
<> 128:9bcdf88f62b0 8840 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 8841 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
<> 128:9bcdf88f62b0 8842 #define GPIO_IDR_ID14_Pos (14U)
<> 128:9bcdf88f62b0 8843 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 8844 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
<> 128:9bcdf88f62b0 8845 #define GPIO_IDR_ID15_Pos (15U)
<> 128:9bcdf88f62b0 8846 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 8847 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
<> 128:9bcdf88f62b0 8848
<> 128:9bcdf88f62b0 8849 /* Legacy defines */
<> 128:9bcdf88f62b0 8850 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
<> 128:9bcdf88f62b0 8851 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
<> 128:9bcdf88f62b0 8852 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
<> 128:9bcdf88f62b0 8853 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
<> 128:9bcdf88f62b0 8854 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
<> 128:9bcdf88f62b0 8855 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
<> 128:9bcdf88f62b0 8856 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
<> 128:9bcdf88f62b0 8857 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
<> 128:9bcdf88f62b0 8858 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
<> 128:9bcdf88f62b0 8859 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
<> 128:9bcdf88f62b0 8860 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
<> 128:9bcdf88f62b0 8861 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
<> 128:9bcdf88f62b0 8862 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
<> 128:9bcdf88f62b0 8863 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
<> 128:9bcdf88f62b0 8864 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
<> 128:9bcdf88f62b0 8865 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
<> 128:9bcdf88f62b0 8866
<> 128:9bcdf88f62b0 8867 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
<> 128:9bcdf88f62b0 8868 #define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
<> 128:9bcdf88f62b0 8869 #define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
<> 128:9bcdf88f62b0 8870 #define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
<> 128:9bcdf88f62b0 8871 #define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
<> 128:9bcdf88f62b0 8872 #define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
<> 128:9bcdf88f62b0 8873 #define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
<> 128:9bcdf88f62b0 8874 #define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
<> 128:9bcdf88f62b0 8875 #define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
<> 128:9bcdf88f62b0 8876 #define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
<> 128:9bcdf88f62b0 8877 #define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
<> 128:9bcdf88f62b0 8878 #define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
<> 128:9bcdf88f62b0 8879 #define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
<> 128:9bcdf88f62b0 8880 #define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
<> 128:9bcdf88f62b0 8881 #define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
<> 128:9bcdf88f62b0 8882 #define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
<> 128:9bcdf88f62b0 8883 #define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
<> 128:9bcdf88f62b0 8884
<> 128:9bcdf88f62b0 8885 /****************** Bits definition for GPIO_ODR register *******************/
<> 128:9bcdf88f62b0 8886 #define GPIO_ODR_OD0_Pos (0U)
<> 128:9bcdf88f62b0 8887 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 8888 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
<> 128:9bcdf88f62b0 8889 #define GPIO_ODR_OD1_Pos (1U)
<> 128:9bcdf88f62b0 8890 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 8891 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
<> 128:9bcdf88f62b0 8892 #define GPIO_ODR_OD2_Pos (2U)
<> 128:9bcdf88f62b0 8893 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 8894 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
<> 128:9bcdf88f62b0 8895 #define GPIO_ODR_OD3_Pos (3U)
<> 128:9bcdf88f62b0 8896 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 8897 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
<> 128:9bcdf88f62b0 8898 #define GPIO_ODR_OD4_Pos (4U)
<> 128:9bcdf88f62b0 8899 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 8900 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
<> 128:9bcdf88f62b0 8901 #define GPIO_ODR_OD5_Pos (5U)
<> 128:9bcdf88f62b0 8902 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 8903 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
<> 128:9bcdf88f62b0 8904 #define GPIO_ODR_OD6_Pos (6U)
<> 128:9bcdf88f62b0 8905 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 8906 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
<> 128:9bcdf88f62b0 8907 #define GPIO_ODR_OD7_Pos (7U)
<> 128:9bcdf88f62b0 8908 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 8909 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
<> 128:9bcdf88f62b0 8910 #define GPIO_ODR_OD8_Pos (8U)
<> 128:9bcdf88f62b0 8911 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 8912 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
<> 128:9bcdf88f62b0 8913 #define GPIO_ODR_OD9_Pos (9U)
<> 128:9bcdf88f62b0 8914 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 8915 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
<> 128:9bcdf88f62b0 8916 #define GPIO_ODR_OD10_Pos (10U)
<> 128:9bcdf88f62b0 8917 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 8918 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
<> 128:9bcdf88f62b0 8919 #define GPIO_ODR_OD11_Pos (11U)
<> 128:9bcdf88f62b0 8920 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 8921 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
<> 128:9bcdf88f62b0 8922 #define GPIO_ODR_OD12_Pos (12U)
<> 128:9bcdf88f62b0 8923 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 8924 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
<> 128:9bcdf88f62b0 8925 #define GPIO_ODR_OD13_Pos (13U)
<> 128:9bcdf88f62b0 8926 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 8927 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
<> 128:9bcdf88f62b0 8928 #define GPIO_ODR_OD14_Pos (14U)
<> 128:9bcdf88f62b0 8929 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 8930 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
<> 128:9bcdf88f62b0 8931 #define GPIO_ODR_OD15_Pos (15U)
<> 128:9bcdf88f62b0 8932 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 8933 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
<> 128:9bcdf88f62b0 8934
<> 128:9bcdf88f62b0 8935 /* Legacy defines */
<> 128:9bcdf88f62b0 8936 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
<> 128:9bcdf88f62b0 8937 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
<> 128:9bcdf88f62b0 8938 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
<> 128:9bcdf88f62b0 8939 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
<> 128:9bcdf88f62b0 8940 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
<> 128:9bcdf88f62b0 8941 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
<> 128:9bcdf88f62b0 8942 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
<> 128:9bcdf88f62b0 8943 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
<> 128:9bcdf88f62b0 8944 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
<> 128:9bcdf88f62b0 8945 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
<> 128:9bcdf88f62b0 8946 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
<> 128:9bcdf88f62b0 8947 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
<> 128:9bcdf88f62b0 8948 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
<> 128:9bcdf88f62b0 8949 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
<> 128:9bcdf88f62b0 8950 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
<> 128:9bcdf88f62b0 8951 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
<> 128:9bcdf88f62b0 8952
<> 128:9bcdf88f62b0 8953 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
<> 128:9bcdf88f62b0 8954 #define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
<> 128:9bcdf88f62b0 8955 #define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
<> 128:9bcdf88f62b0 8956 #define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
<> 128:9bcdf88f62b0 8957 #define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
<> 128:9bcdf88f62b0 8958 #define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
<> 128:9bcdf88f62b0 8959 #define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
<> 128:9bcdf88f62b0 8960 #define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
<> 128:9bcdf88f62b0 8961 #define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
<> 128:9bcdf88f62b0 8962 #define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
<> 128:9bcdf88f62b0 8963 #define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
<> 128:9bcdf88f62b0 8964 #define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
<> 128:9bcdf88f62b0 8965 #define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
<> 128:9bcdf88f62b0 8966 #define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
<> 128:9bcdf88f62b0 8967 #define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
<> 128:9bcdf88f62b0 8968 #define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
<> 128:9bcdf88f62b0 8969 #define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
<> 128:9bcdf88f62b0 8970
<> 128:9bcdf88f62b0 8971 /****************** Bits definition for GPIO_BSRR register ******************/
<> 128:9bcdf88f62b0 8972 #define GPIO_BSRR_BS0_Pos (0U)
<> 128:9bcdf88f62b0 8973 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 8974 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
<> 128:9bcdf88f62b0 8975 #define GPIO_BSRR_BS1_Pos (1U)
<> 128:9bcdf88f62b0 8976 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 8977 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
<> 128:9bcdf88f62b0 8978 #define GPIO_BSRR_BS2_Pos (2U)
<> 128:9bcdf88f62b0 8979 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 8980 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
<> 128:9bcdf88f62b0 8981 #define GPIO_BSRR_BS3_Pos (3U)
<> 128:9bcdf88f62b0 8982 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 8983 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
<> 128:9bcdf88f62b0 8984 #define GPIO_BSRR_BS4_Pos (4U)
<> 128:9bcdf88f62b0 8985 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 8986 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
<> 128:9bcdf88f62b0 8987 #define GPIO_BSRR_BS5_Pos (5U)
<> 128:9bcdf88f62b0 8988 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 8989 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
<> 128:9bcdf88f62b0 8990 #define GPIO_BSRR_BS6_Pos (6U)
<> 128:9bcdf88f62b0 8991 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 8992 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
<> 128:9bcdf88f62b0 8993 #define GPIO_BSRR_BS7_Pos (7U)
<> 128:9bcdf88f62b0 8994 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 8995 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
<> 128:9bcdf88f62b0 8996 #define GPIO_BSRR_BS8_Pos (8U)
<> 128:9bcdf88f62b0 8997 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 8998 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
<> 128:9bcdf88f62b0 8999 #define GPIO_BSRR_BS9_Pos (9U)
<> 128:9bcdf88f62b0 9000 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 9001 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
<> 128:9bcdf88f62b0 9002 #define GPIO_BSRR_BS10_Pos (10U)
<> 128:9bcdf88f62b0 9003 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 9004 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
<> 128:9bcdf88f62b0 9005 #define GPIO_BSRR_BS11_Pos (11U)
<> 128:9bcdf88f62b0 9006 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 9007 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
<> 128:9bcdf88f62b0 9008 #define GPIO_BSRR_BS12_Pos (12U)
<> 128:9bcdf88f62b0 9009 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 9010 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
<> 128:9bcdf88f62b0 9011 #define GPIO_BSRR_BS13_Pos (13U)
<> 128:9bcdf88f62b0 9012 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 9013 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
<> 128:9bcdf88f62b0 9014 #define GPIO_BSRR_BS14_Pos (14U)
<> 128:9bcdf88f62b0 9015 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 9016 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
<> 128:9bcdf88f62b0 9017 #define GPIO_BSRR_BS15_Pos (15U)
<> 128:9bcdf88f62b0 9018 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 9019 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
<> 128:9bcdf88f62b0 9020 #define GPIO_BSRR_BR0_Pos (16U)
<> 128:9bcdf88f62b0 9021 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 9022 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
<> 128:9bcdf88f62b0 9023 #define GPIO_BSRR_BR1_Pos (17U)
<> 128:9bcdf88f62b0 9024 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 9025 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
<> 128:9bcdf88f62b0 9026 #define GPIO_BSRR_BR2_Pos (18U)
<> 128:9bcdf88f62b0 9027 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 9028 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
<> 128:9bcdf88f62b0 9029 #define GPIO_BSRR_BR3_Pos (19U)
<> 128:9bcdf88f62b0 9030 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 9031 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
<> 128:9bcdf88f62b0 9032 #define GPIO_BSRR_BR4_Pos (20U)
<> 128:9bcdf88f62b0 9033 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 9034 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
<> 128:9bcdf88f62b0 9035 #define GPIO_BSRR_BR5_Pos (21U)
<> 128:9bcdf88f62b0 9036 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 9037 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
<> 128:9bcdf88f62b0 9038 #define GPIO_BSRR_BR6_Pos (22U)
<> 128:9bcdf88f62b0 9039 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 9040 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
<> 128:9bcdf88f62b0 9041 #define GPIO_BSRR_BR7_Pos (23U)
<> 128:9bcdf88f62b0 9042 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 9043 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
<> 128:9bcdf88f62b0 9044 #define GPIO_BSRR_BR8_Pos (24U)
<> 128:9bcdf88f62b0 9045 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 9046 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
<> 128:9bcdf88f62b0 9047 #define GPIO_BSRR_BR9_Pos (25U)
<> 128:9bcdf88f62b0 9048 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 9049 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
<> 128:9bcdf88f62b0 9050 #define GPIO_BSRR_BR10_Pos (26U)
<> 128:9bcdf88f62b0 9051 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 9052 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
<> 128:9bcdf88f62b0 9053 #define GPIO_BSRR_BR11_Pos (27U)
<> 128:9bcdf88f62b0 9054 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 9055 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
<> 128:9bcdf88f62b0 9056 #define GPIO_BSRR_BR12_Pos (28U)
<> 128:9bcdf88f62b0 9057 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 9058 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
<> 128:9bcdf88f62b0 9059 #define GPIO_BSRR_BR13_Pos (29U)
<> 128:9bcdf88f62b0 9060 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 9061 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
<> 128:9bcdf88f62b0 9062 #define GPIO_BSRR_BR14_Pos (30U)
<> 128:9bcdf88f62b0 9063 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 9064 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
<> 128:9bcdf88f62b0 9065 #define GPIO_BSRR_BR15_Pos (31U)
<> 128:9bcdf88f62b0 9066 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 9067 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
<> 128:9bcdf88f62b0 9068
<> 128:9bcdf88f62b0 9069 /* Legacy defines */
<> 128:9bcdf88f62b0 9070 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
<> 128:9bcdf88f62b0 9071 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
<> 128:9bcdf88f62b0 9072 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
<> 128:9bcdf88f62b0 9073 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
<> 128:9bcdf88f62b0 9074 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
<> 128:9bcdf88f62b0 9075 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
<> 128:9bcdf88f62b0 9076 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
<> 128:9bcdf88f62b0 9077 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
<> 128:9bcdf88f62b0 9078 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
<> 128:9bcdf88f62b0 9079 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
<> 128:9bcdf88f62b0 9080 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
<> 128:9bcdf88f62b0 9081 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
<> 128:9bcdf88f62b0 9082 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
<> 128:9bcdf88f62b0 9083 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
<> 128:9bcdf88f62b0 9084 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
<> 128:9bcdf88f62b0 9085 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
<> 128:9bcdf88f62b0 9086 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
<> 128:9bcdf88f62b0 9087 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
<> 128:9bcdf88f62b0 9088 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
<> 128:9bcdf88f62b0 9089 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
<> 128:9bcdf88f62b0 9090 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
<> 128:9bcdf88f62b0 9091 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
<> 128:9bcdf88f62b0 9092 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
<> 128:9bcdf88f62b0 9093 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
<> 128:9bcdf88f62b0 9094 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
<> 128:9bcdf88f62b0 9095 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
<> 128:9bcdf88f62b0 9096 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
<> 128:9bcdf88f62b0 9097 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
<> 128:9bcdf88f62b0 9098 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
<> 128:9bcdf88f62b0 9099 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
<> 128:9bcdf88f62b0 9100 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
<> 128:9bcdf88f62b0 9101 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
<> 128:9bcdf88f62b0 9102
<> 128:9bcdf88f62b0 9103 /****************** Bit definition for GPIO_LCKR register *********************/
<> 128:9bcdf88f62b0 9104 #define GPIO_LCKR_LCK0_Pos (0U)
<> 128:9bcdf88f62b0 9105 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 9106 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
<> 128:9bcdf88f62b0 9107 #define GPIO_LCKR_LCK1_Pos (1U)
<> 128:9bcdf88f62b0 9108 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 9109 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
<> 128:9bcdf88f62b0 9110 #define GPIO_LCKR_LCK2_Pos (2U)
<> 128:9bcdf88f62b0 9111 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 9112 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
<> 128:9bcdf88f62b0 9113 #define GPIO_LCKR_LCK3_Pos (3U)
<> 128:9bcdf88f62b0 9114 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 9115 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
<> 128:9bcdf88f62b0 9116 #define GPIO_LCKR_LCK4_Pos (4U)
<> 128:9bcdf88f62b0 9117 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 9118 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
<> 128:9bcdf88f62b0 9119 #define GPIO_LCKR_LCK5_Pos (5U)
<> 128:9bcdf88f62b0 9120 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 9121 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
<> 128:9bcdf88f62b0 9122 #define GPIO_LCKR_LCK6_Pos (6U)
<> 128:9bcdf88f62b0 9123 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 9124 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
<> 128:9bcdf88f62b0 9125 #define GPIO_LCKR_LCK7_Pos (7U)
<> 128:9bcdf88f62b0 9126 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 9127 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
<> 128:9bcdf88f62b0 9128 #define GPIO_LCKR_LCK8_Pos (8U)
<> 128:9bcdf88f62b0 9129 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 9130 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
<> 128:9bcdf88f62b0 9131 #define GPIO_LCKR_LCK9_Pos (9U)
<> 128:9bcdf88f62b0 9132 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 9133 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
<> 128:9bcdf88f62b0 9134 #define GPIO_LCKR_LCK10_Pos (10U)
<> 128:9bcdf88f62b0 9135 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 9136 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
<> 128:9bcdf88f62b0 9137 #define GPIO_LCKR_LCK11_Pos (11U)
<> 128:9bcdf88f62b0 9138 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 9139 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
<> 128:9bcdf88f62b0 9140 #define GPIO_LCKR_LCK12_Pos (12U)
<> 128:9bcdf88f62b0 9141 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 9142 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
<> 128:9bcdf88f62b0 9143 #define GPIO_LCKR_LCK13_Pos (13U)
<> 128:9bcdf88f62b0 9144 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 9145 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
<> 128:9bcdf88f62b0 9146 #define GPIO_LCKR_LCK14_Pos (14U)
<> 128:9bcdf88f62b0 9147 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 9148 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
<> 128:9bcdf88f62b0 9149 #define GPIO_LCKR_LCK15_Pos (15U)
<> 128:9bcdf88f62b0 9150 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 9151 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
<> 128:9bcdf88f62b0 9152 #define GPIO_LCKR_LCKK_Pos (16U)
<> 128:9bcdf88f62b0 9153 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 9154 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
<> 128:9bcdf88f62b0 9155
<> 128:9bcdf88f62b0 9156 /****************** Bit definition for GPIO_AFRL register *********************/
<> 128:9bcdf88f62b0 9157 #define GPIO_AFRL_AFSEL0_Pos (0U)
<> 128:9bcdf88f62b0 9158 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 9159 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
<> 128:9bcdf88f62b0 9160 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 9161 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 9162 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 9163 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 9164 #define GPIO_AFRL_AFSEL1_Pos (4U)
<> 128:9bcdf88f62b0 9165 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
<> 128:9bcdf88f62b0 9166 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
<> 128:9bcdf88f62b0 9167 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 9168 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 9169 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 9170 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 9171 #define GPIO_AFRL_AFSEL2_Pos (8U)
<> 128:9bcdf88f62b0 9172 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
<> 128:9bcdf88f62b0 9173 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
<> 128:9bcdf88f62b0 9174 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 9175 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 9176 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 9177 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 9178 #define GPIO_AFRL_AFSEL3_Pos (12U)
<> 128:9bcdf88f62b0 9179 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
<> 128:9bcdf88f62b0 9180 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
<> 128:9bcdf88f62b0 9181 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 9182 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 9183 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 9184 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 9185 #define GPIO_AFRL_AFSEL4_Pos (16U)
<> 128:9bcdf88f62b0 9186 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
<> 128:9bcdf88f62b0 9187 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
<> 128:9bcdf88f62b0 9188 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 9189 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 9190 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 9191 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 9192 #define GPIO_AFRL_AFSEL5_Pos (20U)
<> 128:9bcdf88f62b0 9193 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
<> 128:9bcdf88f62b0 9194 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
<> 128:9bcdf88f62b0 9195 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 9196 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 9197 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 9198 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 9199 #define GPIO_AFRL_AFSEL6_Pos (24U)
<> 128:9bcdf88f62b0 9200 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
<> 128:9bcdf88f62b0 9201 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
<> 128:9bcdf88f62b0 9202 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 9203 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 9204 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 9205 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 9206 #define GPIO_AFRL_AFSEL7_Pos (28U)
<> 128:9bcdf88f62b0 9207 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
<> 128:9bcdf88f62b0 9208 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
<> 128:9bcdf88f62b0 9209 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 9210 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 9211 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 9212 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 9213
<> 128:9bcdf88f62b0 9214 /* Legacy defines */
<> 128:9bcdf88f62b0 9215 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
<> 128:9bcdf88f62b0 9216 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
<> 128:9bcdf88f62b0 9217 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
<> 128:9bcdf88f62b0 9218 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
<> 128:9bcdf88f62b0 9219 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
<> 128:9bcdf88f62b0 9220 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
<> 128:9bcdf88f62b0 9221 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
<> 128:9bcdf88f62b0 9222 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
<> 128:9bcdf88f62b0 9223
<> 128:9bcdf88f62b0 9224 /****************** Bit definition for GPIO_AFRH register *********************/
<> 128:9bcdf88f62b0 9225 #define GPIO_AFRH_AFSEL8_Pos (0U)
<> 128:9bcdf88f62b0 9226 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 9227 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
<> 128:9bcdf88f62b0 9228 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 9229 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 9230 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 9231 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 9232 #define GPIO_AFRH_AFSEL9_Pos (4U)
<> 128:9bcdf88f62b0 9233 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
<> 128:9bcdf88f62b0 9234 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
<> 128:9bcdf88f62b0 9235 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 9236 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 9237 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 9238 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 9239 #define GPIO_AFRH_AFSEL10_Pos (8U)
<> 128:9bcdf88f62b0 9240 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
<> 128:9bcdf88f62b0 9241 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
<> 128:9bcdf88f62b0 9242 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 9243 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 9244 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 9245 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 9246 #define GPIO_AFRH_AFSEL11_Pos (12U)
<> 128:9bcdf88f62b0 9247 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
<> 128:9bcdf88f62b0 9248 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
<> 128:9bcdf88f62b0 9249 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 9250 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 9251 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 9252 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 9253 #define GPIO_AFRH_AFSEL12_Pos (16U)
<> 128:9bcdf88f62b0 9254 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
<> 128:9bcdf88f62b0 9255 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
<> 128:9bcdf88f62b0 9256 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 9257 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 9258 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 9259 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 9260 #define GPIO_AFRH_AFSEL13_Pos (20U)
<> 128:9bcdf88f62b0 9261 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
<> 128:9bcdf88f62b0 9262 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
<> 128:9bcdf88f62b0 9263 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 9264 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 9265 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 9266 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 9267 #define GPIO_AFRH_AFSEL14_Pos (24U)
<> 128:9bcdf88f62b0 9268 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
<> 128:9bcdf88f62b0 9269 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
<> 128:9bcdf88f62b0 9270 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 9271 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 9272 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 9273 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 9274 #define GPIO_AFRH_AFSEL15_Pos (28U)
<> 128:9bcdf88f62b0 9275 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
<> 128:9bcdf88f62b0 9276 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
<> 128:9bcdf88f62b0 9277 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 9278 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 9279 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 9280 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 9281
<> 128:9bcdf88f62b0 9282 /* Legacy defines */
<> 128:9bcdf88f62b0 9283 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
<> 128:9bcdf88f62b0 9284 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
<> 128:9bcdf88f62b0 9285 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
<> 128:9bcdf88f62b0 9286 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
<> 128:9bcdf88f62b0 9287 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
<> 128:9bcdf88f62b0 9288 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
<> 128:9bcdf88f62b0 9289 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
<> 128:9bcdf88f62b0 9290 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
<> 128:9bcdf88f62b0 9291
<> 128:9bcdf88f62b0 9292 /****************** Bits definition for GPIO_BRR register ******************/
<> 128:9bcdf88f62b0 9293 #define GPIO_BRR_BR0_Pos (0U)
<> 128:9bcdf88f62b0 9294 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 9295 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
<> 128:9bcdf88f62b0 9296 #define GPIO_BRR_BR1_Pos (1U)
<> 128:9bcdf88f62b0 9297 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 9298 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
<> 128:9bcdf88f62b0 9299 #define GPIO_BRR_BR2_Pos (2U)
<> 128:9bcdf88f62b0 9300 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 9301 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
<> 128:9bcdf88f62b0 9302 #define GPIO_BRR_BR3_Pos (3U)
<> 128:9bcdf88f62b0 9303 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 9304 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
<> 128:9bcdf88f62b0 9305 #define GPIO_BRR_BR4_Pos (4U)
<> 128:9bcdf88f62b0 9306 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 9307 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
<> 128:9bcdf88f62b0 9308 #define GPIO_BRR_BR5_Pos (5U)
<> 128:9bcdf88f62b0 9309 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 9310 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
<> 128:9bcdf88f62b0 9311 #define GPIO_BRR_BR6_Pos (6U)
<> 128:9bcdf88f62b0 9312 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 9313 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
<> 128:9bcdf88f62b0 9314 #define GPIO_BRR_BR7_Pos (7U)
<> 128:9bcdf88f62b0 9315 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 9316 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
<> 128:9bcdf88f62b0 9317 #define GPIO_BRR_BR8_Pos (8U)
<> 128:9bcdf88f62b0 9318 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 9319 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
<> 128:9bcdf88f62b0 9320 #define GPIO_BRR_BR9_Pos (9U)
<> 128:9bcdf88f62b0 9321 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 9322 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
<> 128:9bcdf88f62b0 9323 #define GPIO_BRR_BR10_Pos (10U)
<> 128:9bcdf88f62b0 9324 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 9325 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
<> 128:9bcdf88f62b0 9326 #define GPIO_BRR_BR11_Pos (11U)
<> 128:9bcdf88f62b0 9327 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 9328 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
<> 128:9bcdf88f62b0 9329 #define GPIO_BRR_BR12_Pos (12U)
<> 128:9bcdf88f62b0 9330 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 9331 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
<> 128:9bcdf88f62b0 9332 #define GPIO_BRR_BR13_Pos (13U)
<> 128:9bcdf88f62b0 9333 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 9334 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
<> 128:9bcdf88f62b0 9335 #define GPIO_BRR_BR14_Pos (14U)
<> 128:9bcdf88f62b0 9336 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 9337 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
<> 128:9bcdf88f62b0 9338 #define GPIO_BRR_BR15_Pos (15U)
<> 128:9bcdf88f62b0 9339 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 9340 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
<> 128:9bcdf88f62b0 9341
<> 128:9bcdf88f62b0 9342 /* Legacy defines */
<> 128:9bcdf88f62b0 9343 #define GPIO_BRR_BR_0 GPIO_BRR_BR0
<> 128:9bcdf88f62b0 9344 #define GPIO_BRR_BR_1 GPIO_BRR_BR1
<> 128:9bcdf88f62b0 9345 #define GPIO_BRR_BR_2 GPIO_BRR_BR2
<> 128:9bcdf88f62b0 9346 #define GPIO_BRR_BR_3 GPIO_BRR_BR3
<> 128:9bcdf88f62b0 9347 #define GPIO_BRR_BR_4 GPIO_BRR_BR4
<> 128:9bcdf88f62b0 9348 #define GPIO_BRR_BR_5 GPIO_BRR_BR5
<> 128:9bcdf88f62b0 9349 #define GPIO_BRR_BR_6 GPIO_BRR_BR6
<> 128:9bcdf88f62b0 9350 #define GPIO_BRR_BR_7 GPIO_BRR_BR7
<> 128:9bcdf88f62b0 9351 #define GPIO_BRR_BR_8 GPIO_BRR_BR8
<> 128:9bcdf88f62b0 9352 #define GPIO_BRR_BR_9 GPIO_BRR_BR9
<> 128:9bcdf88f62b0 9353 #define GPIO_BRR_BR_10 GPIO_BRR_BR10
<> 128:9bcdf88f62b0 9354 #define GPIO_BRR_BR_11 GPIO_BRR_BR11
<> 128:9bcdf88f62b0 9355 #define GPIO_BRR_BR_12 GPIO_BRR_BR12
<> 128:9bcdf88f62b0 9356 #define GPIO_BRR_BR_13 GPIO_BRR_BR13
<> 128:9bcdf88f62b0 9357 #define GPIO_BRR_BR_14 GPIO_BRR_BR14
<> 128:9bcdf88f62b0 9358 #define GPIO_BRR_BR_15 GPIO_BRR_BR15
<> 128:9bcdf88f62b0 9359
<> 128:9bcdf88f62b0 9360
<> 128:9bcdf88f62b0 9361 /****************** Bits definition for GPIO_ASCR register *******************/
<> 128:9bcdf88f62b0 9362 #define GPIO_ASCR_ASC0_Pos (0U)
<> 128:9bcdf88f62b0 9363 #define GPIO_ASCR_ASC0_Msk (0x1U << GPIO_ASCR_ASC0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 9364 #define GPIO_ASCR_ASC0 GPIO_ASCR_ASC0_Msk
<> 128:9bcdf88f62b0 9365 #define GPIO_ASCR_ASC1_Pos (1U)
<> 128:9bcdf88f62b0 9366 #define GPIO_ASCR_ASC1_Msk (0x1U << GPIO_ASCR_ASC1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 9367 #define GPIO_ASCR_ASC1 GPIO_ASCR_ASC1_Msk
<> 128:9bcdf88f62b0 9368 #define GPIO_ASCR_ASC2_Pos (2U)
<> 128:9bcdf88f62b0 9369 #define GPIO_ASCR_ASC2_Msk (0x1U << GPIO_ASCR_ASC2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 9370 #define GPIO_ASCR_ASC2 GPIO_ASCR_ASC2_Msk
<> 128:9bcdf88f62b0 9371 #define GPIO_ASCR_ASC3_Pos (3U)
<> 128:9bcdf88f62b0 9372 #define GPIO_ASCR_ASC3_Msk (0x1U << GPIO_ASCR_ASC3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 9373 #define GPIO_ASCR_ASC3 GPIO_ASCR_ASC3_Msk
<> 128:9bcdf88f62b0 9374 #define GPIO_ASCR_ASC4_Pos (4U)
<> 128:9bcdf88f62b0 9375 #define GPIO_ASCR_ASC4_Msk (0x1U << GPIO_ASCR_ASC4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 9376 #define GPIO_ASCR_ASC4 GPIO_ASCR_ASC4_Msk
<> 128:9bcdf88f62b0 9377 #define GPIO_ASCR_ASC5_Pos (5U)
<> 128:9bcdf88f62b0 9378 #define GPIO_ASCR_ASC5_Msk (0x1U << GPIO_ASCR_ASC5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 9379 #define GPIO_ASCR_ASC5 GPIO_ASCR_ASC5_Msk
<> 128:9bcdf88f62b0 9380 #define GPIO_ASCR_ASC6_Pos (6U)
<> 128:9bcdf88f62b0 9381 #define GPIO_ASCR_ASC6_Msk (0x1U << GPIO_ASCR_ASC6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 9382 #define GPIO_ASCR_ASC6 GPIO_ASCR_ASC6_Msk
<> 128:9bcdf88f62b0 9383 #define GPIO_ASCR_ASC7_Pos (7U)
<> 128:9bcdf88f62b0 9384 #define GPIO_ASCR_ASC7_Msk (0x1U << GPIO_ASCR_ASC7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 9385 #define GPIO_ASCR_ASC7 GPIO_ASCR_ASC7_Msk
<> 128:9bcdf88f62b0 9386 #define GPIO_ASCR_ASC8_Pos (8U)
<> 128:9bcdf88f62b0 9387 #define GPIO_ASCR_ASC8_Msk (0x1U << GPIO_ASCR_ASC8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 9388 #define GPIO_ASCR_ASC8 GPIO_ASCR_ASC8_Msk
<> 128:9bcdf88f62b0 9389 #define GPIO_ASCR_ASC9_Pos (9U)
<> 128:9bcdf88f62b0 9390 #define GPIO_ASCR_ASC9_Msk (0x1U << GPIO_ASCR_ASC9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 9391 #define GPIO_ASCR_ASC9 GPIO_ASCR_ASC9_Msk
<> 128:9bcdf88f62b0 9392 #define GPIO_ASCR_ASC10_Pos (10U)
<> 128:9bcdf88f62b0 9393 #define GPIO_ASCR_ASC10_Msk (0x1U << GPIO_ASCR_ASC10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 9394 #define GPIO_ASCR_ASC10 GPIO_ASCR_ASC10_Msk
<> 128:9bcdf88f62b0 9395 #define GPIO_ASCR_ASC11_Pos (11U)
<> 128:9bcdf88f62b0 9396 #define GPIO_ASCR_ASC11_Msk (0x1U << GPIO_ASCR_ASC11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 9397 #define GPIO_ASCR_ASC11 GPIO_ASCR_ASC11_Msk
<> 128:9bcdf88f62b0 9398 #define GPIO_ASCR_ASC12_Pos (12U)
<> 128:9bcdf88f62b0 9399 #define GPIO_ASCR_ASC12_Msk (0x1U << GPIO_ASCR_ASC12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 9400 #define GPIO_ASCR_ASC12 GPIO_ASCR_ASC12_Msk
<> 128:9bcdf88f62b0 9401 #define GPIO_ASCR_ASC13_Pos (13U)
<> 128:9bcdf88f62b0 9402 #define GPIO_ASCR_ASC13_Msk (0x1U << GPIO_ASCR_ASC13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 9403 #define GPIO_ASCR_ASC13 GPIO_ASCR_ASC13_Msk
<> 128:9bcdf88f62b0 9404 #define GPIO_ASCR_ASC14_Pos (14U)
<> 128:9bcdf88f62b0 9405 #define GPIO_ASCR_ASC14_Msk (0x1U << GPIO_ASCR_ASC14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 9406 #define GPIO_ASCR_ASC14 GPIO_ASCR_ASC14_Msk
<> 128:9bcdf88f62b0 9407 #define GPIO_ASCR_ASC15_Pos (15U)
<> 128:9bcdf88f62b0 9408 #define GPIO_ASCR_ASC15_Msk (0x1U << GPIO_ASCR_ASC15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 9409 #define GPIO_ASCR_ASC15 GPIO_ASCR_ASC15_Msk
<> 128:9bcdf88f62b0 9410
<> 128:9bcdf88f62b0 9411 /* Legacy defines */
<> 128:9bcdf88f62b0 9412 #define GPIO_ASCR_EN_0 GPIO_ASCR_ASC0
<> 128:9bcdf88f62b0 9413 #define GPIO_ASCR_EN_1 GPIO_ASCR_ASC1
<> 128:9bcdf88f62b0 9414 #define GPIO_ASCR_EN_2 GPIO_ASCR_ASC2
<> 128:9bcdf88f62b0 9415 #define GPIO_ASCR_EN_3 GPIO_ASCR_ASC3
<> 128:9bcdf88f62b0 9416 #define GPIO_ASCR_EN_4 GPIO_ASCR_ASC4
<> 128:9bcdf88f62b0 9417 #define GPIO_ASCR_EN_5 GPIO_ASCR_ASC5
<> 128:9bcdf88f62b0 9418 #define GPIO_ASCR_EN_6 GPIO_ASCR_ASC6
<> 128:9bcdf88f62b0 9419 #define GPIO_ASCR_EN_7 GPIO_ASCR_ASC7
<> 128:9bcdf88f62b0 9420 #define GPIO_ASCR_EN_8 GPIO_ASCR_ASC8
<> 128:9bcdf88f62b0 9421 #define GPIO_ASCR_EN_9 GPIO_ASCR_ASC9
<> 128:9bcdf88f62b0 9422 #define GPIO_ASCR_EN_10 GPIO_ASCR_ASC10
<> 128:9bcdf88f62b0 9423 #define GPIO_ASCR_EN_11 GPIO_ASCR_ASC11
<> 128:9bcdf88f62b0 9424 #define GPIO_ASCR_EN_12 GPIO_ASCR_ASC12
<> 128:9bcdf88f62b0 9425 #define GPIO_ASCR_EN_13 GPIO_ASCR_ASC13
<> 128:9bcdf88f62b0 9426 #define GPIO_ASCR_EN_14 GPIO_ASCR_ASC14
<> 128:9bcdf88f62b0 9427 #define GPIO_ASCR_EN_15 GPIO_ASCR_ASC15
<> 128:9bcdf88f62b0 9428
<> 128:9bcdf88f62b0 9429 /******************************************************************************/
<> 128:9bcdf88f62b0 9430 /* */
<> 128:9bcdf88f62b0 9431 /* Inter-integrated Circuit Interface (I2C) */
<> 128:9bcdf88f62b0 9432 /* */
<> 128:9bcdf88f62b0 9433 /******************************************************************************/
<> 128:9bcdf88f62b0 9434 /******************* Bit definition for I2C_CR1 register *******************/
<> 128:9bcdf88f62b0 9435 #define I2C_CR1_PE_Pos (0U)
<> 128:9bcdf88f62b0 9436 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 9437 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
<> 128:9bcdf88f62b0 9438 #define I2C_CR1_TXIE_Pos (1U)
<> 128:9bcdf88f62b0 9439 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 9440 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
<> 128:9bcdf88f62b0 9441 #define I2C_CR1_RXIE_Pos (2U)
<> 128:9bcdf88f62b0 9442 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 9443 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
<> 128:9bcdf88f62b0 9444 #define I2C_CR1_ADDRIE_Pos (3U)
<> 128:9bcdf88f62b0 9445 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 9446 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
<> 128:9bcdf88f62b0 9447 #define I2C_CR1_NACKIE_Pos (4U)
<> 128:9bcdf88f62b0 9448 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 9449 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
<> 128:9bcdf88f62b0 9450 #define I2C_CR1_STOPIE_Pos (5U)
<> 128:9bcdf88f62b0 9451 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 9452 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
<> 128:9bcdf88f62b0 9453 #define I2C_CR1_TCIE_Pos (6U)
<> 128:9bcdf88f62b0 9454 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 9455 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
<> 128:9bcdf88f62b0 9456 #define I2C_CR1_ERRIE_Pos (7U)
<> 128:9bcdf88f62b0 9457 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 9458 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
<> 128:9bcdf88f62b0 9459 #define I2C_CR1_DNF_Pos (8U)
<> 128:9bcdf88f62b0 9460 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
<> 128:9bcdf88f62b0 9461 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
<> 128:9bcdf88f62b0 9462 #define I2C_CR1_ANFOFF_Pos (12U)
<> 128:9bcdf88f62b0 9463 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 9464 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
<> 128:9bcdf88f62b0 9465 #define I2C_CR1_SWRST_Pos (13U)
<> 128:9bcdf88f62b0 9466 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 9467 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
<> 128:9bcdf88f62b0 9468 #define I2C_CR1_TXDMAEN_Pos (14U)
<> 128:9bcdf88f62b0 9469 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 9470 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
<> 128:9bcdf88f62b0 9471 #define I2C_CR1_RXDMAEN_Pos (15U)
<> 128:9bcdf88f62b0 9472 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 9473 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
<> 128:9bcdf88f62b0 9474 #define I2C_CR1_SBC_Pos (16U)
<> 128:9bcdf88f62b0 9475 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 9476 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
<> 128:9bcdf88f62b0 9477 #define I2C_CR1_NOSTRETCH_Pos (17U)
<> 128:9bcdf88f62b0 9478 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 9479 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
<> 128:9bcdf88f62b0 9480 #define I2C_CR1_WUPEN_Pos (18U)
<> 128:9bcdf88f62b0 9481 #define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 9482 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
<> 128:9bcdf88f62b0 9483 #define I2C_CR1_GCEN_Pos (19U)
<> 128:9bcdf88f62b0 9484 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 9485 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
<> 128:9bcdf88f62b0 9486 #define I2C_CR1_SMBHEN_Pos (20U)
<> 128:9bcdf88f62b0 9487 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 9488 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
<> 128:9bcdf88f62b0 9489 #define I2C_CR1_SMBDEN_Pos (21U)
<> 128:9bcdf88f62b0 9490 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 9491 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
<> 128:9bcdf88f62b0 9492 #define I2C_CR1_ALERTEN_Pos (22U)
<> 128:9bcdf88f62b0 9493 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 9494 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
<> 128:9bcdf88f62b0 9495 #define I2C_CR1_PECEN_Pos (23U)
<> 128:9bcdf88f62b0 9496 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 9497 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
<> 128:9bcdf88f62b0 9498
<> 128:9bcdf88f62b0 9499 /****************** Bit definition for I2C_CR2 register ********************/
<> 128:9bcdf88f62b0 9500 #define I2C_CR2_SADD_Pos (0U)
<> 128:9bcdf88f62b0 9501 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
<> 128:9bcdf88f62b0 9502 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
<> 128:9bcdf88f62b0 9503 #define I2C_CR2_RD_WRN_Pos (10U)
<> 128:9bcdf88f62b0 9504 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 9505 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
<> 128:9bcdf88f62b0 9506 #define I2C_CR2_ADD10_Pos (11U)
<> 128:9bcdf88f62b0 9507 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 9508 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
<> 128:9bcdf88f62b0 9509 #define I2C_CR2_HEAD10R_Pos (12U)
<> 128:9bcdf88f62b0 9510 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 9511 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
<> 128:9bcdf88f62b0 9512 #define I2C_CR2_START_Pos (13U)
<> 128:9bcdf88f62b0 9513 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 9514 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
<> 128:9bcdf88f62b0 9515 #define I2C_CR2_STOP_Pos (14U)
<> 128:9bcdf88f62b0 9516 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 9517 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
<> 128:9bcdf88f62b0 9518 #define I2C_CR2_NACK_Pos (15U)
<> 128:9bcdf88f62b0 9519 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 9520 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
<> 128:9bcdf88f62b0 9521 #define I2C_CR2_NBYTES_Pos (16U)
<> 128:9bcdf88f62b0 9522 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 9523 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
<> 128:9bcdf88f62b0 9524 #define I2C_CR2_RELOAD_Pos (24U)
<> 128:9bcdf88f62b0 9525 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 9526 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
<> 128:9bcdf88f62b0 9527 #define I2C_CR2_AUTOEND_Pos (25U)
<> 128:9bcdf88f62b0 9528 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 9529 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
<> 128:9bcdf88f62b0 9530 #define I2C_CR2_PECBYTE_Pos (26U)
<> 128:9bcdf88f62b0 9531 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 9532 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
<> 128:9bcdf88f62b0 9533
<> 128:9bcdf88f62b0 9534 /******************* Bit definition for I2C_OAR1 register ******************/
<> 128:9bcdf88f62b0 9535 #define I2C_OAR1_OA1_Pos (0U)
<> 128:9bcdf88f62b0 9536 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
<> 128:9bcdf88f62b0 9537 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
<> 128:9bcdf88f62b0 9538 #define I2C_OAR1_OA1MODE_Pos (10U)
<> 128:9bcdf88f62b0 9539 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 9540 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
<> 128:9bcdf88f62b0 9541 #define I2C_OAR1_OA1EN_Pos (15U)
<> 128:9bcdf88f62b0 9542 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 9543 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
<> 128:9bcdf88f62b0 9544
<> 128:9bcdf88f62b0 9545 /******************* Bit definition for I2C_OAR2 register ******************/
<> 128:9bcdf88f62b0 9546 #define I2C_OAR2_OA2_Pos (1U)
<> 128:9bcdf88f62b0 9547 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
<> 128:9bcdf88f62b0 9548 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
<> 128:9bcdf88f62b0 9549 #define I2C_OAR2_OA2MSK_Pos (8U)
<> 128:9bcdf88f62b0 9550 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
<> 128:9bcdf88f62b0 9551 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
<> 128:9bcdf88f62b0 9552 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
<> 128:9bcdf88f62b0 9553 #define I2C_OAR2_OA2MASK01_Pos (8U)
<> 128:9bcdf88f62b0 9554 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 9555 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
<> 128:9bcdf88f62b0 9556 #define I2C_OAR2_OA2MASK02_Pos (9U)
<> 128:9bcdf88f62b0 9557 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 9558 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
<> 128:9bcdf88f62b0 9559 #define I2C_OAR2_OA2MASK03_Pos (8U)
<> 128:9bcdf88f62b0 9560 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
<> 128:9bcdf88f62b0 9561 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
<> 128:9bcdf88f62b0 9562 #define I2C_OAR2_OA2MASK04_Pos (10U)
<> 128:9bcdf88f62b0 9563 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 9564 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
<> 128:9bcdf88f62b0 9565 #define I2C_OAR2_OA2MASK05_Pos (8U)
<> 128:9bcdf88f62b0 9566 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
<> 128:9bcdf88f62b0 9567 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
<> 128:9bcdf88f62b0 9568 #define I2C_OAR2_OA2MASK06_Pos (9U)
<> 128:9bcdf88f62b0 9569 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
<> 128:9bcdf88f62b0 9570 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
<> 128:9bcdf88f62b0 9571 #define I2C_OAR2_OA2MASK07_Pos (8U)
<> 128:9bcdf88f62b0 9572 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
<> 128:9bcdf88f62b0 9573 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
<> 128:9bcdf88f62b0 9574 #define I2C_OAR2_OA2EN_Pos (15U)
<> 128:9bcdf88f62b0 9575 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 9576 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
<> 128:9bcdf88f62b0 9577
<> 128:9bcdf88f62b0 9578 /******************* Bit definition for I2C_TIMINGR register *******************/
<> 128:9bcdf88f62b0 9579 #define I2C_TIMINGR_SCLL_Pos (0U)
<> 128:9bcdf88f62b0 9580 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 9581 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
<> 128:9bcdf88f62b0 9582 #define I2C_TIMINGR_SCLH_Pos (8U)
<> 128:9bcdf88f62b0 9583 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 9584 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
<> 128:9bcdf88f62b0 9585 #define I2C_TIMINGR_SDADEL_Pos (16U)
<> 128:9bcdf88f62b0 9586 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
<> 128:9bcdf88f62b0 9587 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
<> 128:9bcdf88f62b0 9588 #define I2C_TIMINGR_SCLDEL_Pos (20U)
<> 128:9bcdf88f62b0 9589 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
<> 128:9bcdf88f62b0 9590 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
<> 128:9bcdf88f62b0 9591 #define I2C_TIMINGR_PRESC_Pos (28U)
<> 128:9bcdf88f62b0 9592 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
<> 128:9bcdf88f62b0 9593 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
<> 128:9bcdf88f62b0 9594
<> 128:9bcdf88f62b0 9595 /******************* Bit definition for I2C_TIMEOUTR register *******************/
<> 128:9bcdf88f62b0 9596 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
<> 128:9bcdf88f62b0 9597 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
<> 128:9bcdf88f62b0 9598 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
<> 128:9bcdf88f62b0 9599 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
<> 128:9bcdf88f62b0 9600 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 9601 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
<> 128:9bcdf88f62b0 9602 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
<> 128:9bcdf88f62b0 9603 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 9604 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
<> 128:9bcdf88f62b0 9605 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
<> 128:9bcdf88f62b0 9606 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
<> 128:9bcdf88f62b0 9607 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
<> 128:9bcdf88f62b0 9608 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
<> 128:9bcdf88f62b0 9609 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 9610 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
<> 128:9bcdf88f62b0 9611
<> 128:9bcdf88f62b0 9612 /****************** Bit definition for I2C_ISR register *********************/
<> 128:9bcdf88f62b0 9613 #define I2C_ISR_TXE_Pos (0U)
<> 128:9bcdf88f62b0 9614 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 9615 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
<> 128:9bcdf88f62b0 9616 #define I2C_ISR_TXIS_Pos (1U)
<> 128:9bcdf88f62b0 9617 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 9618 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
<> 128:9bcdf88f62b0 9619 #define I2C_ISR_RXNE_Pos (2U)
<> 128:9bcdf88f62b0 9620 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 9621 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
<> 128:9bcdf88f62b0 9622 #define I2C_ISR_ADDR_Pos (3U)
<> 128:9bcdf88f62b0 9623 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 9624 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
<> 128:9bcdf88f62b0 9625 #define I2C_ISR_NACKF_Pos (4U)
<> 128:9bcdf88f62b0 9626 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 9627 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
<> 128:9bcdf88f62b0 9628 #define I2C_ISR_STOPF_Pos (5U)
<> 128:9bcdf88f62b0 9629 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 9630 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
<> 128:9bcdf88f62b0 9631 #define I2C_ISR_TC_Pos (6U)
<> 128:9bcdf88f62b0 9632 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 9633 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
<> 128:9bcdf88f62b0 9634 #define I2C_ISR_TCR_Pos (7U)
<> 128:9bcdf88f62b0 9635 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 9636 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
<> 128:9bcdf88f62b0 9637 #define I2C_ISR_BERR_Pos (8U)
<> 128:9bcdf88f62b0 9638 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 9639 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
<> 128:9bcdf88f62b0 9640 #define I2C_ISR_ARLO_Pos (9U)
<> 128:9bcdf88f62b0 9641 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 9642 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
<> 128:9bcdf88f62b0 9643 #define I2C_ISR_OVR_Pos (10U)
<> 128:9bcdf88f62b0 9644 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 9645 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
<> 128:9bcdf88f62b0 9646 #define I2C_ISR_PECERR_Pos (11U)
<> 128:9bcdf88f62b0 9647 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 9648 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
<> 128:9bcdf88f62b0 9649 #define I2C_ISR_TIMEOUT_Pos (12U)
<> 128:9bcdf88f62b0 9650 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 9651 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
<> 128:9bcdf88f62b0 9652 #define I2C_ISR_ALERT_Pos (13U)
<> 128:9bcdf88f62b0 9653 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 9654 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
<> 128:9bcdf88f62b0 9655 #define I2C_ISR_BUSY_Pos (15U)
<> 128:9bcdf88f62b0 9656 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 9657 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
<> 128:9bcdf88f62b0 9658 #define I2C_ISR_DIR_Pos (16U)
<> 128:9bcdf88f62b0 9659 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 9660 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
<> 128:9bcdf88f62b0 9661 #define I2C_ISR_ADDCODE_Pos (17U)
<> 128:9bcdf88f62b0 9662 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
<> 128:9bcdf88f62b0 9663 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
<> 128:9bcdf88f62b0 9664
<> 128:9bcdf88f62b0 9665 /****************** Bit definition for I2C_ICR register *********************/
<> 128:9bcdf88f62b0 9666 #define I2C_ICR_ADDRCF_Pos (3U)
<> 128:9bcdf88f62b0 9667 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 9668 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
<> 128:9bcdf88f62b0 9669 #define I2C_ICR_NACKCF_Pos (4U)
<> 128:9bcdf88f62b0 9670 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 9671 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
<> 128:9bcdf88f62b0 9672 #define I2C_ICR_STOPCF_Pos (5U)
<> 128:9bcdf88f62b0 9673 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 9674 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
<> 128:9bcdf88f62b0 9675 #define I2C_ICR_BERRCF_Pos (8U)
<> 128:9bcdf88f62b0 9676 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 9677 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
<> 128:9bcdf88f62b0 9678 #define I2C_ICR_ARLOCF_Pos (9U)
<> 128:9bcdf88f62b0 9679 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 9680 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
<> 128:9bcdf88f62b0 9681 #define I2C_ICR_OVRCF_Pos (10U)
<> 128:9bcdf88f62b0 9682 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 9683 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
<> 128:9bcdf88f62b0 9684 #define I2C_ICR_PECCF_Pos (11U)
<> 128:9bcdf88f62b0 9685 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 9686 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
<> 128:9bcdf88f62b0 9687 #define I2C_ICR_TIMOUTCF_Pos (12U)
<> 128:9bcdf88f62b0 9688 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 9689 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
<> 128:9bcdf88f62b0 9690 #define I2C_ICR_ALERTCF_Pos (13U)
<> 128:9bcdf88f62b0 9691 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 9692 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
<> 128:9bcdf88f62b0 9693
<> 128:9bcdf88f62b0 9694 /****************** Bit definition for I2C_PECR register *********************/
<> 128:9bcdf88f62b0 9695 #define I2C_PECR_PEC_Pos (0U)
<> 128:9bcdf88f62b0 9696 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 9697 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
<> 128:9bcdf88f62b0 9698
<> 128:9bcdf88f62b0 9699 /****************** Bit definition for I2C_RXDR register *********************/
<> 128:9bcdf88f62b0 9700 #define I2C_RXDR_RXDATA_Pos (0U)
<> 128:9bcdf88f62b0 9701 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 9702 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
<> 128:9bcdf88f62b0 9703
<> 128:9bcdf88f62b0 9704 /****************** Bit definition for I2C_TXDR register *********************/
<> 128:9bcdf88f62b0 9705 #define I2C_TXDR_TXDATA_Pos (0U)
<> 128:9bcdf88f62b0 9706 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 9707 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
<> 128:9bcdf88f62b0 9708
<> 128:9bcdf88f62b0 9709 /******************************************************************************/
<> 128:9bcdf88f62b0 9710 /* */
<> 128:9bcdf88f62b0 9711 /* Independent WATCHDOG */
<> 128:9bcdf88f62b0 9712 /* */
<> 128:9bcdf88f62b0 9713 /******************************************************************************/
<> 128:9bcdf88f62b0 9714 /******************* Bit definition for IWDG_KR register ********************/
<> 128:9bcdf88f62b0 9715 #define IWDG_KR_KEY_Pos (0U)
<> 128:9bcdf88f62b0 9716 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 9717 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
<> 128:9bcdf88f62b0 9718
<> 128:9bcdf88f62b0 9719 /******************* Bit definition for IWDG_PR register ********************/
<> 128:9bcdf88f62b0 9720 #define IWDG_PR_PR_Pos (0U)
<> 128:9bcdf88f62b0 9721 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
<> 128:9bcdf88f62b0 9722 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
<> 128:9bcdf88f62b0 9723 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 9724 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 9725 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 9726
<> 128:9bcdf88f62b0 9727 /******************* Bit definition for IWDG_RLR register *******************/
<> 128:9bcdf88f62b0 9728 #define IWDG_RLR_RL_Pos (0U)
<> 128:9bcdf88f62b0 9729 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
<> 128:9bcdf88f62b0 9730 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
<> 128:9bcdf88f62b0 9731
<> 128:9bcdf88f62b0 9732 /******************* Bit definition for IWDG_SR register ********************/
<> 128:9bcdf88f62b0 9733 #define IWDG_SR_PVU_Pos (0U)
<> 128:9bcdf88f62b0 9734 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 9735 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
<> 128:9bcdf88f62b0 9736 #define IWDG_SR_RVU_Pos (1U)
<> 128:9bcdf88f62b0 9737 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 9738 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
<> 128:9bcdf88f62b0 9739 #define IWDG_SR_WVU_Pos (2U)
<> 128:9bcdf88f62b0 9740 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 9741 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
<> 128:9bcdf88f62b0 9742
<> 128:9bcdf88f62b0 9743 /******************* Bit definition for IWDG_KR register ********************/
<> 128:9bcdf88f62b0 9744 #define IWDG_WINR_WIN_Pos (0U)
<> 128:9bcdf88f62b0 9745 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
<> 128:9bcdf88f62b0 9746 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
<> 128:9bcdf88f62b0 9747
<> 128:9bcdf88f62b0 9748 /******************************************************************************/
<> 128:9bcdf88f62b0 9749 /* */
<> 128:9bcdf88f62b0 9750 /* Firewall */
<> 128:9bcdf88f62b0 9751 /* */
<> 128:9bcdf88f62b0 9752 /******************************************************************************/
<> 128:9bcdf88f62b0 9753
<> 128:9bcdf88f62b0 9754 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL;LSSA;LSL register */
<> 128:9bcdf88f62b0 9755 #define FW_CSSA_ADD_Pos (8U)
<> 128:9bcdf88f62b0 9756 #define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
<> 128:9bcdf88f62b0 9757 #define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
<> 128:9bcdf88f62b0 9758 #define FW_CSL_LENG_Pos (8U)
<> 128:9bcdf88f62b0 9759 #define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
<> 128:9bcdf88f62b0 9760 #define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
<> 128:9bcdf88f62b0 9761 #define FW_NVDSSA_ADD_Pos (8U)
<> 128:9bcdf88f62b0 9762 #define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
<> 128:9bcdf88f62b0 9763 #define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
<> 128:9bcdf88f62b0 9764 #define FW_NVDSL_LENG_Pos (8U)
<> 128:9bcdf88f62b0 9765 #define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
<> 128:9bcdf88f62b0 9766 #define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
<> 128:9bcdf88f62b0 9767 #define FW_VDSSA_ADD_Pos (6U)
<> 128:9bcdf88f62b0 9768 #define FW_VDSSA_ADD_Msk (0x7FFU << FW_VDSSA_ADD_Pos) /*!< 0x0001FFC0 */
<> 128:9bcdf88f62b0 9769 #define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
<> 128:9bcdf88f62b0 9770 #define FW_VDSL_LENG_Pos (6U)
<> 128:9bcdf88f62b0 9771 #define FW_VDSL_LENG_Msk (0x7FFU << FW_VDSL_LENG_Pos) /*!< 0x0001FFC0 */
<> 128:9bcdf88f62b0 9772 #define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
<> 128:9bcdf88f62b0 9773 #define FW_LSSA_ADD_Pos (7U)
<> 128:9bcdf88f62b0 9774 #define FW_LSSA_ADD_Msk (0xFFFU << FW_LSSA_ADD_Pos) /*!< 0x0007FF80 */
<> 128:9bcdf88f62b0 9775 #define FW_LSSA_ADD FW_LSSA_ADD_Msk /*!< Library Segment Start Address*/
<> 128:9bcdf88f62b0 9776 #define FW_LSL_LENG_Pos (7U)
<> 128:9bcdf88f62b0 9777 #define FW_LSL_LENG_Msk (0xFFFU << FW_LSL_LENG_Pos) /*!< 0x0007FF80 */
<> 128:9bcdf88f62b0 9778 #define FW_LSL_LENG FW_LSL_LENG_Msk /*!< Library Segment Length*/
<> 128:9bcdf88f62b0 9779
<> 128:9bcdf88f62b0 9780 /**************************Bit definition for CR register *********************/
<> 128:9bcdf88f62b0 9781 #define FW_CR_FPA_Pos (0U)
<> 128:9bcdf88f62b0 9782 #define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 9783 #define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
<> 128:9bcdf88f62b0 9784 #define FW_CR_VDS_Pos (1U)
<> 128:9bcdf88f62b0 9785 #define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 9786 #define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
<> 128:9bcdf88f62b0 9787 #define FW_CR_VDE_Pos (2U)
<> 128:9bcdf88f62b0 9788 #define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 9789 #define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
<> 128:9bcdf88f62b0 9790
<> 128:9bcdf88f62b0 9791 /******************************************************************************/
<> 128:9bcdf88f62b0 9792 /* */
<> 128:9bcdf88f62b0 9793 /* Power Control */
<> 128:9bcdf88f62b0 9794 /* */
<> 128:9bcdf88f62b0 9795 /******************************************************************************/
<> 128:9bcdf88f62b0 9796
<> 128:9bcdf88f62b0 9797 /******************** Bit definition for PWR_CR1 register ********************/
<> 128:9bcdf88f62b0 9798
<> 128:9bcdf88f62b0 9799 #define PWR_CR1_LPR_Pos (14U)
<> 128:9bcdf88f62b0 9800 #define PWR_CR1_LPR_Msk (0x1U << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 9801 #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
<> 128:9bcdf88f62b0 9802 #define PWR_CR1_VOS_Pos (9U)
<> 128:9bcdf88f62b0 9803 #define PWR_CR1_VOS_Msk (0x3U << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
<> 128:9bcdf88f62b0 9804 #define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
<> 128:9bcdf88f62b0 9805 #define PWR_CR1_VOS_0 (0x1U << PWR_CR1_VOS_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 9806 #define PWR_CR1_VOS_1 (0x2U << PWR_CR1_VOS_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 9807 #define PWR_CR1_DBP_Pos (8U)
<> 128:9bcdf88f62b0 9808 #define PWR_CR1_DBP_Msk (0x1U << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 9809 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
<> 128:9bcdf88f62b0 9810 #define PWR_CR1_LPMS_Pos (0U)
<> 128:9bcdf88f62b0 9811 #define PWR_CR1_LPMS_Msk (0x7U << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
<> 128:9bcdf88f62b0 9812 #define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
<> 128:9bcdf88f62b0 9813 #define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */
<> 128:9bcdf88f62b0 9814 #define PWR_CR1_LPMS_STOP1_Pos (0U)
<> 128:9bcdf88f62b0 9815 #define PWR_CR1_LPMS_STOP1_Msk (0x1U << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 9816 #define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */
<> 128:9bcdf88f62b0 9817 #define PWR_CR1_LPMS_STOP2_Pos (1U)
<> 128:9bcdf88f62b0 9818 #define PWR_CR1_LPMS_STOP2_Msk (0x1U << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 9819 #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
<> 128:9bcdf88f62b0 9820 #define PWR_CR1_LPMS_STANDBY_Pos (0U)
<> 128:9bcdf88f62b0 9821 #define PWR_CR1_LPMS_STANDBY_Msk (0x3U << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 9822 #define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */
<> 128:9bcdf88f62b0 9823 #define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
<> 128:9bcdf88f62b0 9824 #define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 9825 #define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */
<> 128:9bcdf88f62b0 9826
<> 128:9bcdf88f62b0 9827
<> 128:9bcdf88f62b0 9828 /******************** Bit definition for PWR_CR2 register ********************/
<> 128:9bcdf88f62b0 9829 #define PWR_CR2_USV_Pos (10U)
<> 128:9bcdf88f62b0 9830 #define PWR_CR2_USV_Msk (0x1U << PWR_CR2_USV_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 9831 #define PWR_CR2_USV PWR_CR2_USV_Msk /*!< VDD USB Supply Valid */
<> 128:9bcdf88f62b0 9832 #define PWR_CR2_IOSV_Pos (9U)
<> 128:9bcdf88f62b0 9833 #define PWR_CR2_IOSV_Msk (0x1U << PWR_CR2_IOSV_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 9834 #define PWR_CR2_IOSV PWR_CR2_IOSV_Msk /*!< VDD IO2 independent I/Os Supply Valid */
<> 128:9bcdf88f62b0 9835 /*!< PVME Peripheral Voltage Monitor Enable */
<> 128:9bcdf88f62b0 9836 #define PWR_CR2_PVME_Pos (4U)
<> 128:9bcdf88f62b0 9837 #define PWR_CR2_PVME_Msk (0xFU << PWR_CR2_PVME_Pos) /*!< 0x000000F0 */
<> 128:9bcdf88f62b0 9838 #define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
<> 128:9bcdf88f62b0 9839 #define PWR_CR2_PVME4_Pos (7U)
<> 128:9bcdf88f62b0 9840 #define PWR_CR2_PVME4_Msk (0x1U << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 9841 #define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
<> 128:9bcdf88f62b0 9842 #define PWR_CR2_PVME3_Pos (6U)
<> 128:9bcdf88f62b0 9843 #define PWR_CR2_PVME3_Msk (0x1U << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 9844 #define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
<> 128:9bcdf88f62b0 9845 #define PWR_CR2_PVME2_Pos (5U)
<> 128:9bcdf88f62b0 9846 #define PWR_CR2_PVME2_Msk (0x1U << PWR_CR2_PVME2_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 9847 #define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk /*!< PVM 2 Enable */
<> 128:9bcdf88f62b0 9848 #define PWR_CR2_PVME1_Pos (4U)
<> 128:9bcdf88f62b0 9849 #define PWR_CR2_PVME1_Msk (0x1U << PWR_CR2_PVME1_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 9850 #define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk /*!< PVM 1 Enable */
<> 128:9bcdf88f62b0 9851 /*!< PVD level configuration */
<> 128:9bcdf88f62b0 9852 #define PWR_CR2_PLS_Pos (1U)
<> 128:9bcdf88f62b0 9853 #define PWR_CR2_PLS_Msk (0x7U << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
<> 128:9bcdf88f62b0 9854 #define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
<> 128:9bcdf88f62b0 9855 #define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
<> 128:9bcdf88f62b0 9856 #define PWR_CR2_PLS_LEV1_Pos (1U)
<> 128:9bcdf88f62b0 9857 #define PWR_CR2_PLS_LEV1_Msk (0x1U << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 9858 #define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */
<> 128:9bcdf88f62b0 9859 #define PWR_CR2_PLS_LEV2_Pos (2U)
<> 128:9bcdf88f62b0 9860 #define PWR_CR2_PLS_LEV2_Msk (0x1U << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 9861 #define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */
<> 128:9bcdf88f62b0 9862 #define PWR_CR2_PLS_LEV3_Pos (1U)
<> 128:9bcdf88f62b0 9863 #define PWR_CR2_PLS_LEV3_Msk (0x3U << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */
<> 128:9bcdf88f62b0 9864 #define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */
<> 128:9bcdf88f62b0 9865 #define PWR_CR2_PLS_LEV4_Pos (3U)
<> 128:9bcdf88f62b0 9866 #define PWR_CR2_PLS_LEV4_Msk (0x1U << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 9867 #define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */
<> 128:9bcdf88f62b0 9868 #define PWR_CR2_PLS_LEV5_Pos (1U)
<> 128:9bcdf88f62b0 9869 #define PWR_CR2_PLS_LEV5_Msk (0x5U << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */
<> 128:9bcdf88f62b0 9870 #define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */
<> 128:9bcdf88f62b0 9871 #define PWR_CR2_PLS_LEV6_Pos (2U)
<> 128:9bcdf88f62b0 9872 #define PWR_CR2_PLS_LEV6_Msk (0x3U << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */
<> 128:9bcdf88f62b0 9873 #define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */
<> 128:9bcdf88f62b0 9874 #define PWR_CR2_PLS_LEV7_Pos (1U)
<> 128:9bcdf88f62b0 9875 #define PWR_CR2_PLS_LEV7_Msk (0x7U << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */
<> 128:9bcdf88f62b0 9876 #define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */
<> 128:9bcdf88f62b0 9877 #define PWR_CR2_PVDE_Pos (0U)
<> 128:9bcdf88f62b0 9878 #define PWR_CR2_PVDE_Msk (0x1U << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 9879 #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
<> 128:9bcdf88f62b0 9880
<> 128:9bcdf88f62b0 9881 /******************** Bit definition for PWR_CR3 register ********************/
<> 128:9bcdf88f62b0 9882 #define PWR_CR3_EIWF_Pos (15U)
<> 128:9bcdf88f62b0 9883 #define PWR_CR3_EIWF_Msk (0x1U << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 9884 #define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
<> 128:9bcdf88f62b0 9885 #define PWR_CR3_APC_Pos (10U)
<> 128:9bcdf88f62b0 9886 #define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 9887 #define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
<> 128:9bcdf88f62b0 9888 #define PWR_CR3_RRS_Pos (8U)
<> 128:9bcdf88f62b0 9889 #define PWR_CR3_RRS_Msk (0x1U << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 9890 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */
<> 128:9bcdf88f62b0 9891 #define PWR_CR3_EWUP5_Pos (4U)
<> 128:9bcdf88f62b0 9892 #define PWR_CR3_EWUP5_Msk (0x1U << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 9893 #define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
<> 128:9bcdf88f62b0 9894 #define PWR_CR3_EWUP4_Pos (3U)
<> 128:9bcdf88f62b0 9895 #define PWR_CR3_EWUP4_Msk (0x1U << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 9896 #define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
<> 128:9bcdf88f62b0 9897 #define PWR_CR3_EWUP3_Pos (2U)
<> 128:9bcdf88f62b0 9898 #define PWR_CR3_EWUP3_Msk (0x1U << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 9899 #define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
<> 128:9bcdf88f62b0 9900 #define PWR_CR3_EWUP2_Pos (1U)
<> 128:9bcdf88f62b0 9901 #define PWR_CR3_EWUP2_Msk (0x1U << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 9902 #define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
<> 128:9bcdf88f62b0 9903 #define PWR_CR3_EWUP1_Pos (0U)
<> 128:9bcdf88f62b0 9904 #define PWR_CR3_EWUP1_Msk (0x1U << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 9905 #define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
<> 128:9bcdf88f62b0 9906 #define PWR_CR3_EWUP_Pos (0U)
<> 128:9bcdf88f62b0 9907 #define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
<> 128:9bcdf88f62b0 9908 #define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
<> 128:9bcdf88f62b0 9909
<> 128:9bcdf88f62b0 9910 /******************** Bit definition for PWR_CR4 register ********************/
<> 128:9bcdf88f62b0 9911 #define PWR_CR4_VBRS_Pos (9U)
<> 128:9bcdf88f62b0 9912 #define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 9913 #define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
<> 128:9bcdf88f62b0 9914 #define PWR_CR4_VBE_Pos (8U)
<> 128:9bcdf88f62b0 9915 #define PWR_CR4_VBE_Msk (0x1U << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 9916 #define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
<> 128:9bcdf88f62b0 9917 #define PWR_CR4_WP5_Pos (4U)
<> 128:9bcdf88f62b0 9918 #define PWR_CR4_WP5_Msk (0x1U << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 9919 #define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
<> 128:9bcdf88f62b0 9920 #define PWR_CR4_WP4_Pos (3U)
<> 128:9bcdf88f62b0 9921 #define PWR_CR4_WP4_Msk (0x1U << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 9922 #define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
<> 128:9bcdf88f62b0 9923 #define PWR_CR4_WP3_Pos (2U)
<> 128:9bcdf88f62b0 9924 #define PWR_CR4_WP3_Msk (0x1U << PWR_CR4_WP3_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 9925 #define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */
<> 128:9bcdf88f62b0 9926 #define PWR_CR4_WP2_Pos (1U)
<> 128:9bcdf88f62b0 9927 #define PWR_CR4_WP2_Msk (0x1U << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 9928 #define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
<> 128:9bcdf88f62b0 9929 #define PWR_CR4_WP1_Pos (0U)
<> 128:9bcdf88f62b0 9930 #define PWR_CR4_WP1_Msk (0x1U << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 9931 #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
<> 128:9bcdf88f62b0 9932
<> 128:9bcdf88f62b0 9933 /******************** Bit definition for PWR_SR1 register ********************/
<> 128:9bcdf88f62b0 9934 #define PWR_SR1_WUFI_Pos (15U)
<> 128:9bcdf88f62b0 9935 #define PWR_SR1_WUFI_Msk (0x1U << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 9936 #define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
<> 128:9bcdf88f62b0 9937 #define PWR_SR1_SBF_Pos (8U)
<> 128:9bcdf88f62b0 9938 #define PWR_SR1_SBF_Msk (0x1U << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 9939 #define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
<> 128:9bcdf88f62b0 9940 #define PWR_SR1_WUF_Pos (0U)
<> 128:9bcdf88f62b0 9941 #define PWR_SR1_WUF_Msk (0x1FU << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
<> 128:9bcdf88f62b0 9942 #define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
<> 128:9bcdf88f62b0 9943 #define PWR_SR1_WUF5_Pos (4U)
<> 128:9bcdf88f62b0 9944 #define PWR_SR1_WUF5_Msk (0x1U << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 9945 #define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
<> 128:9bcdf88f62b0 9946 #define PWR_SR1_WUF4_Pos (3U)
<> 128:9bcdf88f62b0 9947 #define PWR_SR1_WUF4_Msk (0x1U << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 9948 #define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
<> 128:9bcdf88f62b0 9949 #define PWR_SR1_WUF3_Pos (2U)
<> 128:9bcdf88f62b0 9950 #define PWR_SR1_WUF3_Msk (0x1U << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 9951 #define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
<> 128:9bcdf88f62b0 9952 #define PWR_SR1_WUF2_Pos (1U)
<> 128:9bcdf88f62b0 9953 #define PWR_SR1_WUF2_Msk (0x1U << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 9954 #define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
<> 128:9bcdf88f62b0 9955 #define PWR_SR1_WUF1_Pos (0U)
<> 128:9bcdf88f62b0 9956 #define PWR_SR1_WUF1_Msk (0x1U << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 9957 #define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
<> 128:9bcdf88f62b0 9958
<> 128:9bcdf88f62b0 9959 /******************** Bit definition for PWR_SR2 register ********************/
<> 128:9bcdf88f62b0 9960 #define PWR_SR2_PVMO4_Pos (15U)
<> 128:9bcdf88f62b0 9961 #define PWR_SR2_PVMO4_Msk (0x1U << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 9962 #define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
<> 128:9bcdf88f62b0 9963 #define PWR_SR2_PVMO3_Pos (14U)
<> 128:9bcdf88f62b0 9964 #define PWR_SR2_PVMO3_Msk (0x1U << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 9965 #define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
<> 128:9bcdf88f62b0 9966 #define PWR_SR2_PVMO2_Pos (13U)
<> 128:9bcdf88f62b0 9967 #define PWR_SR2_PVMO2_Msk (0x1U << PWR_SR2_PVMO2_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 9968 #define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk /*!< Peripheral Voltage Monitoring Output 2 */
<> 128:9bcdf88f62b0 9969 #define PWR_SR2_PVMO1_Pos (12U)
<> 128:9bcdf88f62b0 9970 #define PWR_SR2_PVMO1_Msk (0x1U << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 9971 #define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk /*!< Peripheral Voltage Monitoring Output 1 */
<> 128:9bcdf88f62b0 9972 #define PWR_SR2_PVDO_Pos (11U)
<> 128:9bcdf88f62b0 9973 #define PWR_SR2_PVDO_Msk (0x1U << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 9974 #define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
<> 128:9bcdf88f62b0 9975 #define PWR_SR2_VOSF_Pos (10U)
<> 128:9bcdf88f62b0 9976 #define PWR_SR2_VOSF_Msk (0x1U << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 9977 #define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
<> 128:9bcdf88f62b0 9978 #define PWR_SR2_REGLPF_Pos (9U)
<> 128:9bcdf88f62b0 9979 #define PWR_SR2_REGLPF_Msk (0x1U << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 9980 #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
<> 128:9bcdf88f62b0 9981 #define PWR_SR2_REGLPS_Pos (8U)
<> 128:9bcdf88f62b0 9982 #define PWR_SR2_REGLPS_Msk (0x1U << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 9983 #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
<> 128:9bcdf88f62b0 9984
<> 128:9bcdf88f62b0 9985 /******************** Bit definition for PWR_SCR register ********************/
<> 128:9bcdf88f62b0 9986 #define PWR_SCR_CSBF_Pos (8U)
<> 128:9bcdf88f62b0 9987 #define PWR_SCR_CSBF_Msk (0x1U << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 9988 #define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
<> 128:9bcdf88f62b0 9989 #define PWR_SCR_CWUF_Pos (0U)
<> 128:9bcdf88f62b0 9990 #define PWR_SCR_CWUF_Msk (0x1FU << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
<> 128:9bcdf88f62b0 9991 #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
<> 128:9bcdf88f62b0 9992 #define PWR_SCR_CWUF5_Pos (4U)
<> 128:9bcdf88f62b0 9993 #define PWR_SCR_CWUF5_Msk (0x1U << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 9994 #define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
<> 128:9bcdf88f62b0 9995 #define PWR_SCR_CWUF4_Pos (3U)
<> 128:9bcdf88f62b0 9996 #define PWR_SCR_CWUF4_Msk (0x1U << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 9997 #define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
<> 128:9bcdf88f62b0 9998 #define PWR_SCR_CWUF3_Pos (2U)
<> 128:9bcdf88f62b0 9999 #define PWR_SCR_CWUF3_Msk (0x1U << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 10000 #define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
<> 128:9bcdf88f62b0 10001 #define PWR_SCR_CWUF2_Pos (1U)
<> 128:9bcdf88f62b0 10002 #define PWR_SCR_CWUF2_Msk (0x1U << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 10003 #define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
<> 128:9bcdf88f62b0 10004 #define PWR_SCR_CWUF1_Pos (0U)
<> 128:9bcdf88f62b0 10005 #define PWR_SCR_CWUF1_Msk (0x1U << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 10006 #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
<> 128:9bcdf88f62b0 10007
<> 128:9bcdf88f62b0 10008 /******************** Bit definition for PWR_PUCRA register ********************/
<> 128:9bcdf88f62b0 10009 #define PWR_PUCRA_PA15_Pos (15U)
<> 128:9bcdf88f62b0 10010 #define PWR_PUCRA_PA15_Msk (0x1U << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 10011 #define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */
<> 128:9bcdf88f62b0 10012 #define PWR_PUCRA_PA13_Pos (13U)
<> 128:9bcdf88f62b0 10013 #define PWR_PUCRA_PA13_Msk (0x1U << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 10014 #define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */
<> 128:9bcdf88f62b0 10015 #define PWR_PUCRA_PA12_Pos (12U)
<> 128:9bcdf88f62b0 10016 #define PWR_PUCRA_PA12_Msk (0x1U << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 10017 #define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */
<> 128:9bcdf88f62b0 10018 #define PWR_PUCRA_PA11_Pos (11U)
<> 128:9bcdf88f62b0 10019 #define PWR_PUCRA_PA11_Msk (0x1U << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 10020 #define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */
<> 128:9bcdf88f62b0 10021 #define PWR_PUCRA_PA10_Pos (10U)
<> 128:9bcdf88f62b0 10022 #define PWR_PUCRA_PA10_Msk (0x1U << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 10023 #define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */
<> 128:9bcdf88f62b0 10024 #define PWR_PUCRA_PA9_Pos (9U)
<> 128:9bcdf88f62b0 10025 #define PWR_PUCRA_PA9_Msk (0x1U << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 10026 #define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */
<> 128:9bcdf88f62b0 10027 #define PWR_PUCRA_PA8_Pos (8U)
<> 128:9bcdf88f62b0 10028 #define PWR_PUCRA_PA8_Msk (0x1U << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 10029 #define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */
<> 128:9bcdf88f62b0 10030 #define PWR_PUCRA_PA7_Pos (7U)
<> 128:9bcdf88f62b0 10031 #define PWR_PUCRA_PA7_Msk (0x1U << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 10032 #define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */
<> 128:9bcdf88f62b0 10033 #define PWR_PUCRA_PA6_Pos (6U)
<> 128:9bcdf88f62b0 10034 #define PWR_PUCRA_PA6_Msk (0x1U << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 10035 #define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */
<> 128:9bcdf88f62b0 10036 #define PWR_PUCRA_PA5_Pos (5U)
<> 128:9bcdf88f62b0 10037 #define PWR_PUCRA_PA5_Msk (0x1U << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 10038 #define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */
<> 128:9bcdf88f62b0 10039 #define PWR_PUCRA_PA4_Pos (4U)
<> 128:9bcdf88f62b0 10040 #define PWR_PUCRA_PA4_Msk (0x1U << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 10041 #define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */
<> 128:9bcdf88f62b0 10042 #define PWR_PUCRA_PA3_Pos (3U)
<> 128:9bcdf88f62b0 10043 #define PWR_PUCRA_PA3_Msk (0x1U << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 10044 #define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */
<> 128:9bcdf88f62b0 10045 #define PWR_PUCRA_PA2_Pos (2U)
<> 128:9bcdf88f62b0 10046 #define PWR_PUCRA_PA2_Msk (0x1U << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 10047 #define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */
<> 128:9bcdf88f62b0 10048 #define PWR_PUCRA_PA1_Pos (1U)
<> 128:9bcdf88f62b0 10049 #define PWR_PUCRA_PA1_Msk (0x1U << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 10050 #define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */
<> 128:9bcdf88f62b0 10051 #define PWR_PUCRA_PA0_Pos (0U)
<> 128:9bcdf88f62b0 10052 #define PWR_PUCRA_PA0_Msk (0x1U << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 10053 #define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */
<> 128:9bcdf88f62b0 10054
<> 128:9bcdf88f62b0 10055 /******************** Bit definition for PWR_PDCRA register ********************/
<> 128:9bcdf88f62b0 10056 #define PWR_PDCRA_PA14_Pos (14U)
<> 128:9bcdf88f62b0 10057 #define PWR_PDCRA_PA14_Msk (0x1U << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 10058 #define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */
<> 128:9bcdf88f62b0 10059 #define PWR_PDCRA_PA12_Pos (12U)
<> 128:9bcdf88f62b0 10060 #define PWR_PDCRA_PA12_Msk (0x1U << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 10061 #define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */
<> 128:9bcdf88f62b0 10062 #define PWR_PDCRA_PA11_Pos (11U)
<> 128:9bcdf88f62b0 10063 #define PWR_PDCRA_PA11_Msk (0x1U << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 10064 #define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */
<> 128:9bcdf88f62b0 10065 #define PWR_PDCRA_PA10_Pos (10U)
<> 128:9bcdf88f62b0 10066 #define PWR_PDCRA_PA10_Msk (0x1U << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 10067 #define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */
<> 128:9bcdf88f62b0 10068 #define PWR_PDCRA_PA9_Pos (9U)
<> 128:9bcdf88f62b0 10069 #define PWR_PDCRA_PA9_Msk (0x1U << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 10070 #define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */
<> 128:9bcdf88f62b0 10071 #define PWR_PDCRA_PA8_Pos (8U)
<> 128:9bcdf88f62b0 10072 #define PWR_PDCRA_PA8_Msk (0x1U << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 10073 #define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */
<> 128:9bcdf88f62b0 10074 #define PWR_PDCRA_PA7_Pos (7U)
<> 128:9bcdf88f62b0 10075 #define PWR_PDCRA_PA7_Msk (0x1U << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 10076 #define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */
<> 128:9bcdf88f62b0 10077 #define PWR_PDCRA_PA6_Pos (6U)
<> 128:9bcdf88f62b0 10078 #define PWR_PDCRA_PA6_Msk (0x1U << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 10079 #define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */
<> 128:9bcdf88f62b0 10080 #define PWR_PDCRA_PA5_Pos (5U)
<> 128:9bcdf88f62b0 10081 #define PWR_PDCRA_PA5_Msk (0x1U << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 10082 #define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */
<> 128:9bcdf88f62b0 10083 #define PWR_PDCRA_PA4_Pos (4U)
<> 128:9bcdf88f62b0 10084 #define PWR_PDCRA_PA4_Msk (0x1U << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 10085 #define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */
<> 128:9bcdf88f62b0 10086 #define PWR_PDCRA_PA3_Pos (3U)
<> 128:9bcdf88f62b0 10087 #define PWR_PDCRA_PA3_Msk (0x1U << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 10088 #define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */
<> 128:9bcdf88f62b0 10089 #define PWR_PDCRA_PA2_Pos (2U)
<> 128:9bcdf88f62b0 10090 #define PWR_PDCRA_PA2_Msk (0x1U << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 10091 #define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */
<> 128:9bcdf88f62b0 10092 #define PWR_PDCRA_PA1_Pos (1U)
<> 128:9bcdf88f62b0 10093 #define PWR_PDCRA_PA1_Msk (0x1U << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 10094 #define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */
<> 128:9bcdf88f62b0 10095 #define PWR_PDCRA_PA0_Pos (0U)
<> 128:9bcdf88f62b0 10096 #define PWR_PDCRA_PA0_Msk (0x1U << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 10097 #define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */
<> 128:9bcdf88f62b0 10098
<> 128:9bcdf88f62b0 10099 /******************** Bit definition for PWR_PUCRB register ********************/
<> 128:9bcdf88f62b0 10100 #define PWR_PUCRB_PB15_Pos (15U)
<> 128:9bcdf88f62b0 10101 #define PWR_PUCRB_PB15_Msk (0x1U << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 10102 #define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Port PB15 Pull-Up set */
<> 128:9bcdf88f62b0 10103 #define PWR_PUCRB_PB14_Pos (14U)
<> 128:9bcdf88f62b0 10104 #define PWR_PUCRB_PB14_Msk (0x1U << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 10105 #define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Port PB14 Pull-Up set */
<> 128:9bcdf88f62b0 10106 #define PWR_PUCRB_PB13_Pos (13U)
<> 128:9bcdf88f62b0 10107 #define PWR_PUCRB_PB13_Msk (0x1U << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 10108 #define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Port PB13 Pull-Up set */
<> 128:9bcdf88f62b0 10109 #define PWR_PUCRB_PB12_Pos (12U)
<> 128:9bcdf88f62b0 10110 #define PWR_PUCRB_PB12_Msk (0x1U << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 10111 #define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Port PB12 Pull-Up set */
<> 128:9bcdf88f62b0 10112 #define PWR_PUCRB_PB11_Pos (11U)
<> 128:9bcdf88f62b0 10113 #define PWR_PUCRB_PB11_Msk (0x1U << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 10114 #define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Port PB11 Pull-Up set */
<> 128:9bcdf88f62b0 10115 #define PWR_PUCRB_PB10_Pos (10U)
<> 128:9bcdf88f62b0 10116 #define PWR_PUCRB_PB10_Msk (0x1U << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 10117 #define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Port PB10 Pull-Up set */
<> 128:9bcdf88f62b0 10118 #define PWR_PUCRB_PB9_Pos (9U)
<> 128:9bcdf88f62b0 10119 #define PWR_PUCRB_PB9_Msk (0x1U << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 10120 #define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Port PB9 Pull-Up set */
<> 128:9bcdf88f62b0 10121 #define PWR_PUCRB_PB8_Pos (8U)
<> 128:9bcdf88f62b0 10122 #define PWR_PUCRB_PB8_Msk (0x1U << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 10123 #define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Port PB8 Pull-Up set */
<> 128:9bcdf88f62b0 10124 #define PWR_PUCRB_PB7_Pos (7U)
<> 128:9bcdf88f62b0 10125 #define PWR_PUCRB_PB7_Msk (0x1U << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 10126 #define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */
<> 128:9bcdf88f62b0 10127 #define PWR_PUCRB_PB6_Pos (6U)
<> 128:9bcdf88f62b0 10128 #define PWR_PUCRB_PB6_Msk (0x1U << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 10129 #define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */
<> 128:9bcdf88f62b0 10130 #define PWR_PUCRB_PB5_Pos (5U)
<> 128:9bcdf88f62b0 10131 #define PWR_PUCRB_PB5_Msk (0x1U << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 10132 #define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */
<> 128:9bcdf88f62b0 10133 #define PWR_PUCRB_PB4_Pos (4U)
<> 128:9bcdf88f62b0 10134 #define PWR_PUCRB_PB4_Msk (0x1U << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 10135 #define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */
<> 128:9bcdf88f62b0 10136 #define PWR_PUCRB_PB3_Pos (3U)
<> 128:9bcdf88f62b0 10137 #define PWR_PUCRB_PB3_Msk (0x1U << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 10138 #define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */
<> 128:9bcdf88f62b0 10139 #define PWR_PUCRB_PB2_Pos (2U)
<> 128:9bcdf88f62b0 10140 #define PWR_PUCRB_PB2_Msk (0x1U << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 10141 #define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Port PB2 Pull-Up set */
<> 128:9bcdf88f62b0 10142 #define PWR_PUCRB_PB1_Pos (1U)
<> 128:9bcdf88f62b0 10143 #define PWR_PUCRB_PB1_Msk (0x1U << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 10144 #define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */
<> 128:9bcdf88f62b0 10145 #define PWR_PUCRB_PB0_Pos (0U)
<> 128:9bcdf88f62b0 10146 #define PWR_PUCRB_PB0_Msk (0x1U << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 10147 #define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */
<> 128:9bcdf88f62b0 10148
<> 128:9bcdf88f62b0 10149 /******************** Bit definition for PWR_PDCRB register ********************/
<> 128:9bcdf88f62b0 10150 #define PWR_PDCRB_PB15_Pos (15U)
<> 128:9bcdf88f62b0 10151 #define PWR_PDCRB_PB15_Msk (0x1U << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 10152 #define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Port PB15 Pull-Down set */
<> 128:9bcdf88f62b0 10153 #define PWR_PDCRB_PB14_Pos (14U)
<> 128:9bcdf88f62b0 10154 #define PWR_PDCRB_PB14_Msk (0x1U << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 10155 #define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Port PB14 Pull-Down set */
<> 128:9bcdf88f62b0 10156 #define PWR_PDCRB_PB13_Pos (13U)
<> 128:9bcdf88f62b0 10157 #define PWR_PDCRB_PB13_Msk (0x1U << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 10158 #define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Port PB13 Pull-Down set */
<> 128:9bcdf88f62b0 10159 #define PWR_PDCRB_PB12_Pos (12U)
<> 128:9bcdf88f62b0 10160 #define PWR_PDCRB_PB12_Msk (0x1U << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 10161 #define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Port PB12 Pull-Down set */
<> 128:9bcdf88f62b0 10162 #define PWR_PDCRB_PB11_Pos (11U)
<> 128:9bcdf88f62b0 10163 #define PWR_PDCRB_PB11_Msk (0x1U << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 10164 #define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Port PB11 Pull-Down set */
<> 128:9bcdf88f62b0 10165 #define PWR_PDCRB_PB10_Pos (10U)
<> 128:9bcdf88f62b0 10166 #define PWR_PDCRB_PB10_Msk (0x1U << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 10167 #define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Port PB10 Pull-Down set */
<> 128:9bcdf88f62b0 10168 #define PWR_PDCRB_PB9_Pos (9U)
<> 128:9bcdf88f62b0 10169 #define PWR_PDCRB_PB9_Msk (0x1U << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 10170 #define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Port PB9 Pull-Down set */
<> 128:9bcdf88f62b0 10171 #define PWR_PDCRB_PB8_Pos (8U)
<> 128:9bcdf88f62b0 10172 #define PWR_PDCRB_PB8_Msk (0x1U << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 10173 #define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Port PB8 Pull-Down set */
<> 128:9bcdf88f62b0 10174 #define PWR_PDCRB_PB7_Pos (7U)
<> 128:9bcdf88f62b0 10175 #define PWR_PDCRB_PB7_Msk (0x1U << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 10176 #define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */
<> 128:9bcdf88f62b0 10177 #define PWR_PDCRB_PB6_Pos (6U)
<> 128:9bcdf88f62b0 10178 #define PWR_PDCRB_PB6_Msk (0x1U << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 10179 #define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */
<> 128:9bcdf88f62b0 10180 #define PWR_PDCRB_PB5_Pos (5U)
<> 128:9bcdf88f62b0 10181 #define PWR_PDCRB_PB5_Msk (0x1U << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 10182 #define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */
<> 128:9bcdf88f62b0 10183 #define PWR_PDCRB_PB3_Pos (3U)
<> 128:9bcdf88f62b0 10184 #define PWR_PDCRB_PB3_Msk (0x1U << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 10185 #define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */
<> 128:9bcdf88f62b0 10186 #define PWR_PDCRB_PB2_Pos (2U)
<> 128:9bcdf88f62b0 10187 #define PWR_PDCRB_PB2_Msk (0x1U << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 10188 #define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Port PB2 Pull-Down set */
<> 128:9bcdf88f62b0 10189 #define PWR_PDCRB_PB1_Pos (1U)
<> 128:9bcdf88f62b0 10190 #define PWR_PDCRB_PB1_Msk (0x1U << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 10191 #define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */
<> 128:9bcdf88f62b0 10192 #define PWR_PDCRB_PB0_Pos (0U)
<> 128:9bcdf88f62b0 10193 #define PWR_PDCRB_PB0_Msk (0x1U << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 10194 #define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */
<> 128:9bcdf88f62b0 10195
<> 128:9bcdf88f62b0 10196 /******************** Bit definition for PWR_PUCRC register ********************/
<> 128:9bcdf88f62b0 10197 #define PWR_PUCRC_PC15_Pos (15U)
<> 128:9bcdf88f62b0 10198 #define PWR_PUCRC_PC15_Msk (0x1U << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 10199 #define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */
<> 128:9bcdf88f62b0 10200 #define PWR_PUCRC_PC14_Pos (14U)
<> 128:9bcdf88f62b0 10201 #define PWR_PUCRC_PC14_Msk (0x1U << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 10202 #define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */
<> 128:9bcdf88f62b0 10203 #define PWR_PUCRC_PC13_Pos (13U)
<> 128:9bcdf88f62b0 10204 #define PWR_PUCRC_PC13_Msk (0x1U << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 10205 #define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Port PC13 Pull-Up set */
<> 128:9bcdf88f62b0 10206 #define PWR_PUCRC_PC12_Pos (12U)
<> 128:9bcdf88f62b0 10207 #define PWR_PUCRC_PC12_Msk (0x1U << PWR_PUCRC_PC12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 10208 #define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk /*!< Port PC12 Pull-Up set */
<> 128:9bcdf88f62b0 10209 #define PWR_PUCRC_PC11_Pos (11U)
<> 128:9bcdf88f62b0 10210 #define PWR_PUCRC_PC11_Msk (0x1U << PWR_PUCRC_PC11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 10211 #define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk /*!< Port PC11 Pull-Up set */
<> 128:9bcdf88f62b0 10212 #define PWR_PUCRC_PC10_Pos (10U)
<> 128:9bcdf88f62b0 10213 #define PWR_PUCRC_PC10_Msk (0x1U << PWR_PUCRC_PC10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 10214 #define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk /*!< Port PC10 Pull-Up set */
<> 128:9bcdf88f62b0 10215 #define PWR_PUCRC_PC9_Pos (9U)
<> 128:9bcdf88f62b0 10216 #define PWR_PUCRC_PC9_Msk (0x1U << PWR_PUCRC_PC9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 10217 #define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk /*!< Port PC9 Pull-Up set */
<> 128:9bcdf88f62b0 10218 #define PWR_PUCRC_PC8_Pos (8U)
<> 128:9bcdf88f62b0 10219 #define PWR_PUCRC_PC8_Msk (0x1U << PWR_PUCRC_PC8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 10220 #define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk /*!< Port PC8 Pull-Up set */
<> 128:9bcdf88f62b0 10221 #define PWR_PUCRC_PC7_Pos (7U)
<> 128:9bcdf88f62b0 10222 #define PWR_PUCRC_PC7_Msk (0x1U << PWR_PUCRC_PC7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 10223 #define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk /*!< Port PC7 Pull-Up set */
<> 128:9bcdf88f62b0 10224 #define PWR_PUCRC_PC6_Pos (6U)
<> 128:9bcdf88f62b0 10225 #define PWR_PUCRC_PC6_Msk (0x1U << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 10226 #define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Port PC6 Pull-Up set */
<> 128:9bcdf88f62b0 10227 #define PWR_PUCRC_PC5_Pos (5U)
<> 128:9bcdf88f62b0 10228 #define PWR_PUCRC_PC5_Msk (0x1U << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 10229 #define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Port PC5 Pull-Up set */
<> 128:9bcdf88f62b0 10230 #define PWR_PUCRC_PC4_Pos (4U)
<> 128:9bcdf88f62b0 10231 #define PWR_PUCRC_PC4_Msk (0x1U << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 10232 #define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Port PC4 Pull-Up set */
<> 128:9bcdf88f62b0 10233 #define PWR_PUCRC_PC3_Pos (3U)
<> 128:9bcdf88f62b0 10234 #define PWR_PUCRC_PC3_Msk (0x1U << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 10235 #define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Port PC3 Pull-Up set */
<> 128:9bcdf88f62b0 10236 #define PWR_PUCRC_PC2_Pos (2U)
<> 128:9bcdf88f62b0 10237 #define PWR_PUCRC_PC2_Msk (0x1U << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 10238 #define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Port PC2 Pull-Up set */
<> 128:9bcdf88f62b0 10239 #define PWR_PUCRC_PC1_Pos (1U)
<> 128:9bcdf88f62b0 10240 #define PWR_PUCRC_PC1_Msk (0x1U << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 10241 #define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Port PC1 Pull-Up set */
<> 128:9bcdf88f62b0 10242 #define PWR_PUCRC_PC0_Pos (0U)
<> 128:9bcdf88f62b0 10243 #define PWR_PUCRC_PC0_Msk (0x1U << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 10244 #define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Port PC0 Pull-Up set */
<> 128:9bcdf88f62b0 10245
<> 128:9bcdf88f62b0 10246 /******************** Bit definition for PWR_PDCRC register ********************/
<> 128:9bcdf88f62b0 10247 #define PWR_PDCRC_PC15_Pos (15U)
<> 128:9bcdf88f62b0 10248 #define PWR_PDCRC_PC15_Msk (0x1U << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 10249 #define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */
<> 128:9bcdf88f62b0 10250 #define PWR_PDCRC_PC14_Pos (14U)
<> 128:9bcdf88f62b0 10251 #define PWR_PDCRC_PC14_Msk (0x1U << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 10252 #define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */
<> 128:9bcdf88f62b0 10253 #define PWR_PDCRC_PC13_Pos (13U)
<> 128:9bcdf88f62b0 10254 #define PWR_PDCRC_PC13_Msk (0x1U << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 10255 #define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Port PC13 Pull-Down set */
<> 128:9bcdf88f62b0 10256 #define PWR_PDCRC_PC12_Pos (12U)
<> 128:9bcdf88f62b0 10257 #define PWR_PDCRC_PC12_Msk (0x1U << PWR_PDCRC_PC12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 10258 #define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk /*!< Port PC12 Pull-Down set */
<> 128:9bcdf88f62b0 10259 #define PWR_PDCRC_PC11_Pos (11U)
<> 128:9bcdf88f62b0 10260 #define PWR_PDCRC_PC11_Msk (0x1U << PWR_PDCRC_PC11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 10261 #define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk /*!< Port PC11 Pull-Down set */
<> 128:9bcdf88f62b0 10262 #define PWR_PDCRC_PC10_Pos (10U)
<> 128:9bcdf88f62b0 10263 #define PWR_PDCRC_PC10_Msk (0x1U << PWR_PDCRC_PC10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 10264 #define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk /*!< Port PC10 Pull-Down set */
<> 128:9bcdf88f62b0 10265 #define PWR_PDCRC_PC9_Pos (9U)
<> 128:9bcdf88f62b0 10266 #define PWR_PDCRC_PC9_Msk (0x1U << PWR_PDCRC_PC9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 10267 #define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk /*!< Port PC9 Pull-Down set */
<> 128:9bcdf88f62b0 10268 #define PWR_PDCRC_PC8_Pos (8U)
<> 128:9bcdf88f62b0 10269 #define PWR_PDCRC_PC8_Msk (0x1U << PWR_PDCRC_PC8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 10270 #define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk /*!< Port PC8 Pull-Down set */
<> 128:9bcdf88f62b0 10271 #define PWR_PDCRC_PC7_Pos (7U)
<> 128:9bcdf88f62b0 10272 #define PWR_PDCRC_PC7_Msk (0x1U << PWR_PDCRC_PC7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 10273 #define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk /*!< Port PC7 Pull-Down set */
<> 128:9bcdf88f62b0 10274 #define PWR_PDCRC_PC6_Pos (6U)
<> 128:9bcdf88f62b0 10275 #define PWR_PDCRC_PC6_Msk (0x1U << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 10276 #define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Port PC6 Pull-Down set */
<> 128:9bcdf88f62b0 10277 #define PWR_PDCRC_PC5_Pos (5U)
<> 128:9bcdf88f62b0 10278 #define PWR_PDCRC_PC5_Msk (0x1U << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 10279 #define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Port PC5 Pull-Down set */
<> 128:9bcdf88f62b0 10280 #define PWR_PDCRC_PC4_Pos (4U)
<> 128:9bcdf88f62b0 10281 #define PWR_PDCRC_PC4_Msk (0x1U << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 10282 #define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Port PC4 Pull-Down set */
<> 128:9bcdf88f62b0 10283 #define PWR_PDCRC_PC3_Pos (3U)
<> 128:9bcdf88f62b0 10284 #define PWR_PDCRC_PC3_Msk (0x1U << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 10285 #define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Port PC3 Pull-Down set */
<> 128:9bcdf88f62b0 10286 #define PWR_PDCRC_PC2_Pos (2U)
<> 128:9bcdf88f62b0 10287 #define PWR_PDCRC_PC2_Msk (0x1U << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 10288 #define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Port PC2 Pull-Down set */
<> 128:9bcdf88f62b0 10289 #define PWR_PDCRC_PC1_Pos (1U)
<> 128:9bcdf88f62b0 10290 #define PWR_PDCRC_PC1_Msk (0x1U << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 10291 #define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Port PC1 Pull-Down set */
<> 128:9bcdf88f62b0 10292 #define PWR_PDCRC_PC0_Pos (0U)
<> 128:9bcdf88f62b0 10293 #define PWR_PDCRC_PC0_Msk (0x1U << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 10294 #define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Port PC0 Pull-Down set */
<> 128:9bcdf88f62b0 10295
<> 128:9bcdf88f62b0 10296 /******************** Bit definition for PWR_PUCRD register ********************/
<> 128:9bcdf88f62b0 10297 #define PWR_PUCRD_PD15_Pos (15U)
<> 128:9bcdf88f62b0 10298 #define PWR_PUCRD_PD15_Msk (0x1U << PWR_PUCRD_PD15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 10299 #define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk /*!< Port PD15 Pull-Up set */
<> 128:9bcdf88f62b0 10300 #define PWR_PUCRD_PD14_Pos (14U)
<> 128:9bcdf88f62b0 10301 #define PWR_PUCRD_PD14_Msk (0x1U << PWR_PUCRD_PD14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 10302 #define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk /*!< Port PD14 Pull-Up set */
<> 128:9bcdf88f62b0 10303 #define PWR_PUCRD_PD13_Pos (13U)
<> 128:9bcdf88f62b0 10304 #define PWR_PUCRD_PD13_Msk (0x1U << PWR_PUCRD_PD13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 10305 #define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk /*!< Port PD13 Pull-Up set */
<> 128:9bcdf88f62b0 10306 #define PWR_PUCRD_PD12_Pos (12U)
<> 128:9bcdf88f62b0 10307 #define PWR_PUCRD_PD12_Msk (0x1U << PWR_PUCRD_PD12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 10308 #define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk /*!< Port PD12 Pull-Up set */
<> 128:9bcdf88f62b0 10309 #define PWR_PUCRD_PD11_Pos (11U)
<> 128:9bcdf88f62b0 10310 #define PWR_PUCRD_PD11_Msk (0x1U << PWR_PUCRD_PD11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 10311 #define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk /*!< Port PD11 Pull-Up set */
<> 128:9bcdf88f62b0 10312 #define PWR_PUCRD_PD10_Pos (10U)
<> 128:9bcdf88f62b0 10313 #define PWR_PUCRD_PD10_Msk (0x1U << PWR_PUCRD_PD10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 10314 #define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk /*!< Port PD10 Pull-Up set */
<> 128:9bcdf88f62b0 10315 #define PWR_PUCRD_PD9_Pos (9U)
<> 128:9bcdf88f62b0 10316 #define PWR_PUCRD_PD9_Msk (0x1U << PWR_PUCRD_PD9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 10317 #define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk /*!< Port PD9 Pull-Up set */
<> 128:9bcdf88f62b0 10318 #define PWR_PUCRD_PD8_Pos (8U)
<> 128:9bcdf88f62b0 10319 #define PWR_PUCRD_PD8_Msk (0x1U << PWR_PUCRD_PD8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 10320 #define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk /*!< Port PD8 Pull-Up set */
<> 128:9bcdf88f62b0 10321 #define PWR_PUCRD_PD7_Pos (7U)
<> 128:9bcdf88f62b0 10322 #define PWR_PUCRD_PD7_Msk (0x1U << PWR_PUCRD_PD7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 10323 #define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk /*!< Port PD7 Pull-Up set */
<> 128:9bcdf88f62b0 10324 #define PWR_PUCRD_PD6_Pos (6U)
<> 128:9bcdf88f62b0 10325 #define PWR_PUCRD_PD6_Msk (0x1U << PWR_PUCRD_PD6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 10326 #define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk /*!< Port PD6 Pull-Up set */
<> 128:9bcdf88f62b0 10327 #define PWR_PUCRD_PD5_Pos (5U)
<> 128:9bcdf88f62b0 10328 #define PWR_PUCRD_PD5_Msk (0x1U << PWR_PUCRD_PD5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 10329 #define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk /*!< Port PD5 Pull-Up set */
<> 128:9bcdf88f62b0 10330 #define PWR_PUCRD_PD4_Pos (4U)
<> 128:9bcdf88f62b0 10331 #define PWR_PUCRD_PD4_Msk (0x1U << PWR_PUCRD_PD4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 10332 #define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk /*!< Port PD4 Pull-Up set */
<> 128:9bcdf88f62b0 10333 #define PWR_PUCRD_PD3_Pos (3U)
<> 128:9bcdf88f62b0 10334 #define PWR_PUCRD_PD3_Msk (0x1U << PWR_PUCRD_PD3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 10335 #define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk /*!< Port PD3 Pull-Up set */
<> 128:9bcdf88f62b0 10336 #define PWR_PUCRD_PD2_Pos (2U)
<> 128:9bcdf88f62b0 10337 #define PWR_PUCRD_PD2_Msk (0x1U << PWR_PUCRD_PD2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 10338 #define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk /*!< Port PD2 Pull-Up set */
<> 128:9bcdf88f62b0 10339 #define PWR_PUCRD_PD1_Pos (1U)
<> 128:9bcdf88f62b0 10340 #define PWR_PUCRD_PD1_Msk (0x1U << PWR_PUCRD_PD1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 10341 #define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk /*!< Port PD1 Pull-Up set */
<> 128:9bcdf88f62b0 10342 #define PWR_PUCRD_PD0_Pos (0U)
<> 128:9bcdf88f62b0 10343 #define PWR_PUCRD_PD0_Msk (0x1U << PWR_PUCRD_PD0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 10344 #define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk /*!< Port PD0 Pull-Up set */
<> 128:9bcdf88f62b0 10345
<> 128:9bcdf88f62b0 10346 /******************** Bit definition for PWR_PDCRD register ********************/
<> 128:9bcdf88f62b0 10347 #define PWR_PDCRD_PD15_Pos (15U)
<> 128:9bcdf88f62b0 10348 #define PWR_PDCRD_PD15_Msk (0x1U << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 10349 #define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Port PD15 Pull-Down set */
<> 128:9bcdf88f62b0 10350 #define PWR_PDCRD_PD14_Pos (14U)
<> 128:9bcdf88f62b0 10351 #define PWR_PDCRD_PD14_Msk (0x1U << PWR_PDCRD_PD14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 10352 #define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk /*!< Port PD14 Pull-Down set */
<> 128:9bcdf88f62b0 10353 #define PWR_PDCRD_PD13_Pos (13U)
<> 128:9bcdf88f62b0 10354 #define PWR_PDCRD_PD13_Msk (0x1U << PWR_PDCRD_PD13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 10355 #define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk /*!< Port PD13 Pull-Down set */
<> 128:9bcdf88f62b0 10356 #define PWR_PDCRD_PD12_Pos (12U)
<> 128:9bcdf88f62b0 10357 #define PWR_PDCRD_PD12_Msk (0x1U << PWR_PDCRD_PD12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 10358 #define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk /*!< Port PD12 Pull-Down set */
<> 128:9bcdf88f62b0 10359 #define PWR_PDCRD_PD11_Pos (11U)
<> 128:9bcdf88f62b0 10360 #define PWR_PDCRD_PD11_Msk (0x1U << PWR_PDCRD_PD11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 10361 #define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk /*!< Port PD11 Pull-Down set */
<> 128:9bcdf88f62b0 10362 #define PWR_PDCRD_PD10_Pos (10U)
<> 128:9bcdf88f62b0 10363 #define PWR_PDCRD_PD10_Msk (0x1U << PWR_PDCRD_PD10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 10364 #define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk /*!< Port PD10 Pull-Down set */
<> 128:9bcdf88f62b0 10365 #define PWR_PDCRD_PD9_Pos (9U)
<> 128:9bcdf88f62b0 10366 #define PWR_PDCRD_PD9_Msk (0x1U << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 10367 #define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Port PD9 Pull-Down set */
<> 128:9bcdf88f62b0 10368 #define PWR_PDCRD_PD8_Pos (8U)
<> 128:9bcdf88f62b0 10369 #define PWR_PDCRD_PD8_Msk (0x1U << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 10370 #define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Port PD8 Pull-Down set */
<> 128:9bcdf88f62b0 10371 #define PWR_PDCRD_PD7_Pos (7U)
<> 128:9bcdf88f62b0 10372 #define PWR_PDCRD_PD7_Msk (0x1U << PWR_PDCRD_PD7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 10373 #define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk /*!< Port PD7 Pull-Down set */
<> 128:9bcdf88f62b0 10374 #define PWR_PDCRD_PD6_Pos (6U)
<> 128:9bcdf88f62b0 10375 #define PWR_PDCRD_PD6_Msk (0x1U << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 10376 #define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Port PD6 Pull-Down set */
<> 128:9bcdf88f62b0 10377 #define PWR_PDCRD_PD5_Pos (5U)
<> 128:9bcdf88f62b0 10378 #define PWR_PDCRD_PD5_Msk (0x1U << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 10379 #define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Port PD5 Pull-Down set */
<> 128:9bcdf88f62b0 10380 #define PWR_PDCRD_PD4_Pos (4U)
<> 128:9bcdf88f62b0 10381 #define PWR_PDCRD_PD4_Msk (0x1U << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 10382 #define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Port PD4 Pull-Down set */
<> 128:9bcdf88f62b0 10383 #define PWR_PDCRD_PD3_Pos (3U)
<> 128:9bcdf88f62b0 10384 #define PWR_PDCRD_PD3_Msk (0x1U << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 10385 #define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Port PD3 Pull-Down set */
<> 128:9bcdf88f62b0 10386 #define PWR_PDCRD_PD2_Pos (2U)
<> 128:9bcdf88f62b0 10387 #define PWR_PDCRD_PD2_Msk (0x1U << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 10388 #define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Port PD2 Pull-Down set */
<> 128:9bcdf88f62b0 10389 #define PWR_PDCRD_PD1_Pos (1U)
<> 128:9bcdf88f62b0 10390 #define PWR_PDCRD_PD1_Msk (0x1U << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 10391 #define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Port PD1 Pull-Down set */
<> 128:9bcdf88f62b0 10392 #define PWR_PDCRD_PD0_Pos (0U)
<> 128:9bcdf88f62b0 10393 #define PWR_PDCRD_PD0_Msk (0x1U << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 10394 #define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Port PD0 Pull-Down set */
<> 128:9bcdf88f62b0 10395
<> 128:9bcdf88f62b0 10396 /******************** Bit definition for PWR_PUCRE register ********************/
<> 128:9bcdf88f62b0 10397 #define PWR_PUCRE_PE15_Pos (15U)
<> 128:9bcdf88f62b0 10398 #define PWR_PUCRE_PE15_Msk (0x1U << PWR_PUCRE_PE15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 10399 #define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk /*!< Port PE15 Pull-Up set */
<> 128:9bcdf88f62b0 10400 #define PWR_PUCRE_PE14_Pos (14U)
<> 128:9bcdf88f62b0 10401 #define PWR_PUCRE_PE14_Msk (0x1U << PWR_PUCRE_PE14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 10402 #define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk /*!< Port PE14 Pull-Up set */
<> 128:9bcdf88f62b0 10403 #define PWR_PUCRE_PE13_Pos (13U)
<> 128:9bcdf88f62b0 10404 #define PWR_PUCRE_PE13_Msk (0x1U << PWR_PUCRE_PE13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 10405 #define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk /*!< Port PE13 Pull-Up set */
<> 128:9bcdf88f62b0 10406 #define PWR_PUCRE_PE12_Pos (12U)
<> 128:9bcdf88f62b0 10407 #define PWR_PUCRE_PE12_Msk (0x1U << PWR_PUCRE_PE12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 10408 #define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk /*!< Port PE12 Pull-Up set */
<> 128:9bcdf88f62b0 10409 #define PWR_PUCRE_PE11_Pos (11U)
<> 128:9bcdf88f62b0 10410 #define PWR_PUCRE_PE11_Msk (0x1U << PWR_PUCRE_PE11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 10411 #define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk /*!< Port PE11 Pull-Up set */
<> 128:9bcdf88f62b0 10412 #define PWR_PUCRE_PE10_Pos (10U)
<> 128:9bcdf88f62b0 10413 #define PWR_PUCRE_PE10_Msk (0x1U << PWR_PUCRE_PE10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 10414 #define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk /*!< Port PE10 Pull-Up set */
<> 128:9bcdf88f62b0 10415 #define PWR_PUCRE_PE9_Pos (9U)
<> 128:9bcdf88f62b0 10416 #define PWR_PUCRE_PE9_Msk (0x1U << PWR_PUCRE_PE9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 10417 #define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk /*!< Port PE9 Pull-Up set */
<> 128:9bcdf88f62b0 10418 #define PWR_PUCRE_PE8_Pos (8U)
<> 128:9bcdf88f62b0 10419 #define PWR_PUCRE_PE8_Msk (0x1U << PWR_PUCRE_PE8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 10420 #define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk /*!< Port PE8 Pull-Up set */
<> 128:9bcdf88f62b0 10421 #define PWR_PUCRE_PE7_Pos (7U)
<> 128:9bcdf88f62b0 10422 #define PWR_PUCRE_PE7_Msk (0x1U << PWR_PUCRE_PE7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 10423 #define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk /*!< Port PE7 Pull-Up set */
<> 128:9bcdf88f62b0 10424 #define PWR_PUCRE_PE6_Pos (6U)
<> 128:9bcdf88f62b0 10425 #define PWR_PUCRE_PE6_Msk (0x1U << PWR_PUCRE_PE6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 10426 #define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk /*!< Port PE6 Pull-Up set */
<> 128:9bcdf88f62b0 10427 #define PWR_PUCRE_PE5_Pos (5U)
<> 128:9bcdf88f62b0 10428 #define PWR_PUCRE_PE5_Msk (0x1U << PWR_PUCRE_PE5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 10429 #define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk /*!< Port PE5 Pull-Up set */
<> 128:9bcdf88f62b0 10430 #define PWR_PUCRE_PE4_Pos (4U)
<> 128:9bcdf88f62b0 10431 #define PWR_PUCRE_PE4_Msk (0x1U << PWR_PUCRE_PE4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 10432 #define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Port PE4 Pull-Up set */
<> 128:9bcdf88f62b0 10433 #define PWR_PUCRE_PE3_Pos (3U)
<> 128:9bcdf88f62b0 10434 #define PWR_PUCRE_PE3_Msk (0x1U << PWR_PUCRE_PE3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 10435 #define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk /*!< Port PE3 Pull-Up set */
<> 128:9bcdf88f62b0 10436 #define PWR_PUCRE_PE2_Pos (2U)
<> 128:9bcdf88f62b0 10437 #define PWR_PUCRE_PE2_Msk (0x1U << PWR_PUCRE_PE2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 10438 #define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk /*!< Port PE2 Pull-Up set */
<> 128:9bcdf88f62b0 10439 #define PWR_PUCRE_PE1_Pos (1U)
<> 128:9bcdf88f62b0 10440 #define PWR_PUCRE_PE1_Msk (0x1U << PWR_PUCRE_PE1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 10441 #define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk /*!< Port PE1 Pull-Up set */
<> 128:9bcdf88f62b0 10442 #define PWR_PUCRE_PE0_Pos (0U)
<> 128:9bcdf88f62b0 10443 #define PWR_PUCRE_PE0_Msk (0x1U << PWR_PUCRE_PE0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 10444 #define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk /*!< Port PE0 Pull-Up set */
<> 128:9bcdf88f62b0 10445
<> 128:9bcdf88f62b0 10446 /******************** Bit definition for PWR_PDCRE register ********************/
<> 128:9bcdf88f62b0 10447 #define PWR_PDCRE_PE15_Pos (15U)
<> 128:9bcdf88f62b0 10448 #define PWR_PDCRE_PE15_Msk (0x1U << PWR_PDCRE_PE15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 10449 #define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk /*!< Port PE15 Pull-Down set */
<> 128:9bcdf88f62b0 10450 #define PWR_PDCRE_PE14_Pos (14U)
<> 128:9bcdf88f62b0 10451 #define PWR_PDCRE_PE14_Msk (0x1U << PWR_PDCRE_PE14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 10452 #define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk /*!< Port PE14 Pull-Down set */
<> 128:9bcdf88f62b0 10453 #define PWR_PDCRE_PE13_Pos (13U)
<> 128:9bcdf88f62b0 10454 #define PWR_PDCRE_PE13_Msk (0x1U << PWR_PDCRE_PE13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 10455 #define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk /*!< Port PE13 Pull-Down set */
<> 128:9bcdf88f62b0 10456 #define PWR_PDCRE_PE12_Pos (12U)
<> 128:9bcdf88f62b0 10457 #define PWR_PDCRE_PE12_Msk (0x1U << PWR_PDCRE_PE12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 10458 #define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk /*!< Port PE12 Pull-Down set */
<> 128:9bcdf88f62b0 10459 #define PWR_PDCRE_PE11_Pos (11U)
<> 128:9bcdf88f62b0 10460 #define PWR_PDCRE_PE11_Msk (0x1U << PWR_PDCRE_PE11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 10461 #define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk /*!< Port PE11 Pull-Down set */
<> 128:9bcdf88f62b0 10462 #define PWR_PDCRE_PE10_Pos (10U)
<> 128:9bcdf88f62b0 10463 #define PWR_PDCRE_PE10_Msk (0x1U << PWR_PDCRE_PE10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 10464 #define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk /*!< Port PE10 Pull-Down set */
<> 128:9bcdf88f62b0 10465 #define PWR_PDCRE_PE9_Pos (9U)
<> 128:9bcdf88f62b0 10466 #define PWR_PDCRE_PE9_Msk (0x1U << PWR_PDCRE_PE9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 10467 #define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk /*!< Port PE9 Pull-Down set */
<> 128:9bcdf88f62b0 10468 #define PWR_PDCRE_PE8_Pos (8U)
<> 128:9bcdf88f62b0 10469 #define PWR_PDCRE_PE8_Msk (0x1U << PWR_PDCRE_PE8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 10470 #define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk /*!< Port PE8 Pull-Down set */
<> 128:9bcdf88f62b0 10471 #define PWR_PDCRE_PE7_Pos (7U)
<> 128:9bcdf88f62b0 10472 #define PWR_PDCRE_PE7_Msk (0x1U << PWR_PDCRE_PE7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 10473 #define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk /*!< Port PE7 Pull-Down set */
<> 128:9bcdf88f62b0 10474 #define PWR_PDCRE_PE6_Pos (6U)
<> 128:9bcdf88f62b0 10475 #define PWR_PDCRE_PE6_Msk (0x1U << PWR_PDCRE_PE6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 10476 #define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk /*!< Port PE6 Pull-Down set */
<> 128:9bcdf88f62b0 10477 #define PWR_PDCRE_PE5_Pos (5U)
<> 128:9bcdf88f62b0 10478 #define PWR_PDCRE_PE5_Msk (0x1U << PWR_PDCRE_PE5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 10479 #define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk /*!< Port PE5 Pull-Down set */
<> 128:9bcdf88f62b0 10480 #define PWR_PDCRE_PE4_Pos (4U)
<> 128:9bcdf88f62b0 10481 #define PWR_PDCRE_PE4_Msk (0x1U << PWR_PDCRE_PE4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 10482 #define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Port PE4 Pull-Down set */
<> 128:9bcdf88f62b0 10483 #define PWR_PDCRE_PE3_Pos (3U)
<> 128:9bcdf88f62b0 10484 #define PWR_PDCRE_PE3_Msk (0x1U << PWR_PDCRE_PE3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 10485 #define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk /*!< Port PE3 Pull-Down set */
<> 128:9bcdf88f62b0 10486 #define PWR_PDCRE_PE2_Pos (2U)
<> 128:9bcdf88f62b0 10487 #define PWR_PDCRE_PE2_Msk (0x1U << PWR_PDCRE_PE2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 10488 #define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk /*!< Port PE2 Pull-Down set */
<> 128:9bcdf88f62b0 10489 #define PWR_PDCRE_PE1_Pos (1U)
<> 128:9bcdf88f62b0 10490 #define PWR_PDCRE_PE1_Msk (0x1U << PWR_PDCRE_PE1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 10491 #define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk /*!< Port PE1 Pull-Down set */
<> 128:9bcdf88f62b0 10492 #define PWR_PDCRE_PE0_Pos (0U)
<> 128:9bcdf88f62b0 10493 #define PWR_PDCRE_PE0_Msk (0x1U << PWR_PDCRE_PE0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 10494 #define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk /*!< Port PE0 Pull-Down set */
<> 128:9bcdf88f62b0 10495
<> 128:9bcdf88f62b0 10496 /******************** Bit definition for PWR_PUCRF register ********************/
<> 128:9bcdf88f62b0 10497 #define PWR_PUCRF_PF15_Pos (15U)
<> 128:9bcdf88f62b0 10498 #define PWR_PUCRF_PF15_Msk (0x1U << PWR_PUCRF_PF15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 10499 #define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk /*!< Port PF15 Pull-Up set */
<> 128:9bcdf88f62b0 10500 #define PWR_PUCRF_PF14_Pos (14U)
<> 128:9bcdf88f62b0 10501 #define PWR_PUCRF_PF14_Msk (0x1U << PWR_PUCRF_PF14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 10502 #define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk /*!< Port PF14 Pull-Up set */
<> 128:9bcdf88f62b0 10503 #define PWR_PUCRF_PF13_Pos (13U)
<> 128:9bcdf88f62b0 10504 #define PWR_PUCRF_PF13_Msk (0x1U << PWR_PUCRF_PF13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 10505 #define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk /*!< Port PF13 Pull-Up set */
<> 128:9bcdf88f62b0 10506 #define PWR_PUCRF_PF12_Pos (12U)
<> 128:9bcdf88f62b0 10507 #define PWR_PUCRF_PF12_Msk (0x1U << PWR_PUCRF_PF12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 10508 #define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk /*!< Port PF12 Pull-Up set */
<> 128:9bcdf88f62b0 10509 #define PWR_PUCRF_PF11_Pos (11U)
<> 128:9bcdf88f62b0 10510 #define PWR_PUCRF_PF11_Msk (0x1U << PWR_PUCRF_PF11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 10511 #define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk /*!< Port PF11 Pull-Up set */
<> 128:9bcdf88f62b0 10512 #define PWR_PUCRF_PF10_Pos (10U)
<> 128:9bcdf88f62b0 10513 #define PWR_PUCRF_PF10_Msk (0x1U << PWR_PUCRF_PF10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 10514 #define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk /*!< Port PF10 Pull-Up set */
<> 128:9bcdf88f62b0 10515 #define PWR_PUCRF_PF9_Pos (9U)
<> 128:9bcdf88f62b0 10516 #define PWR_PUCRF_PF9_Msk (0x1U << PWR_PUCRF_PF9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 10517 #define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk /*!< Port PF9 Pull-Up set */
<> 128:9bcdf88f62b0 10518 #define PWR_PUCRF_PF8_Pos (8U)
<> 128:9bcdf88f62b0 10519 #define PWR_PUCRF_PF8_Msk (0x1U << PWR_PUCRF_PF8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 10520 #define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk /*!< Port PF8 Pull-Up set */
<> 128:9bcdf88f62b0 10521 #define PWR_PUCRF_PF7_Pos (7U)
<> 128:9bcdf88f62b0 10522 #define PWR_PUCRF_PF7_Msk (0x1U << PWR_PUCRF_PF7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 10523 #define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk /*!< Port PF7 Pull-Up set */
<> 128:9bcdf88f62b0 10524 #define PWR_PUCRF_PF6_Pos (6U)
<> 128:9bcdf88f62b0 10525 #define PWR_PUCRF_PF6_Msk (0x1U << PWR_PUCRF_PF6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 10526 #define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk /*!< Port PF6 Pull-Up set */
<> 128:9bcdf88f62b0 10527 #define PWR_PUCRF_PF5_Pos (5U)
<> 128:9bcdf88f62b0 10528 #define PWR_PUCRF_PF5_Msk (0x1U << PWR_PUCRF_PF5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 10529 #define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk /*!< Port PF5 Pull-Up set */
<> 128:9bcdf88f62b0 10530 #define PWR_PUCRF_PF4_Pos (4U)
<> 128:9bcdf88f62b0 10531 #define PWR_PUCRF_PF4_Msk (0x1U << PWR_PUCRF_PF4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 10532 #define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk /*!< Port PF4 Pull-Up set */
<> 128:9bcdf88f62b0 10533 #define PWR_PUCRF_PF3_Pos (3U)
<> 128:9bcdf88f62b0 10534 #define PWR_PUCRF_PF3_Msk (0x1U << PWR_PUCRF_PF3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 10535 #define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk /*!< Port PF3 Pull-Up set */
<> 128:9bcdf88f62b0 10536 #define PWR_PUCRF_PF2_Pos (2U)
<> 128:9bcdf88f62b0 10537 #define PWR_PUCRF_PF2_Msk (0x1U << PWR_PUCRF_PF2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 10538 #define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk /*!< Port PF2 Pull-Up set */
<> 128:9bcdf88f62b0 10539 #define PWR_PUCRF_PF1_Pos (1U)
<> 128:9bcdf88f62b0 10540 #define PWR_PUCRF_PF1_Msk (0x1U << PWR_PUCRF_PF1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 10541 #define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk /*!< Port PF1 Pull-Up set */
<> 128:9bcdf88f62b0 10542 #define PWR_PUCRF_PF0_Pos (0U)
<> 128:9bcdf88f62b0 10543 #define PWR_PUCRF_PF0_Msk (0x1U << PWR_PUCRF_PF0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 10544 #define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk /*!< Port PF0 Pull-Up set */
<> 128:9bcdf88f62b0 10545
<> 128:9bcdf88f62b0 10546 /******************** Bit definition for PWR_PDCRF register ********************/
<> 128:9bcdf88f62b0 10547 #define PWR_PDCRF_PF15_Pos (15U)
<> 128:9bcdf88f62b0 10548 #define PWR_PDCRF_PF15_Msk (0x1U << PWR_PDCRF_PF15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 10549 #define PWR_PDCRF_PF15 PWR_PDCRF_PF15_Msk /*!< Port PF15 Pull-Down set */
<> 128:9bcdf88f62b0 10550 #define PWR_PDCRF_PF14_Pos (14U)
<> 128:9bcdf88f62b0 10551 #define PWR_PDCRF_PF14_Msk (0x1U << PWR_PDCRF_PF14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 10552 #define PWR_PDCRF_PF14 PWR_PDCRF_PF14_Msk /*!< Port PF14 Pull-Down set */
<> 128:9bcdf88f62b0 10553 #define PWR_PDCRF_PF13_Pos (13U)
<> 128:9bcdf88f62b0 10554 #define PWR_PDCRF_PF13_Msk (0x1U << PWR_PDCRF_PF13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 10555 #define PWR_PDCRF_PF13 PWR_PDCRF_PF13_Msk /*!< Port PF13 Pull-Down set */
<> 128:9bcdf88f62b0 10556 #define PWR_PDCRF_PF12_Pos (12U)
<> 128:9bcdf88f62b0 10557 #define PWR_PDCRF_PF12_Msk (0x1U << PWR_PDCRF_PF12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 10558 #define PWR_PDCRF_PF12 PWR_PDCRF_PF12_Msk /*!< Port PF12 Pull-Down set */
<> 128:9bcdf88f62b0 10559 #define PWR_PDCRF_PF11_Pos (11U)
<> 128:9bcdf88f62b0 10560 #define PWR_PDCRF_PF11_Msk (0x1U << PWR_PDCRF_PF11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 10561 #define PWR_PDCRF_PF11 PWR_PDCRF_PF11_Msk /*!< Port PF11 Pull-Down set */
<> 128:9bcdf88f62b0 10562 #define PWR_PDCRF_PF10_Pos (10U)
<> 128:9bcdf88f62b0 10563 #define PWR_PDCRF_PF10_Msk (0x1U << PWR_PDCRF_PF10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 10564 #define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk /*!< Port PF10 Pull-Down set */
<> 128:9bcdf88f62b0 10565 #define PWR_PDCRF_PF9_Pos (9U)
<> 128:9bcdf88f62b0 10566 #define PWR_PDCRF_PF9_Msk (0x1U << PWR_PDCRF_PF9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 10567 #define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk /*!< Port PF9 Pull-Down set */
<> 128:9bcdf88f62b0 10568 #define PWR_PDCRF_PF8_Pos (8U)
<> 128:9bcdf88f62b0 10569 #define PWR_PDCRF_PF8_Msk (0x1U << PWR_PDCRF_PF8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 10570 #define PWR_PDCRF_PF8 PWR_PDCRF_PF8_Msk /*!< Port PF8 Pull-Down set */
<> 128:9bcdf88f62b0 10571 #define PWR_PDCRF_PF7_Pos (7U)
<> 128:9bcdf88f62b0 10572 #define PWR_PDCRF_PF7_Msk (0x1U << PWR_PDCRF_PF7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 10573 #define PWR_PDCRF_PF7 PWR_PDCRF_PF7_Msk /*!< Port PF7 Pull-Down set */
<> 128:9bcdf88f62b0 10574 #define PWR_PDCRF_PF6_Pos (6U)
<> 128:9bcdf88f62b0 10575 #define PWR_PDCRF_PF6_Msk (0x1U << PWR_PDCRF_PF6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 10576 #define PWR_PDCRF_PF6 PWR_PDCRF_PF6_Msk /*!< Port PF6 Pull-Down set */
<> 128:9bcdf88f62b0 10577 #define PWR_PDCRF_PF5_Pos (5U)
<> 128:9bcdf88f62b0 10578 #define PWR_PDCRF_PF5_Msk (0x1U << PWR_PDCRF_PF5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 10579 #define PWR_PDCRF_PF5 PWR_PDCRF_PF5_Msk /*!< Port PF5 Pull-Down set */
<> 128:9bcdf88f62b0 10580 #define PWR_PDCRF_PF4_Pos (4U)
<> 128:9bcdf88f62b0 10581 #define PWR_PDCRF_PF4_Msk (0x1U << PWR_PDCRF_PF4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 10582 #define PWR_PDCRF_PF4 PWR_PDCRF_PF4_Msk /*!< Port PF4 Pull-Down set */
<> 128:9bcdf88f62b0 10583 #define PWR_PDCRF_PF3_Pos (3U)
<> 128:9bcdf88f62b0 10584 #define PWR_PDCRF_PF3_Msk (0x1U << PWR_PDCRF_PF3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 10585 #define PWR_PDCRF_PF3 PWR_PDCRF_PF3_Msk /*!< Port PF3 Pull-Down set */
<> 128:9bcdf88f62b0 10586 #define PWR_PDCRF_PF2_Pos (2U)
<> 128:9bcdf88f62b0 10587 #define PWR_PDCRF_PF2_Msk (0x1U << PWR_PDCRF_PF2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 10588 #define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk /*!< Port PF2 Pull-Down set */
<> 128:9bcdf88f62b0 10589 #define PWR_PDCRF_PF1_Pos (1U)
<> 128:9bcdf88f62b0 10590 #define PWR_PDCRF_PF1_Msk (0x1U << PWR_PDCRF_PF1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 10591 #define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk /*!< Port PF1 Pull-Down set */
<> 128:9bcdf88f62b0 10592 #define PWR_PDCRF_PF0_Pos (0U)
<> 128:9bcdf88f62b0 10593 #define PWR_PDCRF_PF0_Msk (0x1U << PWR_PDCRF_PF0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 10594 #define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk /*!< Port PF0 Pull-Down set */
<> 128:9bcdf88f62b0 10595
<> 128:9bcdf88f62b0 10596 /******************** Bit definition for PWR_PUCRG register ********************/
<> 128:9bcdf88f62b0 10597 #define PWR_PUCRG_PG15_Pos (15U)
<> 128:9bcdf88f62b0 10598 #define PWR_PUCRG_PG15_Msk (0x1U << PWR_PUCRG_PG15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 10599 #define PWR_PUCRG_PG15 PWR_PUCRG_PG15_Msk /*!< Port PG15 Pull-Up set */
<> 128:9bcdf88f62b0 10600 #define PWR_PUCRG_PG14_Pos (14U)
<> 128:9bcdf88f62b0 10601 #define PWR_PUCRG_PG14_Msk (0x1U << PWR_PUCRG_PG14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 10602 #define PWR_PUCRG_PG14 PWR_PUCRG_PG14_Msk /*!< Port PG14 Pull-Up set */
<> 128:9bcdf88f62b0 10603 #define PWR_PUCRG_PG13_Pos (13U)
<> 128:9bcdf88f62b0 10604 #define PWR_PUCRG_PG13_Msk (0x1U << PWR_PUCRG_PG13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 10605 #define PWR_PUCRG_PG13 PWR_PUCRG_PG13_Msk /*!< Port PG13 Pull-Up set */
<> 128:9bcdf88f62b0 10606 #define PWR_PUCRG_PG12_Pos (12U)
<> 128:9bcdf88f62b0 10607 #define PWR_PUCRG_PG12_Msk (0x1U << PWR_PUCRG_PG12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 10608 #define PWR_PUCRG_PG12 PWR_PUCRG_PG12_Msk /*!< Port PG12 Pull-Up set */
<> 128:9bcdf88f62b0 10609 #define PWR_PUCRG_PG11_Pos (11U)
<> 128:9bcdf88f62b0 10610 #define PWR_PUCRG_PG11_Msk (0x1U << PWR_PUCRG_PG11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 10611 #define PWR_PUCRG_PG11 PWR_PUCRG_PG11_Msk /*!< Port PG11 Pull-Up set */
<> 128:9bcdf88f62b0 10612 #define PWR_PUCRG_PG10_Pos (10U)
<> 128:9bcdf88f62b0 10613 #define PWR_PUCRG_PG10_Msk (0x1U << PWR_PUCRG_PG10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 10614 #define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk /*!< Port PG10 Pull-Up set */
<> 128:9bcdf88f62b0 10615 #define PWR_PUCRG_PG9_Pos (9U)
<> 128:9bcdf88f62b0 10616 #define PWR_PUCRG_PG9_Msk (0x1U << PWR_PUCRG_PG9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 10617 #define PWR_PUCRG_PG9 PWR_PUCRG_PG9_Msk /*!< Port PG9 Pull-Up set */
<> 128:9bcdf88f62b0 10618 #define PWR_PUCRG_PG8_Pos (8U)
<> 128:9bcdf88f62b0 10619 #define PWR_PUCRG_PG8_Msk (0x1U << PWR_PUCRG_PG8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 10620 #define PWR_PUCRG_PG8 PWR_PUCRG_PG8_Msk /*!< Port PG8 Pull-Up set */
<> 128:9bcdf88f62b0 10621 #define PWR_PUCRG_PG7_Pos (7U)
<> 128:9bcdf88f62b0 10622 #define PWR_PUCRG_PG7_Msk (0x1U << PWR_PUCRG_PG7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 10623 #define PWR_PUCRG_PG7 PWR_PUCRG_PG7_Msk /*!< Port PG7 Pull-Up set */
<> 128:9bcdf88f62b0 10624 #define PWR_PUCRG_PG6_Pos (6U)
<> 128:9bcdf88f62b0 10625 #define PWR_PUCRG_PG6_Msk (0x1U << PWR_PUCRG_PG6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 10626 #define PWR_PUCRG_PG6 PWR_PUCRG_PG6_Msk /*!< Port PG6 Pull-Up set */
<> 128:9bcdf88f62b0 10627 #define PWR_PUCRG_PG5_Pos (5U)
<> 128:9bcdf88f62b0 10628 #define PWR_PUCRG_PG5_Msk (0x1U << PWR_PUCRG_PG5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 10629 #define PWR_PUCRG_PG5 PWR_PUCRG_PG5_Msk /*!< Port PG5 Pull-Up set */
<> 128:9bcdf88f62b0 10630 #define PWR_PUCRG_PG4_Pos (4U)
<> 128:9bcdf88f62b0 10631 #define PWR_PUCRG_PG4_Msk (0x1U << PWR_PUCRG_PG4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 10632 #define PWR_PUCRG_PG4 PWR_PUCRG_PG4_Msk /*!< Port PG4 Pull-Up set */
<> 128:9bcdf88f62b0 10633 #define PWR_PUCRG_PG3_Pos (3U)
<> 128:9bcdf88f62b0 10634 #define PWR_PUCRG_PG3_Msk (0x1U << PWR_PUCRG_PG3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 10635 #define PWR_PUCRG_PG3 PWR_PUCRG_PG3_Msk /*!< Port PG3 Pull-Up set */
<> 128:9bcdf88f62b0 10636 #define PWR_PUCRG_PG2_Pos (2U)
<> 128:9bcdf88f62b0 10637 #define PWR_PUCRG_PG2_Msk (0x1U << PWR_PUCRG_PG2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 10638 #define PWR_PUCRG_PG2 PWR_PUCRG_PG2_Msk /*!< Port PG2 Pull-Up set */
<> 128:9bcdf88f62b0 10639 #define PWR_PUCRG_PG1_Pos (1U)
<> 128:9bcdf88f62b0 10640 #define PWR_PUCRG_PG1_Msk (0x1U << PWR_PUCRG_PG1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 10641 #define PWR_PUCRG_PG1 PWR_PUCRG_PG1_Msk /*!< Port PG1 Pull-Up set */
<> 128:9bcdf88f62b0 10642 #define PWR_PUCRG_PG0_Pos (0U)
<> 128:9bcdf88f62b0 10643 #define PWR_PUCRG_PG0_Msk (0x1U << PWR_PUCRG_PG0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 10644 #define PWR_PUCRG_PG0 PWR_PUCRG_PG0_Msk /*!< Port PG0 Pull-Up set */
<> 128:9bcdf88f62b0 10645
<> 128:9bcdf88f62b0 10646 /******************** Bit definition for PWR_PDCRG register ********************/
<> 128:9bcdf88f62b0 10647 #define PWR_PDCRG_PG15_Pos (15U)
<> 128:9bcdf88f62b0 10648 #define PWR_PDCRG_PG15_Msk (0x1U << PWR_PDCRG_PG15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 10649 #define PWR_PDCRG_PG15 PWR_PDCRG_PG15_Msk /*!< Port PG15 Pull-Down set */
<> 128:9bcdf88f62b0 10650 #define PWR_PDCRG_PG14_Pos (14U)
<> 128:9bcdf88f62b0 10651 #define PWR_PDCRG_PG14_Msk (0x1U << PWR_PDCRG_PG14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 10652 #define PWR_PDCRG_PG14 PWR_PDCRG_PG14_Msk /*!< Port PG14 Pull-Down set */
<> 128:9bcdf88f62b0 10653 #define PWR_PDCRG_PG13_Pos (13U)
<> 128:9bcdf88f62b0 10654 #define PWR_PDCRG_PG13_Msk (0x1U << PWR_PDCRG_PG13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 10655 #define PWR_PDCRG_PG13 PWR_PDCRG_PG13_Msk /*!< Port PG13 Pull-Down set */
<> 128:9bcdf88f62b0 10656 #define PWR_PDCRG_PG12_Pos (12U)
<> 128:9bcdf88f62b0 10657 #define PWR_PDCRG_PG12_Msk (0x1U << PWR_PDCRG_PG12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 10658 #define PWR_PDCRG_PG12 PWR_PDCRG_PG12_Msk /*!< Port PG12 Pull-Down set */
<> 128:9bcdf88f62b0 10659 #define PWR_PDCRG_PG11_Pos (11U)
<> 128:9bcdf88f62b0 10660 #define PWR_PDCRG_PG11_Msk (0x1U << PWR_PDCRG_PG11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 10661 #define PWR_PDCRG_PG11 PWR_PDCRG_PG11_Msk /*!< Port PG11 Pull-Down set */
<> 128:9bcdf88f62b0 10662 #define PWR_PDCRG_PG10_Pos (10U)
<> 128:9bcdf88f62b0 10663 #define PWR_PDCRG_PG10_Msk (0x1U << PWR_PDCRG_PG10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 10664 #define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk /*!< Port PG10 Pull-Down set */
<> 128:9bcdf88f62b0 10665 #define PWR_PDCRG_PG9_Pos (9U)
<> 128:9bcdf88f62b0 10666 #define PWR_PDCRG_PG9_Msk (0x1U << PWR_PDCRG_PG9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 10667 #define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk /*!< Port PG9 Pull-Down set */
<> 128:9bcdf88f62b0 10668 #define PWR_PDCRG_PG8_Pos (8U)
<> 128:9bcdf88f62b0 10669 #define PWR_PDCRG_PG8_Msk (0x1U << PWR_PDCRG_PG8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 10670 #define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk /*!< Port PG8 Pull-Down set */
<> 128:9bcdf88f62b0 10671 #define PWR_PDCRG_PG7_Pos (7U)
<> 128:9bcdf88f62b0 10672 #define PWR_PDCRG_PG7_Msk (0x1U << PWR_PDCRG_PG7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 10673 #define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk /*!< Port PG7 Pull-Down set */
<> 128:9bcdf88f62b0 10674 #define PWR_PDCRG_PG6_Pos (6U)
<> 128:9bcdf88f62b0 10675 #define PWR_PDCRG_PG6_Msk (0x1U << PWR_PDCRG_PG6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 10676 #define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk /*!< Port PG6 Pull-Down set */
<> 128:9bcdf88f62b0 10677 #define PWR_PDCRG_PG5_Pos (5U)
<> 128:9bcdf88f62b0 10678 #define PWR_PDCRG_PG5_Msk (0x1U << PWR_PDCRG_PG5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 10679 #define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk /*!< Port PG5 Pull-Down set */
<> 128:9bcdf88f62b0 10680 #define PWR_PDCRG_PG4_Pos (4U)
<> 128:9bcdf88f62b0 10681 #define PWR_PDCRG_PG4_Msk (0x1U << PWR_PDCRG_PG4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 10682 #define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk /*!< Port PG4 Pull-Down set */
<> 128:9bcdf88f62b0 10683 #define PWR_PDCRG_PG3_Pos (3U)
<> 128:9bcdf88f62b0 10684 #define PWR_PDCRG_PG3_Msk (0x1U << PWR_PDCRG_PG3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 10685 #define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk /*!< Port PG3 Pull-Down set */
<> 128:9bcdf88f62b0 10686 #define PWR_PDCRG_PG2_Pos (2U)
<> 128:9bcdf88f62b0 10687 #define PWR_PDCRG_PG2_Msk (0x1U << PWR_PDCRG_PG2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 10688 #define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk /*!< Port PG2 Pull-Down set */
<> 128:9bcdf88f62b0 10689 #define PWR_PDCRG_PG1_Pos (1U)
<> 128:9bcdf88f62b0 10690 #define PWR_PDCRG_PG1_Msk (0x1U << PWR_PDCRG_PG1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 10691 #define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk /*!< Port PG1 Pull-Down set */
<> 128:9bcdf88f62b0 10692 #define PWR_PDCRG_PG0_Pos (0U)
<> 128:9bcdf88f62b0 10693 #define PWR_PDCRG_PG0_Msk (0x1U << PWR_PDCRG_PG0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 10694 #define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk /*!< Port PG0 Pull-Down set */
<> 128:9bcdf88f62b0 10695
<> 128:9bcdf88f62b0 10696 /******************** Bit definition for PWR_PUCRH register ********************/
<> 128:9bcdf88f62b0 10697 #define PWR_PUCRH_PH1_Pos (1U)
<> 128:9bcdf88f62b0 10698 #define PWR_PUCRH_PH1_Msk (0x1U << PWR_PUCRH_PH1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 10699 #define PWR_PUCRH_PH1 PWR_PUCRH_PH1_Msk /*!< Port PH1 Pull-Up set */
<> 128:9bcdf88f62b0 10700 #define PWR_PUCRH_PH0_Pos (0U)
<> 128:9bcdf88f62b0 10701 #define PWR_PUCRH_PH0_Msk (0x1U << PWR_PUCRH_PH0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 10702 #define PWR_PUCRH_PH0 PWR_PUCRH_PH0_Msk /*!< Port PH0 Pull-Up set */
<> 128:9bcdf88f62b0 10703
<> 128:9bcdf88f62b0 10704 /******************** Bit definition for PWR_PDCRH register ********************/
<> 128:9bcdf88f62b0 10705 #define PWR_PDCRH_PH1_Pos (1U)
<> 128:9bcdf88f62b0 10706 #define PWR_PDCRH_PH1_Msk (0x1U << PWR_PDCRH_PH1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 10707 #define PWR_PDCRH_PH1 PWR_PDCRH_PH1_Msk /*!< Port PH1 Pull-Down set */
<> 128:9bcdf88f62b0 10708 #define PWR_PDCRH_PH0_Pos (0U)
<> 128:9bcdf88f62b0 10709 #define PWR_PDCRH_PH0_Msk (0x1U << PWR_PDCRH_PH0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 10710 #define PWR_PDCRH_PH0 PWR_PDCRH_PH0_Msk /*!< Port PH0 Pull-Down set */
<> 128:9bcdf88f62b0 10711
<> 128:9bcdf88f62b0 10712
<> 128:9bcdf88f62b0 10713 /******************************************************************************/
<> 128:9bcdf88f62b0 10714 /* */
<> 128:9bcdf88f62b0 10715 /* Reset and Clock Control */
<> 128:9bcdf88f62b0 10716 /* */
<> 128:9bcdf88f62b0 10717 /******************************************************************************/
<> 128:9bcdf88f62b0 10718 /*
<> 128:9bcdf88f62b0 10719 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
<> 128:9bcdf88f62b0 10720 */
<> 128:9bcdf88f62b0 10721 #define RCC_PLLSAI2_SUPPORT
<> 128:9bcdf88f62b0 10722
<> 128:9bcdf88f62b0 10723 /******************** Bit definition for RCC_CR register ********************/
<> 128:9bcdf88f62b0 10724 #define RCC_CR_MSION_Pos (0U)
<> 128:9bcdf88f62b0 10725 #define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 10726 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed oscillator (MSI) clock enable */
<> 128:9bcdf88f62b0 10727 #define RCC_CR_MSIRDY_Pos (1U)
<> 128:9bcdf88f62b0 10728 #define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 10729 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
<> 128:9bcdf88f62b0 10730 #define RCC_CR_MSIPLLEN_Pos (2U)
<> 128:9bcdf88f62b0 10731 #define RCC_CR_MSIPLLEN_Msk (0x1U << RCC_CR_MSIPLLEN_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 10732 #define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk /*!< Internal Multi Speed oscillator (MSI) PLL enable */
<> 128:9bcdf88f62b0 10733 #define RCC_CR_MSIRGSEL_Pos (3U)
<> 128:9bcdf88f62b0 10734 #define RCC_CR_MSIRGSEL_Msk (0x1U << RCC_CR_MSIRGSEL_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 10735 #define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk /*!< Internal Multi Speed oscillator (MSI) range selection */
<> 128:9bcdf88f62b0 10736
<> 128:9bcdf88f62b0 10737 /*!< MSIRANGE configuration : 12 frequency ranges available */
<> 128:9bcdf88f62b0 10738 #define RCC_CR_MSIRANGE_Pos (4U)
<> 128:9bcdf88f62b0 10739 #define RCC_CR_MSIRANGE_Msk (0xFU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000F0 */
<> 128:9bcdf88f62b0 10740 #define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk /*!< Internal Multi Speed oscillator (MSI) clock Range */
<> 128:9bcdf88f62b0 10741 #define RCC_CR_MSIRANGE_0 (0x0U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000000 */
<> 128:9bcdf88f62b0 10742 #define RCC_CR_MSIRANGE_1 (0x1U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 10743 #define RCC_CR_MSIRANGE_2 (0x2U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 10744 #define RCC_CR_MSIRANGE_3 (0x3U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000030 */
<> 128:9bcdf88f62b0 10745 #define RCC_CR_MSIRANGE_4 (0x4U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 10746 #define RCC_CR_MSIRANGE_5 (0x5U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000050 */
<> 128:9bcdf88f62b0 10747 #define RCC_CR_MSIRANGE_6 (0x6U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000060 */
<> 128:9bcdf88f62b0 10748 #define RCC_CR_MSIRANGE_7 (0x7U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000070 */
<> 128:9bcdf88f62b0 10749 #define RCC_CR_MSIRANGE_8 (0x8U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 10750 #define RCC_CR_MSIRANGE_9 (0x9U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000090 */
<> 128:9bcdf88f62b0 10751 #define RCC_CR_MSIRANGE_10 (0xAU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000A0 */
<> 128:9bcdf88f62b0 10752 #define RCC_CR_MSIRANGE_11 (0xBU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000B0 */
<> 128:9bcdf88f62b0 10753
<> 128:9bcdf88f62b0 10754 #define RCC_CR_HSION_Pos (8U)
<> 128:9bcdf88f62b0 10755 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 10756 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
<> 128:9bcdf88f62b0 10757 #define RCC_CR_HSIKERON_Pos (9U)
<> 128:9bcdf88f62b0 10758 #define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 10759 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
<> 128:9bcdf88f62b0 10760 #define RCC_CR_HSIRDY_Pos (10U)
<> 128:9bcdf88f62b0 10761 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 10762 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
<> 128:9bcdf88f62b0 10763 #define RCC_CR_HSIASFS_Pos (11U)
<> 128:9bcdf88f62b0 10764 #define RCC_CR_HSIASFS_Msk (0x1U << RCC_CR_HSIASFS_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 10765 #define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk /*!< HSI16 Automatic Start from Stop */
<> 128:9bcdf88f62b0 10766
<> 128:9bcdf88f62b0 10767 #define RCC_CR_HSEON_Pos (16U)
<> 128:9bcdf88f62b0 10768 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 10769 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
<> 128:9bcdf88f62b0 10770 #define RCC_CR_HSERDY_Pos (17U)
<> 128:9bcdf88f62b0 10771 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 10772 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
<> 128:9bcdf88f62b0 10773 #define RCC_CR_HSEBYP_Pos (18U)
<> 128:9bcdf88f62b0 10774 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 10775 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
<> 128:9bcdf88f62b0 10776 #define RCC_CR_CSSON_Pos (19U)
<> 128:9bcdf88f62b0 10777 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 10778 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
<> 128:9bcdf88f62b0 10779
<> 128:9bcdf88f62b0 10780 #define RCC_CR_PLLON_Pos (24U)
<> 128:9bcdf88f62b0 10781 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 10782 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
<> 128:9bcdf88f62b0 10783 #define RCC_CR_PLLRDY_Pos (25U)
<> 128:9bcdf88f62b0 10784 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 10785 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
<> 128:9bcdf88f62b0 10786 #define RCC_CR_PLLSAI1ON_Pos (26U)
<> 128:9bcdf88f62b0 10787 #define RCC_CR_PLLSAI1ON_Msk (0x1U << RCC_CR_PLLSAI1ON_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 10788 #define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk /*!< SAI1 PLL enable */
<> 128:9bcdf88f62b0 10789 #define RCC_CR_PLLSAI1RDY_Pos (27U)
<> 128:9bcdf88f62b0 10790 #define RCC_CR_PLLSAI1RDY_Msk (0x1U << RCC_CR_PLLSAI1RDY_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 10791 #define RCC_CR_PLLSAI1RDY RCC_CR_PLLSAI1RDY_Msk /*!< SAI1 PLL ready */
<> 128:9bcdf88f62b0 10792 #define RCC_CR_PLLSAI2ON_Pos (28U)
<> 128:9bcdf88f62b0 10793 #define RCC_CR_PLLSAI2ON_Msk (0x1U << RCC_CR_PLLSAI2ON_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 10794 #define RCC_CR_PLLSAI2ON RCC_CR_PLLSAI2ON_Msk /*!< SAI2 PLL enable */
<> 128:9bcdf88f62b0 10795 #define RCC_CR_PLLSAI2RDY_Pos (29U)
<> 128:9bcdf88f62b0 10796 #define RCC_CR_PLLSAI2RDY_Msk (0x1U << RCC_CR_PLLSAI2RDY_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 10797 #define RCC_CR_PLLSAI2RDY RCC_CR_PLLSAI2RDY_Msk /*!< SAI2 PLL ready */
<> 128:9bcdf88f62b0 10798
<> 128:9bcdf88f62b0 10799 /******************** Bit definition for RCC_ICSCR register ***************/
<> 128:9bcdf88f62b0 10800 /*!< MSICAL configuration */
<> 128:9bcdf88f62b0 10801 #define RCC_ICSCR_MSICAL_Pos (0U)
<> 128:9bcdf88f62b0 10802 #define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 10803 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< MSICAL[7:0] bits */
<> 128:9bcdf88f62b0 10804 #define RCC_ICSCR_MSICAL_0 (0x01U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 10805 #define RCC_ICSCR_MSICAL_1 (0x02U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 10806 #define RCC_ICSCR_MSICAL_2 (0x04U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 10807 #define RCC_ICSCR_MSICAL_3 (0x08U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 10808 #define RCC_ICSCR_MSICAL_4 (0x10U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 10809 #define RCC_ICSCR_MSICAL_5 (0x20U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 10810 #define RCC_ICSCR_MSICAL_6 (0x40U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 10811 #define RCC_ICSCR_MSICAL_7 (0x80U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 10812
<> 128:9bcdf88f62b0 10813 /*!< MSITRIM configuration */
<> 128:9bcdf88f62b0 10814 #define RCC_ICSCR_MSITRIM_Pos (8U)
<> 128:9bcdf88f62b0 10815 #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 10816 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< MSITRIM[7:0] bits */
<> 128:9bcdf88f62b0 10817 #define RCC_ICSCR_MSITRIM_0 (0x01U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 10818 #define RCC_ICSCR_MSITRIM_1 (0x02U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 10819 #define RCC_ICSCR_MSITRIM_2 (0x04U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 10820 #define RCC_ICSCR_MSITRIM_3 (0x08U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 10821 #define RCC_ICSCR_MSITRIM_4 (0x10U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 10822 #define RCC_ICSCR_MSITRIM_5 (0x20U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 10823 #define RCC_ICSCR_MSITRIM_6 (0x40U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 10824 #define RCC_ICSCR_MSITRIM_7 (0x80U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 10825
<> 128:9bcdf88f62b0 10826 /*!< HSICAL configuration */
<> 128:9bcdf88f62b0 10827 #define RCC_ICSCR_HSICAL_Pos (16U)
<> 128:9bcdf88f62b0 10828 #define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 10829 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
<> 128:9bcdf88f62b0 10830 #define RCC_ICSCR_HSICAL_0 (0x01U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 10831 #define RCC_ICSCR_HSICAL_1 (0x02U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 10832 #define RCC_ICSCR_HSICAL_2 (0x04U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 10833 #define RCC_ICSCR_HSICAL_3 (0x08U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 10834 #define RCC_ICSCR_HSICAL_4 (0x10U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 10835 #define RCC_ICSCR_HSICAL_5 (0x20U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 10836 #define RCC_ICSCR_HSICAL_6 (0x40U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 10837 #define RCC_ICSCR_HSICAL_7 (0x80U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 10838
<> 128:9bcdf88f62b0 10839 /*!< HSITRIM configuration */
<> 128:9bcdf88f62b0 10840 #define RCC_ICSCR_HSITRIM_Pos (24U)
<> 128:9bcdf88f62b0 10841 #define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
<> 128:9bcdf88f62b0 10842 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */
<> 128:9bcdf88f62b0 10843 #define RCC_ICSCR_HSITRIM_0 (0x01U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 10844 #define RCC_ICSCR_HSITRIM_1 (0x02U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 10845 #define RCC_ICSCR_HSITRIM_2 (0x04U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 10846 #define RCC_ICSCR_HSITRIM_3 (0x08U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 10847 #define RCC_ICSCR_HSITRIM_4 (0x10U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 10848
<> 128:9bcdf88f62b0 10849 /******************** Bit definition for RCC_CFGR register ******************/
<> 128:9bcdf88f62b0 10850 /*!< SW configuration */
<> 128:9bcdf88f62b0 10851 #define RCC_CFGR_SW_Pos (0U)
<> 128:9bcdf88f62b0 10852 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 10853 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
<> 128:9bcdf88f62b0 10854 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 10855 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 10856
<> 128:9bcdf88f62b0 10857 #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI oscillator selection as system clock */
<> 128:9bcdf88f62b0 10858 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */
<> 128:9bcdf88f62b0 10859 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */
<> 128:9bcdf88f62b0 10860 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */
<> 128:9bcdf88f62b0 10861
<> 128:9bcdf88f62b0 10862 /*!< SWS configuration */
<> 128:9bcdf88f62b0 10863 #define RCC_CFGR_SWS_Pos (2U)
<> 128:9bcdf88f62b0 10864 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
<> 128:9bcdf88f62b0 10865 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
<> 128:9bcdf88f62b0 10866 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 10867 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 10868
<> 128:9bcdf88f62b0 10869 #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
<> 128:9bcdf88f62b0 10870 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */
<> 128:9bcdf88f62b0 10871 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
<> 128:9bcdf88f62b0 10872 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
<> 128:9bcdf88f62b0 10873
<> 128:9bcdf88f62b0 10874 /*!< HPRE configuration */
<> 128:9bcdf88f62b0 10875 #define RCC_CFGR_HPRE_Pos (4U)
<> 128:9bcdf88f62b0 10876 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
<> 128:9bcdf88f62b0 10877 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
<> 128:9bcdf88f62b0 10878 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 10879 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 10880 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 10881 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 10882
<> 128:9bcdf88f62b0 10883 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
<> 128:9bcdf88f62b0 10884 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
<> 128:9bcdf88f62b0 10885 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
<> 128:9bcdf88f62b0 10886 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
<> 128:9bcdf88f62b0 10887 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
<> 128:9bcdf88f62b0 10888 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
<> 128:9bcdf88f62b0 10889 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
<> 128:9bcdf88f62b0 10890 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
<> 128:9bcdf88f62b0 10891 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
<> 128:9bcdf88f62b0 10892
<> 128:9bcdf88f62b0 10893 /*!< PPRE1 configuration */
<> 128:9bcdf88f62b0 10894 #define RCC_CFGR_PPRE1_Pos (8U)
<> 128:9bcdf88f62b0 10895 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
<> 128:9bcdf88f62b0 10896 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
<> 128:9bcdf88f62b0 10897 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 10898 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 10899 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 10900
<> 128:9bcdf88f62b0 10901 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
<> 128:9bcdf88f62b0 10902 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
<> 128:9bcdf88f62b0 10903 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
<> 128:9bcdf88f62b0 10904 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
<> 128:9bcdf88f62b0 10905 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
<> 128:9bcdf88f62b0 10906
<> 128:9bcdf88f62b0 10907 /*!< PPRE2 configuration */
<> 128:9bcdf88f62b0 10908 #define RCC_CFGR_PPRE2_Pos (11U)
<> 128:9bcdf88f62b0 10909 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
<> 128:9bcdf88f62b0 10910 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
<> 128:9bcdf88f62b0 10911 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 10912 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 10913 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 10914
<> 128:9bcdf88f62b0 10915 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
<> 128:9bcdf88f62b0 10916 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
<> 128:9bcdf88f62b0 10917 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
<> 128:9bcdf88f62b0 10918 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
<> 128:9bcdf88f62b0 10919 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
<> 128:9bcdf88f62b0 10920
<> 128:9bcdf88f62b0 10921 #define RCC_CFGR_STOPWUCK_Pos (15U)
<> 128:9bcdf88f62b0 10922 #define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 10923 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */
<> 128:9bcdf88f62b0 10924
<> 128:9bcdf88f62b0 10925 /*!< MCOSEL configuration */
<> 128:9bcdf88f62b0 10926 #define RCC_CFGR_MCOSEL_Pos (24U)
<> 128:9bcdf88f62b0 10927 #define RCC_CFGR_MCOSEL_Msk (0x7U << RCC_CFGR_MCOSEL_Pos) /*!< 0x07000000 */
<> 128:9bcdf88f62b0 10928 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [2:0] bits (Clock output selection) */
<> 128:9bcdf88f62b0 10929 #define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 10930 #define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 10931 #define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 10932
<> 128:9bcdf88f62b0 10933 #define RCC_CFGR_MCOPRE_Pos (28U)
<> 128:9bcdf88f62b0 10934 #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
<> 128:9bcdf88f62b0 10935 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
<> 128:9bcdf88f62b0 10936 #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 10937 #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 10938 #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 10939
<> 128:9bcdf88f62b0 10940 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
<> 128:9bcdf88f62b0 10941 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
<> 128:9bcdf88f62b0 10942 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
<> 128:9bcdf88f62b0 10943 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
<> 128:9bcdf88f62b0 10944 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
<> 128:9bcdf88f62b0 10945
<> 128:9bcdf88f62b0 10946 /* Legacy aliases */
<> 128:9bcdf88f62b0 10947 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
<> 128:9bcdf88f62b0 10948 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
<> 128:9bcdf88f62b0 10949 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
<> 128:9bcdf88f62b0 10950 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
<> 128:9bcdf88f62b0 10951 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
<> 128:9bcdf88f62b0 10952 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
<> 128:9bcdf88f62b0 10953
<> 128:9bcdf88f62b0 10954 /******************** Bit definition for RCC_PLLCFGR register ***************/
<> 128:9bcdf88f62b0 10955 #define RCC_PLLCFGR_PLLSRC_Pos (0U)
<> 128:9bcdf88f62b0 10956 #define RCC_PLLCFGR_PLLSRC_Msk (0x3U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 10957 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
<> 128:9bcdf88f62b0 10958
<> 128:9bcdf88f62b0 10959 #define RCC_PLLCFGR_PLLSRC_MSI_Pos (0U)
<> 128:9bcdf88f62b0 10960 #define RCC_PLLCFGR_PLLSRC_MSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 10961 #define RCC_PLLCFGR_PLLSRC_MSI RCC_PLLCFGR_PLLSRC_MSI_Msk /*!< MSI oscillator source clock selected */
<> 128:9bcdf88f62b0 10962 #define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
<> 128:9bcdf88f62b0 10963 #define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 10964 #define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
<> 128:9bcdf88f62b0 10965 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
<> 128:9bcdf88f62b0 10966 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 10967 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
<> 128:9bcdf88f62b0 10968
<> 128:9bcdf88f62b0 10969 #define RCC_PLLCFGR_PLLM_Pos (4U)
<> 128:9bcdf88f62b0 10970 #define RCC_PLLCFGR_PLLM_Msk (0x7U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */
<> 128:9bcdf88f62b0 10971 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
<> 128:9bcdf88f62b0 10972 #define RCC_PLLCFGR_PLLM_0 (0x1U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 10973 #define RCC_PLLCFGR_PLLM_1 (0x2U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 10974 #define RCC_PLLCFGR_PLLM_2 (0x4U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 10975
<> 128:9bcdf88f62b0 10976 #define RCC_PLLCFGR_PLLN_Pos (8U)
<> 128:9bcdf88f62b0 10977 #define RCC_PLLCFGR_PLLN_Msk (0x7FU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
<> 128:9bcdf88f62b0 10978 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
<> 128:9bcdf88f62b0 10979 #define RCC_PLLCFGR_PLLN_0 (0x01U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 10980 #define RCC_PLLCFGR_PLLN_1 (0x02U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 10981 #define RCC_PLLCFGR_PLLN_2 (0x04U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 10982 #define RCC_PLLCFGR_PLLN_3 (0x08U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 10983 #define RCC_PLLCFGR_PLLN_4 (0x10U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 10984 #define RCC_PLLCFGR_PLLN_5 (0x20U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 10985 #define RCC_PLLCFGR_PLLN_6 (0x40U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 10986
<> 128:9bcdf88f62b0 10987 #define RCC_PLLCFGR_PLLPEN_Pos (16U)
<> 128:9bcdf88f62b0 10988 #define RCC_PLLCFGR_PLLPEN_Msk (0x1U << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 10989 #define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
<> 128:9bcdf88f62b0 10990 #define RCC_PLLCFGR_PLLP_Pos (17U)
<> 128:9bcdf88f62b0 10991 #define RCC_PLLCFGR_PLLP_Msk (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 10992 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
<> 128:9bcdf88f62b0 10993 #define RCC_PLLCFGR_PLLQEN_Pos (20U)
<> 128:9bcdf88f62b0 10994 #define RCC_PLLCFGR_PLLQEN_Msk (0x1U << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 10995 #define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
<> 128:9bcdf88f62b0 10996
<> 128:9bcdf88f62b0 10997 #define RCC_PLLCFGR_PLLQ_Pos (21U)
<> 128:9bcdf88f62b0 10998 #define RCC_PLLCFGR_PLLQ_Msk (0x3U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
<> 128:9bcdf88f62b0 10999 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
<> 128:9bcdf88f62b0 11000 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 11001 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 11002
<> 128:9bcdf88f62b0 11003 #define RCC_PLLCFGR_PLLREN_Pos (24U)
<> 128:9bcdf88f62b0 11004 #define RCC_PLLCFGR_PLLREN_Msk (0x1U << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 11005 #define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
<> 128:9bcdf88f62b0 11006 #define RCC_PLLCFGR_PLLR_Pos (25U)
<> 128:9bcdf88f62b0 11007 #define RCC_PLLCFGR_PLLR_Msk (0x3U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
<> 128:9bcdf88f62b0 11008 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
<> 128:9bcdf88f62b0 11009 #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 11010 #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 11011
<> 128:9bcdf88f62b0 11012 /******************** Bit definition for RCC_PLLSAI1CFGR register ************/
<> 128:9bcdf88f62b0 11013 #define RCC_PLLSAI1CFGR_PLLSAI1N_Pos (8U)
<> 128:9bcdf88f62b0 11014 #define RCC_PLLSAI1CFGR_PLLSAI1N_Msk (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */
<> 128:9bcdf88f62b0 11015 #define RCC_PLLSAI1CFGR_PLLSAI1N RCC_PLLSAI1CFGR_PLLSAI1N_Msk
<> 128:9bcdf88f62b0 11016 #define RCC_PLLSAI1CFGR_PLLSAI1N_0 (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 11017 #define RCC_PLLSAI1CFGR_PLLSAI1N_1 (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 11018 #define RCC_PLLSAI1CFGR_PLLSAI1N_2 (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 11019 #define RCC_PLLSAI1CFGR_PLLSAI1N_3 (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 11020 #define RCC_PLLSAI1CFGR_PLLSAI1N_4 (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 11021 #define RCC_PLLSAI1CFGR_PLLSAI1N_5 (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 11022 #define RCC_PLLSAI1CFGR_PLLSAI1N_6 (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 11023
<> 128:9bcdf88f62b0 11024 #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos (16U)
<> 128:9bcdf88f62b0 11025 #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 11026 #define RCC_PLLSAI1CFGR_PLLSAI1PEN RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk
<> 128:9bcdf88f62b0 11027 #define RCC_PLLSAI1CFGR_PLLSAI1P_Pos (17U)
<> 128:9bcdf88f62b0 11028 #define RCC_PLLSAI1CFGR_PLLSAI1P_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 11029 #define RCC_PLLSAI1CFGR_PLLSAI1P RCC_PLLSAI1CFGR_PLLSAI1P_Msk
<> 128:9bcdf88f62b0 11030
<> 128:9bcdf88f62b0 11031 #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos (20U)
<> 128:9bcdf88f62b0 11032 #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 11033 #define RCC_PLLSAI1CFGR_PLLSAI1QEN RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk
<> 128:9bcdf88f62b0 11034 #define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos (21U)
<> 128:9bcdf88f62b0 11035 #define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */
<> 128:9bcdf88f62b0 11036 #define RCC_PLLSAI1CFGR_PLLSAI1Q RCC_PLLSAI1CFGR_PLLSAI1Q_Msk
<> 128:9bcdf88f62b0 11037 #define RCC_PLLSAI1CFGR_PLLSAI1Q_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 11038 #define RCC_PLLSAI1CFGR_PLLSAI1Q_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 11039
<> 128:9bcdf88f62b0 11040 #define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos (24U)
<> 128:9bcdf88f62b0 11041 #define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 11042 #define RCC_PLLSAI1CFGR_PLLSAI1REN RCC_PLLSAI1CFGR_PLLSAI1REN_Msk
<> 128:9bcdf88f62b0 11043 #define RCC_PLLSAI1CFGR_PLLSAI1R_Pos (25U)
<> 128:9bcdf88f62b0 11044 #define RCC_PLLSAI1CFGR_PLLSAI1R_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */
<> 128:9bcdf88f62b0 11045 #define RCC_PLLSAI1CFGR_PLLSAI1R RCC_PLLSAI1CFGR_PLLSAI1R_Msk
<> 128:9bcdf88f62b0 11046 #define RCC_PLLSAI1CFGR_PLLSAI1R_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 11047 #define RCC_PLLSAI1CFGR_PLLSAI1R_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 11048
<> 128:9bcdf88f62b0 11049 /******************** Bit definition for RCC_PLLSAI2CFGR register ************/
<> 128:9bcdf88f62b0 11050 #define RCC_PLLSAI2CFGR_PLLSAI2N_Pos (8U)
<> 128:9bcdf88f62b0 11051 #define RCC_PLLSAI2CFGR_PLLSAI2N_Msk (0x7FU << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00007F00 */
<> 128:9bcdf88f62b0 11052 #define RCC_PLLSAI2CFGR_PLLSAI2N RCC_PLLSAI2CFGR_PLLSAI2N_Msk
<> 128:9bcdf88f62b0 11053 #define RCC_PLLSAI2CFGR_PLLSAI2N_0 (0x01U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 11054 #define RCC_PLLSAI2CFGR_PLLSAI2N_1 (0x02U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 11055 #define RCC_PLLSAI2CFGR_PLLSAI2N_2 (0x04U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 11056 #define RCC_PLLSAI2CFGR_PLLSAI2N_3 (0x08U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 11057 #define RCC_PLLSAI2CFGR_PLLSAI2N_4 (0x10U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 11058 #define RCC_PLLSAI2CFGR_PLLSAI2N_5 (0x20U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 11059 #define RCC_PLLSAI2CFGR_PLLSAI2N_6 (0x40U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 11060
<> 128:9bcdf88f62b0 11061 #define RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos (16U)
<> 128:9bcdf88f62b0 11062 #define RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 11063 #define RCC_PLLSAI2CFGR_PLLSAI2PEN RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk
<> 128:9bcdf88f62b0 11064 #define RCC_PLLSAI2CFGR_PLLSAI2P_Pos (17U)
<> 128:9bcdf88f62b0 11065 #define RCC_PLLSAI2CFGR_PLLSAI2P_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 11066 #define RCC_PLLSAI2CFGR_PLLSAI2P RCC_PLLSAI2CFGR_PLLSAI2P_Msk
<> 128:9bcdf88f62b0 11067
<> 128:9bcdf88f62b0 11068 #define RCC_PLLSAI2CFGR_PLLSAI2REN_Pos (24U)
<> 128:9bcdf88f62b0 11069 #define RCC_PLLSAI2CFGR_PLLSAI2REN_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2REN_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 11070 #define RCC_PLLSAI2CFGR_PLLSAI2REN RCC_PLLSAI2CFGR_PLLSAI2REN_Msk
<> 128:9bcdf88f62b0 11071 #define RCC_PLLSAI2CFGR_PLLSAI2R_Pos (25U)
<> 128:9bcdf88f62b0 11072 #define RCC_PLLSAI2CFGR_PLLSAI2R_Msk (0x3U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x06000000 */
<> 128:9bcdf88f62b0 11073 #define RCC_PLLSAI2CFGR_PLLSAI2R RCC_PLLSAI2CFGR_PLLSAI2R_Msk
<> 128:9bcdf88f62b0 11074 #define RCC_PLLSAI2CFGR_PLLSAI2R_0 (0x1U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 11075 #define RCC_PLLSAI2CFGR_PLLSAI2R_1 (0x2U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 11076
<> 128:9bcdf88f62b0 11077 /******************** Bit definition for RCC_CIER register ******************/
<> 128:9bcdf88f62b0 11078 #define RCC_CIER_LSIRDYIE_Pos (0U)
<> 128:9bcdf88f62b0 11079 #define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11080 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
<> 128:9bcdf88f62b0 11081 #define RCC_CIER_LSERDYIE_Pos (1U)
<> 128:9bcdf88f62b0 11082 #define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 11083 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
<> 128:9bcdf88f62b0 11084 #define RCC_CIER_MSIRDYIE_Pos (2U)
<> 128:9bcdf88f62b0 11085 #define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 11086 #define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk
<> 128:9bcdf88f62b0 11087 #define RCC_CIER_HSIRDYIE_Pos (3U)
<> 128:9bcdf88f62b0 11088 #define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 11089 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
<> 128:9bcdf88f62b0 11090 #define RCC_CIER_HSERDYIE_Pos (4U)
<> 128:9bcdf88f62b0 11091 #define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 11092 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
<> 128:9bcdf88f62b0 11093 #define RCC_CIER_PLLRDYIE_Pos (5U)
<> 128:9bcdf88f62b0 11094 #define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 11095 #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
<> 128:9bcdf88f62b0 11096 #define RCC_CIER_PLLSAI1RDYIE_Pos (6U)
<> 128:9bcdf88f62b0 11097 #define RCC_CIER_PLLSAI1RDYIE_Msk (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 11098 #define RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE_Msk
<> 128:9bcdf88f62b0 11099 #define RCC_CIER_PLLSAI2RDYIE_Pos (7U)
<> 128:9bcdf88f62b0 11100 #define RCC_CIER_PLLSAI2RDYIE_Msk (0x1U << RCC_CIER_PLLSAI2RDYIE_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 11101 #define RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE_Msk
<> 128:9bcdf88f62b0 11102 #define RCC_CIER_LSECSSIE_Pos (9U)
<> 128:9bcdf88f62b0 11103 #define RCC_CIER_LSECSSIE_Msk (0x1U << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 11104 #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
<> 128:9bcdf88f62b0 11105
<> 128:9bcdf88f62b0 11106 /******************** Bit definition for RCC_CIFR register ******************/
<> 128:9bcdf88f62b0 11107 #define RCC_CIFR_LSIRDYF_Pos (0U)
<> 128:9bcdf88f62b0 11108 #define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11109 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
<> 128:9bcdf88f62b0 11110 #define RCC_CIFR_LSERDYF_Pos (1U)
<> 128:9bcdf88f62b0 11111 #define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 11112 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
<> 128:9bcdf88f62b0 11113 #define RCC_CIFR_MSIRDYF_Pos (2U)
<> 128:9bcdf88f62b0 11114 #define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 11115 #define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk
<> 128:9bcdf88f62b0 11116 #define RCC_CIFR_HSIRDYF_Pos (3U)
<> 128:9bcdf88f62b0 11117 #define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 11118 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
<> 128:9bcdf88f62b0 11119 #define RCC_CIFR_HSERDYF_Pos (4U)
<> 128:9bcdf88f62b0 11120 #define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 11121 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
<> 128:9bcdf88f62b0 11122 #define RCC_CIFR_PLLRDYF_Pos (5U)
<> 128:9bcdf88f62b0 11123 #define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 11124 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
<> 128:9bcdf88f62b0 11125 #define RCC_CIFR_PLLSAI1RDYF_Pos (6U)
<> 128:9bcdf88f62b0 11126 #define RCC_CIFR_PLLSAI1RDYF_Msk (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 11127 #define RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF_Msk
<> 128:9bcdf88f62b0 11128 #define RCC_CIFR_PLLSAI2RDYF_Pos (7U)
<> 128:9bcdf88f62b0 11129 #define RCC_CIFR_PLLSAI2RDYF_Msk (0x1U << RCC_CIFR_PLLSAI2RDYF_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 11130 #define RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF_Msk
<> 128:9bcdf88f62b0 11131 #define RCC_CIFR_CSSF_Pos (8U)
<> 128:9bcdf88f62b0 11132 #define RCC_CIFR_CSSF_Msk (0x1U << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 11133 #define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
<> 128:9bcdf88f62b0 11134 #define RCC_CIFR_LSECSSF_Pos (9U)
<> 128:9bcdf88f62b0 11135 #define RCC_CIFR_LSECSSF_Msk (0x1U << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 11136 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
<> 128:9bcdf88f62b0 11137
<> 128:9bcdf88f62b0 11138 /******************** Bit definition for RCC_CICR register ******************/
<> 128:9bcdf88f62b0 11139 #define RCC_CICR_LSIRDYC_Pos (0U)
<> 128:9bcdf88f62b0 11140 #define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11141 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
<> 128:9bcdf88f62b0 11142 #define RCC_CICR_LSERDYC_Pos (1U)
<> 128:9bcdf88f62b0 11143 #define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 11144 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
<> 128:9bcdf88f62b0 11145 #define RCC_CICR_MSIRDYC_Pos (2U)
<> 128:9bcdf88f62b0 11146 #define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 11147 #define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk
<> 128:9bcdf88f62b0 11148 #define RCC_CICR_HSIRDYC_Pos (3U)
<> 128:9bcdf88f62b0 11149 #define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 11150 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
<> 128:9bcdf88f62b0 11151 #define RCC_CICR_HSERDYC_Pos (4U)
<> 128:9bcdf88f62b0 11152 #define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 11153 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
<> 128:9bcdf88f62b0 11154 #define RCC_CICR_PLLRDYC_Pos (5U)
<> 128:9bcdf88f62b0 11155 #define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 11156 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
<> 128:9bcdf88f62b0 11157 #define RCC_CICR_PLLSAI1RDYC_Pos (6U)
<> 128:9bcdf88f62b0 11158 #define RCC_CICR_PLLSAI1RDYC_Msk (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 11159 #define RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC_Msk
<> 128:9bcdf88f62b0 11160 #define RCC_CICR_PLLSAI2RDYC_Pos (7U)
<> 128:9bcdf88f62b0 11161 #define RCC_CICR_PLLSAI2RDYC_Msk (0x1U << RCC_CICR_PLLSAI2RDYC_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 11162 #define RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC_Msk
<> 128:9bcdf88f62b0 11163 #define RCC_CICR_CSSC_Pos (8U)
<> 128:9bcdf88f62b0 11164 #define RCC_CICR_CSSC_Msk (0x1U << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 11165 #define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
<> 128:9bcdf88f62b0 11166 #define RCC_CICR_LSECSSC_Pos (9U)
<> 128:9bcdf88f62b0 11167 #define RCC_CICR_LSECSSC_Msk (0x1U << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 11168 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
<> 128:9bcdf88f62b0 11169
<> 128:9bcdf88f62b0 11170 /******************** Bit definition for RCC_AHB1RSTR register **************/
<> 128:9bcdf88f62b0 11171 #define RCC_AHB1RSTR_DMA1RST_Pos (0U)
<> 128:9bcdf88f62b0 11172 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11173 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
<> 128:9bcdf88f62b0 11174 #define RCC_AHB1RSTR_DMA2RST_Pos (1U)
<> 128:9bcdf88f62b0 11175 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 11176 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
<> 128:9bcdf88f62b0 11177 #define RCC_AHB1RSTR_FLASHRST_Pos (8U)
<> 128:9bcdf88f62b0 11178 #define RCC_AHB1RSTR_FLASHRST_Msk (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 11179 #define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
<> 128:9bcdf88f62b0 11180 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
<> 128:9bcdf88f62b0 11181 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 11182 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
<> 128:9bcdf88f62b0 11183 #define RCC_AHB1RSTR_TSCRST_Pos (16U)
<> 128:9bcdf88f62b0 11184 #define RCC_AHB1RSTR_TSCRST_Msk (0x1U << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 11185 #define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk
<> 128:9bcdf88f62b0 11186
<> 128:9bcdf88f62b0 11187 /******************** Bit definition for RCC_AHB2RSTR register **************/
<> 128:9bcdf88f62b0 11188 #define RCC_AHB2RSTR_GPIOARST_Pos (0U)
<> 128:9bcdf88f62b0 11189 #define RCC_AHB2RSTR_GPIOARST_Msk (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11190 #define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
<> 128:9bcdf88f62b0 11191 #define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
<> 128:9bcdf88f62b0 11192 #define RCC_AHB2RSTR_GPIOBRST_Msk (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 11193 #define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
<> 128:9bcdf88f62b0 11194 #define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
<> 128:9bcdf88f62b0 11195 #define RCC_AHB2RSTR_GPIOCRST_Msk (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 11196 #define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
<> 128:9bcdf88f62b0 11197 #define RCC_AHB2RSTR_GPIODRST_Pos (3U)
<> 128:9bcdf88f62b0 11198 #define RCC_AHB2RSTR_GPIODRST_Msk (0x1U << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 11199 #define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
<> 128:9bcdf88f62b0 11200 #define RCC_AHB2RSTR_GPIOERST_Pos (4U)
<> 128:9bcdf88f62b0 11201 #define RCC_AHB2RSTR_GPIOERST_Msk (0x1U << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 11202 #define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
<> 128:9bcdf88f62b0 11203 #define RCC_AHB2RSTR_GPIOFRST_Pos (5U)
<> 128:9bcdf88f62b0 11204 #define RCC_AHB2RSTR_GPIOFRST_Msk (0x1U << RCC_AHB2RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 11205 #define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk
<> 128:9bcdf88f62b0 11206 #define RCC_AHB2RSTR_GPIOGRST_Pos (6U)
<> 128:9bcdf88f62b0 11207 #define RCC_AHB2RSTR_GPIOGRST_Msk (0x1U << RCC_AHB2RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 11208 #define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk
<> 128:9bcdf88f62b0 11209 #define RCC_AHB2RSTR_GPIOHRST_Pos (7U)
<> 128:9bcdf88f62b0 11210 #define RCC_AHB2RSTR_GPIOHRST_Msk (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 11211 #define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk
<> 128:9bcdf88f62b0 11212 #define RCC_AHB2RSTR_OTGFSRST_Pos (12U)
<> 128:9bcdf88f62b0 11213 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 11214 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
<> 128:9bcdf88f62b0 11215 #define RCC_AHB2RSTR_ADCRST_Pos (13U)
<> 128:9bcdf88f62b0 11216 #define RCC_AHB2RSTR_ADCRST_Msk (0x1U << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 11217 #define RCC_AHB2RSTR_ADCRST RCC_AHB2RSTR_ADCRST_Msk
<> 128:9bcdf88f62b0 11218 #define RCC_AHB2RSTR_AESRST_Pos (16U)
<> 128:9bcdf88f62b0 11219 #define RCC_AHB2RSTR_AESRST_Msk (0x1U << RCC_AHB2RSTR_AESRST_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 11220 #define RCC_AHB2RSTR_AESRST RCC_AHB2RSTR_AESRST_Msk
<> 128:9bcdf88f62b0 11221 #define RCC_AHB2RSTR_RNGRST_Pos (18U)
<> 128:9bcdf88f62b0 11222 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 11223 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
<> 128:9bcdf88f62b0 11224
<> 128:9bcdf88f62b0 11225 /******************** Bit definition for RCC_AHB3RSTR register **************/
<> 128:9bcdf88f62b0 11226 #define RCC_AHB3RSTR_FMCRST_Pos (0U)
<> 128:9bcdf88f62b0 11227 #define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11228 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
<> 128:9bcdf88f62b0 11229 #define RCC_AHB3RSTR_QSPIRST_Pos (8U)
<> 128:9bcdf88f62b0 11230 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 11231 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
<> 128:9bcdf88f62b0 11232
<> 128:9bcdf88f62b0 11233 /******************** Bit definition for RCC_APB1RSTR1 register **************/
<> 128:9bcdf88f62b0 11234 #define RCC_APB1RSTR1_TIM2RST_Pos (0U)
<> 128:9bcdf88f62b0 11235 #define RCC_APB1RSTR1_TIM2RST_Msk (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11236 #define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
<> 128:9bcdf88f62b0 11237 #define RCC_APB1RSTR1_TIM3RST_Pos (1U)
<> 128:9bcdf88f62b0 11238 #define RCC_APB1RSTR1_TIM3RST_Msk (0x1U << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 11239 #define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
<> 128:9bcdf88f62b0 11240 #define RCC_APB1RSTR1_TIM4RST_Pos (2U)
<> 128:9bcdf88f62b0 11241 #define RCC_APB1RSTR1_TIM4RST_Msk (0x1U << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 11242 #define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
<> 128:9bcdf88f62b0 11243 #define RCC_APB1RSTR1_TIM5RST_Pos (3U)
<> 128:9bcdf88f62b0 11244 #define RCC_APB1RSTR1_TIM5RST_Msk (0x1U << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 11245 #define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk
<> 128:9bcdf88f62b0 11246 #define RCC_APB1RSTR1_TIM6RST_Pos (4U)
<> 128:9bcdf88f62b0 11247 #define RCC_APB1RSTR1_TIM6RST_Msk (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 11248 #define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
<> 128:9bcdf88f62b0 11249 #define RCC_APB1RSTR1_TIM7RST_Pos (5U)
<> 128:9bcdf88f62b0 11250 #define RCC_APB1RSTR1_TIM7RST_Msk (0x1U << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 11251 #define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
<> 128:9bcdf88f62b0 11252 #define RCC_APB1RSTR1_LCDRST_Pos (9U)
<> 128:9bcdf88f62b0 11253 #define RCC_APB1RSTR1_LCDRST_Msk (0x1U << RCC_APB1RSTR1_LCDRST_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 11254 #define RCC_APB1RSTR1_LCDRST RCC_APB1RSTR1_LCDRST_Msk
<> 128:9bcdf88f62b0 11255 #define RCC_APB1RSTR1_SPI2RST_Pos (14U)
<> 128:9bcdf88f62b0 11256 #define RCC_APB1RSTR1_SPI2RST_Msk (0x1U << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 11257 #define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
<> 128:9bcdf88f62b0 11258 #define RCC_APB1RSTR1_SPI3RST_Pos (15U)
<> 128:9bcdf88f62b0 11259 #define RCC_APB1RSTR1_SPI3RST_Msk (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 11260 #define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
<> 128:9bcdf88f62b0 11261 #define RCC_APB1RSTR1_USART2RST_Pos (17U)
<> 128:9bcdf88f62b0 11262 #define RCC_APB1RSTR1_USART2RST_Msk (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 11263 #define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
<> 128:9bcdf88f62b0 11264 #define RCC_APB1RSTR1_USART3RST_Pos (18U)
<> 128:9bcdf88f62b0 11265 #define RCC_APB1RSTR1_USART3RST_Msk (0x1U << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 11266 #define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
<> 128:9bcdf88f62b0 11267 #define RCC_APB1RSTR1_UART4RST_Pos (19U)
<> 128:9bcdf88f62b0 11268 #define RCC_APB1RSTR1_UART4RST_Msk (0x1U << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 11269 #define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk
<> 128:9bcdf88f62b0 11270 #define RCC_APB1RSTR1_UART5RST_Pos (20U)
<> 128:9bcdf88f62b0 11271 #define RCC_APB1RSTR1_UART5RST_Msk (0x1U << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 11272 #define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk
<> 128:9bcdf88f62b0 11273 #define RCC_APB1RSTR1_I2C1RST_Pos (21U)
<> 128:9bcdf88f62b0 11274 #define RCC_APB1RSTR1_I2C1RST_Msk (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 11275 #define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
<> 128:9bcdf88f62b0 11276 #define RCC_APB1RSTR1_I2C2RST_Pos (22U)
<> 128:9bcdf88f62b0 11277 #define RCC_APB1RSTR1_I2C2RST_Msk (0x1U << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 11278 #define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
<> 128:9bcdf88f62b0 11279 #define RCC_APB1RSTR1_I2C3RST_Pos (23U)
<> 128:9bcdf88f62b0 11280 #define RCC_APB1RSTR1_I2C3RST_Msk (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 11281 #define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
<> 128:9bcdf88f62b0 11282 #define RCC_APB1RSTR1_CAN1RST_Pos (25U)
<> 128:9bcdf88f62b0 11283 #define RCC_APB1RSTR1_CAN1RST_Msk (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 11284 #define RCC_APB1RSTR1_CAN1RST RCC_APB1RSTR1_CAN1RST_Msk
<> 128:9bcdf88f62b0 11285 #define RCC_APB1RSTR1_PWRRST_Pos (28U)
<> 128:9bcdf88f62b0 11286 #define RCC_APB1RSTR1_PWRRST_Msk (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 11287 #define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
<> 128:9bcdf88f62b0 11288 #define RCC_APB1RSTR1_DAC1RST_Pos (29U)
<> 128:9bcdf88f62b0 11289 #define RCC_APB1RSTR1_DAC1RST_Msk (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 11290 #define RCC_APB1RSTR1_DAC1RST RCC_APB1RSTR1_DAC1RST_Msk
<> 128:9bcdf88f62b0 11291 #define RCC_APB1RSTR1_OPAMPRST_Pos (30U)
<> 128:9bcdf88f62b0 11292 #define RCC_APB1RSTR1_OPAMPRST_Msk (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 11293 #define RCC_APB1RSTR1_OPAMPRST RCC_APB1RSTR1_OPAMPRST_Msk
<> 128:9bcdf88f62b0 11294 #define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
<> 128:9bcdf88f62b0 11295 #define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 11296 #define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
<> 128:9bcdf88f62b0 11297
<> 128:9bcdf88f62b0 11298 /******************** Bit definition for RCC_APB1RSTR2 register **************/
<> 128:9bcdf88f62b0 11299 #define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
<> 128:9bcdf88f62b0 11300 #define RCC_APB1RSTR2_LPUART1RST_Msk (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11301 #define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
<> 128:9bcdf88f62b0 11302 #define RCC_APB1RSTR2_SWPMI1RST_Pos (2U)
<> 128:9bcdf88f62b0 11303 #define RCC_APB1RSTR2_SWPMI1RST_Msk (0x1U << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 11304 #define RCC_APB1RSTR2_SWPMI1RST RCC_APB1RSTR2_SWPMI1RST_Msk
<> 128:9bcdf88f62b0 11305 #define RCC_APB1RSTR2_LPTIM2RST_Pos (5U)
<> 128:9bcdf88f62b0 11306 #define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 11307 #define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk
<> 128:9bcdf88f62b0 11308
<> 128:9bcdf88f62b0 11309 /******************** Bit definition for RCC_APB2RSTR register **************/
<> 128:9bcdf88f62b0 11310 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
<> 128:9bcdf88f62b0 11311 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11312 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
<> 128:9bcdf88f62b0 11313 #define RCC_APB2RSTR_SDMMC1RST_Pos (10U)
<> 128:9bcdf88f62b0 11314 #define RCC_APB2RSTR_SDMMC1RST_Msk (0x1U << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 11315 #define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk
<> 128:9bcdf88f62b0 11316 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
<> 128:9bcdf88f62b0 11317 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 11318 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
<> 128:9bcdf88f62b0 11319 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
<> 128:9bcdf88f62b0 11320 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 11321 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
<> 128:9bcdf88f62b0 11322 #define RCC_APB2RSTR_TIM8RST_Pos (13U)
<> 128:9bcdf88f62b0 11323 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 11324 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
<> 128:9bcdf88f62b0 11325 #define RCC_APB2RSTR_USART1RST_Pos (14U)
<> 128:9bcdf88f62b0 11326 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 11327 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
<> 128:9bcdf88f62b0 11328 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
<> 128:9bcdf88f62b0 11329 #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 11330 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
<> 128:9bcdf88f62b0 11331 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
<> 128:9bcdf88f62b0 11332 #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 11333 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
<> 128:9bcdf88f62b0 11334 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
<> 128:9bcdf88f62b0 11335 #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 11336 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
<> 128:9bcdf88f62b0 11337 #define RCC_APB2RSTR_SAI1RST_Pos (21U)
<> 128:9bcdf88f62b0 11338 #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 11339 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
<> 128:9bcdf88f62b0 11340 #define RCC_APB2RSTR_SAI2RST_Pos (22U)
<> 128:9bcdf88f62b0 11341 #define RCC_APB2RSTR_SAI2RST_Msk (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 11342 #define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
<> 128:9bcdf88f62b0 11343 #define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
<> 128:9bcdf88f62b0 11344 #define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 11345 #define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
<> 128:9bcdf88f62b0 11346
<> 128:9bcdf88f62b0 11347 /******************** Bit definition for RCC_AHB1ENR register ***************/
<> 128:9bcdf88f62b0 11348 #define RCC_AHB1ENR_DMA1EN_Pos (0U)
<> 128:9bcdf88f62b0 11349 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11350 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
<> 128:9bcdf88f62b0 11351 #define RCC_AHB1ENR_DMA2EN_Pos (1U)
<> 128:9bcdf88f62b0 11352 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 11353 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
<> 128:9bcdf88f62b0 11354 #define RCC_AHB1ENR_FLASHEN_Pos (8U)
<> 128:9bcdf88f62b0 11355 #define RCC_AHB1ENR_FLASHEN_Msk (0x1U << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 11356 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
<> 128:9bcdf88f62b0 11357 #define RCC_AHB1ENR_CRCEN_Pos (12U)
<> 128:9bcdf88f62b0 11358 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 11359 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
<> 128:9bcdf88f62b0 11360 #define RCC_AHB1ENR_TSCEN_Pos (16U)
<> 128:9bcdf88f62b0 11361 #define RCC_AHB1ENR_TSCEN_Msk (0x1U << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 11362 #define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk
<> 128:9bcdf88f62b0 11363
<> 128:9bcdf88f62b0 11364 /******************** Bit definition for RCC_AHB2ENR register ***************/
<> 128:9bcdf88f62b0 11365 #define RCC_AHB2ENR_GPIOAEN_Pos (0U)
<> 128:9bcdf88f62b0 11366 #define RCC_AHB2ENR_GPIOAEN_Msk (0x1U << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11367 #define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
<> 128:9bcdf88f62b0 11368 #define RCC_AHB2ENR_GPIOBEN_Pos (1U)
<> 128:9bcdf88f62b0 11369 #define RCC_AHB2ENR_GPIOBEN_Msk (0x1U << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 11370 #define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
<> 128:9bcdf88f62b0 11371 #define RCC_AHB2ENR_GPIOCEN_Pos (2U)
<> 128:9bcdf88f62b0 11372 #define RCC_AHB2ENR_GPIOCEN_Msk (0x1U << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 11373 #define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
<> 128:9bcdf88f62b0 11374 #define RCC_AHB2ENR_GPIODEN_Pos (3U)
<> 128:9bcdf88f62b0 11375 #define RCC_AHB2ENR_GPIODEN_Msk (0x1U << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 11376 #define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
<> 128:9bcdf88f62b0 11377 #define RCC_AHB2ENR_GPIOEEN_Pos (4U)
<> 128:9bcdf88f62b0 11378 #define RCC_AHB2ENR_GPIOEEN_Msk (0x1U << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 11379 #define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
<> 128:9bcdf88f62b0 11380 #define RCC_AHB2ENR_GPIOFEN_Pos (5U)
<> 128:9bcdf88f62b0 11381 #define RCC_AHB2ENR_GPIOFEN_Msk (0x1U << RCC_AHB2ENR_GPIOFEN_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 11382 #define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk
<> 128:9bcdf88f62b0 11383 #define RCC_AHB2ENR_GPIOGEN_Pos (6U)
<> 128:9bcdf88f62b0 11384 #define RCC_AHB2ENR_GPIOGEN_Msk (0x1U << RCC_AHB2ENR_GPIOGEN_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 11385 #define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk
<> 128:9bcdf88f62b0 11386 #define RCC_AHB2ENR_GPIOHEN_Pos (7U)
<> 128:9bcdf88f62b0 11387 #define RCC_AHB2ENR_GPIOHEN_Msk (0x1U << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 11388 #define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk
<> 128:9bcdf88f62b0 11389 #define RCC_AHB2ENR_OTGFSEN_Pos (12U)
<> 128:9bcdf88f62b0 11390 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 11391 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
<> 128:9bcdf88f62b0 11392 #define RCC_AHB2ENR_ADCEN_Pos (13U)
<> 128:9bcdf88f62b0 11393 #define RCC_AHB2ENR_ADCEN_Msk (0x1U << RCC_AHB2ENR_ADCEN_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 11394 #define RCC_AHB2ENR_ADCEN RCC_AHB2ENR_ADCEN_Msk
<> 128:9bcdf88f62b0 11395 #define RCC_AHB2ENR_AESEN_Pos (16U)
<> 128:9bcdf88f62b0 11396 #define RCC_AHB2ENR_AESEN_Msk (0x1U << RCC_AHB2ENR_AESEN_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 11397 #define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk
<> 128:9bcdf88f62b0 11398 #define RCC_AHB2ENR_RNGEN_Pos (18U)
<> 128:9bcdf88f62b0 11399 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 11400 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
<> 128:9bcdf88f62b0 11401
<> 128:9bcdf88f62b0 11402 /******************** Bit definition for RCC_AHB3ENR register ***************/
<> 128:9bcdf88f62b0 11403 #define RCC_AHB3ENR_FMCEN_Pos (0U)
<> 128:9bcdf88f62b0 11404 #define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11405 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
<> 128:9bcdf88f62b0 11406 #define RCC_AHB3ENR_QSPIEN_Pos (8U)
<> 128:9bcdf88f62b0 11407 #define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 11408 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
<> 128:9bcdf88f62b0 11409
<> 128:9bcdf88f62b0 11410 /******************** Bit definition for RCC_APB1ENR1 register ***************/
<> 128:9bcdf88f62b0 11411 #define RCC_APB1ENR1_TIM2EN_Pos (0U)
<> 128:9bcdf88f62b0 11412 #define RCC_APB1ENR1_TIM2EN_Msk (0x1U << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11413 #define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
<> 128:9bcdf88f62b0 11414 #define RCC_APB1ENR1_TIM3EN_Pos (1U)
<> 128:9bcdf88f62b0 11415 #define RCC_APB1ENR1_TIM3EN_Msk (0x1U << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 11416 #define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
<> 128:9bcdf88f62b0 11417 #define RCC_APB1ENR1_TIM4EN_Pos (2U)
<> 128:9bcdf88f62b0 11418 #define RCC_APB1ENR1_TIM4EN_Msk (0x1U << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 11419 #define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
<> 128:9bcdf88f62b0 11420 #define RCC_APB1ENR1_TIM5EN_Pos (3U)
<> 128:9bcdf88f62b0 11421 #define RCC_APB1ENR1_TIM5EN_Msk (0x1U << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 11422 #define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk
<> 128:9bcdf88f62b0 11423 #define RCC_APB1ENR1_TIM6EN_Pos (4U)
<> 128:9bcdf88f62b0 11424 #define RCC_APB1ENR1_TIM6EN_Msk (0x1U << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 11425 #define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
<> 128:9bcdf88f62b0 11426 #define RCC_APB1ENR1_TIM7EN_Pos (5U)
<> 128:9bcdf88f62b0 11427 #define RCC_APB1ENR1_TIM7EN_Msk (0x1U << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 11428 #define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
<> 128:9bcdf88f62b0 11429 #define RCC_APB1ENR1_LCDEN_Pos (9U)
<> 128:9bcdf88f62b0 11430 #define RCC_APB1ENR1_LCDEN_Msk (0x1U << RCC_APB1ENR1_LCDEN_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 11431 #define RCC_APB1ENR1_LCDEN RCC_APB1ENR1_LCDEN_Msk
<> 128:9bcdf88f62b0 11432 #define RCC_APB1ENR1_WWDGEN_Pos (11U)
<> 128:9bcdf88f62b0 11433 #define RCC_APB1ENR1_WWDGEN_Msk (0x1U << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 11434 #define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
<> 128:9bcdf88f62b0 11435 #define RCC_APB1ENR1_SPI2EN_Pos (14U)
<> 128:9bcdf88f62b0 11436 #define RCC_APB1ENR1_SPI2EN_Msk (0x1U << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 11437 #define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
<> 128:9bcdf88f62b0 11438 #define RCC_APB1ENR1_SPI3EN_Pos (15U)
<> 128:9bcdf88f62b0 11439 #define RCC_APB1ENR1_SPI3EN_Msk (0x1U << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 11440 #define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
<> 128:9bcdf88f62b0 11441 #define RCC_APB1ENR1_USART2EN_Pos (17U)
<> 128:9bcdf88f62b0 11442 #define RCC_APB1ENR1_USART2EN_Msk (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 11443 #define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
<> 128:9bcdf88f62b0 11444 #define RCC_APB1ENR1_USART3EN_Pos (18U)
<> 128:9bcdf88f62b0 11445 #define RCC_APB1ENR1_USART3EN_Msk (0x1U << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 11446 #define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
<> 128:9bcdf88f62b0 11447 #define RCC_APB1ENR1_UART4EN_Pos (19U)
<> 128:9bcdf88f62b0 11448 #define RCC_APB1ENR1_UART4EN_Msk (0x1U << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 11449 #define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk
<> 128:9bcdf88f62b0 11450 #define RCC_APB1ENR1_UART5EN_Pos (20U)
<> 128:9bcdf88f62b0 11451 #define RCC_APB1ENR1_UART5EN_Msk (0x1U << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 11452 #define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk
<> 128:9bcdf88f62b0 11453 #define RCC_APB1ENR1_I2C1EN_Pos (21U)
<> 128:9bcdf88f62b0 11454 #define RCC_APB1ENR1_I2C1EN_Msk (0x1U << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 11455 #define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
<> 128:9bcdf88f62b0 11456 #define RCC_APB1ENR1_I2C2EN_Pos (22U)
<> 128:9bcdf88f62b0 11457 #define RCC_APB1ENR1_I2C2EN_Msk (0x1U << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 11458 #define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
<> 128:9bcdf88f62b0 11459 #define RCC_APB1ENR1_I2C3EN_Pos (23U)
<> 128:9bcdf88f62b0 11460 #define RCC_APB1ENR1_I2C3EN_Msk (0x1U << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 11461 #define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
<> 128:9bcdf88f62b0 11462 #define RCC_APB1ENR1_CAN1EN_Pos (25U)
<> 128:9bcdf88f62b0 11463 #define RCC_APB1ENR1_CAN1EN_Msk (0x1U << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 11464 #define RCC_APB1ENR1_CAN1EN RCC_APB1ENR1_CAN1EN_Msk
<> 128:9bcdf88f62b0 11465 #define RCC_APB1ENR1_PWREN_Pos (28U)
<> 128:9bcdf88f62b0 11466 #define RCC_APB1ENR1_PWREN_Msk (0x1U << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 11467 #define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
<> 128:9bcdf88f62b0 11468 #define RCC_APB1ENR1_DAC1EN_Pos (29U)
<> 128:9bcdf88f62b0 11469 #define RCC_APB1ENR1_DAC1EN_Msk (0x1U << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 11470 #define RCC_APB1ENR1_DAC1EN RCC_APB1ENR1_DAC1EN_Msk
<> 128:9bcdf88f62b0 11471 #define RCC_APB1ENR1_OPAMPEN_Pos (30U)
<> 128:9bcdf88f62b0 11472 #define RCC_APB1ENR1_OPAMPEN_Msk (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 11473 #define RCC_APB1ENR1_OPAMPEN RCC_APB1ENR1_OPAMPEN_Msk
<> 128:9bcdf88f62b0 11474 #define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
<> 128:9bcdf88f62b0 11475 #define RCC_APB1ENR1_LPTIM1EN_Msk (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 11476 #define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
<> 128:9bcdf88f62b0 11477
<> 128:9bcdf88f62b0 11478 /******************** Bit definition for RCC_APB1RSTR2 register **************/
<> 128:9bcdf88f62b0 11479 #define RCC_APB1ENR2_LPUART1EN_Pos (0U)
<> 128:9bcdf88f62b0 11480 #define RCC_APB1ENR2_LPUART1EN_Msk (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11481 #define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
<> 128:9bcdf88f62b0 11482 #define RCC_APB1ENR2_SWPMI1EN_Pos (2U)
<> 128:9bcdf88f62b0 11483 #define RCC_APB1ENR2_SWPMI1EN_Msk (0x1U << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 11484 #define RCC_APB1ENR2_SWPMI1EN RCC_APB1ENR2_SWPMI1EN_Msk
<> 128:9bcdf88f62b0 11485 #define RCC_APB1ENR2_LPTIM2EN_Pos (5U)
<> 128:9bcdf88f62b0 11486 #define RCC_APB1ENR2_LPTIM2EN_Msk (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 11487 #define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk
<> 128:9bcdf88f62b0 11488
<> 128:9bcdf88f62b0 11489 /******************** Bit definition for RCC_APB2ENR register ***************/
<> 128:9bcdf88f62b0 11490 #define RCC_APB2ENR_SYSCFGEN_Pos (0U)
<> 128:9bcdf88f62b0 11491 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11492 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
<> 128:9bcdf88f62b0 11493 #define RCC_APB2ENR_FWEN_Pos (7U)
<> 128:9bcdf88f62b0 11494 #define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 11495 #define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk
<> 128:9bcdf88f62b0 11496 #define RCC_APB2ENR_SDMMC1EN_Pos (10U)
<> 128:9bcdf88f62b0 11497 #define RCC_APB2ENR_SDMMC1EN_Msk (0x1U << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 11498 #define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk
<> 128:9bcdf88f62b0 11499 #define RCC_APB2ENR_TIM1EN_Pos (11U)
<> 128:9bcdf88f62b0 11500 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 11501 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
<> 128:9bcdf88f62b0 11502 #define RCC_APB2ENR_SPI1EN_Pos (12U)
<> 128:9bcdf88f62b0 11503 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 11504 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
<> 128:9bcdf88f62b0 11505 #define RCC_APB2ENR_TIM8EN_Pos (13U)
<> 128:9bcdf88f62b0 11506 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 11507 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
<> 128:9bcdf88f62b0 11508 #define RCC_APB2ENR_USART1EN_Pos (14U)
<> 128:9bcdf88f62b0 11509 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 11510 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
<> 128:9bcdf88f62b0 11511 #define RCC_APB2ENR_TIM15EN_Pos (16U)
<> 128:9bcdf88f62b0 11512 #define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 11513 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
<> 128:9bcdf88f62b0 11514 #define RCC_APB2ENR_TIM16EN_Pos (17U)
<> 128:9bcdf88f62b0 11515 #define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 11516 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
<> 128:9bcdf88f62b0 11517 #define RCC_APB2ENR_TIM17EN_Pos (18U)
<> 128:9bcdf88f62b0 11518 #define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 11519 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
<> 128:9bcdf88f62b0 11520 #define RCC_APB2ENR_SAI1EN_Pos (21U)
<> 128:9bcdf88f62b0 11521 #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 11522 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
<> 128:9bcdf88f62b0 11523 #define RCC_APB2ENR_SAI2EN_Pos (22U)
<> 128:9bcdf88f62b0 11524 #define RCC_APB2ENR_SAI2EN_Msk (0x1U << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 11525 #define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
<> 128:9bcdf88f62b0 11526 #define RCC_APB2ENR_DFSDM1EN_Pos (24U)
<> 128:9bcdf88f62b0 11527 #define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 11528 #define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
<> 128:9bcdf88f62b0 11529
<> 128:9bcdf88f62b0 11530 /******************** Bit definition for RCC_AHB1SMENR register ***************/
<> 128:9bcdf88f62b0 11531 #define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
<> 128:9bcdf88f62b0 11532 #define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11533 #define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
<> 128:9bcdf88f62b0 11534 #define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
<> 128:9bcdf88f62b0 11535 #define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 11536 #define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
<> 128:9bcdf88f62b0 11537 #define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
<> 128:9bcdf88f62b0 11538 #define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 11539 #define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
<> 128:9bcdf88f62b0 11540 #define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
<> 128:9bcdf88f62b0 11541 #define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 11542 #define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
<> 128:9bcdf88f62b0 11543 #define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
<> 128:9bcdf88f62b0 11544 #define RCC_AHB1SMENR_CRCSMEN_Msk (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 11545 #define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
<> 128:9bcdf88f62b0 11546 #define RCC_AHB1SMENR_TSCSMEN_Pos (16U)
<> 128:9bcdf88f62b0 11547 #define RCC_AHB1SMENR_TSCSMEN_Msk (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 11548 #define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk
<> 128:9bcdf88f62b0 11549
<> 128:9bcdf88f62b0 11550 /******************** Bit definition for RCC_AHB2SMENR register *************/
<> 128:9bcdf88f62b0 11551 #define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
<> 128:9bcdf88f62b0 11552 #define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11553 #define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
<> 128:9bcdf88f62b0 11554 #define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
<> 128:9bcdf88f62b0 11555 #define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 11556 #define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
<> 128:9bcdf88f62b0 11557 #define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
<> 128:9bcdf88f62b0 11558 #define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 11559 #define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
<> 128:9bcdf88f62b0 11560 #define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
<> 128:9bcdf88f62b0 11561 #define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 11562 #define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
<> 128:9bcdf88f62b0 11563 #define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
<> 128:9bcdf88f62b0 11564 #define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 11565 #define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
<> 128:9bcdf88f62b0 11566 #define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)
<> 128:9bcdf88f62b0 11567 #define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 11568 #define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk
<> 128:9bcdf88f62b0 11569 #define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)
<> 128:9bcdf88f62b0 11570 #define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOGSMEN_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 11571 #define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk
<> 128:9bcdf88f62b0 11572 #define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U)
<> 128:9bcdf88f62b0 11573 #define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 11574 #define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk
<> 128:9bcdf88f62b0 11575 #define RCC_AHB2SMENR_SRAM2SMEN_Pos (9U)
<> 128:9bcdf88f62b0 11576 #define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 11577 #define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
<> 128:9bcdf88f62b0 11578 #define RCC_AHB2SMENR_OTGFSSMEN_Pos (12U)
<> 128:9bcdf88f62b0 11579 #define RCC_AHB2SMENR_OTGFSSMEN_Msk (0x1U << RCC_AHB2SMENR_OTGFSSMEN_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 11580 #define RCC_AHB2SMENR_OTGFSSMEN RCC_AHB2SMENR_OTGFSSMEN_Msk
<> 128:9bcdf88f62b0 11581 #define RCC_AHB2SMENR_ADCSMEN_Pos (13U)
<> 128:9bcdf88f62b0 11582 #define RCC_AHB2SMENR_ADCSMEN_Msk (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 11583 #define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk
<> 128:9bcdf88f62b0 11584 #define RCC_AHB2SMENR_AESSMEN_Pos (16U)
<> 128:9bcdf88f62b0 11585 #define RCC_AHB2SMENR_AESSMEN_Msk (0x1U << RCC_AHB2SMENR_AESSMEN_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 11586 #define RCC_AHB2SMENR_AESSMEN RCC_AHB2SMENR_AESSMEN_Msk
<> 128:9bcdf88f62b0 11587 #define RCC_AHB2SMENR_RNGSMEN_Pos (18U)
<> 128:9bcdf88f62b0 11588 #define RCC_AHB2SMENR_RNGSMEN_Msk (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 11589 #define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
<> 128:9bcdf88f62b0 11590
<> 128:9bcdf88f62b0 11591 /******************** Bit definition for RCC_AHB3SMENR register *************/
<> 128:9bcdf88f62b0 11592 #define RCC_AHB3SMENR_FMCSMEN_Pos (0U)
<> 128:9bcdf88f62b0 11593 #define RCC_AHB3SMENR_FMCSMEN_Msk (0x1U << RCC_AHB3SMENR_FMCSMEN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11594 #define RCC_AHB3SMENR_FMCSMEN RCC_AHB3SMENR_FMCSMEN_Msk
<> 128:9bcdf88f62b0 11595 #define RCC_AHB3SMENR_QSPISMEN_Pos (8U)
<> 128:9bcdf88f62b0 11596 #define RCC_AHB3SMENR_QSPISMEN_Msk (0x1U << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 11597 #define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk
<> 128:9bcdf88f62b0 11598
<> 128:9bcdf88f62b0 11599 /******************** Bit definition for RCC_APB1SMENR1 register *************/
<> 128:9bcdf88f62b0 11600 #define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
<> 128:9bcdf88f62b0 11601 #define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11602 #define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
<> 128:9bcdf88f62b0 11603 #define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
<> 128:9bcdf88f62b0 11604 #define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 11605 #define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
<> 128:9bcdf88f62b0 11606 #define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
<> 128:9bcdf88f62b0 11607 #define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM4SMEN_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 11608 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
<> 128:9bcdf88f62b0 11609 #define RCC_APB1SMENR1_TIM5SMEN_Pos (3U)
<> 128:9bcdf88f62b0 11610 #define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM5SMEN_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 11611 #define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk
<> 128:9bcdf88f62b0 11612 #define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
<> 128:9bcdf88f62b0 11613 #define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 11614 #define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
<> 128:9bcdf88f62b0 11615 #define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
<> 128:9bcdf88f62b0 11616 #define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 11617 #define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
<> 128:9bcdf88f62b0 11618 #define RCC_APB1SMENR1_LCDSMEN_Pos (9U)
<> 128:9bcdf88f62b0 11619 #define RCC_APB1SMENR1_LCDSMEN_Msk (0x1U << RCC_APB1SMENR1_LCDSMEN_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 11620 #define RCC_APB1SMENR1_LCDSMEN RCC_APB1SMENR1_LCDSMEN_Msk
<> 128:9bcdf88f62b0 11621 #define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
<> 128:9bcdf88f62b0 11622 #define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 11623 #define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
<> 128:9bcdf88f62b0 11624 #define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
<> 128:9bcdf88f62b0 11625 #define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 11626 #define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
<> 128:9bcdf88f62b0 11627 #define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
<> 128:9bcdf88f62b0 11628 #define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 11629 #define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
<> 128:9bcdf88f62b0 11630 #define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
<> 128:9bcdf88f62b0 11631 #define RCC_APB1SMENR1_USART2SMEN_Msk (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 11632 #define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
<> 128:9bcdf88f62b0 11633 #define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
<> 128:9bcdf88f62b0 11634 #define RCC_APB1SMENR1_USART3SMEN_Msk (0x1U << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 11635 #define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
<> 128:9bcdf88f62b0 11636 #define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
<> 128:9bcdf88f62b0 11637 #define RCC_APB1SMENR1_UART4SMEN_Msk (0x1U << RCC_APB1SMENR1_UART4SMEN_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 11638 #define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk
<> 128:9bcdf88f62b0 11639 #define RCC_APB1SMENR1_UART5SMEN_Pos (20U)
<> 128:9bcdf88f62b0 11640 #define RCC_APB1SMENR1_UART5SMEN_Msk (0x1U << RCC_APB1SMENR1_UART5SMEN_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 11641 #define RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk
<> 128:9bcdf88f62b0 11642 #define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
<> 128:9bcdf88f62b0 11643 #define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 11644 #define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
<> 128:9bcdf88f62b0 11645 #define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
<> 128:9bcdf88f62b0 11646 #define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 11647 #define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
<> 128:9bcdf88f62b0 11648 #define RCC_APB1SMENR1_I2C3SMEN_Pos (23U)
<> 128:9bcdf88f62b0 11649 #define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 11650 #define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
<> 128:9bcdf88f62b0 11651 #define RCC_APB1SMENR1_CAN1SMEN_Pos (25U)
<> 128:9bcdf88f62b0 11652 #define RCC_APB1SMENR1_CAN1SMEN_Msk (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 11653 #define RCC_APB1SMENR1_CAN1SMEN RCC_APB1SMENR1_CAN1SMEN_Msk
<> 128:9bcdf88f62b0 11654 #define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
<> 128:9bcdf88f62b0 11655 #define RCC_APB1SMENR1_PWRSMEN_Msk (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 11656 #define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
<> 128:9bcdf88f62b0 11657 #define RCC_APB1SMENR1_DAC1SMEN_Pos (29U)
<> 128:9bcdf88f62b0 11658 #define RCC_APB1SMENR1_DAC1SMEN_Msk (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 11659 #define RCC_APB1SMENR1_DAC1SMEN RCC_APB1SMENR1_DAC1SMEN_Msk
<> 128:9bcdf88f62b0 11660 #define RCC_APB1SMENR1_OPAMPSMEN_Pos (30U)
<> 128:9bcdf88f62b0 11661 #define RCC_APB1SMENR1_OPAMPSMEN_Msk (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 11662 #define RCC_APB1SMENR1_OPAMPSMEN RCC_APB1SMENR1_OPAMPSMEN_Msk
<> 128:9bcdf88f62b0 11663 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
<> 128:9bcdf88f62b0 11664 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 11665 #define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
<> 128:9bcdf88f62b0 11666
<> 128:9bcdf88f62b0 11667 /******************** Bit definition for RCC_APB1SMENR2 register *************/
<> 128:9bcdf88f62b0 11668 #define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
<> 128:9bcdf88f62b0 11669 #define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11670 #define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
<> 128:9bcdf88f62b0 11671 #define RCC_APB1SMENR2_SWPMI1SMEN_Pos (2U)
<> 128:9bcdf88f62b0 11672 #define RCC_APB1SMENR2_SWPMI1SMEN_Msk (0x1U << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 11673 #define RCC_APB1SMENR2_SWPMI1SMEN RCC_APB1SMENR2_SWPMI1SMEN_Msk
<> 128:9bcdf88f62b0 11674 #define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U)
<> 128:9bcdf88f62b0 11675 #define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 11676 #define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk
<> 128:9bcdf88f62b0 11677
<> 128:9bcdf88f62b0 11678 /******************** Bit definition for RCC_APB2SMENR register *************/
<> 128:9bcdf88f62b0 11679 #define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
<> 128:9bcdf88f62b0 11680 #define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11681 #define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
<> 128:9bcdf88f62b0 11682 #define RCC_APB2SMENR_SDMMC1SMEN_Pos (10U)
<> 128:9bcdf88f62b0 11683 #define RCC_APB2SMENR_SDMMC1SMEN_Msk (0x1U << RCC_APB2SMENR_SDMMC1SMEN_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 11684 #define RCC_APB2SMENR_SDMMC1SMEN RCC_APB2SMENR_SDMMC1SMEN_Msk
<> 128:9bcdf88f62b0 11685 #define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
<> 128:9bcdf88f62b0 11686 #define RCC_APB2SMENR_TIM1SMEN_Msk (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 11687 #define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
<> 128:9bcdf88f62b0 11688 #define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
<> 128:9bcdf88f62b0 11689 #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 11690 #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
<> 128:9bcdf88f62b0 11691 #define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
<> 128:9bcdf88f62b0 11692 #define RCC_APB2SMENR_TIM8SMEN_Msk (0x1U << RCC_APB2SMENR_TIM8SMEN_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 11693 #define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk
<> 128:9bcdf88f62b0 11694 #define RCC_APB2SMENR_USART1SMEN_Pos (14U)
<> 128:9bcdf88f62b0 11695 #define RCC_APB2SMENR_USART1SMEN_Msk (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 11696 #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
<> 128:9bcdf88f62b0 11697 #define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
<> 128:9bcdf88f62b0 11698 #define RCC_APB2SMENR_TIM15SMEN_Msk (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 11699 #define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
<> 128:9bcdf88f62b0 11700 #define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
<> 128:9bcdf88f62b0 11701 #define RCC_APB2SMENR_TIM16SMEN_Msk (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 11702 #define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
<> 128:9bcdf88f62b0 11703 #define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
<> 128:9bcdf88f62b0 11704 #define RCC_APB2SMENR_TIM17SMEN_Msk (0x1U << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 11705 #define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
<> 128:9bcdf88f62b0 11706 #define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
<> 128:9bcdf88f62b0 11707 #define RCC_APB2SMENR_SAI1SMEN_Msk (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 11708 #define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
<> 128:9bcdf88f62b0 11709 #define RCC_APB2SMENR_SAI2SMEN_Pos (22U)
<> 128:9bcdf88f62b0 11710 #define RCC_APB2SMENR_SAI2SMEN_Msk (0x1U << RCC_APB2SMENR_SAI2SMEN_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 11711 #define RCC_APB2SMENR_SAI2SMEN RCC_APB2SMENR_SAI2SMEN_Msk
<> 128:9bcdf88f62b0 11712 #define RCC_APB2SMENR_DFSDM1SMEN_Pos (24U)
<> 128:9bcdf88f62b0 11713 #define RCC_APB2SMENR_DFSDM1SMEN_Msk (0x1U << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 11714 #define RCC_APB2SMENR_DFSDM1SMEN RCC_APB2SMENR_DFSDM1SMEN_Msk
<> 128:9bcdf88f62b0 11715
<> 128:9bcdf88f62b0 11716 /******************** Bit definition for RCC_CCIPR register ******************/
<> 128:9bcdf88f62b0 11717 #define RCC_CCIPR_USART1SEL_Pos (0U)
<> 128:9bcdf88f62b0 11718 #define RCC_CCIPR_USART1SEL_Msk (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 11719 #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
<> 128:9bcdf88f62b0 11720 #define RCC_CCIPR_USART1SEL_0 (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11721 #define RCC_CCIPR_USART1SEL_1 (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 11722
<> 128:9bcdf88f62b0 11723 #define RCC_CCIPR_USART2SEL_Pos (2U)
<> 128:9bcdf88f62b0 11724 #define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
<> 128:9bcdf88f62b0 11725 #define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
<> 128:9bcdf88f62b0 11726 #define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 11727 #define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 11728
<> 128:9bcdf88f62b0 11729 #define RCC_CCIPR_USART3SEL_Pos (4U)
<> 128:9bcdf88f62b0 11730 #define RCC_CCIPR_USART3SEL_Msk (0x3U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000030 */
<> 128:9bcdf88f62b0 11731 #define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
<> 128:9bcdf88f62b0 11732 #define RCC_CCIPR_USART3SEL_0 (0x1U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 11733 #define RCC_CCIPR_USART3SEL_1 (0x2U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 11734
<> 128:9bcdf88f62b0 11735 #define RCC_CCIPR_UART4SEL_Pos (6U)
<> 128:9bcdf88f62b0 11736 #define RCC_CCIPR_UART4SEL_Msk (0x3U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
<> 128:9bcdf88f62b0 11737 #define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk
<> 128:9bcdf88f62b0 11738 #define RCC_CCIPR_UART4SEL_0 (0x1U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 11739 #define RCC_CCIPR_UART4SEL_1 (0x2U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 11740
<> 128:9bcdf88f62b0 11741 #define RCC_CCIPR_UART5SEL_Pos (8U)
<> 128:9bcdf88f62b0 11742 #define RCC_CCIPR_UART5SEL_Msk (0x3U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000300 */
<> 128:9bcdf88f62b0 11743 #define RCC_CCIPR_UART5SEL RCC_CCIPR_UART5SEL_Msk
<> 128:9bcdf88f62b0 11744 #define RCC_CCIPR_UART5SEL_0 (0x1U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 11745 #define RCC_CCIPR_UART5SEL_1 (0x2U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 11746
<> 128:9bcdf88f62b0 11747 #define RCC_CCIPR_LPUART1SEL_Pos (10U)
<> 128:9bcdf88f62b0 11748 #define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
<> 128:9bcdf88f62b0 11749 #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
<> 128:9bcdf88f62b0 11750 #define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 11751 #define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 11752
<> 128:9bcdf88f62b0 11753 #define RCC_CCIPR_I2C1SEL_Pos (12U)
<> 128:9bcdf88f62b0 11754 #define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
<> 128:9bcdf88f62b0 11755 #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
<> 128:9bcdf88f62b0 11756 #define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 11757 #define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 11758
<> 128:9bcdf88f62b0 11759 #define RCC_CCIPR_I2C2SEL_Pos (14U)
<> 128:9bcdf88f62b0 11760 #define RCC_CCIPR_I2C2SEL_Msk (0x3U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */
<> 128:9bcdf88f62b0 11761 #define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
<> 128:9bcdf88f62b0 11762 #define RCC_CCIPR_I2C2SEL_0 (0x1U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 11763 #define RCC_CCIPR_I2C2SEL_1 (0x2U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 11764
<> 128:9bcdf88f62b0 11765 #define RCC_CCIPR_I2C3SEL_Pos (16U)
<> 128:9bcdf88f62b0 11766 #define RCC_CCIPR_I2C3SEL_Msk (0x3U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
<> 128:9bcdf88f62b0 11767 #define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
<> 128:9bcdf88f62b0 11768 #define RCC_CCIPR_I2C3SEL_0 (0x1U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 11769 #define RCC_CCIPR_I2C3SEL_1 (0x2U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 11770
<> 128:9bcdf88f62b0 11771 #define RCC_CCIPR_LPTIM1SEL_Pos (18U)
<> 128:9bcdf88f62b0 11772 #define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
<> 128:9bcdf88f62b0 11773 #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
<> 128:9bcdf88f62b0 11774 #define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 11775 #define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 11776
<> 128:9bcdf88f62b0 11777 #define RCC_CCIPR_LPTIM2SEL_Pos (20U)
<> 128:9bcdf88f62b0 11778 #define RCC_CCIPR_LPTIM2SEL_Msk (0x3U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
<> 128:9bcdf88f62b0 11779 #define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk
<> 128:9bcdf88f62b0 11780 #define RCC_CCIPR_LPTIM2SEL_0 (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 11781 #define RCC_CCIPR_LPTIM2SEL_1 (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 11782
<> 128:9bcdf88f62b0 11783 #define RCC_CCIPR_SAI1SEL_Pos (22U)
<> 128:9bcdf88f62b0 11784 #define RCC_CCIPR_SAI1SEL_Msk (0x3U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00C00000 */
<> 128:9bcdf88f62b0 11785 #define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
<> 128:9bcdf88f62b0 11786 #define RCC_CCIPR_SAI1SEL_0 (0x1U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 11787 #define RCC_CCIPR_SAI1SEL_1 (0x2U << RCC_CCIPR_SAI1SEL_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 11788
<> 128:9bcdf88f62b0 11789 #define RCC_CCIPR_SAI2SEL_Pos (24U)
<> 128:9bcdf88f62b0 11790 #define RCC_CCIPR_SAI2SEL_Msk (0x3U << RCC_CCIPR_SAI2SEL_Pos) /*!< 0x03000000 */
<> 128:9bcdf88f62b0 11791 #define RCC_CCIPR_SAI2SEL RCC_CCIPR_SAI2SEL_Msk
<> 128:9bcdf88f62b0 11792 #define RCC_CCIPR_SAI2SEL_0 (0x1U << RCC_CCIPR_SAI2SEL_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 11793 #define RCC_CCIPR_SAI2SEL_1 (0x2U << RCC_CCIPR_SAI2SEL_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 11794
<> 128:9bcdf88f62b0 11795 #define RCC_CCIPR_CLK48SEL_Pos (26U)
<> 128:9bcdf88f62b0 11796 #define RCC_CCIPR_CLK48SEL_Msk (0x3U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
<> 128:9bcdf88f62b0 11797 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
<> 128:9bcdf88f62b0 11798 #define RCC_CCIPR_CLK48SEL_0 (0x1U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 11799 #define RCC_CCIPR_CLK48SEL_1 (0x2U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 11800
<> 128:9bcdf88f62b0 11801 #define RCC_CCIPR_ADCSEL_Pos (28U)
<> 128:9bcdf88f62b0 11802 #define RCC_CCIPR_ADCSEL_Msk (0x3U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x30000000 */
<> 128:9bcdf88f62b0 11803 #define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk
<> 128:9bcdf88f62b0 11804 #define RCC_CCIPR_ADCSEL_0 (0x1U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 11805 #define RCC_CCIPR_ADCSEL_1 (0x2U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 11806
<> 128:9bcdf88f62b0 11807 #define RCC_CCIPR_SWPMI1SEL_Pos (30U)
<> 128:9bcdf88f62b0 11808 #define RCC_CCIPR_SWPMI1SEL_Msk (0x1U << RCC_CCIPR_SWPMI1SEL_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 11809 #define RCC_CCIPR_SWPMI1SEL RCC_CCIPR_SWPMI1SEL_Msk
<> 128:9bcdf88f62b0 11810
<> 128:9bcdf88f62b0 11811 #define RCC_CCIPR_DFSDM1SEL_Pos (31U)
<> 128:9bcdf88f62b0 11812 #define RCC_CCIPR_DFSDM1SEL_Msk (0x1U << RCC_CCIPR_DFSDM1SEL_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 11813 #define RCC_CCIPR_DFSDM1SEL RCC_CCIPR_DFSDM1SEL_Msk
<> 128:9bcdf88f62b0 11814
<> 128:9bcdf88f62b0 11815 /******************** Bit definition for RCC_BDCR register ******************/
<> 128:9bcdf88f62b0 11816 #define RCC_BDCR_LSEON_Pos (0U)
<> 128:9bcdf88f62b0 11817 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11818 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
<> 128:9bcdf88f62b0 11819 #define RCC_BDCR_LSERDY_Pos (1U)
<> 128:9bcdf88f62b0 11820 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 11821 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
<> 128:9bcdf88f62b0 11822 #define RCC_BDCR_LSEBYP_Pos (2U)
<> 128:9bcdf88f62b0 11823 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 11824 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
<> 128:9bcdf88f62b0 11825
<> 128:9bcdf88f62b0 11826 #define RCC_BDCR_LSEDRV_Pos (3U)
<> 128:9bcdf88f62b0 11827 #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
<> 128:9bcdf88f62b0 11828 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
<> 128:9bcdf88f62b0 11829 #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 11830 #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 11831
<> 128:9bcdf88f62b0 11832 #define RCC_BDCR_LSECSSON_Pos (5U)
<> 128:9bcdf88f62b0 11833 #define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 11834 #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
<> 128:9bcdf88f62b0 11835 #define RCC_BDCR_LSECSSD_Pos (6U)
<> 128:9bcdf88f62b0 11836 #define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 11837 #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
<> 128:9bcdf88f62b0 11838
<> 128:9bcdf88f62b0 11839 #define RCC_BDCR_RTCSEL_Pos (8U)
<> 128:9bcdf88f62b0 11840 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
<> 128:9bcdf88f62b0 11841 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
<> 128:9bcdf88f62b0 11842 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 11843 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 11844
<> 128:9bcdf88f62b0 11845 #define RCC_BDCR_RTCEN_Pos (15U)
<> 128:9bcdf88f62b0 11846 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 11847 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
<> 128:9bcdf88f62b0 11848 #define RCC_BDCR_BDRST_Pos (16U)
<> 128:9bcdf88f62b0 11849 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 11850 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
<> 128:9bcdf88f62b0 11851 #define RCC_BDCR_LSCOEN_Pos (24U)
<> 128:9bcdf88f62b0 11852 #define RCC_BDCR_LSCOEN_Msk (0x1U << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 11853 #define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
<> 128:9bcdf88f62b0 11854 #define RCC_BDCR_LSCOSEL_Pos (25U)
<> 128:9bcdf88f62b0 11855 #define RCC_BDCR_LSCOSEL_Msk (0x1U << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 11856 #define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
<> 128:9bcdf88f62b0 11857
<> 128:9bcdf88f62b0 11858 /******************** Bit definition for RCC_CSR register *******************/
<> 128:9bcdf88f62b0 11859 #define RCC_CSR_LSION_Pos (0U)
<> 128:9bcdf88f62b0 11860 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11861 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
<> 128:9bcdf88f62b0 11862 #define RCC_CSR_LSIRDY_Pos (1U)
<> 128:9bcdf88f62b0 11863 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 11864 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
<> 128:9bcdf88f62b0 11865
<> 128:9bcdf88f62b0 11866 #define RCC_CSR_MSISRANGE_Pos (8U)
<> 128:9bcdf88f62b0 11867 #define RCC_CSR_MSISRANGE_Msk (0xFU << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000F00 */
<> 128:9bcdf88f62b0 11868 #define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk
<> 128:9bcdf88f62b0 11869 #define RCC_CSR_MSISRANGE_1 (0x4U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 11870 #define RCC_CSR_MSISRANGE_2 (0x5U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000500 */
<> 128:9bcdf88f62b0 11871 #define RCC_CSR_MSISRANGE_4 (0x6U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000600 */
<> 128:9bcdf88f62b0 11872 #define RCC_CSR_MSISRANGE_8 (0x7U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000700 */
<> 128:9bcdf88f62b0 11873
<> 128:9bcdf88f62b0 11874 #define RCC_CSR_RMVF_Pos (23U)
<> 128:9bcdf88f62b0 11875 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 11876 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
<> 128:9bcdf88f62b0 11877 #define RCC_CSR_FWRSTF_Pos (24U)
<> 128:9bcdf88f62b0 11878 #define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 11879 #define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk
<> 128:9bcdf88f62b0 11880 #define RCC_CSR_OBLRSTF_Pos (25U)
<> 128:9bcdf88f62b0 11881 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 11882 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
<> 128:9bcdf88f62b0 11883 #define RCC_CSR_PINRSTF_Pos (26U)
<> 128:9bcdf88f62b0 11884 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 11885 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
<> 128:9bcdf88f62b0 11886 #define RCC_CSR_BORRSTF_Pos (27U)
<> 128:9bcdf88f62b0 11887 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 11888 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
<> 128:9bcdf88f62b0 11889 #define RCC_CSR_SFTRSTF_Pos (28U)
<> 128:9bcdf88f62b0 11890 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 11891 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
<> 128:9bcdf88f62b0 11892 #define RCC_CSR_IWDGRSTF_Pos (29U)
<> 128:9bcdf88f62b0 11893 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 11894 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
<> 128:9bcdf88f62b0 11895 #define RCC_CSR_WWDGRSTF_Pos (30U)
<> 128:9bcdf88f62b0 11896 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 11897 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
<> 128:9bcdf88f62b0 11898 #define RCC_CSR_LPWRRSTF_Pos (31U)
<> 128:9bcdf88f62b0 11899 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 11900 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
<> 128:9bcdf88f62b0 11901
<> 128:9bcdf88f62b0 11902 /******************************************************************************/
<> 128:9bcdf88f62b0 11903 /* */
<> 128:9bcdf88f62b0 11904 /* RNG */
<> 128:9bcdf88f62b0 11905 /* */
<> 128:9bcdf88f62b0 11906 /******************************************************************************/
<> 128:9bcdf88f62b0 11907 /******************** Bits definition for RNG_CR register *******************/
<> 128:9bcdf88f62b0 11908 #define RNG_CR_RNGEN_Pos (2U)
<> 128:9bcdf88f62b0 11909 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 11910 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
<> 128:9bcdf88f62b0 11911 #define RNG_CR_IE_Pos (3U)
<> 128:9bcdf88f62b0 11912 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 11913 #define RNG_CR_IE RNG_CR_IE_Msk
<> 128:9bcdf88f62b0 11914
<> 128:9bcdf88f62b0 11915 /******************** Bits definition for RNG_SR register *******************/
<> 128:9bcdf88f62b0 11916 #define RNG_SR_DRDY_Pos (0U)
<> 128:9bcdf88f62b0 11917 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11918 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
<> 128:9bcdf88f62b0 11919 #define RNG_SR_CECS_Pos (1U)
<> 128:9bcdf88f62b0 11920 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 11921 #define RNG_SR_CECS RNG_SR_CECS_Msk
<> 128:9bcdf88f62b0 11922 #define RNG_SR_SECS_Pos (2U)
<> 128:9bcdf88f62b0 11923 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 11924 #define RNG_SR_SECS RNG_SR_SECS_Msk
<> 128:9bcdf88f62b0 11925 #define RNG_SR_CEIS_Pos (5U)
<> 128:9bcdf88f62b0 11926 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 11927 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
<> 128:9bcdf88f62b0 11928 #define RNG_SR_SEIS_Pos (6U)
<> 128:9bcdf88f62b0 11929 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 11930 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
<> 128:9bcdf88f62b0 11931
<> 128:9bcdf88f62b0 11932 /******************************************************************************/
<> 128:9bcdf88f62b0 11933 /* */
<> 128:9bcdf88f62b0 11934 /* Real-Time Clock (RTC) */
<> 128:9bcdf88f62b0 11935 /* */
<> 128:9bcdf88f62b0 11936 /******************************************************************************/
<> 128:9bcdf88f62b0 11937 /*
<> 128:9bcdf88f62b0 11938 * @brief Specific device feature definitions
<> 128:9bcdf88f62b0 11939 */
<> 128:9bcdf88f62b0 11940 #define RTC_TAMPER1_SUPPORT
<> 128:9bcdf88f62b0 11941 #define RTC_TAMPER2_SUPPORT
<> 128:9bcdf88f62b0 11942 #define RTC_TAMPER3_SUPPORT
<> 128:9bcdf88f62b0 11943 #define RTC_WAKEUP_SUPPORT
<> 128:9bcdf88f62b0 11944 #define RTC_BACKUP_SUPPORT
<> 128:9bcdf88f62b0 11945
<> 128:9bcdf88f62b0 11946 /******************** Bits definition for RTC_TR register *******************/
<> 128:9bcdf88f62b0 11947 #define RTC_TR_PM_Pos (22U)
<> 128:9bcdf88f62b0 11948 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 11949 #define RTC_TR_PM RTC_TR_PM_Msk
<> 128:9bcdf88f62b0 11950 #define RTC_TR_HT_Pos (20U)
<> 128:9bcdf88f62b0 11951 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
<> 128:9bcdf88f62b0 11952 #define RTC_TR_HT RTC_TR_HT_Msk
<> 128:9bcdf88f62b0 11953 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 11954 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 11955 #define RTC_TR_HU_Pos (16U)
<> 128:9bcdf88f62b0 11956 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
<> 128:9bcdf88f62b0 11957 #define RTC_TR_HU RTC_TR_HU_Msk
<> 128:9bcdf88f62b0 11958 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 11959 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 11960 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 11961 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 11962 #define RTC_TR_MNT_Pos (12U)
<> 128:9bcdf88f62b0 11963 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
<> 128:9bcdf88f62b0 11964 #define RTC_TR_MNT RTC_TR_MNT_Msk
<> 128:9bcdf88f62b0 11965 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 11966 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 11967 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 11968 #define RTC_TR_MNU_Pos (8U)
<> 128:9bcdf88f62b0 11969 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
<> 128:9bcdf88f62b0 11970 #define RTC_TR_MNU RTC_TR_MNU_Msk
<> 128:9bcdf88f62b0 11971 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 11972 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 11973 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 11974 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 11975 #define RTC_TR_ST_Pos (4U)
<> 128:9bcdf88f62b0 11976 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
<> 128:9bcdf88f62b0 11977 #define RTC_TR_ST RTC_TR_ST_Msk
<> 128:9bcdf88f62b0 11978 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 11979 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 11980 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 11981 #define RTC_TR_SU_Pos (0U)
<> 128:9bcdf88f62b0 11982 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 11983 #define RTC_TR_SU RTC_TR_SU_Msk
<> 128:9bcdf88f62b0 11984 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 11985 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 11986 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 11987 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 11988
<> 128:9bcdf88f62b0 11989 /******************** Bits definition for RTC_DR register *******************/
<> 128:9bcdf88f62b0 11990 #define RTC_DR_YT_Pos (20U)
<> 128:9bcdf88f62b0 11991 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
<> 128:9bcdf88f62b0 11992 #define RTC_DR_YT RTC_DR_YT_Msk
<> 128:9bcdf88f62b0 11993 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 11994 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 11995 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 11996 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 11997 #define RTC_DR_YU_Pos (16U)
<> 128:9bcdf88f62b0 11998 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
<> 128:9bcdf88f62b0 11999 #define RTC_DR_YU RTC_DR_YU_Msk
<> 128:9bcdf88f62b0 12000 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 12001 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 12002 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 12003 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 12004 #define RTC_DR_WDU_Pos (13U)
<> 128:9bcdf88f62b0 12005 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
<> 128:9bcdf88f62b0 12006 #define RTC_DR_WDU RTC_DR_WDU_Msk
<> 128:9bcdf88f62b0 12007 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 12008 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 12009 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 12010 #define RTC_DR_MT_Pos (12U)
<> 128:9bcdf88f62b0 12011 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 12012 #define RTC_DR_MT RTC_DR_MT_Msk
<> 128:9bcdf88f62b0 12013 #define RTC_DR_MU_Pos (8U)
<> 128:9bcdf88f62b0 12014 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
<> 128:9bcdf88f62b0 12015 #define RTC_DR_MU RTC_DR_MU_Msk
<> 128:9bcdf88f62b0 12016 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 12017 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 12018 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 12019 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 12020 #define RTC_DR_DT_Pos (4U)
<> 128:9bcdf88f62b0 12021 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
<> 128:9bcdf88f62b0 12022 #define RTC_DR_DT RTC_DR_DT_Msk
<> 128:9bcdf88f62b0 12023 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 12024 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 12025 #define RTC_DR_DU_Pos (0U)
<> 128:9bcdf88f62b0 12026 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 12027 #define RTC_DR_DU RTC_DR_DU_Msk
<> 128:9bcdf88f62b0 12028 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 12029 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 12030 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 12031 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 12032
<> 128:9bcdf88f62b0 12033 /******************** Bits definition for RTC_CR register *******************/
<> 128:9bcdf88f62b0 12034 #define RTC_CR_ITSE_Pos (24U)
<> 128:9bcdf88f62b0 12035 #define RTC_CR_ITSE_Msk (0x1U << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 12036 #define RTC_CR_ITSE RTC_CR_ITSE_Msk
<> 128:9bcdf88f62b0 12037 #define RTC_CR_COE_Pos (23U)
<> 128:9bcdf88f62b0 12038 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 12039 #define RTC_CR_COE RTC_CR_COE_Msk
<> 128:9bcdf88f62b0 12040 #define RTC_CR_OSEL_Pos (21U)
<> 128:9bcdf88f62b0 12041 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
<> 128:9bcdf88f62b0 12042 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
<> 128:9bcdf88f62b0 12043 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 12044 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 12045 #define RTC_CR_POL_Pos (20U)
<> 128:9bcdf88f62b0 12046 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 12047 #define RTC_CR_POL RTC_CR_POL_Msk
<> 128:9bcdf88f62b0 12048 #define RTC_CR_COSEL_Pos (19U)
<> 128:9bcdf88f62b0 12049 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 12050 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
<> 128:9bcdf88f62b0 12051 #define RTC_CR_BCK_Pos (18U)
<> 128:9bcdf88f62b0 12052 #define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 12053 #define RTC_CR_BCK RTC_CR_BCK_Msk
<> 128:9bcdf88f62b0 12054 #define RTC_CR_SUB1H_Pos (17U)
<> 128:9bcdf88f62b0 12055 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 12056 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
<> 128:9bcdf88f62b0 12057 #define RTC_CR_ADD1H_Pos (16U)
<> 128:9bcdf88f62b0 12058 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 12059 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
<> 128:9bcdf88f62b0 12060 #define RTC_CR_TSIE_Pos (15U)
<> 128:9bcdf88f62b0 12061 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 12062 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
<> 128:9bcdf88f62b0 12063 #define RTC_CR_WUTIE_Pos (14U)
<> 128:9bcdf88f62b0 12064 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 12065 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
<> 128:9bcdf88f62b0 12066 #define RTC_CR_ALRBIE_Pos (13U)
<> 128:9bcdf88f62b0 12067 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 12068 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
<> 128:9bcdf88f62b0 12069 #define RTC_CR_ALRAIE_Pos (12U)
<> 128:9bcdf88f62b0 12070 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 12071 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
<> 128:9bcdf88f62b0 12072 #define RTC_CR_TSE_Pos (11U)
<> 128:9bcdf88f62b0 12073 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 12074 #define RTC_CR_TSE RTC_CR_TSE_Msk
<> 128:9bcdf88f62b0 12075 #define RTC_CR_WUTE_Pos (10U)
<> 128:9bcdf88f62b0 12076 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 12077 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
<> 128:9bcdf88f62b0 12078 #define RTC_CR_ALRBE_Pos (9U)
<> 128:9bcdf88f62b0 12079 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 12080 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
<> 128:9bcdf88f62b0 12081 #define RTC_CR_ALRAE_Pos (8U)
<> 128:9bcdf88f62b0 12082 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 12083 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
<> 128:9bcdf88f62b0 12084 #define RTC_CR_FMT_Pos (6U)
<> 128:9bcdf88f62b0 12085 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 12086 #define RTC_CR_FMT RTC_CR_FMT_Msk
<> 128:9bcdf88f62b0 12087 #define RTC_CR_BYPSHAD_Pos (5U)
<> 128:9bcdf88f62b0 12088 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 12089 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
<> 128:9bcdf88f62b0 12090 #define RTC_CR_REFCKON_Pos (4U)
<> 128:9bcdf88f62b0 12091 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 12092 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
<> 128:9bcdf88f62b0 12093 #define RTC_CR_TSEDGE_Pos (3U)
<> 128:9bcdf88f62b0 12094 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 12095 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
<> 128:9bcdf88f62b0 12096 #define RTC_CR_WUCKSEL_Pos (0U)
<> 128:9bcdf88f62b0 12097 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
<> 128:9bcdf88f62b0 12098 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
<> 128:9bcdf88f62b0 12099 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 12100 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 12101 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 12102
<> 128:9bcdf88f62b0 12103 /******************** Bits definition for RTC_ISR register ******************/
<> 128:9bcdf88f62b0 12104 #define RTC_ISR_ITSF_Pos (17U)
<> 128:9bcdf88f62b0 12105 #define RTC_ISR_ITSF_Msk (0x1U << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 12106 #define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
<> 128:9bcdf88f62b0 12107 #define RTC_ISR_RECALPF_Pos (16U)
<> 128:9bcdf88f62b0 12108 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 12109 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
<> 128:9bcdf88f62b0 12110 #define RTC_ISR_TAMP3F_Pos (15U)
<> 128:9bcdf88f62b0 12111 #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 12112 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
<> 128:9bcdf88f62b0 12113 #define RTC_ISR_TAMP2F_Pos (14U)
<> 128:9bcdf88f62b0 12114 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 12115 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
<> 128:9bcdf88f62b0 12116 #define RTC_ISR_TAMP1F_Pos (13U)
<> 128:9bcdf88f62b0 12117 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 12118 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
<> 128:9bcdf88f62b0 12119 #define RTC_ISR_TSOVF_Pos (12U)
<> 128:9bcdf88f62b0 12120 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 12121 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
<> 128:9bcdf88f62b0 12122 #define RTC_ISR_TSF_Pos (11U)
<> 128:9bcdf88f62b0 12123 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 12124 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
<> 128:9bcdf88f62b0 12125 #define RTC_ISR_WUTF_Pos (10U)
<> 128:9bcdf88f62b0 12126 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 12127 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
<> 128:9bcdf88f62b0 12128 #define RTC_ISR_ALRBF_Pos (9U)
<> 128:9bcdf88f62b0 12129 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 12130 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
<> 128:9bcdf88f62b0 12131 #define RTC_ISR_ALRAF_Pos (8U)
<> 128:9bcdf88f62b0 12132 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 12133 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
<> 128:9bcdf88f62b0 12134 #define RTC_ISR_INIT_Pos (7U)
<> 128:9bcdf88f62b0 12135 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 12136 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
<> 128:9bcdf88f62b0 12137 #define RTC_ISR_INITF_Pos (6U)
<> 128:9bcdf88f62b0 12138 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 12139 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
<> 128:9bcdf88f62b0 12140 #define RTC_ISR_RSF_Pos (5U)
<> 128:9bcdf88f62b0 12141 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 12142 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
<> 128:9bcdf88f62b0 12143 #define RTC_ISR_INITS_Pos (4U)
<> 128:9bcdf88f62b0 12144 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 12145 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
<> 128:9bcdf88f62b0 12146 #define RTC_ISR_SHPF_Pos (3U)
<> 128:9bcdf88f62b0 12147 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 12148 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
<> 128:9bcdf88f62b0 12149 #define RTC_ISR_WUTWF_Pos (2U)
<> 128:9bcdf88f62b0 12150 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 12151 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
<> 128:9bcdf88f62b0 12152 #define RTC_ISR_ALRBWF_Pos (1U)
<> 128:9bcdf88f62b0 12153 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 12154 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
<> 128:9bcdf88f62b0 12155 #define RTC_ISR_ALRAWF_Pos (0U)
<> 128:9bcdf88f62b0 12156 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 12157 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
<> 128:9bcdf88f62b0 12158
<> 128:9bcdf88f62b0 12159 /******************** Bits definition for RTC_PRER register *****************/
<> 128:9bcdf88f62b0 12160 #define RTC_PRER_PREDIV_A_Pos (16U)
<> 128:9bcdf88f62b0 12161 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
<> 128:9bcdf88f62b0 12162 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
<> 128:9bcdf88f62b0 12163 #define RTC_PRER_PREDIV_S_Pos (0U)
<> 128:9bcdf88f62b0 12164 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
<> 128:9bcdf88f62b0 12165 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
<> 128:9bcdf88f62b0 12166
<> 128:9bcdf88f62b0 12167 /******************** Bits definition for RTC_WUTR register *****************/
<> 128:9bcdf88f62b0 12168 #define RTC_WUTR_WUT_Pos (0U)
<> 128:9bcdf88f62b0 12169 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 12170 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
<> 128:9bcdf88f62b0 12171
<> 128:9bcdf88f62b0 12172 /******************** Bits definition for RTC_ALRMAR register ***************/
<> 128:9bcdf88f62b0 12173 #define RTC_ALRMAR_MSK4_Pos (31U)
<> 128:9bcdf88f62b0 12174 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 12175 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
<> 128:9bcdf88f62b0 12176 #define RTC_ALRMAR_WDSEL_Pos (30U)
<> 128:9bcdf88f62b0 12177 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 12178 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
<> 128:9bcdf88f62b0 12179 #define RTC_ALRMAR_DT_Pos (28U)
<> 128:9bcdf88f62b0 12180 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
<> 128:9bcdf88f62b0 12181 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
<> 128:9bcdf88f62b0 12182 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 12183 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 12184 #define RTC_ALRMAR_DU_Pos (24U)
<> 128:9bcdf88f62b0 12185 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
<> 128:9bcdf88f62b0 12186 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
<> 128:9bcdf88f62b0 12187 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 12188 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 12189 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 12190 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 12191 #define RTC_ALRMAR_MSK3_Pos (23U)
<> 128:9bcdf88f62b0 12192 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 12193 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
<> 128:9bcdf88f62b0 12194 #define RTC_ALRMAR_PM_Pos (22U)
<> 128:9bcdf88f62b0 12195 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 12196 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
<> 128:9bcdf88f62b0 12197 #define RTC_ALRMAR_HT_Pos (20U)
<> 128:9bcdf88f62b0 12198 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
<> 128:9bcdf88f62b0 12199 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
<> 128:9bcdf88f62b0 12200 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 12201 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 12202 #define RTC_ALRMAR_HU_Pos (16U)
<> 128:9bcdf88f62b0 12203 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
<> 128:9bcdf88f62b0 12204 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
<> 128:9bcdf88f62b0 12205 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 12206 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 12207 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 12208 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 12209 #define RTC_ALRMAR_MSK2_Pos (15U)
<> 128:9bcdf88f62b0 12210 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 12211 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
<> 128:9bcdf88f62b0 12212 #define RTC_ALRMAR_MNT_Pos (12U)
<> 128:9bcdf88f62b0 12213 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
<> 128:9bcdf88f62b0 12214 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
<> 128:9bcdf88f62b0 12215 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 12216 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 12217 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 12218 #define RTC_ALRMAR_MNU_Pos (8U)
<> 128:9bcdf88f62b0 12219 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
<> 128:9bcdf88f62b0 12220 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
<> 128:9bcdf88f62b0 12221 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 12222 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 12223 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 12224 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 12225 #define RTC_ALRMAR_MSK1_Pos (7U)
<> 128:9bcdf88f62b0 12226 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 12227 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
<> 128:9bcdf88f62b0 12228 #define RTC_ALRMAR_ST_Pos (4U)
<> 128:9bcdf88f62b0 12229 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
<> 128:9bcdf88f62b0 12230 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
<> 128:9bcdf88f62b0 12231 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 12232 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 12233 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 12234 #define RTC_ALRMAR_SU_Pos (0U)
<> 128:9bcdf88f62b0 12235 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 12236 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
<> 128:9bcdf88f62b0 12237 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 12238 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 12239 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 12240 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 12241
<> 128:9bcdf88f62b0 12242 /******************** Bits definition for RTC_ALRMBR register ***************/
<> 128:9bcdf88f62b0 12243 #define RTC_ALRMBR_MSK4_Pos (31U)
<> 128:9bcdf88f62b0 12244 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 12245 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
<> 128:9bcdf88f62b0 12246 #define RTC_ALRMBR_WDSEL_Pos (30U)
<> 128:9bcdf88f62b0 12247 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 12248 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
<> 128:9bcdf88f62b0 12249 #define RTC_ALRMBR_DT_Pos (28U)
<> 128:9bcdf88f62b0 12250 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
<> 128:9bcdf88f62b0 12251 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
<> 128:9bcdf88f62b0 12252 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 12253 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 12254 #define RTC_ALRMBR_DU_Pos (24U)
<> 128:9bcdf88f62b0 12255 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
<> 128:9bcdf88f62b0 12256 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
<> 128:9bcdf88f62b0 12257 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 12258 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 12259 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 12260 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 12261 #define RTC_ALRMBR_MSK3_Pos (23U)
<> 128:9bcdf88f62b0 12262 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 12263 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
<> 128:9bcdf88f62b0 12264 #define RTC_ALRMBR_PM_Pos (22U)
<> 128:9bcdf88f62b0 12265 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 12266 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
<> 128:9bcdf88f62b0 12267 #define RTC_ALRMBR_HT_Pos (20U)
<> 128:9bcdf88f62b0 12268 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
<> 128:9bcdf88f62b0 12269 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
<> 128:9bcdf88f62b0 12270 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 12271 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 12272 #define RTC_ALRMBR_HU_Pos (16U)
<> 128:9bcdf88f62b0 12273 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
<> 128:9bcdf88f62b0 12274 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
<> 128:9bcdf88f62b0 12275 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 12276 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 12277 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 12278 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 12279 #define RTC_ALRMBR_MSK2_Pos (15U)
<> 128:9bcdf88f62b0 12280 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 12281 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
<> 128:9bcdf88f62b0 12282 #define RTC_ALRMBR_MNT_Pos (12U)
<> 128:9bcdf88f62b0 12283 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
<> 128:9bcdf88f62b0 12284 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
<> 128:9bcdf88f62b0 12285 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 12286 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 12287 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 12288 #define RTC_ALRMBR_MNU_Pos (8U)
<> 128:9bcdf88f62b0 12289 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
<> 128:9bcdf88f62b0 12290 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
<> 128:9bcdf88f62b0 12291 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 12292 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 12293 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 12294 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 12295 #define RTC_ALRMBR_MSK1_Pos (7U)
<> 128:9bcdf88f62b0 12296 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 12297 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
<> 128:9bcdf88f62b0 12298 #define RTC_ALRMBR_ST_Pos (4U)
<> 128:9bcdf88f62b0 12299 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
<> 128:9bcdf88f62b0 12300 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
<> 128:9bcdf88f62b0 12301 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 12302 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 12303 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 12304 #define RTC_ALRMBR_SU_Pos (0U)
<> 128:9bcdf88f62b0 12305 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 12306 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
<> 128:9bcdf88f62b0 12307 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 12308 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 12309 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 12310 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 12311
<> 128:9bcdf88f62b0 12312 /******************** Bits definition for RTC_WPR register ******************/
<> 128:9bcdf88f62b0 12313 #define RTC_WPR_KEY_Pos (0U)
<> 128:9bcdf88f62b0 12314 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 12315 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
<> 128:9bcdf88f62b0 12316
<> 128:9bcdf88f62b0 12317 /******************** Bits definition for RTC_SSR register ******************/
<> 128:9bcdf88f62b0 12318 #define RTC_SSR_SS_Pos (0U)
<> 128:9bcdf88f62b0 12319 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 12320 #define RTC_SSR_SS RTC_SSR_SS_Msk
<> 128:9bcdf88f62b0 12321
<> 128:9bcdf88f62b0 12322 /******************** Bits definition for RTC_SHIFTR register ***************/
<> 128:9bcdf88f62b0 12323 #define RTC_SHIFTR_SUBFS_Pos (0U)
<> 128:9bcdf88f62b0 12324 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
<> 128:9bcdf88f62b0 12325 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
<> 128:9bcdf88f62b0 12326 #define RTC_SHIFTR_ADD1S_Pos (31U)
<> 128:9bcdf88f62b0 12327 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 12328 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
<> 128:9bcdf88f62b0 12329
<> 128:9bcdf88f62b0 12330 /******************** Bits definition for RTC_TSTR register *****************/
<> 128:9bcdf88f62b0 12331 #define RTC_TSTR_PM_Pos (22U)
<> 128:9bcdf88f62b0 12332 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 12333 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
<> 128:9bcdf88f62b0 12334 #define RTC_TSTR_HT_Pos (20U)
<> 128:9bcdf88f62b0 12335 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
<> 128:9bcdf88f62b0 12336 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
<> 128:9bcdf88f62b0 12337 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 12338 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 12339 #define RTC_TSTR_HU_Pos (16U)
<> 128:9bcdf88f62b0 12340 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
<> 128:9bcdf88f62b0 12341 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
<> 128:9bcdf88f62b0 12342 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 12343 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 12344 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 12345 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 12346 #define RTC_TSTR_MNT_Pos (12U)
<> 128:9bcdf88f62b0 12347 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
<> 128:9bcdf88f62b0 12348 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
<> 128:9bcdf88f62b0 12349 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 12350 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 12351 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 12352 #define RTC_TSTR_MNU_Pos (8U)
<> 128:9bcdf88f62b0 12353 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
<> 128:9bcdf88f62b0 12354 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
<> 128:9bcdf88f62b0 12355 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 12356 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 12357 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 12358 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 12359 #define RTC_TSTR_ST_Pos (4U)
<> 128:9bcdf88f62b0 12360 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
<> 128:9bcdf88f62b0 12361 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
<> 128:9bcdf88f62b0 12362 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 12363 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 12364 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 12365 #define RTC_TSTR_SU_Pos (0U)
<> 128:9bcdf88f62b0 12366 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 12367 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
<> 128:9bcdf88f62b0 12368 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 12369 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 12370 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 12371 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 12372
<> 128:9bcdf88f62b0 12373 /******************** Bits definition for RTC_TSDR register *****************/
<> 128:9bcdf88f62b0 12374 #define RTC_TSDR_WDU_Pos (13U)
<> 128:9bcdf88f62b0 12375 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
<> 128:9bcdf88f62b0 12376 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
<> 128:9bcdf88f62b0 12377 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 12378 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 12379 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 12380 #define RTC_TSDR_MT_Pos (12U)
<> 128:9bcdf88f62b0 12381 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 12382 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
<> 128:9bcdf88f62b0 12383 #define RTC_TSDR_MU_Pos (8U)
<> 128:9bcdf88f62b0 12384 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
<> 128:9bcdf88f62b0 12385 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
<> 128:9bcdf88f62b0 12386 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 12387 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 12388 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 12389 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 12390 #define RTC_TSDR_DT_Pos (4U)
<> 128:9bcdf88f62b0 12391 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
<> 128:9bcdf88f62b0 12392 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
<> 128:9bcdf88f62b0 12393 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 12394 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 12395 #define RTC_TSDR_DU_Pos (0U)
<> 128:9bcdf88f62b0 12396 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 12397 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
<> 128:9bcdf88f62b0 12398 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 12399 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 12400 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 12401 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 12402
<> 128:9bcdf88f62b0 12403 /******************** Bits definition for RTC_TSSSR register ****************/
<> 128:9bcdf88f62b0 12404 #define RTC_TSSSR_SS_Pos (0U)
<> 128:9bcdf88f62b0 12405 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 12406 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
<> 128:9bcdf88f62b0 12407
<> 128:9bcdf88f62b0 12408 /******************** Bits definition for RTC_CAL register *****************/
<> 128:9bcdf88f62b0 12409 #define RTC_CALR_CALP_Pos (15U)
<> 128:9bcdf88f62b0 12410 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 12411 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
<> 128:9bcdf88f62b0 12412 #define RTC_CALR_CALW8_Pos (14U)
<> 128:9bcdf88f62b0 12413 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 12414 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
<> 128:9bcdf88f62b0 12415 #define RTC_CALR_CALW16_Pos (13U)
<> 128:9bcdf88f62b0 12416 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 12417 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
<> 128:9bcdf88f62b0 12418 #define RTC_CALR_CALM_Pos (0U)
<> 128:9bcdf88f62b0 12419 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
<> 128:9bcdf88f62b0 12420 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
<> 128:9bcdf88f62b0 12421 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 12422 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 12423 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 12424 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 12425 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 12426 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 12427 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 12428 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 12429 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 12430
<> 128:9bcdf88f62b0 12431 /******************** Bits definition for RTC_TAMPCR register ***************/
<> 128:9bcdf88f62b0 12432 #define RTC_TAMPCR_TAMP3MF_Pos (24U)
<> 128:9bcdf88f62b0 12433 #define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 12434 #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
<> 128:9bcdf88f62b0 12435 #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
<> 128:9bcdf88f62b0 12436 #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 12437 #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
<> 128:9bcdf88f62b0 12438 #define RTC_TAMPCR_TAMP3IE_Pos (22U)
<> 128:9bcdf88f62b0 12439 #define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 12440 #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
<> 128:9bcdf88f62b0 12441 #define RTC_TAMPCR_TAMP2MF_Pos (21U)
<> 128:9bcdf88f62b0 12442 #define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 12443 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
<> 128:9bcdf88f62b0 12444 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
<> 128:9bcdf88f62b0 12445 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 12446 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
<> 128:9bcdf88f62b0 12447 #define RTC_TAMPCR_TAMP2IE_Pos (19U)
<> 128:9bcdf88f62b0 12448 #define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 12449 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
<> 128:9bcdf88f62b0 12450 #define RTC_TAMPCR_TAMP1MF_Pos (18U)
<> 128:9bcdf88f62b0 12451 #define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 12452 #define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
<> 128:9bcdf88f62b0 12453 #define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
<> 128:9bcdf88f62b0 12454 #define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 12455 #define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
<> 128:9bcdf88f62b0 12456 #define RTC_TAMPCR_TAMP1IE_Pos (16U)
<> 128:9bcdf88f62b0 12457 #define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 12458 #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
<> 128:9bcdf88f62b0 12459 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
<> 128:9bcdf88f62b0 12460 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 12461 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
<> 128:9bcdf88f62b0 12462 #define RTC_TAMPCR_TAMPPRCH_Pos (13U)
<> 128:9bcdf88f62b0 12463 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
<> 128:9bcdf88f62b0 12464 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
<> 128:9bcdf88f62b0 12465 #define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 12466 #define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 12467 #define RTC_TAMPCR_TAMPFLT_Pos (11U)
<> 128:9bcdf88f62b0 12468 #define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
<> 128:9bcdf88f62b0 12469 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
<> 128:9bcdf88f62b0 12470 #define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 12471 #define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 12472 #define RTC_TAMPCR_TAMPFREQ_Pos (8U)
<> 128:9bcdf88f62b0 12473 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
<> 128:9bcdf88f62b0 12474 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
<> 128:9bcdf88f62b0 12475 #define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 12476 #define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 12477 #define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 12478 #define RTC_TAMPCR_TAMPTS_Pos (7U)
<> 128:9bcdf88f62b0 12479 #define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 12480 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
<> 128:9bcdf88f62b0 12481 #define RTC_TAMPCR_TAMP3TRG_Pos (6U)
<> 128:9bcdf88f62b0 12482 #define RTC_TAMPCR_TAMP3TRG_Msk (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 12483 #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
<> 128:9bcdf88f62b0 12484 #define RTC_TAMPCR_TAMP3E_Pos (5U)
<> 128:9bcdf88f62b0 12485 #define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 12486 #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
<> 128:9bcdf88f62b0 12487 #define RTC_TAMPCR_TAMP2TRG_Pos (4U)
<> 128:9bcdf88f62b0 12488 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 12489 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
<> 128:9bcdf88f62b0 12490 #define RTC_TAMPCR_TAMP2E_Pos (3U)
<> 128:9bcdf88f62b0 12491 #define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 12492 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
<> 128:9bcdf88f62b0 12493 #define RTC_TAMPCR_TAMPIE_Pos (2U)
<> 128:9bcdf88f62b0 12494 #define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 12495 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
<> 128:9bcdf88f62b0 12496 #define RTC_TAMPCR_TAMP1TRG_Pos (1U)
<> 128:9bcdf88f62b0 12497 #define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 12498 #define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
<> 128:9bcdf88f62b0 12499 #define RTC_TAMPCR_TAMP1E_Pos (0U)
<> 128:9bcdf88f62b0 12500 #define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 12501 #define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
<> 128:9bcdf88f62b0 12502
<> 128:9bcdf88f62b0 12503 /******************** Bits definition for RTC_ALRMASSR register *************/
<> 128:9bcdf88f62b0 12504 #define RTC_ALRMASSR_MASKSS_Pos (24U)
<> 128:9bcdf88f62b0 12505 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
<> 128:9bcdf88f62b0 12506 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
<> 128:9bcdf88f62b0 12507 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 12508 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 12509 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 12510 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 12511 #define RTC_ALRMASSR_SS_Pos (0U)
<> 128:9bcdf88f62b0 12512 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
<> 128:9bcdf88f62b0 12513 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
<> 128:9bcdf88f62b0 12514
<> 128:9bcdf88f62b0 12515 /******************** Bits definition for RTC_ALRMBSSR register *************/
<> 128:9bcdf88f62b0 12516 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
<> 128:9bcdf88f62b0 12517 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
<> 128:9bcdf88f62b0 12518 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
<> 128:9bcdf88f62b0 12519 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 12520 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 12521 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 12522 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 12523 #define RTC_ALRMBSSR_SS_Pos (0U)
<> 128:9bcdf88f62b0 12524 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
<> 128:9bcdf88f62b0 12525 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
<> 128:9bcdf88f62b0 12526
<> 128:9bcdf88f62b0 12527 /******************** Bits definition for RTC_0R register *******************/
<> 128:9bcdf88f62b0 12528 #define RTC_OR_OUT_RMP_Pos (1U)
<> 128:9bcdf88f62b0 12529 #define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 12530 #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
<> 128:9bcdf88f62b0 12531 #define RTC_OR_ALARMOUTTYPE_Pos (0U)
<> 128:9bcdf88f62b0 12532 #define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 12533 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
<> 128:9bcdf88f62b0 12534
<> 128:9bcdf88f62b0 12535
<> 128:9bcdf88f62b0 12536 /******************** Bits definition for RTC_BKP0R register ****************/
<> 128:9bcdf88f62b0 12537 #define RTC_BKP0R_Pos (0U)
<> 128:9bcdf88f62b0 12538 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12539 #define RTC_BKP0R RTC_BKP0R_Msk
<> 128:9bcdf88f62b0 12540
<> 128:9bcdf88f62b0 12541 /******************** Bits definition for RTC_BKP1R register ****************/
<> 128:9bcdf88f62b0 12542 #define RTC_BKP1R_Pos (0U)
<> 128:9bcdf88f62b0 12543 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12544 #define RTC_BKP1R RTC_BKP1R_Msk
<> 128:9bcdf88f62b0 12545
<> 128:9bcdf88f62b0 12546 /******************** Bits definition for RTC_BKP2R register ****************/
<> 128:9bcdf88f62b0 12547 #define RTC_BKP2R_Pos (0U)
<> 128:9bcdf88f62b0 12548 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12549 #define RTC_BKP2R RTC_BKP2R_Msk
<> 128:9bcdf88f62b0 12550
<> 128:9bcdf88f62b0 12551 /******************** Bits definition for RTC_BKP3R register ****************/
<> 128:9bcdf88f62b0 12552 #define RTC_BKP3R_Pos (0U)
<> 128:9bcdf88f62b0 12553 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12554 #define RTC_BKP3R RTC_BKP3R_Msk
<> 128:9bcdf88f62b0 12555
<> 128:9bcdf88f62b0 12556 /******************** Bits definition for RTC_BKP4R register ****************/
<> 128:9bcdf88f62b0 12557 #define RTC_BKP4R_Pos (0U)
<> 128:9bcdf88f62b0 12558 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12559 #define RTC_BKP4R RTC_BKP4R_Msk
<> 128:9bcdf88f62b0 12560
<> 128:9bcdf88f62b0 12561 /******************** Bits definition for RTC_BKP5R register ****************/
<> 128:9bcdf88f62b0 12562 #define RTC_BKP5R_Pos (0U)
<> 128:9bcdf88f62b0 12563 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12564 #define RTC_BKP5R RTC_BKP5R_Msk
<> 128:9bcdf88f62b0 12565
<> 128:9bcdf88f62b0 12566 /******************** Bits definition for RTC_BKP6R register ****************/
<> 128:9bcdf88f62b0 12567 #define RTC_BKP6R_Pos (0U)
<> 128:9bcdf88f62b0 12568 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12569 #define RTC_BKP6R RTC_BKP6R_Msk
<> 128:9bcdf88f62b0 12570
<> 128:9bcdf88f62b0 12571 /******************** Bits definition for RTC_BKP7R register ****************/
<> 128:9bcdf88f62b0 12572 #define RTC_BKP7R_Pos (0U)
<> 128:9bcdf88f62b0 12573 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12574 #define RTC_BKP7R RTC_BKP7R_Msk
<> 128:9bcdf88f62b0 12575
<> 128:9bcdf88f62b0 12576 /******************** Bits definition for RTC_BKP8R register ****************/
<> 128:9bcdf88f62b0 12577 #define RTC_BKP8R_Pos (0U)
<> 128:9bcdf88f62b0 12578 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12579 #define RTC_BKP8R RTC_BKP8R_Msk
<> 128:9bcdf88f62b0 12580
<> 128:9bcdf88f62b0 12581 /******************** Bits definition for RTC_BKP9R register ****************/
<> 128:9bcdf88f62b0 12582 #define RTC_BKP9R_Pos (0U)
<> 128:9bcdf88f62b0 12583 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12584 #define RTC_BKP9R RTC_BKP9R_Msk
<> 128:9bcdf88f62b0 12585
<> 128:9bcdf88f62b0 12586 /******************** Bits definition for RTC_BKP10R register ***************/
<> 128:9bcdf88f62b0 12587 #define RTC_BKP10R_Pos (0U)
<> 128:9bcdf88f62b0 12588 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12589 #define RTC_BKP10R RTC_BKP10R_Msk
<> 128:9bcdf88f62b0 12590
<> 128:9bcdf88f62b0 12591 /******************** Bits definition for RTC_BKP11R register ***************/
<> 128:9bcdf88f62b0 12592 #define RTC_BKP11R_Pos (0U)
<> 128:9bcdf88f62b0 12593 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12594 #define RTC_BKP11R RTC_BKP11R_Msk
<> 128:9bcdf88f62b0 12595
<> 128:9bcdf88f62b0 12596 /******************** Bits definition for RTC_BKP12R register ***************/
<> 128:9bcdf88f62b0 12597 #define RTC_BKP12R_Pos (0U)
<> 128:9bcdf88f62b0 12598 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12599 #define RTC_BKP12R RTC_BKP12R_Msk
<> 128:9bcdf88f62b0 12600
<> 128:9bcdf88f62b0 12601 /******************** Bits definition for RTC_BKP13R register ***************/
<> 128:9bcdf88f62b0 12602 #define RTC_BKP13R_Pos (0U)
<> 128:9bcdf88f62b0 12603 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12604 #define RTC_BKP13R RTC_BKP13R_Msk
<> 128:9bcdf88f62b0 12605
<> 128:9bcdf88f62b0 12606 /******************** Bits definition for RTC_BKP14R register ***************/
<> 128:9bcdf88f62b0 12607 #define RTC_BKP14R_Pos (0U)
<> 128:9bcdf88f62b0 12608 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12609 #define RTC_BKP14R RTC_BKP14R_Msk
<> 128:9bcdf88f62b0 12610
<> 128:9bcdf88f62b0 12611 /******************** Bits definition for RTC_BKP15R register ***************/
<> 128:9bcdf88f62b0 12612 #define RTC_BKP15R_Pos (0U)
<> 128:9bcdf88f62b0 12613 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12614 #define RTC_BKP15R RTC_BKP15R_Msk
<> 128:9bcdf88f62b0 12615
<> 128:9bcdf88f62b0 12616 /******************** Bits definition for RTC_BKP16R register ***************/
<> 128:9bcdf88f62b0 12617 #define RTC_BKP16R_Pos (0U)
<> 128:9bcdf88f62b0 12618 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12619 #define RTC_BKP16R RTC_BKP16R_Msk
<> 128:9bcdf88f62b0 12620
<> 128:9bcdf88f62b0 12621 /******************** Bits definition for RTC_BKP17R register ***************/
<> 128:9bcdf88f62b0 12622 #define RTC_BKP17R_Pos (0U)
<> 128:9bcdf88f62b0 12623 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12624 #define RTC_BKP17R RTC_BKP17R_Msk
<> 128:9bcdf88f62b0 12625
<> 128:9bcdf88f62b0 12626 /******************** Bits definition for RTC_BKP18R register ***************/
<> 128:9bcdf88f62b0 12627 #define RTC_BKP18R_Pos (0U)
<> 128:9bcdf88f62b0 12628 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12629 #define RTC_BKP18R RTC_BKP18R_Msk
<> 128:9bcdf88f62b0 12630
<> 128:9bcdf88f62b0 12631 /******************** Bits definition for RTC_BKP19R register ***************/
<> 128:9bcdf88f62b0 12632 #define RTC_BKP19R_Pos (0U)
<> 128:9bcdf88f62b0 12633 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12634 #define RTC_BKP19R RTC_BKP19R_Msk
<> 128:9bcdf88f62b0 12635
<> 128:9bcdf88f62b0 12636 /******************** Bits definition for RTC_BKP20R register ***************/
<> 128:9bcdf88f62b0 12637 #define RTC_BKP20R_Pos (0U)
<> 128:9bcdf88f62b0 12638 #define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12639 #define RTC_BKP20R RTC_BKP20R_Msk
<> 128:9bcdf88f62b0 12640
<> 128:9bcdf88f62b0 12641 /******************** Bits definition for RTC_BKP21R register ***************/
<> 128:9bcdf88f62b0 12642 #define RTC_BKP21R_Pos (0U)
<> 128:9bcdf88f62b0 12643 #define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12644 #define RTC_BKP21R RTC_BKP21R_Msk
<> 128:9bcdf88f62b0 12645
<> 128:9bcdf88f62b0 12646 /******************** Bits definition for RTC_BKP22R register ***************/
<> 128:9bcdf88f62b0 12647 #define RTC_BKP22R_Pos (0U)
<> 128:9bcdf88f62b0 12648 #define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12649 #define RTC_BKP22R RTC_BKP22R_Msk
<> 128:9bcdf88f62b0 12650
<> 128:9bcdf88f62b0 12651 /******************** Bits definition for RTC_BKP23R register ***************/
<> 128:9bcdf88f62b0 12652 #define RTC_BKP23R_Pos (0U)
<> 128:9bcdf88f62b0 12653 #define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12654 #define RTC_BKP23R RTC_BKP23R_Msk
<> 128:9bcdf88f62b0 12655
<> 128:9bcdf88f62b0 12656 /******************** Bits definition for RTC_BKP24R register ***************/
<> 128:9bcdf88f62b0 12657 #define RTC_BKP24R_Pos (0U)
<> 128:9bcdf88f62b0 12658 #define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12659 #define RTC_BKP24R RTC_BKP24R_Msk
<> 128:9bcdf88f62b0 12660
<> 128:9bcdf88f62b0 12661 /******************** Bits definition for RTC_BKP25R register ***************/
<> 128:9bcdf88f62b0 12662 #define RTC_BKP25R_Pos (0U)
<> 128:9bcdf88f62b0 12663 #define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12664 #define RTC_BKP25R RTC_BKP25R_Msk
<> 128:9bcdf88f62b0 12665
<> 128:9bcdf88f62b0 12666 /******************** Bits definition for RTC_BKP26R register ***************/
<> 128:9bcdf88f62b0 12667 #define RTC_BKP26R_Pos (0U)
<> 128:9bcdf88f62b0 12668 #define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12669 #define RTC_BKP26R RTC_BKP26R_Msk
<> 128:9bcdf88f62b0 12670
<> 128:9bcdf88f62b0 12671 /******************** Bits definition for RTC_BKP27R register ***************/
<> 128:9bcdf88f62b0 12672 #define RTC_BKP27R_Pos (0U)
<> 128:9bcdf88f62b0 12673 #define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12674 #define RTC_BKP27R RTC_BKP27R_Msk
<> 128:9bcdf88f62b0 12675
<> 128:9bcdf88f62b0 12676 /******************** Bits definition for RTC_BKP28R register ***************/
<> 128:9bcdf88f62b0 12677 #define RTC_BKP28R_Pos (0U)
<> 128:9bcdf88f62b0 12678 #define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12679 #define RTC_BKP28R RTC_BKP28R_Msk
<> 128:9bcdf88f62b0 12680
<> 128:9bcdf88f62b0 12681 /******************** Bits definition for RTC_BKP29R register ***************/
<> 128:9bcdf88f62b0 12682 #define RTC_BKP29R_Pos (0U)
<> 128:9bcdf88f62b0 12683 #define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12684 #define RTC_BKP29R RTC_BKP29R_Msk
<> 128:9bcdf88f62b0 12685
<> 128:9bcdf88f62b0 12686 /******************** Bits definition for RTC_BKP30R register ***************/
<> 128:9bcdf88f62b0 12687 #define RTC_BKP30R_Pos (0U)
<> 128:9bcdf88f62b0 12688 #define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12689 #define RTC_BKP30R RTC_BKP30R_Msk
<> 128:9bcdf88f62b0 12690
<> 128:9bcdf88f62b0 12691 /******************** Bits definition for RTC_BKP31R register ***************/
<> 128:9bcdf88f62b0 12692 #define RTC_BKP31R_Pos (0U)
<> 128:9bcdf88f62b0 12693 #define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12694 #define RTC_BKP31R RTC_BKP31R_Msk
<> 128:9bcdf88f62b0 12695
<> 128:9bcdf88f62b0 12696 /******************** Number of backup registers ******************************/
<> 128:9bcdf88f62b0 12697 #define RTC_BKP_NUMBER 32U
<> 128:9bcdf88f62b0 12698
<> 128:9bcdf88f62b0 12699 /******************************************************************************/
<> 128:9bcdf88f62b0 12700 /* */
<> 128:9bcdf88f62b0 12701 /* Serial Audio Interface */
<> 128:9bcdf88f62b0 12702 /* */
<> 128:9bcdf88f62b0 12703 /******************************************************************************/
<> 128:9bcdf88f62b0 12704 /******************** Bit definition for SAI_GCR register *******************/
<> 128:9bcdf88f62b0 12705 #define SAI_GCR_SYNCIN_Pos (0U)
<> 128:9bcdf88f62b0 12706 #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 12707 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
<> 128:9bcdf88f62b0 12708 #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 12709 #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 12710
<> 128:9bcdf88f62b0 12711 #define SAI_GCR_SYNCOUT_Pos (4U)
<> 128:9bcdf88f62b0 12712 #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
<> 128:9bcdf88f62b0 12713 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
<> 128:9bcdf88f62b0 12714 #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 12715 #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 12716
<> 128:9bcdf88f62b0 12717 /******************* Bit definition for SAI_xCR1 register *******************/
<> 128:9bcdf88f62b0 12718 #define SAI_xCR1_MODE_Pos (0U)
<> 128:9bcdf88f62b0 12719 #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 12720 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
<> 128:9bcdf88f62b0 12721 #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 12722 #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 12723
<> 128:9bcdf88f62b0 12724 #define SAI_xCR1_PRTCFG_Pos (2U)
<> 128:9bcdf88f62b0 12725 #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
<> 128:9bcdf88f62b0 12726 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
<> 128:9bcdf88f62b0 12727 #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 12728 #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 12729
<> 128:9bcdf88f62b0 12730 #define SAI_xCR1_DS_Pos (5U)
<> 128:9bcdf88f62b0 12731 #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
<> 128:9bcdf88f62b0 12732 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
<> 128:9bcdf88f62b0 12733 #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 12734 #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 12735 #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 12736
<> 128:9bcdf88f62b0 12737 #define SAI_xCR1_LSBFIRST_Pos (8U)
<> 128:9bcdf88f62b0 12738 #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 12739 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
<> 128:9bcdf88f62b0 12740 #define SAI_xCR1_CKSTR_Pos (9U)
<> 128:9bcdf88f62b0 12741 #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 12742 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
<> 128:9bcdf88f62b0 12743
<> 128:9bcdf88f62b0 12744 #define SAI_xCR1_SYNCEN_Pos (10U)
<> 128:9bcdf88f62b0 12745 #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
<> 128:9bcdf88f62b0 12746 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
<> 128:9bcdf88f62b0 12747 #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 12748 #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 12749
<> 128:9bcdf88f62b0 12750 #define SAI_xCR1_MONO_Pos (12U)
<> 128:9bcdf88f62b0 12751 #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 12752 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
<> 128:9bcdf88f62b0 12753 #define SAI_xCR1_OUTDRIV_Pos (13U)
<> 128:9bcdf88f62b0 12754 #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 12755 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
<> 128:9bcdf88f62b0 12756 #define SAI_xCR1_SAIEN_Pos (16U)
<> 128:9bcdf88f62b0 12757 #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 12758 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
<> 128:9bcdf88f62b0 12759 #define SAI_xCR1_DMAEN_Pos (17U)
<> 128:9bcdf88f62b0 12760 #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 12761 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
<> 128:9bcdf88f62b0 12762 #define SAI_xCR1_NODIV_Pos (19U)
<> 128:9bcdf88f62b0 12763 #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 12764 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
<> 128:9bcdf88f62b0 12765
<> 128:9bcdf88f62b0 12766 #define SAI_xCR1_MCKDIV_Pos (20U)
<> 128:9bcdf88f62b0 12767 #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
<> 128:9bcdf88f62b0 12768 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
<> 128:9bcdf88f62b0 12769 #define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */
<> 128:9bcdf88f62b0 12770 #define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */
<> 128:9bcdf88f62b0 12771 #define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */
<> 128:9bcdf88f62b0 12772 #define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */
<> 128:9bcdf88f62b0 12773
<> 128:9bcdf88f62b0 12774 /******************* Bit definition for SAI_xCR2 register *******************/
<> 128:9bcdf88f62b0 12775 #define SAI_xCR2_FTH_Pos (0U)
<> 128:9bcdf88f62b0 12776 #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
<> 128:9bcdf88f62b0 12777 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
<> 128:9bcdf88f62b0 12778 #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 12779 #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 12780 #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 12781
<> 128:9bcdf88f62b0 12782 #define SAI_xCR2_FFLUSH_Pos (3U)
<> 128:9bcdf88f62b0 12783 #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 12784 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
<> 128:9bcdf88f62b0 12785 #define SAI_xCR2_TRIS_Pos (4U)
<> 128:9bcdf88f62b0 12786 #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 12787 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
<> 128:9bcdf88f62b0 12788 #define SAI_xCR2_MUTE_Pos (5U)
<> 128:9bcdf88f62b0 12789 #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 12790 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
<> 128:9bcdf88f62b0 12791 #define SAI_xCR2_MUTEVAL_Pos (6U)
<> 128:9bcdf88f62b0 12792 #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 12793 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
<> 128:9bcdf88f62b0 12794
<> 128:9bcdf88f62b0 12795
<> 128:9bcdf88f62b0 12796 #define SAI_xCR2_MUTECNT_Pos (7U)
<> 128:9bcdf88f62b0 12797 #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
<> 128:9bcdf88f62b0 12798 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
<> 128:9bcdf88f62b0 12799 #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 12800 #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 12801 #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 12802 #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 12803 #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 12804 #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 12805
<> 128:9bcdf88f62b0 12806 #define SAI_xCR2_CPL_Pos (13U)
<> 128:9bcdf88f62b0 12807 #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 12808 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
<> 128:9bcdf88f62b0 12809 #define SAI_xCR2_COMP_Pos (14U)
<> 128:9bcdf88f62b0 12810 #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
<> 128:9bcdf88f62b0 12811 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
<> 128:9bcdf88f62b0 12812 #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 12813 #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 12814
<> 128:9bcdf88f62b0 12815
<> 128:9bcdf88f62b0 12816 /****************** Bit definition for SAI_xFRCR register *******************/
<> 128:9bcdf88f62b0 12817 #define SAI_xFRCR_FRL_Pos (0U)
<> 128:9bcdf88f62b0 12818 #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 12819 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
<> 128:9bcdf88f62b0 12820 #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 12821 #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 12822 #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 12823 #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 12824 #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 12825 #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 12826 #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 12827 #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 12828
<> 128:9bcdf88f62b0 12829 #define SAI_xFRCR_FSALL_Pos (8U)
<> 128:9bcdf88f62b0 12830 #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
<> 128:9bcdf88f62b0 12831 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
<> 128:9bcdf88f62b0 12832 #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 12833 #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 12834 #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 12835 #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 12836 #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 12837 #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 12838 #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 12839
<> 128:9bcdf88f62b0 12840 #define SAI_xFRCR_FSDEF_Pos (16U)
<> 128:9bcdf88f62b0 12841 #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 12842 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
<> 128:9bcdf88f62b0 12843 #define SAI_xFRCR_FSPOL_Pos (17U)
<> 128:9bcdf88f62b0 12844 #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 12845 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
<> 128:9bcdf88f62b0 12846 #define SAI_xFRCR_FSOFF_Pos (18U)
<> 128:9bcdf88f62b0 12847 #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 12848 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
<> 128:9bcdf88f62b0 12849
<> 128:9bcdf88f62b0 12850 /****************** Bit definition for SAI_xSLOTR register *******************/
<> 128:9bcdf88f62b0 12851 #define SAI_xSLOTR_FBOFF_Pos (0U)
<> 128:9bcdf88f62b0 12852 #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
<> 128:9bcdf88f62b0 12853 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
<> 128:9bcdf88f62b0 12854 #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 12855 #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 12856 #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 12857 #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 12858 #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 12859
<> 128:9bcdf88f62b0 12860 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
<> 128:9bcdf88f62b0 12861 #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
<> 128:9bcdf88f62b0 12862 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
<> 128:9bcdf88f62b0 12863 #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 12864 #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 12865
<> 128:9bcdf88f62b0 12866 #define SAI_xSLOTR_NBSLOT_Pos (8U)
<> 128:9bcdf88f62b0 12867 #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
<> 128:9bcdf88f62b0 12868 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
<> 128:9bcdf88f62b0 12869 #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 12870 #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 12871 #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 12872 #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 12873
<> 128:9bcdf88f62b0 12874 #define SAI_xSLOTR_SLOTEN_Pos (16U)
<> 128:9bcdf88f62b0 12875 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
<> 128:9bcdf88f62b0 12876 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
<> 128:9bcdf88f62b0 12877
<> 128:9bcdf88f62b0 12878 /******************* Bit definition for SAI_xIMR register *******************/
<> 128:9bcdf88f62b0 12879 #define SAI_xIMR_OVRUDRIE_Pos (0U)
<> 128:9bcdf88f62b0 12880 #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 12881 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
<> 128:9bcdf88f62b0 12882 #define SAI_xIMR_MUTEDETIE_Pos (1U)
<> 128:9bcdf88f62b0 12883 #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 12884 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
<> 128:9bcdf88f62b0 12885 #define SAI_xIMR_WCKCFGIE_Pos (2U)
<> 128:9bcdf88f62b0 12886 #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 12887 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
<> 128:9bcdf88f62b0 12888 #define SAI_xIMR_FREQIE_Pos (3U)
<> 128:9bcdf88f62b0 12889 #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 12890 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
<> 128:9bcdf88f62b0 12891 #define SAI_xIMR_CNRDYIE_Pos (4U)
<> 128:9bcdf88f62b0 12892 #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 12893 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
<> 128:9bcdf88f62b0 12894 #define SAI_xIMR_AFSDETIE_Pos (5U)
<> 128:9bcdf88f62b0 12895 #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 12896 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
<> 128:9bcdf88f62b0 12897 #define SAI_xIMR_LFSDETIE_Pos (6U)
<> 128:9bcdf88f62b0 12898 #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 12899 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
<> 128:9bcdf88f62b0 12900
<> 128:9bcdf88f62b0 12901 /******************** Bit definition for SAI_xSR register *******************/
<> 128:9bcdf88f62b0 12902 #define SAI_xSR_OVRUDR_Pos (0U)
<> 128:9bcdf88f62b0 12903 #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 12904 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
<> 128:9bcdf88f62b0 12905 #define SAI_xSR_MUTEDET_Pos (1U)
<> 128:9bcdf88f62b0 12906 #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 12907 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
<> 128:9bcdf88f62b0 12908 #define SAI_xSR_WCKCFG_Pos (2U)
<> 128:9bcdf88f62b0 12909 #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 12910 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
<> 128:9bcdf88f62b0 12911 #define SAI_xSR_FREQ_Pos (3U)
<> 128:9bcdf88f62b0 12912 #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 12913 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
<> 128:9bcdf88f62b0 12914 #define SAI_xSR_CNRDY_Pos (4U)
<> 128:9bcdf88f62b0 12915 #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 12916 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
<> 128:9bcdf88f62b0 12917 #define SAI_xSR_AFSDET_Pos (5U)
<> 128:9bcdf88f62b0 12918 #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 12919 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
<> 128:9bcdf88f62b0 12920 #define SAI_xSR_LFSDET_Pos (6U)
<> 128:9bcdf88f62b0 12921 #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 12922 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
<> 128:9bcdf88f62b0 12923
<> 128:9bcdf88f62b0 12924 #define SAI_xSR_FLVL_Pos (16U)
<> 128:9bcdf88f62b0 12925 #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
<> 128:9bcdf88f62b0 12926 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
<> 128:9bcdf88f62b0 12927 #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 12928 #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 12929 #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 12930
<> 128:9bcdf88f62b0 12931 /****************** Bit definition for SAI_xCLRFR register ******************/
<> 128:9bcdf88f62b0 12932 #define SAI_xCLRFR_COVRUDR_Pos (0U)
<> 128:9bcdf88f62b0 12933 #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 12934 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
<> 128:9bcdf88f62b0 12935 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
<> 128:9bcdf88f62b0 12936 #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 12937 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
<> 128:9bcdf88f62b0 12938 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
<> 128:9bcdf88f62b0 12939 #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 12940 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
<> 128:9bcdf88f62b0 12941 #define SAI_xCLRFR_CFREQ_Pos (3U)
<> 128:9bcdf88f62b0 12942 #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 12943 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
<> 128:9bcdf88f62b0 12944 #define SAI_xCLRFR_CCNRDY_Pos (4U)
<> 128:9bcdf88f62b0 12945 #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 12946 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
<> 128:9bcdf88f62b0 12947 #define SAI_xCLRFR_CAFSDET_Pos (5U)
<> 128:9bcdf88f62b0 12948 #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 12949 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
<> 128:9bcdf88f62b0 12950 #define SAI_xCLRFR_CLFSDET_Pos (6U)
<> 128:9bcdf88f62b0 12951 #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 12952 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
<> 128:9bcdf88f62b0 12953
<> 128:9bcdf88f62b0 12954 /****************** Bit definition for SAI_xDR register ******************/
<> 128:9bcdf88f62b0 12955 #define SAI_xDR_DATA_Pos (0U)
<> 128:9bcdf88f62b0 12956 #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 12957 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
<> 128:9bcdf88f62b0 12958
<> 128:9bcdf88f62b0 12959 /******************************************************************************/
<> 128:9bcdf88f62b0 12960 /* */
<> 128:9bcdf88f62b0 12961 /* LCD Controller (LCD) */
<> 128:9bcdf88f62b0 12962 /* */
<> 128:9bcdf88f62b0 12963 /******************************************************************************/
<> 128:9bcdf88f62b0 12964
<> 128:9bcdf88f62b0 12965 /******************* Bit definition for LCD_CR register *********************/
<> 128:9bcdf88f62b0 12966 #define LCD_CR_LCDEN_Pos (0U)
<> 128:9bcdf88f62b0 12967 #define LCD_CR_LCDEN_Msk (0x1U << LCD_CR_LCDEN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 12968 #define LCD_CR_LCDEN LCD_CR_LCDEN_Msk /*!< LCD Enable Bit */
<> 128:9bcdf88f62b0 12969 #define LCD_CR_VSEL_Pos (1U)
<> 128:9bcdf88f62b0 12970 #define LCD_CR_VSEL_Msk (0x1U << LCD_CR_VSEL_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 12971 #define LCD_CR_VSEL LCD_CR_VSEL_Msk /*!< Voltage source selector Bit */
<> 128:9bcdf88f62b0 12972
<> 128:9bcdf88f62b0 12973 #define LCD_CR_DUTY_Pos (2U)
<> 128:9bcdf88f62b0 12974 #define LCD_CR_DUTY_Msk (0x7U << LCD_CR_DUTY_Pos) /*!< 0x0000001C */
<> 128:9bcdf88f62b0 12975 #define LCD_CR_DUTY LCD_CR_DUTY_Msk /*!< DUTY[2:0] bits (Duty selector) */
<> 128:9bcdf88f62b0 12976 #define LCD_CR_DUTY_0 (0x1U << LCD_CR_DUTY_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 12977 #define LCD_CR_DUTY_1 (0x2U << LCD_CR_DUTY_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 12978 #define LCD_CR_DUTY_2 (0x4U << LCD_CR_DUTY_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 12979
<> 128:9bcdf88f62b0 12980 #define LCD_CR_BIAS_Pos (5U)
<> 128:9bcdf88f62b0 12981 #define LCD_CR_BIAS_Msk (0x3U << LCD_CR_BIAS_Pos) /*!< 0x00000060 */
<> 128:9bcdf88f62b0 12982 #define LCD_CR_BIAS LCD_CR_BIAS_Msk /*!< BIAS[1:0] bits (Bias selector) */
<> 128:9bcdf88f62b0 12983 #define LCD_CR_BIAS_0 (0x1U << LCD_CR_BIAS_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 12984 #define LCD_CR_BIAS_1 (0x2U << LCD_CR_BIAS_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 12985
<> 128:9bcdf88f62b0 12986 #define LCD_CR_MUX_SEG_Pos (7U)
<> 128:9bcdf88f62b0 12987 #define LCD_CR_MUX_SEG_Msk (0x1U << LCD_CR_MUX_SEG_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 12988 #define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk /*!< Mux Segment Enable Bit */
<> 128:9bcdf88f62b0 12989 #define LCD_CR_BUFEN_Pos (8U)
<> 128:9bcdf88f62b0 12990 #define LCD_CR_BUFEN_Msk (0x1U << LCD_CR_BUFEN_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 12991 #define LCD_CR_BUFEN LCD_CR_BUFEN_Msk /*!< Voltage output buffer enable */
<> 128:9bcdf88f62b0 12992
<> 128:9bcdf88f62b0 12993 /******************* Bit definition for LCD_FCR register ********************/
<> 128:9bcdf88f62b0 12994 #define LCD_FCR_HD_Pos (0U)
<> 128:9bcdf88f62b0 12995 #define LCD_FCR_HD_Msk (0x1U << LCD_FCR_HD_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 12996 #define LCD_FCR_HD LCD_FCR_HD_Msk /*!< High Drive Enable Bit */
<> 128:9bcdf88f62b0 12997 #define LCD_FCR_SOFIE_Pos (1U)
<> 128:9bcdf88f62b0 12998 #define LCD_FCR_SOFIE_Msk (0x1U << LCD_FCR_SOFIE_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 12999 #define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk /*!< Start of Frame Interrupt Enable Bit */
<> 128:9bcdf88f62b0 13000 #define LCD_FCR_UDDIE_Pos (3U)
<> 128:9bcdf88f62b0 13001 #define LCD_FCR_UDDIE_Msk (0x1U << LCD_FCR_UDDIE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 13002 #define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk /*!< Update Display Done Interrupt Enable Bit */
<> 128:9bcdf88f62b0 13003
<> 128:9bcdf88f62b0 13004 #define LCD_FCR_PON_Pos (4U)
<> 128:9bcdf88f62b0 13005 #define LCD_FCR_PON_Msk (0x7U << LCD_FCR_PON_Pos) /*!< 0x00000070 */
<> 128:9bcdf88f62b0 13006 #define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
<> 128:9bcdf88f62b0 13007 #define LCD_FCR_PON_0 (0x1U << LCD_FCR_PON_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 13008 #define LCD_FCR_PON_1 (0x2U << LCD_FCR_PON_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 13009 #define LCD_FCR_PON_2 (0x4U << LCD_FCR_PON_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 13010
<> 128:9bcdf88f62b0 13011 #define LCD_FCR_DEAD_Pos (7U)
<> 128:9bcdf88f62b0 13012 #define LCD_FCR_DEAD_Msk (0x7U << LCD_FCR_DEAD_Pos) /*!< 0x00000380 */
<> 128:9bcdf88f62b0 13013 #define LCD_FCR_DEAD LCD_FCR_DEAD_Msk /*!< DEAD[2:0] bits (DEAD Time) */
<> 128:9bcdf88f62b0 13014 #define LCD_FCR_DEAD_0 (0x1U << LCD_FCR_DEAD_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 13015 #define LCD_FCR_DEAD_1 (0x2U << LCD_FCR_DEAD_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 13016 #define LCD_FCR_DEAD_2 (0x4U << LCD_FCR_DEAD_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 13017
<> 128:9bcdf88f62b0 13018 #define LCD_FCR_CC_Pos (10U)
<> 128:9bcdf88f62b0 13019 #define LCD_FCR_CC_Msk (0x7U << LCD_FCR_CC_Pos) /*!< 0x00001C00 */
<> 128:9bcdf88f62b0 13020 #define LCD_FCR_CC LCD_FCR_CC_Msk /*!< CC[2:0] bits (Contrast Control) */
<> 128:9bcdf88f62b0 13021 #define LCD_FCR_CC_0 (0x1U << LCD_FCR_CC_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 13022 #define LCD_FCR_CC_1 (0x2U << LCD_FCR_CC_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 13023 #define LCD_FCR_CC_2 (0x4U << LCD_FCR_CC_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 13024
<> 128:9bcdf88f62b0 13025 #define LCD_FCR_BLINKF_Pos (13U)
<> 128:9bcdf88f62b0 13026 #define LCD_FCR_BLINKF_Msk (0x7U << LCD_FCR_BLINKF_Pos) /*!< 0x0000E000 */
<> 128:9bcdf88f62b0 13027 #define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk /*!< BLINKF[2:0] bits (Blink Frequency) */
<> 128:9bcdf88f62b0 13028 #define LCD_FCR_BLINKF_0 (0x1U << LCD_FCR_BLINKF_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 13029 #define LCD_FCR_BLINKF_1 (0x2U << LCD_FCR_BLINKF_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 13030 #define LCD_FCR_BLINKF_2 (0x4U << LCD_FCR_BLINKF_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 13031
<> 128:9bcdf88f62b0 13032 #define LCD_FCR_BLINK_Pos (16U)
<> 128:9bcdf88f62b0 13033 #define LCD_FCR_BLINK_Msk (0x3U << LCD_FCR_BLINK_Pos) /*!< 0x00030000 */
<> 128:9bcdf88f62b0 13034 #define LCD_FCR_BLINK LCD_FCR_BLINK_Msk /*!< BLINK[1:0] bits (Blink Enable) */
<> 128:9bcdf88f62b0 13035 #define LCD_FCR_BLINK_0 (0x1U << LCD_FCR_BLINK_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 13036 #define LCD_FCR_BLINK_1 (0x2U << LCD_FCR_BLINK_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 13037
<> 128:9bcdf88f62b0 13038 #define LCD_FCR_DIV_Pos (18U)
<> 128:9bcdf88f62b0 13039 #define LCD_FCR_DIV_Msk (0xFU << LCD_FCR_DIV_Pos) /*!< 0x003C0000 */
<> 128:9bcdf88f62b0 13040 #define LCD_FCR_DIV LCD_FCR_DIV_Msk /*!< DIV[3:0] bits (Divider) */
<> 128:9bcdf88f62b0 13041 #define LCD_FCR_PS_Pos (22U)
<> 128:9bcdf88f62b0 13042 #define LCD_FCR_PS_Msk (0xFU << LCD_FCR_PS_Pos) /*!< 0x03C00000 */
<> 128:9bcdf88f62b0 13043 #define LCD_FCR_PS LCD_FCR_PS_Msk /*!< PS[3:0] bits (Prescaler) */
<> 128:9bcdf88f62b0 13044
<> 128:9bcdf88f62b0 13045 /******************* Bit definition for LCD_SR register *********************/
<> 128:9bcdf88f62b0 13046 #define LCD_SR_ENS_Pos (0U)
<> 128:9bcdf88f62b0 13047 #define LCD_SR_ENS_Msk (0x1U << LCD_SR_ENS_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 13048 #define LCD_SR_ENS LCD_SR_ENS_Msk /*!< LCD Enabled Bit */
<> 128:9bcdf88f62b0 13049 #define LCD_SR_SOF_Pos (1U)
<> 128:9bcdf88f62b0 13050 #define LCD_SR_SOF_Msk (0x1U << LCD_SR_SOF_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 13051 #define LCD_SR_SOF LCD_SR_SOF_Msk /*!< Start Of Frame Flag Bit */
<> 128:9bcdf88f62b0 13052 #define LCD_SR_UDR_Pos (2U)
<> 128:9bcdf88f62b0 13053 #define LCD_SR_UDR_Msk (0x1U << LCD_SR_UDR_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 13054 #define LCD_SR_UDR LCD_SR_UDR_Msk /*!< Update Display Request Bit */
<> 128:9bcdf88f62b0 13055 #define LCD_SR_UDD_Pos (3U)
<> 128:9bcdf88f62b0 13056 #define LCD_SR_UDD_Msk (0x1U << LCD_SR_UDD_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 13057 #define LCD_SR_UDD LCD_SR_UDD_Msk /*!< Update Display Done Flag Bit */
<> 128:9bcdf88f62b0 13058 #define LCD_SR_RDY_Pos (4U)
<> 128:9bcdf88f62b0 13059 #define LCD_SR_RDY_Msk (0x1U << LCD_SR_RDY_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 13060 #define LCD_SR_RDY LCD_SR_RDY_Msk /*!< Ready Flag Bit */
<> 128:9bcdf88f62b0 13061 #define LCD_SR_FCRSR_Pos (5U)
<> 128:9bcdf88f62b0 13062 #define LCD_SR_FCRSR_Msk (0x1U << LCD_SR_FCRSR_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 13063 #define LCD_SR_FCRSR LCD_SR_FCRSR_Msk /*!< LCD FCR Register Synchronization Flag Bit */
<> 128:9bcdf88f62b0 13064
<> 128:9bcdf88f62b0 13065 /******************* Bit definition for LCD_CLR register ********************/
<> 128:9bcdf88f62b0 13066 #define LCD_CLR_SOFC_Pos (1U)
<> 128:9bcdf88f62b0 13067 #define LCD_CLR_SOFC_Msk (0x1U << LCD_CLR_SOFC_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 13068 #define LCD_CLR_SOFC LCD_CLR_SOFC_Msk /*!< Start Of Frame Flag Clear Bit */
<> 128:9bcdf88f62b0 13069 #define LCD_CLR_UDDC_Pos (3U)
<> 128:9bcdf88f62b0 13070 #define LCD_CLR_UDDC_Msk (0x1U << LCD_CLR_UDDC_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 13071 #define LCD_CLR_UDDC LCD_CLR_UDDC_Msk /*!< Update Display Done Flag Clear Bit */
<> 128:9bcdf88f62b0 13072
<> 128:9bcdf88f62b0 13073 /******************* Bit definition for LCD_RAM register ********************/
<> 128:9bcdf88f62b0 13074 #define LCD_RAM_SEGMENT_DATA_Pos (0U)
<> 128:9bcdf88f62b0 13075 #define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 13076 #define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk /*!< Segment Data Bits */
<> 128:9bcdf88f62b0 13077
<> 128:9bcdf88f62b0 13078 /******************************************************************************/
<> 128:9bcdf88f62b0 13079 /* */
<> 128:9bcdf88f62b0 13080 /* SDMMC Interface */
<> 128:9bcdf88f62b0 13081 /* */
<> 128:9bcdf88f62b0 13082 /******************************************************************************/
<> 128:9bcdf88f62b0 13083 /****************** Bit definition for SDMMC_POWER register ******************/
<> 128:9bcdf88f62b0 13084 #define SDMMC_POWER_PWRCTRL_Pos (0U)
<> 128:9bcdf88f62b0 13085 #define SDMMC_POWER_PWRCTRL_Msk (0x3U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 13086 #define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
<> 128:9bcdf88f62b0 13087 #define SDMMC_POWER_PWRCTRL_0 (0x1U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 13088 #define SDMMC_POWER_PWRCTRL_1 (0x2U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 13089
<> 128:9bcdf88f62b0 13090 /****************** Bit definition for SDMMC_CLKCR register ******************/
<> 128:9bcdf88f62b0 13091 #define SDMMC_CLKCR_CLKDIV_Pos (0U)
<> 128:9bcdf88f62b0 13092 #define SDMMC_CLKCR_CLKDIV_Msk (0xFFU << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 13093 #define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
<> 128:9bcdf88f62b0 13094 #define SDMMC_CLKCR_CLKEN_Pos (8U)
<> 128:9bcdf88f62b0 13095 #define SDMMC_CLKCR_CLKEN_Msk (0x1U << SDMMC_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 13096 #define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk /*!<Clock enable bit */
<> 128:9bcdf88f62b0 13097 #define SDMMC_CLKCR_PWRSAV_Pos (9U)
<> 128:9bcdf88f62b0 13098 #define SDMMC_CLKCR_PWRSAV_Msk (0x1U << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 13099 #define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
<> 128:9bcdf88f62b0 13100 #define SDMMC_CLKCR_BYPASS_Pos (10U)
<> 128:9bcdf88f62b0 13101 #define SDMMC_CLKCR_BYPASS_Msk (0x1U << SDMMC_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 13102 #define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
<> 128:9bcdf88f62b0 13103 #define SDMMC_CLKCR_WIDBUS_Pos (11U)
<> 128:9bcdf88f62b0 13104 #define SDMMC_CLKCR_WIDBUS_Msk (0x3U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
<> 128:9bcdf88f62b0 13105 #define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
<> 128:9bcdf88f62b0 13106 #define SDMMC_CLKCR_WIDBUS_0 (0x1U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 13107 #define SDMMC_CLKCR_WIDBUS_1 (0x2U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 13108 #define SDMMC_CLKCR_NEGEDGE_Pos (13U)
<> 128:9bcdf88f62b0 13109 #define SDMMC_CLKCR_NEGEDGE_Msk (0x1U << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 13110 #define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
<> 128:9bcdf88f62b0 13111 #define SDMMC_CLKCR_HWFC_EN_Pos (14U)
<> 128:9bcdf88f62b0 13112 #define SDMMC_CLKCR_HWFC_EN_Msk (0x1U << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 13113 #define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
<> 128:9bcdf88f62b0 13114
<> 128:9bcdf88f62b0 13115 /******************* Bit definition for SDMMC_ARG register *******************/
<> 128:9bcdf88f62b0 13116 #define SDMMC_ARG_CMDARG_Pos (0U)
<> 128:9bcdf88f62b0 13117 #define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 13118 #define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
<> 128:9bcdf88f62b0 13119
<> 128:9bcdf88f62b0 13120 /******************* Bit definition for SDMMC_CMD register *******************/
<> 128:9bcdf88f62b0 13121 #define SDMMC_CMD_CMDINDEX_Pos (0U)
<> 128:9bcdf88f62b0 13122 #define SDMMC_CMD_CMDINDEX_Msk (0x3FU << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
<> 128:9bcdf88f62b0 13123 #define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
<> 128:9bcdf88f62b0 13124 #define SDMMC_CMD_WAITRESP_Pos (6U)
<> 128:9bcdf88f62b0 13125 #define SDMMC_CMD_WAITRESP_Msk (0x3U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
<> 128:9bcdf88f62b0 13126 #define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
<> 128:9bcdf88f62b0 13127 #define SDMMC_CMD_WAITRESP_0 (0x1U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 13128 #define SDMMC_CMD_WAITRESP_1 (0x2U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 13129 #define SDMMC_CMD_WAITINT_Pos (8U)
<> 128:9bcdf88f62b0 13130 #define SDMMC_CMD_WAITINT_Msk (0x1U << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 13131 #define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
<> 128:9bcdf88f62b0 13132 #define SDMMC_CMD_WAITPEND_Pos (9U)
<> 128:9bcdf88f62b0 13133 #define SDMMC_CMD_WAITPEND_Msk (0x1U << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 13134 #define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
<> 128:9bcdf88f62b0 13135 #define SDMMC_CMD_CPSMEN_Pos (10U)
<> 128:9bcdf88f62b0 13136 #define SDMMC_CMD_CPSMEN_Msk (0x1U << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 13137 #define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
<> 128:9bcdf88f62b0 13138 #define SDMMC_CMD_SDIOSUSPEND_Pos (11U)
<> 128:9bcdf88f62b0 13139 #define SDMMC_CMD_SDIOSUSPEND_Msk (0x1U << SDMMC_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 13140 #define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
<> 128:9bcdf88f62b0 13141
<> 128:9bcdf88f62b0 13142 /***************** Bit definition for SDMMC_RESPCMD register *****************/
<> 128:9bcdf88f62b0 13143 #define SDMMC_RESPCMD_RESPCMD_Pos (0U)
<> 128:9bcdf88f62b0 13144 #define SDMMC_RESPCMD_RESPCMD_Msk (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
<> 128:9bcdf88f62b0 13145 #define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
<> 128:9bcdf88f62b0 13146
<> 128:9bcdf88f62b0 13147 /****************** Bit definition for SDMMC_RESP0 register ******************/
<> 128:9bcdf88f62b0 13148 #define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
<> 128:9bcdf88f62b0 13149 #define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 13150 #define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk /*!<Card Status */
<> 128:9bcdf88f62b0 13151
<> 128:9bcdf88f62b0 13152 /****************** Bit definition for SDMMC_RESP1 register ******************/
<> 128:9bcdf88f62b0 13153 #define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
<> 128:9bcdf88f62b0 13154 #define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 13155 #define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
<> 128:9bcdf88f62b0 13156
<> 128:9bcdf88f62b0 13157 /****************** Bit definition for SDMMC_RESP2 register ******************/
<> 128:9bcdf88f62b0 13158 #define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
<> 128:9bcdf88f62b0 13159 #define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 13160 #define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
<> 128:9bcdf88f62b0 13161
<> 128:9bcdf88f62b0 13162 /****************** Bit definition for SDMMC_RESP3 register ******************/
<> 128:9bcdf88f62b0 13163 #define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
<> 128:9bcdf88f62b0 13164 #define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 13165 #define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
<> 128:9bcdf88f62b0 13166
<> 128:9bcdf88f62b0 13167 /****************** Bit definition for SDMMC_RESP4 register ******************/
<> 128:9bcdf88f62b0 13168 #define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
<> 128:9bcdf88f62b0 13169 #define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 13170 #define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
<> 128:9bcdf88f62b0 13171
<> 128:9bcdf88f62b0 13172 /****************** Bit definition for SDMMC_DTIMER register *****************/
<> 128:9bcdf88f62b0 13173 #define SDMMC_DTIMER_DATATIME_Pos (0U)
<> 128:9bcdf88f62b0 13174 #define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 13175 #define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
<> 128:9bcdf88f62b0 13176
<> 128:9bcdf88f62b0 13177 /****************** Bit definition for SDMMC_DLEN register *******************/
<> 128:9bcdf88f62b0 13178 #define SDMMC_DLEN_DATALENGTH_Pos (0U)
<> 128:9bcdf88f62b0 13179 #define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
<> 128:9bcdf88f62b0 13180 #define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
<> 128:9bcdf88f62b0 13181
<> 128:9bcdf88f62b0 13182 /****************** Bit definition for SDMMC_DCTRL register ******************/
<> 128:9bcdf88f62b0 13183 #define SDMMC_DCTRL_DTEN_Pos (0U)
<> 128:9bcdf88f62b0 13184 #define SDMMC_DCTRL_DTEN_Msk (0x1U << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 13185 #define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
<> 128:9bcdf88f62b0 13186 #define SDMMC_DCTRL_DTDIR_Pos (1U)
<> 128:9bcdf88f62b0 13187 #define SDMMC_DCTRL_DTDIR_Msk (0x1U << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 13188 #define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
<> 128:9bcdf88f62b0 13189 #define SDMMC_DCTRL_DTMODE_Pos (2U)
<> 128:9bcdf88f62b0 13190 #define SDMMC_DCTRL_DTMODE_Msk (0x1U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 13191 #define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
<> 128:9bcdf88f62b0 13192 #define SDMMC_DCTRL_DMAEN_Pos (3U)
<> 128:9bcdf88f62b0 13193 #define SDMMC_DCTRL_DMAEN_Msk (0x1U << SDMMC_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 13194 #define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
<> 128:9bcdf88f62b0 13195 #define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
<> 128:9bcdf88f62b0 13196 #define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
<> 128:9bcdf88f62b0 13197 #define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
<> 128:9bcdf88f62b0 13198 #define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 13199 #define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 13200 #define SDMMC_DCTRL_DBLOCKSIZE_2 (0x3U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 13201 #define SDMMC_DCTRL_DBLOCKSIZE_3 (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 13202 #define SDMMC_DCTRL_RWSTART_Pos (8U)
<> 128:9bcdf88f62b0 13203 #define SDMMC_DCTRL_RWSTART_Msk (0x1U << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 13204 #define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
<> 128:9bcdf88f62b0 13205 #define SDMMC_DCTRL_RWSTOP_Pos (9U)
<> 128:9bcdf88f62b0 13206 #define SDMMC_DCTRL_RWSTOP_Msk (0x1U << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 13207 #define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
<> 128:9bcdf88f62b0 13208 #define SDMMC_DCTRL_RWMOD_Pos (10U)
<> 128:9bcdf88f62b0 13209 #define SDMMC_DCTRL_RWMOD_Msk (0x1U << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 13210 #define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
<> 128:9bcdf88f62b0 13211 #define SDMMC_DCTRL_SDIOEN_Pos (11U)
<> 128:9bcdf88f62b0 13212 #define SDMMC_DCTRL_SDIOEN_Msk (0x1U << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 13213 #define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
<> 128:9bcdf88f62b0 13214
<> 128:9bcdf88f62b0 13215 /****************** Bit definition for SDMMC_DCOUNT register *****************/
<> 128:9bcdf88f62b0 13216 #define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
<> 128:9bcdf88f62b0 13217 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
<> 128:9bcdf88f62b0 13218 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
<> 128:9bcdf88f62b0 13219
<> 128:9bcdf88f62b0 13220 /****************** Bit definition for SDMMC_STA register ********************/
<> 128:9bcdf88f62b0 13221 #define SDMMC_STA_CCRCFAIL_Pos (0U)
<> 128:9bcdf88f62b0 13222 #define SDMMC_STA_CCRCFAIL_Msk (0x1U << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 13223 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
<> 128:9bcdf88f62b0 13224 #define SDMMC_STA_DCRCFAIL_Pos (1U)
<> 128:9bcdf88f62b0 13225 #define SDMMC_STA_DCRCFAIL_Msk (0x1U << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 13226 #define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
<> 128:9bcdf88f62b0 13227 #define SDMMC_STA_CTIMEOUT_Pos (2U)
<> 128:9bcdf88f62b0 13228 #define SDMMC_STA_CTIMEOUT_Msk (0x1U << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 13229 #define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
<> 128:9bcdf88f62b0 13230 #define SDMMC_STA_DTIMEOUT_Pos (3U)
<> 128:9bcdf88f62b0 13231 #define SDMMC_STA_DTIMEOUT_Msk (0x1U << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 13232 #define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
<> 128:9bcdf88f62b0 13233 #define SDMMC_STA_TXUNDERR_Pos (4U)
<> 128:9bcdf88f62b0 13234 #define SDMMC_STA_TXUNDERR_Msk (0x1U << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 13235 #define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
<> 128:9bcdf88f62b0 13236 #define SDMMC_STA_RXOVERR_Pos (5U)
<> 128:9bcdf88f62b0 13237 #define SDMMC_STA_RXOVERR_Msk (0x1U << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 13238 #define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
<> 128:9bcdf88f62b0 13239 #define SDMMC_STA_CMDREND_Pos (6U)
<> 128:9bcdf88f62b0 13240 #define SDMMC_STA_CMDREND_Msk (0x1U << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 13241 #define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
<> 128:9bcdf88f62b0 13242 #define SDMMC_STA_CMDSENT_Pos (7U)
<> 128:9bcdf88f62b0 13243 #define SDMMC_STA_CMDSENT_Msk (0x1U << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 13244 #define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
<> 128:9bcdf88f62b0 13245 #define SDMMC_STA_DATAEND_Pos (8U)
<> 128:9bcdf88f62b0 13246 #define SDMMC_STA_DATAEND_Msk (0x1U << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 13247 #define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
<> 128:9bcdf88f62b0 13248 #define SDMMC_STA_STBITERR_Pos (9U)
<> 128:9bcdf88f62b0 13249 #define SDMMC_STA_STBITERR_Msk (0x1U << SDMMC_STA_STBITERR_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 13250 #define SDMMC_STA_STBITERR SDMMC_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
<> 128:9bcdf88f62b0 13251 #define SDMMC_STA_DBCKEND_Pos (10U)
<> 128:9bcdf88f62b0 13252 #define SDMMC_STA_DBCKEND_Msk (0x1U << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 13253 #define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
<> 128:9bcdf88f62b0 13254 #define SDMMC_STA_CMDACT_Pos (11U)
<> 128:9bcdf88f62b0 13255 #define SDMMC_STA_CMDACT_Msk (0x1U << SDMMC_STA_CMDACT_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 13256 #define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk /*!<Command transfer in progress */
<> 128:9bcdf88f62b0 13257 #define SDMMC_STA_TXACT_Pos (12U)
<> 128:9bcdf88f62b0 13258 #define SDMMC_STA_TXACT_Msk (0x1U << SDMMC_STA_TXACT_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 13259 #define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk /*!<Data transmit in progress */
<> 128:9bcdf88f62b0 13260 #define SDMMC_STA_RXACT_Pos (13U)
<> 128:9bcdf88f62b0 13261 #define SDMMC_STA_RXACT_Msk (0x1U << SDMMC_STA_RXACT_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 13262 #define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk /*!<Data receive in progress */
<> 128:9bcdf88f62b0 13263 #define SDMMC_STA_TXFIFOHE_Pos (14U)
<> 128:9bcdf88f62b0 13264 #define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 13265 #define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
<> 128:9bcdf88f62b0 13266 #define SDMMC_STA_RXFIFOHF_Pos (15U)
<> 128:9bcdf88f62b0 13267 #define SDMMC_STA_RXFIFOHF_Msk (0x1U << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 13268 #define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
<> 128:9bcdf88f62b0 13269 #define SDMMC_STA_TXFIFOF_Pos (16U)
<> 128:9bcdf88f62b0 13270 #define SDMMC_STA_TXFIFOF_Msk (0x1U << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 13271 #define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
<> 128:9bcdf88f62b0 13272 #define SDMMC_STA_RXFIFOF_Pos (17U)
<> 128:9bcdf88f62b0 13273 #define SDMMC_STA_RXFIFOF_Msk (0x1U << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 13274 #define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
<> 128:9bcdf88f62b0 13275 #define SDMMC_STA_TXFIFOE_Pos (18U)
<> 128:9bcdf88f62b0 13276 #define SDMMC_STA_TXFIFOE_Msk (0x1U << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 13277 #define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
<> 128:9bcdf88f62b0 13278 #define SDMMC_STA_RXFIFOE_Pos (19U)
<> 128:9bcdf88f62b0 13279 #define SDMMC_STA_RXFIFOE_Msk (0x1U << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 13280 #define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
<> 128:9bcdf88f62b0 13281 #define SDMMC_STA_TXDAVL_Pos (20U)
<> 128:9bcdf88f62b0 13282 #define SDMMC_STA_TXDAVL_Msk (0x1U << SDMMC_STA_TXDAVL_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 13283 #define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
<> 128:9bcdf88f62b0 13284 #define SDMMC_STA_RXDAVL_Pos (21U)
<> 128:9bcdf88f62b0 13285 #define SDMMC_STA_RXDAVL_Msk (0x1U << SDMMC_STA_RXDAVL_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 13286 #define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
<> 128:9bcdf88f62b0 13287 #define SDMMC_STA_SDIOIT_Pos (22U)
<> 128:9bcdf88f62b0 13288 #define SDMMC_STA_SDIOIT_Msk (0x1U << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 13289 #define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */
<> 128:9bcdf88f62b0 13290
<> 128:9bcdf88f62b0 13291 /******************* Bit definition for SDMMC_ICR register *******************/
<> 128:9bcdf88f62b0 13292 #define SDMMC_ICR_CCRCFAILC_Pos (0U)
<> 128:9bcdf88f62b0 13293 #define SDMMC_ICR_CCRCFAILC_Msk (0x1U << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 13294 #define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
<> 128:9bcdf88f62b0 13295 #define SDMMC_ICR_DCRCFAILC_Pos (1U)
<> 128:9bcdf88f62b0 13296 #define SDMMC_ICR_DCRCFAILC_Msk (0x1U << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 13297 #define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
<> 128:9bcdf88f62b0 13298 #define SDMMC_ICR_CTIMEOUTC_Pos (2U)
<> 128:9bcdf88f62b0 13299 #define SDMMC_ICR_CTIMEOUTC_Msk (0x1U << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 13300 #define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
<> 128:9bcdf88f62b0 13301 #define SDMMC_ICR_DTIMEOUTC_Pos (3U)
<> 128:9bcdf88f62b0 13302 #define SDMMC_ICR_DTIMEOUTC_Msk (0x1U << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 13303 #define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
<> 128:9bcdf88f62b0 13304 #define SDMMC_ICR_TXUNDERRC_Pos (4U)
<> 128:9bcdf88f62b0 13305 #define SDMMC_ICR_TXUNDERRC_Msk (0x1U << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 13306 #define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
<> 128:9bcdf88f62b0 13307 #define SDMMC_ICR_RXOVERRC_Pos (5U)
<> 128:9bcdf88f62b0 13308 #define SDMMC_ICR_RXOVERRC_Msk (0x1U << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 13309 #define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
<> 128:9bcdf88f62b0 13310 #define SDMMC_ICR_CMDRENDC_Pos (6U)
<> 128:9bcdf88f62b0 13311 #define SDMMC_ICR_CMDRENDC_Msk (0x1U << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 13312 #define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
<> 128:9bcdf88f62b0 13313 #define SDMMC_ICR_CMDSENTC_Pos (7U)
<> 128:9bcdf88f62b0 13314 #define SDMMC_ICR_CMDSENTC_Msk (0x1U << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 13315 #define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
<> 128:9bcdf88f62b0 13316 #define SDMMC_ICR_DATAENDC_Pos (8U)
<> 128:9bcdf88f62b0 13317 #define SDMMC_ICR_DATAENDC_Msk (0x1U << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 13318 #define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
<> 128:9bcdf88f62b0 13319 #define SDMMC_ICR_STBITERRC_Pos (9U)
<> 128:9bcdf88f62b0 13320 #define SDMMC_ICR_STBITERRC_Msk (0x1U << SDMMC_ICR_STBITERRC_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 13321 #define SDMMC_ICR_STBITERRC SDMMC_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
<> 128:9bcdf88f62b0 13322 #define SDMMC_ICR_DBCKENDC_Pos (10U)
<> 128:9bcdf88f62b0 13323 #define SDMMC_ICR_DBCKENDC_Msk (0x1U << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 13324 #define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
<> 128:9bcdf88f62b0 13325 #define SDMMC_ICR_SDIOITC_Pos (22U)
<> 128:9bcdf88f62b0 13326 #define SDMMC_ICR_SDIOITC_Msk (0x1U << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 13327 #define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
<> 128:9bcdf88f62b0 13328
<> 128:9bcdf88f62b0 13329 /****************** Bit definition for SDMMC_MASK register *******************/
<> 128:9bcdf88f62b0 13330 #define SDMMC_MASK_CCRCFAILIE_Pos (0U)
<> 128:9bcdf88f62b0 13331 #define SDMMC_MASK_CCRCFAILIE_Msk (0x1U << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 13332 #define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
<> 128:9bcdf88f62b0 13333 #define SDMMC_MASK_DCRCFAILIE_Pos (1U)
<> 128:9bcdf88f62b0 13334 #define SDMMC_MASK_DCRCFAILIE_Msk (0x1U << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 13335 #define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
<> 128:9bcdf88f62b0 13336 #define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
<> 128:9bcdf88f62b0 13337 #define SDMMC_MASK_CTIMEOUTIE_Msk (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 13338 #define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
<> 128:9bcdf88f62b0 13339 #define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
<> 128:9bcdf88f62b0 13340 #define SDMMC_MASK_DTIMEOUTIE_Msk (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 13341 #define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
<> 128:9bcdf88f62b0 13342 #define SDMMC_MASK_TXUNDERRIE_Pos (4U)
<> 128:9bcdf88f62b0 13343 #define SDMMC_MASK_TXUNDERRIE_Msk (0x1U << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 13344 #define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
<> 128:9bcdf88f62b0 13345 #define SDMMC_MASK_RXOVERRIE_Pos (5U)
<> 128:9bcdf88f62b0 13346 #define SDMMC_MASK_RXOVERRIE_Msk (0x1U << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 13347 #define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
<> 128:9bcdf88f62b0 13348 #define SDMMC_MASK_CMDRENDIE_Pos (6U)
<> 128:9bcdf88f62b0 13349 #define SDMMC_MASK_CMDRENDIE_Msk (0x1U << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 13350 #define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
<> 128:9bcdf88f62b0 13351 #define SDMMC_MASK_CMDSENTIE_Pos (7U)
<> 128:9bcdf88f62b0 13352 #define SDMMC_MASK_CMDSENTIE_Msk (0x1U << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 13353 #define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
<> 128:9bcdf88f62b0 13354 #define SDMMC_MASK_DATAENDIE_Pos (8U)
<> 128:9bcdf88f62b0 13355 #define SDMMC_MASK_DATAENDIE_Msk (0x1U << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 13356 #define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
<> 128:9bcdf88f62b0 13357 #define SDMMC_MASK_DBCKENDIE_Pos (10U)
<> 128:9bcdf88f62b0 13358 #define SDMMC_MASK_DBCKENDIE_Msk (0x1U << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 13359 #define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
<> 128:9bcdf88f62b0 13360 #define SDMMC_MASK_CMDACTIE_Pos (11U)
<> 128:9bcdf88f62b0 13361 #define SDMMC_MASK_CMDACTIE_Msk (0x1U << SDMMC_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 13362 #define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
<> 128:9bcdf88f62b0 13363 #define SDMMC_MASK_TXACTIE_Pos (12U)
<> 128:9bcdf88f62b0 13364 #define SDMMC_MASK_TXACTIE_Msk (0x1U << SDMMC_MASK_TXACTIE_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 13365 #define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
<> 128:9bcdf88f62b0 13366 #define SDMMC_MASK_RXACTIE_Pos (13U)
<> 128:9bcdf88f62b0 13367 #define SDMMC_MASK_RXACTIE_Msk (0x1U << SDMMC_MASK_RXACTIE_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 13368 #define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
<> 128:9bcdf88f62b0 13369 #define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
<> 128:9bcdf88f62b0 13370 #define SDMMC_MASK_TXFIFOHEIE_Msk (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 13371 #define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
<> 128:9bcdf88f62b0 13372 #define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
<> 128:9bcdf88f62b0 13373 #define SDMMC_MASK_RXFIFOHFIE_Msk (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 13374 #define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
<> 128:9bcdf88f62b0 13375 #define SDMMC_MASK_TXFIFOFIE_Pos (16U)
<> 128:9bcdf88f62b0 13376 #define SDMMC_MASK_TXFIFOFIE_Msk (0x1U << SDMMC_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 13377 #define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
<> 128:9bcdf88f62b0 13378 #define SDMMC_MASK_RXFIFOFIE_Pos (17U)
<> 128:9bcdf88f62b0 13379 #define SDMMC_MASK_RXFIFOFIE_Msk (0x1U << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 13380 #define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
<> 128:9bcdf88f62b0 13381 #define SDMMC_MASK_TXFIFOEIE_Pos (18U)
<> 128:9bcdf88f62b0 13382 #define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 13383 #define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
<> 128:9bcdf88f62b0 13384 #define SDMMC_MASK_RXFIFOEIE_Pos (19U)
<> 128:9bcdf88f62b0 13385 #define SDMMC_MASK_RXFIFOEIE_Msk (0x1U << SDMMC_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 13386 #define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
<> 128:9bcdf88f62b0 13387 #define SDMMC_MASK_TXDAVLIE_Pos (20U)
<> 128:9bcdf88f62b0 13388 #define SDMMC_MASK_TXDAVLIE_Msk (0x1U << SDMMC_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 13389 #define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
<> 128:9bcdf88f62b0 13390 #define SDMMC_MASK_RXDAVLIE_Pos (21U)
<> 128:9bcdf88f62b0 13391 #define SDMMC_MASK_RXDAVLIE_Msk (0x1U << SDMMC_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 13392 #define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
<> 128:9bcdf88f62b0 13393 #define SDMMC_MASK_SDIOITIE_Pos (22U)
<> 128:9bcdf88f62b0 13394 #define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 13395 #define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
<> 128:9bcdf88f62b0 13396
<> 128:9bcdf88f62b0 13397 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
<> 128:9bcdf88f62b0 13398 #define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
<> 128:9bcdf88f62b0 13399 #define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
<> 128:9bcdf88f62b0 13400 #define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
<> 128:9bcdf88f62b0 13401
<> 128:9bcdf88f62b0 13402 /****************** Bit definition for SDMMC_FIFO register *******************/
<> 128:9bcdf88f62b0 13403 #define SDMMC_FIFO_FIFODATA_Pos (0U)
<> 128:9bcdf88f62b0 13404 #define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 13405 #define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
<> 128:9bcdf88f62b0 13406
<> 128:9bcdf88f62b0 13407 /******************************************************************************/
<> 128:9bcdf88f62b0 13408 /* */
<> 128:9bcdf88f62b0 13409 /* Serial Peripheral Interface (SPI) */
<> 128:9bcdf88f62b0 13410 /* */
<> 128:9bcdf88f62b0 13411 /******************************************************************************/
<> 128:9bcdf88f62b0 13412 /******************* Bit definition for SPI_CR1 register ********************/
<> 128:9bcdf88f62b0 13413 #define SPI_CR1_CPHA_Pos (0U)
<> 128:9bcdf88f62b0 13414 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 13415 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
<> 128:9bcdf88f62b0 13416 #define SPI_CR1_CPOL_Pos (1U)
<> 128:9bcdf88f62b0 13417 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 13418 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
<> 128:9bcdf88f62b0 13419 #define SPI_CR1_MSTR_Pos (2U)
<> 128:9bcdf88f62b0 13420 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 13421 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
<> 128:9bcdf88f62b0 13422
<> 128:9bcdf88f62b0 13423 #define SPI_CR1_BR_Pos (3U)
<> 128:9bcdf88f62b0 13424 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
<> 128:9bcdf88f62b0 13425 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
<> 128:9bcdf88f62b0 13426 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 13427 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 13428 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 13429
<> 128:9bcdf88f62b0 13430 #define SPI_CR1_SPE_Pos (6U)
<> 128:9bcdf88f62b0 13431 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 13432 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
<> 128:9bcdf88f62b0 13433 #define SPI_CR1_LSBFIRST_Pos (7U)
<> 128:9bcdf88f62b0 13434 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 13435 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
<> 128:9bcdf88f62b0 13436 #define SPI_CR1_SSI_Pos (8U)
<> 128:9bcdf88f62b0 13437 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 13438 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
<> 128:9bcdf88f62b0 13439 #define SPI_CR1_SSM_Pos (9U)
<> 128:9bcdf88f62b0 13440 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 13441 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
<> 128:9bcdf88f62b0 13442 #define SPI_CR1_RXONLY_Pos (10U)
<> 128:9bcdf88f62b0 13443 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 13444 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
<> 128:9bcdf88f62b0 13445 #define SPI_CR1_CRCL_Pos (11U)
<> 128:9bcdf88f62b0 13446 #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 13447 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
<> 128:9bcdf88f62b0 13448 #define SPI_CR1_CRCNEXT_Pos (12U)
<> 128:9bcdf88f62b0 13449 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 13450 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
<> 128:9bcdf88f62b0 13451 #define SPI_CR1_CRCEN_Pos (13U)
<> 128:9bcdf88f62b0 13452 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 13453 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
<> 128:9bcdf88f62b0 13454 #define SPI_CR1_BIDIOE_Pos (14U)
<> 128:9bcdf88f62b0 13455 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 13456 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
<> 128:9bcdf88f62b0 13457 #define SPI_CR1_BIDIMODE_Pos (15U)
<> 128:9bcdf88f62b0 13458 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 13459 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
<> 128:9bcdf88f62b0 13460
<> 128:9bcdf88f62b0 13461 /******************* Bit definition for SPI_CR2 register ********************/
<> 128:9bcdf88f62b0 13462 #define SPI_CR2_RXDMAEN_Pos (0U)
<> 128:9bcdf88f62b0 13463 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 13464 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
<> 128:9bcdf88f62b0 13465 #define SPI_CR2_TXDMAEN_Pos (1U)
<> 128:9bcdf88f62b0 13466 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 13467 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
<> 128:9bcdf88f62b0 13468 #define SPI_CR2_SSOE_Pos (2U)
<> 128:9bcdf88f62b0 13469 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 13470 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
<> 128:9bcdf88f62b0 13471 #define SPI_CR2_NSSP_Pos (3U)
<> 128:9bcdf88f62b0 13472 #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 13473 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
<> 128:9bcdf88f62b0 13474 #define SPI_CR2_FRF_Pos (4U)
<> 128:9bcdf88f62b0 13475 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 13476 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
<> 128:9bcdf88f62b0 13477 #define SPI_CR2_ERRIE_Pos (5U)
<> 128:9bcdf88f62b0 13478 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 13479 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
<> 128:9bcdf88f62b0 13480 #define SPI_CR2_RXNEIE_Pos (6U)
<> 128:9bcdf88f62b0 13481 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 13482 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
<> 128:9bcdf88f62b0 13483 #define SPI_CR2_TXEIE_Pos (7U)
<> 128:9bcdf88f62b0 13484 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 13485 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
<> 128:9bcdf88f62b0 13486 #define SPI_CR2_DS_Pos (8U)
<> 128:9bcdf88f62b0 13487 #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
<> 128:9bcdf88f62b0 13488 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
<> 128:9bcdf88f62b0 13489 #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 13490 #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 13491 #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 13492 #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 13493 #define SPI_CR2_FRXTH_Pos (12U)
<> 128:9bcdf88f62b0 13494 #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 13495 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
<> 128:9bcdf88f62b0 13496 #define SPI_CR2_LDMARX_Pos (13U)
<> 128:9bcdf88f62b0 13497 #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 13498 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
<> 128:9bcdf88f62b0 13499 #define SPI_CR2_LDMATX_Pos (14U)
<> 128:9bcdf88f62b0 13500 #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 13501 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
<> 128:9bcdf88f62b0 13502
<> 128:9bcdf88f62b0 13503 /******************** Bit definition for SPI_SR register ********************/
<> 128:9bcdf88f62b0 13504 #define SPI_SR_RXNE_Pos (0U)
<> 128:9bcdf88f62b0 13505 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 13506 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
<> 128:9bcdf88f62b0 13507 #define SPI_SR_TXE_Pos (1U)
<> 128:9bcdf88f62b0 13508 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 13509 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
<> 128:9bcdf88f62b0 13510 #define SPI_SR_CHSIDE_Pos (2U)
<> 128:9bcdf88f62b0 13511 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 13512 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
<> 128:9bcdf88f62b0 13513 #define SPI_SR_UDR_Pos (3U)
<> 128:9bcdf88f62b0 13514 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 13515 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
<> 128:9bcdf88f62b0 13516 #define SPI_SR_CRCERR_Pos (4U)
<> 128:9bcdf88f62b0 13517 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 13518 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
<> 128:9bcdf88f62b0 13519 #define SPI_SR_MODF_Pos (5U)
<> 128:9bcdf88f62b0 13520 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 13521 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
<> 128:9bcdf88f62b0 13522 #define SPI_SR_OVR_Pos (6U)
<> 128:9bcdf88f62b0 13523 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 13524 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
<> 128:9bcdf88f62b0 13525 #define SPI_SR_BSY_Pos (7U)
<> 128:9bcdf88f62b0 13526 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 13527 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
<> 128:9bcdf88f62b0 13528 #define SPI_SR_FRE_Pos (8U)
<> 128:9bcdf88f62b0 13529 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 13530 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
<> 128:9bcdf88f62b0 13531 #define SPI_SR_FRLVL_Pos (9U)
<> 128:9bcdf88f62b0 13532 #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
<> 128:9bcdf88f62b0 13533 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
<> 128:9bcdf88f62b0 13534 #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 13535 #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 13536 #define SPI_SR_FTLVL_Pos (11U)
<> 128:9bcdf88f62b0 13537 #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
<> 128:9bcdf88f62b0 13538 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
<> 128:9bcdf88f62b0 13539 #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 13540 #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 13541
<> 128:9bcdf88f62b0 13542 /******************** Bit definition for SPI_DR register ********************/
<> 128:9bcdf88f62b0 13543 #define SPI_DR_DR_Pos (0U)
<> 128:9bcdf88f62b0 13544 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 13545 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
<> 128:9bcdf88f62b0 13546
<> 128:9bcdf88f62b0 13547 /******************* Bit definition for SPI_CRCPR register ******************/
<> 128:9bcdf88f62b0 13548 #define SPI_CRCPR_CRCPOLY_Pos (0U)
<> 128:9bcdf88f62b0 13549 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 13550 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
<> 128:9bcdf88f62b0 13551
<> 128:9bcdf88f62b0 13552 /****************** Bit definition for SPI_RXCRCR register ******************/
<> 128:9bcdf88f62b0 13553 #define SPI_RXCRCR_RXCRC_Pos (0U)
<> 128:9bcdf88f62b0 13554 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 13555 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
<> 128:9bcdf88f62b0 13556
<> 128:9bcdf88f62b0 13557 /****************** Bit definition for SPI_TXCRCR register ******************/
<> 128:9bcdf88f62b0 13558 #define SPI_TXCRCR_TXCRC_Pos (0U)
<> 128:9bcdf88f62b0 13559 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 13560 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
<> 128:9bcdf88f62b0 13561
<> 128:9bcdf88f62b0 13562 /******************************************************************************/
<> 128:9bcdf88f62b0 13563 /* */
<> 128:9bcdf88f62b0 13564 /* QUADSPI */
<> 128:9bcdf88f62b0 13565 /* */
<> 128:9bcdf88f62b0 13566 /******************************************************************************/
<> 128:9bcdf88f62b0 13567 /***************** Bit definition for QUADSPI_CR register *******************/
<> 128:9bcdf88f62b0 13568 #define QUADSPI_CR_EN_Pos (0U)
<> 128:9bcdf88f62b0 13569 #define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 13570 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
<> 128:9bcdf88f62b0 13571 #define QUADSPI_CR_ABORT_Pos (1U)
<> 128:9bcdf88f62b0 13572 #define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 13573 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
<> 128:9bcdf88f62b0 13574 #define QUADSPI_CR_DMAEN_Pos (2U)
<> 128:9bcdf88f62b0 13575 #define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 13576 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
<> 128:9bcdf88f62b0 13577 #define QUADSPI_CR_TCEN_Pos (3U)
<> 128:9bcdf88f62b0 13578 #define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 13579 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
<> 128:9bcdf88f62b0 13580 #define QUADSPI_CR_SSHIFT_Pos (4U)
<> 128:9bcdf88f62b0 13581 #define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 13582 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
<> 128:9bcdf88f62b0 13583 #define QUADSPI_CR_FTHRES_Pos (8U)
<> 128:9bcdf88f62b0 13584 #define QUADSPI_CR_FTHRES_Msk (0xFU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
<> 128:9bcdf88f62b0 13585 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
<> 128:9bcdf88f62b0 13586 #define QUADSPI_CR_TEIE_Pos (16U)
<> 128:9bcdf88f62b0 13587 #define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 13588 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
<> 128:9bcdf88f62b0 13589 #define QUADSPI_CR_TCIE_Pos (17U)
<> 128:9bcdf88f62b0 13590 #define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 13591 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
<> 128:9bcdf88f62b0 13592 #define QUADSPI_CR_FTIE_Pos (18U)
<> 128:9bcdf88f62b0 13593 #define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 13594 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
<> 128:9bcdf88f62b0 13595 #define QUADSPI_CR_SMIE_Pos (19U)
<> 128:9bcdf88f62b0 13596 #define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 13597 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
<> 128:9bcdf88f62b0 13598 #define QUADSPI_CR_TOIE_Pos (20U)
<> 128:9bcdf88f62b0 13599 #define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 13600 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
<> 128:9bcdf88f62b0 13601 #define QUADSPI_CR_APMS_Pos (22U)
<> 128:9bcdf88f62b0 13602 #define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 13603 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Automatic Polling Mode Stop */
<> 128:9bcdf88f62b0 13604 #define QUADSPI_CR_PMM_Pos (23U)
<> 128:9bcdf88f62b0 13605 #define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 13606 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
<> 128:9bcdf88f62b0 13607 #define QUADSPI_CR_PRESCALER_Pos (24U)
<> 128:9bcdf88f62b0 13608 #define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
<> 128:9bcdf88f62b0 13609 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
<> 128:9bcdf88f62b0 13610
<> 128:9bcdf88f62b0 13611 /***************** Bit definition for QUADSPI_DCR register ******************/
<> 128:9bcdf88f62b0 13612 #define QUADSPI_DCR_CKMODE_Pos (0U)
<> 128:9bcdf88f62b0 13613 #define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 13614 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
<> 128:9bcdf88f62b0 13615 #define QUADSPI_DCR_CSHT_Pos (8U)
<> 128:9bcdf88f62b0 13616 #define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
<> 128:9bcdf88f62b0 13617 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
<> 128:9bcdf88f62b0 13618 #define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 13619 #define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 13620 #define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 13621 #define QUADSPI_DCR_FSIZE_Pos (16U)
<> 128:9bcdf88f62b0 13622 #define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
<> 128:9bcdf88f62b0 13623 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
<> 128:9bcdf88f62b0 13624
<> 128:9bcdf88f62b0 13625 /****************** Bit definition for QUADSPI_SR register *******************/
<> 128:9bcdf88f62b0 13626 #define QUADSPI_SR_TEF_Pos (0U)
<> 128:9bcdf88f62b0 13627 #define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 13628 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
<> 128:9bcdf88f62b0 13629 #define QUADSPI_SR_TCF_Pos (1U)
<> 128:9bcdf88f62b0 13630 #define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 13631 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
<> 128:9bcdf88f62b0 13632 #define QUADSPI_SR_FTF_Pos (2U)
<> 128:9bcdf88f62b0 13633 #define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 13634 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
<> 128:9bcdf88f62b0 13635 #define QUADSPI_SR_SMF_Pos (3U)
<> 128:9bcdf88f62b0 13636 #define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 13637 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
<> 128:9bcdf88f62b0 13638 #define QUADSPI_SR_TOF_Pos (4U)
<> 128:9bcdf88f62b0 13639 #define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 13640 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
<> 128:9bcdf88f62b0 13641 #define QUADSPI_SR_BUSY_Pos (5U)
<> 128:9bcdf88f62b0 13642 #define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 13643 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
<> 128:9bcdf88f62b0 13644 #define QUADSPI_SR_FLEVEL_Pos (8U)
<> 128:9bcdf88f62b0 13645 #define QUADSPI_SR_FLEVEL_Msk (0x1FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
<> 128:9bcdf88f62b0 13646 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
<> 128:9bcdf88f62b0 13647
<> 128:9bcdf88f62b0 13648 /****************** Bit definition for QUADSPI_FCR register ******************/
<> 128:9bcdf88f62b0 13649 #define QUADSPI_FCR_CTEF_Pos (0U)
<> 128:9bcdf88f62b0 13650 #define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 13651 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
<> 128:9bcdf88f62b0 13652 #define QUADSPI_FCR_CTCF_Pos (1U)
<> 128:9bcdf88f62b0 13653 #define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 13654 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
<> 128:9bcdf88f62b0 13655 #define QUADSPI_FCR_CSMF_Pos (3U)
<> 128:9bcdf88f62b0 13656 #define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 13657 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
<> 128:9bcdf88f62b0 13658 #define QUADSPI_FCR_CTOF_Pos (4U)
<> 128:9bcdf88f62b0 13659 #define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 13660 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
<> 128:9bcdf88f62b0 13661
<> 128:9bcdf88f62b0 13662 /****************** Bit definition for QUADSPI_DLR register ******************/
<> 128:9bcdf88f62b0 13663 #define QUADSPI_DLR_DL_Pos (0U)
<> 128:9bcdf88f62b0 13664 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 13665 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
<> 128:9bcdf88f62b0 13666
<> 128:9bcdf88f62b0 13667 /****************** Bit definition for QUADSPI_CCR register ******************/
<> 128:9bcdf88f62b0 13668 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
<> 128:9bcdf88f62b0 13669 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 13670 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
<> 128:9bcdf88f62b0 13671 #define QUADSPI_CCR_IMODE_Pos (8U)
<> 128:9bcdf88f62b0 13672 #define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
<> 128:9bcdf88f62b0 13673 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
<> 128:9bcdf88f62b0 13674 #define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 13675 #define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 13676 #define QUADSPI_CCR_ADMODE_Pos (10U)
<> 128:9bcdf88f62b0 13677 #define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
<> 128:9bcdf88f62b0 13678 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
<> 128:9bcdf88f62b0 13679 #define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 13680 #define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 13681 #define QUADSPI_CCR_ADSIZE_Pos (12U)
<> 128:9bcdf88f62b0 13682 #define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
<> 128:9bcdf88f62b0 13683 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
<> 128:9bcdf88f62b0 13684 #define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 13685 #define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 13686 #define QUADSPI_CCR_ABMODE_Pos (14U)
<> 128:9bcdf88f62b0 13687 #define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
<> 128:9bcdf88f62b0 13688 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
<> 128:9bcdf88f62b0 13689 #define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 13690 #define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 13691 #define QUADSPI_CCR_ABSIZE_Pos (16U)
<> 128:9bcdf88f62b0 13692 #define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
<> 128:9bcdf88f62b0 13693 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
<> 128:9bcdf88f62b0 13694 #define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 13695 #define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 13696 #define QUADSPI_CCR_DCYC_Pos (18U)
<> 128:9bcdf88f62b0 13697 #define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
<> 128:9bcdf88f62b0 13698 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
<> 128:9bcdf88f62b0 13699 #define QUADSPI_CCR_DMODE_Pos (24U)
<> 128:9bcdf88f62b0 13700 #define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
<> 128:9bcdf88f62b0 13701 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
<> 128:9bcdf88f62b0 13702 #define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 13703 #define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 13704 #define QUADSPI_CCR_FMODE_Pos (26U)
<> 128:9bcdf88f62b0 13705 #define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
<> 128:9bcdf88f62b0 13706 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
<> 128:9bcdf88f62b0 13707 #define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 13708 #define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 13709 #define QUADSPI_CCR_SIOO_Pos (28U)
<> 128:9bcdf88f62b0 13710 #define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 13711 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
<> 128:9bcdf88f62b0 13712 #define QUADSPI_CCR_DDRM_Pos (31U)
<> 128:9bcdf88f62b0 13713 #define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 13714 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
<> 128:9bcdf88f62b0 13715
<> 128:9bcdf88f62b0 13716 /****************** Bit definition for QUADSPI_AR register *******************/
<> 128:9bcdf88f62b0 13717 #define QUADSPI_AR_ADDRESS_Pos (0U)
<> 128:9bcdf88f62b0 13718 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 13719 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
<> 128:9bcdf88f62b0 13720
<> 128:9bcdf88f62b0 13721 /****************** Bit definition for QUADSPI_ABR register ******************/
<> 128:9bcdf88f62b0 13722 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
<> 128:9bcdf88f62b0 13723 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 13724 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
<> 128:9bcdf88f62b0 13725
<> 128:9bcdf88f62b0 13726 /****************** Bit definition for QUADSPI_DR register *******************/
<> 128:9bcdf88f62b0 13727 #define QUADSPI_DR_DATA_Pos (0U)
<> 128:9bcdf88f62b0 13728 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 13729 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
<> 128:9bcdf88f62b0 13730
<> 128:9bcdf88f62b0 13731 /****************** Bit definition for QUADSPI_PSMKR register ****************/
<> 128:9bcdf88f62b0 13732 #define QUADSPI_PSMKR_MASK_Pos (0U)
<> 128:9bcdf88f62b0 13733 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 13734 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
<> 128:9bcdf88f62b0 13735
<> 128:9bcdf88f62b0 13736 /****************** Bit definition for QUADSPI_PSMAR register ****************/
<> 128:9bcdf88f62b0 13737 #define QUADSPI_PSMAR_MATCH_Pos (0U)
<> 128:9bcdf88f62b0 13738 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 13739 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
<> 128:9bcdf88f62b0 13740
<> 128:9bcdf88f62b0 13741 /****************** Bit definition for QUADSPI_PIR register *****************/
<> 128:9bcdf88f62b0 13742 #define QUADSPI_PIR_INTERVAL_Pos (0U)
<> 128:9bcdf88f62b0 13743 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 13744 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
<> 128:9bcdf88f62b0 13745
<> 128:9bcdf88f62b0 13746 /****************** Bit definition for QUADSPI_LPTR register *****************/
<> 128:9bcdf88f62b0 13747 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
<> 128:9bcdf88f62b0 13748 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 13749 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
<> 128:9bcdf88f62b0 13750
<> 128:9bcdf88f62b0 13751 /******************************************************************************/
<> 128:9bcdf88f62b0 13752 /* */
<> 128:9bcdf88f62b0 13753 /* SYSCFG */
<> 128:9bcdf88f62b0 13754 /* */
<> 128:9bcdf88f62b0 13755 /******************************************************************************/
<> 128:9bcdf88f62b0 13756 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
<> 128:9bcdf88f62b0 13757 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
<> 128:9bcdf88f62b0 13758 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
<> 128:9bcdf88f62b0 13759 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
<> 128:9bcdf88f62b0 13760 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 13761 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 13762 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 13763
<> 128:9bcdf88f62b0 13764 #define SYSCFG_MEMRMP_FB_MODE_Pos (8U)
<> 128:9bcdf88f62b0 13765 #define SYSCFG_MEMRMP_FB_MODE_Msk (0x1U << SYSCFG_MEMRMP_FB_MODE_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 13766 #define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk /*!< Flash Bank mode selection */
<> 128:9bcdf88f62b0 13767
<> 128:9bcdf88f62b0 13768 /****************** Bit definition for SYSCFG_CFGR1 register ******************/
<> 128:9bcdf88f62b0 13769 #define SYSCFG_CFGR1_FWDIS_Pos (0U)
<> 128:9bcdf88f62b0 13770 #define SYSCFG_CFGR1_FWDIS_Msk (0x1U << SYSCFG_CFGR1_FWDIS_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 13771 #define SYSCFG_CFGR1_FWDIS SYSCFG_CFGR1_FWDIS_Msk /*!< FIREWALL access enable*/
<> 128:9bcdf88f62b0 13772 #define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
<> 128:9bcdf88f62b0 13773 #define SYSCFG_CFGR1_BOOSTEN_Msk (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 13774 #define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
<> 128:9bcdf88f62b0 13775 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
<> 128:9bcdf88f62b0 13776 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 13777 #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
<> 128:9bcdf88f62b0 13778 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
<> 128:9bcdf88f62b0 13779 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 13780 #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
<> 128:9bcdf88f62b0 13781 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
<> 128:9bcdf88f62b0 13782 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 13783 #define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
<> 128:9bcdf88f62b0 13784 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
<> 128:9bcdf88f62b0 13785 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 13786 #define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
<> 128:9bcdf88f62b0 13787 #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
<> 128:9bcdf88f62b0 13788 #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 13789 #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
<> 128:9bcdf88f62b0 13790 #define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
<> 128:9bcdf88f62b0 13791 #define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 13792 #define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
<> 128:9bcdf88f62b0 13793 #define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
<> 128:9bcdf88f62b0 13794 #define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 13795 #define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
<> 128:9bcdf88f62b0 13796 #define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */
<> 128:9bcdf88f62b0 13797 #define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */
<> 128:9bcdf88f62b0 13798 #define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */
<> 128:9bcdf88f62b0 13799 #define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */
<> 128:9bcdf88f62b0 13800 #define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */
<> 128:9bcdf88f62b0 13801 #define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
<> 128:9bcdf88f62b0 13802
<> 128:9bcdf88f62b0 13803 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
<> 128:9bcdf88f62b0 13804 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
<> 128:9bcdf88f62b0 13805 #define SYSCFG_EXTICR1_EXTI0_Msk (0x7U << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */
<> 128:9bcdf88f62b0 13806 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
<> 128:9bcdf88f62b0 13807 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
<> 128:9bcdf88f62b0 13808 #define SYSCFG_EXTICR1_EXTI1_Msk (0x7U << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x00000070 */
<> 128:9bcdf88f62b0 13809 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
<> 128:9bcdf88f62b0 13810 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
<> 128:9bcdf88f62b0 13811 #define SYSCFG_EXTICR1_EXTI2_Msk (0x7U << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000700 */
<> 128:9bcdf88f62b0 13812 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
<> 128:9bcdf88f62b0 13813 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
<> 128:9bcdf88f62b0 13814 #define SYSCFG_EXTICR1_EXTI3_Msk (0x7U << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x00007000 */
<> 128:9bcdf88f62b0 13815 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
<> 128:9bcdf88f62b0 13816
<> 128:9bcdf88f62b0 13817 /**
<> 128:9bcdf88f62b0 13818 * @brief EXTI0 configuration
<> 128:9bcdf88f62b0 13819 */
<> 128:9bcdf88f62b0 13820 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */
<> 128:9bcdf88f62b0 13821 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
<> 128:9bcdf88f62b0 13822 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
<> 128:9bcdf88f62b0 13823 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
<> 128:9bcdf88f62b0 13824 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
<> 128:9bcdf88f62b0 13825 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
<> 128:9bcdf88f62b0 13826 #define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
<> 128:9bcdf88f62b0 13827 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
<> 128:9bcdf88f62b0 13828
<> 128:9bcdf88f62b0 13829 /**
<> 128:9bcdf88f62b0 13830 * @brief EXTI1 configuration
<> 128:9bcdf88f62b0 13831 */
<> 128:9bcdf88f62b0 13832 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */
<> 128:9bcdf88f62b0 13833 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
<> 128:9bcdf88f62b0 13834 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
<> 128:9bcdf88f62b0 13835 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
<> 128:9bcdf88f62b0 13836 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
<> 128:9bcdf88f62b0 13837 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
<> 128:9bcdf88f62b0 13838 #define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
<> 128:9bcdf88f62b0 13839 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
<> 128:9bcdf88f62b0 13840
<> 128:9bcdf88f62b0 13841 /**
<> 128:9bcdf88f62b0 13842 * @brief EXTI2 configuration
<> 128:9bcdf88f62b0 13843 */
<> 128:9bcdf88f62b0 13844 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */
<> 128:9bcdf88f62b0 13845 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
<> 128:9bcdf88f62b0 13846 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
<> 128:9bcdf88f62b0 13847 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
<> 128:9bcdf88f62b0 13848 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
<> 128:9bcdf88f62b0 13849 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
<> 128:9bcdf88f62b0 13850 #define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
<> 128:9bcdf88f62b0 13851
<> 128:9bcdf88f62b0 13852 /**
<> 128:9bcdf88f62b0 13853 * @brief EXTI3 configuration
<> 128:9bcdf88f62b0 13854 */
<> 128:9bcdf88f62b0 13855 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */
<> 128:9bcdf88f62b0 13856 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
<> 128:9bcdf88f62b0 13857 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
<> 128:9bcdf88f62b0 13858 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
<> 128:9bcdf88f62b0 13859 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
<> 128:9bcdf88f62b0 13860 #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
<> 128:9bcdf88f62b0 13861 #define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
<> 128:9bcdf88f62b0 13862
<> 128:9bcdf88f62b0 13863 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
<> 128:9bcdf88f62b0 13864 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
<> 128:9bcdf88f62b0 13865 #define SYSCFG_EXTICR2_EXTI4_Msk (0x7U << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */
<> 128:9bcdf88f62b0 13866 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
<> 128:9bcdf88f62b0 13867 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
<> 128:9bcdf88f62b0 13868 #define SYSCFG_EXTICR2_EXTI5_Msk (0x7U << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x00000070 */
<> 128:9bcdf88f62b0 13869 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
<> 128:9bcdf88f62b0 13870 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
<> 128:9bcdf88f62b0 13871 #define SYSCFG_EXTICR2_EXTI6_Msk (0x7U << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000700 */
<> 128:9bcdf88f62b0 13872 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
<> 128:9bcdf88f62b0 13873 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
<> 128:9bcdf88f62b0 13874 #define SYSCFG_EXTICR2_EXTI7_Msk (0x7U << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x00007000 */
<> 128:9bcdf88f62b0 13875 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
<> 128:9bcdf88f62b0 13876 /**
<> 128:9bcdf88f62b0 13877 * @brief EXTI4 configuration
<> 128:9bcdf88f62b0 13878 */
<> 128:9bcdf88f62b0 13879 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */
<> 128:9bcdf88f62b0 13880 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
<> 128:9bcdf88f62b0 13881 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
<> 128:9bcdf88f62b0 13882 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
<> 128:9bcdf88f62b0 13883 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
<> 128:9bcdf88f62b0 13884 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
<> 128:9bcdf88f62b0 13885 #define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
<> 128:9bcdf88f62b0 13886
<> 128:9bcdf88f62b0 13887 /**
<> 128:9bcdf88f62b0 13888 * @brief EXTI5 configuration
<> 128:9bcdf88f62b0 13889 */
<> 128:9bcdf88f62b0 13890 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */
<> 128:9bcdf88f62b0 13891 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
<> 128:9bcdf88f62b0 13892 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
<> 128:9bcdf88f62b0 13893 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
<> 128:9bcdf88f62b0 13894 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
<> 128:9bcdf88f62b0 13895 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
<> 128:9bcdf88f62b0 13896 #define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
<> 128:9bcdf88f62b0 13897
<> 128:9bcdf88f62b0 13898 /**
<> 128:9bcdf88f62b0 13899 * @brief EXTI6 configuration
<> 128:9bcdf88f62b0 13900 */
<> 128:9bcdf88f62b0 13901 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */
<> 128:9bcdf88f62b0 13902 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
<> 128:9bcdf88f62b0 13903 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
<> 128:9bcdf88f62b0 13904 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
<> 128:9bcdf88f62b0 13905 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
<> 128:9bcdf88f62b0 13906 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
<> 128:9bcdf88f62b0 13907 #define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
<> 128:9bcdf88f62b0 13908
<> 128:9bcdf88f62b0 13909 /**
<> 128:9bcdf88f62b0 13910 * @brief EXTI7 configuration
<> 128:9bcdf88f62b0 13911 */
<> 128:9bcdf88f62b0 13912 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */
<> 128:9bcdf88f62b0 13913 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
<> 128:9bcdf88f62b0 13914 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
<> 128:9bcdf88f62b0 13915 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
<> 128:9bcdf88f62b0 13916 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
<> 128:9bcdf88f62b0 13917 #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
<> 128:9bcdf88f62b0 13918 #define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
<> 128:9bcdf88f62b0 13919
<> 128:9bcdf88f62b0 13920 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
<> 128:9bcdf88f62b0 13921 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
<> 128:9bcdf88f62b0 13922 #define SYSCFG_EXTICR3_EXTI8_Msk (0x7U << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */
<> 128:9bcdf88f62b0 13923 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
<> 128:9bcdf88f62b0 13924 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
<> 128:9bcdf88f62b0 13925 #define SYSCFG_EXTICR3_EXTI9_Msk (0x7U << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x00000070 */
<> 128:9bcdf88f62b0 13926 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
<> 128:9bcdf88f62b0 13927 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
<> 128:9bcdf88f62b0 13928 #define SYSCFG_EXTICR3_EXTI10_Msk (0x7U << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000700 */
<> 128:9bcdf88f62b0 13929 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
<> 128:9bcdf88f62b0 13930 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
<> 128:9bcdf88f62b0 13931 #define SYSCFG_EXTICR3_EXTI11_Msk (0x7U << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x00007000 */
<> 128:9bcdf88f62b0 13932 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
<> 128:9bcdf88f62b0 13933
<> 128:9bcdf88f62b0 13934 /**
<> 128:9bcdf88f62b0 13935 * @brief EXTI8 configuration
<> 128:9bcdf88f62b0 13936 */
<> 128:9bcdf88f62b0 13937 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */
<> 128:9bcdf88f62b0 13938 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
<> 128:9bcdf88f62b0 13939 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
<> 128:9bcdf88f62b0 13940 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
<> 128:9bcdf88f62b0 13941 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
<> 128:9bcdf88f62b0 13942 #define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
<> 128:9bcdf88f62b0 13943 #define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
<> 128:9bcdf88f62b0 13944
<> 128:9bcdf88f62b0 13945 /**
<> 128:9bcdf88f62b0 13946 * @brief EXTI9 configuration
<> 128:9bcdf88f62b0 13947 */
<> 128:9bcdf88f62b0 13948 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */
<> 128:9bcdf88f62b0 13949 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
<> 128:9bcdf88f62b0 13950 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
<> 128:9bcdf88f62b0 13951 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
<> 128:9bcdf88f62b0 13952 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
<> 128:9bcdf88f62b0 13953 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
<> 128:9bcdf88f62b0 13954 #define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
<> 128:9bcdf88f62b0 13955
<> 128:9bcdf88f62b0 13956 /**
<> 128:9bcdf88f62b0 13957 * @brief EXTI10 configuration
<> 128:9bcdf88f62b0 13958 */
<> 128:9bcdf88f62b0 13959 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */
<> 128:9bcdf88f62b0 13960 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
<> 128:9bcdf88f62b0 13961 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
<> 128:9bcdf88f62b0 13962 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
<> 128:9bcdf88f62b0 13963 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
<> 128:9bcdf88f62b0 13964 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
<> 128:9bcdf88f62b0 13965 #define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
<> 128:9bcdf88f62b0 13966
<> 128:9bcdf88f62b0 13967 /**
<> 128:9bcdf88f62b0 13968 * @brief EXTI11 configuration
<> 128:9bcdf88f62b0 13969 */
<> 128:9bcdf88f62b0 13970 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */
<> 128:9bcdf88f62b0 13971 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
<> 128:9bcdf88f62b0 13972 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
<> 128:9bcdf88f62b0 13973 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
<> 128:9bcdf88f62b0 13974 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
<> 128:9bcdf88f62b0 13975 #define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
<> 128:9bcdf88f62b0 13976 #define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
<> 128:9bcdf88f62b0 13977
<> 128:9bcdf88f62b0 13978 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
<> 128:9bcdf88f62b0 13979 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
<> 128:9bcdf88f62b0 13980 #define SYSCFG_EXTICR4_EXTI12_Msk (0x7U << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
<> 128:9bcdf88f62b0 13981 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
<> 128:9bcdf88f62b0 13982 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
<> 128:9bcdf88f62b0 13983 #define SYSCFG_EXTICR4_EXTI13_Msk (0x7U << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
<> 128:9bcdf88f62b0 13984 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
<> 128:9bcdf88f62b0 13985 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
<> 128:9bcdf88f62b0 13986 #define SYSCFG_EXTICR4_EXTI14_Msk (0x7U << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
<> 128:9bcdf88f62b0 13987 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
<> 128:9bcdf88f62b0 13988 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
<> 128:9bcdf88f62b0 13989 #define SYSCFG_EXTICR4_EXTI15_Msk (0x7U << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
<> 128:9bcdf88f62b0 13990 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
<> 128:9bcdf88f62b0 13991
<> 128:9bcdf88f62b0 13992 /**
<> 128:9bcdf88f62b0 13993 * @brief EXTI12 configuration
<> 128:9bcdf88f62b0 13994 */
<> 128:9bcdf88f62b0 13995 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */
<> 128:9bcdf88f62b0 13996 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
<> 128:9bcdf88f62b0 13997 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
<> 128:9bcdf88f62b0 13998 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
<> 128:9bcdf88f62b0 13999 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
<> 128:9bcdf88f62b0 14000 #define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
<> 128:9bcdf88f62b0 14001 #define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
<> 128:9bcdf88f62b0 14002
<> 128:9bcdf88f62b0 14003 /**
<> 128:9bcdf88f62b0 14004 * @brief EXTI13 configuration
<> 128:9bcdf88f62b0 14005 */
<> 128:9bcdf88f62b0 14006 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */
<> 128:9bcdf88f62b0 14007 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
<> 128:9bcdf88f62b0 14008 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
<> 128:9bcdf88f62b0 14009 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
<> 128:9bcdf88f62b0 14010 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
<> 128:9bcdf88f62b0 14011 #define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
<> 128:9bcdf88f62b0 14012 #define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
<> 128:9bcdf88f62b0 14013
<> 128:9bcdf88f62b0 14014 /**
<> 128:9bcdf88f62b0 14015 * @brief EXTI14 configuration
<> 128:9bcdf88f62b0 14016 */
<> 128:9bcdf88f62b0 14017 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */
<> 128:9bcdf88f62b0 14018 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
<> 128:9bcdf88f62b0 14019 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
<> 128:9bcdf88f62b0 14020 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
<> 128:9bcdf88f62b0 14021 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
<> 128:9bcdf88f62b0 14022 #define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
<> 128:9bcdf88f62b0 14023 #define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
<> 128:9bcdf88f62b0 14024
<> 128:9bcdf88f62b0 14025 /**
<> 128:9bcdf88f62b0 14026 * @brief EXTI15 configuration
<> 128:9bcdf88f62b0 14027 */
<> 128:9bcdf88f62b0 14028 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */
<> 128:9bcdf88f62b0 14029 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
<> 128:9bcdf88f62b0 14030 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
<> 128:9bcdf88f62b0 14031 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
<> 128:9bcdf88f62b0 14032 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
<> 128:9bcdf88f62b0 14033 #define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
<> 128:9bcdf88f62b0 14034 #define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
<> 128:9bcdf88f62b0 14035
<> 128:9bcdf88f62b0 14036 /****************** Bit definition for SYSCFG_SCSR register ****************/
<> 128:9bcdf88f62b0 14037 #define SYSCFG_SCSR_SRAM2ER_Pos (0U)
<> 128:9bcdf88f62b0 14038 #define SYSCFG_SCSR_SRAM2ER_Msk (0x1U << SYSCFG_SCSR_SRAM2ER_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 14039 #define SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk /*!< SRAM2 Erase Request */
<> 128:9bcdf88f62b0 14040 #define SYSCFG_SCSR_SRAM2BSY_Pos (1U)
<> 128:9bcdf88f62b0 14041 #define SYSCFG_SCSR_SRAM2BSY_Msk (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 14042 #define SYSCFG_SCSR_SRAM2BSY SYSCFG_SCSR_SRAM2BSY_Msk /*!< SRAM2 Erase Ongoing */
<> 128:9bcdf88f62b0 14043
<> 128:9bcdf88f62b0 14044 /****************** Bit definition for SYSCFG_CFGR2 register ****************/
<> 128:9bcdf88f62b0 14045 #define SYSCFG_CFGR2_CLL_Pos (0U)
<> 128:9bcdf88f62b0 14046 #define SYSCFG_CFGR2_CLL_Msk (0x1U << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 14047 #define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
<> 128:9bcdf88f62b0 14048 #define SYSCFG_CFGR2_SPL_Pos (1U)
<> 128:9bcdf88f62b0 14049 #define SYSCFG_CFGR2_SPL_Msk (0x1U << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 14050 #define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
<> 128:9bcdf88f62b0 14051 #define SYSCFG_CFGR2_PVDL_Pos (2U)
<> 128:9bcdf88f62b0 14052 #define SYSCFG_CFGR2_PVDL_Msk (0x1U << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14053 #define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
<> 128:9bcdf88f62b0 14054 #define SYSCFG_CFGR2_ECCL_Pos (3U)
<> 128:9bcdf88f62b0 14055 #define SYSCFG_CFGR2_ECCL_Msk (0x1U << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 14056 #define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
<> 128:9bcdf88f62b0 14057 #define SYSCFG_CFGR2_SPF_Pos (8U)
<> 128:9bcdf88f62b0 14058 #define SYSCFG_CFGR2_SPF_Msk (0x1U << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 14059 #define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
<> 128:9bcdf88f62b0 14060
<> 128:9bcdf88f62b0 14061 /****************** Bit definition for SYSCFG_SWPR register ****************/
<> 128:9bcdf88f62b0 14062 #define SYSCFG_SWPR_PAGE0_Pos (0U)
<> 128:9bcdf88f62b0 14063 #define SYSCFG_SWPR_PAGE0_Msk (0x1U << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 14064 #define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 */
<> 128:9bcdf88f62b0 14065 #define SYSCFG_SWPR_PAGE1_Pos (1U)
<> 128:9bcdf88f62b0 14066 #define SYSCFG_SWPR_PAGE1_Msk (0x1U << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 14067 #define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 */
<> 128:9bcdf88f62b0 14068 #define SYSCFG_SWPR_PAGE2_Pos (2U)
<> 128:9bcdf88f62b0 14069 #define SYSCFG_SWPR_PAGE2_Msk (0x1U << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14070 #define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 */
<> 128:9bcdf88f62b0 14071 #define SYSCFG_SWPR_PAGE3_Pos (3U)
<> 128:9bcdf88f62b0 14072 #define SYSCFG_SWPR_PAGE3_Msk (0x1U << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 14073 #define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 */
<> 128:9bcdf88f62b0 14074 #define SYSCFG_SWPR_PAGE4_Pos (4U)
<> 128:9bcdf88f62b0 14075 #define SYSCFG_SWPR_PAGE4_Msk (0x1U << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 14076 #define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 */
<> 128:9bcdf88f62b0 14077 #define SYSCFG_SWPR_PAGE5_Pos (5U)
<> 128:9bcdf88f62b0 14078 #define SYSCFG_SWPR_PAGE5_Msk (0x1U << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 14079 #define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 */
<> 128:9bcdf88f62b0 14080 #define SYSCFG_SWPR_PAGE6_Pos (6U)
<> 128:9bcdf88f62b0 14081 #define SYSCFG_SWPR_PAGE6_Msk (0x1U << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 14082 #define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 */
<> 128:9bcdf88f62b0 14083 #define SYSCFG_SWPR_PAGE7_Pos (7U)
<> 128:9bcdf88f62b0 14084 #define SYSCFG_SWPR_PAGE7_Msk (0x1U << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 14085 #define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 */
<> 128:9bcdf88f62b0 14086 #define SYSCFG_SWPR_PAGE8_Pos (8U)
<> 128:9bcdf88f62b0 14087 #define SYSCFG_SWPR_PAGE8_Msk (0x1U << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 14088 #define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 */
<> 128:9bcdf88f62b0 14089 #define SYSCFG_SWPR_PAGE9_Pos (9U)
<> 128:9bcdf88f62b0 14090 #define SYSCFG_SWPR_PAGE9_Msk (0x1U << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 14091 #define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 */
<> 128:9bcdf88f62b0 14092 #define SYSCFG_SWPR_PAGE10_Pos (10U)
<> 128:9bcdf88f62b0 14093 #define SYSCFG_SWPR_PAGE10_Msk (0x1U << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 14094 #define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10*/
<> 128:9bcdf88f62b0 14095 #define SYSCFG_SWPR_PAGE11_Pos (11U)
<> 128:9bcdf88f62b0 14096 #define SYSCFG_SWPR_PAGE11_Msk (0x1U << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 14097 #define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11*/
<> 128:9bcdf88f62b0 14098 #define SYSCFG_SWPR_PAGE12_Pos (12U)
<> 128:9bcdf88f62b0 14099 #define SYSCFG_SWPR_PAGE12_Msk (0x1U << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 14100 #define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12*/
<> 128:9bcdf88f62b0 14101 #define SYSCFG_SWPR_PAGE13_Pos (13U)
<> 128:9bcdf88f62b0 14102 #define SYSCFG_SWPR_PAGE13_Msk (0x1U << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 14103 #define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13*/
<> 128:9bcdf88f62b0 14104 #define SYSCFG_SWPR_PAGE14_Pos (14U)
<> 128:9bcdf88f62b0 14105 #define SYSCFG_SWPR_PAGE14_Msk (0x1U << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 14106 #define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14*/
<> 128:9bcdf88f62b0 14107 #define SYSCFG_SWPR_PAGE15_Pos (15U)
<> 128:9bcdf88f62b0 14108 #define SYSCFG_SWPR_PAGE15_Msk (0x1U << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 14109 #define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15*/
<> 128:9bcdf88f62b0 14110 #define SYSCFG_SWPR_PAGE16_Pos (16U)
<> 128:9bcdf88f62b0 14111 #define SYSCFG_SWPR_PAGE16_Msk (0x1U << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 14112 #define SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk /*!< SRAM2 Write protection page 16*/
<> 128:9bcdf88f62b0 14113 #define SYSCFG_SWPR_PAGE17_Pos (17U)
<> 128:9bcdf88f62b0 14114 #define SYSCFG_SWPR_PAGE17_Msk (0x1U << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 14115 #define SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk /*!< SRAM2 Write protection page 17*/
<> 128:9bcdf88f62b0 14116 #define SYSCFG_SWPR_PAGE18_Pos (18U)
<> 128:9bcdf88f62b0 14117 #define SYSCFG_SWPR_PAGE18_Msk (0x1U << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 14118 #define SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk /*!< SRAM2 Write protection page 18*/
<> 128:9bcdf88f62b0 14119 #define SYSCFG_SWPR_PAGE19_Pos (19U)
<> 128:9bcdf88f62b0 14120 #define SYSCFG_SWPR_PAGE19_Msk (0x1U << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 14121 #define SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk /*!< SRAM2 Write protection page 19*/
<> 128:9bcdf88f62b0 14122 #define SYSCFG_SWPR_PAGE20_Pos (20U)
<> 128:9bcdf88f62b0 14123 #define SYSCFG_SWPR_PAGE20_Msk (0x1U << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 14124 #define SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk /*!< SRAM2 Write protection page 20*/
<> 128:9bcdf88f62b0 14125 #define SYSCFG_SWPR_PAGE21_Pos (21U)
<> 128:9bcdf88f62b0 14126 #define SYSCFG_SWPR_PAGE21_Msk (0x1U << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 14127 #define SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk /*!< SRAM2 Write protection page 21*/
<> 128:9bcdf88f62b0 14128 #define SYSCFG_SWPR_PAGE22_Pos (22U)
<> 128:9bcdf88f62b0 14129 #define SYSCFG_SWPR_PAGE22_Msk (0x1U << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 14130 #define SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk /*!< SRAM2 Write protection page 22*/
<> 128:9bcdf88f62b0 14131 #define SYSCFG_SWPR_PAGE23_Pos (23U)
<> 128:9bcdf88f62b0 14132 #define SYSCFG_SWPR_PAGE23_Msk (0x1U << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 14133 #define SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk /*!< SRAM2 Write protection page 23*/
<> 128:9bcdf88f62b0 14134 #define SYSCFG_SWPR_PAGE24_Pos (24U)
<> 128:9bcdf88f62b0 14135 #define SYSCFG_SWPR_PAGE24_Msk (0x1U << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 14136 #define SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk /*!< SRAM2 Write protection page 24*/
<> 128:9bcdf88f62b0 14137 #define SYSCFG_SWPR_PAGE25_Pos (25U)
<> 128:9bcdf88f62b0 14138 #define SYSCFG_SWPR_PAGE25_Msk (0x1U << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 14139 #define SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk /*!< SRAM2 Write protection page 25*/
<> 128:9bcdf88f62b0 14140 #define SYSCFG_SWPR_PAGE26_Pos (26U)
<> 128:9bcdf88f62b0 14141 #define SYSCFG_SWPR_PAGE26_Msk (0x1U << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 14142 #define SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk /*!< SRAM2 Write protection page 26*/
<> 128:9bcdf88f62b0 14143 #define SYSCFG_SWPR_PAGE27_Pos (27U)
<> 128:9bcdf88f62b0 14144 #define SYSCFG_SWPR_PAGE27_Msk (0x1U << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 14145 #define SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk /*!< SRAM2 Write protection page 27*/
<> 128:9bcdf88f62b0 14146 #define SYSCFG_SWPR_PAGE28_Pos (28U)
<> 128:9bcdf88f62b0 14147 #define SYSCFG_SWPR_PAGE28_Msk (0x1U << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 14148 #define SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk /*!< SRAM2 Write protection page 28*/
<> 128:9bcdf88f62b0 14149 #define SYSCFG_SWPR_PAGE29_Pos (29U)
<> 128:9bcdf88f62b0 14150 #define SYSCFG_SWPR_PAGE29_Msk (0x1U << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 14151 #define SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk /*!< SRAM2 Write protection page 29*/
<> 128:9bcdf88f62b0 14152 #define SYSCFG_SWPR_PAGE30_Pos (30U)
<> 128:9bcdf88f62b0 14153 #define SYSCFG_SWPR_PAGE30_Msk (0x1U << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 14154 #define SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk /*!< SRAM2 Write protection page 30*/
<> 128:9bcdf88f62b0 14155 #define SYSCFG_SWPR_PAGE31_Pos (31U)
<> 128:9bcdf88f62b0 14156 #define SYSCFG_SWPR_PAGE31_Msk (0x1U << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 14157 #define SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk /*!< SRAM2 Write protection page 31*/
<> 128:9bcdf88f62b0 14158
<> 128:9bcdf88f62b0 14159 /****************** Bit definition for SYSCFG_SKR register ****************/
<> 128:9bcdf88f62b0 14160 #define SYSCFG_SKR_KEY_Pos (0U)
<> 128:9bcdf88f62b0 14161 #define SYSCFG_SKR_KEY_Msk (0xFFU << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 14162 #define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< SRAM2 write protection key for software erase */
<> 128:9bcdf88f62b0 14163
<> 128:9bcdf88f62b0 14164
<> 128:9bcdf88f62b0 14165
<> 128:9bcdf88f62b0 14166
<> 128:9bcdf88f62b0 14167 /******************************************************************************/
<> 128:9bcdf88f62b0 14168 /* */
<> 128:9bcdf88f62b0 14169 /* TIM */
<> 128:9bcdf88f62b0 14170 /* */
<> 128:9bcdf88f62b0 14171 /******************************************************************************/
<> 128:9bcdf88f62b0 14172 /******************* Bit definition for TIM_CR1 register ********************/
<> 128:9bcdf88f62b0 14173 #define TIM_CR1_CEN_Pos (0U)
<> 128:9bcdf88f62b0 14174 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 14175 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
<> 128:9bcdf88f62b0 14176 #define TIM_CR1_UDIS_Pos (1U)
<> 128:9bcdf88f62b0 14177 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 14178 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
<> 128:9bcdf88f62b0 14179 #define TIM_CR1_URS_Pos (2U)
<> 128:9bcdf88f62b0 14180 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14181 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
<> 128:9bcdf88f62b0 14182 #define TIM_CR1_OPM_Pos (3U)
<> 128:9bcdf88f62b0 14183 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 14184 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
<> 128:9bcdf88f62b0 14185 #define TIM_CR1_DIR_Pos (4U)
<> 128:9bcdf88f62b0 14186 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 14187 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
<> 128:9bcdf88f62b0 14188
<> 128:9bcdf88f62b0 14189 #define TIM_CR1_CMS_Pos (5U)
<> 128:9bcdf88f62b0 14190 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
<> 128:9bcdf88f62b0 14191 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
<> 128:9bcdf88f62b0 14192 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 14193 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 14194
<> 128:9bcdf88f62b0 14195 #define TIM_CR1_ARPE_Pos (7U)
<> 128:9bcdf88f62b0 14196 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 14197 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
<> 128:9bcdf88f62b0 14198
<> 128:9bcdf88f62b0 14199 #define TIM_CR1_CKD_Pos (8U)
<> 128:9bcdf88f62b0 14200 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
<> 128:9bcdf88f62b0 14201 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
<> 128:9bcdf88f62b0 14202 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 14203 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 14204
<> 128:9bcdf88f62b0 14205 #define TIM_CR1_UIFREMAP_Pos (11U)
<> 128:9bcdf88f62b0 14206 #define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 14207 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
<> 128:9bcdf88f62b0 14208
<> 128:9bcdf88f62b0 14209 /******************* Bit definition for TIM_CR2 register ********************/
<> 128:9bcdf88f62b0 14210 #define TIM_CR2_CCPC_Pos (0U)
<> 128:9bcdf88f62b0 14211 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 14212 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
<> 128:9bcdf88f62b0 14213 #define TIM_CR2_CCUS_Pos (2U)
<> 128:9bcdf88f62b0 14214 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14215 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
<> 128:9bcdf88f62b0 14216 #define TIM_CR2_CCDS_Pos (3U)
<> 128:9bcdf88f62b0 14217 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 14218 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
<> 128:9bcdf88f62b0 14219
<> 128:9bcdf88f62b0 14220 #define TIM_CR2_MMS_Pos (4U)
<> 128:9bcdf88f62b0 14221 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
<> 128:9bcdf88f62b0 14222 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
<> 128:9bcdf88f62b0 14223 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 14224 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 14225 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 14226
<> 128:9bcdf88f62b0 14227 #define TIM_CR2_TI1S_Pos (7U)
<> 128:9bcdf88f62b0 14228 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 14229 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
<> 128:9bcdf88f62b0 14230 #define TIM_CR2_OIS1_Pos (8U)
<> 128:9bcdf88f62b0 14231 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 14232 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
<> 128:9bcdf88f62b0 14233 #define TIM_CR2_OIS1N_Pos (9U)
<> 128:9bcdf88f62b0 14234 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 14235 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
<> 128:9bcdf88f62b0 14236 #define TIM_CR2_OIS2_Pos (10U)
<> 128:9bcdf88f62b0 14237 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 14238 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
<> 128:9bcdf88f62b0 14239 #define TIM_CR2_OIS2N_Pos (11U)
<> 128:9bcdf88f62b0 14240 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 14241 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
<> 128:9bcdf88f62b0 14242 #define TIM_CR2_OIS3_Pos (12U)
<> 128:9bcdf88f62b0 14243 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 14244 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
<> 128:9bcdf88f62b0 14245 #define TIM_CR2_OIS3N_Pos (13U)
<> 128:9bcdf88f62b0 14246 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 14247 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
<> 128:9bcdf88f62b0 14248 #define TIM_CR2_OIS4_Pos (14U)
<> 128:9bcdf88f62b0 14249 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 14250 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
<> 128:9bcdf88f62b0 14251 #define TIM_CR2_OIS5_Pos (16U)
<> 128:9bcdf88f62b0 14252 #define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 14253 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
<> 128:9bcdf88f62b0 14254 #define TIM_CR2_OIS6_Pos (18U)
<> 128:9bcdf88f62b0 14255 #define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 14256 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
<> 128:9bcdf88f62b0 14257
<> 128:9bcdf88f62b0 14258 #define TIM_CR2_MMS2_Pos (20U)
<> 128:9bcdf88f62b0 14259 #define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
<> 128:9bcdf88f62b0 14260 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
<> 128:9bcdf88f62b0 14261 #define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 14262 #define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 14263 #define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 14264 #define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 14265
<> 128:9bcdf88f62b0 14266 /******************* Bit definition for TIM_SMCR register *******************/
<> 128:9bcdf88f62b0 14267 #define TIM_SMCR_SMS_Pos (0U)
<> 128:9bcdf88f62b0 14268 #define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
<> 128:9bcdf88f62b0 14269 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
<> 128:9bcdf88f62b0 14270 #define TIM_SMCR_SMS_0 (0x00001U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 14271 #define TIM_SMCR_SMS_1 (0x00002U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 14272 #define TIM_SMCR_SMS_2 (0x00004U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14273 #define TIM_SMCR_SMS_3 (0x10000U << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 14274
<> 128:9bcdf88f62b0 14275 #define TIM_SMCR_OCCS_Pos (3U)
<> 128:9bcdf88f62b0 14276 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 14277 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
<> 128:9bcdf88f62b0 14278
<> 128:9bcdf88f62b0 14279 #define TIM_SMCR_TS_Pos (4U)
<> 128:9bcdf88f62b0 14280 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
<> 128:9bcdf88f62b0 14281 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
<> 128:9bcdf88f62b0 14282 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 14283 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 14284 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 14285
<> 128:9bcdf88f62b0 14286 #define TIM_SMCR_MSM_Pos (7U)
<> 128:9bcdf88f62b0 14287 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 14288 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
<> 128:9bcdf88f62b0 14289
<> 128:9bcdf88f62b0 14290 #define TIM_SMCR_ETF_Pos (8U)
<> 128:9bcdf88f62b0 14291 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
<> 128:9bcdf88f62b0 14292 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
<> 128:9bcdf88f62b0 14293 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 14294 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 14295 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 14296 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 14297
<> 128:9bcdf88f62b0 14298 #define TIM_SMCR_ETPS_Pos (12U)
<> 128:9bcdf88f62b0 14299 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
<> 128:9bcdf88f62b0 14300 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
<> 128:9bcdf88f62b0 14301 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 14302 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 14303
<> 128:9bcdf88f62b0 14304 #define TIM_SMCR_ECE_Pos (14U)
<> 128:9bcdf88f62b0 14305 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 14306 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
<> 128:9bcdf88f62b0 14307 #define TIM_SMCR_ETP_Pos (15U)
<> 128:9bcdf88f62b0 14308 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 14309 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
<> 128:9bcdf88f62b0 14310
<> 128:9bcdf88f62b0 14311 /******************* Bit definition for TIM_DIER register *******************/
<> 128:9bcdf88f62b0 14312 #define TIM_DIER_UIE_Pos (0U)
<> 128:9bcdf88f62b0 14313 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 14314 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
<> 128:9bcdf88f62b0 14315 #define TIM_DIER_CC1IE_Pos (1U)
<> 128:9bcdf88f62b0 14316 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 14317 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
<> 128:9bcdf88f62b0 14318 #define TIM_DIER_CC2IE_Pos (2U)
<> 128:9bcdf88f62b0 14319 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14320 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
<> 128:9bcdf88f62b0 14321 #define TIM_DIER_CC3IE_Pos (3U)
<> 128:9bcdf88f62b0 14322 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 14323 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
<> 128:9bcdf88f62b0 14324 #define TIM_DIER_CC4IE_Pos (4U)
<> 128:9bcdf88f62b0 14325 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 14326 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
<> 128:9bcdf88f62b0 14327 #define TIM_DIER_COMIE_Pos (5U)
<> 128:9bcdf88f62b0 14328 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 14329 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
<> 128:9bcdf88f62b0 14330 #define TIM_DIER_TIE_Pos (6U)
<> 128:9bcdf88f62b0 14331 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 14332 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
<> 128:9bcdf88f62b0 14333 #define TIM_DIER_BIE_Pos (7U)
<> 128:9bcdf88f62b0 14334 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 14335 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
<> 128:9bcdf88f62b0 14336 #define TIM_DIER_UDE_Pos (8U)
<> 128:9bcdf88f62b0 14337 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 14338 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
<> 128:9bcdf88f62b0 14339 #define TIM_DIER_CC1DE_Pos (9U)
<> 128:9bcdf88f62b0 14340 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 14341 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
<> 128:9bcdf88f62b0 14342 #define TIM_DIER_CC2DE_Pos (10U)
<> 128:9bcdf88f62b0 14343 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 14344 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
<> 128:9bcdf88f62b0 14345 #define TIM_DIER_CC3DE_Pos (11U)
<> 128:9bcdf88f62b0 14346 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 14347 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
<> 128:9bcdf88f62b0 14348 #define TIM_DIER_CC4DE_Pos (12U)
<> 128:9bcdf88f62b0 14349 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 14350 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
<> 128:9bcdf88f62b0 14351 #define TIM_DIER_COMDE_Pos (13U)
<> 128:9bcdf88f62b0 14352 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 14353 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
<> 128:9bcdf88f62b0 14354 #define TIM_DIER_TDE_Pos (14U)
<> 128:9bcdf88f62b0 14355 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 14356 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
<> 128:9bcdf88f62b0 14357
<> 128:9bcdf88f62b0 14358 /******************** Bit definition for TIM_SR register ********************/
<> 128:9bcdf88f62b0 14359 #define TIM_SR_UIF_Pos (0U)
<> 128:9bcdf88f62b0 14360 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 14361 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
<> 128:9bcdf88f62b0 14362 #define TIM_SR_CC1IF_Pos (1U)
<> 128:9bcdf88f62b0 14363 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 14364 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
<> 128:9bcdf88f62b0 14365 #define TIM_SR_CC2IF_Pos (2U)
<> 128:9bcdf88f62b0 14366 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14367 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
<> 128:9bcdf88f62b0 14368 #define TIM_SR_CC3IF_Pos (3U)
<> 128:9bcdf88f62b0 14369 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 14370 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
<> 128:9bcdf88f62b0 14371 #define TIM_SR_CC4IF_Pos (4U)
<> 128:9bcdf88f62b0 14372 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 14373 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
<> 128:9bcdf88f62b0 14374 #define TIM_SR_COMIF_Pos (5U)
<> 128:9bcdf88f62b0 14375 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 14376 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
<> 128:9bcdf88f62b0 14377 #define TIM_SR_TIF_Pos (6U)
<> 128:9bcdf88f62b0 14378 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 14379 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
<> 128:9bcdf88f62b0 14380 #define TIM_SR_BIF_Pos (7U)
<> 128:9bcdf88f62b0 14381 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 14382 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
<> 128:9bcdf88f62b0 14383 #define TIM_SR_B2IF_Pos (8U)
<> 128:9bcdf88f62b0 14384 #define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 14385 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
<> 128:9bcdf88f62b0 14386 #define TIM_SR_CC1OF_Pos (9U)
<> 128:9bcdf88f62b0 14387 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 14388 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
<> 128:9bcdf88f62b0 14389 #define TIM_SR_CC2OF_Pos (10U)
<> 128:9bcdf88f62b0 14390 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 14391 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
<> 128:9bcdf88f62b0 14392 #define TIM_SR_CC3OF_Pos (11U)
<> 128:9bcdf88f62b0 14393 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 14394 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
<> 128:9bcdf88f62b0 14395 #define TIM_SR_CC4OF_Pos (12U)
<> 128:9bcdf88f62b0 14396 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 14397 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
<> 128:9bcdf88f62b0 14398 #define TIM_SR_SBIF_Pos (13U)
<> 128:9bcdf88f62b0 14399 #define TIM_SR_SBIF_Msk (0x1U << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 14400 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
<> 128:9bcdf88f62b0 14401 #define TIM_SR_CC5IF_Pos (16U)
<> 128:9bcdf88f62b0 14402 #define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 14403 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
<> 128:9bcdf88f62b0 14404 #define TIM_SR_CC6IF_Pos (17U)
<> 128:9bcdf88f62b0 14405 #define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 14406 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
<> 128:9bcdf88f62b0 14407
<> 128:9bcdf88f62b0 14408
<> 128:9bcdf88f62b0 14409 /******************* Bit definition for TIM_EGR register ********************/
<> 128:9bcdf88f62b0 14410 #define TIM_EGR_UG_Pos (0U)
<> 128:9bcdf88f62b0 14411 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 14412 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
<> 128:9bcdf88f62b0 14413 #define TIM_EGR_CC1G_Pos (1U)
<> 128:9bcdf88f62b0 14414 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 14415 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
<> 128:9bcdf88f62b0 14416 #define TIM_EGR_CC2G_Pos (2U)
<> 128:9bcdf88f62b0 14417 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14418 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
<> 128:9bcdf88f62b0 14419 #define TIM_EGR_CC3G_Pos (3U)
<> 128:9bcdf88f62b0 14420 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 14421 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
<> 128:9bcdf88f62b0 14422 #define TIM_EGR_CC4G_Pos (4U)
<> 128:9bcdf88f62b0 14423 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 14424 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
<> 128:9bcdf88f62b0 14425 #define TIM_EGR_COMG_Pos (5U)
<> 128:9bcdf88f62b0 14426 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 14427 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
<> 128:9bcdf88f62b0 14428 #define TIM_EGR_TG_Pos (6U)
<> 128:9bcdf88f62b0 14429 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 14430 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
<> 128:9bcdf88f62b0 14431 #define TIM_EGR_BG_Pos (7U)
<> 128:9bcdf88f62b0 14432 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 14433 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
<> 128:9bcdf88f62b0 14434 #define TIM_EGR_B2G_Pos (8U)
<> 128:9bcdf88f62b0 14435 #define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 14436 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
<> 128:9bcdf88f62b0 14437
<> 128:9bcdf88f62b0 14438
<> 128:9bcdf88f62b0 14439 /****************** Bit definition for TIM_CCMR1 register *******************/
<> 128:9bcdf88f62b0 14440 #define TIM_CCMR1_CC1S_Pos (0U)
<> 128:9bcdf88f62b0 14441 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 14442 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
<> 128:9bcdf88f62b0 14443 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 14444 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 14445
<> 128:9bcdf88f62b0 14446 #define TIM_CCMR1_OC1FE_Pos (2U)
<> 128:9bcdf88f62b0 14447 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14448 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
<> 128:9bcdf88f62b0 14449 #define TIM_CCMR1_OC1PE_Pos (3U)
<> 128:9bcdf88f62b0 14450 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 14451 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
<> 128:9bcdf88f62b0 14452
<> 128:9bcdf88f62b0 14453 #define TIM_CCMR1_OC1M_Pos (4U)
<> 128:9bcdf88f62b0 14454 #define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
<> 128:9bcdf88f62b0 14455 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
<> 128:9bcdf88f62b0 14456 #define TIM_CCMR1_OC1M_0 (0x0001U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 14457 #define TIM_CCMR1_OC1M_1 (0x0002U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 14458 #define TIM_CCMR1_OC1M_2 (0x0004U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 14459 #define TIM_CCMR1_OC1M_3 (0x1000U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 14460
<> 128:9bcdf88f62b0 14461 #define TIM_CCMR1_OC1CE_Pos (7U)
<> 128:9bcdf88f62b0 14462 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 14463 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
<> 128:9bcdf88f62b0 14464
<> 128:9bcdf88f62b0 14465 #define TIM_CCMR1_CC2S_Pos (8U)
<> 128:9bcdf88f62b0 14466 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
<> 128:9bcdf88f62b0 14467 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
<> 128:9bcdf88f62b0 14468 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 14469 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 14470
<> 128:9bcdf88f62b0 14471 #define TIM_CCMR1_OC2FE_Pos (10U)
<> 128:9bcdf88f62b0 14472 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 14473 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
<> 128:9bcdf88f62b0 14474 #define TIM_CCMR1_OC2PE_Pos (11U)
<> 128:9bcdf88f62b0 14475 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 14476 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
<> 128:9bcdf88f62b0 14477
<> 128:9bcdf88f62b0 14478 #define TIM_CCMR1_OC2M_Pos (12U)
<> 128:9bcdf88f62b0 14479 #define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
<> 128:9bcdf88f62b0 14480 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
<> 128:9bcdf88f62b0 14481 #define TIM_CCMR1_OC2M_0 (0x0001U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 14482 #define TIM_CCMR1_OC2M_1 (0x0002U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 14483 #define TIM_CCMR1_OC2M_2 (0x0004U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 14484 #define TIM_CCMR1_OC2M_3 (0x1000U << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 14485
<> 128:9bcdf88f62b0 14486 #define TIM_CCMR1_OC2CE_Pos (15U)
<> 128:9bcdf88f62b0 14487 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 14488 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
<> 128:9bcdf88f62b0 14489
<> 128:9bcdf88f62b0 14490 /*----------------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 14491 #define TIM_CCMR1_IC1PSC_Pos (2U)
<> 128:9bcdf88f62b0 14492 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
<> 128:9bcdf88f62b0 14493 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
<> 128:9bcdf88f62b0 14494 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14495 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 14496
<> 128:9bcdf88f62b0 14497 #define TIM_CCMR1_IC1F_Pos (4U)
<> 128:9bcdf88f62b0 14498 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
<> 128:9bcdf88f62b0 14499 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
<> 128:9bcdf88f62b0 14500 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 14501 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 14502 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 14503 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 14504
<> 128:9bcdf88f62b0 14505 #define TIM_CCMR1_IC2PSC_Pos (10U)
<> 128:9bcdf88f62b0 14506 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
<> 128:9bcdf88f62b0 14507 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
<> 128:9bcdf88f62b0 14508 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 14509 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 14510
<> 128:9bcdf88f62b0 14511 #define TIM_CCMR1_IC2F_Pos (12U)
<> 128:9bcdf88f62b0 14512 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
<> 128:9bcdf88f62b0 14513 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
<> 128:9bcdf88f62b0 14514 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 14515 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 14516 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 14517 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 14518
<> 128:9bcdf88f62b0 14519 /****************** Bit definition for TIM_CCMR2 register *******************/
<> 128:9bcdf88f62b0 14520 #define TIM_CCMR2_CC3S_Pos (0U)
<> 128:9bcdf88f62b0 14521 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 14522 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
<> 128:9bcdf88f62b0 14523 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 14524 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 14525
<> 128:9bcdf88f62b0 14526 #define TIM_CCMR2_OC3FE_Pos (2U)
<> 128:9bcdf88f62b0 14527 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14528 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
<> 128:9bcdf88f62b0 14529 #define TIM_CCMR2_OC3PE_Pos (3U)
<> 128:9bcdf88f62b0 14530 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 14531 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
<> 128:9bcdf88f62b0 14532
<> 128:9bcdf88f62b0 14533 #define TIM_CCMR2_OC3M_Pos (4U)
<> 128:9bcdf88f62b0 14534 #define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
<> 128:9bcdf88f62b0 14535 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
<> 128:9bcdf88f62b0 14536 #define TIM_CCMR2_OC3M_0 (0x0001U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 14537 #define TIM_CCMR2_OC3M_1 (0x0002U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 14538 #define TIM_CCMR2_OC3M_2 (0x0004U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 14539 #define TIM_CCMR2_OC3M_3 (0x1000U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 14540
<> 128:9bcdf88f62b0 14541 #define TIM_CCMR2_OC3CE_Pos (7U)
<> 128:9bcdf88f62b0 14542 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 14543 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
<> 128:9bcdf88f62b0 14544
<> 128:9bcdf88f62b0 14545 #define TIM_CCMR2_CC4S_Pos (8U)
<> 128:9bcdf88f62b0 14546 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
<> 128:9bcdf88f62b0 14547 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
<> 128:9bcdf88f62b0 14548 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 14549 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 14550
<> 128:9bcdf88f62b0 14551 #define TIM_CCMR2_OC4FE_Pos (10U)
<> 128:9bcdf88f62b0 14552 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 14553 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
<> 128:9bcdf88f62b0 14554 #define TIM_CCMR2_OC4PE_Pos (11U)
<> 128:9bcdf88f62b0 14555 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 14556 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
<> 128:9bcdf88f62b0 14557
<> 128:9bcdf88f62b0 14558 #define TIM_CCMR2_OC4M_Pos (12U)
<> 128:9bcdf88f62b0 14559 #define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
<> 128:9bcdf88f62b0 14560 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
<> 128:9bcdf88f62b0 14561 #define TIM_CCMR2_OC4M_0 (0x0001U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 14562 #define TIM_CCMR2_OC4M_1 (0x0002U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 14563 #define TIM_CCMR2_OC4M_2 (0x0004U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 14564 #define TIM_CCMR2_OC4M_3 (0x1000U << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 14565
<> 128:9bcdf88f62b0 14566 #define TIM_CCMR2_OC4CE_Pos (15U)
<> 128:9bcdf88f62b0 14567 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 14568 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
<> 128:9bcdf88f62b0 14569
<> 128:9bcdf88f62b0 14570 /*----------------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 14571 #define TIM_CCMR2_IC3PSC_Pos (2U)
<> 128:9bcdf88f62b0 14572 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
<> 128:9bcdf88f62b0 14573 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
<> 128:9bcdf88f62b0 14574 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14575 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 14576
<> 128:9bcdf88f62b0 14577 #define TIM_CCMR2_IC3F_Pos (4U)
<> 128:9bcdf88f62b0 14578 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
<> 128:9bcdf88f62b0 14579 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
<> 128:9bcdf88f62b0 14580 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 14581 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 14582 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 14583 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 14584
<> 128:9bcdf88f62b0 14585 #define TIM_CCMR2_IC4PSC_Pos (10U)
<> 128:9bcdf88f62b0 14586 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
<> 128:9bcdf88f62b0 14587 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
<> 128:9bcdf88f62b0 14588 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 14589 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 14590
<> 128:9bcdf88f62b0 14591 #define TIM_CCMR2_IC4F_Pos (12U)
<> 128:9bcdf88f62b0 14592 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
<> 128:9bcdf88f62b0 14593 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
<> 128:9bcdf88f62b0 14594 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 14595 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 14596 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 14597 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 14598
<> 128:9bcdf88f62b0 14599 /****************** Bit definition for TIM_CCMR3 register *******************/
<> 128:9bcdf88f62b0 14600 #define TIM_CCMR3_OC5FE_Pos (2U)
<> 128:9bcdf88f62b0 14601 #define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14602 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
<> 128:9bcdf88f62b0 14603 #define TIM_CCMR3_OC5PE_Pos (3U)
<> 128:9bcdf88f62b0 14604 #define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 14605 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
<> 128:9bcdf88f62b0 14606
<> 128:9bcdf88f62b0 14607 #define TIM_CCMR3_OC5M_Pos (4U)
<> 128:9bcdf88f62b0 14608 #define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
<> 128:9bcdf88f62b0 14609 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
<> 128:9bcdf88f62b0 14610 #define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 14611 #define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 14612 #define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 14613 #define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 14614
<> 128:9bcdf88f62b0 14615 #define TIM_CCMR3_OC5CE_Pos (7U)
<> 128:9bcdf88f62b0 14616 #define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 14617 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
<> 128:9bcdf88f62b0 14618
<> 128:9bcdf88f62b0 14619 #define TIM_CCMR3_OC6FE_Pos (10U)
<> 128:9bcdf88f62b0 14620 #define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 14621 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
<> 128:9bcdf88f62b0 14622 #define TIM_CCMR3_OC6PE_Pos (11U)
<> 128:9bcdf88f62b0 14623 #define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 14624 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
<> 128:9bcdf88f62b0 14625
<> 128:9bcdf88f62b0 14626 #define TIM_CCMR3_OC6M_Pos (12U)
<> 128:9bcdf88f62b0 14627 #define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
<> 128:9bcdf88f62b0 14628 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
<> 128:9bcdf88f62b0 14629 #define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 14630 #define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 14631 #define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 14632 #define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 14633
<> 128:9bcdf88f62b0 14634 #define TIM_CCMR3_OC6CE_Pos (15U)
<> 128:9bcdf88f62b0 14635 #define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 14636 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
<> 128:9bcdf88f62b0 14637
<> 128:9bcdf88f62b0 14638 /******************* Bit definition for TIM_CCER register *******************/
<> 128:9bcdf88f62b0 14639 #define TIM_CCER_CC1E_Pos (0U)
<> 128:9bcdf88f62b0 14640 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 14641 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
<> 128:9bcdf88f62b0 14642 #define TIM_CCER_CC1P_Pos (1U)
<> 128:9bcdf88f62b0 14643 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 14644 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
<> 128:9bcdf88f62b0 14645 #define TIM_CCER_CC1NE_Pos (2U)
<> 128:9bcdf88f62b0 14646 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14647 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
<> 128:9bcdf88f62b0 14648 #define TIM_CCER_CC1NP_Pos (3U)
<> 128:9bcdf88f62b0 14649 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 14650 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
<> 128:9bcdf88f62b0 14651 #define TIM_CCER_CC2E_Pos (4U)
<> 128:9bcdf88f62b0 14652 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 14653 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
<> 128:9bcdf88f62b0 14654 #define TIM_CCER_CC2P_Pos (5U)
<> 128:9bcdf88f62b0 14655 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 14656 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
<> 128:9bcdf88f62b0 14657 #define TIM_CCER_CC2NE_Pos (6U)
<> 128:9bcdf88f62b0 14658 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 14659 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
<> 128:9bcdf88f62b0 14660 #define TIM_CCER_CC2NP_Pos (7U)
<> 128:9bcdf88f62b0 14661 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 14662 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
<> 128:9bcdf88f62b0 14663 #define TIM_CCER_CC3E_Pos (8U)
<> 128:9bcdf88f62b0 14664 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 14665 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
<> 128:9bcdf88f62b0 14666 #define TIM_CCER_CC3P_Pos (9U)
<> 128:9bcdf88f62b0 14667 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 14668 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
<> 128:9bcdf88f62b0 14669 #define TIM_CCER_CC3NE_Pos (10U)
<> 128:9bcdf88f62b0 14670 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 14671 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
<> 128:9bcdf88f62b0 14672 #define TIM_CCER_CC3NP_Pos (11U)
<> 128:9bcdf88f62b0 14673 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 14674 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
<> 128:9bcdf88f62b0 14675 #define TIM_CCER_CC4E_Pos (12U)
<> 128:9bcdf88f62b0 14676 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 14677 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
<> 128:9bcdf88f62b0 14678 #define TIM_CCER_CC4P_Pos (13U)
<> 128:9bcdf88f62b0 14679 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 14680 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
<> 128:9bcdf88f62b0 14681 #define TIM_CCER_CC4NP_Pos (15U)
<> 128:9bcdf88f62b0 14682 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 14683 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
<> 128:9bcdf88f62b0 14684 #define TIM_CCER_CC5E_Pos (16U)
<> 128:9bcdf88f62b0 14685 #define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 14686 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
<> 128:9bcdf88f62b0 14687 #define TIM_CCER_CC5P_Pos (17U)
<> 128:9bcdf88f62b0 14688 #define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 14689 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
<> 128:9bcdf88f62b0 14690 #define TIM_CCER_CC6E_Pos (20U)
<> 128:9bcdf88f62b0 14691 #define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 14692 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
<> 128:9bcdf88f62b0 14693 #define TIM_CCER_CC6P_Pos (21U)
<> 128:9bcdf88f62b0 14694 #define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 14695 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
<> 128:9bcdf88f62b0 14696
<> 128:9bcdf88f62b0 14697 /******************* Bit definition for TIM_CNT register ********************/
<> 128:9bcdf88f62b0 14698 #define TIM_CNT_CNT_Pos (0U)
<> 128:9bcdf88f62b0 14699 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 14700 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
<> 128:9bcdf88f62b0 14701 #define TIM_CNT_UIFCPY_Pos (31U)
<> 128:9bcdf88f62b0 14702 #define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 14703 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
<> 128:9bcdf88f62b0 14704
<> 128:9bcdf88f62b0 14705 /******************* Bit definition for TIM_PSC register ********************/
<> 128:9bcdf88f62b0 14706 #define TIM_PSC_PSC_Pos (0U)
<> 128:9bcdf88f62b0 14707 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 14708 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
<> 128:9bcdf88f62b0 14709
<> 128:9bcdf88f62b0 14710 /******************* Bit definition for TIM_ARR register ********************/
<> 128:9bcdf88f62b0 14711 #define TIM_ARR_ARR_Pos (0U)
<> 128:9bcdf88f62b0 14712 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 14713 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
<> 128:9bcdf88f62b0 14714
<> 128:9bcdf88f62b0 14715 /******************* Bit definition for TIM_RCR register ********************/
<> 128:9bcdf88f62b0 14716 #define TIM_RCR_REP_Pos (0U)
<> 128:9bcdf88f62b0 14717 #define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 14718 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
<> 128:9bcdf88f62b0 14719
<> 128:9bcdf88f62b0 14720 /******************* Bit definition for TIM_CCR1 register *******************/
<> 128:9bcdf88f62b0 14721 #define TIM_CCR1_CCR1_Pos (0U)
<> 128:9bcdf88f62b0 14722 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 14723 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
<> 128:9bcdf88f62b0 14724
<> 128:9bcdf88f62b0 14725 /******************* Bit definition for TIM_CCR2 register *******************/
<> 128:9bcdf88f62b0 14726 #define TIM_CCR2_CCR2_Pos (0U)
<> 128:9bcdf88f62b0 14727 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 14728 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
<> 128:9bcdf88f62b0 14729
<> 128:9bcdf88f62b0 14730 /******************* Bit definition for TIM_CCR3 register *******************/
<> 128:9bcdf88f62b0 14731 #define TIM_CCR3_CCR3_Pos (0U)
<> 128:9bcdf88f62b0 14732 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 14733 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
<> 128:9bcdf88f62b0 14734
<> 128:9bcdf88f62b0 14735 /******************* Bit definition for TIM_CCR4 register *******************/
<> 128:9bcdf88f62b0 14736 #define TIM_CCR4_CCR4_Pos (0U)
<> 128:9bcdf88f62b0 14737 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 14738 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
<> 128:9bcdf88f62b0 14739
<> 128:9bcdf88f62b0 14740 /******************* Bit definition for TIM_CCR5 register *******************/
<> 128:9bcdf88f62b0 14741 #define TIM_CCR5_CCR5_Pos (0U)
<> 128:9bcdf88f62b0 14742 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 14743 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
<> 128:9bcdf88f62b0 14744 #define TIM_CCR5_GC5C1_Pos (29U)
<> 128:9bcdf88f62b0 14745 #define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 14746 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
<> 128:9bcdf88f62b0 14747 #define TIM_CCR5_GC5C2_Pos (30U)
<> 128:9bcdf88f62b0 14748 #define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 14749 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
<> 128:9bcdf88f62b0 14750 #define TIM_CCR5_GC5C3_Pos (31U)
<> 128:9bcdf88f62b0 14751 #define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 14752 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
<> 128:9bcdf88f62b0 14753
<> 128:9bcdf88f62b0 14754 /******************* Bit definition for TIM_CCR6 register *******************/
<> 128:9bcdf88f62b0 14755 #define TIM_CCR6_CCR6_Pos (0U)
<> 128:9bcdf88f62b0 14756 #define TIM_CCR6_CCR6_Msk (0xFFFFU << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 14757 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
<> 128:9bcdf88f62b0 14758
<> 128:9bcdf88f62b0 14759 /******************* Bit definition for TIM_BDTR register *******************/
<> 128:9bcdf88f62b0 14760 #define TIM_BDTR_DTG_Pos (0U)
<> 128:9bcdf88f62b0 14761 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 14762 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
<> 128:9bcdf88f62b0 14763 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 14764 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 14765 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14766 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 14767 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 14768 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 14769 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 14770 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 14771
<> 128:9bcdf88f62b0 14772 #define TIM_BDTR_LOCK_Pos (8U)
<> 128:9bcdf88f62b0 14773 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
<> 128:9bcdf88f62b0 14774 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
<> 128:9bcdf88f62b0 14775 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 14776 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 14777
<> 128:9bcdf88f62b0 14778 #define TIM_BDTR_OSSI_Pos (10U)
<> 128:9bcdf88f62b0 14779 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 14780 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
<> 128:9bcdf88f62b0 14781 #define TIM_BDTR_OSSR_Pos (11U)
<> 128:9bcdf88f62b0 14782 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 14783 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
<> 128:9bcdf88f62b0 14784 #define TIM_BDTR_BKE_Pos (12U)
<> 128:9bcdf88f62b0 14785 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 14786 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
<> 128:9bcdf88f62b0 14787 #define TIM_BDTR_BKP_Pos (13U)
<> 128:9bcdf88f62b0 14788 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 14789 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
<> 128:9bcdf88f62b0 14790 #define TIM_BDTR_AOE_Pos (14U)
<> 128:9bcdf88f62b0 14791 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 14792 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
<> 128:9bcdf88f62b0 14793 #define TIM_BDTR_MOE_Pos (15U)
<> 128:9bcdf88f62b0 14794 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 14795 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
<> 128:9bcdf88f62b0 14796
<> 128:9bcdf88f62b0 14797 #define TIM_BDTR_BKF_Pos (16U)
<> 128:9bcdf88f62b0 14798 #define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
<> 128:9bcdf88f62b0 14799 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
<> 128:9bcdf88f62b0 14800 #define TIM_BDTR_BK2F_Pos (20U)
<> 128:9bcdf88f62b0 14801 #define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
<> 128:9bcdf88f62b0 14802 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
<> 128:9bcdf88f62b0 14803
<> 128:9bcdf88f62b0 14804 #define TIM_BDTR_BK2E_Pos (24U)
<> 128:9bcdf88f62b0 14805 #define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 14806 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
<> 128:9bcdf88f62b0 14807 #define TIM_BDTR_BK2P_Pos (25U)
<> 128:9bcdf88f62b0 14808 #define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 14809 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
<> 128:9bcdf88f62b0 14810
<> 128:9bcdf88f62b0 14811 /******************* Bit definition for TIM_DCR register ********************/
<> 128:9bcdf88f62b0 14812 #define TIM_DCR_DBA_Pos (0U)
<> 128:9bcdf88f62b0 14813 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
<> 128:9bcdf88f62b0 14814 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
<> 128:9bcdf88f62b0 14815 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 14816 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 14817 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14818 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 14819 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 14820
<> 128:9bcdf88f62b0 14821 #define TIM_DCR_DBL_Pos (8U)
<> 128:9bcdf88f62b0 14822 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
<> 128:9bcdf88f62b0 14823 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
<> 128:9bcdf88f62b0 14824 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 14825 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 14826 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 14827 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 14828 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 14829
<> 128:9bcdf88f62b0 14830 /******************* Bit definition for TIM_DMAR register *******************/
<> 128:9bcdf88f62b0 14831 #define TIM_DMAR_DMAB_Pos (0U)
<> 128:9bcdf88f62b0 14832 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 14833 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
<> 128:9bcdf88f62b0 14834
<> 128:9bcdf88f62b0 14835 /******************* Bit definition for TIM1_OR1 register *******************/
<> 128:9bcdf88f62b0 14836 #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U)
<> 128:9bcdf88f62b0 14837 #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 14838 #define TIM1_OR1_ETR_ADC1_RMP TIM1_OR1_ETR_ADC1_RMP_Msk /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
<> 128:9bcdf88f62b0 14839 #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 14840 #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 14841
<> 128:9bcdf88f62b0 14842 #define TIM1_OR1_ETR_ADC3_RMP_Pos (2U)
<> 128:9bcdf88f62b0 14843 #define TIM1_OR1_ETR_ADC3_RMP_Msk (0x3U << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x0000000C */
<> 128:9bcdf88f62b0 14844 #define TIM1_OR1_ETR_ADC3_RMP TIM1_OR1_ETR_ADC3_RMP_Msk /*!<ETR_ADC3_RMP[1:0] bits (TIM1 ETR remap on ADC3) */
<> 128:9bcdf88f62b0 14845 #define TIM1_OR1_ETR_ADC3_RMP_0 (0x1U << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14846 #define TIM1_OR1_ETR_ADC3_RMP_1 (0x2U << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 14847
<> 128:9bcdf88f62b0 14848 #define TIM1_OR1_TI1_RMP_Pos (4U)
<> 128:9bcdf88f62b0 14849 #define TIM1_OR1_TI1_RMP_Msk (0x1U << TIM1_OR1_TI1_RMP_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 14850 #define TIM1_OR1_TI1_RMP TIM1_OR1_TI1_RMP_Msk /*!<TIM1 Input Capture 1 remap */
<> 128:9bcdf88f62b0 14851
<> 128:9bcdf88f62b0 14852 /******************* Bit definition for TIM1_OR2 register *******************/
<> 128:9bcdf88f62b0 14853 #define TIM1_OR2_BKINE_Pos (0U)
<> 128:9bcdf88f62b0 14854 #define TIM1_OR2_BKINE_Msk (0x1U << TIM1_OR2_BKINE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 14855 #define TIM1_OR2_BKINE TIM1_OR2_BKINE_Msk /*!<BRK BKIN input enable */
<> 128:9bcdf88f62b0 14856 #define TIM1_OR2_BKCMP1E_Pos (1U)
<> 128:9bcdf88f62b0 14857 #define TIM1_OR2_BKCMP1E_Msk (0x1U << TIM1_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 14858 #define TIM1_OR2_BKCMP1E TIM1_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
<> 128:9bcdf88f62b0 14859 #define TIM1_OR2_BKCMP2E_Pos (2U)
<> 128:9bcdf88f62b0 14860 #define TIM1_OR2_BKCMP2E_Msk (0x1U << TIM1_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14861 #define TIM1_OR2_BKCMP2E TIM1_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
<> 128:9bcdf88f62b0 14862 #define TIM1_OR2_BKDF1BK0E_Pos (8U)
<> 128:9bcdf88f62b0 14863 #define TIM1_OR2_BKDF1BK0E_Msk (0x1U << TIM1_OR2_BKDF1BK0E_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 14864 #define TIM1_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E_Msk /*!<BRK DFSDM1_BREAK[0] enable */
<> 128:9bcdf88f62b0 14865 #define TIM1_OR2_BKINP_Pos (9U)
<> 128:9bcdf88f62b0 14866 #define TIM1_OR2_BKINP_Msk (0x1U << TIM1_OR2_BKINP_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 14867 #define TIM1_OR2_BKINP TIM1_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
<> 128:9bcdf88f62b0 14868 #define TIM1_OR2_BKCMP1P_Pos (10U)
<> 128:9bcdf88f62b0 14869 #define TIM1_OR2_BKCMP1P_Msk (0x1U << TIM1_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 14870 #define TIM1_OR2_BKCMP1P TIM1_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
<> 128:9bcdf88f62b0 14871 #define TIM1_OR2_BKCMP2P_Pos (11U)
<> 128:9bcdf88f62b0 14872 #define TIM1_OR2_BKCMP2P_Msk (0x1U << TIM1_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 14873 #define TIM1_OR2_BKCMP2P TIM1_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
<> 128:9bcdf88f62b0 14874
<> 128:9bcdf88f62b0 14875 #define TIM1_OR2_ETRSEL_Pos (14U)
<> 128:9bcdf88f62b0 14876 #define TIM1_OR2_ETRSEL_Msk (0x7U << TIM1_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
<> 128:9bcdf88f62b0 14877 #define TIM1_OR2_ETRSEL TIM1_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
<> 128:9bcdf88f62b0 14878 #define TIM1_OR2_ETRSEL_0 (0x1U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 14879 #define TIM1_OR2_ETRSEL_1 (0x2U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 14880 #define TIM1_OR2_ETRSEL_2 (0x4U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 14881
<> 128:9bcdf88f62b0 14882 /******************* Bit definition for TIM1_OR3 register *******************/
<> 128:9bcdf88f62b0 14883 #define TIM1_OR3_BK2INE_Pos (0U)
<> 128:9bcdf88f62b0 14884 #define TIM1_OR3_BK2INE_Msk (0x1U << TIM1_OR3_BK2INE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 14885 #define TIM1_OR3_BK2INE TIM1_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
<> 128:9bcdf88f62b0 14886 #define TIM1_OR3_BK2CMP1E_Pos (1U)
<> 128:9bcdf88f62b0 14887 #define TIM1_OR3_BK2CMP1E_Msk (0x1U << TIM1_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 14888 #define TIM1_OR3_BK2CMP1E TIM1_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
<> 128:9bcdf88f62b0 14889 #define TIM1_OR3_BK2CMP2E_Pos (2U)
<> 128:9bcdf88f62b0 14890 #define TIM1_OR3_BK2CMP2E_Msk (0x1U << TIM1_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14891 #define TIM1_OR3_BK2CMP2E TIM1_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
<> 128:9bcdf88f62b0 14892 #define TIM1_OR3_BK2DF1BK1E_Pos (8U)
<> 128:9bcdf88f62b0 14893 #define TIM1_OR3_BK2DF1BK1E_Msk (0x1U << TIM1_OR3_BK2DF1BK1E_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 14894 #define TIM1_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E_Msk /*!<BRK2 DFSDM1_BREAK[1] enable */
<> 128:9bcdf88f62b0 14895 #define TIM1_OR3_BK2INP_Pos (9U)
<> 128:9bcdf88f62b0 14896 #define TIM1_OR3_BK2INP_Msk (0x1U << TIM1_OR3_BK2INP_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 14897 #define TIM1_OR3_BK2INP TIM1_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
<> 128:9bcdf88f62b0 14898 #define TIM1_OR3_BK2CMP1P_Pos (10U)
<> 128:9bcdf88f62b0 14899 #define TIM1_OR3_BK2CMP1P_Msk (0x1U << TIM1_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 14900 #define TIM1_OR3_BK2CMP1P TIM1_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
<> 128:9bcdf88f62b0 14901 #define TIM1_OR3_BK2CMP2P_Pos (11U)
<> 128:9bcdf88f62b0 14902 #define TIM1_OR3_BK2CMP2P_Msk (0x1U << TIM1_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 14903 #define TIM1_OR3_BK2CMP2P TIM1_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
<> 128:9bcdf88f62b0 14904
<> 128:9bcdf88f62b0 14905 /******************* Bit definition for TIM8_OR1 register *******************/
<> 128:9bcdf88f62b0 14906 #define TIM8_OR1_ETR_ADC2_RMP_Pos (0U)
<> 128:9bcdf88f62b0 14907 #define TIM8_OR1_ETR_ADC2_RMP_Msk (0x3U << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 14908 #define TIM8_OR1_ETR_ADC2_RMP TIM8_OR1_ETR_ADC2_RMP_Msk /*!<ETR_ADC2_RMP[1:0] bits (TIM8 ETR remap on ADC2) */
<> 128:9bcdf88f62b0 14909 #define TIM8_OR1_ETR_ADC2_RMP_0 (0x1U << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 14910 #define TIM8_OR1_ETR_ADC2_RMP_1 (0x2U << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 14911
<> 128:9bcdf88f62b0 14912 #define TIM8_OR1_ETR_ADC3_RMP_Pos (2U)
<> 128:9bcdf88f62b0 14913 #define TIM8_OR1_ETR_ADC3_RMP_Msk (0x3U << TIM8_OR1_ETR_ADC3_RMP_Pos) /*!< 0x0000000C */
<> 128:9bcdf88f62b0 14914 #define TIM8_OR1_ETR_ADC3_RMP TIM8_OR1_ETR_ADC3_RMP_Msk /*!<ETR_ADC3_RMP[1:0] bits (TIM8 ETR remap on ADC3) */
<> 128:9bcdf88f62b0 14915 #define TIM8_OR1_ETR_ADC3_RMP_0 (0x1U << TIM8_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14916 #define TIM8_OR1_ETR_ADC3_RMP_1 (0x2U << TIM8_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 14917
<> 128:9bcdf88f62b0 14918 #define TIM8_OR1_TI1_RMP_Pos (4U)
<> 128:9bcdf88f62b0 14919 #define TIM8_OR1_TI1_RMP_Msk (0x1U << TIM8_OR1_TI1_RMP_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 14920 #define TIM8_OR1_TI1_RMP TIM8_OR1_TI1_RMP_Msk /*!<TIM8 Input Capture 1 remap */
<> 128:9bcdf88f62b0 14921
<> 128:9bcdf88f62b0 14922 /******************* Bit definition for TIM8_OR2 register *******************/
<> 128:9bcdf88f62b0 14923 #define TIM8_OR2_BKINE_Pos (0U)
<> 128:9bcdf88f62b0 14924 #define TIM8_OR2_BKINE_Msk (0x1U << TIM8_OR2_BKINE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 14925 #define TIM8_OR2_BKINE TIM8_OR2_BKINE_Msk /*!<BRK BKIN input enable */
<> 128:9bcdf88f62b0 14926 #define TIM8_OR2_BKCMP1E_Pos (1U)
<> 128:9bcdf88f62b0 14927 #define TIM8_OR2_BKCMP1E_Msk (0x1U << TIM8_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 14928 #define TIM8_OR2_BKCMP1E TIM8_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
<> 128:9bcdf88f62b0 14929 #define TIM8_OR2_BKCMP2E_Pos (2U)
<> 128:9bcdf88f62b0 14930 #define TIM8_OR2_BKCMP2E_Msk (0x1U << TIM8_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14931 #define TIM8_OR2_BKCMP2E TIM8_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
<> 128:9bcdf88f62b0 14932 #define TIM8_OR2_BKDF1BK2E_Pos (8U)
<> 128:9bcdf88f62b0 14933 #define TIM8_OR2_BKDF1BK2E_Msk (0x1U << TIM8_OR2_BKDF1BK2E_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 14934 #define TIM8_OR2_BKDF1BK2E TIM8_OR2_BKDF1BK2E_Msk /*!<BRK DFSDM1_BREAK[2] enable */
<> 128:9bcdf88f62b0 14935 #define TIM8_OR2_BKINP_Pos (9U)
<> 128:9bcdf88f62b0 14936 #define TIM8_OR2_BKINP_Msk (0x1U << TIM8_OR2_BKINP_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 14937 #define TIM8_OR2_BKINP TIM8_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
<> 128:9bcdf88f62b0 14938 #define TIM8_OR2_BKCMP1P_Pos (10U)
<> 128:9bcdf88f62b0 14939 #define TIM8_OR2_BKCMP1P_Msk (0x1U << TIM8_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 14940 #define TIM8_OR2_BKCMP1P TIM8_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
<> 128:9bcdf88f62b0 14941 #define TIM8_OR2_BKCMP2P_Pos (11U)
<> 128:9bcdf88f62b0 14942 #define TIM8_OR2_BKCMP2P_Msk (0x1U << TIM8_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 14943 #define TIM8_OR2_BKCMP2P TIM8_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
<> 128:9bcdf88f62b0 14944
<> 128:9bcdf88f62b0 14945 #define TIM8_OR2_ETRSEL_Pos (14U)
<> 128:9bcdf88f62b0 14946 #define TIM8_OR2_ETRSEL_Msk (0x7U << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
<> 128:9bcdf88f62b0 14947 #define TIM8_OR2_ETRSEL TIM8_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */
<> 128:9bcdf88f62b0 14948 #define TIM8_OR2_ETRSEL_0 (0x1U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 14949 #define TIM8_OR2_ETRSEL_1 (0x2U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 14950 #define TIM8_OR2_ETRSEL_2 (0x4U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 14951
<> 128:9bcdf88f62b0 14952 /******************* Bit definition for TIM8_OR3 register *******************/
<> 128:9bcdf88f62b0 14953 #define TIM8_OR3_BK2INE_Pos (0U)
<> 128:9bcdf88f62b0 14954 #define TIM8_OR3_BK2INE_Msk (0x1U << TIM8_OR3_BK2INE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 14955 #define TIM8_OR3_BK2INE TIM8_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
<> 128:9bcdf88f62b0 14956 #define TIM8_OR3_BK2CMP1E_Pos (1U)
<> 128:9bcdf88f62b0 14957 #define TIM8_OR3_BK2CMP1E_Msk (0x1U << TIM8_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 14958 #define TIM8_OR3_BK2CMP1E TIM8_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
<> 128:9bcdf88f62b0 14959 #define TIM8_OR3_BK2CMP2E_Pos (2U)
<> 128:9bcdf88f62b0 14960 #define TIM8_OR3_BK2CMP2E_Msk (0x1U << TIM8_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14961 #define TIM8_OR3_BK2CMP2E TIM8_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
<> 128:9bcdf88f62b0 14962 #define TIM8_OR3_BK2DF1BK3E_Pos (8U)
<> 128:9bcdf88f62b0 14963 #define TIM8_OR3_BK2DF1BK3E_Msk (0x1U << TIM8_OR3_BK2DF1BK3E_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 14964 #define TIM8_OR3_BK2DF1BK3E TIM8_OR3_BK2DF1BK3E_Msk /*!<BRK2 DFSDM1_BREAK[3] enable */
<> 128:9bcdf88f62b0 14965 #define TIM8_OR3_BK2INP_Pos (9U)
<> 128:9bcdf88f62b0 14966 #define TIM8_OR3_BK2INP_Msk (0x1U << TIM8_OR3_BK2INP_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 14967 #define TIM8_OR3_BK2INP TIM8_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
<> 128:9bcdf88f62b0 14968 #define TIM8_OR3_BK2CMP1P_Pos (10U)
<> 128:9bcdf88f62b0 14969 #define TIM8_OR3_BK2CMP1P_Msk (0x1U << TIM8_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 14970 #define TIM8_OR3_BK2CMP1P TIM8_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
<> 128:9bcdf88f62b0 14971 #define TIM8_OR3_BK2CMP2P_Pos (11U)
<> 128:9bcdf88f62b0 14972 #define TIM8_OR3_BK2CMP2P_Msk (0x1U << TIM8_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 14973 #define TIM8_OR3_BK2CMP2P TIM8_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
<> 128:9bcdf88f62b0 14974
<> 128:9bcdf88f62b0 14975 /******************* Bit definition for TIM2_OR1 register *******************/
<> 128:9bcdf88f62b0 14976 #define TIM2_OR1_ITR1_RMP_Pos (0U)
<> 128:9bcdf88f62b0 14977 #define TIM2_OR1_ITR1_RMP_Msk (0x1U << TIM2_OR1_ITR1_RMP_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 14978 #define TIM2_OR1_ITR1_RMP TIM2_OR1_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */
<> 128:9bcdf88f62b0 14979 #define TIM2_OR1_ETR1_RMP_Pos (1U)
<> 128:9bcdf88f62b0 14980 #define TIM2_OR1_ETR1_RMP_Msk (0x1U << TIM2_OR1_ETR1_RMP_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 14981 #define TIM2_OR1_ETR1_RMP TIM2_OR1_ETR1_RMP_Msk /*!<TIM2 External trigger 1 remap */
<> 128:9bcdf88f62b0 14982
<> 128:9bcdf88f62b0 14983 #define TIM2_OR1_TI4_RMP_Pos (2U)
<> 128:9bcdf88f62b0 14984 #define TIM2_OR1_TI4_RMP_Msk (0x3U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x0000000C */
<> 128:9bcdf88f62b0 14985 #define TIM2_OR1_TI4_RMP TIM2_OR1_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
<> 128:9bcdf88f62b0 14986 #define TIM2_OR1_TI4_RMP_0 (0x1U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 14987 #define TIM2_OR1_TI4_RMP_1 (0x2U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 14988
<> 128:9bcdf88f62b0 14989 /******************* Bit definition for TIM2_OR2 register *******************/
<> 128:9bcdf88f62b0 14990 #define TIM2_OR2_ETRSEL_Pos (14U)
<> 128:9bcdf88f62b0 14991 #define TIM2_OR2_ETRSEL_Msk (0x7U << TIM2_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
<> 128:9bcdf88f62b0 14992 #define TIM2_OR2_ETRSEL TIM2_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
<> 128:9bcdf88f62b0 14993 #define TIM2_OR2_ETRSEL_0 (0x1U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 14994 #define TIM2_OR2_ETRSEL_1 (0x2U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 14995 #define TIM2_OR2_ETRSEL_2 (0x4U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 14996
<> 128:9bcdf88f62b0 14997 /******************* Bit definition for TIM3_OR1 register *******************/
<> 128:9bcdf88f62b0 14998 #define TIM3_OR1_TI1_RMP_Pos (0U)
<> 128:9bcdf88f62b0 14999 #define TIM3_OR1_TI1_RMP_Msk (0x3U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 15000 #define TIM3_OR1_TI1_RMP TIM3_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */
<> 128:9bcdf88f62b0 15001 #define TIM3_OR1_TI1_RMP_0 (0x1U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15002 #define TIM3_OR1_TI1_RMP_1 (0x2U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15003
<> 128:9bcdf88f62b0 15004 /******************* Bit definition for TIM3_OR2 register *******************/
<> 128:9bcdf88f62b0 15005 #define TIM3_OR2_ETRSEL_Pos (14U)
<> 128:9bcdf88f62b0 15006 #define TIM3_OR2_ETRSEL_Msk (0x7U << TIM3_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
<> 128:9bcdf88f62b0 15007 #define TIM3_OR2_ETRSEL TIM3_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */
<> 128:9bcdf88f62b0 15008 #define TIM3_OR2_ETRSEL_0 (0x1U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 15009 #define TIM3_OR2_ETRSEL_1 (0x2U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 15010 #define TIM3_OR2_ETRSEL_2 (0x4U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 15011
<> 128:9bcdf88f62b0 15012 /******************* Bit definition for TIM15_OR1 register ******************/
<> 128:9bcdf88f62b0 15013 #define TIM15_OR1_TI1_RMP_Pos (0U)
<> 128:9bcdf88f62b0 15014 #define TIM15_OR1_TI1_RMP_Msk (0x1U << TIM15_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15015 #define TIM15_OR1_TI1_RMP TIM15_OR1_TI1_RMP_Msk /*!<TIM15 Input Capture 1 remap */
<> 128:9bcdf88f62b0 15016
<> 128:9bcdf88f62b0 15017 #define TIM15_OR1_ENCODER_MODE_Pos (1U)
<> 128:9bcdf88f62b0 15018 #define TIM15_OR1_ENCODER_MODE_Msk (0x3U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000006 */
<> 128:9bcdf88f62b0 15019 #define TIM15_OR1_ENCODER_MODE TIM15_OR1_ENCODER_MODE_Msk /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
<> 128:9bcdf88f62b0 15020 #define TIM15_OR1_ENCODER_MODE_0 (0x1U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15021 #define TIM15_OR1_ENCODER_MODE_1 (0x2U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 15022
<> 128:9bcdf88f62b0 15023 /******************* Bit definition for TIM15_OR2 register ******************/
<> 128:9bcdf88f62b0 15024 #define TIM15_OR2_BKINE_Pos (0U)
<> 128:9bcdf88f62b0 15025 #define TIM15_OR2_BKINE_Msk (0x1U << TIM15_OR2_BKINE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15026 #define TIM15_OR2_BKINE TIM15_OR2_BKINE_Msk /*!<BRK BKIN input enable */
<> 128:9bcdf88f62b0 15027 #define TIM15_OR2_BKCMP1E_Pos (1U)
<> 128:9bcdf88f62b0 15028 #define TIM15_OR2_BKCMP1E_Msk (0x1U << TIM15_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15029 #define TIM15_OR2_BKCMP1E TIM15_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
<> 128:9bcdf88f62b0 15030 #define TIM15_OR2_BKCMP2E_Pos (2U)
<> 128:9bcdf88f62b0 15031 #define TIM15_OR2_BKCMP2E_Msk (0x1U << TIM15_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 15032 #define TIM15_OR2_BKCMP2E TIM15_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
<> 128:9bcdf88f62b0 15033 #define TIM15_OR2_BKDF1BK0E_Pos (8U)
<> 128:9bcdf88f62b0 15034 #define TIM15_OR2_BKDF1BK0E_Msk (0x1U << TIM15_OR2_BKDF1BK0E_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 15035 #define TIM15_OR2_BKDF1BK0E TIM15_OR2_BKDF1BK0E_Msk /*!<BRK DFSDM1_BREAK[0] enable */
<> 128:9bcdf88f62b0 15036 #define TIM15_OR2_BKINP_Pos (9U)
<> 128:9bcdf88f62b0 15037 #define TIM15_OR2_BKINP_Msk (0x1U << TIM15_OR2_BKINP_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 15038 #define TIM15_OR2_BKINP TIM15_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
<> 128:9bcdf88f62b0 15039 #define TIM15_OR2_BKCMP1P_Pos (10U)
<> 128:9bcdf88f62b0 15040 #define TIM15_OR2_BKCMP1P_Msk (0x1U << TIM15_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 15041 #define TIM15_OR2_BKCMP1P TIM15_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
<> 128:9bcdf88f62b0 15042 #define TIM15_OR2_BKCMP2P_Pos (11U)
<> 128:9bcdf88f62b0 15043 #define TIM15_OR2_BKCMP2P_Msk (0x1U << TIM15_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 15044 #define TIM15_OR2_BKCMP2P TIM15_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
<> 128:9bcdf88f62b0 15045
<> 128:9bcdf88f62b0 15046 /******************* Bit definition for TIM16_OR1 register ******************/
<> 128:9bcdf88f62b0 15047 #define TIM16_OR1_TI1_RMP_Pos (0U)
<> 128:9bcdf88f62b0 15048 #define TIM16_OR1_TI1_RMP_Msk (0x3U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 15049 #define TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */
<> 128:9bcdf88f62b0 15050 #define TIM16_OR1_TI1_RMP_0 (0x1U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15051 #define TIM16_OR1_TI1_RMP_1 (0x2U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15052
<> 128:9bcdf88f62b0 15053 /******************* Bit definition for TIM16_OR2 register ******************/
<> 128:9bcdf88f62b0 15054 #define TIM16_OR2_BKINE_Pos (0U)
<> 128:9bcdf88f62b0 15055 #define TIM16_OR2_BKINE_Msk (0x1U << TIM16_OR2_BKINE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15056 #define TIM16_OR2_BKINE TIM16_OR2_BKINE_Msk /*!<BRK BKIN input enable */
<> 128:9bcdf88f62b0 15057 #define TIM16_OR2_BKCMP1E_Pos (1U)
<> 128:9bcdf88f62b0 15058 #define TIM16_OR2_BKCMP1E_Msk (0x1U << TIM16_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15059 #define TIM16_OR2_BKCMP1E TIM16_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
<> 128:9bcdf88f62b0 15060 #define TIM16_OR2_BKCMP2E_Pos (2U)
<> 128:9bcdf88f62b0 15061 #define TIM16_OR2_BKCMP2E_Msk (0x1U << TIM16_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 15062 #define TIM16_OR2_BKCMP2E TIM16_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
<> 128:9bcdf88f62b0 15063 #define TIM16_OR2_BKDF1BK1E_Pos (8U)
<> 128:9bcdf88f62b0 15064 #define TIM16_OR2_BKDF1BK1E_Msk (0x1U << TIM16_OR2_BKDF1BK1E_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 15065 #define TIM16_OR2_BKDF1BK1E TIM16_OR2_BKDF1BK1E_Msk /*!<BRK DFSDM1_BREAK[1] enable */
<> 128:9bcdf88f62b0 15066 #define TIM16_OR2_BKINP_Pos (9U)
<> 128:9bcdf88f62b0 15067 #define TIM16_OR2_BKINP_Msk (0x1U << TIM16_OR2_BKINP_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 15068 #define TIM16_OR2_BKINP TIM16_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
<> 128:9bcdf88f62b0 15069 #define TIM16_OR2_BKCMP1P_Pos (10U)
<> 128:9bcdf88f62b0 15070 #define TIM16_OR2_BKCMP1P_Msk (0x1U << TIM16_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 15071 #define TIM16_OR2_BKCMP1P TIM16_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
<> 128:9bcdf88f62b0 15072 #define TIM16_OR2_BKCMP2P_Pos (11U)
<> 128:9bcdf88f62b0 15073 #define TIM16_OR2_BKCMP2P_Msk (0x1U << TIM16_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 15074 #define TIM16_OR2_BKCMP2P TIM16_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
<> 128:9bcdf88f62b0 15075
<> 128:9bcdf88f62b0 15076 /******************* Bit definition for TIM17_OR1 register ******************/
<> 128:9bcdf88f62b0 15077 #define TIM17_OR1_TI1_RMP_Pos (0U)
<> 128:9bcdf88f62b0 15078 #define TIM17_OR1_TI1_RMP_Msk (0x3U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 15079 #define TIM17_OR1_TI1_RMP TIM17_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */
<> 128:9bcdf88f62b0 15080 #define TIM17_OR1_TI1_RMP_0 (0x1U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15081 #define TIM17_OR1_TI1_RMP_1 (0x2U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15082
<> 128:9bcdf88f62b0 15083 /******************* Bit definition for TIM17_OR2 register ******************/
<> 128:9bcdf88f62b0 15084 #define TIM17_OR2_BKINE_Pos (0U)
<> 128:9bcdf88f62b0 15085 #define TIM17_OR2_BKINE_Msk (0x1U << TIM17_OR2_BKINE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15086 #define TIM17_OR2_BKINE TIM17_OR2_BKINE_Msk /*!<BRK BKIN input enable */
<> 128:9bcdf88f62b0 15087 #define TIM17_OR2_BKCMP1E_Pos (1U)
<> 128:9bcdf88f62b0 15088 #define TIM17_OR2_BKCMP1E_Msk (0x1U << TIM17_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15089 #define TIM17_OR2_BKCMP1E TIM17_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
<> 128:9bcdf88f62b0 15090 #define TIM17_OR2_BKCMP2E_Pos (2U)
<> 128:9bcdf88f62b0 15091 #define TIM17_OR2_BKCMP2E_Msk (0x1U << TIM17_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 15092 #define TIM17_OR2_BKCMP2E TIM17_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
<> 128:9bcdf88f62b0 15093 #define TIM17_OR2_BKDF1BK2E_Pos (8U)
<> 128:9bcdf88f62b0 15094 #define TIM17_OR2_BKDF1BK2E_Msk (0x1U << TIM17_OR2_BKDF1BK2E_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 15095 #define TIM17_OR2_BKDF1BK2E TIM17_OR2_BKDF1BK2E_Msk /*!<BRK DFSDM1_BREAK[2] enable */
<> 128:9bcdf88f62b0 15096 #define TIM17_OR2_BKINP_Pos (9U)
<> 128:9bcdf88f62b0 15097 #define TIM17_OR2_BKINP_Msk (0x1U << TIM17_OR2_BKINP_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 15098 #define TIM17_OR2_BKINP TIM17_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
<> 128:9bcdf88f62b0 15099 #define TIM17_OR2_BKCMP1P_Pos (10U)
<> 128:9bcdf88f62b0 15100 #define TIM17_OR2_BKCMP1P_Msk (0x1U << TIM17_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 15101 #define TIM17_OR2_BKCMP1P TIM17_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
<> 128:9bcdf88f62b0 15102 #define TIM17_OR2_BKCMP2P_Pos (11U)
<> 128:9bcdf88f62b0 15103 #define TIM17_OR2_BKCMP2P_Msk (0x1U << TIM17_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 15104 #define TIM17_OR2_BKCMP2P TIM17_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
<> 128:9bcdf88f62b0 15105
<> 128:9bcdf88f62b0 15106 /******************************************************************************/
<> 128:9bcdf88f62b0 15107 /* */
<> 128:9bcdf88f62b0 15108 /* Low Power Timer (LPTTIM) */
<> 128:9bcdf88f62b0 15109 /* */
<> 128:9bcdf88f62b0 15110 /******************************************************************************/
<> 128:9bcdf88f62b0 15111 /****************** Bit definition for LPTIM_ISR register *******************/
<> 128:9bcdf88f62b0 15112 #define LPTIM_ISR_CMPM_Pos (0U)
<> 128:9bcdf88f62b0 15113 #define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15114 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
<> 128:9bcdf88f62b0 15115 #define LPTIM_ISR_ARRM_Pos (1U)
<> 128:9bcdf88f62b0 15116 #define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15117 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
<> 128:9bcdf88f62b0 15118 #define LPTIM_ISR_EXTTRIG_Pos (2U)
<> 128:9bcdf88f62b0 15119 #define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 15120 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
<> 128:9bcdf88f62b0 15121 #define LPTIM_ISR_CMPOK_Pos (3U)
<> 128:9bcdf88f62b0 15122 #define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 15123 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
<> 128:9bcdf88f62b0 15124 #define LPTIM_ISR_ARROK_Pos (4U)
<> 128:9bcdf88f62b0 15125 #define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 15126 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
<> 128:9bcdf88f62b0 15127 #define LPTIM_ISR_UP_Pos (5U)
<> 128:9bcdf88f62b0 15128 #define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 15129 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
<> 128:9bcdf88f62b0 15130 #define LPTIM_ISR_DOWN_Pos (6U)
<> 128:9bcdf88f62b0 15131 #define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 15132 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
<> 128:9bcdf88f62b0 15133
<> 128:9bcdf88f62b0 15134 /****************** Bit definition for LPTIM_ICR register *******************/
<> 128:9bcdf88f62b0 15135 #define LPTIM_ICR_CMPMCF_Pos (0U)
<> 128:9bcdf88f62b0 15136 #define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15137 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
<> 128:9bcdf88f62b0 15138 #define LPTIM_ICR_ARRMCF_Pos (1U)
<> 128:9bcdf88f62b0 15139 #define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15140 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
<> 128:9bcdf88f62b0 15141 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
<> 128:9bcdf88f62b0 15142 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 15143 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
<> 128:9bcdf88f62b0 15144 #define LPTIM_ICR_CMPOKCF_Pos (3U)
<> 128:9bcdf88f62b0 15145 #define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 15146 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
<> 128:9bcdf88f62b0 15147 #define LPTIM_ICR_ARROKCF_Pos (4U)
<> 128:9bcdf88f62b0 15148 #define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 15149 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
<> 128:9bcdf88f62b0 15150 #define LPTIM_ICR_UPCF_Pos (5U)
<> 128:9bcdf88f62b0 15151 #define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 15152 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
<> 128:9bcdf88f62b0 15153 #define LPTIM_ICR_DOWNCF_Pos (6U)
<> 128:9bcdf88f62b0 15154 #define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 15155 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
<> 128:9bcdf88f62b0 15156
<> 128:9bcdf88f62b0 15157 /****************** Bit definition for LPTIM_IER register ********************/
<> 128:9bcdf88f62b0 15158 #define LPTIM_IER_CMPMIE_Pos (0U)
<> 128:9bcdf88f62b0 15159 #define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15160 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
<> 128:9bcdf88f62b0 15161 #define LPTIM_IER_ARRMIE_Pos (1U)
<> 128:9bcdf88f62b0 15162 #define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15163 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
<> 128:9bcdf88f62b0 15164 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
<> 128:9bcdf88f62b0 15165 #define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 15166 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
<> 128:9bcdf88f62b0 15167 #define LPTIM_IER_CMPOKIE_Pos (3U)
<> 128:9bcdf88f62b0 15168 #define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 15169 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
<> 128:9bcdf88f62b0 15170 #define LPTIM_IER_ARROKIE_Pos (4U)
<> 128:9bcdf88f62b0 15171 #define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 15172 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
<> 128:9bcdf88f62b0 15173 #define LPTIM_IER_UPIE_Pos (5U)
<> 128:9bcdf88f62b0 15174 #define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 15175 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
<> 128:9bcdf88f62b0 15176 #define LPTIM_IER_DOWNIE_Pos (6U)
<> 128:9bcdf88f62b0 15177 #define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 15178 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
<> 128:9bcdf88f62b0 15179
<> 128:9bcdf88f62b0 15180 /****************** Bit definition for LPTIM_CFGR register *******************/
<> 128:9bcdf88f62b0 15181 #define LPTIM_CFGR_CKSEL_Pos (0U)
<> 128:9bcdf88f62b0 15182 #define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15183 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
<> 128:9bcdf88f62b0 15184
<> 128:9bcdf88f62b0 15185 #define LPTIM_CFGR_CKPOL_Pos (1U)
<> 128:9bcdf88f62b0 15186 #define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
<> 128:9bcdf88f62b0 15187 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
<> 128:9bcdf88f62b0 15188 #define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15189 #define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 15190
<> 128:9bcdf88f62b0 15191 #define LPTIM_CFGR_CKFLT_Pos (3U)
<> 128:9bcdf88f62b0 15192 #define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
<> 128:9bcdf88f62b0 15193 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
<> 128:9bcdf88f62b0 15194 #define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 15195 #define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 15196
<> 128:9bcdf88f62b0 15197 #define LPTIM_CFGR_TRGFLT_Pos (6U)
<> 128:9bcdf88f62b0 15198 #define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
<> 128:9bcdf88f62b0 15199 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
<> 128:9bcdf88f62b0 15200 #define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 15201 #define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 15202
<> 128:9bcdf88f62b0 15203 #define LPTIM_CFGR_PRESC_Pos (9U)
<> 128:9bcdf88f62b0 15204 #define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
<> 128:9bcdf88f62b0 15205 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
<> 128:9bcdf88f62b0 15206 #define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 15207 #define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 15208 #define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 15209
<> 128:9bcdf88f62b0 15210 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
<> 128:9bcdf88f62b0 15211 #define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
<> 128:9bcdf88f62b0 15212 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
<> 128:9bcdf88f62b0 15213 #define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 15214 #define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 15215 #define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 15216
<> 128:9bcdf88f62b0 15217 #define LPTIM_CFGR_TRIGEN_Pos (17U)
<> 128:9bcdf88f62b0 15218 #define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
<> 128:9bcdf88f62b0 15219 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
<> 128:9bcdf88f62b0 15220 #define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 15221 #define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 15222
<> 128:9bcdf88f62b0 15223 #define LPTIM_CFGR_TIMOUT_Pos (19U)
<> 128:9bcdf88f62b0 15224 #define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 15225 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
<> 128:9bcdf88f62b0 15226 #define LPTIM_CFGR_WAVE_Pos (20U)
<> 128:9bcdf88f62b0 15227 #define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 15228 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
<> 128:9bcdf88f62b0 15229 #define LPTIM_CFGR_WAVPOL_Pos (21U)
<> 128:9bcdf88f62b0 15230 #define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 15231 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
<> 128:9bcdf88f62b0 15232 #define LPTIM_CFGR_PRELOAD_Pos (22U)
<> 128:9bcdf88f62b0 15233 #define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 15234 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
<> 128:9bcdf88f62b0 15235 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
<> 128:9bcdf88f62b0 15236 #define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 15237 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
<> 128:9bcdf88f62b0 15238 #define LPTIM_CFGR_ENC_Pos (24U)
<> 128:9bcdf88f62b0 15239 #define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 15240 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
<> 128:9bcdf88f62b0 15241
<> 128:9bcdf88f62b0 15242 /****************** Bit definition for LPTIM_CR register ********************/
<> 128:9bcdf88f62b0 15243 #define LPTIM_CR_ENABLE_Pos (0U)
<> 128:9bcdf88f62b0 15244 #define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15245 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
<> 128:9bcdf88f62b0 15246 #define LPTIM_CR_SNGSTRT_Pos (1U)
<> 128:9bcdf88f62b0 15247 #define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15248 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
<> 128:9bcdf88f62b0 15249 #define LPTIM_CR_CNTSTRT_Pos (2U)
<> 128:9bcdf88f62b0 15250 #define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 15251 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
<> 128:9bcdf88f62b0 15252
<> 128:9bcdf88f62b0 15253 /****************** Bit definition for LPTIM_CMP register *******************/
<> 128:9bcdf88f62b0 15254 #define LPTIM_CMP_CMP_Pos (0U)
<> 128:9bcdf88f62b0 15255 #define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 15256 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
<> 128:9bcdf88f62b0 15257
<> 128:9bcdf88f62b0 15258 /****************** Bit definition for LPTIM_ARR register *******************/
<> 128:9bcdf88f62b0 15259 #define LPTIM_ARR_ARR_Pos (0U)
<> 128:9bcdf88f62b0 15260 #define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 15261 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
<> 128:9bcdf88f62b0 15262
<> 128:9bcdf88f62b0 15263 /****************** Bit definition for LPTIM_CNT register *******************/
<> 128:9bcdf88f62b0 15264 #define LPTIM_CNT_CNT_Pos (0U)
<> 128:9bcdf88f62b0 15265 #define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 15266 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
<> 128:9bcdf88f62b0 15267
<> 128:9bcdf88f62b0 15268 /****************** Bit definition for LPTIM_OR register *******************/
<> 128:9bcdf88f62b0 15269 #define LPTIM_OR_OR_Pos (0U)
<> 128:9bcdf88f62b0 15270 #define LPTIM_OR_OR_Msk (0x3U << LPTIM_OR_OR_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 15271 #define LPTIM_OR_OR LPTIM_OR_OR_Msk /*!< LPTIMER[1:0] bits (Remap selection) */
<> 128:9bcdf88f62b0 15272 #define LPTIM_OR_OR_0 (0x1U << LPTIM_OR_OR_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15273 #define LPTIM_OR_OR_1 (0x2U << LPTIM_OR_OR_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15274
<> 128:9bcdf88f62b0 15275 /******************************************************************************/
<> 128:9bcdf88f62b0 15276 /* */
<> 128:9bcdf88f62b0 15277 /* Analog Comparators (COMP) */
<> 128:9bcdf88f62b0 15278 /* */
<> 128:9bcdf88f62b0 15279 /******************************************************************************/
<> 128:9bcdf88f62b0 15280 /********************** Bit definition for COMP_CSR register ****************/
<> 128:9bcdf88f62b0 15281 #define COMP_CSR_EN_Pos (0U)
<> 128:9bcdf88f62b0 15282 #define COMP_CSR_EN_Msk (0x1U << COMP_CSR_EN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15283 #define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
<> 128:9bcdf88f62b0 15284
<> 128:9bcdf88f62b0 15285 #define COMP_CSR_PWRMODE_Pos (2U)
<> 128:9bcdf88f62b0 15286 #define COMP_CSR_PWRMODE_Msk (0x3U << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */
<> 128:9bcdf88f62b0 15287 #define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */
<> 128:9bcdf88f62b0 15288 #define COMP_CSR_PWRMODE_0 (0x1U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 15289 #define COMP_CSR_PWRMODE_1 (0x2U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 15290
<> 128:9bcdf88f62b0 15291 #define COMP_CSR_INMSEL_Pos (4U)
<> 128:9bcdf88f62b0 15292 #define COMP_CSR_INMSEL_Msk (0x7U << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
<> 128:9bcdf88f62b0 15293 #define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
<> 128:9bcdf88f62b0 15294 #define COMP_CSR_INMSEL_0 (0x1U << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 15295 #define COMP_CSR_INMSEL_1 (0x2U << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 15296 #define COMP_CSR_INMSEL_2 (0x4U << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 15297
<> 128:9bcdf88f62b0 15298 #define COMP_CSR_INPSEL_Pos (7U)
<> 128:9bcdf88f62b0 15299 #define COMP_CSR_INPSEL_Msk (0x1U << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 15300 #define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
<> 128:9bcdf88f62b0 15301 #define COMP_CSR_INPSEL_0 (0x1U << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 15302
<> 128:9bcdf88f62b0 15303 #define COMP_CSR_WINMODE_Pos (9U)
<> 128:9bcdf88f62b0 15304 #define COMP_CSR_WINMODE_Msk (0x1U << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 15305 #define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
<> 128:9bcdf88f62b0 15306
<> 128:9bcdf88f62b0 15307 #define COMP_CSR_POLARITY_Pos (15U)
<> 128:9bcdf88f62b0 15308 #define COMP_CSR_POLARITY_Msk (0x1U << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 15309 #define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
<> 128:9bcdf88f62b0 15310
<> 128:9bcdf88f62b0 15311 #define COMP_CSR_HYST_Pos (16U)
<> 128:9bcdf88f62b0 15312 #define COMP_CSR_HYST_Msk (0x3U << COMP_CSR_HYST_Pos) /*!< 0x00030000 */
<> 128:9bcdf88f62b0 15313 #define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
<> 128:9bcdf88f62b0 15314 #define COMP_CSR_HYST_0 (0x1U << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 15315 #define COMP_CSR_HYST_1 (0x2U << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 15316
<> 128:9bcdf88f62b0 15317 #define COMP_CSR_BLANKING_Pos (18U)
<> 128:9bcdf88f62b0 15318 #define COMP_CSR_BLANKING_Msk (0x7U << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
<> 128:9bcdf88f62b0 15319 #define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
<> 128:9bcdf88f62b0 15320 #define COMP_CSR_BLANKING_0 (0x1U << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 15321 #define COMP_CSR_BLANKING_1 (0x2U << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 15322 #define COMP_CSR_BLANKING_2 (0x4U << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 15323
<> 128:9bcdf88f62b0 15324 #define COMP_CSR_BRGEN_Pos (22U)
<> 128:9bcdf88f62b0 15325 #define COMP_CSR_BRGEN_Msk (0x1U << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 15326 #define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
<> 128:9bcdf88f62b0 15327 #define COMP_CSR_SCALEN_Pos (23U)
<> 128:9bcdf88f62b0 15328 #define COMP_CSR_SCALEN_Msk (0x1U << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 15329 #define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
<> 128:9bcdf88f62b0 15330
<> 128:9bcdf88f62b0 15331 #define COMP_CSR_VALUE_Pos (30U)
<> 128:9bcdf88f62b0 15332 #define COMP_CSR_VALUE_Msk (0x1U << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 15333 #define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
<> 128:9bcdf88f62b0 15334
<> 128:9bcdf88f62b0 15335 #define COMP_CSR_LOCK_Pos (31U)
<> 128:9bcdf88f62b0 15336 #define COMP_CSR_LOCK_Msk (0x1U << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 15337 #define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
<> 128:9bcdf88f62b0 15338
<> 128:9bcdf88f62b0 15339 /******************************************************************************/
<> 128:9bcdf88f62b0 15340 /* */
<> 128:9bcdf88f62b0 15341 /* Operational Amplifier (OPAMP) */
<> 128:9bcdf88f62b0 15342 /* */
<> 128:9bcdf88f62b0 15343 /******************************************************************************/
<> 128:9bcdf88f62b0 15344 /********************* Bit definition for OPAMPx_CSR register ***************/
<> 128:9bcdf88f62b0 15345 #define OPAMP_CSR_OPAMPxEN_Pos (0U)
<> 128:9bcdf88f62b0 15346 #define OPAMP_CSR_OPAMPxEN_Msk (0x1U << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15347 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
<> 128:9bcdf88f62b0 15348 #define OPAMP_CSR_OPALPM_Pos (1U)
<> 128:9bcdf88f62b0 15349 #define OPAMP_CSR_OPALPM_Msk (0x1U << OPAMP_CSR_OPALPM_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15350 #define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk /*!< Operational amplifier Low Power Mode */
<> 128:9bcdf88f62b0 15351
<> 128:9bcdf88f62b0 15352 #define OPAMP_CSR_OPAMODE_Pos (2U)
<> 128:9bcdf88f62b0 15353 #define OPAMP_CSR_OPAMODE_Msk (0x3U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x0000000C */
<> 128:9bcdf88f62b0 15354 #define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk /*!< Operational amplifier PGA mode */
<> 128:9bcdf88f62b0 15355 #define OPAMP_CSR_OPAMODE_0 (0x1U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 15356 #define OPAMP_CSR_OPAMODE_1 (0x2U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 15357
<> 128:9bcdf88f62b0 15358 #define OPAMP_CSR_PGGAIN_Pos (4U)
<> 128:9bcdf88f62b0 15359 #define OPAMP_CSR_PGGAIN_Msk (0x3U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000030 */
<> 128:9bcdf88f62b0 15360 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
<> 128:9bcdf88f62b0 15361 #define OPAMP_CSR_PGGAIN_0 (0x1U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 15362 #define OPAMP_CSR_PGGAIN_1 (0x2U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 15363
<> 128:9bcdf88f62b0 15364 #define OPAMP_CSR_VMSEL_Pos (8U)
<> 128:9bcdf88f62b0 15365 #define OPAMP_CSR_VMSEL_Msk (0x3U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000300 */
<> 128:9bcdf88f62b0 15366 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
<> 128:9bcdf88f62b0 15367 #define OPAMP_CSR_VMSEL_0 (0x1U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 15368 #define OPAMP_CSR_VMSEL_1 (0x2U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 15369
<> 128:9bcdf88f62b0 15370 #define OPAMP_CSR_VPSEL_Pos (10U)
<> 128:9bcdf88f62b0 15371 #define OPAMP_CSR_VPSEL_Msk (0x1U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 15372 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
<> 128:9bcdf88f62b0 15373 #define OPAMP_CSR_CALON_Pos (12U)
<> 128:9bcdf88f62b0 15374 #define OPAMP_CSR_CALON_Msk (0x1U << OPAMP_CSR_CALON_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 15375 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
<> 128:9bcdf88f62b0 15376 #define OPAMP_CSR_CALSEL_Pos (13U)
<> 128:9bcdf88f62b0 15377 #define OPAMP_CSR_CALSEL_Msk (0x1U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 15378 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
<> 128:9bcdf88f62b0 15379 #define OPAMP_CSR_USERTRIM_Pos (14U)
<> 128:9bcdf88f62b0 15380 #define OPAMP_CSR_USERTRIM_Msk (0x1U << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 15381 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
<> 128:9bcdf88f62b0 15382 #define OPAMP_CSR_CALOUT_Pos (15U)
<> 128:9bcdf88f62b0 15383 #define OPAMP_CSR_CALOUT_Msk (0x1U << OPAMP_CSR_CALOUT_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 15384 #define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
<> 128:9bcdf88f62b0 15385
<> 128:9bcdf88f62b0 15386 /********************* Bit definition for OPAMP1_CSR register ***************/
<> 128:9bcdf88f62b0 15387 #define OPAMP1_CSR_OPAEN_Pos (0U)
<> 128:9bcdf88f62b0 15388 #define OPAMP1_CSR_OPAEN_Msk (0x1U << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15389 #define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
<> 128:9bcdf88f62b0 15390 #define OPAMP1_CSR_OPALPM_Pos (1U)
<> 128:9bcdf88f62b0 15391 #define OPAMP1_CSR_OPALPM_Msk (0x1U << OPAMP1_CSR_OPALPM_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15392 #define OPAMP1_CSR_OPALPM OPAMP1_CSR_OPALPM_Msk /*!< Operational amplifier1 Low Power Mode */
<> 128:9bcdf88f62b0 15393
<> 128:9bcdf88f62b0 15394 #define OPAMP1_CSR_OPAMODE_Pos (2U)
<> 128:9bcdf88f62b0 15395 #define OPAMP1_CSR_OPAMODE_Msk (0x3U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x0000000C */
<> 128:9bcdf88f62b0 15396 #define OPAMP1_CSR_OPAMODE OPAMP1_CSR_OPAMODE_Msk /*!< Operational amplifier1 PGA mode */
<> 128:9bcdf88f62b0 15397 #define OPAMP1_CSR_OPAMODE_0 (0x1U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 15398 #define OPAMP1_CSR_OPAMODE_1 (0x2U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 15399
<> 128:9bcdf88f62b0 15400 #define OPAMP1_CSR_PGAGAIN_Pos (4U)
<> 128:9bcdf88f62b0 15401 #define OPAMP1_CSR_PGAGAIN_Msk (0x3U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000030 */
<> 128:9bcdf88f62b0 15402 #define OPAMP1_CSR_PGAGAIN OPAMP1_CSR_PGAGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
<> 128:9bcdf88f62b0 15403 #define OPAMP1_CSR_PGAGAIN_0 (0x1U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 15404 #define OPAMP1_CSR_PGAGAIN_1 (0x2U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 15405
<> 128:9bcdf88f62b0 15406 #define OPAMP1_CSR_VMSEL_Pos (8U)
<> 128:9bcdf88f62b0 15407 #define OPAMP1_CSR_VMSEL_Msk (0x3U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000300 */
<> 128:9bcdf88f62b0 15408 #define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
<> 128:9bcdf88f62b0 15409 #define OPAMP1_CSR_VMSEL_0 (0x1U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 15410 #define OPAMP1_CSR_VMSEL_1 (0x2U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 15411
<> 128:9bcdf88f62b0 15412 #define OPAMP1_CSR_VPSEL_Pos (10U)
<> 128:9bcdf88f62b0 15413 #define OPAMP1_CSR_VPSEL_Msk (0x1U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 15414 #define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
<> 128:9bcdf88f62b0 15415 #define OPAMP1_CSR_CALON_Pos (12U)
<> 128:9bcdf88f62b0 15416 #define OPAMP1_CSR_CALON_Msk (0x1U << OPAMP1_CSR_CALON_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 15417 #define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
<> 128:9bcdf88f62b0 15418 #define OPAMP1_CSR_CALSEL_Pos (13U)
<> 128:9bcdf88f62b0 15419 #define OPAMP1_CSR_CALSEL_Msk (0x1U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 15420 #define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
<> 128:9bcdf88f62b0 15421 #define OPAMP1_CSR_USERTRIM_Pos (14U)
<> 128:9bcdf88f62b0 15422 #define OPAMP1_CSR_USERTRIM_Msk (0x1U << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 15423 #define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
<> 128:9bcdf88f62b0 15424 #define OPAMP1_CSR_CALOUT_Pos (15U)
<> 128:9bcdf88f62b0 15425 #define OPAMP1_CSR_CALOUT_Msk (0x1U << OPAMP1_CSR_CALOUT_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 15426 #define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
<> 128:9bcdf88f62b0 15427
<> 128:9bcdf88f62b0 15428 #define OPAMP1_CSR_OPARANGE_Pos (31U)
<> 128:9bcdf88f62b0 15429 #define OPAMP1_CSR_OPARANGE_Msk (0x1U << OPAMP1_CSR_OPARANGE_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 15430 #define OPAMP1_CSR_OPARANGE OPAMP1_CSR_OPARANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
<> 128:9bcdf88f62b0 15431
<> 128:9bcdf88f62b0 15432 /********************* Bit definition for OPAMP2_CSR register ***************/
<> 128:9bcdf88f62b0 15433 #define OPAMP2_CSR_OPAEN_Pos (0U)
<> 128:9bcdf88f62b0 15434 #define OPAMP2_CSR_OPAEN_Msk (0x1U << OPAMP2_CSR_OPAEN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15435 #define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk /*!< Operational amplifier2 Enable */
<> 128:9bcdf88f62b0 15436 #define OPAMP2_CSR_OPALPM_Pos (1U)
<> 128:9bcdf88f62b0 15437 #define OPAMP2_CSR_OPALPM_Msk (0x1U << OPAMP2_CSR_OPALPM_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15438 #define OPAMP2_CSR_OPALPM OPAMP2_CSR_OPALPM_Msk /*!< Operational amplifier2 Low Power Mode */
<> 128:9bcdf88f62b0 15439
<> 128:9bcdf88f62b0 15440 #define OPAMP2_CSR_OPAMODE_Pos (2U)
<> 128:9bcdf88f62b0 15441 #define OPAMP2_CSR_OPAMODE_Msk (0x3U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x0000000C */
<> 128:9bcdf88f62b0 15442 #define OPAMP2_CSR_OPAMODE OPAMP2_CSR_OPAMODE_Msk /*!< Operational amplifier2 PGA mode */
<> 128:9bcdf88f62b0 15443 #define OPAMP2_CSR_OPAMODE_0 (0x1U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 15444 #define OPAMP2_CSR_OPAMODE_1 (0x2U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 15445
<> 128:9bcdf88f62b0 15446 #define OPAMP2_CSR_PGAGAIN_Pos (4U)
<> 128:9bcdf88f62b0 15447 #define OPAMP2_CSR_PGAGAIN_Msk (0x3U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000030 */
<> 128:9bcdf88f62b0 15448 #define OPAMP2_CSR_PGAGAIN OPAMP2_CSR_PGAGAIN_Msk /*!< Operational amplifier2 Programmable amplifier gain value */
<> 128:9bcdf88f62b0 15449 #define OPAMP2_CSR_PGAGAIN_0 (0x1U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 15450 #define OPAMP2_CSR_PGAGAIN_1 (0x2U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 15451
<> 128:9bcdf88f62b0 15452 #define OPAMP2_CSR_VMSEL_Pos (8U)
<> 128:9bcdf88f62b0 15453 #define OPAMP2_CSR_VMSEL_Msk (0x3U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000300 */
<> 128:9bcdf88f62b0 15454 #define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
<> 128:9bcdf88f62b0 15455 #define OPAMP2_CSR_VMSEL_0 (0x1U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 15456 #define OPAMP2_CSR_VMSEL_1 (0x2U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 15457
<> 128:9bcdf88f62b0 15458 #define OPAMP2_CSR_VPSEL_Pos (10U)
<> 128:9bcdf88f62b0 15459 #define OPAMP2_CSR_VPSEL_Msk (0x1U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 15460 #define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverted input selection */
<> 128:9bcdf88f62b0 15461 #define OPAMP2_CSR_CALON_Pos (12U)
<> 128:9bcdf88f62b0 15462 #define OPAMP2_CSR_CALON_Msk (0x1U << OPAMP2_CSR_CALON_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 15463 #define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
<> 128:9bcdf88f62b0 15464 #define OPAMP2_CSR_CALSEL_Pos (13U)
<> 128:9bcdf88f62b0 15465 #define OPAMP2_CSR_CALSEL_Msk (0x1U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 15466 #define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
<> 128:9bcdf88f62b0 15467 #define OPAMP2_CSR_USERTRIM_Pos (14U)
<> 128:9bcdf88f62b0 15468 #define OPAMP2_CSR_USERTRIM_Msk (0x1U << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 15469 #define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
<> 128:9bcdf88f62b0 15470 #define OPAMP2_CSR_CALOUT_Pos (15U)
<> 128:9bcdf88f62b0 15471 #define OPAMP2_CSR_CALOUT_Msk (0x1U << OPAMP2_CSR_CALOUT_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 15472 #define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk /*!< Operational amplifier2 calibration output */
<> 128:9bcdf88f62b0 15473
<> 128:9bcdf88f62b0 15474 /******************* Bit definition for OPAMP_OTR register ******************/
<> 128:9bcdf88f62b0 15475 #define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
<> 128:9bcdf88f62b0 15476 #define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
<> 128:9bcdf88f62b0 15477 #define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
<> 128:9bcdf88f62b0 15478 #define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
<> 128:9bcdf88f62b0 15479 #define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
<> 128:9bcdf88f62b0 15480 #define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
<> 128:9bcdf88f62b0 15481
<> 128:9bcdf88f62b0 15482 /******************* Bit definition for OPAMP1_OTR register ******************/
<> 128:9bcdf88f62b0 15483 #define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
<> 128:9bcdf88f62b0 15484 #define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
<> 128:9bcdf88f62b0 15485 #define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
<> 128:9bcdf88f62b0 15486 #define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
<> 128:9bcdf88f62b0 15487 #define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
<> 128:9bcdf88f62b0 15488 #define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
<> 128:9bcdf88f62b0 15489
<> 128:9bcdf88f62b0 15490 /******************* Bit definition for OPAMP2_OTR register ******************/
<> 128:9bcdf88f62b0 15491 #define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
<> 128:9bcdf88f62b0 15492 #define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
<> 128:9bcdf88f62b0 15493 #define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
<> 128:9bcdf88f62b0 15494 #define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
<> 128:9bcdf88f62b0 15495 #define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
<> 128:9bcdf88f62b0 15496 #define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
<> 128:9bcdf88f62b0 15497
<> 128:9bcdf88f62b0 15498 /******************* Bit definition for OPAMP_LPOTR register ****************/
<> 128:9bcdf88f62b0 15499 #define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0U)
<> 128:9bcdf88f62b0 15500 #define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
<> 128:9bcdf88f62b0 15501 #define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
<> 128:9bcdf88f62b0 15502 #define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8U)
<> 128:9bcdf88f62b0 15503 #define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
<> 128:9bcdf88f62b0 15504 #define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
<> 128:9bcdf88f62b0 15505
<> 128:9bcdf88f62b0 15506 /******************* Bit definition for OPAMP1_LPOTR register ****************/
<> 128:9bcdf88f62b0 15507 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos (0U)
<> 128:9bcdf88f62b0 15508 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
<> 128:9bcdf88f62b0 15509 #define OPAMP1_LPOTR_TRIMLPOFFSETN OPAMP1_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
<> 128:9bcdf88f62b0 15510 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos (8U)
<> 128:9bcdf88f62b0 15511 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
<> 128:9bcdf88f62b0 15512 #define OPAMP1_LPOTR_TRIMLPOFFSETP OPAMP1_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
<> 128:9bcdf88f62b0 15513
<> 128:9bcdf88f62b0 15514 /******************* Bit definition for OPAMP2_LPOTR register ****************/
<> 128:9bcdf88f62b0 15515 #define OPAMP2_LPOTR_TRIMLPOFFSETN_Pos (0U)
<> 128:9bcdf88f62b0 15516 #define OPAMP2_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
<> 128:9bcdf88f62b0 15517 #define OPAMP2_LPOTR_TRIMLPOFFSETN OPAMP2_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
<> 128:9bcdf88f62b0 15518 #define OPAMP2_LPOTR_TRIMLPOFFSETP_Pos (8U)
<> 128:9bcdf88f62b0 15519 #define OPAMP2_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
<> 128:9bcdf88f62b0 15520 #define OPAMP2_LPOTR_TRIMLPOFFSETP OPAMP2_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
<> 128:9bcdf88f62b0 15521
<> 128:9bcdf88f62b0 15522 /******************************************************************************/
<> 128:9bcdf88f62b0 15523 /* */
<> 128:9bcdf88f62b0 15524 /* Touch Sensing Controller (TSC) */
<> 128:9bcdf88f62b0 15525 /* */
<> 128:9bcdf88f62b0 15526 /******************************************************************************/
<> 128:9bcdf88f62b0 15527 /******************* Bit definition for TSC_CR register *********************/
<> 128:9bcdf88f62b0 15528 #define TSC_CR_TSCE_Pos (0U)
<> 128:9bcdf88f62b0 15529 #define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15530 #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
<> 128:9bcdf88f62b0 15531 #define TSC_CR_START_Pos (1U)
<> 128:9bcdf88f62b0 15532 #define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15533 #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
<> 128:9bcdf88f62b0 15534 #define TSC_CR_AM_Pos (2U)
<> 128:9bcdf88f62b0 15535 #define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 15536 #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
<> 128:9bcdf88f62b0 15537 #define TSC_CR_SYNCPOL_Pos (3U)
<> 128:9bcdf88f62b0 15538 #define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 15539 #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
<> 128:9bcdf88f62b0 15540 #define TSC_CR_IODEF_Pos (4U)
<> 128:9bcdf88f62b0 15541 #define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 15542 #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
<> 128:9bcdf88f62b0 15543
<> 128:9bcdf88f62b0 15544 #define TSC_CR_MCV_Pos (5U)
<> 128:9bcdf88f62b0 15545 #define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
<> 128:9bcdf88f62b0 15546 #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
<> 128:9bcdf88f62b0 15547 #define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 15548 #define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 15549 #define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 15550
<> 128:9bcdf88f62b0 15551 #define TSC_CR_PGPSC_Pos (12U)
<> 128:9bcdf88f62b0 15552 #define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
<> 128:9bcdf88f62b0 15553 #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
<> 128:9bcdf88f62b0 15554 #define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 15555 #define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 15556 #define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 15557
<> 128:9bcdf88f62b0 15558 #define TSC_CR_SSPSC_Pos (15U)
<> 128:9bcdf88f62b0 15559 #define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 15560 #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
<> 128:9bcdf88f62b0 15561 #define TSC_CR_SSE_Pos (16U)
<> 128:9bcdf88f62b0 15562 #define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 15563 #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
<> 128:9bcdf88f62b0 15564
<> 128:9bcdf88f62b0 15565 #define TSC_CR_SSD_Pos (17U)
<> 128:9bcdf88f62b0 15566 #define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
<> 128:9bcdf88f62b0 15567 #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
<> 128:9bcdf88f62b0 15568 #define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 15569 #define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 15570 #define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 15571 #define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 15572 #define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 15573 #define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 15574 #define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 15575
<> 128:9bcdf88f62b0 15576 #define TSC_CR_CTPL_Pos (24U)
<> 128:9bcdf88f62b0 15577 #define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
<> 128:9bcdf88f62b0 15578 #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
<> 128:9bcdf88f62b0 15579 #define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 15580 #define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 15581 #define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 15582 #define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 15583
<> 128:9bcdf88f62b0 15584 #define TSC_CR_CTPH_Pos (28U)
<> 128:9bcdf88f62b0 15585 #define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
<> 128:9bcdf88f62b0 15586 #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
<> 128:9bcdf88f62b0 15587 #define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 15588 #define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 15589 #define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 15590 #define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 15591
<> 128:9bcdf88f62b0 15592 /******************* Bit definition for TSC_IER register ********************/
<> 128:9bcdf88f62b0 15593 #define TSC_IER_EOAIE_Pos (0U)
<> 128:9bcdf88f62b0 15594 #define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15595 #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
<> 128:9bcdf88f62b0 15596 #define TSC_IER_MCEIE_Pos (1U)
<> 128:9bcdf88f62b0 15597 #define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15598 #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
<> 128:9bcdf88f62b0 15599
<> 128:9bcdf88f62b0 15600 /******************* Bit definition for TSC_ICR register ********************/
<> 128:9bcdf88f62b0 15601 #define TSC_ICR_EOAIC_Pos (0U)
<> 128:9bcdf88f62b0 15602 #define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15603 #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
<> 128:9bcdf88f62b0 15604 #define TSC_ICR_MCEIC_Pos (1U)
<> 128:9bcdf88f62b0 15605 #define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15606 #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
<> 128:9bcdf88f62b0 15607
<> 128:9bcdf88f62b0 15608 /******************* Bit definition for TSC_ISR register ********************/
<> 128:9bcdf88f62b0 15609 #define TSC_ISR_EOAF_Pos (0U)
<> 128:9bcdf88f62b0 15610 #define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15611 #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
<> 128:9bcdf88f62b0 15612 #define TSC_ISR_MCEF_Pos (1U)
<> 128:9bcdf88f62b0 15613 #define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15614 #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
<> 128:9bcdf88f62b0 15615
<> 128:9bcdf88f62b0 15616 /******************* Bit definition for TSC_IOHCR register ******************/
<> 128:9bcdf88f62b0 15617 #define TSC_IOHCR_G1_IO1_Pos (0U)
<> 128:9bcdf88f62b0 15618 #define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15619 #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15620 #define TSC_IOHCR_G1_IO2_Pos (1U)
<> 128:9bcdf88f62b0 15621 #define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15622 #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15623 #define TSC_IOHCR_G1_IO3_Pos (2U)
<> 128:9bcdf88f62b0 15624 #define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 15625 #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15626 #define TSC_IOHCR_G1_IO4_Pos (3U)
<> 128:9bcdf88f62b0 15627 #define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 15628 #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15629 #define TSC_IOHCR_G2_IO1_Pos (4U)
<> 128:9bcdf88f62b0 15630 #define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 15631 #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15632 #define TSC_IOHCR_G2_IO2_Pos (5U)
<> 128:9bcdf88f62b0 15633 #define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 15634 #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15635 #define TSC_IOHCR_G2_IO3_Pos (6U)
<> 128:9bcdf88f62b0 15636 #define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 15637 #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15638 #define TSC_IOHCR_G2_IO4_Pos (7U)
<> 128:9bcdf88f62b0 15639 #define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 15640 #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15641 #define TSC_IOHCR_G3_IO1_Pos (8U)
<> 128:9bcdf88f62b0 15642 #define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 15643 #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15644 #define TSC_IOHCR_G3_IO2_Pos (9U)
<> 128:9bcdf88f62b0 15645 #define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 15646 #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15647 #define TSC_IOHCR_G3_IO3_Pos (10U)
<> 128:9bcdf88f62b0 15648 #define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 15649 #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15650 #define TSC_IOHCR_G3_IO4_Pos (11U)
<> 128:9bcdf88f62b0 15651 #define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 15652 #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15653 #define TSC_IOHCR_G4_IO1_Pos (12U)
<> 128:9bcdf88f62b0 15654 #define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 15655 #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15656 #define TSC_IOHCR_G4_IO2_Pos (13U)
<> 128:9bcdf88f62b0 15657 #define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 15658 #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15659 #define TSC_IOHCR_G4_IO3_Pos (14U)
<> 128:9bcdf88f62b0 15660 #define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 15661 #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15662 #define TSC_IOHCR_G4_IO4_Pos (15U)
<> 128:9bcdf88f62b0 15663 #define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 15664 #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15665 #define TSC_IOHCR_G5_IO1_Pos (16U)
<> 128:9bcdf88f62b0 15666 #define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 15667 #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15668 #define TSC_IOHCR_G5_IO2_Pos (17U)
<> 128:9bcdf88f62b0 15669 #define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 15670 #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15671 #define TSC_IOHCR_G5_IO3_Pos (18U)
<> 128:9bcdf88f62b0 15672 #define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 15673 #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15674 #define TSC_IOHCR_G5_IO4_Pos (19U)
<> 128:9bcdf88f62b0 15675 #define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 15676 #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15677 #define TSC_IOHCR_G6_IO1_Pos (20U)
<> 128:9bcdf88f62b0 15678 #define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 15679 #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15680 #define TSC_IOHCR_G6_IO2_Pos (21U)
<> 128:9bcdf88f62b0 15681 #define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 15682 #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15683 #define TSC_IOHCR_G6_IO3_Pos (22U)
<> 128:9bcdf88f62b0 15684 #define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 15685 #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15686 #define TSC_IOHCR_G6_IO4_Pos (23U)
<> 128:9bcdf88f62b0 15687 #define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 15688 #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15689 #define TSC_IOHCR_G7_IO1_Pos (24U)
<> 128:9bcdf88f62b0 15690 #define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 15691 #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15692 #define TSC_IOHCR_G7_IO2_Pos (25U)
<> 128:9bcdf88f62b0 15693 #define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 15694 #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15695 #define TSC_IOHCR_G7_IO3_Pos (26U)
<> 128:9bcdf88f62b0 15696 #define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 15697 #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15698 #define TSC_IOHCR_G7_IO4_Pos (27U)
<> 128:9bcdf88f62b0 15699 #define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 15700 #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15701 #define TSC_IOHCR_G8_IO1_Pos (28U)
<> 128:9bcdf88f62b0 15702 #define TSC_IOHCR_G8_IO1_Msk (0x1U << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 15703 #define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15704 #define TSC_IOHCR_G8_IO2_Pos (29U)
<> 128:9bcdf88f62b0 15705 #define TSC_IOHCR_G8_IO2_Msk (0x1U << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 15706 #define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15707 #define TSC_IOHCR_G8_IO3_Pos (30U)
<> 128:9bcdf88f62b0 15708 #define TSC_IOHCR_G8_IO3_Msk (0x1U << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 15709 #define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15710 #define TSC_IOHCR_G8_IO4_Pos (31U)
<> 128:9bcdf88f62b0 15711 #define TSC_IOHCR_G8_IO4_Msk (0x1U << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 15712 #define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
<> 128:9bcdf88f62b0 15713
<> 128:9bcdf88f62b0 15714 /******************* Bit definition for TSC_IOASCR register *****************/
<> 128:9bcdf88f62b0 15715 #define TSC_IOASCR_G1_IO1_Pos (0U)
<> 128:9bcdf88f62b0 15716 #define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15717 #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
<> 128:9bcdf88f62b0 15718 #define TSC_IOASCR_G1_IO2_Pos (1U)
<> 128:9bcdf88f62b0 15719 #define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15720 #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
<> 128:9bcdf88f62b0 15721 #define TSC_IOASCR_G1_IO3_Pos (2U)
<> 128:9bcdf88f62b0 15722 #define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 15723 #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
<> 128:9bcdf88f62b0 15724 #define TSC_IOASCR_G1_IO4_Pos (3U)
<> 128:9bcdf88f62b0 15725 #define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 15726 #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
<> 128:9bcdf88f62b0 15727 #define TSC_IOASCR_G2_IO1_Pos (4U)
<> 128:9bcdf88f62b0 15728 #define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 15729 #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
<> 128:9bcdf88f62b0 15730 #define TSC_IOASCR_G2_IO2_Pos (5U)
<> 128:9bcdf88f62b0 15731 #define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 15732 #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
<> 128:9bcdf88f62b0 15733 #define TSC_IOASCR_G2_IO3_Pos (6U)
<> 128:9bcdf88f62b0 15734 #define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 15735 #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
<> 128:9bcdf88f62b0 15736 #define TSC_IOASCR_G2_IO4_Pos (7U)
<> 128:9bcdf88f62b0 15737 #define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 15738 #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
<> 128:9bcdf88f62b0 15739 #define TSC_IOASCR_G3_IO1_Pos (8U)
<> 128:9bcdf88f62b0 15740 #define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 15741 #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
<> 128:9bcdf88f62b0 15742 #define TSC_IOASCR_G3_IO2_Pos (9U)
<> 128:9bcdf88f62b0 15743 #define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 15744 #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
<> 128:9bcdf88f62b0 15745 #define TSC_IOASCR_G3_IO3_Pos (10U)
<> 128:9bcdf88f62b0 15746 #define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 15747 #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
<> 128:9bcdf88f62b0 15748 #define TSC_IOASCR_G3_IO4_Pos (11U)
<> 128:9bcdf88f62b0 15749 #define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 15750 #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
<> 128:9bcdf88f62b0 15751 #define TSC_IOASCR_G4_IO1_Pos (12U)
<> 128:9bcdf88f62b0 15752 #define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 15753 #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
<> 128:9bcdf88f62b0 15754 #define TSC_IOASCR_G4_IO2_Pos (13U)
<> 128:9bcdf88f62b0 15755 #define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 15756 #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
<> 128:9bcdf88f62b0 15757 #define TSC_IOASCR_G4_IO3_Pos (14U)
<> 128:9bcdf88f62b0 15758 #define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 15759 #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
<> 128:9bcdf88f62b0 15760 #define TSC_IOASCR_G4_IO4_Pos (15U)
<> 128:9bcdf88f62b0 15761 #define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 15762 #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
<> 128:9bcdf88f62b0 15763 #define TSC_IOASCR_G5_IO1_Pos (16U)
<> 128:9bcdf88f62b0 15764 #define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 15765 #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
<> 128:9bcdf88f62b0 15766 #define TSC_IOASCR_G5_IO2_Pos (17U)
<> 128:9bcdf88f62b0 15767 #define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 15768 #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
<> 128:9bcdf88f62b0 15769 #define TSC_IOASCR_G5_IO3_Pos (18U)
<> 128:9bcdf88f62b0 15770 #define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 15771 #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
<> 128:9bcdf88f62b0 15772 #define TSC_IOASCR_G5_IO4_Pos (19U)
<> 128:9bcdf88f62b0 15773 #define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 15774 #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
<> 128:9bcdf88f62b0 15775 #define TSC_IOASCR_G6_IO1_Pos (20U)
<> 128:9bcdf88f62b0 15776 #define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 15777 #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
<> 128:9bcdf88f62b0 15778 #define TSC_IOASCR_G6_IO2_Pos (21U)
<> 128:9bcdf88f62b0 15779 #define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 15780 #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
<> 128:9bcdf88f62b0 15781 #define TSC_IOASCR_G6_IO3_Pos (22U)
<> 128:9bcdf88f62b0 15782 #define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 15783 #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
<> 128:9bcdf88f62b0 15784 #define TSC_IOASCR_G6_IO4_Pos (23U)
<> 128:9bcdf88f62b0 15785 #define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 15786 #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
<> 128:9bcdf88f62b0 15787 #define TSC_IOASCR_G7_IO1_Pos (24U)
<> 128:9bcdf88f62b0 15788 #define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 15789 #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
<> 128:9bcdf88f62b0 15790 #define TSC_IOASCR_G7_IO2_Pos (25U)
<> 128:9bcdf88f62b0 15791 #define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 15792 #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
<> 128:9bcdf88f62b0 15793 #define TSC_IOASCR_G7_IO3_Pos (26U)
<> 128:9bcdf88f62b0 15794 #define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 15795 #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
<> 128:9bcdf88f62b0 15796 #define TSC_IOASCR_G7_IO4_Pos (27U)
<> 128:9bcdf88f62b0 15797 #define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 15798 #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
<> 128:9bcdf88f62b0 15799 #define TSC_IOASCR_G8_IO1_Pos (28U)
<> 128:9bcdf88f62b0 15800 #define TSC_IOASCR_G8_IO1_Msk (0x1U << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 15801 #define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
<> 128:9bcdf88f62b0 15802 #define TSC_IOASCR_G8_IO2_Pos (29U)
<> 128:9bcdf88f62b0 15803 #define TSC_IOASCR_G8_IO2_Msk (0x1U << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 15804 #define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
<> 128:9bcdf88f62b0 15805 #define TSC_IOASCR_G8_IO3_Pos (30U)
<> 128:9bcdf88f62b0 15806 #define TSC_IOASCR_G8_IO3_Msk (0x1U << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 15807 #define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
<> 128:9bcdf88f62b0 15808 #define TSC_IOASCR_G8_IO4_Pos (31U)
<> 128:9bcdf88f62b0 15809 #define TSC_IOASCR_G8_IO4_Msk (0x1U << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 15810 #define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
<> 128:9bcdf88f62b0 15811
<> 128:9bcdf88f62b0 15812 /******************* Bit definition for TSC_IOSCR register ******************/
<> 128:9bcdf88f62b0 15813 #define TSC_IOSCR_G1_IO1_Pos (0U)
<> 128:9bcdf88f62b0 15814 #define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15815 #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
<> 128:9bcdf88f62b0 15816 #define TSC_IOSCR_G1_IO2_Pos (1U)
<> 128:9bcdf88f62b0 15817 #define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15818 #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
<> 128:9bcdf88f62b0 15819 #define TSC_IOSCR_G1_IO3_Pos (2U)
<> 128:9bcdf88f62b0 15820 #define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 15821 #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
<> 128:9bcdf88f62b0 15822 #define TSC_IOSCR_G1_IO4_Pos (3U)
<> 128:9bcdf88f62b0 15823 #define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 15824 #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
<> 128:9bcdf88f62b0 15825 #define TSC_IOSCR_G2_IO1_Pos (4U)
<> 128:9bcdf88f62b0 15826 #define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 15827 #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
<> 128:9bcdf88f62b0 15828 #define TSC_IOSCR_G2_IO2_Pos (5U)
<> 128:9bcdf88f62b0 15829 #define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 15830 #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
<> 128:9bcdf88f62b0 15831 #define TSC_IOSCR_G2_IO3_Pos (6U)
<> 128:9bcdf88f62b0 15832 #define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 15833 #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
<> 128:9bcdf88f62b0 15834 #define TSC_IOSCR_G2_IO4_Pos (7U)
<> 128:9bcdf88f62b0 15835 #define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 15836 #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
<> 128:9bcdf88f62b0 15837 #define TSC_IOSCR_G3_IO1_Pos (8U)
<> 128:9bcdf88f62b0 15838 #define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 15839 #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
<> 128:9bcdf88f62b0 15840 #define TSC_IOSCR_G3_IO2_Pos (9U)
<> 128:9bcdf88f62b0 15841 #define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 15842 #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
<> 128:9bcdf88f62b0 15843 #define TSC_IOSCR_G3_IO3_Pos (10U)
<> 128:9bcdf88f62b0 15844 #define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 15845 #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
<> 128:9bcdf88f62b0 15846 #define TSC_IOSCR_G3_IO4_Pos (11U)
<> 128:9bcdf88f62b0 15847 #define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 15848 #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
<> 128:9bcdf88f62b0 15849 #define TSC_IOSCR_G4_IO1_Pos (12U)
<> 128:9bcdf88f62b0 15850 #define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 15851 #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
<> 128:9bcdf88f62b0 15852 #define TSC_IOSCR_G4_IO2_Pos (13U)
<> 128:9bcdf88f62b0 15853 #define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 15854 #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
<> 128:9bcdf88f62b0 15855 #define TSC_IOSCR_G4_IO3_Pos (14U)
<> 128:9bcdf88f62b0 15856 #define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 15857 #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
<> 128:9bcdf88f62b0 15858 #define TSC_IOSCR_G4_IO4_Pos (15U)
<> 128:9bcdf88f62b0 15859 #define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 15860 #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
<> 128:9bcdf88f62b0 15861 #define TSC_IOSCR_G5_IO1_Pos (16U)
<> 128:9bcdf88f62b0 15862 #define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 15863 #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
<> 128:9bcdf88f62b0 15864 #define TSC_IOSCR_G5_IO2_Pos (17U)
<> 128:9bcdf88f62b0 15865 #define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 15866 #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
<> 128:9bcdf88f62b0 15867 #define TSC_IOSCR_G5_IO3_Pos (18U)
<> 128:9bcdf88f62b0 15868 #define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 15869 #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
<> 128:9bcdf88f62b0 15870 #define TSC_IOSCR_G5_IO4_Pos (19U)
<> 128:9bcdf88f62b0 15871 #define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 15872 #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
<> 128:9bcdf88f62b0 15873 #define TSC_IOSCR_G6_IO1_Pos (20U)
<> 128:9bcdf88f62b0 15874 #define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 15875 #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
<> 128:9bcdf88f62b0 15876 #define TSC_IOSCR_G6_IO2_Pos (21U)
<> 128:9bcdf88f62b0 15877 #define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 15878 #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
<> 128:9bcdf88f62b0 15879 #define TSC_IOSCR_G6_IO3_Pos (22U)
<> 128:9bcdf88f62b0 15880 #define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 15881 #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
<> 128:9bcdf88f62b0 15882 #define TSC_IOSCR_G6_IO4_Pos (23U)
<> 128:9bcdf88f62b0 15883 #define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 15884 #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
<> 128:9bcdf88f62b0 15885 #define TSC_IOSCR_G7_IO1_Pos (24U)
<> 128:9bcdf88f62b0 15886 #define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 15887 #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
<> 128:9bcdf88f62b0 15888 #define TSC_IOSCR_G7_IO2_Pos (25U)
<> 128:9bcdf88f62b0 15889 #define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 15890 #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
<> 128:9bcdf88f62b0 15891 #define TSC_IOSCR_G7_IO3_Pos (26U)
<> 128:9bcdf88f62b0 15892 #define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 15893 #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
<> 128:9bcdf88f62b0 15894 #define TSC_IOSCR_G7_IO4_Pos (27U)
<> 128:9bcdf88f62b0 15895 #define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 15896 #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
<> 128:9bcdf88f62b0 15897 #define TSC_IOSCR_G8_IO1_Pos (28U)
<> 128:9bcdf88f62b0 15898 #define TSC_IOSCR_G8_IO1_Msk (0x1U << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 15899 #define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
<> 128:9bcdf88f62b0 15900 #define TSC_IOSCR_G8_IO2_Pos (29U)
<> 128:9bcdf88f62b0 15901 #define TSC_IOSCR_G8_IO2_Msk (0x1U << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 15902 #define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
<> 128:9bcdf88f62b0 15903 #define TSC_IOSCR_G8_IO3_Pos (30U)
<> 128:9bcdf88f62b0 15904 #define TSC_IOSCR_G8_IO3_Msk (0x1U << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 15905 #define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
<> 128:9bcdf88f62b0 15906 #define TSC_IOSCR_G8_IO4_Pos (31U)
<> 128:9bcdf88f62b0 15907 #define TSC_IOSCR_G8_IO4_Msk (0x1U << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 15908 #define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
<> 128:9bcdf88f62b0 15909
<> 128:9bcdf88f62b0 15910 /******************* Bit definition for TSC_IOCCR register ******************/
<> 128:9bcdf88f62b0 15911 #define TSC_IOCCR_G1_IO1_Pos (0U)
<> 128:9bcdf88f62b0 15912 #define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 15913 #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
<> 128:9bcdf88f62b0 15914 #define TSC_IOCCR_G1_IO2_Pos (1U)
<> 128:9bcdf88f62b0 15915 #define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 15916 #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
<> 128:9bcdf88f62b0 15917 #define TSC_IOCCR_G1_IO3_Pos (2U)
<> 128:9bcdf88f62b0 15918 #define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 15919 #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
<> 128:9bcdf88f62b0 15920 #define TSC_IOCCR_G1_IO4_Pos (3U)
<> 128:9bcdf88f62b0 15921 #define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 15922 #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
<> 128:9bcdf88f62b0 15923 #define TSC_IOCCR_G2_IO1_Pos (4U)
<> 128:9bcdf88f62b0 15924 #define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 15925 #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
<> 128:9bcdf88f62b0 15926 #define TSC_IOCCR_G2_IO2_Pos (5U)
<> 128:9bcdf88f62b0 15927 #define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 15928 #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
<> 128:9bcdf88f62b0 15929 #define TSC_IOCCR_G2_IO3_Pos (6U)
<> 128:9bcdf88f62b0 15930 #define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 15931 #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
<> 128:9bcdf88f62b0 15932 #define TSC_IOCCR_G2_IO4_Pos (7U)
<> 128:9bcdf88f62b0 15933 #define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 15934 #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
<> 128:9bcdf88f62b0 15935 #define TSC_IOCCR_G3_IO1_Pos (8U)
<> 128:9bcdf88f62b0 15936 #define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 15937 #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
<> 128:9bcdf88f62b0 15938 #define TSC_IOCCR_G3_IO2_Pos (9U)
<> 128:9bcdf88f62b0 15939 #define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 15940 #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
<> 128:9bcdf88f62b0 15941 #define TSC_IOCCR_G3_IO3_Pos (10U)
<> 128:9bcdf88f62b0 15942 #define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 15943 #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
<> 128:9bcdf88f62b0 15944 #define TSC_IOCCR_G3_IO4_Pos (11U)
<> 128:9bcdf88f62b0 15945 #define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 15946 #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
<> 128:9bcdf88f62b0 15947 #define TSC_IOCCR_G4_IO1_Pos (12U)
<> 128:9bcdf88f62b0 15948 #define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 15949 #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
<> 128:9bcdf88f62b0 15950 #define TSC_IOCCR_G4_IO2_Pos (13U)
<> 128:9bcdf88f62b0 15951 #define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 15952 #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
<> 128:9bcdf88f62b0 15953 #define TSC_IOCCR_G4_IO3_Pos (14U)
<> 128:9bcdf88f62b0 15954 #define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 15955 #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
<> 128:9bcdf88f62b0 15956 #define TSC_IOCCR_G4_IO4_Pos (15U)
<> 128:9bcdf88f62b0 15957 #define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 15958 #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
<> 128:9bcdf88f62b0 15959 #define TSC_IOCCR_G5_IO1_Pos (16U)
<> 128:9bcdf88f62b0 15960 #define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 15961 #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
<> 128:9bcdf88f62b0 15962 #define TSC_IOCCR_G5_IO2_Pos (17U)
<> 128:9bcdf88f62b0 15963 #define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 15964 #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
<> 128:9bcdf88f62b0 15965 #define TSC_IOCCR_G5_IO3_Pos (18U)
<> 128:9bcdf88f62b0 15966 #define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 15967 #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
<> 128:9bcdf88f62b0 15968 #define TSC_IOCCR_G5_IO4_Pos (19U)
<> 128:9bcdf88f62b0 15969 #define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 15970 #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
<> 128:9bcdf88f62b0 15971 #define TSC_IOCCR_G6_IO1_Pos (20U)
<> 128:9bcdf88f62b0 15972 #define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 15973 #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
<> 128:9bcdf88f62b0 15974 #define TSC_IOCCR_G6_IO2_Pos (21U)
<> 128:9bcdf88f62b0 15975 #define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 15976 #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
<> 128:9bcdf88f62b0 15977 #define TSC_IOCCR_G6_IO3_Pos (22U)
<> 128:9bcdf88f62b0 15978 #define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 15979 #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
<> 128:9bcdf88f62b0 15980 #define TSC_IOCCR_G6_IO4_Pos (23U)
<> 128:9bcdf88f62b0 15981 #define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 15982 #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
<> 128:9bcdf88f62b0 15983 #define TSC_IOCCR_G7_IO1_Pos (24U)
<> 128:9bcdf88f62b0 15984 #define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 15985 #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
<> 128:9bcdf88f62b0 15986 #define TSC_IOCCR_G7_IO2_Pos (25U)
<> 128:9bcdf88f62b0 15987 #define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 15988 #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
<> 128:9bcdf88f62b0 15989 #define TSC_IOCCR_G7_IO3_Pos (26U)
<> 128:9bcdf88f62b0 15990 #define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 15991 #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
<> 128:9bcdf88f62b0 15992 #define TSC_IOCCR_G7_IO4_Pos (27U)
<> 128:9bcdf88f62b0 15993 #define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 15994 #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
<> 128:9bcdf88f62b0 15995 #define TSC_IOCCR_G8_IO1_Pos (28U)
<> 128:9bcdf88f62b0 15996 #define TSC_IOCCR_G8_IO1_Msk (0x1U << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 15997 #define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
<> 128:9bcdf88f62b0 15998 #define TSC_IOCCR_G8_IO2_Pos (29U)
<> 128:9bcdf88f62b0 15999 #define TSC_IOCCR_G8_IO2_Msk (0x1U << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 16000 #define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
<> 128:9bcdf88f62b0 16001 #define TSC_IOCCR_G8_IO3_Pos (30U)
<> 128:9bcdf88f62b0 16002 #define TSC_IOCCR_G8_IO3_Msk (0x1U << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 16003 #define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
<> 128:9bcdf88f62b0 16004 #define TSC_IOCCR_G8_IO4_Pos (31U)
<> 128:9bcdf88f62b0 16005 #define TSC_IOCCR_G8_IO4_Msk (0x1U << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 16006 #define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
<> 128:9bcdf88f62b0 16007
<> 128:9bcdf88f62b0 16008 /******************* Bit definition for TSC_IOGCSR register *****************/
<> 128:9bcdf88f62b0 16009 #define TSC_IOGCSR_G1E_Pos (0U)
<> 128:9bcdf88f62b0 16010 #define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16011 #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
<> 128:9bcdf88f62b0 16012 #define TSC_IOGCSR_G2E_Pos (1U)
<> 128:9bcdf88f62b0 16013 #define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16014 #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
<> 128:9bcdf88f62b0 16015 #define TSC_IOGCSR_G3E_Pos (2U)
<> 128:9bcdf88f62b0 16016 #define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16017 #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
<> 128:9bcdf88f62b0 16018 #define TSC_IOGCSR_G4E_Pos (3U)
<> 128:9bcdf88f62b0 16019 #define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 16020 #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
<> 128:9bcdf88f62b0 16021 #define TSC_IOGCSR_G5E_Pos (4U)
<> 128:9bcdf88f62b0 16022 #define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 16023 #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
<> 128:9bcdf88f62b0 16024 #define TSC_IOGCSR_G6E_Pos (5U)
<> 128:9bcdf88f62b0 16025 #define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 16026 #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
<> 128:9bcdf88f62b0 16027 #define TSC_IOGCSR_G7E_Pos (6U)
<> 128:9bcdf88f62b0 16028 #define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 16029 #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
<> 128:9bcdf88f62b0 16030 #define TSC_IOGCSR_G8E_Pos (7U)
<> 128:9bcdf88f62b0 16031 #define TSC_IOGCSR_G8E_Msk (0x1U << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 16032 #define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
<> 128:9bcdf88f62b0 16033 #define TSC_IOGCSR_G1S_Pos (16U)
<> 128:9bcdf88f62b0 16034 #define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 16035 #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
<> 128:9bcdf88f62b0 16036 #define TSC_IOGCSR_G2S_Pos (17U)
<> 128:9bcdf88f62b0 16037 #define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 16038 #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
<> 128:9bcdf88f62b0 16039 #define TSC_IOGCSR_G3S_Pos (18U)
<> 128:9bcdf88f62b0 16040 #define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 16041 #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
<> 128:9bcdf88f62b0 16042 #define TSC_IOGCSR_G4S_Pos (19U)
<> 128:9bcdf88f62b0 16043 #define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 16044 #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
<> 128:9bcdf88f62b0 16045 #define TSC_IOGCSR_G5S_Pos (20U)
<> 128:9bcdf88f62b0 16046 #define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 16047 #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
<> 128:9bcdf88f62b0 16048 #define TSC_IOGCSR_G6S_Pos (21U)
<> 128:9bcdf88f62b0 16049 #define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 16050 #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
<> 128:9bcdf88f62b0 16051 #define TSC_IOGCSR_G7S_Pos (22U)
<> 128:9bcdf88f62b0 16052 #define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 16053 #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
<> 128:9bcdf88f62b0 16054 #define TSC_IOGCSR_G8S_Pos (23U)
<> 128:9bcdf88f62b0 16055 #define TSC_IOGCSR_G8S_Msk (0x1U << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 16056 #define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
<> 128:9bcdf88f62b0 16057
<> 128:9bcdf88f62b0 16058 /******************* Bit definition for TSC_IOGXCR register *****************/
<> 128:9bcdf88f62b0 16059 #define TSC_IOGXCR_CNT_Pos (0U)
<> 128:9bcdf88f62b0 16060 #define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
<> 128:9bcdf88f62b0 16061 #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
<> 128:9bcdf88f62b0 16062
<> 128:9bcdf88f62b0 16063 /******************************************************************************/
<> 128:9bcdf88f62b0 16064 /* */
<> 128:9bcdf88f62b0 16065 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
<> 128:9bcdf88f62b0 16066 /* */
<> 128:9bcdf88f62b0 16067 /******************************************************************************/
<> 128:9bcdf88f62b0 16068 /****************** Bit definition for USART_CR1 register *******************/
<> 128:9bcdf88f62b0 16069 #define USART_CR1_UE_Pos (0U)
<> 128:9bcdf88f62b0 16070 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16071 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
<> 128:9bcdf88f62b0 16072 #define USART_CR1_UESM_Pos (1U)
<> 128:9bcdf88f62b0 16073 #define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16074 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
<> 128:9bcdf88f62b0 16075 #define USART_CR1_RE_Pos (2U)
<> 128:9bcdf88f62b0 16076 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16077 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
<> 128:9bcdf88f62b0 16078 #define USART_CR1_TE_Pos (3U)
<> 128:9bcdf88f62b0 16079 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 16080 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
<> 128:9bcdf88f62b0 16081 #define USART_CR1_IDLEIE_Pos (4U)
<> 128:9bcdf88f62b0 16082 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 16083 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
<> 128:9bcdf88f62b0 16084 #define USART_CR1_RXNEIE_Pos (5U)
<> 128:9bcdf88f62b0 16085 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 16086 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
<> 128:9bcdf88f62b0 16087 #define USART_CR1_TCIE_Pos (6U)
<> 128:9bcdf88f62b0 16088 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 16089 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
<> 128:9bcdf88f62b0 16090 #define USART_CR1_TXEIE_Pos (7U)
<> 128:9bcdf88f62b0 16091 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 16092 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
<> 128:9bcdf88f62b0 16093 #define USART_CR1_PEIE_Pos (8U)
<> 128:9bcdf88f62b0 16094 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 16095 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
<> 128:9bcdf88f62b0 16096 #define USART_CR1_PS_Pos (9U)
<> 128:9bcdf88f62b0 16097 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 16098 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
<> 128:9bcdf88f62b0 16099 #define USART_CR1_PCE_Pos (10U)
<> 128:9bcdf88f62b0 16100 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 16101 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
<> 128:9bcdf88f62b0 16102 #define USART_CR1_WAKE_Pos (11U)
<> 128:9bcdf88f62b0 16103 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 16104 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
<> 128:9bcdf88f62b0 16105 #define USART_CR1_M_Pos (12U)
<> 128:9bcdf88f62b0 16106 #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
<> 128:9bcdf88f62b0 16107 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
<> 128:9bcdf88f62b0 16108 #define USART_CR1_M0_Pos (12U)
<> 128:9bcdf88f62b0 16109 #define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 16110 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
<> 128:9bcdf88f62b0 16111 #define USART_CR1_MME_Pos (13U)
<> 128:9bcdf88f62b0 16112 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 16113 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
<> 128:9bcdf88f62b0 16114 #define USART_CR1_CMIE_Pos (14U)
<> 128:9bcdf88f62b0 16115 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 16116 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
<> 128:9bcdf88f62b0 16117 #define USART_CR1_OVER8_Pos (15U)
<> 128:9bcdf88f62b0 16118 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 16119 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
<> 128:9bcdf88f62b0 16120 #define USART_CR1_DEDT_Pos (16U)
<> 128:9bcdf88f62b0 16121 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
<> 128:9bcdf88f62b0 16122 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
<> 128:9bcdf88f62b0 16123 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 16124 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 16125 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 16126 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 16127 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 16128 #define USART_CR1_DEAT_Pos (21U)
<> 128:9bcdf88f62b0 16129 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
<> 128:9bcdf88f62b0 16130 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
<> 128:9bcdf88f62b0 16131 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 16132 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 16133 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 16134 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 16135 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 16136 #define USART_CR1_RTOIE_Pos (26U)
<> 128:9bcdf88f62b0 16137 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 16138 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
<> 128:9bcdf88f62b0 16139 #define USART_CR1_EOBIE_Pos (27U)
<> 128:9bcdf88f62b0 16140 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 16141 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
<> 128:9bcdf88f62b0 16142 #define USART_CR1_M1_Pos (28U)
<> 128:9bcdf88f62b0 16143 #define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 16144 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
<> 128:9bcdf88f62b0 16145
<> 128:9bcdf88f62b0 16146 /****************** Bit definition for USART_CR2 register *******************/
<> 128:9bcdf88f62b0 16147 #define USART_CR2_ADDM7_Pos (4U)
<> 128:9bcdf88f62b0 16148 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 16149 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
<> 128:9bcdf88f62b0 16150 #define USART_CR2_LBDL_Pos (5U)
<> 128:9bcdf88f62b0 16151 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 16152 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
<> 128:9bcdf88f62b0 16153 #define USART_CR2_LBDIE_Pos (6U)
<> 128:9bcdf88f62b0 16154 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 16155 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
<> 128:9bcdf88f62b0 16156 #define USART_CR2_LBCL_Pos (8U)
<> 128:9bcdf88f62b0 16157 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 16158 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
<> 128:9bcdf88f62b0 16159 #define USART_CR2_CPHA_Pos (9U)
<> 128:9bcdf88f62b0 16160 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 16161 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
<> 128:9bcdf88f62b0 16162 #define USART_CR2_CPOL_Pos (10U)
<> 128:9bcdf88f62b0 16163 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 16164 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
<> 128:9bcdf88f62b0 16165 #define USART_CR2_CLKEN_Pos (11U)
<> 128:9bcdf88f62b0 16166 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 16167 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
<> 128:9bcdf88f62b0 16168 #define USART_CR2_STOP_Pos (12U)
<> 128:9bcdf88f62b0 16169 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
<> 128:9bcdf88f62b0 16170 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
<> 128:9bcdf88f62b0 16171 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 16172 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 16173 #define USART_CR2_LINEN_Pos (14U)
<> 128:9bcdf88f62b0 16174 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 16175 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
<> 128:9bcdf88f62b0 16176 #define USART_CR2_SWAP_Pos (15U)
<> 128:9bcdf88f62b0 16177 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 16178 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
<> 128:9bcdf88f62b0 16179 #define USART_CR2_RXINV_Pos (16U)
<> 128:9bcdf88f62b0 16180 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 16181 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
<> 128:9bcdf88f62b0 16182 #define USART_CR2_TXINV_Pos (17U)
<> 128:9bcdf88f62b0 16183 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 16184 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
<> 128:9bcdf88f62b0 16185 #define USART_CR2_DATAINV_Pos (18U)
<> 128:9bcdf88f62b0 16186 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 16187 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
<> 128:9bcdf88f62b0 16188 #define USART_CR2_MSBFIRST_Pos (19U)
<> 128:9bcdf88f62b0 16189 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 16190 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
<> 128:9bcdf88f62b0 16191 #define USART_CR2_ABREN_Pos (20U)
<> 128:9bcdf88f62b0 16192 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 16193 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
<> 128:9bcdf88f62b0 16194 #define USART_CR2_ABRMODE_Pos (21U)
<> 128:9bcdf88f62b0 16195 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
<> 128:9bcdf88f62b0 16196 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
<> 128:9bcdf88f62b0 16197 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 16198 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 16199 #define USART_CR2_RTOEN_Pos (23U)
<> 128:9bcdf88f62b0 16200 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 16201 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
<> 128:9bcdf88f62b0 16202 #define USART_CR2_ADD_Pos (24U)
<> 128:9bcdf88f62b0 16203 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
<> 128:9bcdf88f62b0 16204 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
<> 128:9bcdf88f62b0 16205
<> 128:9bcdf88f62b0 16206 /****************** Bit definition for USART_CR3 register *******************/
<> 128:9bcdf88f62b0 16207 #define USART_CR3_EIE_Pos (0U)
<> 128:9bcdf88f62b0 16208 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16209 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
<> 128:9bcdf88f62b0 16210 #define USART_CR3_IREN_Pos (1U)
<> 128:9bcdf88f62b0 16211 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16212 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
<> 128:9bcdf88f62b0 16213 #define USART_CR3_IRLP_Pos (2U)
<> 128:9bcdf88f62b0 16214 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16215 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
<> 128:9bcdf88f62b0 16216 #define USART_CR3_HDSEL_Pos (3U)
<> 128:9bcdf88f62b0 16217 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 16218 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
<> 128:9bcdf88f62b0 16219 #define USART_CR3_NACK_Pos (4U)
<> 128:9bcdf88f62b0 16220 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 16221 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
<> 128:9bcdf88f62b0 16222 #define USART_CR3_SCEN_Pos (5U)
<> 128:9bcdf88f62b0 16223 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 16224 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
<> 128:9bcdf88f62b0 16225 #define USART_CR3_DMAR_Pos (6U)
<> 128:9bcdf88f62b0 16226 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 16227 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
<> 128:9bcdf88f62b0 16228 #define USART_CR3_DMAT_Pos (7U)
<> 128:9bcdf88f62b0 16229 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 16230 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
<> 128:9bcdf88f62b0 16231 #define USART_CR3_RTSE_Pos (8U)
<> 128:9bcdf88f62b0 16232 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 16233 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
<> 128:9bcdf88f62b0 16234 #define USART_CR3_CTSE_Pos (9U)
<> 128:9bcdf88f62b0 16235 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 16236 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
<> 128:9bcdf88f62b0 16237 #define USART_CR3_CTSIE_Pos (10U)
<> 128:9bcdf88f62b0 16238 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 16239 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
<> 128:9bcdf88f62b0 16240 #define USART_CR3_ONEBIT_Pos (11U)
<> 128:9bcdf88f62b0 16241 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 16242 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
<> 128:9bcdf88f62b0 16243 #define USART_CR3_OVRDIS_Pos (12U)
<> 128:9bcdf88f62b0 16244 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 16245 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
<> 128:9bcdf88f62b0 16246 #define USART_CR3_DDRE_Pos (13U)
<> 128:9bcdf88f62b0 16247 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 16248 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
<> 128:9bcdf88f62b0 16249 #define USART_CR3_DEM_Pos (14U)
<> 128:9bcdf88f62b0 16250 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 16251 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
<> 128:9bcdf88f62b0 16252 #define USART_CR3_DEP_Pos (15U)
<> 128:9bcdf88f62b0 16253 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 16254 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
<> 128:9bcdf88f62b0 16255 #define USART_CR3_SCARCNT_Pos (17U)
<> 128:9bcdf88f62b0 16256 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
<> 128:9bcdf88f62b0 16257 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
<> 128:9bcdf88f62b0 16258 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 16259 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 16260 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 16261 #define USART_CR3_WUS_Pos (20U)
<> 128:9bcdf88f62b0 16262 #define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
<> 128:9bcdf88f62b0 16263 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
<> 128:9bcdf88f62b0 16264 #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 16265 #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 16266 #define USART_CR3_WUFIE_Pos (22U)
<> 128:9bcdf88f62b0 16267 #define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 16268 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
<> 128:9bcdf88f62b0 16269
<> 128:9bcdf88f62b0 16270 /****************** Bit definition for USART_BRR register *******************/
<> 128:9bcdf88f62b0 16271 #define USART_BRR_DIV_FRACTION_Pos (0U)
<> 128:9bcdf88f62b0 16272 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 16273 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
<> 128:9bcdf88f62b0 16274 #define USART_BRR_DIV_MANTISSA_Pos (4U)
<> 128:9bcdf88f62b0 16275 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
<> 128:9bcdf88f62b0 16276 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
<> 128:9bcdf88f62b0 16277
<> 128:9bcdf88f62b0 16278 /****************** Bit definition for USART_GTPR register ******************/
<> 128:9bcdf88f62b0 16279 #define USART_GTPR_PSC_Pos (0U)
<> 128:9bcdf88f62b0 16280 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
<> 128:9bcdf88f62b0 16281 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
<> 128:9bcdf88f62b0 16282 #define USART_GTPR_GT_Pos (8U)
<> 128:9bcdf88f62b0 16283 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
<> 128:9bcdf88f62b0 16284 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
<> 128:9bcdf88f62b0 16285
<> 128:9bcdf88f62b0 16286
<> 128:9bcdf88f62b0 16287 /******************* Bit definition for USART_RTOR register *****************/
<> 128:9bcdf88f62b0 16288 #define USART_RTOR_RTO_Pos (0U)
<> 128:9bcdf88f62b0 16289 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
<> 128:9bcdf88f62b0 16290 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
<> 128:9bcdf88f62b0 16291 #define USART_RTOR_BLEN_Pos (24U)
<> 128:9bcdf88f62b0 16292 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
<> 128:9bcdf88f62b0 16293 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
<> 128:9bcdf88f62b0 16294
<> 128:9bcdf88f62b0 16295 /******************* Bit definition for USART_RQR register ******************/
<> 128:9bcdf88f62b0 16296 #define USART_RQR_ABRRQ_Pos (0U)
<> 128:9bcdf88f62b0 16297 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16298 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
<> 128:9bcdf88f62b0 16299 #define USART_RQR_SBKRQ_Pos (1U)
<> 128:9bcdf88f62b0 16300 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16301 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
<> 128:9bcdf88f62b0 16302 #define USART_RQR_MMRQ_Pos (2U)
<> 128:9bcdf88f62b0 16303 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16304 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
<> 128:9bcdf88f62b0 16305 #define USART_RQR_RXFRQ_Pos (3U)
<> 128:9bcdf88f62b0 16306 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 16307 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
<> 128:9bcdf88f62b0 16308 #define USART_RQR_TXFRQ_Pos (4U)
<> 128:9bcdf88f62b0 16309 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 16310 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
<> 128:9bcdf88f62b0 16311
<> 128:9bcdf88f62b0 16312 /******************* Bit definition for USART_ISR register ******************/
<> 128:9bcdf88f62b0 16313 #define USART_ISR_PE_Pos (0U)
<> 128:9bcdf88f62b0 16314 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16315 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
<> 128:9bcdf88f62b0 16316 #define USART_ISR_FE_Pos (1U)
<> 128:9bcdf88f62b0 16317 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16318 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
<> 128:9bcdf88f62b0 16319 #define USART_ISR_NE_Pos (2U)
<> 128:9bcdf88f62b0 16320 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16321 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
<> 128:9bcdf88f62b0 16322 #define USART_ISR_ORE_Pos (3U)
<> 128:9bcdf88f62b0 16323 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 16324 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
<> 128:9bcdf88f62b0 16325 #define USART_ISR_IDLE_Pos (4U)
<> 128:9bcdf88f62b0 16326 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 16327 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
<> 128:9bcdf88f62b0 16328 #define USART_ISR_RXNE_Pos (5U)
<> 128:9bcdf88f62b0 16329 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 16330 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
<> 128:9bcdf88f62b0 16331 #define USART_ISR_TC_Pos (6U)
<> 128:9bcdf88f62b0 16332 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 16333 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
<> 128:9bcdf88f62b0 16334 #define USART_ISR_TXE_Pos (7U)
<> 128:9bcdf88f62b0 16335 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 16336 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
<> 128:9bcdf88f62b0 16337 #define USART_ISR_LBDF_Pos (8U)
<> 128:9bcdf88f62b0 16338 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 16339 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
<> 128:9bcdf88f62b0 16340 #define USART_ISR_CTSIF_Pos (9U)
<> 128:9bcdf88f62b0 16341 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 16342 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
<> 128:9bcdf88f62b0 16343 #define USART_ISR_CTS_Pos (10U)
<> 128:9bcdf88f62b0 16344 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 16345 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
<> 128:9bcdf88f62b0 16346 #define USART_ISR_RTOF_Pos (11U)
<> 128:9bcdf88f62b0 16347 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 16348 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
<> 128:9bcdf88f62b0 16349 #define USART_ISR_EOBF_Pos (12U)
<> 128:9bcdf88f62b0 16350 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 16351 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
<> 128:9bcdf88f62b0 16352 #define USART_ISR_ABRE_Pos (14U)
<> 128:9bcdf88f62b0 16353 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 16354 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
<> 128:9bcdf88f62b0 16355 #define USART_ISR_ABRF_Pos (15U)
<> 128:9bcdf88f62b0 16356 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 16357 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
<> 128:9bcdf88f62b0 16358 #define USART_ISR_BUSY_Pos (16U)
<> 128:9bcdf88f62b0 16359 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 16360 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
<> 128:9bcdf88f62b0 16361 #define USART_ISR_CMF_Pos (17U)
<> 128:9bcdf88f62b0 16362 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 16363 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
<> 128:9bcdf88f62b0 16364 #define USART_ISR_SBKF_Pos (18U)
<> 128:9bcdf88f62b0 16365 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 16366 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
<> 128:9bcdf88f62b0 16367 #define USART_ISR_RWU_Pos (19U)
<> 128:9bcdf88f62b0 16368 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 16369 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
<> 128:9bcdf88f62b0 16370 #define USART_ISR_WUF_Pos (20U)
<> 128:9bcdf88f62b0 16371 #define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 16372 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
<> 128:9bcdf88f62b0 16373 #define USART_ISR_TEACK_Pos (21U)
<> 128:9bcdf88f62b0 16374 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 16375 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
<> 128:9bcdf88f62b0 16376 #define USART_ISR_REACK_Pos (22U)
<> 128:9bcdf88f62b0 16377 #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 16378 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
<> 128:9bcdf88f62b0 16379
<> 128:9bcdf88f62b0 16380 /******************* Bit definition for USART_ICR register ******************/
<> 128:9bcdf88f62b0 16381 #define USART_ICR_PECF_Pos (0U)
<> 128:9bcdf88f62b0 16382 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16383 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
<> 128:9bcdf88f62b0 16384 #define USART_ICR_FECF_Pos (1U)
<> 128:9bcdf88f62b0 16385 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16386 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
<> 128:9bcdf88f62b0 16387 #define USART_ICR_NCF_Pos (2U)
<> 128:9bcdf88f62b0 16388 #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16389 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
<> 128:9bcdf88f62b0 16390 #define USART_ICR_ORECF_Pos (3U)
<> 128:9bcdf88f62b0 16391 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 16392 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
<> 128:9bcdf88f62b0 16393 #define USART_ICR_IDLECF_Pos (4U)
<> 128:9bcdf88f62b0 16394 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 16395 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
<> 128:9bcdf88f62b0 16396 #define USART_ICR_TCCF_Pos (6U)
<> 128:9bcdf88f62b0 16397 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 16398 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
<> 128:9bcdf88f62b0 16399 #define USART_ICR_LBDCF_Pos (8U)
<> 128:9bcdf88f62b0 16400 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 16401 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
<> 128:9bcdf88f62b0 16402 #define USART_ICR_CTSCF_Pos (9U)
<> 128:9bcdf88f62b0 16403 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 16404 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
<> 128:9bcdf88f62b0 16405 #define USART_ICR_RTOCF_Pos (11U)
<> 128:9bcdf88f62b0 16406 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 16407 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
<> 128:9bcdf88f62b0 16408 #define USART_ICR_EOBCF_Pos (12U)
<> 128:9bcdf88f62b0 16409 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 16410 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
<> 128:9bcdf88f62b0 16411 #define USART_ICR_CMCF_Pos (17U)
<> 128:9bcdf88f62b0 16412 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 16413 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
<> 128:9bcdf88f62b0 16414 #define USART_ICR_WUCF_Pos (20U)
<> 128:9bcdf88f62b0 16415 #define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 16416 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
<> 128:9bcdf88f62b0 16417
<> 128:9bcdf88f62b0 16418 /******************* Bit definition for USART_RDR register ******************/
<> 128:9bcdf88f62b0 16419 #define USART_RDR_RDR_Pos (0U)
<> 128:9bcdf88f62b0 16420 #define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
<> 128:9bcdf88f62b0 16421 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
<> 128:9bcdf88f62b0 16422
<> 128:9bcdf88f62b0 16423 /******************* Bit definition for USART_TDR register ******************/
<> 128:9bcdf88f62b0 16424 #define USART_TDR_TDR_Pos (0U)
<> 128:9bcdf88f62b0 16425 #define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
<> 128:9bcdf88f62b0 16426 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
<> 128:9bcdf88f62b0 16427
<> 128:9bcdf88f62b0 16428 /******************************************************************************/
<> 128:9bcdf88f62b0 16429 /* */
<> 128:9bcdf88f62b0 16430 /* Single Wire Protocol Master Interface (SWPMI) */
<> 128:9bcdf88f62b0 16431 /* */
<> 128:9bcdf88f62b0 16432 /******************************************************************************/
<> 128:9bcdf88f62b0 16433
<> 128:9bcdf88f62b0 16434 /******************* Bit definition for SWPMI_CR register ********************/
<> 128:9bcdf88f62b0 16435 #define SWPMI_CR_RXDMA_Pos (0U)
<> 128:9bcdf88f62b0 16436 #define SWPMI_CR_RXDMA_Msk (0x1U << SWPMI_CR_RXDMA_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16437 #define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk /*!<Reception DMA enable */
<> 128:9bcdf88f62b0 16438 #define SWPMI_CR_TXDMA_Pos (1U)
<> 128:9bcdf88f62b0 16439 #define SWPMI_CR_TXDMA_Msk (0x1U << SWPMI_CR_TXDMA_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16440 #define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk /*!<Transmission DMA enable */
<> 128:9bcdf88f62b0 16441 #define SWPMI_CR_RXMODE_Pos (2U)
<> 128:9bcdf88f62b0 16442 #define SWPMI_CR_RXMODE_Msk (0x1U << SWPMI_CR_RXMODE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16443 #define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk /*!<Reception buffering mode */
<> 128:9bcdf88f62b0 16444 #define SWPMI_CR_TXMODE_Pos (3U)
<> 128:9bcdf88f62b0 16445 #define SWPMI_CR_TXMODE_Msk (0x1U << SWPMI_CR_TXMODE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 16446 #define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk /*!<Transmission buffering mode */
<> 128:9bcdf88f62b0 16447 #define SWPMI_CR_LPBK_Pos (4U)
<> 128:9bcdf88f62b0 16448 #define SWPMI_CR_LPBK_Msk (0x1U << SWPMI_CR_LPBK_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 16449 #define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk /*!<Loopback mode enable */
<> 128:9bcdf88f62b0 16450 #define SWPMI_CR_SWPACT_Pos (5U)
<> 128:9bcdf88f62b0 16451 #define SWPMI_CR_SWPACT_Msk (0x1U << SWPMI_CR_SWPACT_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 16452 #define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk /*!<Single wire protocol master interface activate */
<> 128:9bcdf88f62b0 16453 #define SWPMI_CR_DEACT_Pos (10U)
<> 128:9bcdf88f62b0 16454 #define SWPMI_CR_DEACT_Msk (0x1U << SWPMI_CR_DEACT_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 16455 #define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk /*!<Single wire protocol master interface deactivate */
<> 128:9bcdf88f62b0 16456
<> 128:9bcdf88f62b0 16457 /******************* Bit definition for SWPMI_BRR register ********************/
<> 128:9bcdf88f62b0 16458 #define SWPMI_BRR_BR_Pos (0U)
<> 128:9bcdf88f62b0 16459 #define SWPMI_BRR_BR_Msk (0x3FU << SWPMI_BRR_BR_Pos) /*!< 0x0000003F */
<> 128:9bcdf88f62b0 16460 #define SWPMI_BRR_BR SWPMI_BRR_BR_Msk /*!<BR[5:0] bits (Bitrate prescaler) */
<> 128:9bcdf88f62b0 16461
<> 128:9bcdf88f62b0 16462 /******************* Bit definition for SWPMI_ISR register ********************/
<> 128:9bcdf88f62b0 16463 #define SWPMI_ISR_RXBFF_Pos (0U)
<> 128:9bcdf88f62b0 16464 #define SWPMI_ISR_RXBFF_Msk (0x1U << SWPMI_ISR_RXBFF_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16465 #define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk /*!<Receive buffer full flag */
<> 128:9bcdf88f62b0 16466 #define SWPMI_ISR_TXBEF_Pos (1U)
<> 128:9bcdf88f62b0 16467 #define SWPMI_ISR_TXBEF_Msk (0x1U << SWPMI_ISR_TXBEF_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16468 #define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk /*!<Transmit buffer empty flag */
<> 128:9bcdf88f62b0 16469 #define SWPMI_ISR_RXBERF_Pos (2U)
<> 128:9bcdf88f62b0 16470 #define SWPMI_ISR_RXBERF_Msk (0x1U << SWPMI_ISR_RXBERF_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16471 #define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk /*!<Receive CRC error flag */
<> 128:9bcdf88f62b0 16472 #define SWPMI_ISR_RXOVRF_Pos (3U)
<> 128:9bcdf88f62b0 16473 #define SWPMI_ISR_RXOVRF_Msk (0x1U << SWPMI_ISR_RXOVRF_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 16474 #define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk /*!<Receive overrun error flag */
<> 128:9bcdf88f62b0 16475 #define SWPMI_ISR_TXUNRF_Pos (4U)
<> 128:9bcdf88f62b0 16476 #define SWPMI_ISR_TXUNRF_Msk (0x1U << SWPMI_ISR_TXUNRF_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 16477 #define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk /*!<Transmit underrun error flag */
<> 128:9bcdf88f62b0 16478 #define SWPMI_ISR_RXNE_Pos (5U)
<> 128:9bcdf88f62b0 16479 #define SWPMI_ISR_RXNE_Msk (0x1U << SWPMI_ISR_RXNE_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 16480 #define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk /*!<Receive data register not empty */
<> 128:9bcdf88f62b0 16481 #define SWPMI_ISR_TXE_Pos (6U)
<> 128:9bcdf88f62b0 16482 #define SWPMI_ISR_TXE_Msk (0x1U << SWPMI_ISR_TXE_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 16483 #define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk /*!<Transmit data register empty */
<> 128:9bcdf88f62b0 16484 #define SWPMI_ISR_TCF_Pos (7U)
<> 128:9bcdf88f62b0 16485 #define SWPMI_ISR_TCF_Msk (0x1U << SWPMI_ISR_TCF_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 16486 #define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk /*!<Transfer complete flag */
<> 128:9bcdf88f62b0 16487 #define SWPMI_ISR_SRF_Pos (8U)
<> 128:9bcdf88f62b0 16488 #define SWPMI_ISR_SRF_Msk (0x1U << SWPMI_ISR_SRF_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 16489 #define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk /*!<Slave resume flag */
<> 128:9bcdf88f62b0 16490 #define SWPMI_ISR_SUSP_Pos (9U)
<> 128:9bcdf88f62b0 16491 #define SWPMI_ISR_SUSP_Msk (0x1U << SWPMI_ISR_SUSP_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 16492 #define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk /*!<SUSPEND flag */
<> 128:9bcdf88f62b0 16493 #define SWPMI_ISR_DEACTF_Pos (10U)
<> 128:9bcdf88f62b0 16494 #define SWPMI_ISR_DEACTF_Msk (0x1U << SWPMI_ISR_DEACTF_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 16495 #define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk /*!<DEACTIVATED flag */
<> 128:9bcdf88f62b0 16496
<> 128:9bcdf88f62b0 16497 /******************* Bit definition for SWPMI_ICR register ********************/
<> 128:9bcdf88f62b0 16498 #define SWPMI_ICR_CRXBFF_Pos (0U)
<> 128:9bcdf88f62b0 16499 #define SWPMI_ICR_CRXBFF_Msk (0x1U << SWPMI_ICR_CRXBFF_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16500 #define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk /*!<Clear receive buffer full flag */
<> 128:9bcdf88f62b0 16501 #define SWPMI_ICR_CTXBEF_Pos (1U)
<> 128:9bcdf88f62b0 16502 #define SWPMI_ICR_CTXBEF_Msk (0x1U << SWPMI_ICR_CTXBEF_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16503 #define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk /*!<Clear transmit buffer empty flag */
<> 128:9bcdf88f62b0 16504 #define SWPMI_ICR_CRXBERF_Pos (2U)
<> 128:9bcdf88f62b0 16505 #define SWPMI_ICR_CRXBERF_Msk (0x1U << SWPMI_ICR_CRXBERF_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16506 #define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk /*!<Clear receive CRC error flag */
<> 128:9bcdf88f62b0 16507 #define SWPMI_ICR_CRXOVRF_Pos (3U)
<> 128:9bcdf88f62b0 16508 #define SWPMI_ICR_CRXOVRF_Msk (0x1U << SWPMI_ICR_CRXOVRF_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 16509 #define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk /*!<Clear receive overrun error flag */
<> 128:9bcdf88f62b0 16510 #define SWPMI_ICR_CTXUNRF_Pos (4U)
<> 128:9bcdf88f62b0 16511 #define SWPMI_ICR_CTXUNRF_Msk (0x1U << SWPMI_ICR_CTXUNRF_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 16512 #define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk /*!<Clear transmit underrun error flag */
<> 128:9bcdf88f62b0 16513 #define SWPMI_ICR_CTCF_Pos (7U)
<> 128:9bcdf88f62b0 16514 #define SWPMI_ICR_CTCF_Msk (0x1U << SWPMI_ICR_CTCF_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 16515 #define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk /*!<Clear transfer complete flag */
<> 128:9bcdf88f62b0 16516 #define SWPMI_ICR_CSRF_Pos (8U)
<> 128:9bcdf88f62b0 16517 #define SWPMI_ICR_CSRF_Msk (0x1U << SWPMI_ICR_CSRF_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 16518 #define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk /*!<Clear slave resume flag */
<> 128:9bcdf88f62b0 16519
<> 128:9bcdf88f62b0 16520 /******************* Bit definition for SWPMI_IER register ********************/
<> 128:9bcdf88f62b0 16521 #define SWPMI_IER_SRIE_Pos (8U)
<> 128:9bcdf88f62b0 16522 #define SWPMI_IER_SRIE_Msk (0x1U << SWPMI_IER_SRIE_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 16523 #define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk /*!<Slave resume interrupt enable */
<> 128:9bcdf88f62b0 16524 #define SWPMI_IER_TCIE_Pos (7U)
<> 128:9bcdf88f62b0 16525 #define SWPMI_IER_TCIE_Msk (0x1U << SWPMI_IER_TCIE_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 16526 #define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk /*!<Transmit complete interrupt enable */
<> 128:9bcdf88f62b0 16527 #define SWPMI_IER_TIE_Pos (6U)
<> 128:9bcdf88f62b0 16528 #define SWPMI_IER_TIE_Msk (0x1U << SWPMI_IER_TIE_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 16529 #define SWPMI_IER_TIE SWPMI_IER_TIE_Msk /*!<Transmit interrupt enable */
<> 128:9bcdf88f62b0 16530 #define SWPMI_IER_RIE_Pos (5U)
<> 128:9bcdf88f62b0 16531 #define SWPMI_IER_RIE_Msk (0x1U << SWPMI_IER_RIE_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 16532 #define SWPMI_IER_RIE SWPMI_IER_RIE_Msk /*!<Receive interrupt enable */
<> 128:9bcdf88f62b0 16533 #define SWPMI_IER_TXUNRIE_Pos (4U)
<> 128:9bcdf88f62b0 16534 #define SWPMI_IER_TXUNRIE_Msk (0x1U << SWPMI_IER_TXUNRIE_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 16535 #define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk /*!<Transmit underrun error interrupt enable */
<> 128:9bcdf88f62b0 16536 #define SWPMI_IER_RXOVRIE_Pos (3U)
<> 128:9bcdf88f62b0 16537 #define SWPMI_IER_RXOVRIE_Msk (0x1U << SWPMI_IER_RXOVRIE_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 16538 #define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk /*!<Receive overrun error interrupt enable */
<> 128:9bcdf88f62b0 16539 #define SWPMI_IER_RXBERIE_Pos (2U)
<> 128:9bcdf88f62b0 16540 #define SWPMI_IER_RXBERIE_Msk (0x1U << SWPMI_IER_RXBERIE_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16541 #define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk /*!<Receive CRC error interrupt enable */
<> 128:9bcdf88f62b0 16542 #define SWPMI_IER_TXBEIE_Pos (1U)
<> 128:9bcdf88f62b0 16543 #define SWPMI_IER_TXBEIE_Msk (0x1U << SWPMI_IER_TXBEIE_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16544 #define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk /*!<Transmit buffer empty interrupt enable */
<> 128:9bcdf88f62b0 16545 #define SWPMI_IER_RXBFIE_Pos (0U)
<> 128:9bcdf88f62b0 16546 #define SWPMI_IER_RXBFIE_Msk (0x1U << SWPMI_IER_RXBFIE_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16547 #define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk /*!<Receive buffer full interrupt enable */
<> 128:9bcdf88f62b0 16548
<> 128:9bcdf88f62b0 16549 /******************* Bit definition for SWPMI_RFL register ********************/
<> 128:9bcdf88f62b0 16550 #define SWPMI_RFL_RFL_Pos (0U)
<> 128:9bcdf88f62b0 16551 #define SWPMI_RFL_RFL_Msk (0x1FU << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
<> 128:9bcdf88f62b0 16552 #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
<> 128:9bcdf88f62b0 16553 #define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
<> 128:9bcdf88f62b0 16554
<> 128:9bcdf88f62b0 16555 /******************* Bit definition for SWPMI_TDR register ********************/
<> 128:9bcdf88f62b0 16556 #define SWPMI_TDR_TD_Pos (0U)
<> 128:9bcdf88f62b0 16557 #define SWPMI_TDR_TD_Msk (0xFFFFFFFFU << SWPMI_TDR_TD_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 16558 #define SWPMI_TDR_TD SWPMI_TDR_TD_Msk /*!<Transmit Data Register */
<> 128:9bcdf88f62b0 16559
<> 128:9bcdf88f62b0 16560 /******************* Bit definition for SWPMI_RDR register ********************/
<> 128:9bcdf88f62b0 16561 #define SWPMI_RDR_RD_Pos (0U)
<> 128:9bcdf88f62b0 16562 #define SWPMI_RDR_RD_Msk (0xFFFFFFFFU << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 16563 #define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
<> 128:9bcdf88f62b0 16564
<> 128:9bcdf88f62b0 16565 /******************* Bit definition for SWPMI_OR register ********************/
<> 128:9bcdf88f62b0 16566 #define SWPMI_OR_TBYP_Pos (0U)
<> 128:9bcdf88f62b0 16567 #define SWPMI_OR_TBYP_Msk (0x1U << SWPMI_OR_TBYP_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16568 #define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk /*!<SWP Transceiver Bypass */
<> 128:9bcdf88f62b0 16569 #define SWPMI_OR_CLASS_Pos (1U)
<> 128:9bcdf88f62b0 16570 #define SWPMI_OR_CLASS_Msk (0x1U << SWPMI_OR_CLASS_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16571 #define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk /*!<SWP Voltage Class selection */
<> 128:9bcdf88f62b0 16572
<> 128:9bcdf88f62b0 16573 /******************************************************************************/
<> 128:9bcdf88f62b0 16574 /* */
<> 128:9bcdf88f62b0 16575 /* VREFBUF */
<> 128:9bcdf88f62b0 16576 /* */
<> 128:9bcdf88f62b0 16577 /******************************************************************************/
<> 128:9bcdf88f62b0 16578 /******************* Bit definition for VREFBUF_CSR register ****************/
<> 128:9bcdf88f62b0 16579 #define VREFBUF_CSR_ENVR_Pos (0U)
<> 128:9bcdf88f62b0 16580 #define VREFBUF_CSR_ENVR_Msk (0x1U << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16581 #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
<> 128:9bcdf88f62b0 16582 #define VREFBUF_CSR_HIZ_Pos (1U)
<> 128:9bcdf88f62b0 16583 #define VREFBUF_CSR_HIZ_Msk (0x1U << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16584 #define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
<> 128:9bcdf88f62b0 16585 #define VREFBUF_CSR_VRS_Pos (2U)
<> 128:9bcdf88f62b0 16586 #define VREFBUF_CSR_VRS_Msk (0x1U << VREFBUF_CSR_VRS_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16587 #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
<> 128:9bcdf88f62b0 16588 #define VREFBUF_CSR_VRR_Pos (3U)
<> 128:9bcdf88f62b0 16589 #define VREFBUF_CSR_VRR_Msk (0x1U << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 16590 #define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
<> 128:9bcdf88f62b0 16591
<> 128:9bcdf88f62b0 16592 /******************* Bit definition for VREFBUF_CCR register ******************/
<> 128:9bcdf88f62b0 16593 #define VREFBUF_CCR_TRIM_Pos (0U)
<> 128:9bcdf88f62b0 16594 #define VREFBUF_CCR_TRIM_Msk (0x3FU << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
<> 128:9bcdf88f62b0 16595 #define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
<> 128:9bcdf88f62b0 16596
<> 128:9bcdf88f62b0 16597 /******************************************************************************/
<> 128:9bcdf88f62b0 16598 /* */
<> 128:9bcdf88f62b0 16599 /* Window WATCHDOG */
<> 128:9bcdf88f62b0 16600 /* */
<> 128:9bcdf88f62b0 16601 /******************************************************************************/
<> 128:9bcdf88f62b0 16602 /******************* Bit definition for WWDG_CR register ********************/
<> 128:9bcdf88f62b0 16603 #define WWDG_CR_T_Pos (0U)
<> 128:9bcdf88f62b0 16604 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
<> 128:9bcdf88f62b0 16605 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
<> 128:9bcdf88f62b0 16606 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16607 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16608 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16609 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 16610 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 16611 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 16612 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 16613
<> 128:9bcdf88f62b0 16614 #define WWDG_CR_WDGA_Pos (7U)
<> 128:9bcdf88f62b0 16615 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 16616 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
<> 128:9bcdf88f62b0 16617
<> 128:9bcdf88f62b0 16618 /******************* Bit definition for WWDG_CFR register *******************/
<> 128:9bcdf88f62b0 16619 #define WWDG_CFR_W_Pos (0U)
<> 128:9bcdf88f62b0 16620 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
<> 128:9bcdf88f62b0 16621 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
<> 128:9bcdf88f62b0 16622 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16623 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16624 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16625 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 16626 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 16627 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 16628 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 16629
<> 128:9bcdf88f62b0 16630 #define WWDG_CFR_WDGTB_Pos (7U)
<> 128:9bcdf88f62b0 16631 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
<> 128:9bcdf88f62b0 16632 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
<> 128:9bcdf88f62b0 16633 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 16634 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 16635
<> 128:9bcdf88f62b0 16636 #define WWDG_CFR_EWI_Pos (9U)
<> 128:9bcdf88f62b0 16637 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 16638 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
<> 128:9bcdf88f62b0 16639
<> 128:9bcdf88f62b0 16640 /******************* Bit definition for WWDG_SR register ********************/
<> 128:9bcdf88f62b0 16641 #define WWDG_SR_EWIF_Pos (0U)
<> 128:9bcdf88f62b0 16642 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16643 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
<> 128:9bcdf88f62b0 16644
<> 128:9bcdf88f62b0 16645
<> 128:9bcdf88f62b0 16646 /******************************************************************************/
<> 128:9bcdf88f62b0 16647 /* */
<> 128:9bcdf88f62b0 16648 /* Debug MCU */
<> 128:9bcdf88f62b0 16649 /* */
<> 128:9bcdf88f62b0 16650 /******************************************************************************/
<> 128:9bcdf88f62b0 16651 /******************** Bit definition for DBGMCU_IDCODE register *************/
<> 128:9bcdf88f62b0 16652 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
<> 128:9bcdf88f62b0 16653 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
<> 128:9bcdf88f62b0 16654 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
<> 128:9bcdf88f62b0 16655 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
<> 128:9bcdf88f62b0 16656 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
<> 128:9bcdf88f62b0 16657 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
<> 128:9bcdf88f62b0 16658
<> 128:9bcdf88f62b0 16659 /******************** Bit definition for DBGMCU_CR register *****************/
<> 128:9bcdf88f62b0 16660 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
<> 128:9bcdf88f62b0 16661 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16662 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
<> 128:9bcdf88f62b0 16663 #define DBGMCU_CR_DBG_STOP_Pos (1U)
<> 128:9bcdf88f62b0 16664 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16665 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
<> 128:9bcdf88f62b0 16666 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
<> 128:9bcdf88f62b0 16667 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16668 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
<> 128:9bcdf88f62b0 16669 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
<> 128:9bcdf88f62b0 16670 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 16671 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
<> 128:9bcdf88f62b0 16672
<> 128:9bcdf88f62b0 16673 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
<> 128:9bcdf88f62b0 16674 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
<> 128:9bcdf88f62b0 16675 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
<> 128:9bcdf88f62b0 16676 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 16677 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 16678
<> 128:9bcdf88f62b0 16679 /******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
<> 128:9bcdf88f62b0 16680 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
<> 128:9bcdf88f62b0 16681 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16682 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
<> 128:9bcdf88f62b0 16683 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
<> 128:9bcdf88f62b0 16684 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16685 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
<> 128:9bcdf88f62b0 16686 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
<> 128:9bcdf88f62b0 16687 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16688 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
<> 128:9bcdf88f62b0 16689 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U)
<> 128:9bcdf88f62b0 16690 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 16691 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
<> 128:9bcdf88f62b0 16692 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
<> 128:9bcdf88f62b0 16693 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 16694 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
<> 128:9bcdf88f62b0 16695 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
<> 128:9bcdf88f62b0 16696 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 16697 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
<> 128:9bcdf88f62b0 16698 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
<> 128:9bcdf88f62b0 16699 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 16700 #define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
<> 128:9bcdf88f62b0 16701 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
<> 128:9bcdf88f62b0 16702 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 16703 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
<> 128:9bcdf88f62b0 16704 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
<> 128:9bcdf88f62b0 16705 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 16706 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
<> 128:9bcdf88f62b0 16707 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
<> 128:9bcdf88f62b0 16708 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 16709 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
<> 128:9bcdf88f62b0 16710 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
<> 128:9bcdf88f62b0 16711 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 16712 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
<> 128:9bcdf88f62b0 16713 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (23U)
<> 128:9bcdf88f62b0 16714 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 16715 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
<> 128:9bcdf88f62b0 16716 #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos (25U)
<> 128:9bcdf88f62b0 16717 #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 16718 #define DBGMCU_APB1FZR1_DBG_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk
<> 128:9bcdf88f62b0 16719 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
<> 128:9bcdf88f62b0 16720 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 16721 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
<> 128:9bcdf88f62b0 16722
<> 128:9bcdf88f62b0 16723 /******************** Bit definition for DBGMCU_APB1FZR2 register **********/
<> 128:9bcdf88f62b0 16724 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)
<> 128:9bcdf88f62b0 16725 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 16726 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
<> 128:9bcdf88f62b0 16727
<> 128:9bcdf88f62b0 16728 /******************** Bit definition for DBGMCU_APB2FZ register ************/
<> 128:9bcdf88f62b0 16729 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
<> 128:9bcdf88f62b0 16730 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 16731 #define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
<> 128:9bcdf88f62b0 16732 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
<> 128:9bcdf88f62b0 16733 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 16734 #define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
<> 128:9bcdf88f62b0 16735 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
<> 128:9bcdf88f62b0 16736 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 16737 #define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
<> 128:9bcdf88f62b0 16738 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
<> 128:9bcdf88f62b0 16739 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 16740 #define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
<> 128:9bcdf88f62b0 16741 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
<> 128:9bcdf88f62b0 16742 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 16743 #define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
<> 128:9bcdf88f62b0 16744
<> 128:9bcdf88f62b0 16745 /******************************************************************************/
<> 128:9bcdf88f62b0 16746 /* */
<> 128:9bcdf88f62b0 16747 /* USB_OTG */
<> 128:9bcdf88f62b0 16748 /* */
<> 128:9bcdf88f62b0 16749 /******************************************************************************/
<> 128:9bcdf88f62b0 16750 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
<> 128:9bcdf88f62b0 16751 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
<> 128:9bcdf88f62b0 16752 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16753 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
<> 128:9bcdf88f62b0 16754 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
<> 128:9bcdf88f62b0 16755 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16756 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
<> 128:9bcdf88f62b0 16757 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
<> 128:9bcdf88f62b0 16758 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16759 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
<> 128:9bcdf88f62b0 16760 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
<> 128:9bcdf88f62b0 16761 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 16762 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
<> 128:9bcdf88f62b0 16763 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
<> 128:9bcdf88f62b0 16764 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 16765 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
<> 128:9bcdf88f62b0 16766 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
<> 128:9bcdf88f62b0 16767 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 16768 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
<> 128:9bcdf88f62b0 16769 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
<> 128:9bcdf88f62b0 16770 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 16771 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
<> 128:9bcdf88f62b0 16772 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
<> 128:9bcdf88f62b0 16773 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 16774 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
<> 128:9bcdf88f62b0 16775 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
<> 128:9bcdf88f62b0 16776 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 16777 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/
<> 128:9bcdf88f62b0 16778
<> 128:9bcdf88f62b0 16779 /******************** Bit definition for USB_OTG_HCFG register ********************/
<> 128:9bcdf88f62b0 16780
<> 128:9bcdf88f62b0 16781 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
<> 128:9bcdf88f62b0 16782 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 16783 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
<> 128:9bcdf88f62b0 16784 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16785 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16786 #define USB_OTG_HCFG_FSLSS_Pos (2U)
<> 128:9bcdf88f62b0 16787 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16788 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
<> 128:9bcdf88f62b0 16789
<> 128:9bcdf88f62b0 16790 /******************** Bit definition for USB_OTG_DCFG register ********************/
<> 128:9bcdf88f62b0 16791
<> 128:9bcdf88f62b0 16792 #define USB_OTG_DCFG_DSPD_Pos (0U)
<> 128:9bcdf88f62b0 16793 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
<> 128:9bcdf88f62b0 16794 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
<> 128:9bcdf88f62b0 16795 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16796 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16797 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
<> 128:9bcdf88f62b0 16798 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16799 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
<> 128:9bcdf88f62b0 16800 #define USB_OTG_DCFG_DAD_Pos (4U)
<> 128:9bcdf88f62b0 16801 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
<> 128:9bcdf88f62b0 16802 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
<> 128:9bcdf88f62b0 16803 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 16804 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 16805 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 16806 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 16807 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 16808 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 16809 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 16810 #define USB_OTG_DCFG_PFIVL_Pos (11U)
<> 128:9bcdf88f62b0 16811 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
<> 128:9bcdf88f62b0 16812 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
<> 128:9bcdf88f62b0 16813 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 16814 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 16815 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
<> 128:9bcdf88f62b0 16816 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
<> 128:9bcdf88f62b0 16817 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
<> 128:9bcdf88f62b0 16818 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 16819 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 16820
<> 128:9bcdf88f62b0 16821 /******************** Bit definition for USB_OTG_PCGCR register ********************/
<> 128:9bcdf88f62b0 16822 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
<> 128:9bcdf88f62b0 16823 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16824 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
<> 128:9bcdf88f62b0 16825 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
<> 128:9bcdf88f62b0 16826 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16827 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
<> 128:9bcdf88f62b0 16828 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
<> 128:9bcdf88f62b0 16829 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 16830 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
<> 128:9bcdf88f62b0 16831
<> 128:9bcdf88f62b0 16832 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
<> 128:9bcdf88f62b0 16833 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
<> 128:9bcdf88f62b0 16834 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16835 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
<> 128:9bcdf88f62b0 16836 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
<> 128:9bcdf88f62b0 16837 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 16838 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
<> 128:9bcdf88f62b0 16839 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
<> 128:9bcdf88f62b0 16840 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 16841 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
<> 128:9bcdf88f62b0 16842 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
<> 128:9bcdf88f62b0 16843 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 16844 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
<> 128:9bcdf88f62b0 16845 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
<> 128:9bcdf88f62b0 16846 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 16847 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
<> 128:9bcdf88f62b0 16848 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
<> 128:9bcdf88f62b0 16849 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 16850 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
<> 128:9bcdf88f62b0 16851
<> 128:9bcdf88f62b0 16852 /******************** Bit definition for USB_OTG_DCTL register ********************/
<> 128:9bcdf88f62b0 16853 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
<> 128:9bcdf88f62b0 16854 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16855 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
<> 128:9bcdf88f62b0 16856 #define USB_OTG_DCTL_SDIS_Pos (1U)
<> 128:9bcdf88f62b0 16857 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16858 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
<> 128:9bcdf88f62b0 16859 #define USB_OTG_DCTL_GINSTS_Pos (2U)
<> 128:9bcdf88f62b0 16860 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16861 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
<> 128:9bcdf88f62b0 16862 #define USB_OTG_DCTL_GONSTS_Pos (3U)
<> 128:9bcdf88f62b0 16863 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 16864 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
<> 128:9bcdf88f62b0 16865
<> 128:9bcdf88f62b0 16866 #define USB_OTG_DCTL_TCTL_Pos (4U)
<> 128:9bcdf88f62b0 16867 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
<> 128:9bcdf88f62b0 16868 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
<> 128:9bcdf88f62b0 16869 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 16870 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 16871 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 16872 #define USB_OTG_DCTL_SGINAK_Pos (7U)
<> 128:9bcdf88f62b0 16873 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 16874 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
<> 128:9bcdf88f62b0 16875 #define USB_OTG_DCTL_CGINAK_Pos (8U)
<> 128:9bcdf88f62b0 16876 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 16877 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
<> 128:9bcdf88f62b0 16878 #define USB_OTG_DCTL_SGONAK_Pos (9U)
<> 128:9bcdf88f62b0 16879 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 16880 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
<> 128:9bcdf88f62b0 16881 #define USB_OTG_DCTL_CGONAK_Pos (10U)
<> 128:9bcdf88f62b0 16882 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 16883 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
<> 128:9bcdf88f62b0 16884 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
<> 128:9bcdf88f62b0 16885 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 16886 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
<> 128:9bcdf88f62b0 16887
<> 128:9bcdf88f62b0 16888 /******************** Bit definition for USB_OTG_HFIR register ********************/
<> 128:9bcdf88f62b0 16889 #define USB_OTG_HFIR_FRIVL_Pos (0U)
<> 128:9bcdf88f62b0 16890 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 16891 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
<> 128:9bcdf88f62b0 16892
<> 128:9bcdf88f62b0 16893 /******************** Bit definition for USB_OTG_HFNUM register ********************/
<> 128:9bcdf88f62b0 16894 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
<> 128:9bcdf88f62b0 16895 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 16896 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
<> 128:9bcdf88f62b0 16897 #define USB_OTG_HFNUM_FTREM_Pos (16U)
<> 128:9bcdf88f62b0 16898 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
<> 128:9bcdf88f62b0 16899 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
<> 128:9bcdf88f62b0 16900
<> 128:9bcdf88f62b0 16901 /******************** Bit definition for USB_OTG_DSTS register ********************/
<> 128:9bcdf88f62b0 16902 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
<> 128:9bcdf88f62b0 16903 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16904 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
<> 128:9bcdf88f62b0 16905
<> 128:9bcdf88f62b0 16906 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
<> 128:9bcdf88f62b0 16907 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
<> 128:9bcdf88f62b0 16908 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
<> 128:9bcdf88f62b0 16909 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16910 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16911 #define USB_OTG_DSTS_EERR_Pos (3U)
<> 128:9bcdf88f62b0 16912 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 16913 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
<> 128:9bcdf88f62b0 16914 #define USB_OTG_DSTS_FNSOF_Pos (8U)
<> 128:9bcdf88f62b0 16915 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
<> 128:9bcdf88f62b0 16916 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
<> 128:9bcdf88f62b0 16917
<> 128:9bcdf88f62b0 16918 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
<> 128:9bcdf88f62b0 16919 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
<> 128:9bcdf88f62b0 16920 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16921 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
<> 128:9bcdf88f62b0 16922 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
<> 128:9bcdf88f62b0 16923 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
<> 128:9bcdf88f62b0 16924 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
<> 128:9bcdf88f62b0 16925 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16926 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16927 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 16928 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 16929 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
<> 128:9bcdf88f62b0 16930 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 16931 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
<> 128:9bcdf88f62b0 16932 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
<> 128:9bcdf88f62b0 16933 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 16934 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
<> 128:9bcdf88f62b0 16935 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
<> 128:9bcdf88f62b0 16936 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 16937 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
<> 128:9bcdf88f62b0 16938
<> 128:9bcdf88f62b0 16939 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
<> 128:9bcdf88f62b0 16940
<> 128:9bcdf88f62b0 16941 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
<> 128:9bcdf88f62b0 16942 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
<> 128:9bcdf88f62b0 16943 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
<> 128:9bcdf88f62b0 16944 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 16945 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 16946 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 16947 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
<> 128:9bcdf88f62b0 16948 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 16949 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
<> 128:9bcdf88f62b0 16950 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
<> 128:9bcdf88f62b0 16951 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 16952 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
<> 128:9bcdf88f62b0 16953 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
<> 128:9bcdf88f62b0 16954 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 16955 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
<> 128:9bcdf88f62b0 16956 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
<> 128:9bcdf88f62b0 16957 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
<> 128:9bcdf88f62b0 16958 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
<> 128:9bcdf88f62b0 16959 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 16960 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 16961 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 16962 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 16963 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
<> 128:9bcdf88f62b0 16964 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 16965 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
<> 128:9bcdf88f62b0 16966 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
<> 128:9bcdf88f62b0 16967 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 16968 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
<> 128:9bcdf88f62b0 16969 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
<> 128:9bcdf88f62b0 16970 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 16971 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
<> 128:9bcdf88f62b0 16972 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
<> 128:9bcdf88f62b0 16973 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 16974 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
<> 128:9bcdf88f62b0 16975 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
<> 128:9bcdf88f62b0 16976 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 16977 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
<> 128:9bcdf88f62b0 16978 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
<> 128:9bcdf88f62b0 16979 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 16980 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
<> 128:9bcdf88f62b0 16981 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
<> 128:9bcdf88f62b0 16982 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 16983 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
<> 128:9bcdf88f62b0 16984 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
<> 128:9bcdf88f62b0 16985 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 16986 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
<> 128:9bcdf88f62b0 16987 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
<> 128:9bcdf88f62b0 16988 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 16989 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
<> 128:9bcdf88f62b0 16990 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
<> 128:9bcdf88f62b0 16991 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 16992 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
<> 128:9bcdf88f62b0 16993 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
<> 128:9bcdf88f62b0 16994 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 16995 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
<> 128:9bcdf88f62b0 16996 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
<> 128:9bcdf88f62b0 16997 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 16998 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
<> 128:9bcdf88f62b0 16999 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
<> 128:9bcdf88f62b0 17000 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 17001 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
<> 128:9bcdf88f62b0 17002
<> 128:9bcdf88f62b0 17003 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
<> 128:9bcdf88f62b0 17004 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
<> 128:9bcdf88f62b0 17005 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 17006 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
<> 128:9bcdf88f62b0 17007 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
<> 128:9bcdf88f62b0 17008 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 17009 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
<> 128:9bcdf88f62b0 17010 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
<> 128:9bcdf88f62b0 17011 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 17012 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
<> 128:9bcdf88f62b0 17013 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
<> 128:9bcdf88f62b0 17014 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 17015 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
<> 128:9bcdf88f62b0 17016 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
<> 128:9bcdf88f62b0 17017 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 17018 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
<> 128:9bcdf88f62b0 17019 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
<> 128:9bcdf88f62b0 17020 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
<> 128:9bcdf88f62b0 17021 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
<> 128:9bcdf88f62b0 17022 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 17023 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 17024 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 17025 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 17026 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 17027 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
<> 128:9bcdf88f62b0 17028 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 17029 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
<> 128:9bcdf88f62b0 17030 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
<> 128:9bcdf88f62b0 17031 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 17032 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
<> 128:9bcdf88f62b0 17033
<> 128:9bcdf88f62b0 17034 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
<> 128:9bcdf88f62b0 17035 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
<> 128:9bcdf88f62b0 17036 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 17037 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
<> 128:9bcdf88f62b0 17038 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
<> 128:9bcdf88f62b0 17039 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 17040 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
<> 128:9bcdf88f62b0 17041 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
<> 128:9bcdf88f62b0 17042 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 17043 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
<> 128:9bcdf88f62b0 17044 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
<> 128:9bcdf88f62b0 17045 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 17046 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
<> 128:9bcdf88f62b0 17047 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
<> 128:9bcdf88f62b0 17048 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 17049 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
<> 128:9bcdf88f62b0 17050 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
<> 128:9bcdf88f62b0 17051 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 17052 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
<> 128:9bcdf88f62b0 17053 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
<> 128:9bcdf88f62b0 17054 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 17055 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
<> 128:9bcdf88f62b0 17056 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
<> 128:9bcdf88f62b0 17057 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 17058 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
<> 128:9bcdf88f62b0 17059
<> 128:9bcdf88f62b0 17060 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
<> 128:9bcdf88f62b0 17061 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
<> 128:9bcdf88f62b0 17062 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 17063 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
<> 128:9bcdf88f62b0 17064 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
<> 128:9bcdf88f62b0 17065 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 17066 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
<> 128:9bcdf88f62b0 17067 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 17068 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 17069 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 17070 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 17071 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 17072 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 17073 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 17074 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 17075
<> 128:9bcdf88f62b0 17076 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
<> 128:9bcdf88f62b0 17077 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
<> 128:9bcdf88f62b0 17078 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
<> 128:9bcdf88f62b0 17079 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 17080 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 17081 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 17082 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 17083 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 17084 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 17085 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 17086 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 17087
<> 128:9bcdf88f62b0 17088 /******************** Bit definition for USB_OTG_HAINT register ********************/
<> 128:9bcdf88f62b0 17089 #define USB_OTG_HAINT_HAINT_Pos (0U)
<> 128:9bcdf88f62b0 17090 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 17091 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
<> 128:9bcdf88f62b0 17092
<> 128:9bcdf88f62b0 17093 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
<> 128:9bcdf88f62b0 17094 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
<> 128:9bcdf88f62b0 17095 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 17096 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
<> 128:9bcdf88f62b0 17097 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
<> 128:9bcdf88f62b0 17098 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 17099 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
<> 128:9bcdf88f62b0 17100 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
<> 128:9bcdf88f62b0 17101 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 17102 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
<> 128:9bcdf88f62b0 17103 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
<> 128:9bcdf88f62b0 17104 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 17105 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
<> 128:9bcdf88f62b0 17106 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
<> 128:9bcdf88f62b0 17107 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 17108 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
<> 128:9bcdf88f62b0 17109 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
<> 128:9bcdf88f62b0 17110 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 17111 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
<> 128:9bcdf88f62b0 17112 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
<> 128:9bcdf88f62b0 17113 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 17114 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
<> 128:9bcdf88f62b0 17115
<> 128:9bcdf88f62b0 17116 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
<> 128:9bcdf88f62b0 17117 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
<> 128:9bcdf88f62b0 17118 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 17119 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
<> 128:9bcdf88f62b0 17120 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
<> 128:9bcdf88f62b0 17121 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 17122 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
<> 128:9bcdf88f62b0 17123 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
<> 128:9bcdf88f62b0 17124 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 17125 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
<> 128:9bcdf88f62b0 17126 #define USB_OTG_GINTSTS_SOF_Pos (3U)
<> 128:9bcdf88f62b0 17127 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 17128 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
<> 128:9bcdf88f62b0 17129 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
<> 128:9bcdf88f62b0 17130 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 17131 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
<> 128:9bcdf88f62b0 17132 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
<> 128:9bcdf88f62b0 17133 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 17134 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
<> 128:9bcdf88f62b0 17135 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
<> 128:9bcdf88f62b0 17136 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 17137 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
<> 128:9bcdf88f62b0 17138 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
<> 128:9bcdf88f62b0 17139 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 17140 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
<> 128:9bcdf88f62b0 17141 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
<> 128:9bcdf88f62b0 17142 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 17143 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
<> 128:9bcdf88f62b0 17144 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
<> 128:9bcdf88f62b0 17145 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 17146 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
<> 128:9bcdf88f62b0 17147 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
<> 128:9bcdf88f62b0 17148 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 17149 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
<> 128:9bcdf88f62b0 17150 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
<> 128:9bcdf88f62b0 17151 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 17152 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
<> 128:9bcdf88f62b0 17153 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
<> 128:9bcdf88f62b0 17154 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 17155 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
<> 128:9bcdf88f62b0 17156 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
<> 128:9bcdf88f62b0 17157 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 17158 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
<> 128:9bcdf88f62b0 17159 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
<> 128:9bcdf88f62b0 17160 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 17161 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
<> 128:9bcdf88f62b0 17162 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
<> 128:9bcdf88f62b0 17163 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 17164 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
<> 128:9bcdf88f62b0 17165 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
<> 128:9bcdf88f62b0 17166 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 17167 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
<> 128:9bcdf88f62b0 17168 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
<> 128:9bcdf88f62b0 17169 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 17170 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
<> 128:9bcdf88f62b0 17171 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
<> 128:9bcdf88f62b0 17172 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 17173 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
<> 128:9bcdf88f62b0 17174 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
<> 128:9bcdf88f62b0 17175 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 17176 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
<> 128:9bcdf88f62b0 17177 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
<> 128:9bcdf88f62b0 17178 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 17179 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
<> 128:9bcdf88f62b0 17180 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
<> 128:9bcdf88f62b0 17181 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 17182 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
<> 128:9bcdf88f62b0 17183 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
<> 128:9bcdf88f62b0 17184 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 17185 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
<> 128:9bcdf88f62b0 17186 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
<> 128:9bcdf88f62b0 17187 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 17188 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
<> 128:9bcdf88f62b0 17189 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
<> 128:9bcdf88f62b0 17190 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 17191 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
<> 128:9bcdf88f62b0 17192 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
<> 128:9bcdf88f62b0 17193 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 17194 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
<> 128:9bcdf88f62b0 17195 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
<> 128:9bcdf88f62b0 17196 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 17197 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
<> 128:9bcdf88f62b0 17198
<> 128:9bcdf88f62b0 17199 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
<> 128:9bcdf88f62b0 17200
<> 128:9bcdf88f62b0 17201 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
<> 128:9bcdf88f62b0 17202 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 17203 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
<> 128:9bcdf88f62b0 17204 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
<> 128:9bcdf88f62b0 17205 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 17206 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
<> 128:9bcdf88f62b0 17207 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
<> 128:9bcdf88f62b0 17208 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 17209 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
<> 128:9bcdf88f62b0 17210 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
<> 128:9bcdf88f62b0 17211 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 17212 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
<> 128:9bcdf88f62b0 17213 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
<> 128:9bcdf88f62b0 17214 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 17215 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
<> 128:9bcdf88f62b0 17216 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
<> 128:9bcdf88f62b0 17217 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 17218 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
<> 128:9bcdf88f62b0 17219 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
<> 128:9bcdf88f62b0 17220 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 17221 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
<> 128:9bcdf88f62b0 17222 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
<> 128:9bcdf88f62b0 17223 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 17224 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
<> 128:9bcdf88f62b0 17225 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
<> 128:9bcdf88f62b0 17226 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 17227 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
<> 128:9bcdf88f62b0 17228 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
<> 128:9bcdf88f62b0 17229 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 17230 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
<> 128:9bcdf88f62b0 17231 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
<> 128:9bcdf88f62b0 17232 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 17233 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
<> 128:9bcdf88f62b0 17234 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
<> 128:9bcdf88f62b0 17235 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 17236 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
<> 128:9bcdf88f62b0 17237 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
<> 128:9bcdf88f62b0 17238 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 17239 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
<> 128:9bcdf88f62b0 17240 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
<> 128:9bcdf88f62b0 17241 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 17242 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
<> 128:9bcdf88f62b0 17243 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
<> 128:9bcdf88f62b0 17244 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 17245 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
<> 128:9bcdf88f62b0 17246 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
<> 128:9bcdf88f62b0 17247 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 17248 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
<> 128:9bcdf88f62b0 17249 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
<> 128:9bcdf88f62b0 17250 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 17251 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
<> 128:9bcdf88f62b0 17252 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
<> 128:9bcdf88f62b0 17253 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 17254 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
<> 128:9bcdf88f62b0 17255 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
<> 128:9bcdf88f62b0 17256 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 17257 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
<> 128:9bcdf88f62b0 17258 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
<> 128:9bcdf88f62b0 17259 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 17260 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
<> 128:9bcdf88f62b0 17261 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
<> 128:9bcdf88f62b0 17262 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 17263 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
<> 128:9bcdf88f62b0 17264 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
<> 128:9bcdf88f62b0 17265 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 17266 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
<> 128:9bcdf88f62b0 17267 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
<> 128:9bcdf88f62b0 17268 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 17269 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
<> 128:9bcdf88f62b0 17270 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
<> 128:9bcdf88f62b0 17271 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 17272 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
<> 128:9bcdf88f62b0 17273 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
<> 128:9bcdf88f62b0 17274 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 17275 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
<> 128:9bcdf88f62b0 17276 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
<> 128:9bcdf88f62b0 17277 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 17278 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
<> 128:9bcdf88f62b0 17279 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
<> 128:9bcdf88f62b0 17280 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 17281 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
<> 128:9bcdf88f62b0 17282
<> 128:9bcdf88f62b0 17283 /******************** Bit definition for USB_OTG_DAINT register ********************/
<> 128:9bcdf88f62b0 17284 #define USB_OTG_DAINT_IEPINT_Pos (0U)
<> 128:9bcdf88f62b0 17285 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 17286 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
<> 128:9bcdf88f62b0 17287 #define USB_OTG_DAINT_OEPINT_Pos (16U)
<> 128:9bcdf88f62b0 17288 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
<> 128:9bcdf88f62b0 17289 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
<> 128:9bcdf88f62b0 17290
<> 128:9bcdf88f62b0 17291 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
<> 128:9bcdf88f62b0 17292 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
<> 128:9bcdf88f62b0 17293 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 17294 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
<> 128:9bcdf88f62b0 17295
<> 128:9bcdf88f62b0 17296 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
<> 128:9bcdf88f62b0 17297 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
<> 128:9bcdf88f62b0 17298 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 17299 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
<> 128:9bcdf88f62b0 17300 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
<> 128:9bcdf88f62b0 17301 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
<> 128:9bcdf88f62b0 17302 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
<> 128:9bcdf88f62b0 17303 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
<> 128:9bcdf88f62b0 17304 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
<> 128:9bcdf88f62b0 17305 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
<> 128:9bcdf88f62b0 17306 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
<> 128:9bcdf88f62b0 17307 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
<> 128:9bcdf88f62b0 17308 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
<> 128:9bcdf88f62b0 17309
<> 128:9bcdf88f62b0 17310 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
<> 128:9bcdf88f62b0 17311 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
<> 128:9bcdf88f62b0 17312 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 17313 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
<> 128:9bcdf88f62b0 17314 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
<> 128:9bcdf88f62b0 17315 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
<> 128:9bcdf88f62b0 17316 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
<> 128:9bcdf88f62b0 17317
<> 128:9bcdf88f62b0 17318 /******************** Bit definition for OTG register ********************/
<> 128:9bcdf88f62b0 17319
<> 128:9bcdf88f62b0 17320 #define USB_OTG_CHNUM_Pos (0U)
<> 128:9bcdf88f62b0 17321 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 17322 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
<> 128:9bcdf88f62b0 17323 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 17324 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 17325 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 17326 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 17327 #define USB_OTG_BCNT_Pos (4U)
<> 128:9bcdf88f62b0 17328 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
<> 128:9bcdf88f62b0 17329 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
<> 128:9bcdf88f62b0 17330 #define USB_OTG_DPID_Pos (15U)
<> 128:9bcdf88f62b0 17331 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
<> 128:9bcdf88f62b0 17332 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
<> 128:9bcdf88f62b0 17333 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 17334 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 17335 #define USB_OTG_PKTSTS_Pos (17U)
<> 128:9bcdf88f62b0 17336 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
<> 128:9bcdf88f62b0 17337 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
<> 128:9bcdf88f62b0 17338 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 17339 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 17340 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 17341 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 17342 #define USB_OTG_EPNUM_Pos (0U)
<> 128:9bcdf88f62b0 17343 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 17344 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
<> 128:9bcdf88f62b0 17345 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 17346 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 17347 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 17348 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 17349 #define USB_OTG_FRMNUM_Pos (21U)
<> 128:9bcdf88f62b0 17350 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
<> 128:9bcdf88f62b0 17351 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
<> 128:9bcdf88f62b0 17352 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 17353 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 17354 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 17355 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 17356
<> 128:9bcdf88f62b0 17357 /******************** Bit definition for OTG register ********************/
<> 128:9bcdf88f62b0 17358
<> 128:9bcdf88f62b0 17359 #define USB_OTG_CHNUM_Pos (0U)
<> 128:9bcdf88f62b0 17360 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 17361 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
<> 128:9bcdf88f62b0 17362 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 17363 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 17364 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 17365 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 17366 #define USB_OTG_BCNT_Pos (4U)
<> 128:9bcdf88f62b0 17367 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
<> 128:9bcdf88f62b0 17368 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
<> 128:9bcdf88f62b0 17369 #define USB_OTG_DPID_Pos (15U)
<> 128:9bcdf88f62b0 17370 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
<> 128:9bcdf88f62b0 17371 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
<> 128:9bcdf88f62b0 17372 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 17373 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 17374 #define USB_OTG_PKTSTS_Pos (17U)
<> 128:9bcdf88f62b0 17375 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
<> 128:9bcdf88f62b0 17376 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
<> 128:9bcdf88f62b0 17377 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 17378 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 17379 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 17380 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 17381 #define USB_OTG_EPNUM_Pos (0U)
<> 128:9bcdf88f62b0 17382 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
<> 128:9bcdf88f62b0 17383 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
<> 128:9bcdf88f62b0 17384 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 17385 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 17386 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 17387 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 17388 #define USB_OTG_FRMNUM_Pos (21U)
<> 128:9bcdf88f62b0 17389 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
<> 128:9bcdf88f62b0 17390 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
<> 128:9bcdf88f62b0 17391 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 17392 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 17393 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 17394 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 17395
<> 128:9bcdf88f62b0 17396 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
<> 128:9bcdf88f62b0 17397 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
<> 128:9bcdf88f62b0 17398 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 17399 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
<> 128:9bcdf88f62b0 17400
<> 128:9bcdf88f62b0 17401 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
<> 128:9bcdf88f62b0 17402 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
<> 128:9bcdf88f62b0 17403 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 17404 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
<> 128:9bcdf88f62b0 17405
<> 128:9bcdf88f62b0 17406 /******************** Bit definition for OTG register ********************/
<> 128:9bcdf88f62b0 17407 #define USB_OTG_NPTXFSA_Pos (0U)
<> 128:9bcdf88f62b0 17408 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 17409 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
<> 128:9bcdf88f62b0 17410 #define USB_OTG_NPTXFD_Pos (16U)
<> 128:9bcdf88f62b0 17411 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
<> 128:9bcdf88f62b0 17412 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
<> 128:9bcdf88f62b0 17413 #define USB_OTG_TX0FSA_Pos (0U)
<> 128:9bcdf88f62b0 17414 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 17415 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
<> 128:9bcdf88f62b0 17416 #define USB_OTG_TX0FD_Pos (16U)
<> 128:9bcdf88f62b0 17417 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
<> 128:9bcdf88f62b0 17418 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
<> 128:9bcdf88f62b0 17419
<> 128:9bcdf88f62b0 17420 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
<> 128:9bcdf88f62b0 17421 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
<> 128:9bcdf88f62b0 17422 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
<> 128:9bcdf88f62b0 17423 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
<> 128:9bcdf88f62b0 17424
<> 128:9bcdf88f62b0 17425 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
<> 128:9bcdf88f62b0 17426 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
<> 128:9bcdf88f62b0 17427 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 17428 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
<> 128:9bcdf88f62b0 17429
<> 128:9bcdf88f62b0 17430 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
<> 128:9bcdf88f62b0 17431 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
<> 128:9bcdf88f62b0 17432 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
<> 128:9bcdf88f62b0 17433 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 17434 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 17435 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 17436 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 17437 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 17438 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 17439 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 17440 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 17441
<> 128:9bcdf88f62b0 17442 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
<> 128:9bcdf88f62b0 17443 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
<> 128:9bcdf88f62b0 17444 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
<> 128:9bcdf88f62b0 17445 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 17446 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 17447 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 17448 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 17449 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 17450 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 17451 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 17452
<> 128:9bcdf88f62b0 17453 /******************** Bit definition for USB_OTG_DTHRCTL register ***************/
<> 128:9bcdf88f62b0 17454 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
<> 128:9bcdf88f62b0 17455 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 17456 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
<> 128:9bcdf88f62b0 17457 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
<> 128:9bcdf88f62b0 17458 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 17459 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
<> 128:9bcdf88f62b0 17460
<> 128:9bcdf88f62b0 17461 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
<> 128:9bcdf88f62b0 17462 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
<> 128:9bcdf88f62b0 17463 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
<> 128:9bcdf88f62b0 17464 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 17465 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 17466 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 17467 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 17468 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 17469 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 17470 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 17471 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 17472 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 17473 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
<> 128:9bcdf88f62b0 17474 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 17475 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
<> 128:9bcdf88f62b0 17476
<> 128:9bcdf88f62b0 17477 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
<> 128:9bcdf88f62b0 17478 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
<> 128:9bcdf88f62b0 17479 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
<> 128:9bcdf88f62b0 17480 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 17481 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 17482 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 17483 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 17484 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 17485 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 17486 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 17487 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 17488 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 17489 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
<> 128:9bcdf88f62b0 17490 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 17491 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
<> 128:9bcdf88f62b0 17492
<> 128:9bcdf88f62b0 17493 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ***************/
<> 128:9bcdf88f62b0 17494 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
<> 128:9bcdf88f62b0 17495 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 17496 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
<> 128:9bcdf88f62b0 17497
<> 128:9bcdf88f62b0 17498 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
<> 128:9bcdf88f62b0 17499 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
<> 128:9bcdf88f62b0 17500 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 17501 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
<> 128:9bcdf88f62b0 17502 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
<> 128:9bcdf88f62b0 17503 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 17504 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
<> 128:9bcdf88f62b0 17505
<> 128:9bcdf88f62b0 17506 /******************** Bit definition for USB_OTG_GCCFG register ********************/
<> 128:9bcdf88f62b0 17507 #define USB_OTG_GCCFG_DCDET_Pos (0U)
<> 128:9bcdf88f62b0 17508 #define USB_OTG_GCCFG_DCDET_Msk (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 17509 #define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
<> 128:9bcdf88f62b0 17510 #define USB_OTG_GCCFG_PDET_Pos (1U)
<> 128:9bcdf88f62b0 17511 #define USB_OTG_GCCFG_PDET_Msk (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 17512 #define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
<> 128:9bcdf88f62b0 17513 #define USB_OTG_GCCFG_SDET_Pos (2U)
<> 128:9bcdf88f62b0 17514 #define USB_OTG_GCCFG_SDET_Msk (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 17515 #define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
<> 128:9bcdf88f62b0 17516 #define USB_OTG_GCCFG_PS2DET_Pos (3U)
<> 128:9bcdf88f62b0 17517 #define USB_OTG_GCCFG_PS2DET_Msk (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 17518 #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
<> 128:9bcdf88f62b0 17519 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
<> 128:9bcdf88f62b0 17520 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 17521 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
<> 128:9bcdf88f62b0 17522 #define USB_OTG_GCCFG_BCDEN_Pos (17U)
<> 128:9bcdf88f62b0 17523 #define USB_OTG_GCCFG_BCDEN_Msk (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 17524 #define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
<> 128:9bcdf88f62b0 17525 #define USB_OTG_GCCFG_DCDEN_Pos (18U)
<> 128:9bcdf88f62b0 17526 #define USB_OTG_GCCFG_DCDEN_Msk (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 17527 #define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
<> 128:9bcdf88f62b0 17528 #define USB_OTG_GCCFG_PDEN_Pos (19U)
<> 128:9bcdf88f62b0 17529 #define USB_OTG_GCCFG_PDEN_Msk (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 17530 #define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
<> 128:9bcdf88f62b0 17531 #define USB_OTG_GCCFG_SDEN_Pos (20U)
<> 128:9bcdf88f62b0 17532 #define USB_OTG_GCCFG_SDEN_Msk (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 17533 #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
<> 128:9bcdf88f62b0 17534 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
<> 128:9bcdf88f62b0 17535 #define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 17536 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */
<> 128:9bcdf88f62b0 17537
<> 128:9bcdf88f62b0 17538 /******************** Bit definition for USB_OTG_GPWRDN) register ********************/
<> 128:9bcdf88f62b0 17539 #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U)
<> 128:9bcdf88f62b0 17540 #define USB_OTG_GPWRDN_DISABLEVBUS_Msk (0x1U << USB_OTG_GPWRDN_DISABLEVBUS_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 17541 #define USB_OTG_GPWRDN_DISABLEVBUS USB_OTG_GPWRDN_DISABLEVBUS_Msk /*!< Power down */
<> 128:9bcdf88f62b0 17542
<> 128:9bcdf88f62b0 17543 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
<> 128:9bcdf88f62b0 17544 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
<> 128:9bcdf88f62b0 17545 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 17546 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
<> 128:9bcdf88f62b0 17547 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
<> 128:9bcdf88f62b0 17548 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 17549 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
<> 128:9bcdf88f62b0 17550
<> 128:9bcdf88f62b0 17551 /******************** Bit definition for USB_OTG_CID register ********************/
<> 128:9bcdf88f62b0 17552 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
<> 128:9bcdf88f62b0 17553 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 17554 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
<> 128:9bcdf88f62b0 17555
<> 128:9bcdf88f62b0 17556
<> 128:9bcdf88f62b0 17557 /******************** Bit definition for USB_OTG_GHWCFG3 register ********************/
<> 128:9bcdf88f62b0 17558 #define USB_OTG_GHWCFG3_LPMMode_Pos (14U)
<> 128:9bcdf88f62b0 17559 #define USB_OTG_GHWCFG3_LPMMode_Msk (0x1U << USB_OTG_GHWCFG3_LPMMode_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 17560 #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */
<> 128:9bcdf88f62b0 17561
<> 128:9bcdf88f62b0 17562 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
<> 128:9bcdf88f62b0 17563 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
<> 128:9bcdf88f62b0 17564 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 17565 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */
<> 128:9bcdf88f62b0 17566 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
<> 128:9bcdf88f62b0 17567 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
<> 128:9bcdf88f62b0 17568 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */
<> 128:9bcdf88f62b0 17569 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
<> 128:9bcdf88f62b0 17570 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 17571 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */
<> 128:9bcdf88f62b0 17572 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
<> 128:9bcdf88f62b0 17573 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
<> 128:9bcdf88f62b0 17574 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */
<> 128:9bcdf88f62b0 17575 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
<> 128:9bcdf88f62b0 17576 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
<> 128:9bcdf88f62b0 17577 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */
<> 128:9bcdf88f62b0 17578 #define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U)
<> 128:9bcdf88f62b0 17579 #define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 17580 #define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */
<> 128:9bcdf88f62b0 17581 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
<> 128:9bcdf88f62b0 17582 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 17583 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */
<> 128:9bcdf88f62b0 17584 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
<> 128:9bcdf88f62b0 17585 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
<> 128:9bcdf88f62b0 17586 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */
<> 128:9bcdf88f62b0 17587 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
<> 128:9bcdf88f62b0 17588 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 17589 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */
<> 128:9bcdf88f62b0 17590 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
<> 128:9bcdf88f62b0 17591 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
<> 128:9bcdf88f62b0 17592 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */
<> 128:9bcdf88f62b0 17593 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
<> 128:9bcdf88f62b0 17594 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 17595 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */
<> 128:9bcdf88f62b0 17596 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
<> 128:9bcdf88f62b0 17597 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 17598 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */
<> 128:9bcdf88f62b0 17599 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
<> 128:9bcdf88f62b0 17600 #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
<> 128:9bcdf88f62b0 17601 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */
<> 128:9bcdf88f62b0 17602 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
<> 128:9bcdf88f62b0 17603 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 17604 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/
<> 128:9bcdf88f62b0 17605 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
<> 128:9bcdf88f62b0 17606 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 17607 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */
<> 128:9bcdf88f62b0 17608
<> 128:9bcdf88f62b0 17609
<> 128:9bcdf88f62b0 17610 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
<> 128:9bcdf88f62b0 17611 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
<> 128:9bcdf88f62b0 17612 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 17613 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
<> 128:9bcdf88f62b0 17614 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
<> 128:9bcdf88f62b0 17615 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 17616 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
<> 128:9bcdf88f62b0 17617 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
<> 128:9bcdf88f62b0 17618 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 17619 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
<> 128:9bcdf88f62b0 17620 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
<> 128:9bcdf88f62b0 17621 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 17622 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
<> 128:9bcdf88f62b0 17623 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
<> 128:9bcdf88f62b0 17624 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 17625 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
<> 128:9bcdf88f62b0 17626 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
<> 128:9bcdf88f62b0 17627 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 17628 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
<> 128:9bcdf88f62b0 17629 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
<> 128:9bcdf88f62b0 17630 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 17631 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
<> 128:9bcdf88f62b0 17632 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
<> 128:9bcdf88f62b0 17633 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 17634 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
<> 128:9bcdf88f62b0 17635 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
<> 128:9bcdf88f62b0 17636 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 17637 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
<> 128:9bcdf88f62b0 17638
<> 128:9bcdf88f62b0 17639 /******************** Bit definition for USB_OTG_HPRT register ********************/
<> 128:9bcdf88f62b0 17640 #define USB_OTG_HPRT_PCSTS_Pos (0U)
<> 128:9bcdf88f62b0 17641 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 17642 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
<> 128:9bcdf88f62b0 17643 #define USB_OTG_HPRT_PCDET_Pos (1U)
<> 128:9bcdf88f62b0 17644 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 17645 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
<> 128:9bcdf88f62b0 17646 #define USB_OTG_HPRT_PENA_Pos (2U)
<> 128:9bcdf88f62b0 17647 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 17648 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
<> 128:9bcdf88f62b0 17649 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
<> 128:9bcdf88f62b0 17650 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 17651 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
<> 128:9bcdf88f62b0 17652 #define USB_OTG_HPRT_POCA_Pos (4U)
<> 128:9bcdf88f62b0 17653 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 17654 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
<> 128:9bcdf88f62b0 17655 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
<> 128:9bcdf88f62b0 17656 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 17657 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
<> 128:9bcdf88f62b0 17658 #define USB_OTG_HPRT_PRES_Pos (6U)
<> 128:9bcdf88f62b0 17659 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 17660 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
<> 128:9bcdf88f62b0 17661 #define USB_OTG_HPRT_PSUSP_Pos (7U)
<> 128:9bcdf88f62b0 17662 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 17663 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
<> 128:9bcdf88f62b0 17664 #define USB_OTG_HPRT_PRST_Pos (8U)
<> 128:9bcdf88f62b0 17665 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 17666 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
<> 128:9bcdf88f62b0 17667
<> 128:9bcdf88f62b0 17668 #define USB_OTG_HPRT_PLSTS_Pos (10U)
<> 128:9bcdf88f62b0 17669 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
<> 128:9bcdf88f62b0 17670 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
<> 128:9bcdf88f62b0 17671 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 17672 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 17673 #define USB_OTG_HPRT_PPWR_Pos (12U)
<> 128:9bcdf88f62b0 17674 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 17675 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
<> 128:9bcdf88f62b0 17676
<> 128:9bcdf88f62b0 17677 #define USB_OTG_HPRT_PTCTL_Pos (13U)
<> 128:9bcdf88f62b0 17678 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
<> 128:9bcdf88f62b0 17679 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
<> 128:9bcdf88f62b0 17680 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 17681 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 17682 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 17683 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 17684
<> 128:9bcdf88f62b0 17685 #define USB_OTG_HPRT_PSPD_Pos (17U)
<> 128:9bcdf88f62b0 17686 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
<> 128:9bcdf88f62b0 17687 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
<> 128:9bcdf88f62b0 17688 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 17689 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 17690
<> 128:9bcdf88f62b0 17691 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
<> 128:9bcdf88f62b0 17692 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
<> 128:9bcdf88f62b0 17693 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 17694 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
<> 128:9bcdf88f62b0 17695 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
<> 128:9bcdf88f62b0 17696 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 17697 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
<> 128:9bcdf88f62b0 17698 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
<> 128:9bcdf88f62b0 17699 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 17700 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
<> 128:9bcdf88f62b0 17701 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
<> 128:9bcdf88f62b0 17702 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 17703 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
<> 128:9bcdf88f62b0 17704 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
<> 128:9bcdf88f62b0 17705 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 17706 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
<> 128:9bcdf88f62b0 17707 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
<> 128:9bcdf88f62b0 17708 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 17709 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
<> 128:9bcdf88f62b0 17710 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
<> 128:9bcdf88f62b0 17711 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 17712 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
<> 128:9bcdf88f62b0 17713 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
<> 128:9bcdf88f62b0 17714 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 17715 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
<> 128:9bcdf88f62b0 17716 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
<> 128:9bcdf88f62b0 17717 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 17718 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
<> 128:9bcdf88f62b0 17719 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
<> 128:9bcdf88f62b0 17720 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 17721 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
<> 128:9bcdf88f62b0 17722 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
<> 128:9bcdf88f62b0 17723 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 17724 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
<> 128:9bcdf88f62b0 17725
<> 128:9bcdf88f62b0 17726 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
<> 128:9bcdf88f62b0 17727 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
<> 128:9bcdf88f62b0 17728 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 17729 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
<> 128:9bcdf88f62b0 17730 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
<> 128:9bcdf88f62b0 17731 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
<> 128:9bcdf88f62b0 17732 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
<> 128:9bcdf88f62b0 17733
<> 128:9bcdf88f62b0 17734 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
<> 128:9bcdf88f62b0 17735 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
<> 128:9bcdf88f62b0 17736 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
<> 128:9bcdf88f62b0 17737 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
<> 128:9bcdf88f62b0 17738 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
<> 128:9bcdf88f62b0 17739 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 17740 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
<> 128:9bcdf88f62b0 17741 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
<> 128:9bcdf88f62b0 17742 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 17743 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
<> 128:9bcdf88f62b0 17744 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
<> 128:9bcdf88f62b0 17745 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 17746 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
<> 128:9bcdf88f62b0 17747
<> 128:9bcdf88f62b0 17748 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
<> 128:9bcdf88f62b0 17749 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
<> 128:9bcdf88f62b0 17750 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
<> 128:9bcdf88f62b0 17751 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 17752 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 17753 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
<> 128:9bcdf88f62b0 17754 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 17755 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
<> 128:9bcdf88f62b0 17756
<> 128:9bcdf88f62b0 17757 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
<> 128:9bcdf88f62b0 17758 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
<> 128:9bcdf88f62b0 17759 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
<> 128:9bcdf88f62b0 17760 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 17761 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 17762 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 17763 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 17764 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
<> 128:9bcdf88f62b0 17765 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 17766 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
<> 128:9bcdf88f62b0 17767 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
<> 128:9bcdf88f62b0 17768 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 17769 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
<> 128:9bcdf88f62b0 17770 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
<> 128:9bcdf88f62b0 17771 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 17772 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
<> 128:9bcdf88f62b0 17773 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
<> 128:9bcdf88f62b0 17774 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 17775 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
<> 128:9bcdf88f62b0 17776 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
<> 128:9bcdf88f62b0 17777 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 17778 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
<> 128:9bcdf88f62b0 17779 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
<> 128:9bcdf88f62b0 17780 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 17781 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
<> 128:9bcdf88f62b0 17782
<> 128:9bcdf88f62b0 17783 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
<> 128:9bcdf88f62b0 17784 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
<> 128:9bcdf88f62b0 17785 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
<> 128:9bcdf88f62b0 17786 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
<> 128:9bcdf88f62b0 17787
<> 128:9bcdf88f62b0 17788 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
<> 128:9bcdf88f62b0 17789 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
<> 128:9bcdf88f62b0 17790 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
<> 128:9bcdf88f62b0 17791 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 17792 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 17793 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 17794 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 17795 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
<> 128:9bcdf88f62b0 17796 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 17797 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
<> 128:9bcdf88f62b0 17798 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
<> 128:9bcdf88f62b0 17799 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 17800 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
<> 128:9bcdf88f62b0 17801
<> 128:9bcdf88f62b0 17802 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
<> 128:9bcdf88f62b0 17803 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
<> 128:9bcdf88f62b0 17804 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
<> 128:9bcdf88f62b0 17805 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 17806 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 17807
<> 128:9bcdf88f62b0 17808 #define USB_OTG_HCCHAR_MC_Pos (20U)
<> 128:9bcdf88f62b0 17809 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
<> 128:9bcdf88f62b0 17810 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
<> 128:9bcdf88f62b0 17811 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 17812 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 17813
<> 128:9bcdf88f62b0 17814 #define USB_OTG_HCCHAR_DAD_Pos (22U)
<> 128:9bcdf88f62b0 17815 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
<> 128:9bcdf88f62b0 17816 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
<> 128:9bcdf88f62b0 17817 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
<> 128:9bcdf88f62b0 17818 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
<> 128:9bcdf88f62b0 17819 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
<> 128:9bcdf88f62b0 17820 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
<> 128:9bcdf88f62b0 17821 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 17822 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 17823 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 17824 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
<> 128:9bcdf88f62b0 17825 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 17826 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
<> 128:9bcdf88f62b0 17827 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
<> 128:9bcdf88f62b0 17828 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 17829 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
<> 128:9bcdf88f62b0 17830 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
<> 128:9bcdf88f62b0 17831 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 17832 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
<> 128:9bcdf88f62b0 17833
<> 128:9bcdf88f62b0 17834 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
<> 128:9bcdf88f62b0 17835
<> 128:9bcdf88f62b0 17836 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
<> 128:9bcdf88f62b0 17837 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
<> 128:9bcdf88f62b0 17838 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
<> 128:9bcdf88f62b0 17839 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 17840 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 17841 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 17842 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 17843 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 17844 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 17845 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 17846
<> 128:9bcdf88f62b0 17847 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
<> 128:9bcdf88f62b0 17848 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
<> 128:9bcdf88f62b0 17849 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
<> 128:9bcdf88f62b0 17850 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 17851 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 17852 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 17853 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 17854 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 17855 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 17856 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 17857
<> 128:9bcdf88f62b0 17858 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
<> 128:9bcdf88f62b0 17859 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
<> 128:9bcdf88f62b0 17860 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
<> 128:9bcdf88f62b0 17861 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 17862 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 17863 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
<> 128:9bcdf88f62b0 17864 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
<> 128:9bcdf88f62b0 17865 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
<> 128:9bcdf88f62b0 17866 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
<> 128:9bcdf88f62b0 17867 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 17868 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
<> 128:9bcdf88f62b0 17869
<> 128:9bcdf88f62b0 17870 /******************** Bit definition for USB_OTG_HCINT register ********************/
<> 128:9bcdf88f62b0 17871 #define USB_OTG_HCINT_XFRC_Pos (0U)
<> 128:9bcdf88f62b0 17872 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 17873 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
<> 128:9bcdf88f62b0 17874 #define USB_OTG_HCINT_CHH_Pos (1U)
<> 128:9bcdf88f62b0 17875 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 17876 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
<> 128:9bcdf88f62b0 17877 #define USB_OTG_HCINT_AHBERR_Pos (2U)
<> 128:9bcdf88f62b0 17878 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 17879 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
<> 128:9bcdf88f62b0 17880 #define USB_OTG_HCINT_STALL_Pos (3U)
<> 128:9bcdf88f62b0 17881 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 17882 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
<> 128:9bcdf88f62b0 17883 #define USB_OTG_HCINT_NAK_Pos (4U)
<> 128:9bcdf88f62b0 17884 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 17885 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
<> 128:9bcdf88f62b0 17886 #define USB_OTG_HCINT_ACK_Pos (5U)
<> 128:9bcdf88f62b0 17887 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 17888 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
<> 128:9bcdf88f62b0 17889 #define USB_OTG_HCINT_NYET_Pos (6U)
<> 128:9bcdf88f62b0 17890 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 17891 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
<> 128:9bcdf88f62b0 17892 #define USB_OTG_HCINT_TXERR_Pos (7U)
<> 128:9bcdf88f62b0 17893 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 17894 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
<> 128:9bcdf88f62b0 17895 #define USB_OTG_HCINT_BBERR_Pos (8U)
<> 128:9bcdf88f62b0 17896 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 17897 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
<> 128:9bcdf88f62b0 17898 #define USB_OTG_HCINT_FRMOR_Pos (9U)
<> 128:9bcdf88f62b0 17899 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 17900 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
<> 128:9bcdf88f62b0 17901 #define USB_OTG_HCINT_DTERR_Pos (10U)
<> 128:9bcdf88f62b0 17902 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 17903 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
<> 128:9bcdf88f62b0 17904
<> 128:9bcdf88f62b0 17905 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
<> 128:9bcdf88f62b0 17906 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
<> 128:9bcdf88f62b0 17907 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 17908 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
<> 128:9bcdf88f62b0 17909 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
<> 128:9bcdf88f62b0 17910 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 17911 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
<> 128:9bcdf88f62b0 17912 #define USB_OTG_DIEPINT_TOC_Pos (3U)
<> 128:9bcdf88f62b0 17913 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 17914 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
<> 128:9bcdf88f62b0 17915 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
<> 128:9bcdf88f62b0 17916 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 17917 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
<> 128:9bcdf88f62b0 17918 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
<> 128:9bcdf88f62b0 17919 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 17920 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
<> 128:9bcdf88f62b0 17921 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
<> 128:9bcdf88f62b0 17922 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 17923 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
<> 128:9bcdf88f62b0 17924 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
<> 128:9bcdf88f62b0 17925 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 17926 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
<> 128:9bcdf88f62b0 17927 #define USB_OTG_DIEPINT_BNA_Pos (9U)
<> 128:9bcdf88f62b0 17928 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 17929 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
<> 128:9bcdf88f62b0 17930 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
<> 128:9bcdf88f62b0 17931 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
<> 128:9bcdf88f62b0 17932 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
<> 128:9bcdf88f62b0 17933 #define USB_OTG_DIEPINT_BERR_Pos (12U)
<> 128:9bcdf88f62b0 17934 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
<> 128:9bcdf88f62b0 17935 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
<> 128:9bcdf88f62b0 17936 #define USB_OTG_DIEPINT_NAK_Pos (13U)
<> 128:9bcdf88f62b0 17937 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
<> 128:9bcdf88f62b0 17938 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
<> 128:9bcdf88f62b0 17939
<> 128:9bcdf88f62b0 17940 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
<> 128:9bcdf88f62b0 17941 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
<> 128:9bcdf88f62b0 17942 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 17943 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
<> 128:9bcdf88f62b0 17944 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
<> 128:9bcdf88f62b0 17945 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 17946 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
<> 128:9bcdf88f62b0 17947 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
<> 128:9bcdf88f62b0 17948 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
<> 128:9bcdf88f62b0 17949 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
<> 128:9bcdf88f62b0 17950 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
<> 128:9bcdf88f62b0 17951 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 17952 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
<> 128:9bcdf88f62b0 17953 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
<> 128:9bcdf88f62b0 17954 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 17955 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
<> 128:9bcdf88f62b0 17956 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
<> 128:9bcdf88f62b0 17957 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
<> 128:9bcdf88f62b0 17958 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
<> 128:9bcdf88f62b0 17959 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
<> 128:9bcdf88f62b0 17960 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 17961 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
<> 128:9bcdf88f62b0 17962 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
<> 128:9bcdf88f62b0 17963 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
<> 128:9bcdf88f62b0 17964 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
<> 128:9bcdf88f62b0 17965 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
<> 128:9bcdf88f62b0 17966 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
<> 128:9bcdf88f62b0 17967 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
<> 128:9bcdf88f62b0 17968 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
<> 128:9bcdf88f62b0 17969 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
<> 128:9bcdf88f62b0 17970 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
<> 128:9bcdf88f62b0 17971 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
<> 128:9bcdf88f62b0 17972 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
<> 128:9bcdf88f62b0 17973 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
<> 128:9bcdf88f62b0 17974
<> 128:9bcdf88f62b0 17975 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
<> 128:9bcdf88f62b0 17976
<> 128:9bcdf88f62b0 17977 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
<> 128:9bcdf88f62b0 17978 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
<> 128:9bcdf88f62b0 17979 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
<> 128:9bcdf88f62b0 17980 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
<> 128:9bcdf88f62b0 17981 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
<> 128:9bcdf88f62b0 17982 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
<> 128:9bcdf88f62b0 17983 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
<> 128:9bcdf88f62b0 17984 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
<> 128:9bcdf88f62b0 17985 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
<> 128:9bcdf88f62b0 17986 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
<> 128:9bcdf88f62b0 17987 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
<> 128:9bcdf88f62b0 17988 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
<> 128:9bcdf88f62b0 17989 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
<> 128:9bcdf88f62b0 17990 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
<> 128:9bcdf88f62b0 17991 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
<> 128:9bcdf88f62b0 17992 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
<> 128:9bcdf88f62b0 17993 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
<> 128:9bcdf88f62b0 17994 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 17995 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
<> 128:9bcdf88f62b0 17996 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
<> 128:9bcdf88f62b0 17997 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
<> 128:9bcdf88f62b0 17998 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
<> 128:9bcdf88f62b0 17999 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 18000 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 18001
<> 128:9bcdf88f62b0 18002 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
<> 128:9bcdf88f62b0 18003 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
<> 128:9bcdf88f62b0 18004 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 18005 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
<> 128:9bcdf88f62b0 18006
<> 128:9bcdf88f62b0 18007 /******************** Bit definition for USB_OTG_HCDMA register ********************/
<> 128:9bcdf88f62b0 18008 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
<> 128:9bcdf88f62b0 18009 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
<> 128:9bcdf88f62b0 18010 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
<> 128:9bcdf88f62b0 18011
<> 128:9bcdf88f62b0 18012 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
<> 128:9bcdf88f62b0 18013 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
<> 128:9bcdf88f62b0 18014 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 18015 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space avail */
<> 128:9bcdf88f62b0 18016
<> 128:9bcdf88f62b0 18017 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
<> 128:9bcdf88f62b0 18018 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
<> 128:9bcdf88f62b0 18019 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
<> 128:9bcdf88f62b0 18020 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
<> 128:9bcdf88f62b0 18021 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
<> 128:9bcdf88f62b0 18022 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
<> 128:9bcdf88f62b0 18023 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
<> 128:9bcdf88f62b0 18024
<> 128:9bcdf88f62b0 18025 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
<> 128:9bcdf88f62b0 18026
<> 128:9bcdf88f62b0 18027 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
<> 128:9bcdf88f62b0 18028 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
<> 128:9bcdf88f62b0 18029 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
<> 128:9bcdf88f62b0 18030 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
<> 128:9bcdf88f62b0 18031 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
<> 128:9bcdf88f62b0 18032 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
<> 128:9bcdf88f62b0 18033 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
<> 128:9bcdf88f62b0 18034 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
<> 128:9bcdf88f62b0 18035 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
<> 128:9bcdf88f62b0 18036 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
<> 128:9bcdf88f62b0 18037 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
<> 128:9bcdf88f62b0 18038 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
<> 128:9bcdf88f62b0 18039 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
<> 128:9bcdf88f62b0 18040 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 18041 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
<> 128:9bcdf88f62b0 18042 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
<> 128:9bcdf88f62b0 18043 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
<> 128:9bcdf88f62b0 18044 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
<> 128:9bcdf88f62b0 18045 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
<> 128:9bcdf88f62b0 18046 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
<> 128:9bcdf88f62b0 18047 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
<> 128:9bcdf88f62b0 18048 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
<> 128:9bcdf88f62b0 18049 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
<> 128:9bcdf88f62b0 18050 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
<> 128:9bcdf88f62b0 18051 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
<> 128:9bcdf88f62b0 18052 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
<> 128:9bcdf88f62b0 18053 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
<> 128:9bcdf88f62b0 18054 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
<> 128:9bcdf88f62b0 18055 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
<> 128:9bcdf88f62b0 18056 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
<> 128:9bcdf88f62b0 18057 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
<> 128:9bcdf88f62b0 18058 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
<> 128:9bcdf88f62b0 18059 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
<> 128:9bcdf88f62b0 18060 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 18061 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
<> 128:9bcdf88f62b0 18062 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
<> 128:9bcdf88f62b0 18063 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
<> 128:9bcdf88f62b0 18064 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
<> 128:9bcdf88f62b0 18065
<> 128:9bcdf88f62b0 18066 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
<> 128:9bcdf88f62b0 18067 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
<> 128:9bcdf88f62b0 18068 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 18069 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
<> 128:9bcdf88f62b0 18070 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
<> 128:9bcdf88f62b0 18071 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 18072 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
<> 128:9bcdf88f62b0 18073 #define USB_OTG_DOEPINT_STUP_Pos (3U)
<> 128:9bcdf88f62b0 18074 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
<> 128:9bcdf88f62b0 18075 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
<> 128:9bcdf88f62b0 18076 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
<> 128:9bcdf88f62b0 18077 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 18078 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
<> 128:9bcdf88f62b0 18079 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
<> 128:9bcdf88f62b0 18080 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
<> 128:9bcdf88f62b0 18081 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
<> 128:9bcdf88f62b0 18082 #define USB_OTG_DOEPINT_NYET_Pos (14U)
<> 128:9bcdf88f62b0 18083 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
<> 128:9bcdf88f62b0 18084 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
<> 128:9bcdf88f62b0 18085
<> 128:9bcdf88f62b0 18086 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
<> 128:9bcdf88f62b0 18087
<> 128:9bcdf88f62b0 18088 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
<> 128:9bcdf88f62b0 18089 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
<> 128:9bcdf88f62b0 18090 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
<> 128:9bcdf88f62b0 18091 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
<> 128:9bcdf88f62b0 18092 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
<> 128:9bcdf88f62b0 18093 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
<> 128:9bcdf88f62b0 18094
<> 128:9bcdf88f62b0 18095 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
<> 128:9bcdf88f62b0 18096 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
<> 128:9bcdf88f62b0 18097 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
<> 128:9bcdf88f62b0 18098 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
<> 128:9bcdf88f62b0 18099 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
<> 128:9bcdf88f62b0 18100
<> 128:9bcdf88f62b0 18101 /******************** Bit definition for PCGCCTL register ********************/
<> 128:9bcdf88f62b0 18102 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
<> 128:9bcdf88f62b0 18103 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
<> 128:9bcdf88f62b0 18104 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
<> 128:9bcdf88f62b0 18105 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
<> 128:9bcdf88f62b0 18106 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
<> 128:9bcdf88f62b0 18107 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
<> 128:9bcdf88f62b0 18108 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
<> 128:9bcdf88f62b0 18109 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
<> 128:9bcdf88f62b0 18110 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
<> 128:9bcdf88f62b0 18111
<> 128:9bcdf88f62b0 18112
<> 128:9bcdf88f62b0 18113 /**
<> 128:9bcdf88f62b0 18114 * @}
<> 128:9bcdf88f62b0 18115 */
<> 128:9bcdf88f62b0 18116
<> 128:9bcdf88f62b0 18117 /**
<> 128:9bcdf88f62b0 18118 * @}
<> 128:9bcdf88f62b0 18119 */
<> 128:9bcdf88f62b0 18120
<> 128:9bcdf88f62b0 18121 /** @addtogroup Exported_macros
<> 128:9bcdf88f62b0 18122 * @{
<> 128:9bcdf88f62b0 18123 */
<> 128:9bcdf88f62b0 18124
<> 128:9bcdf88f62b0 18125 /******************************* ADC Instances ********************************/
<> 128:9bcdf88f62b0 18126 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
<> 128:9bcdf88f62b0 18127 ((INSTANCE) == ADC2) || \
<> 128:9bcdf88f62b0 18128 ((INSTANCE) == ADC3))
<> 128:9bcdf88f62b0 18129
<> 128:9bcdf88f62b0 18130 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
<> 128:9bcdf88f62b0 18131
<> 128:9bcdf88f62b0 18132 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
<> 128:9bcdf88f62b0 18133
<> 128:9bcdf88f62b0 18134 /******************************* AES Instances ********************************/
<> 128:9bcdf88f62b0 18135 #define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
<> 128:9bcdf88f62b0 18136
<> 128:9bcdf88f62b0 18137 /******************************** CAN Instances ******************************/
<> 128:9bcdf88f62b0 18138 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
<> 128:9bcdf88f62b0 18139
<> 128:9bcdf88f62b0 18140 /******************************** COMP Instances ******************************/
<> 128:9bcdf88f62b0 18141 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
<> 128:9bcdf88f62b0 18142 ((INSTANCE) == COMP2))
<> 128:9bcdf88f62b0 18143
<> 128:9bcdf88f62b0 18144 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
<> 128:9bcdf88f62b0 18145
<> 128:9bcdf88f62b0 18146 /******************** COMP Instances with window mode capability **************/
<> 128:9bcdf88f62b0 18147 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
<> 128:9bcdf88f62b0 18148
<> 128:9bcdf88f62b0 18149 /******************************* CRC Instances ********************************/
<> 128:9bcdf88f62b0 18150 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
<> 128:9bcdf88f62b0 18151
<> 128:9bcdf88f62b0 18152 /******************************* DAC Instances ********************************/
<> 128:9bcdf88f62b0 18153 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
<> 128:9bcdf88f62b0 18154
<> 128:9bcdf88f62b0 18155 /****************************** DFSDM Instances *******************************/
<> 128:9bcdf88f62b0 18156 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
<> 128:9bcdf88f62b0 18157 ((INSTANCE) == DFSDM1_Filter1) || \
<> 128:9bcdf88f62b0 18158 ((INSTANCE) == DFSDM1_Filter2) || \
<> 128:9bcdf88f62b0 18159 ((INSTANCE) == DFSDM1_Filter3))
<> 128:9bcdf88f62b0 18160
<> 128:9bcdf88f62b0 18161 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
<> 128:9bcdf88f62b0 18162 ((INSTANCE) == DFSDM1_Channel1) || \
<> 128:9bcdf88f62b0 18163 ((INSTANCE) == DFSDM1_Channel2) || \
<> 128:9bcdf88f62b0 18164 ((INSTANCE) == DFSDM1_Channel3) || \
<> 128:9bcdf88f62b0 18165 ((INSTANCE) == DFSDM1_Channel4) || \
<> 128:9bcdf88f62b0 18166 ((INSTANCE) == DFSDM1_Channel5) || \
<> 128:9bcdf88f62b0 18167 ((INSTANCE) == DFSDM1_Channel6) || \
<> 128:9bcdf88f62b0 18168 ((INSTANCE) == DFSDM1_Channel7))
<> 128:9bcdf88f62b0 18169
<> 128:9bcdf88f62b0 18170 /******************************** DMA Instances *******************************/
<> 128:9bcdf88f62b0 18171 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
<> 128:9bcdf88f62b0 18172 ((INSTANCE) == DMA1_Channel2) || \
<> 128:9bcdf88f62b0 18173 ((INSTANCE) == DMA1_Channel3) || \
<> 128:9bcdf88f62b0 18174 ((INSTANCE) == DMA1_Channel4) || \
<> 128:9bcdf88f62b0 18175 ((INSTANCE) == DMA1_Channel5) || \
<> 128:9bcdf88f62b0 18176 ((INSTANCE) == DMA1_Channel6) || \
<> 128:9bcdf88f62b0 18177 ((INSTANCE) == DMA1_Channel7) || \
<> 128:9bcdf88f62b0 18178 ((INSTANCE) == DMA2_Channel1) || \
<> 128:9bcdf88f62b0 18179 ((INSTANCE) == DMA2_Channel2) || \
<> 128:9bcdf88f62b0 18180 ((INSTANCE) == DMA2_Channel3) || \
<> 128:9bcdf88f62b0 18181 ((INSTANCE) == DMA2_Channel4) || \
<> 128:9bcdf88f62b0 18182 ((INSTANCE) == DMA2_Channel5) || \
<> 128:9bcdf88f62b0 18183 ((INSTANCE) == DMA2_Channel6) || \
<> 128:9bcdf88f62b0 18184 ((INSTANCE) == DMA2_Channel7))
<> 128:9bcdf88f62b0 18185
<> 128:9bcdf88f62b0 18186 /******************************* GPIO Instances *******************************/
<> 128:9bcdf88f62b0 18187 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
<> 128:9bcdf88f62b0 18188 ((INSTANCE) == GPIOB) || \
<> 128:9bcdf88f62b0 18189 ((INSTANCE) == GPIOC) || \
<> 128:9bcdf88f62b0 18190 ((INSTANCE) == GPIOD) || \
<> 128:9bcdf88f62b0 18191 ((INSTANCE) == GPIOE) || \
<> 128:9bcdf88f62b0 18192 ((INSTANCE) == GPIOF) || \
<> 128:9bcdf88f62b0 18193 ((INSTANCE) == GPIOG) || \
<> 128:9bcdf88f62b0 18194 ((INSTANCE) == GPIOH))
<> 128:9bcdf88f62b0 18195
<> 128:9bcdf88f62b0 18196 /******************************* GPIO AF Instances ****************************/
<> 128:9bcdf88f62b0 18197 /* On L4, all GPIO Bank support AF */
<> 128:9bcdf88f62b0 18198 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
<> 128:9bcdf88f62b0 18199
<> 128:9bcdf88f62b0 18200 /**************************** GPIO Lock Instances *****************************/
<> 128:9bcdf88f62b0 18201 /* On L4, all GPIO Bank support the Lock mechanism */
<> 128:9bcdf88f62b0 18202 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
<> 128:9bcdf88f62b0 18203
<> 128:9bcdf88f62b0 18204 /******************************** I2C Instances *******************************/
<> 128:9bcdf88f62b0 18205 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
<> 128:9bcdf88f62b0 18206 ((INSTANCE) == I2C2) || \
<> 128:9bcdf88f62b0 18207 ((INSTANCE) == I2C3))
<> 128:9bcdf88f62b0 18208
<> 128:9bcdf88f62b0 18209 /****************** I2C Instances : wakeup capability from stop modes *********/
<> 128:9bcdf88f62b0 18210 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
<> 128:9bcdf88f62b0 18211
<> 128:9bcdf88f62b0 18212 /******************************* LCD Instances ********************************/
<> 128:9bcdf88f62b0 18213 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
<> 128:9bcdf88f62b0 18214
<> 128:9bcdf88f62b0 18215 /******************************* HCD Instances *******************************/
<> 128:9bcdf88f62b0 18216 #define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
<> 128:9bcdf88f62b0 18217
<> 128:9bcdf88f62b0 18218 /****************************** OPAMP Instances *******************************/
<> 128:9bcdf88f62b0 18219 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
<> 128:9bcdf88f62b0 18220 ((INSTANCE) == OPAMP2))
<> 128:9bcdf88f62b0 18221
<> 128:9bcdf88f62b0 18222 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
<> 128:9bcdf88f62b0 18223
<> 128:9bcdf88f62b0 18224 /******************************* PCD Instances *******************************/
<> 128:9bcdf88f62b0 18225 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
<> 128:9bcdf88f62b0 18226
<> 128:9bcdf88f62b0 18227 /******************************* QSPI Instances *******************************/
<> 128:9bcdf88f62b0 18228 #define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
<> 128:9bcdf88f62b0 18229
<> 128:9bcdf88f62b0 18230 /******************************* RNG Instances ********************************/
<> 128:9bcdf88f62b0 18231 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
<> 128:9bcdf88f62b0 18232
<> 128:9bcdf88f62b0 18233 /****************************** RTC Instances *********************************/
<> 128:9bcdf88f62b0 18234 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
<> 128:9bcdf88f62b0 18235
<> 128:9bcdf88f62b0 18236 /******************************** SAI Instances *******************************/
<> 128:9bcdf88f62b0 18237 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
<> 128:9bcdf88f62b0 18238 ((INSTANCE) == SAI1_Block_B) || \
<> 128:9bcdf88f62b0 18239 ((INSTANCE) == SAI2_Block_A) || \
<> 128:9bcdf88f62b0 18240 ((INSTANCE) == SAI2_Block_B))
<> 128:9bcdf88f62b0 18241
<> 128:9bcdf88f62b0 18242 /****************************** SDMMC Instances *******************************/
<> 128:9bcdf88f62b0 18243 #define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
<> 128:9bcdf88f62b0 18244
<> 128:9bcdf88f62b0 18245 /****************************** SMBUS Instances *******************************/
<> 128:9bcdf88f62b0 18246 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
<> 128:9bcdf88f62b0 18247 ((INSTANCE) == I2C2) || \
<> 128:9bcdf88f62b0 18248 ((INSTANCE) == I2C3))
<> 128:9bcdf88f62b0 18249
<> 128:9bcdf88f62b0 18250 /******************************** SPI Instances *******************************/
<> 128:9bcdf88f62b0 18251 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
<> 128:9bcdf88f62b0 18252 ((INSTANCE) == SPI2) || \
<> 128:9bcdf88f62b0 18253 ((INSTANCE) == SPI3))
<> 128:9bcdf88f62b0 18254
<> 128:9bcdf88f62b0 18255 /******************************** SWPMI Instances *****************************/
<> 128:9bcdf88f62b0 18256 #define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
<> 128:9bcdf88f62b0 18257
<> 128:9bcdf88f62b0 18258 /****************** LPTIM Instances : All supported instances *****************/
<> 128:9bcdf88f62b0 18259 #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
<> 128:9bcdf88f62b0 18260 ((INSTANCE) == LPTIM2))
<> 128:9bcdf88f62b0 18261
<> 128:9bcdf88f62b0 18262 /****************** TIM Instances : All supported instances *******************/
<> 128:9bcdf88f62b0 18263 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18264 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18265 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18266 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 18267 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 18268 ((INSTANCE) == TIM6) || \
<> 128:9bcdf88f62b0 18269 ((INSTANCE) == TIM7) || \
<> 128:9bcdf88f62b0 18270 ((INSTANCE) == TIM8) || \
<> 128:9bcdf88f62b0 18271 ((INSTANCE) == TIM15) || \
<> 128:9bcdf88f62b0 18272 ((INSTANCE) == TIM16) || \
<> 128:9bcdf88f62b0 18273 ((INSTANCE) == TIM17))
<> 128:9bcdf88f62b0 18274
<> 128:9bcdf88f62b0 18275 /****************** TIM Instances : supporting 32 bits counter ****************/
<> 128:9bcdf88f62b0 18276 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18277 ((INSTANCE) == TIM5))
<> 128:9bcdf88f62b0 18278
<> 128:9bcdf88f62b0 18279 /****************** TIM Instances : supporting the break function *************/
<> 128:9bcdf88f62b0 18280 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18281 ((INSTANCE) == TIM8) || \
<> 128:9bcdf88f62b0 18282 ((INSTANCE) == TIM15) || \
<> 128:9bcdf88f62b0 18283 ((INSTANCE) == TIM16) || \
<> 128:9bcdf88f62b0 18284 ((INSTANCE) == TIM17))
<> 128:9bcdf88f62b0 18285
<> 128:9bcdf88f62b0 18286 /************** TIM Instances : supporting Break source selection *************/
<> 128:9bcdf88f62b0 18287 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18288 ((INSTANCE) == TIM8) || \
<> 128:9bcdf88f62b0 18289 ((INSTANCE) == TIM15) || \
<> 128:9bcdf88f62b0 18290 ((INSTANCE) == TIM16) || \
<> 128:9bcdf88f62b0 18291 ((INSTANCE) == TIM17))
<> 128:9bcdf88f62b0 18292
<> 128:9bcdf88f62b0 18293 /****************** TIM Instances : supporting 2 break inputs *****************/
<> 128:9bcdf88f62b0 18294 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18295 ((INSTANCE) == TIM8))
<> 128:9bcdf88f62b0 18296
<> 128:9bcdf88f62b0 18297 /************* TIM Instances : at least 1 capture/compare channel *************/
<> 128:9bcdf88f62b0 18298 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18299 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18300 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18301 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 18302 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 18303 ((INSTANCE) == TIM8) || \
<> 128:9bcdf88f62b0 18304 ((INSTANCE) == TIM15) || \
<> 128:9bcdf88f62b0 18305 ((INSTANCE) == TIM16) || \
<> 128:9bcdf88f62b0 18306 ((INSTANCE) == TIM17))
<> 128:9bcdf88f62b0 18307
<> 128:9bcdf88f62b0 18308 /************ TIM Instances : at least 2 capture/compare channels *************/
<> 128:9bcdf88f62b0 18309 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18310 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18311 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18312 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 18313 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 18314 ((INSTANCE) == TIM8) || \
<> 128:9bcdf88f62b0 18315 ((INSTANCE) == TIM15))
<> 128:9bcdf88f62b0 18316
<> 128:9bcdf88f62b0 18317 /************ TIM Instances : at least 3 capture/compare channels *************/
<> 128:9bcdf88f62b0 18318 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18319 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18320 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18321 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 18322 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 18323 ((INSTANCE) == TIM8))
<> 128:9bcdf88f62b0 18324
<> 128:9bcdf88f62b0 18325 /************ TIM Instances : at least 4 capture/compare channels *************/
<> 128:9bcdf88f62b0 18326 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18327 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18328 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18329 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 18330 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 18331 ((INSTANCE) == TIM8))
<> 128:9bcdf88f62b0 18332
<> 128:9bcdf88f62b0 18333 /****************** TIM Instances : at least 5 capture/compare channels *******/
<> 128:9bcdf88f62b0 18334 #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18335 ((INSTANCE) == TIM8))
<> 128:9bcdf88f62b0 18336
<> 128:9bcdf88f62b0 18337 /****************** TIM Instances : at least 6 capture/compare channels *******/
<> 128:9bcdf88f62b0 18338 #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18339 ((INSTANCE) == TIM8))
<> 128:9bcdf88f62b0 18340
<> 128:9bcdf88f62b0 18341 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
<> 128:9bcdf88f62b0 18342 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18343 ((INSTANCE) == TIM8) || \
<> 128:9bcdf88f62b0 18344 ((INSTANCE) == TIM15) || \
<> 128:9bcdf88f62b0 18345 ((INSTANCE) == TIM16) || \
<> 128:9bcdf88f62b0 18346 ((INSTANCE) == TIM17))
<> 128:9bcdf88f62b0 18347
<> 128:9bcdf88f62b0 18348 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
<> 128:9bcdf88f62b0 18349 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18350 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18351 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18352 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 18353 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 18354 ((INSTANCE) == TIM6) || \
<> 128:9bcdf88f62b0 18355 ((INSTANCE) == TIM7) || \
<> 128:9bcdf88f62b0 18356 ((INSTANCE) == TIM8) || \
<> 128:9bcdf88f62b0 18357 ((INSTANCE) == TIM15) || \
<> 128:9bcdf88f62b0 18358 ((INSTANCE) == TIM16) || \
<> 128:9bcdf88f62b0 18359 ((INSTANCE) == TIM17))
<> 128:9bcdf88f62b0 18360
<> 128:9bcdf88f62b0 18361 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
<> 128:9bcdf88f62b0 18362 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18363 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18364 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18365 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 18366 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 18367 ((INSTANCE) == TIM8) || \
<> 128:9bcdf88f62b0 18368 ((INSTANCE) == TIM15) || \
<> 128:9bcdf88f62b0 18369 ((INSTANCE) == TIM16) || \
<> 128:9bcdf88f62b0 18370 ((INSTANCE) == TIM17))
<> 128:9bcdf88f62b0 18371
<> 128:9bcdf88f62b0 18372 /******************** TIM Instances : DMA burst feature ***********************/
<> 128:9bcdf88f62b0 18373 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18374 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18375 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18376 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 18377 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 18378 ((INSTANCE) == TIM8) || \
<> 128:9bcdf88f62b0 18379 ((INSTANCE) == TIM15) || \
<> 128:9bcdf88f62b0 18380 ((INSTANCE) == TIM16) || \
<> 128:9bcdf88f62b0 18381 ((INSTANCE) == TIM17))
<> 128:9bcdf88f62b0 18382
<> 128:9bcdf88f62b0 18383 /******************* TIM Instances : output(s) available **********************/
<> 128:9bcdf88f62b0 18384 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
<> 128:9bcdf88f62b0 18385 ((((INSTANCE) == TIM1) && \
<> 128:9bcdf88f62b0 18386 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 18387 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 128:9bcdf88f62b0 18388 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 128:9bcdf88f62b0 18389 ((CHANNEL) == TIM_CHANNEL_4) || \
<> 128:9bcdf88f62b0 18390 ((CHANNEL) == TIM_CHANNEL_5) || \
<> 128:9bcdf88f62b0 18391 ((CHANNEL) == TIM_CHANNEL_6))) \
<> 128:9bcdf88f62b0 18392 || \
<> 128:9bcdf88f62b0 18393 (((INSTANCE) == TIM2) && \
<> 128:9bcdf88f62b0 18394 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 18395 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 128:9bcdf88f62b0 18396 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 128:9bcdf88f62b0 18397 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 128:9bcdf88f62b0 18398 || \
<> 128:9bcdf88f62b0 18399 (((INSTANCE) == TIM3) && \
<> 128:9bcdf88f62b0 18400 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 18401 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 128:9bcdf88f62b0 18402 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 128:9bcdf88f62b0 18403 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 128:9bcdf88f62b0 18404 || \
<> 128:9bcdf88f62b0 18405 (((INSTANCE) == TIM4) && \
<> 128:9bcdf88f62b0 18406 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 18407 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 128:9bcdf88f62b0 18408 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 128:9bcdf88f62b0 18409 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 128:9bcdf88f62b0 18410 || \
<> 128:9bcdf88f62b0 18411 (((INSTANCE) == TIM5) && \
<> 128:9bcdf88f62b0 18412 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 18413 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 128:9bcdf88f62b0 18414 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 128:9bcdf88f62b0 18415 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 128:9bcdf88f62b0 18416 || \
<> 128:9bcdf88f62b0 18417 (((INSTANCE) == TIM8) && \
<> 128:9bcdf88f62b0 18418 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 18419 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 128:9bcdf88f62b0 18420 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 128:9bcdf88f62b0 18421 ((CHANNEL) == TIM_CHANNEL_4) || \
<> 128:9bcdf88f62b0 18422 ((CHANNEL) == TIM_CHANNEL_5) || \
<> 128:9bcdf88f62b0 18423 ((CHANNEL) == TIM_CHANNEL_6))) \
<> 128:9bcdf88f62b0 18424 || \
<> 128:9bcdf88f62b0 18425 (((INSTANCE) == TIM15) && \
<> 128:9bcdf88f62b0 18426 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 18427 ((CHANNEL) == TIM_CHANNEL_2))) \
<> 128:9bcdf88f62b0 18428 || \
<> 128:9bcdf88f62b0 18429 (((INSTANCE) == TIM16) && \
<> 128:9bcdf88f62b0 18430 (((CHANNEL) == TIM_CHANNEL_1))) \
<> 128:9bcdf88f62b0 18431 || \
<> 128:9bcdf88f62b0 18432 (((INSTANCE) == TIM17) && \
<> 128:9bcdf88f62b0 18433 (((CHANNEL) == TIM_CHANNEL_1))))
<> 128:9bcdf88f62b0 18434
<> 128:9bcdf88f62b0 18435 /****************** TIM Instances : supporting complementary output(s) ********/
<> 128:9bcdf88f62b0 18436 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
<> 128:9bcdf88f62b0 18437 ((((INSTANCE) == TIM1) && \
<> 128:9bcdf88f62b0 18438 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 18439 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 128:9bcdf88f62b0 18440 ((CHANNEL) == TIM_CHANNEL_3))) \
<> 128:9bcdf88f62b0 18441 || \
<> 128:9bcdf88f62b0 18442 (((INSTANCE) == TIM8) && \
<> 128:9bcdf88f62b0 18443 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 18444 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 128:9bcdf88f62b0 18445 ((CHANNEL) == TIM_CHANNEL_3))) \
<> 128:9bcdf88f62b0 18446 || \
<> 128:9bcdf88f62b0 18447 (((INSTANCE) == TIM15) && \
<> 128:9bcdf88f62b0 18448 ((CHANNEL) == TIM_CHANNEL_1)) \
<> 128:9bcdf88f62b0 18449 || \
<> 128:9bcdf88f62b0 18450 (((INSTANCE) == TIM16) && \
<> 128:9bcdf88f62b0 18451 ((CHANNEL) == TIM_CHANNEL_1)) \
<> 128:9bcdf88f62b0 18452 || \
<> 128:9bcdf88f62b0 18453 (((INSTANCE) == TIM17) && \
<> 128:9bcdf88f62b0 18454 ((CHANNEL) == TIM_CHANNEL_1)))
<> 128:9bcdf88f62b0 18455
<> 128:9bcdf88f62b0 18456 /****************** TIM Instances : supporting clock division *****************/
<> 128:9bcdf88f62b0 18457 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18458 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18459 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18460 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 18461 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 18462 ((INSTANCE) == TIM8) || \
<> 128:9bcdf88f62b0 18463 ((INSTANCE) == TIM15) || \
<> 128:9bcdf88f62b0 18464 ((INSTANCE) == TIM16) || \
<> 128:9bcdf88f62b0 18465 ((INSTANCE) == TIM17))
<> 128:9bcdf88f62b0 18466
<> 128:9bcdf88f62b0 18467 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
<> 128:9bcdf88f62b0 18468 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18469 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18470 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18471 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 18472 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 18473 ((INSTANCE) == TIM8) || \
<> 128:9bcdf88f62b0 18474 ((INSTANCE) == TIM15))
<> 128:9bcdf88f62b0 18475
<> 128:9bcdf88f62b0 18476 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
<> 128:9bcdf88f62b0 18477 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18478 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18479 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18480 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 18481 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 18482 ((INSTANCE) == TIM8))
<> 128:9bcdf88f62b0 18483
<> 128:9bcdf88f62b0 18484 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
<> 128:9bcdf88f62b0 18485 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18486 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18487 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18488 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 18489 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 18490 ((INSTANCE) == TIM8) || \
<> 128:9bcdf88f62b0 18491 ((INSTANCE) == TIM15))
<> 128:9bcdf88f62b0 18492
<> 128:9bcdf88f62b0 18493 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
<> 128:9bcdf88f62b0 18494 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18495 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18496 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18497 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 18498 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 18499 ((INSTANCE) == TIM8) || \
<> 128:9bcdf88f62b0 18500 ((INSTANCE) == TIM15))
<> 128:9bcdf88f62b0 18501
<> 128:9bcdf88f62b0 18502 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
<> 128:9bcdf88f62b0 18503 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18504 ((INSTANCE) == TIM8))
<> 128:9bcdf88f62b0 18505
<> 128:9bcdf88f62b0 18506 /****************** TIM Instances : supporting commutation event generation ***/
<> 128:9bcdf88f62b0 18507 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18508 ((INSTANCE) == TIM8) || \
<> 128:9bcdf88f62b0 18509 ((INSTANCE) == TIM15) || \
<> 128:9bcdf88f62b0 18510 ((INSTANCE) == TIM16) || \
<> 128:9bcdf88f62b0 18511 ((INSTANCE) == TIM17))
<> 128:9bcdf88f62b0 18512
<> 128:9bcdf88f62b0 18513 /****************** TIM Instances : supporting counting mode selection ********/
<> 128:9bcdf88f62b0 18514 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18515 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18516 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18517 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 18518 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 18519 ((INSTANCE) == TIM8))
<> 128:9bcdf88f62b0 18520
<> 128:9bcdf88f62b0 18521 /****************** TIM Instances : supporting encoder interface **************/
<> 128:9bcdf88f62b0 18522 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18523 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18524 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18525 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 18526 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 18527 ((INSTANCE) == TIM8))
<> 128:9bcdf88f62b0 18528
<> 128:9bcdf88f62b0 18529 /****************** TIM Instances : supporting Hall sensor interface **********/
<> 128:9bcdf88f62b0 18530 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18531 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18532 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18533 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 18534 ((INSTANCE) == TIM5))
<> 128:9bcdf88f62b0 18535
<> 128:9bcdf88f62b0 18536 /**************** TIM Instances : external trigger input available ************/
<> 128:9bcdf88f62b0 18537 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18538 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18539 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18540 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 18541 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 18542 ((INSTANCE) == TIM8))
<> 128:9bcdf88f62b0 18543
<> 128:9bcdf88f62b0 18544 /************* TIM Instances : supporting ETR source selection ***************/
<> 128:9bcdf88f62b0 18545 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18546 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18547 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18548 ((INSTANCE) == TIM8))
<> 128:9bcdf88f62b0 18549
<> 128:9bcdf88f62b0 18550 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
<> 128:9bcdf88f62b0 18551 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18552 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18553 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18554 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 18555 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 18556 ((INSTANCE) == TIM6) || \
<> 128:9bcdf88f62b0 18557 ((INSTANCE) == TIM7) || \
<> 128:9bcdf88f62b0 18558 ((INSTANCE) == TIM8) || \
<> 128:9bcdf88f62b0 18559 ((INSTANCE) == TIM15))
<> 128:9bcdf88f62b0 18560
<> 128:9bcdf88f62b0 18561 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
<> 128:9bcdf88f62b0 18562 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18563 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18564 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18565 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 18566 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 18567 ((INSTANCE) == TIM8) || \
<> 128:9bcdf88f62b0 18568 ((INSTANCE) == TIM15))
<> 128:9bcdf88f62b0 18569
<> 128:9bcdf88f62b0 18570 /****************** TIM Instances : supporting OCxREF clear *******************/
<> 128:9bcdf88f62b0 18571 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18572 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18573 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18574 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 18575 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 18576 ((INSTANCE) == TIM8))
<> 128:9bcdf88f62b0 18577
<> 128:9bcdf88f62b0 18578 /****************** TIM Instances : remapping capability **********************/
<> 128:9bcdf88f62b0 18579 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18580 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18581 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18582 ((INSTANCE) == TIM8) || \
<> 128:9bcdf88f62b0 18583 ((INSTANCE) == TIM15) || \
<> 128:9bcdf88f62b0 18584 ((INSTANCE) == TIM16) || \
<> 128:9bcdf88f62b0 18585 ((INSTANCE) == TIM17))
<> 128:9bcdf88f62b0 18586
<> 128:9bcdf88f62b0 18587 /****************** TIM Instances : supporting repetition counter *************/
<> 128:9bcdf88f62b0 18588 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18589 ((INSTANCE) == TIM8) || \
<> 128:9bcdf88f62b0 18590 ((INSTANCE) == TIM15) || \
<> 128:9bcdf88f62b0 18591 ((INSTANCE) == TIM16) || \
<> 128:9bcdf88f62b0 18592 ((INSTANCE) == TIM17))
<> 128:9bcdf88f62b0 18593
<> 128:9bcdf88f62b0 18594 /****************** TIM Instances : supporting synchronization ****************/
<> 128:9bcdf88f62b0 18595 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
<> 128:9bcdf88f62b0 18596
<> 128:9bcdf88f62b0 18597 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
<> 128:9bcdf88f62b0 18598 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18599 ((INSTANCE) == TIM8))
<> 128:9bcdf88f62b0 18600
<> 128:9bcdf88f62b0 18601 /******************* TIM Instances : Timer input XOR function *****************/
<> 128:9bcdf88f62b0 18602 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 128:9bcdf88f62b0 18603 ((INSTANCE) == TIM2) || \
<> 128:9bcdf88f62b0 18604 ((INSTANCE) == TIM3) || \
<> 128:9bcdf88f62b0 18605 ((INSTANCE) == TIM4) || \
<> 128:9bcdf88f62b0 18606 ((INSTANCE) == TIM5) || \
<> 128:9bcdf88f62b0 18607 ((INSTANCE) == TIM8) || \
<> 128:9bcdf88f62b0 18608 ((INSTANCE) == TIM15))
<> 128:9bcdf88f62b0 18609
<> 128:9bcdf88f62b0 18610 /****************************** TSC Instances *********************************/
<> 128:9bcdf88f62b0 18611 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
<> 128:9bcdf88f62b0 18612
<> 128:9bcdf88f62b0 18613 /******************** USART Instances : Synchronous mode **********************/
<> 128:9bcdf88f62b0 18614 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 128:9bcdf88f62b0 18615 ((INSTANCE) == USART2) || \
<> 128:9bcdf88f62b0 18616 ((INSTANCE) == USART3))
<> 128:9bcdf88f62b0 18617
<> 128:9bcdf88f62b0 18618 /******************** UART Instances : Asynchronous mode **********************/
<> 128:9bcdf88f62b0 18619 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 128:9bcdf88f62b0 18620 ((INSTANCE) == USART2) || \
<> 128:9bcdf88f62b0 18621 ((INSTANCE) == USART3) || \
<> 128:9bcdf88f62b0 18622 ((INSTANCE) == UART4) || \
<> 128:9bcdf88f62b0 18623 ((INSTANCE) == UART5))
<> 128:9bcdf88f62b0 18624
<> 128:9bcdf88f62b0 18625 /****************** UART Instances : Auto Baud Rate detection ****************/
<> 128:9bcdf88f62b0 18626 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 128:9bcdf88f62b0 18627 ((INSTANCE) == USART2) || \
<> 128:9bcdf88f62b0 18628 ((INSTANCE) == USART3) || \
<> 128:9bcdf88f62b0 18629 ((INSTANCE) == UART4) || \
<> 128:9bcdf88f62b0 18630 ((INSTANCE) == UART5))
<> 128:9bcdf88f62b0 18631
<> 128:9bcdf88f62b0 18632 /****************** UART Instances : Driver Enable *****************/
<> 128:9bcdf88f62b0 18633 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 128:9bcdf88f62b0 18634 ((INSTANCE) == USART2) || \
<> 128:9bcdf88f62b0 18635 ((INSTANCE) == USART3) || \
<> 128:9bcdf88f62b0 18636 ((INSTANCE) == UART4) || \
<> 128:9bcdf88f62b0 18637 ((INSTANCE) == UART5) || \
<> 128:9bcdf88f62b0 18638 ((INSTANCE) == LPUART1))
<> 128:9bcdf88f62b0 18639
<> 128:9bcdf88f62b0 18640 /******************** UART Instances : Half-Duplex mode **********************/
<> 128:9bcdf88f62b0 18641 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 128:9bcdf88f62b0 18642 ((INSTANCE) == USART2) || \
<> 128:9bcdf88f62b0 18643 ((INSTANCE) == USART3) || \
<> 128:9bcdf88f62b0 18644 ((INSTANCE) == UART4) || \
<> 128:9bcdf88f62b0 18645 ((INSTANCE) == UART5) || \
<> 128:9bcdf88f62b0 18646 ((INSTANCE) == LPUART1))
<> 128:9bcdf88f62b0 18647
<> 128:9bcdf88f62b0 18648 /****************** UART Instances : Hardware Flow control ********************/
<> 128:9bcdf88f62b0 18649 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 128:9bcdf88f62b0 18650 ((INSTANCE) == USART2) || \
<> 128:9bcdf88f62b0 18651 ((INSTANCE) == USART3) || \
<> 128:9bcdf88f62b0 18652 ((INSTANCE) == UART4) || \
<> 128:9bcdf88f62b0 18653 ((INSTANCE) == UART5) || \
<> 128:9bcdf88f62b0 18654 ((INSTANCE) == LPUART1))
<> 128:9bcdf88f62b0 18655
<> 128:9bcdf88f62b0 18656 /******************** UART Instances : LIN mode **********************/
<> 128:9bcdf88f62b0 18657 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 128:9bcdf88f62b0 18658 ((INSTANCE) == USART2) || \
<> 128:9bcdf88f62b0 18659 ((INSTANCE) == USART3) || \
<> 128:9bcdf88f62b0 18660 ((INSTANCE) == UART4) || \
<> 128:9bcdf88f62b0 18661 ((INSTANCE) == UART5))
<> 128:9bcdf88f62b0 18662
<> 128:9bcdf88f62b0 18663 /******************** UART Instances : Wake-up from Stop mode **********************/
<> 128:9bcdf88f62b0 18664 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 128:9bcdf88f62b0 18665 ((INSTANCE) == USART2) || \
<> 128:9bcdf88f62b0 18666 ((INSTANCE) == USART3) || \
<> 128:9bcdf88f62b0 18667 ((INSTANCE) == UART4) || \
<> 128:9bcdf88f62b0 18668 ((INSTANCE) == UART5) || \
<> 128:9bcdf88f62b0 18669 ((INSTANCE) == LPUART1))
<> 128:9bcdf88f62b0 18670
<> 128:9bcdf88f62b0 18671 /*********************** UART Instances : IRDA mode ***************************/
<> 128:9bcdf88f62b0 18672 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 128:9bcdf88f62b0 18673 ((INSTANCE) == USART2) || \
<> 128:9bcdf88f62b0 18674 ((INSTANCE) == USART3) || \
<> 128:9bcdf88f62b0 18675 ((INSTANCE) == UART4) || \
<> 128:9bcdf88f62b0 18676 ((INSTANCE) == UART5))
<> 128:9bcdf88f62b0 18677
<> 128:9bcdf88f62b0 18678 /********************* USART Instances : Smard card mode ***********************/
<> 128:9bcdf88f62b0 18679 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 128:9bcdf88f62b0 18680 ((INSTANCE) == USART2) || \
<> 128:9bcdf88f62b0 18681 ((INSTANCE) == USART3))
<> 128:9bcdf88f62b0 18682
<> 128:9bcdf88f62b0 18683 /******************** LPUART Instance *****************************************/
<> 128:9bcdf88f62b0 18684 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
<> 128:9bcdf88f62b0 18685
<> 128:9bcdf88f62b0 18686 /****************************** IWDG Instances ********************************/
<> 128:9bcdf88f62b0 18687 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
<> 128:9bcdf88f62b0 18688
<> 128:9bcdf88f62b0 18689 /****************************** WWDG Instances ********************************/
<> 128:9bcdf88f62b0 18690 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
<> 128:9bcdf88f62b0 18691
<> 128:9bcdf88f62b0 18692 /**
<> 128:9bcdf88f62b0 18693 * @}
<> 128:9bcdf88f62b0 18694 */
<> 128:9bcdf88f62b0 18695
<> 128:9bcdf88f62b0 18696
<> 128:9bcdf88f62b0 18697 /******************************************************************************/
<> 128:9bcdf88f62b0 18698 /* For a painless codes migration between the STM32L4xx device product */
<> 128:9bcdf88f62b0 18699 /* lines, the aliases defined below are put in place to overcome the */
<> 128:9bcdf88f62b0 18700 /* differences in the interrupt handlers and IRQn definitions. */
<> 128:9bcdf88f62b0 18701 /* No need to update developed interrupt code when moving across */
<> 128:9bcdf88f62b0 18702 /* product lines within the same STM32L4 Family */
<> 128:9bcdf88f62b0 18703 /******************************************************************************/
<> 128:9bcdf88f62b0 18704
<> 128:9bcdf88f62b0 18705 /* Aliases for __IRQn */
<> 128:9bcdf88f62b0 18706 #define ADC1_IRQn ADC1_2_IRQn
<> 128:9bcdf88f62b0 18707 #define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
<> 128:9bcdf88f62b0 18708 #define TIM8_IRQn TIM8_UP_IRQn
<> 128:9bcdf88f62b0 18709 #define DFSDM0_IRQn DFSDM1_FLT0_IRQn
<> 128:9bcdf88f62b0 18710 #define DFSDM1_IRQn DFSDM1_FLT1_IRQn
<> 128:9bcdf88f62b0 18711 #define DFSDM2_IRQn DFSDM1_FLT2_IRQn
<> 128:9bcdf88f62b0 18712 #define DFSDM3_IRQn DFSDM1_FLT3_IRQn
<> 128:9bcdf88f62b0 18713
<> 128:9bcdf88f62b0 18714 /* Aliases for __IRQHandler */
<> 128:9bcdf88f62b0 18715 #define ADC1_IRQHandler ADC1_2_IRQHandler
<> 128:9bcdf88f62b0 18716 #define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
<> 128:9bcdf88f62b0 18717 #define TIM8_IRQHandler TIM8_UP_IRQHandler
<> 128:9bcdf88f62b0 18718 #define DFSDM0_IRQHandler DFSDM1_FLT0_IRQHandler
<> 128:9bcdf88f62b0 18719 #define DFSDM1_IRQHandler DFSDM1_FLT1_IRQHandler
<> 128:9bcdf88f62b0 18720 #define DFSDM2_IRQHandler DFSDM1_FLT2_IRQHandler
<> 128:9bcdf88f62b0 18721 #define DFSDM3_IRQHandler DFSDM1_FLT3_IRQHandler
<> 128:9bcdf88f62b0 18722
<> 128:9bcdf88f62b0 18723 #ifdef __cplusplus
<> 128:9bcdf88f62b0 18724 }
<> 128:9bcdf88f62b0 18725 #endif /* __cplusplus */
<> 128:9bcdf88f62b0 18726
<> 128:9bcdf88f62b0 18727 #endif /* __STM32L486xx_H */
<> 128:9bcdf88f62b0 18728
<> 128:9bcdf88f62b0 18729 /**
<> 128:9bcdf88f62b0 18730 * @}
<> 128:9bcdf88f62b0 18731 */
<> 128:9bcdf88f62b0 18732
<> 128:9bcdf88f62b0 18733 /**
<> 128:9bcdf88f62b0 18734 * @}
<> 128:9bcdf88f62b0 18735 */
<> 128:9bcdf88f62b0 18736
<> 128:9bcdf88f62b0 18737 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/