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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32PG12_STK3402/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_usart.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
139:856d2700e60b 
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 139:856d2700e60b 1 /**************************************************************************//**
<> 139:856d2700e60b 2 * @file efm32pg12b_usart.h
<> 139:856d2700e60b 3 * @brief EFM32PG12B_USART register and bit field definitions
<> 139:856d2700e60b 4 * @version 5.1.2
<> 139:856d2700e60b 5 ******************************************************************************
<> 139:856d2700e60b 6 * @section License
<> 139:856d2700e60b 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 139:856d2700e60b 8 ******************************************************************************
<> 139:856d2700e60b 9 *
<> 139:856d2700e60b 10 * Permission is granted to anyone to use this software for any purpose,
<> 139:856d2700e60b 11 * including commercial applications, and to alter it and redistribute it
<> 139:856d2700e60b 12 * freely, subject to the following restrictions:
<> 139:856d2700e60b 13 *
<> 139:856d2700e60b 14 * 1. The origin of this software must not be misrepresented; you must not
<> 139:856d2700e60b 15 * claim that you wrote the original software.@n
<> 139:856d2700e60b 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 139:856d2700e60b 17 * misrepresented as being the original software.@n
<> 139:856d2700e60b 18 * 3. This notice may not be removed or altered from any source distribution.
<> 139:856d2700e60b 19 *
<> 139:856d2700e60b 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 139:856d2700e60b 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 139:856d2700e60b 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 139:856d2700e60b 23 * kind, including, but not limited to, any implied warranties of
<> 139:856d2700e60b 24 * merchantability or fitness for any particular purpose or warranties against
<> 139:856d2700e60b 25 * infringement of any proprietary rights of a third party.
<> 139:856d2700e60b 26 *
<> 139:856d2700e60b 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 139:856d2700e60b 28 * incidental, or special damages, or any other relief, or for any claim by
<> 139:856d2700e60b 29 * any third party, arising from your use of this Software.
<> 139:856d2700e60b 30 *
<> 139:856d2700e60b 31 *****************************************************************************/
<> 139:856d2700e60b 32 /**************************************************************************//**
<> 139:856d2700e60b 33 * @addtogroup Parts
<> 139:856d2700e60b 34 * @{
<> 139:856d2700e60b 35 ******************************************************************************/
<> 139:856d2700e60b 36 /**************************************************************************//**
<> 139:856d2700e60b 37 * @defgroup EFM32PG12B_USART
<> 139:856d2700e60b 38 * @{
<> 139:856d2700e60b 39 * @brief EFM32PG12B_USART Register Declaration
<> 139:856d2700e60b 40 *****************************************************************************/
<> 139:856d2700e60b 41 typedef struct
<> 139:856d2700e60b 42 {
<> 139:856d2700e60b 43 __IOM uint32_t CTRL; /**< Control Register */
<> 139:856d2700e60b 44 __IOM uint32_t FRAME; /**< USART Frame Format Register */
<> 139:856d2700e60b 45 __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */
<> 139:856d2700e60b 46 __IOM uint32_t CMD; /**< Command Register */
<> 139:856d2700e60b 47 __IM uint32_t STATUS; /**< USART Status Register */
<> 139:856d2700e60b 48 __IOM uint32_t CLKDIV; /**< Clock Control Register */
<> 139:856d2700e60b 49 __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */
<> 139:856d2700e60b 50 __IM uint32_t RXDATA; /**< RX Buffer Data Register */
<> 139:856d2700e60b 51 __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */
<> 139:856d2700e60b 52 __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */
<> 139:856d2700e60b 53 __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */
<> 139:856d2700e60b 54 __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */
<> 139:856d2700e60b 55 __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */
<> 139:856d2700e60b 56 __IOM uint32_t TXDATA; /**< TX Buffer Data Register */
<> 139:856d2700e60b 57 __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */
<> 139:856d2700e60b 58 __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */
<> 139:856d2700e60b 59 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 139:856d2700e60b 60 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 139:856d2700e60b 61 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 139:856d2700e60b 62 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 139:856d2700e60b 63 __IOM uint32_t IRCTRL; /**< IrDA Control Register */
<> 139:856d2700e60b 64 uint32_t RESERVED0[1]; /**< Reserved for future use **/
<> 139:856d2700e60b 65 __IOM uint32_t INPUT; /**< USART Input Register */
<> 139:856d2700e60b 66 __IOM uint32_t I2SCTRL; /**< I2S Control Register */
<> 139:856d2700e60b 67 __IOM uint32_t TIMING; /**< Timing Register */
<> 139:856d2700e60b 68 __IOM uint32_t CTRLX; /**< Control Register Extended */
<> 139:856d2700e60b 69 __IOM uint32_t TIMECMP0; /**< Used to generate interrupts and various delays */
<> 139:856d2700e60b 70 __IOM uint32_t TIMECMP1; /**< Used to generate interrupts and various delays */
<> 139:856d2700e60b 71 __IOM uint32_t TIMECMP2; /**< Used to generate interrupts and various delays */
<> 139:856d2700e60b 72 __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
<> 139:856d2700e60b 73 __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
<> 139:856d2700e60b 74 __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */
<> 139:856d2700e60b 75 } USART_TypeDef; /** @} */
<> 139:856d2700e60b 76
<> 139:856d2700e60b 77 /**************************************************************************//**
<> 139:856d2700e60b 78 * @defgroup EFM32PG12B_USART_BitFields
<> 139:856d2700e60b 79 * @{
<> 139:856d2700e60b 80 *****************************************************************************/
<> 139:856d2700e60b 81
<> 139:856d2700e60b 82 /* Bit fields for USART CTRL */
<> 139:856d2700e60b 83 #define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */
<> 139:856d2700e60b 84 #define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */
<> 139:856d2700e60b 85 #define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */
<> 139:856d2700e60b 86 #define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */
<> 139:856d2700e60b 87 #define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */
<> 139:856d2700e60b 88 #define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 89 #define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 90 #define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */
<> 139:856d2700e60b 91 #define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */
<> 139:856d2700e60b 92 #define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */
<> 139:856d2700e60b 93 #define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 94 #define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 95 #define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */
<> 139:856d2700e60b 96 #define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */
<> 139:856d2700e60b 97 #define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */
<> 139:856d2700e60b 98 #define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 99 #define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 100 #define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */
<> 139:856d2700e60b 101 #define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */
<> 139:856d2700e60b 102 #define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */
<> 139:856d2700e60b 103 #define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 104 #define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 105 #define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */
<> 139:856d2700e60b 106 #define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */
<> 139:856d2700e60b 107 #define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */
<> 139:856d2700e60b 108 #define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 109 #define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 110 #define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */
<> 139:856d2700e60b 111 #define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */
<> 139:856d2700e60b 112 #define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 113 #define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */
<> 139:856d2700e60b 114 #define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */
<> 139:856d2700e60b 115 #define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */
<> 139:856d2700e60b 116 #define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */
<> 139:856d2700e60b 117 #define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 118 #define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */
<> 139:856d2700e60b 119 #define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */
<> 139:856d2700e60b 120 #define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */
<> 139:856d2700e60b 121 #define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */
<> 139:856d2700e60b 122 #define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */
<> 139:856d2700e60b 123 #define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */
<> 139:856d2700e60b 124 #define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */
<> 139:856d2700e60b 125 #define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 126 #define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */
<> 139:856d2700e60b 127 #define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */
<> 139:856d2700e60b 128 #define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 129 #define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */
<> 139:856d2700e60b 130 #define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */
<> 139:856d2700e60b 131 #define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */
<> 139:856d2700e60b 132 #define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */
<> 139:856d2700e60b 133 #define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */
<> 139:856d2700e60b 134 #define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 135 #define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */
<> 139:856d2700e60b 136 #define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */
<> 139:856d2700e60b 137 #define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 138 #define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */
<> 139:856d2700e60b 139 #define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */
<> 139:856d2700e60b 140 #define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */
<> 139:856d2700e60b 141 #define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */
<> 139:856d2700e60b 142 #define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */
<> 139:856d2700e60b 143 #define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 144 #define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 145 #define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Slave-Select In Master Mode */
<> 139:856d2700e60b 146 #define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */
<> 139:856d2700e60b 147 #define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */
<> 139:856d2700e60b 148 #define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 149 #define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */
<> 139:856d2700e60b 150 #define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */
<> 139:856d2700e60b 151 #define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 152 #define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */
<> 139:856d2700e60b 153 #define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */
<> 139:856d2700e60b 154 #define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */
<> 139:856d2700e60b 155 #define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */
<> 139:856d2700e60b 156 #define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */
<> 139:856d2700e60b 157 #define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 158 #define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */
<> 139:856d2700e60b 159 #define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */
<> 139:856d2700e60b 160 #define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 161 #define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */
<> 139:856d2700e60b 162 #define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */
<> 139:856d2700e60b 163 #define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */
<> 139:856d2700e60b 164 #define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */
<> 139:856d2700e60b 165 #define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */
<> 139:856d2700e60b 166 #define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 167 #define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 168 #define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */
<> 139:856d2700e60b 169 #define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */
<> 139:856d2700e60b 170 #define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */
<> 139:856d2700e60b 171 #define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 172 #define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 173 #define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */
<> 139:856d2700e60b 174 #define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */
<> 139:856d2700e60b 175 #define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */
<> 139:856d2700e60b 176 #define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 177 #define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 178 #define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */
<> 139:856d2700e60b 179 #define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */
<> 139:856d2700e60b 180 #define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */
<> 139:856d2700e60b 181 #define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 182 #define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 183 #define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */
<> 139:856d2700e60b 184 #define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */
<> 139:856d2700e60b 185 #define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */
<> 139:856d2700e60b 186 #define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 187 #define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 188 #define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */
<> 139:856d2700e60b 189 #define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */
<> 139:856d2700e60b 190 #define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */
<> 139:856d2700e60b 191 #define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 192 #define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 193 #define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */
<> 139:856d2700e60b 194 #define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */
<> 139:856d2700e60b 195 #define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */
<> 139:856d2700e60b 196 #define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 197 #define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 198 #define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */
<> 139:856d2700e60b 199 #define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */
<> 139:856d2700e60b 200 #define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */
<> 139:856d2700e60b 201 #define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 202 #define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 203 #define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */
<> 139:856d2700e60b 204 #define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */
<> 139:856d2700e60b 205 #define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */
<> 139:856d2700e60b 206 #define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 207 #define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 208 #define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */
<> 139:856d2700e60b 209 #define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */
<> 139:856d2700e60b 210 #define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */
<> 139:856d2700e60b 211 #define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 212 #define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 213 #define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */
<> 139:856d2700e60b 214 #define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */
<> 139:856d2700e60b 215 #define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */
<> 139:856d2700e60b 216 #define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 217 #define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 218 #define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */
<> 139:856d2700e60b 219 #define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */
<> 139:856d2700e60b 220 #define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */
<> 139:856d2700e60b 221 #define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 222 #define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 223 #define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */
<> 139:856d2700e60b 224 #define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */
<> 139:856d2700e60b 225 #define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */
<> 139:856d2700e60b 226 #define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 227 #define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 228 #define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */
<> 139:856d2700e60b 229 #define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */
<> 139:856d2700e60b 230 #define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */
<> 139:856d2700e60b 231 #define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 232 #define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 233 #define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */
<> 139:856d2700e60b 234 #define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */
<> 139:856d2700e60b 235 #define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */
<> 139:856d2700e60b 236 #define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 237 #define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 238 #define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */
<> 139:856d2700e60b 239 #define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */
<> 139:856d2700e60b 240 #define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */
<> 139:856d2700e60b 241 #define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 242 #define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 243 #define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */
<> 139:856d2700e60b 244 #define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */
<> 139:856d2700e60b 245 #define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */
<> 139:856d2700e60b 246 #define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 247 #define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */
<> 139:856d2700e60b 248
<> 139:856d2700e60b 249 /* Bit fields for USART FRAME */
<> 139:856d2700e60b 250 #define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */
<> 139:856d2700e60b 251 #define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */
<> 139:856d2700e60b 252 #define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */
<> 139:856d2700e60b 253 #define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */
<> 139:856d2700e60b 254 #define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */
<> 139:856d2700e60b 255 #define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */
<> 139:856d2700e60b 256 #define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */
<> 139:856d2700e60b 257 #define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */
<> 139:856d2700e60b 258 #define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */
<> 139:856d2700e60b 259 #define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */
<> 139:856d2700e60b 260 #define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */
<> 139:856d2700e60b 261 #define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */
<> 139:856d2700e60b 262 #define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */
<> 139:856d2700e60b 263 #define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */
<> 139:856d2700e60b 264 #define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */
<> 139:856d2700e60b 265 #define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */
<> 139:856d2700e60b 266 #define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */
<> 139:856d2700e60b 267 #define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */
<> 139:856d2700e60b 268 #define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */
<> 139:856d2700e60b 269 #define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */
<> 139:856d2700e60b 270 #define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */
<> 139:856d2700e60b 271 #define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */
<> 139:856d2700e60b 272 #define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */
<> 139:856d2700e60b 273 #define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */
<> 139:856d2700e60b 274 #define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */
<> 139:856d2700e60b 275 #define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */
<> 139:856d2700e60b 276 #define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */
<> 139:856d2700e60b 277 #define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */
<> 139:856d2700e60b 278 #define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */
<> 139:856d2700e60b 279 #define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */
<> 139:856d2700e60b 280 #define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */
<> 139:856d2700e60b 281 #define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */
<> 139:856d2700e60b 282 #define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */
<> 139:856d2700e60b 283 #define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */
<> 139:856d2700e60b 284 #define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */
<> 139:856d2700e60b 285 #define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */
<> 139:856d2700e60b 286 #define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */
<> 139:856d2700e60b 287 #define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */
<> 139:856d2700e60b 288 #define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */
<> 139:856d2700e60b 289 #define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */
<> 139:856d2700e60b 290 #define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */
<> 139:856d2700e60b 291 #define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */
<> 139:856d2700e60b 292 #define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */
<> 139:856d2700e60b 293 #define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */
<> 139:856d2700e60b 294 #define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */
<> 139:856d2700e60b 295 #define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */
<> 139:856d2700e60b 296 #define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */
<> 139:856d2700e60b 297 #define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */
<> 139:856d2700e60b 298 #define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */
<> 139:856d2700e60b 299 #define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */
<> 139:856d2700e60b 300 #define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */
<> 139:856d2700e60b 301 #define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */
<> 139:856d2700e60b 302 #define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */
<> 139:856d2700e60b 303 #define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */
<> 139:856d2700e60b 304
<> 139:856d2700e60b 305 /* Bit fields for USART TRIGCTRL */
<> 139:856d2700e60b 306 #define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */
<> 139:856d2700e60b 307 #define _USART_TRIGCTRL_MASK 0x000F1FF0UL /**< Mask for USART_TRIGCTRL */
<> 139:856d2700e60b 308 #define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */
<> 139:856d2700e60b 309 #define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */
<> 139:856d2700e60b 310 #define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */
<> 139:856d2700e60b 311 #define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 139:856d2700e60b 312 #define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 139:856d2700e60b 313 #define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */
<> 139:856d2700e60b 314 #define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */
<> 139:856d2700e60b 315 #define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */
<> 139:856d2700e60b 316 #define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 139:856d2700e60b 317 #define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 139:856d2700e60b 318 #define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */
<> 139:856d2700e60b 319 #define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */
<> 139:856d2700e60b 320 #define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */
<> 139:856d2700e60b 321 #define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 139:856d2700e60b 322 #define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 139:856d2700e60b 323 #define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of Frame plus TCMP0VAL */
<> 139:856d2700e60b 324 #define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */
<> 139:856d2700e60b 325 #define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */
<> 139:856d2700e60b 326 #define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 139:856d2700e60b 327 #define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 139:856d2700e60b 328 #define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of Frame plus TCMP1VAL */
<> 139:856d2700e60b 329 #define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */
<> 139:856d2700e60b 330 #define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */
<> 139:856d2700e60b 331 #define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 139:856d2700e60b 332 #define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 139:856d2700e60b 333 #define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of Frame plus TCMP2VAL */
<> 139:856d2700e60b 334 #define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */
<> 139:856d2700e60b 335 #define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */
<> 139:856d2700e60b 336 #define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 139:856d2700e60b 337 #define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 139:856d2700e60b 338 #define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL0 baud-times */
<> 139:856d2700e60b 339 #define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */
<> 139:856d2700e60b 340 #define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */
<> 139:856d2700e60b 341 #define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 139:856d2700e60b 342 #define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 139:856d2700e60b 343 #define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL1 baud-times */
<> 139:856d2700e60b 344 #define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */
<> 139:856d2700e60b 345 #define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */
<> 139:856d2700e60b 346 #define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 139:856d2700e60b 347 #define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 139:856d2700e60b 348 #define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL2 baud-times */
<> 139:856d2700e60b 349 #define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */
<> 139:856d2700e60b 350 #define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */
<> 139:856d2700e60b 351 #define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 139:856d2700e60b 352 #define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 139:856d2700e60b 353 #define _USART_TRIGCTRL_TSEL_SHIFT 16 /**< Shift value for USART_TSEL */
<> 139:856d2700e60b 354 #define _USART_TRIGCTRL_TSEL_MASK 0xF0000UL /**< Bit mask for USART_TSEL */
<> 139:856d2700e60b 355 #define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 139:856d2700e60b 356 #define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_TRIGCTRL */
<> 139:856d2700e60b 357 #define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_TRIGCTRL */
<> 139:856d2700e60b 358 #define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_TRIGCTRL */
<> 139:856d2700e60b 359 #define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_TRIGCTRL */
<> 139:856d2700e60b 360 #define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_TRIGCTRL */
<> 139:856d2700e60b 361 #define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_TRIGCTRL */
<> 139:856d2700e60b 362 #define _USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_TRIGCTRL */
<> 139:856d2700e60b 363 #define _USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_TRIGCTRL */
<> 139:856d2700e60b 364 #define _USART_TRIGCTRL_TSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_TRIGCTRL */
<> 139:856d2700e60b 365 #define _USART_TRIGCTRL_TSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_TRIGCTRL */
<> 139:856d2700e60b 366 #define _USART_TRIGCTRL_TSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_TRIGCTRL */
<> 139:856d2700e60b 367 #define _USART_TRIGCTRL_TSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_TRIGCTRL */
<> 139:856d2700e60b 368 #define USART_TRIGCTRL_TSEL_DEFAULT (_USART_TRIGCTRL_TSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 139:856d2700e60b 369 #define USART_TRIGCTRL_TSEL_PRSCH0 (_USART_TRIGCTRL_TSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for USART_TRIGCTRL */
<> 139:856d2700e60b 370 #define USART_TRIGCTRL_TSEL_PRSCH1 (_USART_TRIGCTRL_TSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for USART_TRIGCTRL */
<> 139:856d2700e60b 371 #define USART_TRIGCTRL_TSEL_PRSCH2 (_USART_TRIGCTRL_TSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for USART_TRIGCTRL */
<> 139:856d2700e60b 372 #define USART_TRIGCTRL_TSEL_PRSCH3 (_USART_TRIGCTRL_TSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for USART_TRIGCTRL */
<> 139:856d2700e60b 373 #define USART_TRIGCTRL_TSEL_PRSCH4 (_USART_TRIGCTRL_TSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for USART_TRIGCTRL */
<> 139:856d2700e60b 374 #define USART_TRIGCTRL_TSEL_PRSCH5 (_USART_TRIGCTRL_TSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for USART_TRIGCTRL */
<> 139:856d2700e60b 375 #define USART_TRIGCTRL_TSEL_PRSCH6 (_USART_TRIGCTRL_TSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for USART_TRIGCTRL */
<> 139:856d2700e60b 376 #define USART_TRIGCTRL_TSEL_PRSCH7 (_USART_TRIGCTRL_TSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for USART_TRIGCTRL */
<> 139:856d2700e60b 377 #define USART_TRIGCTRL_TSEL_PRSCH8 (_USART_TRIGCTRL_TSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for USART_TRIGCTRL */
<> 139:856d2700e60b 378 #define USART_TRIGCTRL_TSEL_PRSCH9 (_USART_TRIGCTRL_TSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for USART_TRIGCTRL */
<> 139:856d2700e60b 379 #define USART_TRIGCTRL_TSEL_PRSCH10 (_USART_TRIGCTRL_TSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for USART_TRIGCTRL */
<> 139:856d2700e60b 380 #define USART_TRIGCTRL_TSEL_PRSCH11 (_USART_TRIGCTRL_TSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for USART_TRIGCTRL */
<> 139:856d2700e60b 381
<> 139:856d2700e60b 382 /* Bit fields for USART CMD */
<> 139:856d2700e60b 383 #define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */
<> 139:856d2700e60b 384 #define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */
<> 139:856d2700e60b 385 #define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */
<> 139:856d2700e60b 386 #define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */
<> 139:856d2700e60b 387 #define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */
<> 139:856d2700e60b 388 #define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 389 #define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 390 #define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */
<> 139:856d2700e60b 391 #define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */
<> 139:856d2700e60b 392 #define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */
<> 139:856d2700e60b 393 #define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 394 #define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 395 #define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */
<> 139:856d2700e60b 396 #define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */
<> 139:856d2700e60b 397 #define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */
<> 139:856d2700e60b 398 #define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 399 #define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 400 #define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */
<> 139:856d2700e60b 401 #define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */
<> 139:856d2700e60b 402 #define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */
<> 139:856d2700e60b 403 #define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 404 #define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 405 #define USART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */
<> 139:856d2700e60b 406 #define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */
<> 139:856d2700e60b 407 #define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */
<> 139:856d2700e60b 408 #define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 409 #define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 410 #define USART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */
<> 139:856d2700e60b 411 #define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */
<> 139:856d2700e60b 412 #define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */
<> 139:856d2700e60b 413 #define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 414 #define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 415 #define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */
<> 139:856d2700e60b 416 #define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */
<> 139:856d2700e60b 417 #define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */
<> 139:856d2700e60b 418 #define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 419 #define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 420 #define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */
<> 139:856d2700e60b 421 #define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */
<> 139:856d2700e60b 422 #define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */
<> 139:856d2700e60b 423 #define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 424 #define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 425 #define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */
<> 139:856d2700e60b 426 #define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */
<> 139:856d2700e60b 427 #define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */
<> 139:856d2700e60b 428 #define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 429 #define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 430 #define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */
<> 139:856d2700e60b 431 #define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */
<> 139:856d2700e60b 432 #define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */
<> 139:856d2700e60b 433 #define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 434 #define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 435 #define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */
<> 139:856d2700e60b 436 #define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */
<> 139:856d2700e60b 437 #define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */
<> 139:856d2700e60b 438 #define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 439 #define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 440 #define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */
<> 139:856d2700e60b 441 #define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */
<> 139:856d2700e60b 442 #define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */
<> 139:856d2700e60b 443 #define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 444 #define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */
<> 139:856d2700e60b 445
<> 139:856d2700e60b 446 /* Bit fields for USART STATUS */
<> 139:856d2700e60b 447 #define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */
<> 139:856d2700e60b 448 #define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */
<> 139:856d2700e60b 449 #define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */
<> 139:856d2700e60b 450 #define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */
<> 139:856d2700e60b 451 #define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */
<> 139:856d2700e60b 452 #define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 453 #define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 454 #define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */
<> 139:856d2700e60b 455 #define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */
<> 139:856d2700e60b 456 #define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */
<> 139:856d2700e60b 457 #define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 458 #define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 459 #define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */
<> 139:856d2700e60b 460 #define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */
<> 139:856d2700e60b 461 #define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */
<> 139:856d2700e60b 462 #define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 463 #define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 464 #define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */
<> 139:856d2700e60b 465 #define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */
<> 139:856d2700e60b 466 #define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */
<> 139:856d2700e60b 467 #define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 468 #define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 469 #define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */
<> 139:856d2700e60b 470 #define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */
<> 139:856d2700e60b 471 #define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */
<> 139:856d2700e60b 472 #define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 473 #define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 474 #define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */
<> 139:856d2700e60b 475 #define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */
<> 139:856d2700e60b 476 #define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */
<> 139:856d2700e60b 477 #define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 478 #define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 479 #define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */
<> 139:856d2700e60b 480 #define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */
<> 139:856d2700e60b 481 #define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */
<> 139:856d2700e60b 482 #define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 483 #define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 484 #define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */
<> 139:856d2700e60b 485 #define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */
<> 139:856d2700e60b 486 #define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */
<> 139:856d2700e60b 487 #define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 488 #define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 489 #define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */
<> 139:856d2700e60b 490 #define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */
<> 139:856d2700e60b 491 #define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */
<> 139:856d2700e60b 492 #define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 493 #define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 494 #define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */
<> 139:856d2700e60b 495 #define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */
<> 139:856d2700e60b 496 #define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */
<> 139:856d2700e60b 497 #define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 498 #define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 499 #define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */
<> 139:856d2700e60b 500 #define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */
<> 139:856d2700e60b 501 #define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */
<> 139:856d2700e60b 502 #define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 503 #define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 504 #define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */
<> 139:856d2700e60b 505 #define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */
<> 139:856d2700e60b 506 #define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */
<> 139:856d2700e60b 507 #define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 508 #define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 509 #define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */
<> 139:856d2700e60b 510 #define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */
<> 139:856d2700e60b 511 #define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */
<> 139:856d2700e60b 512 #define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 513 #define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 514 #define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */
<> 139:856d2700e60b 515 #define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
<> 139:856d2700e60b 516 #define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
<> 139:856d2700e60b 517 #define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 518 #define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 519 #define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */
<> 139:856d2700e60b 520 #define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */
<> 139:856d2700e60b 521 #define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */
<> 139:856d2700e60b 522 #define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 523 #define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 524 #define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */
<> 139:856d2700e60b 525 #define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */
<> 139:856d2700e60b 526 #define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 527 #define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */
<> 139:856d2700e60b 528
<> 139:856d2700e60b 529 /* Bit fields for USART CLKDIV */
<> 139:856d2700e60b 530 #define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */
<> 139:856d2700e60b 531 #define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */
<> 139:856d2700e60b 532 #define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */
<> 139:856d2700e60b 533 #define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */
<> 139:856d2700e60b 534 #define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */
<> 139:856d2700e60b 535 #define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */
<> 139:856d2700e60b 536 #define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */
<> 139:856d2700e60b 537 #define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */
<> 139:856d2700e60b 538 #define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */
<> 139:856d2700e60b 539 #define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */
<> 139:856d2700e60b 540 #define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */
<> 139:856d2700e60b 541
<> 139:856d2700e60b 542 /* Bit fields for USART RXDATAX */
<> 139:856d2700e60b 543 #define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */
<> 139:856d2700e60b 544 #define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */
<> 139:856d2700e60b 545 #define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
<> 139:856d2700e60b 546 #define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */
<> 139:856d2700e60b 547 #define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
<> 139:856d2700e60b 548 #define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */
<> 139:856d2700e60b 549 #define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */
<> 139:856d2700e60b 550 #define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */
<> 139:856d2700e60b 551 #define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */
<> 139:856d2700e60b 552 #define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
<> 139:856d2700e60b 553 #define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */
<> 139:856d2700e60b 554 #define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */
<> 139:856d2700e60b 555 #define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */
<> 139:856d2700e60b 556 #define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */
<> 139:856d2700e60b 557 #define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
<> 139:856d2700e60b 558 #define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */
<> 139:856d2700e60b 559
<> 139:856d2700e60b 560 /* Bit fields for USART RXDATA */
<> 139:856d2700e60b 561 #define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */
<> 139:856d2700e60b 562 #define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */
<> 139:856d2700e60b 563 #define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
<> 139:856d2700e60b 564 #define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */
<> 139:856d2700e60b 565 #define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */
<> 139:856d2700e60b 566 #define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */
<> 139:856d2700e60b 567
<> 139:856d2700e60b 568 /* Bit fields for USART RXDOUBLEX */
<> 139:856d2700e60b 569 #define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */
<> 139:856d2700e60b 570 #define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */
<> 139:856d2700e60b 571 #define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
<> 139:856d2700e60b 572 #define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */
<> 139:856d2700e60b 573 #define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
<> 139:856d2700e60b 574 #define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
<> 139:856d2700e60b 575 #define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */
<> 139:856d2700e60b 576 #define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */
<> 139:856d2700e60b 577 #define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */
<> 139:856d2700e60b 578 #define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
<> 139:856d2700e60b 579 #define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
<> 139:856d2700e60b 580 #define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */
<> 139:856d2700e60b 581 #define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */
<> 139:856d2700e60b 582 #define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */
<> 139:856d2700e60b 583 #define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
<> 139:856d2700e60b 584 #define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
<> 139:856d2700e60b 585 #define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */
<> 139:856d2700e60b 586 #define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */
<> 139:856d2700e60b 587 #define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
<> 139:856d2700e60b 588 #define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
<> 139:856d2700e60b 589 #define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */
<> 139:856d2700e60b 590 #define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */
<> 139:856d2700e60b 591 #define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */
<> 139:856d2700e60b 592 #define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
<> 139:856d2700e60b 593 #define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
<> 139:856d2700e60b 594 #define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */
<> 139:856d2700e60b 595 #define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */
<> 139:856d2700e60b 596 #define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */
<> 139:856d2700e60b 597 #define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
<> 139:856d2700e60b 598 #define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
<> 139:856d2700e60b 599
<> 139:856d2700e60b 600 /* Bit fields for USART RXDOUBLE */
<> 139:856d2700e60b 601 #define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */
<> 139:856d2700e60b 602 #define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */
<> 139:856d2700e60b 603 #define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
<> 139:856d2700e60b 604 #define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */
<> 139:856d2700e60b 605 #define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */
<> 139:856d2700e60b 606 #define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */
<> 139:856d2700e60b 607 #define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */
<> 139:856d2700e60b 608 #define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */
<> 139:856d2700e60b 609 #define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */
<> 139:856d2700e60b 610 #define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */
<> 139:856d2700e60b 611
<> 139:856d2700e60b 612 /* Bit fields for USART RXDATAXP */
<> 139:856d2700e60b 613 #define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */
<> 139:856d2700e60b 614 #define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */
<> 139:856d2700e60b 615 #define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */
<> 139:856d2700e60b 616 #define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */
<> 139:856d2700e60b 617 #define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
<> 139:856d2700e60b 618 #define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */
<> 139:856d2700e60b 619 #define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */
<> 139:856d2700e60b 620 #define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */
<> 139:856d2700e60b 621 #define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */
<> 139:856d2700e60b 622 #define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
<> 139:856d2700e60b 623 #define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */
<> 139:856d2700e60b 624 #define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */
<> 139:856d2700e60b 625 #define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */
<> 139:856d2700e60b 626 #define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */
<> 139:856d2700e60b 627 #define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
<> 139:856d2700e60b 628 #define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */
<> 139:856d2700e60b 629
<> 139:856d2700e60b 630 /* Bit fields for USART RXDOUBLEXP */
<> 139:856d2700e60b 631 #define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */
<> 139:856d2700e60b 632 #define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */
<> 139:856d2700e60b 633 #define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */
<> 139:856d2700e60b 634 #define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */
<> 139:856d2700e60b 635 #define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
<> 139:856d2700e60b 636 #define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
<> 139:856d2700e60b 637 #define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */
<> 139:856d2700e60b 638 #define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */
<> 139:856d2700e60b 639 #define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */
<> 139:856d2700e60b 640 #define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
<> 139:856d2700e60b 641 #define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
<> 139:856d2700e60b 642 #define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */
<> 139:856d2700e60b 643 #define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */
<> 139:856d2700e60b 644 #define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */
<> 139:856d2700e60b 645 #define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
<> 139:856d2700e60b 646 #define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
<> 139:856d2700e60b 647 #define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */
<> 139:856d2700e60b 648 #define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */
<> 139:856d2700e60b 649 #define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
<> 139:856d2700e60b 650 #define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
<> 139:856d2700e60b 651 #define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */
<> 139:856d2700e60b 652 #define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */
<> 139:856d2700e60b 653 #define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */
<> 139:856d2700e60b 654 #define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
<> 139:856d2700e60b 655 #define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
<> 139:856d2700e60b 656 #define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */
<> 139:856d2700e60b 657 #define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */
<> 139:856d2700e60b 658 #define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */
<> 139:856d2700e60b 659 #define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
<> 139:856d2700e60b 660 #define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
<> 139:856d2700e60b 661
<> 139:856d2700e60b 662 /* Bit fields for USART TXDATAX */
<> 139:856d2700e60b 663 #define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */
<> 139:856d2700e60b 664 #define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */
<> 139:856d2700e60b 665 #define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */
<> 139:856d2700e60b 666 #define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */
<> 139:856d2700e60b 667 #define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
<> 139:856d2700e60b 668 #define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */
<> 139:856d2700e60b 669 #define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */
<> 139:856d2700e60b 670 #define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */
<> 139:856d2700e60b 671 #define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */
<> 139:856d2700e60b 672 #define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
<> 139:856d2700e60b 673 #define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */
<> 139:856d2700e60b 674 #define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */
<> 139:856d2700e60b 675 #define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */
<> 139:856d2700e60b 676 #define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */
<> 139:856d2700e60b 677 #define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
<> 139:856d2700e60b 678 #define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */
<> 139:856d2700e60b 679 #define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */
<> 139:856d2700e60b 680 #define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */
<> 139:856d2700e60b 681 #define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */
<> 139:856d2700e60b 682 #define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
<> 139:856d2700e60b 683 #define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */
<> 139:856d2700e60b 684 #define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */
<> 139:856d2700e60b 685 #define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */
<> 139:856d2700e60b 686 #define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */
<> 139:856d2700e60b 687 #define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
<> 139:856d2700e60b 688 #define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */
<> 139:856d2700e60b 689 #define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */
<> 139:856d2700e60b 690 #define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */
<> 139:856d2700e60b 691 #define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */
<> 139:856d2700e60b 692 #define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
<> 139:856d2700e60b 693 #define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */
<> 139:856d2700e60b 694
<> 139:856d2700e60b 695 /* Bit fields for USART TXDATA */
<> 139:856d2700e60b 696 #define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */
<> 139:856d2700e60b 697 #define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */
<> 139:856d2700e60b 698 #define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */
<> 139:856d2700e60b 699 #define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */
<> 139:856d2700e60b 700 #define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */
<> 139:856d2700e60b 701 #define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */
<> 139:856d2700e60b 702
<> 139:856d2700e60b 703 /* Bit fields for USART TXDOUBLEX */
<> 139:856d2700e60b 704 #define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */
<> 139:856d2700e60b 705 #define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */
<> 139:856d2700e60b 706 #define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
<> 139:856d2700e60b 707 #define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */
<> 139:856d2700e60b 708 #define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 709 #define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 710 #define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */
<> 139:856d2700e60b 711 #define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */
<> 139:856d2700e60b 712 #define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */
<> 139:856d2700e60b 713 #define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 714 #define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 715 #define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */
<> 139:856d2700e60b 716 #define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */
<> 139:856d2700e60b 717 #define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */
<> 139:856d2700e60b 718 #define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 719 #define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 720 #define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */
<> 139:856d2700e60b 721 #define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */
<> 139:856d2700e60b 722 #define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */
<> 139:856d2700e60b 723 #define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 724 #define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 725 #define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */
<> 139:856d2700e60b 726 #define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */
<> 139:856d2700e60b 727 #define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */
<> 139:856d2700e60b 728 #define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 729 #define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 730 #define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */
<> 139:856d2700e60b 731 #define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */
<> 139:856d2700e60b 732 #define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */
<> 139:856d2700e60b 733 #define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 734 #define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 735 #define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */
<> 139:856d2700e60b 736 #define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */
<> 139:856d2700e60b 737 #define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 738 #define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 739 #define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */
<> 139:856d2700e60b 740 #define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */
<> 139:856d2700e60b 741 #define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */
<> 139:856d2700e60b 742 #define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 743 #define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 744 #define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */
<> 139:856d2700e60b 745 #define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */
<> 139:856d2700e60b 746 #define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */
<> 139:856d2700e60b 747 #define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 748 #define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 749 #define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */
<> 139:856d2700e60b 750 #define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */
<> 139:856d2700e60b 751 #define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */
<> 139:856d2700e60b 752 #define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 753 #define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 754 #define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */
<> 139:856d2700e60b 755 #define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */
<> 139:856d2700e60b 756 #define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */
<> 139:856d2700e60b 757 #define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 758 #define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 759 #define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */
<> 139:856d2700e60b 760 #define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */
<> 139:856d2700e60b 761 #define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */
<> 139:856d2700e60b 762 #define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 763 #define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 139:856d2700e60b 764
<> 139:856d2700e60b 765 /* Bit fields for USART TXDOUBLE */
<> 139:856d2700e60b 766 #define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */
<> 139:856d2700e60b 767 #define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */
<> 139:856d2700e60b 768 #define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
<> 139:856d2700e60b 769 #define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */
<> 139:856d2700e60b 770 #define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */
<> 139:856d2700e60b 771 #define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */
<> 139:856d2700e60b 772 #define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */
<> 139:856d2700e60b 773 #define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */
<> 139:856d2700e60b 774 #define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */
<> 139:856d2700e60b 775 #define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */
<> 139:856d2700e60b 776
<> 139:856d2700e60b 777 /* Bit fields for USART IF */
<> 139:856d2700e60b 778 #define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */
<> 139:856d2700e60b 779 #define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */
<> 139:856d2700e60b 780 #define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */
<> 139:856d2700e60b 781 #define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */
<> 139:856d2700e60b 782 #define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
<> 139:856d2700e60b 783 #define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 139:856d2700e60b 784 #define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */
<> 139:856d2700e60b 785 #define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */
<> 139:856d2700e60b 786 #define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
<> 139:856d2700e60b 787 #define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
<> 139:856d2700e60b 788 #define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */
<> 139:856d2700e60b 789 #define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */
<> 139:856d2700e60b 790 #define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */
<> 139:856d2700e60b 791 #define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
<> 139:856d2700e60b 792 #define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
<> 139:856d2700e60b 793 #define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 139:856d2700e60b 794 #define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */
<> 139:856d2700e60b 795 #define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */
<> 139:856d2700e60b 796 #define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
<> 139:856d2700e60b 797 #define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
<> 139:856d2700e60b 798 #define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 139:856d2700e60b 799 #define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */
<> 139:856d2700e60b 800 #define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */
<> 139:856d2700e60b 801 #define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
<> 139:856d2700e60b 802 #define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
<> 139:856d2700e60b 803 #define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 139:856d2700e60b 804 #define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */
<> 139:856d2700e60b 805 #define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */
<> 139:856d2700e60b 806 #define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
<> 139:856d2700e60b 807 #define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
<> 139:856d2700e60b 808 #define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 139:856d2700e60b 809 #define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */
<> 139:856d2700e60b 810 #define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */
<> 139:856d2700e60b 811 #define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
<> 139:856d2700e60b 812 #define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
<> 139:856d2700e60b 813 #define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 139:856d2700e60b 814 #define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */
<> 139:856d2700e60b 815 #define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */
<> 139:856d2700e60b 816 #define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
<> 139:856d2700e60b 817 #define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
<> 139:856d2700e60b 818 #define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 139:856d2700e60b 819 #define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */
<> 139:856d2700e60b 820 #define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */
<> 139:856d2700e60b 821 #define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */
<> 139:856d2700e60b 822 #define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
<> 139:856d2700e60b 823 #define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 139:856d2700e60b 824 #define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */
<> 139:856d2700e60b 825 #define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */
<> 139:856d2700e60b 826 #define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */
<> 139:856d2700e60b 827 #define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
<> 139:856d2700e60b 828 #define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 139:856d2700e60b 829 #define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */
<> 139:856d2700e60b 830 #define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */
<> 139:856d2700e60b 831 #define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
<> 139:856d2700e60b 832 #define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
<> 139:856d2700e60b 833 #define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 139:856d2700e60b 834 #define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */
<> 139:856d2700e60b 835 #define USART_IF_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Flag */
<> 139:856d2700e60b 836 #define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */
<> 139:856d2700e60b 837 #define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
<> 139:856d2700e60b 838 #define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 139:856d2700e60b 839 #define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */
<> 139:856d2700e60b 840 #define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */
<> 139:856d2700e60b 841 #define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */
<> 139:856d2700e60b 842 #define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
<> 139:856d2700e60b 843 #define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 139:856d2700e60b 844 #define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */
<> 139:856d2700e60b 845 #define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */
<> 139:856d2700e60b 846 #define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
<> 139:856d2700e60b 847 #define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
<> 139:856d2700e60b 848 #define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 139:856d2700e60b 849 #define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */
<> 139:856d2700e60b 850 #define USART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */
<> 139:856d2700e60b 851 #define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
<> 139:856d2700e60b 852 #define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
<> 139:856d2700e60b 853 #define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 139:856d2700e60b 854 #define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */
<> 139:856d2700e60b 855 #define USART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */
<> 139:856d2700e60b 856 #define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
<> 139:856d2700e60b 857 #define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
<> 139:856d2700e60b 858 #define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 139:856d2700e60b 859 #define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */
<> 139:856d2700e60b 860 #define USART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */
<> 139:856d2700e60b 861 #define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
<> 139:856d2700e60b 862 #define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
<> 139:856d2700e60b 863 #define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 139:856d2700e60b 864 #define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */
<> 139:856d2700e60b 865
<> 139:856d2700e60b 866 /* Bit fields for USART IFS */
<> 139:856d2700e60b 867 #define _USART_IFS_RESETVALUE 0x00000000UL /**< Default value for USART_IFS */
<> 139:856d2700e60b 868 #define _USART_IFS_MASK 0x0001FFF9UL /**< Mask for USART_IFS */
<> 139:856d2700e60b 869 #define USART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */
<> 139:856d2700e60b 870 #define _USART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */
<> 139:856d2700e60b 871 #define _USART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
<> 139:856d2700e60b 872 #define _USART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 873 #define USART_IFS_TXC_DEFAULT (_USART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 874 #define USART_IFS_RXFULL (0x1UL << 3) /**< Set RXFULL Interrupt Flag */
<> 139:856d2700e60b 875 #define _USART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
<> 139:856d2700e60b 876 #define _USART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
<> 139:856d2700e60b 877 #define _USART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 878 #define USART_IFS_RXFULL_DEFAULT (_USART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 879 #define USART_IFS_RXOF (0x1UL << 4) /**< Set RXOF Interrupt Flag */
<> 139:856d2700e60b 880 #define _USART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
<> 139:856d2700e60b 881 #define _USART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
<> 139:856d2700e60b 882 #define _USART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 883 #define USART_IFS_RXOF_DEFAULT (_USART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 884 #define USART_IFS_RXUF (0x1UL << 5) /**< Set RXUF Interrupt Flag */
<> 139:856d2700e60b 885 #define _USART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
<> 139:856d2700e60b 886 #define _USART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
<> 139:856d2700e60b 887 #define _USART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 888 #define USART_IFS_RXUF_DEFAULT (_USART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 889 #define USART_IFS_TXOF (0x1UL << 6) /**< Set TXOF Interrupt Flag */
<> 139:856d2700e60b 890 #define _USART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
<> 139:856d2700e60b 891 #define _USART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
<> 139:856d2700e60b 892 #define _USART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 893 #define USART_IFS_TXOF_DEFAULT (_USART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 894 #define USART_IFS_TXUF (0x1UL << 7) /**< Set TXUF Interrupt Flag */
<> 139:856d2700e60b 895 #define _USART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
<> 139:856d2700e60b 896 #define _USART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
<> 139:856d2700e60b 897 #define _USART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 898 #define USART_IFS_TXUF_DEFAULT (_USART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 899 #define USART_IFS_PERR (0x1UL << 8) /**< Set PERR Interrupt Flag */
<> 139:856d2700e60b 900 #define _USART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */
<> 139:856d2700e60b 901 #define _USART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
<> 139:856d2700e60b 902 #define _USART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 903 #define USART_IFS_PERR_DEFAULT (_USART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 904 #define USART_IFS_FERR (0x1UL << 9) /**< Set FERR Interrupt Flag */
<> 139:856d2700e60b 905 #define _USART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */
<> 139:856d2700e60b 906 #define _USART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
<> 139:856d2700e60b 907 #define _USART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 908 #define USART_IFS_FERR_DEFAULT (_USART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 909 #define USART_IFS_MPAF (0x1UL << 10) /**< Set MPAF Interrupt Flag */
<> 139:856d2700e60b 910 #define _USART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
<> 139:856d2700e60b 911 #define _USART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
<> 139:856d2700e60b 912 #define _USART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 913 #define USART_IFS_MPAF_DEFAULT (_USART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 914 #define USART_IFS_SSM (0x1UL << 11) /**< Set SSM Interrupt Flag */
<> 139:856d2700e60b 915 #define _USART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */
<> 139:856d2700e60b 916 #define _USART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
<> 139:856d2700e60b 917 #define _USART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 918 #define USART_IFS_SSM_DEFAULT (_USART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 919 #define USART_IFS_CCF (0x1UL << 12) /**< Set CCF Interrupt Flag */
<> 139:856d2700e60b 920 #define _USART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */
<> 139:856d2700e60b 921 #define _USART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
<> 139:856d2700e60b 922 #define _USART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 923 #define USART_IFS_CCF_DEFAULT (_USART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 924 #define USART_IFS_TXIDLE (0x1UL << 13) /**< Set TXIDLE Interrupt Flag */
<> 139:856d2700e60b 925 #define _USART_IFS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
<> 139:856d2700e60b 926 #define _USART_IFS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
<> 139:856d2700e60b 927 #define _USART_IFS_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 928 #define USART_IFS_TXIDLE_DEFAULT (_USART_IFS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 929 #define USART_IFS_TCMP0 (0x1UL << 14) /**< Set TCMP0 Interrupt Flag */
<> 139:856d2700e60b 930 #define _USART_IFS_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
<> 139:856d2700e60b 931 #define _USART_IFS_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
<> 139:856d2700e60b 932 #define _USART_IFS_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 933 #define USART_IFS_TCMP0_DEFAULT (_USART_IFS_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 934 #define USART_IFS_TCMP1 (0x1UL << 15) /**< Set TCMP1 Interrupt Flag */
<> 139:856d2700e60b 935 #define _USART_IFS_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
<> 139:856d2700e60b 936 #define _USART_IFS_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
<> 139:856d2700e60b 937 #define _USART_IFS_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 938 #define USART_IFS_TCMP1_DEFAULT (_USART_IFS_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 939 #define USART_IFS_TCMP2 (0x1UL << 16) /**< Set TCMP2 Interrupt Flag */
<> 139:856d2700e60b 940 #define _USART_IFS_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
<> 139:856d2700e60b 941 #define _USART_IFS_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
<> 139:856d2700e60b 942 #define _USART_IFS_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 943 #define USART_IFS_TCMP2_DEFAULT (_USART_IFS_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFS */
<> 139:856d2700e60b 944
<> 139:856d2700e60b 945 /* Bit fields for USART IFC */
<> 139:856d2700e60b 946 #define _USART_IFC_RESETVALUE 0x00000000UL /**< Default value for USART_IFC */
<> 139:856d2700e60b 947 #define _USART_IFC_MASK 0x0001FFF9UL /**< Mask for USART_IFC */
<> 139:856d2700e60b 948 #define USART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */
<> 139:856d2700e60b 949 #define _USART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */
<> 139:856d2700e60b 950 #define _USART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
<> 139:856d2700e60b 951 #define _USART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 952 #define USART_IFC_TXC_DEFAULT (_USART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 953 #define USART_IFC_RXFULL (0x1UL << 3) /**< Clear RXFULL Interrupt Flag */
<> 139:856d2700e60b 954 #define _USART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
<> 139:856d2700e60b 955 #define _USART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
<> 139:856d2700e60b 956 #define _USART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 957 #define USART_IFC_RXFULL_DEFAULT (_USART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 958 #define USART_IFC_RXOF (0x1UL << 4) /**< Clear RXOF Interrupt Flag */
<> 139:856d2700e60b 959 #define _USART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
<> 139:856d2700e60b 960 #define _USART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
<> 139:856d2700e60b 961 #define _USART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 962 #define USART_IFC_RXOF_DEFAULT (_USART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 963 #define USART_IFC_RXUF (0x1UL << 5) /**< Clear RXUF Interrupt Flag */
<> 139:856d2700e60b 964 #define _USART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
<> 139:856d2700e60b 965 #define _USART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
<> 139:856d2700e60b 966 #define _USART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 967 #define USART_IFC_RXUF_DEFAULT (_USART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 968 #define USART_IFC_TXOF (0x1UL << 6) /**< Clear TXOF Interrupt Flag */
<> 139:856d2700e60b 969 #define _USART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
<> 139:856d2700e60b 970 #define _USART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
<> 139:856d2700e60b 971 #define _USART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 972 #define USART_IFC_TXOF_DEFAULT (_USART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 973 #define USART_IFC_TXUF (0x1UL << 7) /**< Clear TXUF Interrupt Flag */
<> 139:856d2700e60b 974 #define _USART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
<> 139:856d2700e60b 975 #define _USART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
<> 139:856d2700e60b 976 #define _USART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 977 #define USART_IFC_TXUF_DEFAULT (_USART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 978 #define USART_IFC_PERR (0x1UL << 8) /**< Clear PERR Interrupt Flag */
<> 139:856d2700e60b 979 #define _USART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */
<> 139:856d2700e60b 980 #define _USART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
<> 139:856d2700e60b 981 #define _USART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 982 #define USART_IFC_PERR_DEFAULT (_USART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 983 #define USART_IFC_FERR (0x1UL << 9) /**< Clear FERR Interrupt Flag */
<> 139:856d2700e60b 984 #define _USART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */
<> 139:856d2700e60b 985 #define _USART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
<> 139:856d2700e60b 986 #define _USART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 987 #define USART_IFC_FERR_DEFAULT (_USART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 988 #define USART_IFC_MPAF (0x1UL << 10) /**< Clear MPAF Interrupt Flag */
<> 139:856d2700e60b 989 #define _USART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
<> 139:856d2700e60b 990 #define _USART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
<> 139:856d2700e60b 991 #define _USART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 992 #define USART_IFC_MPAF_DEFAULT (_USART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 993 #define USART_IFC_SSM (0x1UL << 11) /**< Clear SSM Interrupt Flag */
<> 139:856d2700e60b 994 #define _USART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */
<> 139:856d2700e60b 995 #define _USART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
<> 139:856d2700e60b 996 #define _USART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 997 #define USART_IFC_SSM_DEFAULT (_USART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 998 #define USART_IFC_CCF (0x1UL << 12) /**< Clear CCF Interrupt Flag */
<> 139:856d2700e60b 999 #define _USART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */
<> 139:856d2700e60b 1000 #define _USART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
<> 139:856d2700e60b 1001 #define _USART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 1002 #define USART_IFC_CCF_DEFAULT (_USART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 1003 #define USART_IFC_TXIDLE (0x1UL << 13) /**< Clear TXIDLE Interrupt Flag */
<> 139:856d2700e60b 1004 #define _USART_IFC_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
<> 139:856d2700e60b 1005 #define _USART_IFC_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
<> 139:856d2700e60b 1006 #define _USART_IFC_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 1007 #define USART_IFC_TXIDLE_DEFAULT (_USART_IFC_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 1008 #define USART_IFC_TCMP0 (0x1UL << 14) /**< Clear TCMP0 Interrupt Flag */
<> 139:856d2700e60b 1009 #define _USART_IFC_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
<> 139:856d2700e60b 1010 #define _USART_IFC_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
<> 139:856d2700e60b 1011 #define _USART_IFC_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 1012 #define USART_IFC_TCMP0_DEFAULT (_USART_IFC_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 1013 #define USART_IFC_TCMP1 (0x1UL << 15) /**< Clear TCMP1 Interrupt Flag */
<> 139:856d2700e60b 1014 #define _USART_IFC_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
<> 139:856d2700e60b 1015 #define _USART_IFC_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
<> 139:856d2700e60b 1016 #define _USART_IFC_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 1017 #define USART_IFC_TCMP1_DEFAULT (_USART_IFC_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 1018 #define USART_IFC_TCMP2 (0x1UL << 16) /**< Clear TCMP2 Interrupt Flag */
<> 139:856d2700e60b 1019 #define _USART_IFC_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
<> 139:856d2700e60b 1020 #define _USART_IFC_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
<> 139:856d2700e60b 1021 #define _USART_IFC_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 1022 #define USART_IFC_TCMP2_DEFAULT (_USART_IFC_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFC */
<> 139:856d2700e60b 1023
<> 139:856d2700e60b 1024 /* Bit fields for USART IEN */
<> 139:856d2700e60b 1025 #define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */
<> 139:856d2700e60b 1026 #define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */
<> 139:856d2700e60b 1027 #define USART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */
<> 139:856d2700e60b 1028 #define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */
<> 139:856d2700e60b 1029 #define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
<> 139:856d2700e60b 1030 #define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1031 #define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1032 #define USART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */
<> 139:856d2700e60b 1033 #define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
<> 139:856d2700e60b 1034 #define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
<> 139:856d2700e60b 1035 #define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1036 #define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1037 #define USART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */
<> 139:856d2700e60b 1038 #define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
<> 139:856d2700e60b 1039 #define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
<> 139:856d2700e60b 1040 #define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1041 #define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1042 #define USART_IEN_RXFULL (0x1UL << 3) /**< RXFULL Interrupt Enable */
<> 139:856d2700e60b 1043 #define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
<> 139:856d2700e60b 1044 #define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
<> 139:856d2700e60b 1045 #define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1046 #define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1047 #define USART_IEN_RXOF (0x1UL << 4) /**< RXOF Interrupt Enable */
<> 139:856d2700e60b 1048 #define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
<> 139:856d2700e60b 1049 #define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
<> 139:856d2700e60b 1050 #define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1051 #define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1052 #define USART_IEN_RXUF (0x1UL << 5) /**< RXUF Interrupt Enable */
<> 139:856d2700e60b 1053 #define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
<> 139:856d2700e60b 1054 #define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
<> 139:856d2700e60b 1055 #define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1056 #define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1057 #define USART_IEN_TXOF (0x1UL << 6) /**< TXOF Interrupt Enable */
<> 139:856d2700e60b 1058 #define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
<> 139:856d2700e60b 1059 #define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
<> 139:856d2700e60b 1060 #define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1061 #define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1062 #define USART_IEN_TXUF (0x1UL << 7) /**< TXUF Interrupt Enable */
<> 139:856d2700e60b 1063 #define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
<> 139:856d2700e60b 1064 #define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
<> 139:856d2700e60b 1065 #define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1066 #define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1067 #define USART_IEN_PERR (0x1UL << 8) /**< PERR Interrupt Enable */
<> 139:856d2700e60b 1068 #define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */
<> 139:856d2700e60b 1069 #define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
<> 139:856d2700e60b 1070 #define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1071 #define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1072 #define USART_IEN_FERR (0x1UL << 9) /**< FERR Interrupt Enable */
<> 139:856d2700e60b 1073 #define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */
<> 139:856d2700e60b 1074 #define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
<> 139:856d2700e60b 1075 #define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1076 #define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1077 #define USART_IEN_MPAF (0x1UL << 10) /**< MPAF Interrupt Enable */
<> 139:856d2700e60b 1078 #define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
<> 139:856d2700e60b 1079 #define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
<> 139:856d2700e60b 1080 #define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1081 #define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1082 #define USART_IEN_SSM (0x1UL << 11) /**< SSM Interrupt Enable */
<> 139:856d2700e60b 1083 #define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */
<> 139:856d2700e60b 1084 #define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
<> 139:856d2700e60b 1085 #define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1086 #define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1087 #define USART_IEN_CCF (0x1UL << 12) /**< CCF Interrupt Enable */
<> 139:856d2700e60b 1088 #define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */
<> 139:856d2700e60b 1089 #define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
<> 139:856d2700e60b 1090 #define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1091 #define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1092 #define USART_IEN_TXIDLE (0x1UL << 13) /**< TXIDLE Interrupt Enable */
<> 139:856d2700e60b 1093 #define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
<> 139:856d2700e60b 1094 #define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
<> 139:856d2700e60b 1095 #define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1096 #define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1097 #define USART_IEN_TCMP0 (0x1UL << 14) /**< TCMP0 Interrupt Enable */
<> 139:856d2700e60b 1098 #define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
<> 139:856d2700e60b 1099 #define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
<> 139:856d2700e60b 1100 #define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1101 #define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1102 #define USART_IEN_TCMP1 (0x1UL << 15) /**< TCMP1 Interrupt Enable */
<> 139:856d2700e60b 1103 #define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
<> 139:856d2700e60b 1104 #define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
<> 139:856d2700e60b 1105 #define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1106 #define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1107 #define USART_IEN_TCMP2 (0x1UL << 16) /**< TCMP2 Interrupt Enable */
<> 139:856d2700e60b 1108 #define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
<> 139:856d2700e60b 1109 #define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
<> 139:856d2700e60b 1110 #define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1111 #define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */
<> 139:856d2700e60b 1112
<> 139:856d2700e60b 1113 /* Bit fields for USART IRCTRL */
<> 139:856d2700e60b 1114 #define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */
<> 139:856d2700e60b 1115 #define _USART_IRCTRL_MASK 0x00000F8FUL /**< Mask for USART_IRCTRL */
<> 139:856d2700e60b 1116 #define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */
<> 139:856d2700e60b 1117 #define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */
<> 139:856d2700e60b 1118 #define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */
<> 139:856d2700e60b 1119 #define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
<> 139:856d2700e60b 1120 #define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */
<> 139:856d2700e60b 1121 #define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */
<> 139:856d2700e60b 1122 #define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */
<> 139:856d2700e60b 1123 #define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
<> 139:856d2700e60b 1124 #define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */
<> 139:856d2700e60b 1125 #define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */
<> 139:856d2700e60b 1126 #define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */
<> 139:856d2700e60b 1127 #define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */
<> 139:856d2700e60b 1128 #define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */
<> 139:856d2700e60b 1129 #define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */
<> 139:856d2700e60b 1130 #define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */
<> 139:856d2700e60b 1131 #define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */
<> 139:856d2700e60b 1132 #define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */
<> 139:856d2700e60b 1133 #define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */
<> 139:856d2700e60b 1134 #define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */
<> 139:856d2700e60b 1135 #define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */
<> 139:856d2700e60b 1136 #define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
<> 139:856d2700e60b 1137 #define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */
<> 139:856d2700e60b 1138 #define USART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */
<> 139:856d2700e60b 1139 #define _USART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */
<> 139:856d2700e60b 1140 #define _USART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */
<> 139:856d2700e60b 1141 #define _USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
<> 139:856d2700e60b 1142 #define USART_IRCTRL_IRPRSEN_DEFAULT (_USART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IRCTRL */
<> 139:856d2700e60b 1143 #define _USART_IRCTRL_IRPRSSEL_SHIFT 8 /**< Shift value for USART_IRPRSSEL */
<> 139:856d2700e60b 1144 #define _USART_IRCTRL_IRPRSSEL_MASK 0xF00UL /**< Bit mask for USART_IRPRSSEL */
<> 139:856d2700e60b 1145 #define _USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
<> 139:856d2700e60b 1146 #define _USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_IRCTRL */
<> 139:856d2700e60b 1147 #define _USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_IRCTRL */
<> 139:856d2700e60b 1148 #define _USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_IRCTRL */
<> 139:856d2700e60b 1149 #define _USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_IRCTRL */
<> 139:856d2700e60b 1150 #define _USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_IRCTRL */
<> 139:856d2700e60b 1151 #define _USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_IRCTRL */
<> 139:856d2700e60b 1152 #define _USART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_IRCTRL */
<> 139:856d2700e60b 1153 #define _USART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_IRCTRL */
<> 139:856d2700e60b 1154 #define _USART_IRCTRL_IRPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_IRCTRL */
<> 139:856d2700e60b 1155 #define _USART_IRCTRL_IRPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_IRCTRL */
<> 139:856d2700e60b 1156 #define _USART_IRCTRL_IRPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_IRCTRL */
<> 139:856d2700e60b 1157 #define _USART_IRCTRL_IRPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_IRCTRL */
<> 139:856d2700e60b 1158 #define USART_IRCTRL_IRPRSSEL_DEFAULT (_USART_IRCTRL_IRPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IRCTRL */
<> 139:856d2700e60b 1159 #define USART_IRCTRL_IRPRSSEL_PRSCH0 (_USART_IRCTRL_IRPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_IRCTRL */
<> 139:856d2700e60b 1160 #define USART_IRCTRL_IRPRSSEL_PRSCH1 (_USART_IRCTRL_IRPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_IRCTRL */
<> 139:856d2700e60b 1161 #define USART_IRCTRL_IRPRSSEL_PRSCH2 (_USART_IRCTRL_IRPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_IRCTRL */
<> 139:856d2700e60b 1162 #define USART_IRCTRL_IRPRSSEL_PRSCH3 (_USART_IRCTRL_IRPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_IRCTRL */
<> 139:856d2700e60b 1163 #define USART_IRCTRL_IRPRSSEL_PRSCH4 (_USART_IRCTRL_IRPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_IRCTRL */
<> 139:856d2700e60b 1164 #define USART_IRCTRL_IRPRSSEL_PRSCH5 (_USART_IRCTRL_IRPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_IRCTRL */
<> 139:856d2700e60b 1165 #define USART_IRCTRL_IRPRSSEL_PRSCH6 (_USART_IRCTRL_IRPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_IRCTRL */
<> 139:856d2700e60b 1166 #define USART_IRCTRL_IRPRSSEL_PRSCH7 (_USART_IRCTRL_IRPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_IRCTRL */
<> 139:856d2700e60b 1167 #define USART_IRCTRL_IRPRSSEL_PRSCH8 (_USART_IRCTRL_IRPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_IRCTRL */
<> 139:856d2700e60b 1168 #define USART_IRCTRL_IRPRSSEL_PRSCH9 (_USART_IRCTRL_IRPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_IRCTRL */
<> 139:856d2700e60b 1169 #define USART_IRCTRL_IRPRSSEL_PRSCH10 (_USART_IRCTRL_IRPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_IRCTRL */
<> 139:856d2700e60b 1170 #define USART_IRCTRL_IRPRSSEL_PRSCH11 (_USART_IRCTRL_IRPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_IRCTRL */
<> 139:856d2700e60b 1171
<> 139:856d2700e60b 1172 /* Bit fields for USART INPUT */
<> 139:856d2700e60b 1173 #define _USART_INPUT_RESETVALUE 0x00000000UL /**< Default value for USART_INPUT */
<> 139:856d2700e60b 1174 #define _USART_INPUT_MASK 0x00008F8FUL /**< Mask for USART_INPUT */
<> 139:856d2700e60b 1175 #define _USART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */
<> 139:856d2700e60b 1176 #define _USART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for USART_RXPRSSEL */
<> 139:856d2700e60b 1177 #define _USART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
<> 139:856d2700e60b 1178 #define _USART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */
<> 139:856d2700e60b 1179 #define _USART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */
<> 139:856d2700e60b 1180 #define _USART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */
<> 139:856d2700e60b 1181 #define _USART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */
<> 139:856d2700e60b 1182 #define _USART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */
<> 139:856d2700e60b 1183 #define _USART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */
<> 139:856d2700e60b 1184 #define _USART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */
<> 139:856d2700e60b 1185 #define _USART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */
<> 139:856d2700e60b 1186 #define _USART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */
<> 139:856d2700e60b 1187 #define _USART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */
<> 139:856d2700e60b 1188 #define _USART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */
<> 139:856d2700e60b 1189 #define _USART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */
<> 139:856d2700e60b 1190 #define USART_INPUT_RXPRSSEL_DEFAULT (_USART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_INPUT */
<> 139:856d2700e60b 1191 #define USART_INPUT_RXPRSSEL_PRSCH0 (_USART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_INPUT */
<> 139:856d2700e60b 1192 #define USART_INPUT_RXPRSSEL_PRSCH1 (_USART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_INPUT */
<> 139:856d2700e60b 1193 #define USART_INPUT_RXPRSSEL_PRSCH2 (_USART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_INPUT */
<> 139:856d2700e60b 1194 #define USART_INPUT_RXPRSSEL_PRSCH3 (_USART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_INPUT */
<> 139:856d2700e60b 1195 #define USART_INPUT_RXPRSSEL_PRSCH4 (_USART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_INPUT */
<> 139:856d2700e60b 1196 #define USART_INPUT_RXPRSSEL_PRSCH5 (_USART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_INPUT */
<> 139:856d2700e60b 1197 #define USART_INPUT_RXPRSSEL_PRSCH6 (_USART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for USART_INPUT */
<> 139:856d2700e60b 1198 #define USART_INPUT_RXPRSSEL_PRSCH7 (_USART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for USART_INPUT */
<> 139:856d2700e60b 1199 #define USART_INPUT_RXPRSSEL_PRSCH8 (_USART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for USART_INPUT */
<> 139:856d2700e60b 1200 #define USART_INPUT_RXPRSSEL_PRSCH9 (_USART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for USART_INPUT */
<> 139:856d2700e60b 1201 #define USART_INPUT_RXPRSSEL_PRSCH10 (_USART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for USART_INPUT */
<> 139:856d2700e60b 1202 #define USART_INPUT_RXPRSSEL_PRSCH11 (_USART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for USART_INPUT */
<> 139:856d2700e60b 1203 #define USART_INPUT_RXPRS (0x1UL << 7) /**< PRS RX Enable */
<> 139:856d2700e60b 1204 #define _USART_INPUT_RXPRS_SHIFT 7 /**< Shift value for USART_RXPRS */
<> 139:856d2700e60b 1205 #define _USART_INPUT_RXPRS_MASK 0x80UL /**< Bit mask for USART_RXPRS */
<> 139:856d2700e60b 1206 #define _USART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
<> 139:856d2700e60b 1207 #define USART_INPUT_RXPRS_DEFAULT (_USART_INPUT_RXPRS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_INPUT */
<> 139:856d2700e60b 1208 #define _USART_INPUT_CLKPRSSEL_SHIFT 8 /**< Shift value for USART_CLKPRSSEL */
<> 139:856d2700e60b 1209 #define _USART_INPUT_CLKPRSSEL_MASK 0xF00UL /**< Bit mask for USART_CLKPRSSEL */
<> 139:856d2700e60b 1210 #define _USART_INPUT_CLKPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
<> 139:856d2700e60b 1211 #define _USART_INPUT_CLKPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */
<> 139:856d2700e60b 1212 #define _USART_INPUT_CLKPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */
<> 139:856d2700e60b 1213 #define _USART_INPUT_CLKPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */
<> 139:856d2700e60b 1214 #define _USART_INPUT_CLKPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */
<> 139:856d2700e60b 1215 #define _USART_INPUT_CLKPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */
<> 139:856d2700e60b 1216 #define _USART_INPUT_CLKPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */
<> 139:856d2700e60b 1217 #define _USART_INPUT_CLKPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */
<> 139:856d2700e60b 1218 #define _USART_INPUT_CLKPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */
<> 139:856d2700e60b 1219 #define _USART_INPUT_CLKPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */
<> 139:856d2700e60b 1220 #define _USART_INPUT_CLKPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */
<> 139:856d2700e60b 1221 #define _USART_INPUT_CLKPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */
<> 139:856d2700e60b 1222 #define _USART_INPUT_CLKPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */
<> 139:856d2700e60b 1223 #define USART_INPUT_CLKPRSSEL_DEFAULT (_USART_INPUT_CLKPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_INPUT */
<> 139:856d2700e60b 1224 #define USART_INPUT_CLKPRSSEL_PRSCH0 (_USART_INPUT_CLKPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_INPUT */
<> 139:856d2700e60b 1225 #define USART_INPUT_CLKPRSSEL_PRSCH1 (_USART_INPUT_CLKPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_INPUT */
<> 139:856d2700e60b 1226 #define USART_INPUT_CLKPRSSEL_PRSCH2 (_USART_INPUT_CLKPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_INPUT */
<> 139:856d2700e60b 1227 #define USART_INPUT_CLKPRSSEL_PRSCH3 (_USART_INPUT_CLKPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_INPUT */
<> 139:856d2700e60b 1228 #define USART_INPUT_CLKPRSSEL_PRSCH4 (_USART_INPUT_CLKPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_INPUT */
<> 139:856d2700e60b 1229 #define USART_INPUT_CLKPRSSEL_PRSCH5 (_USART_INPUT_CLKPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_INPUT */
<> 139:856d2700e60b 1230 #define USART_INPUT_CLKPRSSEL_PRSCH6 (_USART_INPUT_CLKPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_INPUT */
<> 139:856d2700e60b 1231 #define USART_INPUT_CLKPRSSEL_PRSCH7 (_USART_INPUT_CLKPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_INPUT */
<> 139:856d2700e60b 1232 #define USART_INPUT_CLKPRSSEL_PRSCH8 (_USART_INPUT_CLKPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_INPUT */
<> 139:856d2700e60b 1233 #define USART_INPUT_CLKPRSSEL_PRSCH9 (_USART_INPUT_CLKPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_INPUT */
<> 139:856d2700e60b 1234 #define USART_INPUT_CLKPRSSEL_PRSCH10 (_USART_INPUT_CLKPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_INPUT */
<> 139:856d2700e60b 1235 #define USART_INPUT_CLKPRSSEL_PRSCH11 (_USART_INPUT_CLKPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_INPUT */
<> 139:856d2700e60b 1236 #define USART_INPUT_CLKPRS (0x1UL << 15) /**< PRS CLK Enable */
<> 139:856d2700e60b 1237 #define _USART_INPUT_CLKPRS_SHIFT 15 /**< Shift value for USART_CLKPRS */
<> 139:856d2700e60b 1238 #define _USART_INPUT_CLKPRS_MASK 0x8000UL /**< Bit mask for USART_CLKPRS */
<> 139:856d2700e60b 1239 #define _USART_INPUT_CLKPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
<> 139:856d2700e60b 1240 #define USART_INPUT_CLKPRS_DEFAULT (_USART_INPUT_CLKPRS_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_INPUT */
<> 139:856d2700e60b 1241
<> 139:856d2700e60b 1242 /* Bit fields for USART I2SCTRL */
<> 139:856d2700e60b 1243 #define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */
<> 139:856d2700e60b 1244 #define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */
<> 139:856d2700e60b 1245 #define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */
<> 139:856d2700e60b 1246 #define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */
<> 139:856d2700e60b 1247 #define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */
<> 139:856d2700e60b 1248 #define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
<> 139:856d2700e60b 1249 #define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */
<> 139:856d2700e60b 1250 #define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */
<> 139:856d2700e60b 1251 #define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */
<> 139:856d2700e60b 1252 #define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */
<> 139:856d2700e60b 1253 #define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
<> 139:856d2700e60b 1254 #define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */
<> 139:856d2700e60b 1255 #define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */
<> 139:856d2700e60b 1256 #define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */
<> 139:856d2700e60b 1257 #define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */
<> 139:856d2700e60b 1258 #define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
<> 139:856d2700e60b 1259 #define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */
<> 139:856d2700e60b 1260 #define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */
<> 139:856d2700e60b 1261 #define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */
<> 139:856d2700e60b 1262 #define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */
<> 139:856d2700e60b 1263 #define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */
<> 139:856d2700e60b 1264 #define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */
<> 139:856d2700e60b 1265 #define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */
<> 139:856d2700e60b 1266 #define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */
<> 139:856d2700e60b 1267 #define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
<> 139:856d2700e60b 1268 #define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */
<> 139:856d2700e60b 1269 #define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */
<> 139:856d2700e60b 1270 #define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */
<> 139:856d2700e60b 1271 #define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */
<> 139:856d2700e60b 1272 #define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
<> 139:856d2700e60b 1273 #define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */
<> 139:856d2700e60b 1274 #define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */
<> 139:856d2700e60b 1275 #define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */
<> 139:856d2700e60b 1276 #define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
<> 139:856d2700e60b 1277 #define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */
<> 139:856d2700e60b 1278 #define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */
<> 139:856d2700e60b 1279 #define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */
<> 139:856d2700e60b 1280 #define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */
<> 139:856d2700e60b 1281 #define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */
<> 139:856d2700e60b 1282 #define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */
<> 139:856d2700e60b 1283 #define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */
<> 139:856d2700e60b 1284 #define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */
<> 139:856d2700e60b 1285 #define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */
<> 139:856d2700e60b 1286 #define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */
<> 139:856d2700e60b 1287 #define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */
<> 139:856d2700e60b 1288 #define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */
<> 139:856d2700e60b 1289 #define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */
<> 139:856d2700e60b 1290 #define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */
<> 139:856d2700e60b 1291 #define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */
<> 139:856d2700e60b 1292 #define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */
<> 139:856d2700e60b 1293 #define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */
<> 139:856d2700e60b 1294
<> 139:856d2700e60b 1295 /* Bit fields for USART TIMING */
<> 139:856d2700e60b 1296 #define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */
<> 139:856d2700e60b 1297 #define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */
<> 139:856d2700e60b 1298 #define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */
<> 139:856d2700e60b 1299 #define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */
<> 139:856d2700e60b 1300 #define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
<> 139:856d2700e60b 1301 #define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */
<> 139:856d2700e60b 1302 #define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
<> 139:856d2700e60b 1303 #define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
<> 139:856d2700e60b 1304 #define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
<> 139:856d2700e60b 1305 #define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
<> 139:856d2700e60b 1306 #define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
<> 139:856d2700e60b 1307 #define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
<> 139:856d2700e60b 1308 #define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
<> 139:856d2700e60b 1309 #define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */
<> 139:856d2700e60b 1310 #define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */
<> 139:856d2700e60b 1311 #define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */
<> 139:856d2700e60b 1312 #define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */
<> 139:856d2700e60b 1313 #define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */
<> 139:856d2700e60b 1314 #define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */
<> 139:856d2700e60b 1315 #define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */
<> 139:856d2700e60b 1316 #define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */
<> 139:856d2700e60b 1317 #define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */
<> 139:856d2700e60b 1318 #define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */
<> 139:856d2700e60b 1319 #define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */
<> 139:856d2700e60b 1320 #define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
<> 139:856d2700e60b 1321 #define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */
<> 139:856d2700e60b 1322 #define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
<> 139:856d2700e60b 1323 #define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
<> 139:856d2700e60b 1324 #define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
<> 139:856d2700e60b 1325 #define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
<> 139:856d2700e60b 1326 #define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
<> 139:856d2700e60b 1327 #define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
<> 139:856d2700e60b 1328 #define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
<> 139:856d2700e60b 1329 #define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */
<> 139:856d2700e60b 1330 #define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */
<> 139:856d2700e60b 1331 #define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */
<> 139:856d2700e60b 1332 #define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */
<> 139:856d2700e60b 1333 #define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */
<> 139:856d2700e60b 1334 #define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */
<> 139:856d2700e60b 1335 #define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */
<> 139:856d2700e60b 1336 #define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */
<> 139:856d2700e60b 1337 #define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */
<> 139:856d2700e60b 1338 #define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */
<> 139:856d2700e60b 1339 #define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */
<> 139:856d2700e60b 1340 #define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
<> 139:856d2700e60b 1341 #define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */
<> 139:856d2700e60b 1342 #define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
<> 139:856d2700e60b 1343 #define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
<> 139:856d2700e60b 1344 #define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
<> 139:856d2700e60b 1345 #define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
<> 139:856d2700e60b 1346 #define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
<> 139:856d2700e60b 1347 #define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
<> 139:856d2700e60b 1348 #define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
<> 139:856d2700e60b 1349 #define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */
<> 139:856d2700e60b 1350 #define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */
<> 139:856d2700e60b 1351 #define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */
<> 139:856d2700e60b 1352 #define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */
<> 139:856d2700e60b 1353 #define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */
<> 139:856d2700e60b 1354 #define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */
<> 139:856d2700e60b 1355 #define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */
<> 139:856d2700e60b 1356 #define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */
<> 139:856d2700e60b 1357 #define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */
<> 139:856d2700e60b 1358 #define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */
<> 139:856d2700e60b 1359 #define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */
<> 139:856d2700e60b 1360 #define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
<> 139:856d2700e60b 1361 #define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */
<> 139:856d2700e60b 1362 #define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
<> 139:856d2700e60b 1363 #define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
<> 139:856d2700e60b 1364 #define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
<> 139:856d2700e60b 1365 #define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
<> 139:856d2700e60b 1366 #define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
<> 139:856d2700e60b 1367 #define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
<> 139:856d2700e60b 1368 #define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
<> 139:856d2700e60b 1369 #define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */
<> 139:856d2700e60b 1370 #define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */
<> 139:856d2700e60b 1371 #define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */
<> 139:856d2700e60b 1372 #define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */
<> 139:856d2700e60b 1373 #define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */
<> 139:856d2700e60b 1374 #define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */
<> 139:856d2700e60b 1375 #define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */
<> 139:856d2700e60b 1376 #define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */
<> 139:856d2700e60b 1377 #define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */
<> 139:856d2700e60b 1378
<> 139:856d2700e60b 1379 /* Bit fields for USART CTRLX */
<> 139:856d2700e60b 1380 #define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */
<> 139:856d2700e60b 1381 #define _USART_CTRLX_MASK 0x0000000FUL /**< Mask for USART_CTRLX */
<> 139:856d2700e60b 1382 #define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */
<> 139:856d2700e60b 1383 #define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */
<> 139:856d2700e60b 1384 #define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */
<> 139:856d2700e60b 1385 #define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
<> 139:856d2700e60b 1386 #define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */
<> 139:856d2700e60b 1387 #define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */
<> 139:856d2700e60b 1388 #define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */
<> 139:856d2700e60b 1389 #define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */
<> 139:856d2700e60b 1390 #define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
<> 139:856d2700e60b 1391 #define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */
<> 139:856d2700e60b 1392 #define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */
<> 139:856d2700e60b 1393 #define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */
<> 139:856d2700e60b 1394 #define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */
<> 139:856d2700e60b 1395 #define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
<> 139:856d2700e60b 1396 #define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */
<> 139:856d2700e60b 1397 #define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */
<> 139:856d2700e60b 1398 #define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */
<> 139:856d2700e60b 1399 #define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */
<> 139:856d2700e60b 1400 #define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
<> 139:856d2700e60b 1401 #define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */
<> 139:856d2700e60b 1402
<> 139:856d2700e60b 1403 /* Bit fields for USART TIMECMP0 */
<> 139:856d2700e60b 1404 #define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */
<> 139:856d2700e60b 1405 #define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */
<> 139:856d2700e60b 1406 #define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */
<> 139:856d2700e60b 1407 #define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */
<> 139:856d2700e60b 1408 #define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
<> 139:856d2700e60b 1409 #define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
<> 139:856d2700e60b 1410 #define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */
<> 139:856d2700e60b 1411 #define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */
<> 139:856d2700e60b 1412 #define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
<> 139:856d2700e60b 1413 #define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */
<> 139:856d2700e60b 1414 #define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */
<> 139:856d2700e60b 1415 #define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */
<> 139:856d2700e60b 1416 #define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */
<> 139:856d2700e60b 1417 #define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */
<> 139:856d2700e60b 1418 #define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
<> 139:856d2700e60b 1419 #define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */
<> 139:856d2700e60b 1420 #define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */
<> 139:856d2700e60b 1421 #define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */
<> 139:856d2700e60b 1422 #define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */
<> 139:856d2700e60b 1423 #define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */
<> 139:856d2700e60b 1424 #define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */
<> 139:856d2700e60b 1425 #define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */
<> 139:856d2700e60b 1426 #define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
<> 139:856d2700e60b 1427 #define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */
<> 139:856d2700e60b 1428 #define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */
<> 139:856d2700e60b 1429 #define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */
<> 139:856d2700e60b 1430 #define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */
<> 139:856d2700e60b 1431 #define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
<> 139:856d2700e60b 1432 #define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */
<> 139:856d2700e60b 1433 #define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */
<> 139:856d2700e60b 1434 #define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */
<> 139:856d2700e60b 1435 #define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */
<> 139:856d2700e60b 1436 #define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */
<> 139:856d2700e60b 1437 #define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */
<> 139:856d2700e60b 1438 #define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */
<> 139:856d2700e60b 1439 #define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
<> 139:856d2700e60b 1440 #define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
<> 139:856d2700e60b 1441
<> 139:856d2700e60b 1442 /* Bit fields for USART TIMECMP1 */
<> 139:856d2700e60b 1443 #define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */
<> 139:856d2700e60b 1444 #define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */
<> 139:856d2700e60b 1445 #define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */
<> 139:856d2700e60b 1446 #define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */
<> 139:856d2700e60b 1447 #define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
<> 139:856d2700e60b 1448 #define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
<> 139:856d2700e60b 1449 #define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */
<> 139:856d2700e60b 1450 #define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */
<> 139:856d2700e60b 1451 #define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
<> 139:856d2700e60b 1452 #define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */
<> 139:856d2700e60b 1453 #define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */
<> 139:856d2700e60b 1454 #define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */
<> 139:856d2700e60b 1455 #define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */
<> 139:856d2700e60b 1456 #define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */
<> 139:856d2700e60b 1457 #define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
<> 139:856d2700e60b 1458 #define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */
<> 139:856d2700e60b 1459 #define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */
<> 139:856d2700e60b 1460 #define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */
<> 139:856d2700e60b 1461 #define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */
<> 139:856d2700e60b 1462 #define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */
<> 139:856d2700e60b 1463 #define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */
<> 139:856d2700e60b 1464 #define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */
<> 139:856d2700e60b 1465 #define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
<> 139:856d2700e60b 1466 #define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */
<> 139:856d2700e60b 1467 #define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */
<> 139:856d2700e60b 1468 #define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */
<> 139:856d2700e60b 1469 #define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */
<> 139:856d2700e60b 1470 #define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
<> 139:856d2700e60b 1471 #define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */
<> 139:856d2700e60b 1472 #define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */
<> 139:856d2700e60b 1473 #define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */
<> 139:856d2700e60b 1474 #define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */
<> 139:856d2700e60b 1475 #define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */
<> 139:856d2700e60b 1476 #define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */
<> 139:856d2700e60b 1477 #define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */
<> 139:856d2700e60b 1478 #define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
<> 139:856d2700e60b 1479 #define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
<> 139:856d2700e60b 1480
<> 139:856d2700e60b 1481 /* Bit fields for USART TIMECMP2 */
<> 139:856d2700e60b 1482 #define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */
<> 139:856d2700e60b 1483 #define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */
<> 139:856d2700e60b 1484 #define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */
<> 139:856d2700e60b 1485 #define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */
<> 139:856d2700e60b 1486 #define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
<> 139:856d2700e60b 1487 #define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
<> 139:856d2700e60b 1488 #define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */
<> 139:856d2700e60b 1489 #define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */
<> 139:856d2700e60b 1490 #define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
<> 139:856d2700e60b 1491 #define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */
<> 139:856d2700e60b 1492 #define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */
<> 139:856d2700e60b 1493 #define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */
<> 139:856d2700e60b 1494 #define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */
<> 139:856d2700e60b 1495 #define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */
<> 139:856d2700e60b 1496 #define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
<> 139:856d2700e60b 1497 #define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */
<> 139:856d2700e60b 1498 #define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */
<> 139:856d2700e60b 1499 #define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */
<> 139:856d2700e60b 1500 #define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */
<> 139:856d2700e60b 1501 #define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */
<> 139:856d2700e60b 1502 #define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */
<> 139:856d2700e60b 1503 #define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */
<> 139:856d2700e60b 1504 #define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
<> 139:856d2700e60b 1505 #define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */
<> 139:856d2700e60b 1506 #define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */
<> 139:856d2700e60b 1507 #define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */
<> 139:856d2700e60b 1508 #define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */
<> 139:856d2700e60b 1509 #define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
<> 139:856d2700e60b 1510 #define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */
<> 139:856d2700e60b 1511 #define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */
<> 139:856d2700e60b 1512 #define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */
<> 139:856d2700e60b 1513 #define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */
<> 139:856d2700e60b 1514 #define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */
<> 139:856d2700e60b 1515 #define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */
<> 139:856d2700e60b 1516 #define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */
<> 139:856d2700e60b 1517 #define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
<> 139:856d2700e60b 1518 #define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
<> 139:856d2700e60b 1519
<> 139:856d2700e60b 1520 /* Bit fields for USART ROUTEPEN */
<> 139:856d2700e60b 1521 #define _USART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTEPEN */
<> 139:856d2700e60b 1522 #define _USART_ROUTEPEN_MASK 0x0000003FUL /**< Mask for USART_ROUTEPEN */
<> 139:856d2700e60b 1523 #define USART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */
<> 139:856d2700e60b 1524 #define _USART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */
<> 139:856d2700e60b 1525 #define _USART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */
<> 139:856d2700e60b 1526 #define _USART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
<> 139:856d2700e60b 1527 #define USART_ROUTEPEN_RXPEN_DEFAULT (_USART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
<> 139:856d2700e60b 1528 #define USART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */
<> 139:856d2700e60b 1529 #define _USART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */
<> 139:856d2700e60b 1530 #define _USART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */
<> 139:856d2700e60b 1531 #define _USART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
<> 139:856d2700e60b 1532 #define USART_ROUTEPEN_TXPEN_DEFAULT (_USART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
<> 139:856d2700e60b 1533 #define USART_ROUTEPEN_CSPEN (0x1UL << 2) /**< CS Pin Enable */
<> 139:856d2700e60b 1534 #define _USART_ROUTEPEN_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */
<> 139:856d2700e60b 1535 #define _USART_ROUTEPEN_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */
<> 139:856d2700e60b 1536 #define _USART_ROUTEPEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
<> 139:856d2700e60b 1537 #define USART_ROUTEPEN_CSPEN_DEFAULT (_USART_ROUTEPEN_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
<> 139:856d2700e60b 1538 #define USART_ROUTEPEN_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */
<> 139:856d2700e60b 1539 #define _USART_ROUTEPEN_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */
<> 139:856d2700e60b 1540 #define _USART_ROUTEPEN_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */
<> 139:856d2700e60b 1541 #define _USART_ROUTEPEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
<> 139:856d2700e60b 1542 #define USART_ROUTEPEN_CLKPEN_DEFAULT (_USART_ROUTEPEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
<> 139:856d2700e60b 1543 #define USART_ROUTEPEN_CTSPEN (0x1UL << 4) /**< CTS Pin Enable */
<> 139:856d2700e60b 1544 #define _USART_ROUTEPEN_CTSPEN_SHIFT 4 /**< Shift value for USART_CTSPEN */
<> 139:856d2700e60b 1545 #define _USART_ROUTEPEN_CTSPEN_MASK 0x10UL /**< Bit mask for USART_CTSPEN */
<> 139:856d2700e60b 1546 #define _USART_ROUTEPEN_CTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
<> 139:856d2700e60b 1547 #define USART_ROUTEPEN_CTSPEN_DEFAULT (_USART_ROUTEPEN_CTSPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
<> 139:856d2700e60b 1548 #define USART_ROUTEPEN_RTSPEN (0x1UL << 5) /**< RTS Pin Enable */
<> 139:856d2700e60b 1549 #define _USART_ROUTEPEN_RTSPEN_SHIFT 5 /**< Shift value for USART_RTSPEN */
<> 139:856d2700e60b 1550 #define _USART_ROUTEPEN_RTSPEN_MASK 0x20UL /**< Bit mask for USART_RTSPEN */
<> 139:856d2700e60b 1551 #define _USART_ROUTEPEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
<> 139:856d2700e60b 1552 #define USART_ROUTEPEN_RTSPEN_DEFAULT (_USART_ROUTEPEN_RTSPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
<> 139:856d2700e60b 1553
<> 139:856d2700e60b 1554 /* Bit fields for USART ROUTELOC0 */
<> 139:856d2700e60b 1555 #define _USART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC0 */
<> 139:856d2700e60b 1556 #define _USART_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for USART_ROUTELOC0 */
<> 139:856d2700e60b 1557 #define _USART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for USART_RXLOC */
<> 139:856d2700e60b 1558 #define _USART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for USART_RXLOC */
<> 139:856d2700e60b 1559 #define _USART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1560 #define _USART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */
<> 139:856d2700e60b 1561 #define _USART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1562 #define _USART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1563 #define _USART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1564 #define _USART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1565 #define _USART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1566 #define _USART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1567 #define _USART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1568 #define _USART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1569 #define _USART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1570 #define _USART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1571 #define _USART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1572 #define _USART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1573 #define _USART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1574 #define _USART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1575 #define _USART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1576 #define _USART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1577 #define _USART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1578 #define _USART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1579 #define _USART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1580 #define _USART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1581 #define _USART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1582 #define _USART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1583 #define _USART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1584 #define _USART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1585 #define _USART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1586 #define _USART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1587 #define _USART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1588 #define _USART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1589 #define _USART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1590 #define _USART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1591 #define _USART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1592 #define USART_ROUTELOC0_RXLOC_LOC0 (_USART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1593 #define USART_ROUTELOC0_RXLOC_DEFAULT (_USART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
<> 139:856d2700e60b 1594 #define USART_ROUTELOC0_RXLOC_LOC1 (_USART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1595 #define USART_ROUTELOC0_RXLOC_LOC2 (_USART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1596 #define USART_ROUTELOC0_RXLOC_LOC3 (_USART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1597 #define USART_ROUTELOC0_RXLOC_LOC4 (_USART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1598 #define USART_ROUTELOC0_RXLOC_LOC5 (_USART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1599 #define USART_ROUTELOC0_RXLOC_LOC6 (_USART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1600 #define USART_ROUTELOC0_RXLOC_LOC7 (_USART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1601 #define USART_ROUTELOC0_RXLOC_LOC8 (_USART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1602 #define USART_ROUTELOC0_RXLOC_LOC9 (_USART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1603 #define USART_ROUTELOC0_RXLOC_LOC10 (_USART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1604 #define USART_ROUTELOC0_RXLOC_LOC11 (_USART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1605 #define USART_ROUTELOC0_RXLOC_LOC12 (_USART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1606 #define USART_ROUTELOC0_RXLOC_LOC13 (_USART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1607 #define USART_ROUTELOC0_RXLOC_LOC14 (_USART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1608 #define USART_ROUTELOC0_RXLOC_LOC15 (_USART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1609 #define USART_ROUTELOC0_RXLOC_LOC16 (_USART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1610 #define USART_ROUTELOC0_RXLOC_LOC17 (_USART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1611 #define USART_ROUTELOC0_RXLOC_LOC18 (_USART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1612 #define USART_ROUTELOC0_RXLOC_LOC19 (_USART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1613 #define USART_ROUTELOC0_RXLOC_LOC20 (_USART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1614 #define USART_ROUTELOC0_RXLOC_LOC21 (_USART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1615 #define USART_ROUTELOC0_RXLOC_LOC22 (_USART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1616 #define USART_ROUTELOC0_RXLOC_LOC23 (_USART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1617 #define USART_ROUTELOC0_RXLOC_LOC24 (_USART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1618 #define USART_ROUTELOC0_RXLOC_LOC25 (_USART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1619 #define USART_ROUTELOC0_RXLOC_LOC26 (_USART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1620 #define USART_ROUTELOC0_RXLOC_LOC27 (_USART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1621 #define USART_ROUTELOC0_RXLOC_LOC28 (_USART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1622 #define USART_ROUTELOC0_RXLOC_LOC29 (_USART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1623 #define USART_ROUTELOC0_RXLOC_LOC30 (_USART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1624 #define USART_ROUTELOC0_RXLOC_LOC31 (_USART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1625 #define _USART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for USART_TXLOC */
<> 139:856d2700e60b 1626 #define _USART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for USART_TXLOC */
<> 139:856d2700e60b 1627 #define _USART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1628 #define _USART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */
<> 139:856d2700e60b 1629 #define _USART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1630 #define _USART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1631 #define _USART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1632 #define _USART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1633 #define _USART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1634 #define _USART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1635 #define _USART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1636 #define _USART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1637 #define _USART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1638 #define _USART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1639 #define _USART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1640 #define _USART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1641 #define _USART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1642 #define _USART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1643 #define _USART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1644 #define _USART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1645 #define _USART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1646 #define _USART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1647 #define _USART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1648 #define _USART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1649 #define _USART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1650 #define _USART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1651 #define _USART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1652 #define _USART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1653 #define _USART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1654 #define _USART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1655 #define _USART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1656 #define _USART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1657 #define _USART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1658 #define _USART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1659 #define _USART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1660 #define USART_ROUTELOC0_TXLOC_LOC0 (_USART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1661 #define USART_ROUTELOC0_TXLOC_DEFAULT (_USART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
<> 139:856d2700e60b 1662 #define USART_ROUTELOC0_TXLOC_LOC1 (_USART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1663 #define USART_ROUTELOC0_TXLOC_LOC2 (_USART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1664 #define USART_ROUTELOC0_TXLOC_LOC3 (_USART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1665 #define USART_ROUTELOC0_TXLOC_LOC4 (_USART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1666 #define USART_ROUTELOC0_TXLOC_LOC5 (_USART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1667 #define USART_ROUTELOC0_TXLOC_LOC6 (_USART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1668 #define USART_ROUTELOC0_TXLOC_LOC7 (_USART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1669 #define USART_ROUTELOC0_TXLOC_LOC8 (_USART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1670 #define USART_ROUTELOC0_TXLOC_LOC9 (_USART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1671 #define USART_ROUTELOC0_TXLOC_LOC10 (_USART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1672 #define USART_ROUTELOC0_TXLOC_LOC11 (_USART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1673 #define USART_ROUTELOC0_TXLOC_LOC12 (_USART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1674 #define USART_ROUTELOC0_TXLOC_LOC13 (_USART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1675 #define USART_ROUTELOC0_TXLOC_LOC14 (_USART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1676 #define USART_ROUTELOC0_TXLOC_LOC15 (_USART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1677 #define USART_ROUTELOC0_TXLOC_LOC16 (_USART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1678 #define USART_ROUTELOC0_TXLOC_LOC17 (_USART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1679 #define USART_ROUTELOC0_TXLOC_LOC18 (_USART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1680 #define USART_ROUTELOC0_TXLOC_LOC19 (_USART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1681 #define USART_ROUTELOC0_TXLOC_LOC20 (_USART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1682 #define USART_ROUTELOC0_TXLOC_LOC21 (_USART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1683 #define USART_ROUTELOC0_TXLOC_LOC22 (_USART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1684 #define USART_ROUTELOC0_TXLOC_LOC23 (_USART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1685 #define USART_ROUTELOC0_TXLOC_LOC24 (_USART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1686 #define USART_ROUTELOC0_TXLOC_LOC25 (_USART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1687 #define USART_ROUTELOC0_TXLOC_LOC26 (_USART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1688 #define USART_ROUTELOC0_TXLOC_LOC27 (_USART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1689 #define USART_ROUTELOC0_TXLOC_LOC28 (_USART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1690 #define USART_ROUTELOC0_TXLOC_LOC29 (_USART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1691 #define USART_ROUTELOC0_TXLOC_LOC30 (_USART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1692 #define USART_ROUTELOC0_TXLOC_LOC31 (_USART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1693 #define _USART_ROUTELOC0_CSLOC_SHIFT 16 /**< Shift value for USART_CSLOC */
<> 139:856d2700e60b 1694 #define _USART_ROUTELOC0_CSLOC_MASK 0x1F0000UL /**< Bit mask for USART_CSLOC */
<> 139:856d2700e60b 1695 #define _USART_ROUTELOC0_CSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1696 #define _USART_ROUTELOC0_CSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */
<> 139:856d2700e60b 1697 #define _USART_ROUTELOC0_CSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1698 #define _USART_ROUTELOC0_CSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1699 #define _USART_ROUTELOC0_CSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1700 #define _USART_ROUTELOC0_CSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1701 #define _USART_ROUTELOC0_CSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1702 #define _USART_ROUTELOC0_CSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1703 #define _USART_ROUTELOC0_CSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1704 #define _USART_ROUTELOC0_CSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1705 #define _USART_ROUTELOC0_CSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1706 #define _USART_ROUTELOC0_CSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1707 #define _USART_ROUTELOC0_CSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1708 #define _USART_ROUTELOC0_CSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1709 #define _USART_ROUTELOC0_CSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1710 #define _USART_ROUTELOC0_CSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1711 #define _USART_ROUTELOC0_CSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1712 #define _USART_ROUTELOC0_CSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1713 #define _USART_ROUTELOC0_CSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1714 #define _USART_ROUTELOC0_CSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1715 #define _USART_ROUTELOC0_CSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1716 #define _USART_ROUTELOC0_CSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1717 #define _USART_ROUTELOC0_CSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1718 #define _USART_ROUTELOC0_CSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1719 #define _USART_ROUTELOC0_CSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1720 #define _USART_ROUTELOC0_CSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1721 #define _USART_ROUTELOC0_CSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1722 #define _USART_ROUTELOC0_CSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1723 #define _USART_ROUTELOC0_CSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1724 #define _USART_ROUTELOC0_CSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1725 #define _USART_ROUTELOC0_CSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1726 #define _USART_ROUTELOC0_CSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1727 #define _USART_ROUTELOC0_CSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1728 #define USART_ROUTELOC0_CSLOC_LOC0 (_USART_ROUTELOC0_CSLOC_LOC0 << 16) /**< Shifted mode LOC0 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1729 #define USART_ROUTELOC0_CSLOC_DEFAULT (_USART_ROUTELOC0_CSLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
<> 139:856d2700e60b 1730 #define USART_ROUTELOC0_CSLOC_LOC1 (_USART_ROUTELOC0_CSLOC_LOC1 << 16) /**< Shifted mode LOC1 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1731 #define USART_ROUTELOC0_CSLOC_LOC2 (_USART_ROUTELOC0_CSLOC_LOC2 << 16) /**< Shifted mode LOC2 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1732 #define USART_ROUTELOC0_CSLOC_LOC3 (_USART_ROUTELOC0_CSLOC_LOC3 << 16) /**< Shifted mode LOC3 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1733 #define USART_ROUTELOC0_CSLOC_LOC4 (_USART_ROUTELOC0_CSLOC_LOC4 << 16) /**< Shifted mode LOC4 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1734 #define USART_ROUTELOC0_CSLOC_LOC5 (_USART_ROUTELOC0_CSLOC_LOC5 << 16) /**< Shifted mode LOC5 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1735 #define USART_ROUTELOC0_CSLOC_LOC6 (_USART_ROUTELOC0_CSLOC_LOC6 << 16) /**< Shifted mode LOC6 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1736 #define USART_ROUTELOC0_CSLOC_LOC7 (_USART_ROUTELOC0_CSLOC_LOC7 << 16) /**< Shifted mode LOC7 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1737 #define USART_ROUTELOC0_CSLOC_LOC8 (_USART_ROUTELOC0_CSLOC_LOC8 << 16) /**< Shifted mode LOC8 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1738 #define USART_ROUTELOC0_CSLOC_LOC9 (_USART_ROUTELOC0_CSLOC_LOC9 << 16) /**< Shifted mode LOC9 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1739 #define USART_ROUTELOC0_CSLOC_LOC10 (_USART_ROUTELOC0_CSLOC_LOC10 << 16) /**< Shifted mode LOC10 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1740 #define USART_ROUTELOC0_CSLOC_LOC11 (_USART_ROUTELOC0_CSLOC_LOC11 << 16) /**< Shifted mode LOC11 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1741 #define USART_ROUTELOC0_CSLOC_LOC12 (_USART_ROUTELOC0_CSLOC_LOC12 << 16) /**< Shifted mode LOC12 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1742 #define USART_ROUTELOC0_CSLOC_LOC13 (_USART_ROUTELOC0_CSLOC_LOC13 << 16) /**< Shifted mode LOC13 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1743 #define USART_ROUTELOC0_CSLOC_LOC14 (_USART_ROUTELOC0_CSLOC_LOC14 << 16) /**< Shifted mode LOC14 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1744 #define USART_ROUTELOC0_CSLOC_LOC15 (_USART_ROUTELOC0_CSLOC_LOC15 << 16) /**< Shifted mode LOC15 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1745 #define USART_ROUTELOC0_CSLOC_LOC16 (_USART_ROUTELOC0_CSLOC_LOC16 << 16) /**< Shifted mode LOC16 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1746 #define USART_ROUTELOC0_CSLOC_LOC17 (_USART_ROUTELOC0_CSLOC_LOC17 << 16) /**< Shifted mode LOC17 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1747 #define USART_ROUTELOC0_CSLOC_LOC18 (_USART_ROUTELOC0_CSLOC_LOC18 << 16) /**< Shifted mode LOC18 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1748 #define USART_ROUTELOC0_CSLOC_LOC19 (_USART_ROUTELOC0_CSLOC_LOC19 << 16) /**< Shifted mode LOC19 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1749 #define USART_ROUTELOC0_CSLOC_LOC20 (_USART_ROUTELOC0_CSLOC_LOC20 << 16) /**< Shifted mode LOC20 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1750 #define USART_ROUTELOC0_CSLOC_LOC21 (_USART_ROUTELOC0_CSLOC_LOC21 << 16) /**< Shifted mode LOC21 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1751 #define USART_ROUTELOC0_CSLOC_LOC22 (_USART_ROUTELOC0_CSLOC_LOC22 << 16) /**< Shifted mode LOC22 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1752 #define USART_ROUTELOC0_CSLOC_LOC23 (_USART_ROUTELOC0_CSLOC_LOC23 << 16) /**< Shifted mode LOC23 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1753 #define USART_ROUTELOC0_CSLOC_LOC24 (_USART_ROUTELOC0_CSLOC_LOC24 << 16) /**< Shifted mode LOC24 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1754 #define USART_ROUTELOC0_CSLOC_LOC25 (_USART_ROUTELOC0_CSLOC_LOC25 << 16) /**< Shifted mode LOC25 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1755 #define USART_ROUTELOC0_CSLOC_LOC26 (_USART_ROUTELOC0_CSLOC_LOC26 << 16) /**< Shifted mode LOC26 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1756 #define USART_ROUTELOC0_CSLOC_LOC27 (_USART_ROUTELOC0_CSLOC_LOC27 << 16) /**< Shifted mode LOC27 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1757 #define USART_ROUTELOC0_CSLOC_LOC28 (_USART_ROUTELOC0_CSLOC_LOC28 << 16) /**< Shifted mode LOC28 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1758 #define USART_ROUTELOC0_CSLOC_LOC29 (_USART_ROUTELOC0_CSLOC_LOC29 << 16) /**< Shifted mode LOC29 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1759 #define USART_ROUTELOC0_CSLOC_LOC30 (_USART_ROUTELOC0_CSLOC_LOC30 << 16) /**< Shifted mode LOC30 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1760 #define USART_ROUTELOC0_CSLOC_LOC31 (_USART_ROUTELOC0_CSLOC_LOC31 << 16) /**< Shifted mode LOC31 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1761 #define _USART_ROUTELOC0_CLKLOC_SHIFT 24 /**< Shift value for USART_CLKLOC */
<> 139:856d2700e60b 1762 #define _USART_ROUTELOC0_CLKLOC_MASK 0x1F000000UL /**< Bit mask for USART_CLKLOC */
<> 139:856d2700e60b 1763 #define _USART_ROUTELOC0_CLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1764 #define _USART_ROUTELOC0_CLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */
<> 139:856d2700e60b 1765 #define _USART_ROUTELOC0_CLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1766 #define _USART_ROUTELOC0_CLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1767 #define _USART_ROUTELOC0_CLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1768 #define _USART_ROUTELOC0_CLKLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1769 #define _USART_ROUTELOC0_CLKLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1770 #define _USART_ROUTELOC0_CLKLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1771 #define _USART_ROUTELOC0_CLKLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1772 #define _USART_ROUTELOC0_CLKLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1773 #define _USART_ROUTELOC0_CLKLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1774 #define _USART_ROUTELOC0_CLKLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1775 #define _USART_ROUTELOC0_CLKLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1776 #define _USART_ROUTELOC0_CLKLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1777 #define _USART_ROUTELOC0_CLKLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1778 #define _USART_ROUTELOC0_CLKLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1779 #define _USART_ROUTELOC0_CLKLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1780 #define _USART_ROUTELOC0_CLKLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1781 #define _USART_ROUTELOC0_CLKLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1782 #define _USART_ROUTELOC0_CLKLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1783 #define _USART_ROUTELOC0_CLKLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1784 #define _USART_ROUTELOC0_CLKLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1785 #define _USART_ROUTELOC0_CLKLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1786 #define _USART_ROUTELOC0_CLKLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1787 #define _USART_ROUTELOC0_CLKLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1788 #define _USART_ROUTELOC0_CLKLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1789 #define _USART_ROUTELOC0_CLKLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1790 #define _USART_ROUTELOC0_CLKLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1791 #define _USART_ROUTELOC0_CLKLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1792 #define _USART_ROUTELOC0_CLKLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1793 #define _USART_ROUTELOC0_CLKLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1794 #define _USART_ROUTELOC0_CLKLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1795 #define _USART_ROUTELOC0_CLKLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1796 #define USART_ROUTELOC0_CLKLOC_LOC0 (_USART_ROUTELOC0_CLKLOC_LOC0 << 24) /**< Shifted mode LOC0 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1797 #define USART_ROUTELOC0_CLKLOC_DEFAULT (_USART_ROUTELOC0_CLKLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
<> 139:856d2700e60b 1798 #define USART_ROUTELOC0_CLKLOC_LOC1 (_USART_ROUTELOC0_CLKLOC_LOC1 << 24) /**< Shifted mode LOC1 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1799 #define USART_ROUTELOC0_CLKLOC_LOC2 (_USART_ROUTELOC0_CLKLOC_LOC2 << 24) /**< Shifted mode LOC2 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1800 #define USART_ROUTELOC0_CLKLOC_LOC3 (_USART_ROUTELOC0_CLKLOC_LOC3 << 24) /**< Shifted mode LOC3 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1801 #define USART_ROUTELOC0_CLKLOC_LOC4 (_USART_ROUTELOC0_CLKLOC_LOC4 << 24) /**< Shifted mode LOC4 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1802 #define USART_ROUTELOC0_CLKLOC_LOC5 (_USART_ROUTELOC0_CLKLOC_LOC5 << 24) /**< Shifted mode LOC5 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1803 #define USART_ROUTELOC0_CLKLOC_LOC6 (_USART_ROUTELOC0_CLKLOC_LOC6 << 24) /**< Shifted mode LOC6 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1804 #define USART_ROUTELOC0_CLKLOC_LOC7 (_USART_ROUTELOC0_CLKLOC_LOC7 << 24) /**< Shifted mode LOC7 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1805 #define USART_ROUTELOC0_CLKLOC_LOC8 (_USART_ROUTELOC0_CLKLOC_LOC8 << 24) /**< Shifted mode LOC8 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1806 #define USART_ROUTELOC0_CLKLOC_LOC9 (_USART_ROUTELOC0_CLKLOC_LOC9 << 24) /**< Shifted mode LOC9 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1807 #define USART_ROUTELOC0_CLKLOC_LOC10 (_USART_ROUTELOC0_CLKLOC_LOC10 << 24) /**< Shifted mode LOC10 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1808 #define USART_ROUTELOC0_CLKLOC_LOC11 (_USART_ROUTELOC0_CLKLOC_LOC11 << 24) /**< Shifted mode LOC11 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1809 #define USART_ROUTELOC0_CLKLOC_LOC12 (_USART_ROUTELOC0_CLKLOC_LOC12 << 24) /**< Shifted mode LOC12 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1810 #define USART_ROUTELOC0_CLKLOC_LOC13 (_USART_ROUTELOC0_CLKLOC_LOC13 << 24) /**< Shifted mode LOC13 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1811 #define USART_ROUTELOC0_CLKLOC_LOC14 (_USART_ROUTELOC0_CLKLOC_LOC14 << 24) /**< Shifted mode LOC14 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1812 #define USART_ROUTELOC0_CLKLOC_LOC15 (_USART_ROUTELOC0_CLKLOC_LOC15 << 24) /**< Shifted mode LOC15 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1813 #define USART_ROUTELOC0_CLKLOC_LOC16 (_USART_ROUTELOC0_CLKLOC_LOC16 << 24) /**< Shifted mode LOC16 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1814 #define USART_ROUTELOC0_CLKLOC_LOC17 (_USART_ROUTELOC0_CLKLOC_LOC17 << 24) /**< Shifted mode LOC17 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1815 #define USART_ROUTELOC0_CLKLOC_LOC18 (_USART_ROUTELOC0_CLKLOC_LOC18 << 24) /**< Shifted mode LOC18 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1816 #define USART_ROUTELOC0_CLKLOC_LOC19 (_USART_ROUTELOC0_CLKLOC_LOC19 << 24) /**< Shifted mode LOC19 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1817 #define USART_ROUTELOC0_CLKLOC_LOC20 (_USART_ROUTELOC0_CLKLOC_LOC20 << 24) /**< Shifted mode LOC20 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1818 #define USART_ROUTELOC0_CLKLOC_LOC21 (_USART_ROUTELOC0_CLKLOC_LOC21 << 24) /**< Shifted mode LOC21 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1819 #define USART_ROUTELOC0_CLKLOC_LOC22 (_USART_ROUTELOC0_CLKLOC_LOC22 << 24) /**< Shifted mode LOC22 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1820 #define USART_ROUTELOC0_CLKLOC_LOC23 (_USART_ROUTELOC0_CLKLOC_LOC23 << 24) /**< Shifted mode LOC23 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1821 #define USART_ROUTELOC0_CLKLOC_LOC24 (_USART_ROUTELOC0_CLKLOC_LOC24 << 24) /**< Shifted mode LOC24 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1822 #define USART_ROUTELOC0_CLKLOC_LOC25 (_USART_ROUTELOC0_CLKLOC_LOC25 << 24) /**< Shifted mode LOC25 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1823 #define USART_ROUTELOC0_CLKLOC_LOC26 (_USART_ROUTELOC0_CLKLOC_LOC26 << 24) /**< Shifted mode LOC26 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1824 #define USART_ROUTELOC0_CLKLOC_LOC27 (_USART_ROUTELOC0_CLKLOC_LOC27 << 24) /**< Shifted mode LOC27 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1825 #define USART_ROUTELOC0_CLKLOC_LOC28 (_USART_ROUTELOC0_CLKLOC_LOC28 << 24) /**< Shifted mode LOC28 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1826 #define USART_ROUTELOC0_CLKLOC_LOC29 (_USART_ROUTELOC0_CLKLOC_LOC29 << 24) /**< Shifted mode LOC29 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1827 #define USART_ROUTELOC0_CLKLOC_LOC30 (_USART_ROUTELOC0_CLKLOC_LOC30 << 24) /**< Shifted mode LOC30 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1828 #define USART_ROUTELOC0_CLKLOC_LOC31 (_USART_ROUTELOC0_CLKLOC_LOC31 << 24) /**< Shifted mode LOC31 for USART_ROUTELOC0 */
<> 139:856d2700e60b 1829
<> 139:856d2700e60b 1830 /* Bit fields for USART ROUTELOC1 */
<> 139:856d2700e60b 1831 #define _USART_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC1 */
<> 139:856d2700e60b 1832 #define _USART_ROUTELOC1_MASK 0x00001F1FUL /**< Mask for USART_ROUTELOC1 */
<> 139:856d2700e60b 1833 #define _USART_ROUTELOC1_CTSLOC_SHIFT 0 /**< Shift value for USART_CTSLOC */
<> 139:856d2700e60b 1834 #define _USART_ROUTELOC1_CTSLOC_MASK 0x1FUL /**< Bit mask for USART_CTSLOC */
<> 139:856d2700e60b 1835 #define _USART_ROUTELOC1_CTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1836 #define _USART_ROUTELOC1_CTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */
<> 139:856d2700e60b 1837 #define _USART_ROUTELOC1_CTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1838 #define _USART_ROUTELOC1_CTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1839 #define _USART_ROUTELOC1_CTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1840 #define _USART_ROUTELOC1_CTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1841 #define _USART_ROUTELOC1_CTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1842 #define _USART_ROUTELOC1_CTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1843 #define _USART_ROUTELOC1_CTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1844 #define _USART_ROUTELOC1_CTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1845 #define _USART_ROUTELOC1_CTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1846 #define _USART_ROUTELOC1_CTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1847 #define _USART_ROUTELOC1_CTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1848 #define _USART_ROUTELOC1_CTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1849 #define _USART_ROUTELOC1_CTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1850 #define _USART_ROUTELOC1_CTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1851 #define _USART_ROUTELOC1_CTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1852 #define _USART_ROUTELOC1_CTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1853 #define _USART_ROUTELOC1_CTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1854 #define _USART_ROUTELOC1_CTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1855 #define _USART_ROUTELOC1_CTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1856 #define _USART_ROUTELOC1_CTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1857 #define _USART_ROUTELOC1_CTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1858 #define _USART_ROUTELOC1_CTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1859 #define _USART_ROUTELOC1_CTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1860 #define _USART_ROUTELOC1_CTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1861 #define _USART_ROUTELOC1_CTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1862 #define _USART_ROUTELOC1_CTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1863 #define _USART_ROUTELOC1_CTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1864 #define _USART_ROUTELOC1_CTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1865 #define _USART_ROUTELOC1_CTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1866 #define _USART_ROUTELOC1_CTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1867 #define _USART_ROUTELOC1_CTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1868 #define USART_ROUTELOC1_CTSLOC_LOC0 (_USART_ROUTELOC1_CTSLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1869 #define USART_ROUTELOC1_CTSLOC_DEFAULT (_USART_ROUTELOC1_CTSLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */
<> 139:856d2700e60b 1870 #define USART_ROUTELOC1_CTSLOC_LOC1 (_USART_ROUTELOC1_CTSLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1871 #define USART_ROUTELOC1_CTSLOC_LOC2 (_USART_ROUTELOC1_CTSLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1872 #define USART_ROUTELOC1_CTSLOC_LOC3 (_USART_ROUTELOC1_CTSLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1873 #define USART_ROUTELOC1_CTSLOC_LOC4 (_USART_ROUTELOC1_CTSLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1874 #define USART_ROUTELOC1_CTSLOC_LOC5 (_USART_ROUTELOC1_CTSLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1875 #define USART_ROUTELOC1_CTSLOC_LOC6 (_USART_ROUTELOC1_CTSLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1876 #define USART_ROUTELOC1_CTSLOC_LOC7 (_USART_ROUTELOC1_CTSLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1877 #define USART_ROUTELOC1_CTSLOC_LOC8 (_USART_ROUTELOC1_CTSLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1878 #define USART_ROUTELOC1_CTSLOC_LOC9 (_USART_ROUTELOC1_CTSLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1879 #define USART_ROUTELOC1_CTSLOC_LOC10 (_USART_ROUTELOC1_CTSLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1880 #define USART_ROUTELOC1_CTSLOC_LOC11 (_USART_ROUTELOC1_CTSLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1881 #define USART_ROUTELOC1_CTSLOC_LOC12 (_USART_ROUTELOC1_CTSLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1882 #define USART_ROUTELOC1_CTSLOC_LOC13 (_USART_ROUTELOC1_CTSLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1883 #define USART_ROUTELOC1_CTSLOC_LOC14 (_USART_ROUTELOC1_CTSLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1884 #define USART_ROUTELOC1_CTSLOC_LOC15 (_USART_ROUTELOC1_CTSLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1885 #define USART_ROUTELOC1_CTSLOC_LOC16 (_USART_ROUTELOC1_CTSLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1886 #define USART_ROUTELOC1_CTSLOC_LOC17 (_USART_ROUTELOC1_CTSLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1887 #define USART_ROUTELOC1_CTSLOC_LOC18 (_USART_ROUTELOC1_CTSLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1888 #define USART_ROUTELOC1_CTSLOC_LOC19 (_USART_ROUTELOC1_CTSLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1889 #define USART_ROUTELOC1_CTSLOC_LOC20 (_USART_ROUTELOC1_CTSLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1890 #define USART_ROUTELOC1_CTSLOC_LOC21 (_USART_ROUTELOC1_CTSLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1891 #define USART_ROUTELOC1_CTSLOC_LOC22 (_USART_ROUTELOC1_CTSLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1892 #define USART_ROUTELOC1_CTSLOC_LOC23 (_USART_ROUTELOC1_CTSLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1893 #define USART_ROUTELOC1_CTSLOC_LOC24 (_USART_ROUTELOC1_CTSLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1894 #define USART_ROUTELOC1_CTSLOC_LOC25 (_USART_ROUTELOC1_CTSLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1895 #define USART_ROUTELOC1_CTSLOC_LOC26 (_USART_ROUTELOC1_CTSLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1896 #define USART_ROUTELOC1_CTSLOC_LOC27 (_USART_ROUTELOC1_CTSLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1897 #define USART_ROUTELOC1_CTSLOC_LOC28 (_USART_ROUTELOC1_CTSLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1898 #define USART_ROUTELOC1_CTSLOC_LOC29 (_USART_ROUTELOC1_CTSLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1899 #define USART_ROUTELOC1_CTSLOC_LOC30 (_USART_ROUTELOC1_CTSLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1900 #define USART_ROUTELOC1_CTSLOC_LOC31 (_USART_ROUTELOC1_CTSLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1901 #define _USART_ROUTELOC1_RTSLOC_SHIFT 8 /**< Shift value for USART_RTSLOC */
<> 139:856d2700e60b 1902 #define _USART_ROUTELOC1_RTSLOC_MASK 0x1F00UL /**< Bit mask for USART_RTSLOC */
<> 139:856d2700e60b 1903 #define _USART_ROUTELOC1_RTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1904 #define _USART_ROUTELOC1_RTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */
<> 139:856d2700e60b 1905 #define _USART_ROUTELOC1_RTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1906 #define _USART_ROUTELOC1_RTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1907 #define _USART_ROUTELOC1_RTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1908 #define _USART_ROUTELOC1_RTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1909 #define _USART_ROUTELOC1_RTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1910 #define _USART_ROUTELOC1_RTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1911 #define _USART_ROUTELOC1_RTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1912 #define _USART_ROUTELOC1_RTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1913 #define _USART_ROUTELOC1_RTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1914 #define _USART_ROUTELOC1_RTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1915 #define _USART_ROUTELOC1_RTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1916 #define _USART_ROUTELOC1_RTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1917 #define _USART_ROUTELOC1_RTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1918 #define _USART_ROUTELOC1_RTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1919 #define _USART_ROUTELOC1_RTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1920 #define _USART_ROUTELOC1_RTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1921 #define _USART_ROUTELOC1_RTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1922 #define _USART_ROUTELOC1_RTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1923 #define _USART_ROUTELOC1_RTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1924 #define _USART_ROUTELOC1_RTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1925 #define _USART_ROUTELOC1_RTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1926 #define _USART_ROUTELOC1_RTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1927 #define _USART_ROUTELOC1_RTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1928 #define _USART_ROUTELOC1_RTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1929 #define _USART_ROUTELOC1_RTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1930 #define _USART_ROUTELOC1_RTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1931 #define _USART_ROUTELOC1_RTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1932 #define _USART_ROUTELOC1_RTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1933 #define _USART_ROUTELOC1_RTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1934 #define _USART_ROUTELOC1_RTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1935 #define _USART_ROUTELOC1_RTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1936 #define USART_ROUTELOC1_RTSLOC_LOC0 (_USART_ROUTELOC1_RTSLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1937 #define USART_ROUTELOC1_RTSLOC_DEFAULT (_USART_ROUTELOC1_RTSLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */
<> 139:856d2700e60b 1938 #define USART_ROUTELOC1_RTSLOC_LOC1 (_USART_ROUTELOC1_RTSLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1939 #define USART_ROUTELOC1_RTSLOC_LOC2 (_USART_ROUTELOC1_RTSLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1940 #define USART_ROUTELOC1_RTSLOC_LOC3 (_USART_ROUTELOC1_RTSLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1941 #define USART_ROUTELOC1_RTSLOC_LOC4 (_USART_ROUTELOC1_RTSLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1942 #define USART_ROUTELOC1_RTSLOC_LOC5 (_USART_ROUTELOC1_RTSLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1943 #define USART_ROUTELOC1_RTSLOC_LOC6 (_USART_ROUTELOC1_RTSLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1944 #define USART_ROUTELOC1_RTSLOC_LOC7 (_USART_ROUTELOC1_RTSLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1945 #define USART_ROUTELOC1_RTSLOC_LOC8 (_USART_ROUTELOC1_RTSLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1946 #define USART_ROUTELOC1_RTSLOC_LOC9 (_USART_ROUTELOC1_RTSLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1947 #define USART_ROUTELOC1_RTSLOC_LOC10 (_USART_ROUTELOC1_RTSLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1948 #define USART_ROUTELOC1_RTSLOC_LOC11 (_USART_ROUTELOC1_RTSLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1949 #define USART_ROUTELOC1_RTSLOC_LOC12 (_USART_ROUTELOC1_RTSLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1950 #define USART_ROUTELOC1_RTSLOC_LOC13 (_USART_ROUTELOC1_RTSLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1951 #define USART_ROUTELOC1_RTSLOC_LOC14 (_USART_ROUTELOC1_RTSLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1952 #define USART_ROUTELOC1_RTSLOC_LOC15 (_USART_ROUTELOC1_RTSLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1953 #define USART_ROUTELOC1_RTSLOC_LOC16 (_USART_ROUTELOC1_RTSLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1954 #define USART_ROUTELOC1_RTSLOC_LOC17 (_USART_ROUTELOC1_RTSLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1955 #define USART_ROUTELOC1_RTSLOC_LOC18 (_USART_ROUTELOC1_RTSLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1956 #define USART_ROUTELOC1_RTSLOC_LOC19 (_USART_ROUTELOC1_RTSLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1957 #define USART_ROUTELOC1_RTSLOC_LOC20 (_USART_ROUTELOC1_RTSLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1958 #define USART_ROUTELOC1_RTSLOC_LOC21 (_USART_ROUTELOC1_RTSLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1959 #define USART_ROUTELOC1_RTSLOC_LOC22 (_USART_ROUTELOC1_RTSLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1960 #define USART_ROUTELOC1_RTSLOC_LOC23 (_USART_ROUTELOC1_RTSLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1961 #define USART_ROUTELOC1_RTSLOC_LOC24 (_USART_ROUTELOC1_RTSLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1962 #define USART_ROUTELOC1_RTSLOC_LOC25 (_USART_ROUTELOC1_RTSLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1963 #define USART_ROUTELOC1_RTSLOC_LOC26 (_USART_ROUTELOC1_RTSLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1964 #define USART_ROUTELOC1_RTSLOC_LOC27 (_USART_ROUTELOC1_RTSLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1965 #define USART_ROUTELOC1_RTSLOC_LOC28 (_USART_ROUTELOC1_RTSLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1966 #define USART_ROUTELOC1_RTSLOC_LOC29 (_USART_ROUTELOC1_RTSLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1967 #define USART_ROUTELOC1_RTSLOC_LOC30 (_USART_ROUTELOC1_RTSLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1968 #define USART_ROUTELOC1_RTSLOC_LOC31 (_USART_ROUTELOC1_RTSLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC1 */
<> 139:856d2700e60b 1969
<> 139:856d2700e60b 1970 /** @} End of group EFM32PG12B_USART */
<> 139:856d2700e60b 1971 /** @} End of group Parts */
<> 139:856d2700e60b 1972