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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32PG12_STK3402/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_trng.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
139:856d2700e60b 
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 139:856d2700e60b 1 /**************************************************************************//**
<> 139:856d2700e60b 2 * @file efm32pg12b_trng.h
<> 139:856d2700e60b 3 * @brief EFM32PG12B_TRNG register and bit field definitions
<> 139:856d2700e60b 4 * @version 5.1.2
<> 139:856d2700e60b 5 ******************************************************************************
<> 139:856d2700e60b 6 * @section License
<> 139:856d2700e60b 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 139:856d2700e60b 8 ******************************************************************************
<> 139:856d2700e60b 9 *
<> 139:856d2700e60b 10 * Permission is granted to anyone to use this software for any purpose,
<> 139:856d2700e60b 11 * including commercial applications, and to alter it and redistribute it
<> 139:856d2700e60b 12 * freely, subject to the following restrictions:
<> 139:856d2700e60b 13 *
<> 139:856d2700e60b 14 * 1. The origin of this software must not be misrepresented; you must not
<> 139:856d2700e60b 15 * claim that you wrote the original software.@n
<> 139:856d2700e60b 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 139:856d2700e60b 17 * misrepresented as being the original software.@n
<> 139:856d2700e60b 18 * 3. This notice may not be removed or altered from any source distribution.
<> 139:856d2700e60b 19 *
<> 139:856d2700e60b 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 139:856d2700e60b 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 139:856d2700e60b 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 139:856d2700e60b 23 * kind, including, but not limited to, any implied warranties of
<> 139:856d2700e60b 24 * merchantability or fitness for any particular purpose or warranties against
<> 139:856d2700e60b 25 * infringement of any proprietary rights of a third party.
<> 139:856d2700e60b 26 *
<> 139:856d2700e60b 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 139:856d2700e60b 28 * incidental, or special damages, or any other relief, or for any claim by
<> 139:856d2700e60b 29 * any third party, arising from your use of this Software.
<> 139:856d2700e60b 30 *
<> 139:856d2700e60b 31 *****************************************************************************/
<> 139:856d2700e60b 32 /**************************************************************************//**
<> 139:856d2700e60b 33 * @addtogroup Parts
<> 139:856d2700e60b 34 * @{
<> 139:856d2700e60b 35 ******************************************************************************/
<> 139:856d2700e60b 36 /**************************************************************************//**
<> 139:856d2700e60b 37 * @defgroup EFM32PG12B_TRNG
<> 139:856d2700e60b 38 * @{
<> 139:856d2700e60b 39 * @brief EFM32PG12B_TRNG Register Declaration
<> 139:856d2700e60b 40 *****************************************************************************/
<> 139:856d2700e60b 41 typedef struct
<> 139:856d2700e60b 42 {
<> 139:856d2700e60b 43 __IOM uint32_t CONTROL; /**< Main Control Register */
<> 139:856d2700e60b 44 __IM uint32_t FIFOLEVEL; /**< FIFO Level Register */
<> 139:856d2700e60b 45 uint32_t RESERVED0[1]; /**< Reserved for future use **/
<> 139:856d2700e60b 46 __IM uint32_t FIFODEPTH; /**< FIFO Depth Register */
<> 139:856d2700e60b 47 __IOM uint32_t KEY0; /**< Key Register 0 */
<> 139:856d2700e60b 48 __IOM uint32_t KEY1; /**< Key Register 1 */
<> 139:856d2700e60b 49 __IOM uint32_t KEY2; /**< Key Register 2 */
<> 139:856d2700e60b 50 __IOM uint32_t KEY3; /**< Key Register 3 */
<> 139:856d2700e60b 51 __IOM uint32_t TESTDATA; /**< Test Data Register */
<> 139:856d2700e60b 52
<> 139:856d2700e60b 53 uint32_t RESERVED1[3]; /**< Reserved for future use **/
<> 139:856d2700e60b 54 __IOM uint32_t STATUS; /**< Status Register */
<> 139:856d2700e60b 55 __IOM uint32_t INITWAITVAL; /**< Initial Wait Counter */
<> 139:856d2700e60b 56 uint32_t RESERVED2[50]; /**< Reserved for future use **/
<> 139:856d2700e60b 57 __IM uint32_t FIFO; /**< FIFO Data */
<> 139:856d2700e60b 58 } TRNG_TypeDef; /** @} */
<> 139:856d2700e60b 59
<> 139:856d2700e60b 60 /**************************************************************************//**
<> 139:856d2700e60b 61 * @defgroup EFM32PG12B_TRNG_BitFields
<> 139:856d2700e60b 62 * @{
<> 139:856d2700e60b 63 *****************************************************************************/
<> 139:856d2700e60b 64
<> 139:856d2700e60b 65 /* Bit fields for TRNG CONTROL */
<> 139:856d2700e60b 66 #define _TRNG_CONTROL_RESETVALUE 0x00000000UL /**< Default value for TRNG_CONTROL */
<> 139:856d2700e60b 67 #define _TRNG_CONTROL_MASK 0x00003FFDUL /**< Mask for TRNG_CONTROL */
<> 139:856d2700e60b 68 #define TRNG_CONTROL_ENABLE (0x1UL << 0) /**< TRNG Module Enable */
<> 139:856d2700e60b 69 #define _TRNG_CONTROL_ENABLE_SHIFT 0 /**< Shift value for TRNG_ENABLE */
<> 139:856d2700e60b 70 #define _TRNG_CONTROL_ENABLE_MASK 0x1UL /**< Bit mask for TRNG_ENABLE */
<> 139:856d2700e60b 71 #define _TRNG_CONTROL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 72 #define _TRNG_CONTROL_ENABLE_DISABLED 0x00000000UL /**< Mode DISABLED for TRNG_CONTROL */
<> 139:856d2700e60b 73 #define _TRNG_CONTROL_ENABLE_ENABLED 0x00000001UL /**< Mode ENABLED for TRNG_CONTROL */
<> 139:856d2700e60b 74 #define TRNG_CONTROL_ENABLE_DEFAULT (_TRNG_CONTROL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 75 #define TRNG_CONTROL_ENABLE_DISABLED (_TRNG_CONTROL_ENABLE_DISABLED << 0) /**< Shifted mode DISABLED for TRNG_CONTROL */
<> 139:856d2700e60b 76 #define TRNG_CONTROL_ENABLE_ENABLED (_TRNG_CONTROL_ENABLE_ENABLED << 0) /**< Shifted mode ENABLED for TRNG_CONTROL */
<> 139:856d2700e60b 77 #define TRNG_CONTROL_TESTEN (0x1UL << 2) /**< Test Enable */
<> 139:856d2700e60b 78 #define _TRNG_CONTROL_TESTEN_SHIFT 2 /**< Shift value for TRNG_TESTEN */
<> 139:856d2700e60b 79 #define _TRNG_CONTROL_TESTEN_MASK 0x4UL /**< Bit mask for TRNG_TESTEN */
<> 139:856d2700e60b 80 #define _TRNG_CONTROL_TESTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 81 #define _TRNG_CONTROL_TESTEN_NOISE 0x00000000UL /**< Mode NOISE for TRNG_CONTROL */
<> 139:856d2700e60b 82 #define _TRNG_CONTROL_TESTEN_TESTDATA 0x00000001UL /**< Mode TESTDATA for TRNG_CONTROL */
<> 139:856d2700e60b 83 #define TRNG_CONTROL_TESTEN_DEFAULT (_TRNG_CONTROL_TESTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 84 #define TRNG_CONTROL_TESTEN_NOISE (_TRNG_CONTROL_TESTEN_NOISE << 2) /**< Shifted mode NOISE for TRNG_CONTROL */
<> 139:856d2700e60b 85 #define TRNG_CONTROL_TESTEN_TESTDATA (_TRNG_CONTROL_TESTEN_TESTDATA << 2) /**< Shifted mode TESTDATA for TRNG_CONTROL */
<> 139:856d2700e60b 86 #define TRNG_CONTROL_CONDBYPASS (0x1UL << 3) /**< Conditioning Bypass */
<> 139:856d2700e60b 87 #define _TRNG_CONTROL_CONDBYPASS_SHIFT 3 /**< Shift value for TRNG_CONDBYPASS */
<> 139:856d2700e60b 88 #define _TRNG_CONTROL_CONDBYPASS_MASK 0x8UL /**< Bit mask for TRNG_CONDBYPASS */
<> 139:856d2700e60b 89 #define _TRNG_CONTROL_CONDBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 90 #define _TRNG_CONTROL_CONDBYPASS_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */
<> 139:856d2700e60b 91 #define _TRNG_CONTROL_CONDBYPASS_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */
<> 139:856d2700e60b 92 #define TRNG_CONTROL_CONDBYPASS_DEFAULT (_TRNG_CONTROL_CONDBYPASS_DEFAULT << 3) /**< Shifted mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 93 #define TRNG_CONTROL_CONDBYPASS_NORMAL (_TRNG_CONTROL_CONDBYPASS_NORMAL << 3) /**< Shifted mode NORMAL for TRNG_CONTROL */
<> 139:856d2700e60b 94 #define TRNG_CONTROL_CONDBYPASS_BYPASS (_TRNG_CONTROL_CONDBYPASS_BYPASS << 3) /**< Shifted mode BYPASS for TRNG_CONTROL */
<> 139:856d2700e60b 95 #define TRNG_CONTROL_REPCOUNTIEN (0x1UL << 4) /**< Interrupt enable for Repetition Count Test failure */
<> 139:856d2700e60b 96 #define _TRNG_CONTROL_REPCOUNTIEN_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIEN */
<> 139:856d2700e60b 97 #define _TRNG_CONTROL_REPCOUNTIEN_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIEN */
<> 139:856d2700e60b 98 #define _TRNG_CONTROL_REPCOUNTIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 99 #define TRNG_CONTROL_REPCOUNTIEN_DEFAULT (_TRNG_CONTROL_REPCOUNTIEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 100 #define TRNG_CONTROL_APT64IEN (0x1UL << 5) /**< Interrupt enable for Adaptive Proportion Test failure (64-sample window) */
<> 139:856d2700e60b 101 #define _TRNG_CONTROL_APT64IEN_SHIFT 5 /**< Shift value for TRNG_APT64IEN */
<> 139:856d2700e60b 102 #define _TRNG_CONTROL_APT64IEN_MASK 0x20UL /**< Bit mask for TRNG_APT64IEN */
<> 139:856d2700e60b 103 #define _TRNG_CONTROL_APT64IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 104 #define TRNG_CONTROL_APT64IEN_DEFAULT (_TRNG_CONTROL_APT64IEN_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 105 #define TRNG_CONTROL_APT4096IEN (0x1UL << 6) /**< Interrupt enable for Adaptive Proportion Test failure (4096-sample window) */
<> 139:856d2700e60b 106 #define _TRNG_CONTROL_APT4096IEN_SHIFT 6 /**< Shift value for TRNG_APT4096IEN */
<> 139:856d2700e60b 107 #define _TRNG_CONTROL_APT4096IEN_MASK 0x40UL /**< Bit mask for TRNG_APT4096IEN */
<> 139:856d2700e60b 108 #define _TRNG_CONTROL_APT4096IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 109 #define TRNG_CONTROL_APT4096IEN_DEFAULT (_TRNG_CONTROL_APT4096IEN_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 110 #define TRNG_CONTROL_FULLIEN (0x1UL << 7) /**< Interrupt enable for FIFO full */
<> 139:856d2700e60b 111 #define _TRNG_CONTROL_FULLIEN_SHIFT 7 /**< Shift value for TRNG_FULLIEN */
<> 139:856d2700e60b 112 #define _TRNG_CONTROL_FULLIEN_MASK 0x80UL /**< Bit mask for TRNG_FULLIEN */
<> 139:856d2700e60b 113 #define _TRNG_CONTROL_FULLIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 114 #define TRNG_CONTROL_FULLIEN_DEFAULT (_TRNG_CONTROL_FULLIEN_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 115 #define TRNG_CONTROL_SOFTRESET (0x1UL << 8) /**< Software Reset */
<> 139:856d2700e60b 116 #define _TRNG_CONTROL_SOFTRESET_SHIFT 8 /**< Shift value for TRNG_SOFTRESET */
<> 139:856d2700e60b 117 #define _TRNG_CONTROL_SOFTRESET_MASK 0x100UL /**< Bit mask for TRNG_SOFTRESET */
<> 139:856d2700e60b 118 #define _TRNG_CONTROL_SOFTRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 119 #define _TRNG_CONTROL_SOFTRESET_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */
<> 139:856d2700e60b 120 #define _TRNG_CONTROL_SOFTRESET_RESET 0x00000001UL /**< Mode RESET for TRNG_CONTROL */
<> 139:856d2700e60b 121 #define TRNG_CONTROL_SOFTRESET_DEFAULT (_TRNG_CONTROL_SOFTRESET_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 122 #define TRNG_CONTROL_SOFTRESET_NORMAL (_TRNG_CONTROL_SOFTRESET_NORMAL << 8) /**< Shifted mode NORMAL for TRNG_CONTROL */
<> 139:856d2700e60b 123 #define TRNG_CONTROL_SOFTRESET_RESET (_TRNG_CONTROL_SOFTRESET_RESET << 8) /**< Shifted mode RESET for TRNG_CONTROL */
<> 139:856d2700e60b 124 #define TRNG_CONTROL_PREIEN (0x1UL << 9) /**< Interrupt enable for AIS31 preliminary noise alarm */
<> 139:856d2700e60b 125 #define _TRNG_CONTROL_PREIEN_SHIFT 9 /**< Shift value for TRNG_PREIEN */
<> 139:856d2700e60b 126 #define _TRNG_CONTROL_PREIEN_MASK 0x200UL /**< Bit mask for TRNG_PREIEN */
<> 139:856d2700e60b 127 #define _TRNG_CONTROL_PREIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 128 #define TRNG_CONTROL_PREIEN_DEFAULT (_TRNG_CONTROL_PREIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 129 #define TRNG_CONTROL_ALMIEN (0x1UL << 10) /**< Interrupt enable for AIS31 noise alarm */
<> 139:856d2700e60b 130 #define _TRNG_CONTROL_ALMIEN_SHIFT 10 /**< Shift value for TRNG_ALMIEN */
<> 139:856d2700e60b 131 #define _TRNG_CONTROL_ALMIEN_MASK 0x400UL /**< Bit mask for TRNG_ALMIEN */
<> 139:856d2700e60b 132 #define _TRNG_CONTROL_ALMIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 133 #define TRNG_CONTROL_ALMIEN_DEFAULT (_TRNG_CONTROL_ALMIEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 134 #define TRNG_CONTROL_FORCERUN (0x1UL << 11) /**< Oscillator Force Run */
<> 139:856d2700e60b 135 #define _TRNG_CONTROL_FORCERUN_SHIFT 11 /**< Shift value for TRNG_FORCERUN */
<> 139:856d2700e60b 136 #define _TRNG_CONTROL_FORCERUN_MASK 0x800UL /**< Bit mask for TRNG_FORCERUN */
<> 139:856d2700e60b 137 #define _TRNG_CONTROL_FORCERUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 138 #define _TRNG_CONTROL_FORCERUN_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */
<> 139:856d2700e60b 139 #define _TRNG_CONTROL_FORCERUN_RUN 0x00000001UL /**< Mode RUN for TRNG_CONTROL */
<> 139:856d2700e60b 140 #define TRNG_CONTROL_FORCERUN_DEFAULT (_TRNG_CONTROL_FORCERUN_DEFAULT << 11) /**< Shifted mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 141 #define TRNG_CONTROL_FORCERUN_NORMAL (_TRNG_CONTROL_FORCERUN_NORMAL << 11) /**< Shifted mode NORMAL for TRNG_CONTROL */
<> 139:856d2700e60b 142 #define TRNG_CONTROL_FORCERUN_RUN (_TRNG_CONTROL_FORCERUN_RUN << 11) /**< Shifted mode RUN for TRNG_CONTROL */
<> 139:856d2700e60b 143 #define TRNG_CONTROL_BYPNIST (0x1UL << 12) /**< NIST Start-up Test Bypass. */
<> 139:856d2700e60b 144 #define _TRNG_CONTROL_BYPNIST_SHIFT 12 /**< Shift value for TRNG_BYPNIST */
<> 139:856d2700e60b 145 #define _TRNG_CONTROL_BYPNIST_MASK 0x1000UL /**< Bit mask for TRNG_BYPNIST */
<> 139:856d2700e60b 146 #define _TRNG_CONTROL_BYPNIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 147 #define _TRNG_CONTROL_BYPNIST_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */
<> 139:856d2700e60b 148 #define _TRNG_CONTROL_BYPNIST_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */
<> 139:856d2700e60b 149 #define TRNG_CONTROL_BYPNIST_DEFAULT (_TRNG_CONTROL_BYPNIST_DEFAULT << 12) /**< Shifted mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 150 #define TRNG_CONTROL_BYPNIST_NORMAL (_TRNG_CONTROL_BYPNIST_NORMAL << 12) /**< Shifted mode NORMAL for TRNG_CONTROL */
<> 139:856d2700e60b 151 #define TRNG_CONTROL_BYPNIST_BYPASS (_TRNG_CONTROL_BYPNIST_BYPASS << 12) /**< Shifted mode BYPASS for TRNG_CONTROL */
<> 139:856d2700e60b 152 #define TRNG_CONTROL_BYPAIS31 (0x1UL << 13) /**< AIS31 Start-up Test Bypass. */
<> 139:856d2700e60b 153 #define _TRNG_CONTROL_BYPAIS31_SHIFT 13 /**< Shift value for TRNG_BYPAIS31 */
<> 139:856d2700e60b 154 #define _TRNG_CONTROL_BYPAIS31_MASK 0x2000UL /**< Bit mask for TRNG_BYPAIS31 */
<> 139:856d2700e60b 155 #define _TRNG_CONTROL_BYPAIS31_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 156 #define _TRNG_CONTROL_BYPAIS31_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */
<> 139:856d2700e60b 157 #define _TRNG_CONTROL_BYPAIS31_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */
<> 139:856d2700e60b 158 #define TRNG_CONTROL_BYPAIS31_DEFAULT (_TRNG_CONTROL_BYPAIS31_DEFAULT << 13) /**< Shifted mode DEFAULT for TRNG_CONTROL */
<> 139:856d2700e60b 159 #define TRNG_CONTROL_BYPAIS31_NORMAL (_TRNG_CONTROL_BYPAIS31_NORMAL << 13) /**< Shifted mode NORMAL for TRNG_CONTROL */
<> 139:856d2700e60b 160 #define TRNG_CONTROL_BYPAIS31_BYPASS (_TRNG_CONTROL_BYPAIS31_BYPASS << 13) /**< Shifted mode BYPASS for TRNG_CONTROL */
<> 139:856d2700e60b 161
<> 139:856d2700e60b 162 /* Bit fields for TRNG FIFOLEVEL */
<> 139:856d2700e60b 163 #define _TRNG_FIFOLEVEL_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFOLEVEL */
<> 139:856d2700e60b 164 #define _TRNG_FIFOLEVEL_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFOLEVEL */
<> 139:856d2700e60b 165 #define _TRNG_FIFOLEVEL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
<> 139:856d2700e60b 166 #define _TRNG_FIFOLEVEL_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
<> 139:856d2700e60b 167 #define _TRNG_FIFOLEVEL_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFOLEVEL */
<> 139:856d2700e60b 168 #define TRNG_FIFOLEVEL_VALUE_DEFAULT (_TRNG_FIFOLEVEL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFOLEVEL */
<> 139:856d2700e60b 169
<> 139:856d2700e60b 170 /* Bit fields for TRNG FIFODEPTH */
<> 139:856d2700e60b 171 #define _TRNG_FIFODEPTH_RESETVALUE 0x00000040UL /**< Default value for TRNG_FIFODEPTH */
<> 139:856d2700e60b 172 #define _TRNG_FIFODEPTH_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFODEPTH */
<> 139:856d2700e60b 173 #define _TRNG_FIFODEPTH_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
<> 139:856d2700e60b 174 #define _TRNG_FIFODEPTH_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
<> 139:856d2700e60b 175 #define _TRNG_FIFODEPTH_VALUE_DEFAULT 0x00000040UL /**< Mode DEFAULT for TRNG_FIFODEPTH */
<> 139:856d2700e60b 176 #define TRNG_FIFODEPTH_VALUE_DEFAULT (_TRNG_FIFODEPTH_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFODEPTH */
<> 139:856d2700e60b 177
<> 139:856d2700e60b 178 /* Bit fields for TRNG KEY0 */
<> 139:856d2700e60b 179 #define _TRNG_KEY0_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY0 */
<> 139:856d2700e60b 180 #define _TRNG_KEY0_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY0 */
<> 139:856d2700e60b 181 #define _TRNG_KEY0_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
<> 139:856d2700e60b 182 #define _TRNG_KEY0_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
<> 139:856d2700e60b 183 #define _TRNG_KEY0_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY0 */
<> 139:856d2700e60b 184 #define TRNG_KEY0_VALUE_DEFAULT (_TRNG_KEY0_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY0 */
<> 139:856d2700e60b 185
<> 139:856d2700e60b 186 /* Bit fields for TRNG KEY1 */
<> 139:856d2700e60b 187 #define _TRNG_KEY1_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY1 */
<> 139:856d2700e60b 188 #define _TRNG_KEY1_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY1 */
<> 139:856d2700e60b 189 #define _TRNG_KEY1_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
<> 139:856d2700e60b 190 #define _TRNG_KEY1_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
<> 139:856d2700e60b 191 #define _TRNG_KEY1_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY1 */
<> 139:856d2700e60b 192 #define TRNG_KEY1_VALUE_DEFAULT (_TRNG_KEY1_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY1 */
<> 139:856d2700e60b 193
<> 139:856d2700e60b 194 /* Bit fields for TRNG KEY2 */
<> 139:856d2700e60b 195 #define _TRNG_KEY2_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY2 */
<> 139:856d2700e60b 196 #define _TRNG_KEY2_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY2 */
<> 139:856d2700e60b 197 #define _TRNG_KEY2_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
<> 139:856d2700e60b 198 #define _TRNG_KEY2_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
<> 139:856d2700e60b 199 #define _TRNG_KEY2_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY2 */
<> 139:856d2700e60b 200 #define TRNG_KEY2_VALUE_DEFAULT (_TRNG_KEY2_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY2 */
<> 139:856d2700e60b 201
<> 139:856d2700e60b 202 /* Bit fields for TRNG KEY3 */
<> 139:856d2700e60b 203 #define _TRNG_KEY3_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY3 */
<> 139:856d2700e60b 204 #define _TRNG_KEY3_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY3 */
<> 139:856d2700e60b 205 #define _TRNG_KEY3_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
<> 139:856d2700e60b 206 #define _TRNG_KEY3_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
<> 139:856d2700e60b 207 #define _TRNG_KEY3_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY3 */
<> 139:856d2700e60b 208 #define TRNG_KEY3_VALUE_DEFAULT (_TRNG_KEY3_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY3 */
<> 139:856d2700e60b 209
<> 139:856d2700e60b 210 /* Bit fields for TRNG TESTDATA */
<> 139:856d2700e60b 211 #define _TRNG_TESTDATA_RESETVALUE 0x00000000UL /**< Default value for TRNG_TESTDATA */
<> 139:856d2700e60b 212 #define _TRNG_TESTDATA_MASK 0xFFFFFFFFUL /**< Mask for TRNG_TESTDATA */
<> 139:856d2700e60b 213 #define _TRNG_TESTDATA_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
<> 139:856d2700e60b 214 #define _TRNG_TESTDATA_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
<> 139:856d2700e60b 215 #define _TRNG_TESTDATA_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_TESTDATA */
<> 139:856d2700e60b 216 #define TRNG_TESTDATA_VALUE_DEFAULT (_TRNG_TESTDATA_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_TESTDATA */
<> 139:856d2700e60b 217
<> 139:856d2700e60b 218 /* Bit fields for TRNG STATUS */
<> 139:856d2700e60b 219 #define _TRNG_STATUS_RESETVALUE 0x00000000UL /**< Default value for TRNG_STATUS */
<> 139:856d2700e60b 220 #define _TRNG_STATUS_MASK 0x000003F1UL /**< Mask for TRNG_STATUS */
<> 139:856d2700e60b 221 #define TRNG_STATUS_TESTDATABUSY (0x1UL << 0) /**< Test Data Busy */
<> 139:856d2700e60b 222 #define _TRNG_STATUS_TESTDATABUSY_SHIFT 0 /**< Shift value for TRNG_TESTDATABUSY */
<> 139:856d2700e60b 223 #define _TRNG_STATUS_TESTDATABUSY_MASK 0x1UL /**< Bit mask for TRNG_TESTDATABUSY */
<> 139:856d2700e60b 224 #define _TRNG_STATUS_TESTDATABUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
<> 139:856d2700e60b 225 #define _TRNG_STATUS_TESTDATABUSY_IDLE 0x00000000UL /**< Mode IDLE for TRNG_STATUS */
<> 139:856d2700e60b 226 #define _TRNG_STATUS_TESTDATABUSY_BUSY 0x00000001UL /**< Mode BUSY for TRNG_STATUS */
<> 139:856d2700e60b 227 #define TRNG_STATUS_TESTDATABUSY_DEFAULT (_TRNG_STATUS_TESTDATABUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_STATUS */
<> 139:856d2700e60b 228 #define TRNG_STATUS_TESTDATABUSY_IDLE (_TRNG_STATUS_TESTDATABUSY_IDLE << 0) /**< Shifted mode IDLE for TRNG_STATUS */
<> 139:856d2700e60b 229 #define TRNG_STATUS_TESTDATABUSY_BUSY (_TRNG_STATUS_TESTDATABUSY_BUSY << 0) /**< Shifted mode BUSY for TRNG_STATUS */
<> 139:856d2700e60b 230 #define TRNG_STATUS_REPCOUNTIF (0x1UL << 4) /**< Repetition Count Test interrupt status */
<> 139:856d2700e60b 231 #define _TRNG_STATUS_REPCOUNTIF_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIF */
<> 139:856d2700e60b 232 #define _TRNG_STATUS_REPCOUNTIF_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIF */
<> 139:856d2700e60b 233 #define _TRNG_STATUS_REPCOUNTIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
<> 139:856d2700e60b 234 #define TRNG_STATUS_REPCOUNTIF_DEFAULT (_TRNG_STATUS_REPCOUNTIF_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_STATUS */
<> 139:856d2700e60b 235 #define TRNG_STATUS_APT64IF (0x1UL << 5) /**< Adaptive Proportion test failure (64-sample window) interrupt status */
<> 139:856d2700e60b 236 #define _TRNG_STATUS_APT64IF_SHIFT 5 /**< Shift value for TRNG_APT64IF */
<> 139:856d2700e60b 237 #define _TRNG_STATUS_APT64IF_MASK 0x20UL /**< Bit mask for TRNG_APT64IF */
<> 139:856d2700e60b 238 #define _TRNG_STATUS_APT64IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
<> 139:856d2700e60b 239 #define TRNG_STATUS_APT64IF_DEFAULT (_TRNG_STATUS_APT64IF_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_STATUS */
<> 139:856d2700e60b 240 #define TRNG_STATUS_APT4096IF (0x1UL << 6) /**< Adaptive Proportion test failure (4096-sample window) interrupt status */
<> 139:856d2700e60b 241 #define _TRNG_STATUS_APT4096IF_SHIFT 6 /**< Shift value for TRNG_APT4096IF */
<> 139:856d2700e60b 242 #define _TRNG_STATUS_APT4096IF_MASK 0x40UL /**< Bit mask for TRNG_APT4096IF */
<> 139:856d2700e60b 243 #define _TRNG_STATUS_APT4096IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
<> 139:856d2700e60b 244 #define TRNG_STATUS_APT4096IF_DEFAULT (_TRNG_STATUS_APT4096IF_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_STATUS */
<> 139:856d2700e60b 245 #define TRNG_STATUS_FULLIF (0x1UL << 7) /**< FIFO full interrupt status */
<> 139:856d2700e60b 246 #define _TRNG_STATUS_FULLIF_SHIFT 7 /**< Shift value for TRNG_FULLIF */
<> 139:856d2700e60b 247 #define _TRNG_STATUS_FULLIF_MASK 0x80UL /**< Bit mask for TRNG_FULLIF */
<> 139:856d2700e60b 248 #define _TRNG_STATUS_FULLIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
<> 139:856d2700e60b 249 #define TRNG_STATUS_FULLIF_DEFAULT (_TRNG_STATUS_FULLIF_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_STATUS */
<> 139:856d2700e60b 250 #define TRNG_STATUS_PREIF (0x1UL << 8) /**< AIS31 Preliminary Noise Alarm interrupt status */
<> 139:856d2700e60b 251 #define _TRNG_STATUS_PREIF_SHIFT 8 /**< Shift value for TRNG_PREIF */
<> 139:856d2700e60b 252 #define _TRNG_STATUS_PREIF_MASK 0x100UL /**< Bit mask for TRNG_PREIF */
<> 139:856d2700e60b 253 #define _TRNG_STATUS_PREIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
<> 139:856d2700e60b 254 #define TRNG_STATUS_PREIF_DEFAULT (_TRNG_STATUS_PREIF_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_STATUS */
<> 139:856d2700e60b 255 #define TRNG_STATUS_ALMIF (0x1UL << 9) /**< AIS31 Noise Alarm interrupt status */
<> 139:856d2700e60b 256 #define _TRNG_STATUS_ALMIF_SHIFT 9 /**< Shift value for TRNG_ALMIF */
<> 139:856d2700e60b 257 #define _TRNG_STATUS_ALMIF_MASK 0x200UL /**< Bit mask for TRNG_ALMIF */
<> 139:856d2700e60b 258 #define _TRNG_STATUS_ALMIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */
<> 139:856d2700e60b 259 #define TRNG_STATUS_ALMIF_DEFAULT (_TRNG_STATUS_ALMIF_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_STATUS */
<> 139:856d2700e60b 260
<> 139:856d2700e60b 261 /* Bit fields for TRNG INITWAITVAL */
<> 139:856d2700e60b 262 #define _TRNG_INITWAITVAL_RESETVALUE 0x000000FFUL /**< Default value for TRNG_INITWAITVAL */
<> 139:856d2700e60b 263 #define _TRNG_INITWAITVAL_MASK 0x000000FFUL /**< Mask for TRNG_INITWAITVAL */
<> 139:856d2700e60b 264 #define _TRNG_INITWAITVAL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
<> 139:856d2700e60b 265 #define _TRNG_INITWAITVAL_VALUE_MASK 0xFFUL /**< Bit mask for TRNG_VALUE */
<> 139:856d2700e60b 266 #define _TRNG_INITWAITVAL_VALUE_DEFAULT 0x000000FFUL /**< Mode DEFAULT for TRNG_INITWAITVAL */
<> 139:856d2700e60b 267 #define TRNG_INITWAITVAL_VALUE_DEFAULT (_TRNG_INITWAITVAL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_INITWAITVAL */
<> 139:856d2700e60b 268
<> 139:856d2700e60b 269 /* Bit fields for TRNG FIFO */
<> 139:856d2700e60b 270 #define _TRNG_FIFO_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFO */
<> 139:856d2700e60b 271 #define _TRNG_FIFO_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFO */
<> 139:856d2700e60b 272 #define _TRNG_FIFO_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */
<> 139:856d2700e60b 273 #define _TRNG_FIFO_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */
<> 139:856d2700e60b 274 #define _TRNG_FIFO_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFO */
<> 139:856d2700e60b 275 #define TRNG_FIFO_VALUE_DEFAULT (_TRNG_FIFO_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFO */
<> 139:856d2700e60b 276
<> 139:856d2700e60b 277 /** @} End of group EFM32PG12B_TRNG */
<> 139:856d2700e60b 278 /** @} End of group Parts */
<> 139:856d2700e60b 279