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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32PG12_STK3402/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_rtcc.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
139:856d2700e60b 
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 139:856d2700e60b 1 /**************************************************************************//**
<> 139:856d2700e60b 2 * @file efm32pg12b_rtcc.h
<> 139:856d2700e60b 3 * @brief EFM32PG12B_RTCC register and bit field definitions
<> 139:856d2700e60b 4 * @version 5.1.2
<> 139:856d2700e60b 5 ******************************************************************************
<> 139:856d2700e60b 6 * @section License
<> 139:856d2700e60b 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 139:856d2700e60b 8 ******************************************************************************
<> 139:856d2700e60b 9 *
<> 139:856d2700e60b 10 * Permission is granted to anyone to use this software for any purpose,
<> 139:856d2700e60b 11 * including commercial applications, and to alter it and redistribute it
<> 139:856d2700e60b 12 * freely, subject to the following restrictions:
<> 139:856d2700e60b 13 *
<> 139:856d2700e60b 14 * 1. The origin of this software must not be misrepresented; you must not
<> 139:856d2700e60b 15 * claim that you wrote the original software.@n
<> 139:856d2700e60b 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 139:856d2700e60b 17 * misrepresented as being the original software.@n
<> 139:856d2700e60b 18 * 3. This notice may not be removed or altered from any source distribution.
<> 139:856d2700e60b 19 *
<> 139:856d2700e60b 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 139:856d2700e60b 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 139:856d2700e60b 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 139:856d2700e60b 23 * kind, including, but not limited to, any implied warranties of
<> 139:856d2700e60b 24 * merchantability or fitness for any particular purpose or warranties against
<> 139:856d2700e60b 25 * infringement of any proprietary rights of a third party.
<> 139:856d2700e60b 26 *
<> 139:856d2700e60b 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 139:856d2700e60b 28 * incidental, or special damages, or any other relief, or for any claim by
<> 139:856d2700e60b 29 * any third party, arising from your use of this Software.
<> 139:856d2700e60b 30 *
<> 139:856d2700e60b 31 *****************************************************************************/
<> 139:856d2700e60b 32 /**************************************************************************//**
<> 139:856d2700e60b 33 * @addtogroup Parts
<> 139:856d2700e60b 34 * @{
<> 139:856d2700e60b 35 ******************************************************************************/
<> 139:856d2700e60b 36 /**************************************************************************//**
<> 139:856d2700e60b 37 * @defgroup EFM32PG12B_RTCC
<> 139:856d2700e60b 38 * @{
<> 139:856d2700e60b 39 * @brief EFM32PG12B_RTCC Register Declaration
<> 139:856d2700e60b 40 *****************************************************************************/
<> 139:856d2700e60b 41 typedef struct
<> 139:856d2700e60b 42 {
<> 139:856d2700e60b 43 __IOM uint32_t CTRL; /**< Control Register */
<> 139:856d2700e60b 44 __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */
<> 139:856d2700e60b 45 __IOM uint32_t CNT; /**< Counter Value Register */
<> 139:856d2700e60b 46 __IM uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Value Register */
<> 139:856d2700e60b 47 __IOM uint32_t TIME; /**< Time of day register */
<> 139:856d2700e60b 48 __IOM uint32_t DATE; /**< Date register */
<> 139:856d2700e60b 49 __IM uint32_t IF; /**< RTCC Interrupt Flags */
<> 139:856d2700e60b 50 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 139:856d2700e60b 51 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 139:856d2700e60b 52 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 139:856d2700e60b 53 __IM uint32_t STATUS; /**< Status register */
<> 139:856d2700e60b 54 __IOM uint32_t CMD; /**< Command Register */
<> 139:856d2700e60b 55 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
<> 139:856d2700e60b 56 __IOM uint32_t POWERDOWN; /**< Retention RAM power-down register */
<> 139:856d2700e60b 57 __IOM uint32_t LOCK; /**< Configuration Lock Register */
<> 139:856d2700e60b 58 __IOM uint32_t EM4WUEN; /**< Wake Up Enable */
<> 139:856d2700e60b 59
<> 139:856d2700e60b 60 RTCC_CC_TypeDef CC[3]; /**< Capture/Compare Channel */
<> 139:856d2700e60b 61
<> 139:856d2700e60b 62 uint32_t RESERVED0[37]; /**< Reserved registers */
<> 139:856d2700e60b 63 RTCC_RET_TypeDef RET[32]; /**< RetentionReg */
<> 139:856d2700e60b 64 } RTCC_TypeDef; /** @} */
<> 139:856d2700e60b 65
<> 139:856d2700e60b 66 /**************************************************************************//**
<> 139:856d2700e60b 67 * @defgroup EFM32PG12B_RTCC_BitFields
<> 139:856d2700e60b 68 * @{
<> 139:856d2700e60b 69 *****************************************************************************/
<> 139:856d2700e60b 70
<> 139:856d2700e60b 71 /* Bit fields for RTCC CTRL */
<> 139:856d2700e60b 72 #define _RTCC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CTRL */
<> 139:856d2700e60b 73 #define _RTCC_CTRL_MASK 0x00039F35UL /**< Mask for RTCC_CTRL */
<> 139:856d2700e60b 74 #define RTCC_CTRL_ENABLE (0x1UL << 0) /**< RTCC Enable */
<> 139:856d2700e60b 75 #define _RTCC_CTRL_ENABLE_SHIFT 0 /**< Shift value for RTCC_ENABLE */
<> 139:856d2700e60b 76 #define _RTCC_CTRL_ENABLE_MASK 0x1UL /**< Bit mask for RTCC_ENABLE */
<> 139:856d2700e60b 77 #define _RTCC_CTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
<> 139:856d2700e60b 78 #define RTCC_CTRL_ENABLE_DEFAULT (_RTCC_CTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CTRL */
<> 139:856d2700e60b 79 #define RTCC_CTRL_DEBUGRUN (0x1UL << 2) /**< Debug Mode Run Enable */
<> 139:856d2700e60b 80 #define _RTCC_CTRL_DEBUGRUN_SHIFT 2 /**< Shift value for RTCC_DEBUGRUN */
<> 139:856d2700e60b 81 #define _RTCC_CTRL_DEBUGRUN_MASK 0x4UL /**< Bit mask for RTCC_DEBUGRUN */
<> 139:856d2700e60b 82 #define _RTCC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
<> 139:856d2700e60b 83 #define RTCC_CTRL_DEBUGRUN_DEFAULT (_RTCC_CTRL_DEBUGRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CTRL */
<> 139:856d2700e60b 84 #define RTCC_CTRL_PRECCV0TOP (0x1UL << 4) /**< Pre-counter CCV0 top value enable. */
<> 139:856d2700e60b 85 #define _RTCC_CTRL_PRECCV0TOP_SHIFT 4 /**< Shift value for RTCC_PRECCV0TOP */
<> 139:856d2700e60b 86 #define _RTCC_CTRL_PRECCV0TOP_MASK 0x10UL /**< Bit mask for RTCC_PRECCV0TOP */
<> 139:856d2700e60b 87 #define _RTCC_CTRL_PRECCV0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
<> 139:856d2700e60b 88 #define RTCC_CTRL_PRECCV0TOP_DEFAULT (_RTCC_CTRL_PRECCV0TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CTRL */
<> 139:856d2700e60b 89 #define RTCC_CTRL_CCV1TOP (0x1UL << 5) /**< CCV1 top value enable */
<> 139:856d2700e60b 90 #define _RTCC_CTRL_CCV1TOP_SHIFT 5 /**< Shift value for RTCC_CCV1TOP */
<> 139:856d2700e60b 91 #define _RTCC_CTRL_CCV1TOP_MASK 0x20UL /**< Bit mask for RTCC_CCV1TOP */
<> 139:856d2700e60b 92 #define _RTCC_CTRL_CCV1TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
<> 139:856d2700e60b 93 #define RTCC_CTRL_CCV1TOP_DEFAULT (_RTCC_CTRL_CCV1TOP_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_CTRL */
<> 139:856d2700e60b 94 #define _RTCC_CTRL_CNTPRESC_SHIFT 8 /**< Shift value for RTCC_CNTPRESC */
<> 139:856d2700e60b 95 #define _RTCC_CTRL_CNTPRESC_MASK 0xF00UL /**< Bit mask for RTCC_CNTPRESC */
<> 139:856d2700e60b 96 #define _RTCC_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
<> 139:856d2700e60b 97 #define _RTCC_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for RTCC_CTRL */
<> 139:856d2700e60b 98 #define _RTCC_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for RTCC_CTRL */
<> 139:856d2700e60b 99 #define _RTCC_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for RTCC_CTRL */
<> 139:856d2700e60b 100 #define _RTCC_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for RTCC_CTRL */
<> 139:856d2700e60b 101 #define _RTCC_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for RTCC_CTRL */
<> 139:856d2700e60b 102 #define _RTCC_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for RTCC_CTRL */
<> 139:856d2700e60b 103 #define _RTCC_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for RTCC_CTRL */
<> 139:856d2700e60b 104 #define _RTCC_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for RTCC_CTRL */
<> 139:856d2700e60b 105 #define _RTCC_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for RTCC_CTRL */
<> 139:856d2700e60b 106 #define _RTCC_CTRL_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for RTCC_CTRL */
<> 139:856d2700e60b 107 #define _RTCC_CTRL_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for RTCC_CTRL */
<> 139:856d2700e60b 108 #define _RTCC_CTRL_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for RTCC_CTRL */
<> 139:856d2700e60b 109 #define _RTCC_CTRL_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for RTCC_CTRL */
<> 139:856d2700e60b 110 #define _RTCC_CTRL_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for RTCC_CTRL */
<> 139:856d2700e60b 111 #define _RTCC_CTRL_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for RTCC_CTRL */
<> 139:856d2700e60b 112 #define _RTCC_CTRL_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for RTCC_CTRL */
<> 139:856d2700e60b 113 #define RTCC_CTRL_CNTPRESC_DEFAULT (_RTCC_CTRL_CNTPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CTRL */
<> 139:856d2700e60b 114 #define RTCC_CTRL_CNTPRESC_DIV1 (_RTCC_CTRL_CNTPRESC_DIV1 << 8) /**< Shifted mode DIV1 for RTCC_CTRL */
<> 139:856d2700e60b 115 #define RTCC_CTRL_CNTPRESC_DIV2 (_RTCC_CTRL_CNTPRESC_DIV2 << 8) /**< Shifted mode DIV2 for RTCC_CTRL */
<> 139:856d2700e60b 116 #define RTCC_CTRL_CNTPRESC_DIV4 (_RTCC_CTRL_CNTPRESC_DIV4 << 8) /**< Shifted mode DIV4 for RTCC_CTRL */
<> 139:856d2700e60b 117 #define RTCC_CTRL_CNTPRESC_DIV8 (_RTCC_CTRL_CNTPRESC_DIV8 << 8) /**< Shifted mode DIV8 for RTCC_CTRL */
<> 139:856d2700e60b 118 #define RTCC_CTRL_CNTPRESC_DIV16 (_RTCC_CTRL_CNTPRESC_DIV16 << 8) /**< Shifted mode DIV16 for RTCC_CTRL */
<> 139:856d2700e60b 119 #define RTCC_CTRL_CNTPRESC_DIV32 (_RTCC_CTRL_CNTPRESC_DIV32 << 8) /**< Shifted mode DIV32 for RTCC_CTRL */
<> 139:856d2700e60b 120 #define RTCC_CTRL_CNTPRESC_DIV64 (_RTCC_CTRL_CNTPRESC_DIV64 << 8) /**< Shifted mode DIV64 for RTCC_CTRL */
<> 139:856d2700e60b 121 #define RTCC_CTRL_CNTPRESC_DIV128 (_RTCC_CTRL_CNTPRESC_DIV128 << 8) /**< Shifted mode DIV128 for RTCC_CTRL */
<> 139:856d2700e60b 122 #define RTCC_CTRL_CNTPRESC_DIV256 (_RTCC_CTRL_CNTPRESC_DIV256 << 8) /**< Shifted mode DIV256 for RTCC_CTRL */
<> 139:856d2700e60b 123 #define RTCC_CTRL_CNTPRESC_DIV512 (_RTCC_CTRL_CNTPRESC_DIV512 << 8) /**< Shifted mode DIV512 for RTCC_CTRL */
<> 139:856d2700e60b 124 #define RTCC_CTRL_CNTPRESC_DIV1024 (_RTCC_CTRL_CNTPRESC_DIV1024 << 8) /**< Shifted mode DIV1024 for RTCC_CTRL */
<> 139:856d2700e60b 125 #define RTCC_CTRL_CNTPRESC_DIV2048 (_RTCC_CTRL_CNTPRESC_DIV2048 << 8) /**< Shifted mode DIV2048 for RTCC_CTRL */
<> 139:856d2700e60b 126 #define RTCC_CTRL_CNTPRESC_DIV4096 (_RTCC_CTRL_CNTPRESC_DIV4096 << 8) /**< Shifted mode DIV4096 for RTCC_CTRL */
<> 139:856d2700e60b 127 #define RTCC_CTRL_CNTPRESC_DIV8192 (_RTCC_CTRL_CNTPRESC_DIV8192 << 8) /**< Shifted mode DIV8192 for RTCC_CTRL */
<> 139:856d2700e60b 128 #define RTCC_CTRL_CNTPRESC_DIV16384 (_RTCC_CTRL_CNTPRESC_DIV16384 << 8) /**< Shifted mode DIV16384 for RTCC_CTRL */
<> 139:856d2700e60b 129 #define RTCC_CTRL_CNTPRESC_DIV32768 (_RTCC_CTRL_CNTPRESC_DIV32768 << 8) /**< Shifted mode DIV32768 for RTCC_CTRL */
<> 139:856d2700e60b 130 #define RTCC_CTRL_CNTTICK (0x1UL << 12) /**< Counter prescaler mode. */
<> 139:856d2700e60b 131 #define _RTCC_CTRL_CNTTICK_SHIFT 12 /**< Shift value for RTCC_CNTTICK */
<> 139:856d2700e60b 132 #define _RTCC_CTRL_CNTTICK_MASK 0x1000UL /**< Bit mask for RTCC_CNTTICK */
<> 139:856d2700e60b 133 #define _RTCC_CTRL_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
<> 139:856d2700e60b 134 #define _RTCC_CTRL_CNTTICK_PRESC 0x00000000UL /**< Mode PRESC for RTCC_CTRL */
<> 139:856d2700e60b 135 #define _RTCC_CTRL_CNTTICK_CCV0MATCH 0x00000001UL /**< Mode CCV0MATCH for RTCC_CTRL */
<> 139:856d2700e60b 136 #define RTCC_CTRL_CNTTICK_DEFAULT (_RTCC_CTRL_CNTTICK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CTRL */
<> 139:856d2700e60b 137 #define RTCC_CTRL_CNTTICK_PRESC (_RTCC_CTRL_CNTTICK_PRESC << 12) /**< Shifted mode PRESC for RTCC_CTRL */
<> 139:856d2700e60b 138 #define RTCC_CTRL_CNTTICK_CCV0MATCH (_RTCC_CTRL_CNTTICK_CCV0MATCH << 12) /**< Shifted mode CCV0MATCH for RTCC_CTRL */
<> 139:856d2700e60b 139 #define RTCC_CTRL_OSCFDETEN (0x1UL << 15) /**< Oscillator failure detection enable */
<> 139:856d2700e60b 140 #define _RTCC_CTRL_OSCFDETEN_SHIFT 15 /**< Shift value for RTCC_OSCFDETEN */
<> 139:856d2700e60b 141 #define _RTCC_CTRL_OSCFDETEN_MASK 0x8000UL /**< Bit mask for RTCC_OSCFDETEN */
<> 139:856d2700e60b 142 #define _RTCC_CTRL_OSCFDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
<> 139:856d2700e60b 143 #define RTCC_CTRL_OSCFDETEN_DEFAULT (_RTCC_CTRL_OSCFDETEN_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_CTRL */
<> 139:856d2700e60b 144 #define RTCC_CTRL_CNTMODE (0x1UL << 16) /**< Main counter mode */
<> 139:856d2700e60b 145 #define _RTCC_CTRL_CNTMODE_SHIFT 16 /**< Shift value for RTCC_CNTMODE */
<> 139:856d2700e60b 146 #define _RTCC_CTRL_CNTMODE_MASK 0x10000UL /**< Bit mask for RTCC_CNTMODE */
<> 139:856d2700e60b 147 #define _RTCC_CTRL_CNTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
<> 139:856d2700e60b 148 #define _RTCC_CTRL_CNTMODE_NORMAL 0x00000000UL /**< Mode NORMAL for RTCC_CTRL */
<> 139:856d2700e60b 149 #define _RTCC_CTRL_CNTMODE_CALENDAR 0x00000001UL /**< Mode CALENDAR for RTCC_CTRL */
<> 139:856d2700e60b 150 #define RTCC_CTRL_CNTMODE_DEFAULT (_RTCC_CTRL_CNTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CTRL */
<> 139:856d2700e60b 151 #define RTCC_CTRL_CNTMODE_NORMAL (_RTCC_CTRL_CNTMODE_NORMAL << 16) /**< Shifted mode NORMAL for RTCC_CTRL */
<> 139:856d2700e60b 152 #define RTCC_CTRL_CNTMODE_CALENDAR (_RTCC_CTRL_CNTMODE_CALENDAR << 16) /**< Shifted mode CALENDAR for RTCC_CTRL */
<> 139:856d2700e60b 153 #define RTCC_CTRL_LYEARCORRDIS (0x1UL << 17) /**< Leap year correction disabled. */
<> 139:856d2700e60b 154 #define _RTCC_CTRL_LYEARCORRDIS_SHIFT 17 /**< Shift value for RTCC_LYEARCORRDIS */
<> 139:856d2700e60b 155 #define _RTCC_CTRL_LYEARCORRDIS_MASK 0x20000UL /**< Bit mask for RTCC_LYEARCORRDIS */
<> 139:856d2700e60b 156 #define _RTCC_CTRL_LYEARCORRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
<> 139:856d2700e60b 157 #define RTCC_CTRL_LYEARCORRDIS_DEFAULT (_RTCC_CTRL_LYEARCORRDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CTRL */
<> 139:856d2700e60b 158
<> 139:856d2700e60b 159 /* Bit fields for RTCC PRECNT */
<> 139:856d2700e60b 160 #define _RTCC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_PRECNT */
<> 139:856d2700e60b 161 #define _RTCC_PRECNT_MASK 0x00007FFFUL /**< Mask for RTCC_PRECNT */
<> 139:856d2700e60b 162 #define _RTCC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */
<> 139:856d2700e60b 163 #define _RTCC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */
<> 139:856d2700e60b 164 #define _RTCC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_PRECNT */
<> 139:856d2700e60b 165 #define RTCC_PRECNT_PRECNT_DEFAULT (_RTCC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_PRECNT */
<> 139:856d2700e60b 166
<> 139:856d2700e60b 167 /* Bit fields for RTCC CNT */
<> 139:856d2700e60b 168 #define _RTCC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_CNT */
<> 139:856d2700e60b 169 #define _RTCC_CNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CNT */
<> 139:856d2700e60b 170 #define _RTCC_CNT_CNT_SHIFT 0 /**< Shift value for RTCC_CNT */
<> 139:856d2700e60b 171 #define _RTCC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_CNT */
<> 139:856d2700e60b 172 #define _RTCC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CNT */
<> 139:856d2700e60b 173 #define RTCC_CNT_CNT_DEFAULT (_RTCC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CNT */
<> 139:856d2700e60b 174
<> 139:856d2700e60b 175 /* Bit fields for RTCC COMBCNT */
<> 139:856d2700e60b 176 #define _RTCC_COMBCNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_COMBCNT */
<> 139:856d2700e60b 177 #define _RTCC_COMBCNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_COMBCNT */
<> 139:856d2700e60b 178 #define _RTCC_COMBCNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */
<> 139:856d2700e60b 179 #define _RTCC_COMBCNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */
<> 139:856d2700e60b 180 #define _RTCC_COMBCNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */
<> 139:856d2700e60b 181 #define RTCC_COMBCNT_PRECNT_DEFAULT (_RTCC_COMBCNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_COMBCNT */
<> 139:856d2700e60b 182 #define _RTCC_COMBCNT_CNTLSB_SHIFT 15 /**< Shift value for RTCC_CNTLSB */
<> 139:856d2700e60b 183 #define _RTCC_COMBCNT_CNTLSB_MASK 0xFFFF8000UL /**< Bit mask for RTCC_CNTLSB */
<> 139:856d2700e60b 184 #define _RTCC_COMBCNT_CNTLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */
<> 139:856d2700e60b 185 #define RTCC_COMBCNT_CNTLSB_DEFAULT (_RTCC_COMBCNT_CNTLSB_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_COMBCNT */
<> 139:856d2700e60b 186
<> 139:856d2700e60b 187 /* Bit fields for RTCC TIME */
<> 139:856d2700e60b 188 #define _RTCC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_TIME */
<> 139:856d2700e60b 189 #define _RTCC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_TIME */
<> 139:856d2700e60b 190 #define _RTCC_TIME_SECU_SHIFT 0 /**< Shift value for RTCC_SECU */
<> 139:856d2700e60b 191 #define _RTCC_TIME_SECU_MASK 0xFUL /**< Bit mask for RTCC_SECU */
<> 139:856d2700e60b 192 #define _RTCC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
<> 139:856d2700e60b 193 #define RTCC_TIME_SECU_DEFAULT (_RTCC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_TIME */
<> 139:856d2700e60b 194 #define _RTCC_TIME_SECT_SHIFT 4 /**< Shift value for RTCC_SECT */
<> 139:856d2700e60b 195 #define _RTCC_TIME_SECT_MASK 0x70UL /**< Bit mask for RTCC_SECT */
<> 139:856d2700e60b 196 #define _RTCC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
<> 139:856d2700e60b 197 #define RTCC_TIME_SECT_DEFAULT (_RTCC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_TIME */
<> 139:856d2700e60b 198 #define _RTCC_TIME_MINU_SHIFT 8 /**< Shift value for RTCC_MINU */
<> 139:856d2700e60b 199 #define _RTCC_TIME_MINU_MASK 0xF00UL /**< Bit mask for RTCC_MINU */
<> 139:856d2700e60b 200 #define _RTCC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
<> 139:856d2700e60b 201 #define RTCC_TIME_MINU_DEFAULT (_RTCC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_TIME */
<> 139:856d2700e60b 202 #define _RTCC_TIME_MINT_SHIFT 12 /**< Shift value for RTCC_MINT */
<> 139:856d2700e60b 203 #define _RTCC_TIME_MINT_MASK 0x7000UL /**< Bit mask for RTCC_MINT */
<> 139:856d2700e60b 204 #define _RTCC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
<> 139:856d2700e60b 205 #define RTCC_TIME_MINT_DEFAULT (_RTCC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_TIME */
<> 139:856d2700e60b 206 #define _RTCC_TIME_HOURU_SHIFT 16 /**< Shift value for RTCC_HOURU */
<> 139:856d2700e60b 207 #define _RTCC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for RTCC_HOURU */
<> 139:856d2700e60b 208 #define _RTCC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
<> 139:856d2700e60b 209 #define RTCC_TIME_HOURU_DEFAULT (_RTCC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_TIME */
<> 139:856d2700e60b 210 #define _RTCC_TIME_HOURT_SHIFT 20 /**< Shift value for RTCC_HOURT */
<> 139:856d2700e60b 211 #define _RTCC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for RTCC_HOURT */
<> 139:856d2700e60b 212 #define _RTCC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
<> 139:856d2700e60b 213 #define RTCC_TIME_HOURT_DEFAULT (_RTCC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_TIME */
<> 139:856d2700e60b 214
<> 139:856d2700e60b 215 /* Bit fields for RTCC DATE */
<> 139:856d2700e60b 216 #define _RTCC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_DATE */
<> 139:856d2700e60b 217 #define _RTCC_DATE_MASK 0x07FF1F3FUL /**< Mask for RTCC_DATE */
<> 139:856d2700e60b 218 #define _RTCC_DATE_DAYOMU_SHIFT 0 /**< Shift value for RTCC_DAYOMU */
<> 139:856d2700e60b 219 #define _RTCC_DATE_DAYOMU_MASK 0xFUL /**< Bit mask for RTCC_DAYOMU */
<> 139:856d2700e60b 220 #define _RTCC_DATE_DAYOMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
<> 139:856d2700e60b 221 #define RTCC_DATE_DAYOMU_DEFAULT (_RTCC_DATE_DAYOMU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_DATE */
<> 139:856d2700e60b 222 #define _RTCC_DATE_DAYOMT_SHIFT 4 /**< Shift value for RTCC_DAYOMT */
<> 139:856d2700e60b 223 #define _RTCC_DATE_DAYOMT_MASK 0x30UL /**< Bit mask for RTCC_DAYOMT */
<> 139:856d2700e60b 224 #define _RTCC_DATE_DAYOMT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
<> 139:856d2700e60b 225 #define RTCC_DATE_DAYOMT_DEFAULT (_RTCC_DATE_DAYOMT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_DATE */
<> 139:856d2700e60b 226 #define _RTCC_DATE_MONTHU_SHIFT 8 /**< Shift value for RTCC_MONTHU */
<> 139:856d2700e60b 227 #define _RTCC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for RTCC_MONTHU */
<> 139:856d2700e60b 228 #define _RTCC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
<> 139:856d2700e60b 229 #define RTCC_DATE_MONTHU_DEFAULT (_RTCC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_DATE */
<> 139:856d2700e60b 230 #define RTCC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */
<> 139:856d2700e60b 231 #define _RTCC_DATE_MONTHT_SHIFT 12 /**< Shift value for RTCC_MONTHT */
<> 139:856d2700e60b 232 #define _RTCC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for RTCC_MONTHT */
<> 139:856d2700e60b 233 #define _RTCC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
<> 139:856d2700e60b 234 #define RTCC_DATE_MONTHT_DEFAULT (_RTCC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_DATE */
<> 139:856d2700e60b 235 #define _RTCC_DATE_YEARU_SHIFT 16 /**< Shift value for RTCC_YEARU */
<> 139:856d2700e60b 236 #define _RTCC_DATE_YEARU_MASK 0xF0000UL /**< Bit mask for RTCC_YEARU */
<> 139:856d2700e60b 237 #define _RTCC_DATE_YEARU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
<> 139:856d2700e60b 238 #define RTCC_DATE_YEARU_DEFAULT (_RTCC_DATE_YEARU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_DATE */
<> 139:856d2700e60b 239 #define _RTCC_DATE_YEART_SHIFT 20 /**< Shift value for RTCC_YEART */
<> 139:856d2700e60b 240 #define _RTCC_DATE_YEART_MASK 0xF00000UL /**< Bit mask for RTCC_YEART */
<> 139:856d2700e60b 241 #define _RTCC_DATE_YEART_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
<> 139:856d2700e60b 242 #define RTCC_DATE_YEART_DEFAULT (_RTCC_DATE_YEART_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_DATE */
<> 139:856d2700e60b 243 #define _RTCC_DATE_DAYOW_SHIFT 24 /**< Shift value for RTCC_DAYOW */
<> 139:856d2700e60b 244 #define _RTCC_DATE_DAYOW_MASK 0x7000000UL /**< Bit mask for RTCC_DAYOW */
<> 139:856d2700e60b 245 #define _RTCC_DATE_DAYOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
<> 139:856d2700e60b 246 #define RTCC_DATE_DAYOW_DEFAULT (_RTCC_DATE_DAYOW_DEFAULT << 24) /**< Shifted mode DEFAULT for RTCC_DATE */
<> 139:856d2700e60b 247
<> 139:856d2700e60b 248 /* Bit fields for RTCC IF */
<> 139:856d2700e60b 249 #define _RTCC_IF_RESETVALUE 0x00000000UL /**< Default value for RTCC_IF */
<> 139:856d2700e60b 250 #define _RTCC_IF_MASK 0x000007FFUL /**< Mask for RTCC_IF */
<> 139:856d2700e60b 251 #define RTCC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
<> 139:856d2700e60b 252 #define _RTCC_IF_OF_SHIFT 0 /**< Shift value for RTCC_OF */
<> 139:856d2700e60b 253 #define _RTCC_IF_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */
<> 139:856d2700e60b 254 #define _RTCC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 255 #define RTCC_IF_OF_DEFAULT (_RTCC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 256 #define RTCC_IF_CC0 (0x1UL << 1) /**< Channel 0 Interrupt Flag */
<> 139:856d2700e60b 257 #define _RTCC_IF_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */
<> 139:856d2700e60b 258 #define _RTCC_IF_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */
<> 139:856d2700e60b 259 #define _RTCC_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 260 #define RTCC_IF_CC0_DEFAULT (_RTCC_IF_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 261 #define RTCC_IF_CC1 (0x1UL << 2) /**< Channel 1 Interrupt Flag */
<> 139:856d2700e60b 262 #define _RTCC_IF_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */
<> 139:856d2700e60b 263 #define _RTCC_IF_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */
<> 139:856d2700e60b 264 #define _RTCC_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 265 #define RTCC_IF_CC1_DEFAULT (_RTCC_IF_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 266 #define RTCC_IF_CC2 (0x1UL << 3) /**< Channel 2 Interrupt Flag */
<> 139:856d2700e60b 267 #define _RTCC_IF_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */
<> 139:856d2700e60b 268 #define _RTCC_IF_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
<> 139:856d2700e60b 269 #define _RTCC_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 270 #define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 271 #define RTCC_IF_OSCFAIL (0x1UL << 4) /**< Oscillator failure Interrupt Flag */
<> 139:856d2700e60b 272 #define _RTCC_IF_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
<> 139:856d2700e60b 273 #define _RTCC_IF_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
<> 139:856d2700e60b 274 #define _RTCC_IF_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 275 #define RTCC_IF_OSCFAIL_DEFAULT (_RTCC_IF_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 276 #define RTCC_IF_CNTTICK (0x1UL << 5) /**< Main counter tick */
<> 139:856d2700e60b 277 #define _RTCC_IF_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
<> 139:856d2700e60b 278 #define _RTCC_IF_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
<> 139:856d2700e60b 279 #define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 280 #define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 281 #define RTCC_IF_MINTICK (0x1UL << 6) /**< Minute tick */
<> 139:856d2700e60b 282 #define _RTCC_IF_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
<> 139:856d2700e60b 283 #define _RTCC_IF_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
<> 139:856d2700e60b 284 #define _RTCC_IF_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 285 #define RTCC_IF_MINTICK_DEFAULT (_RTCC_IF_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 286 #define RTCC_IF_HOURTICK (0x1UL << 7) /**< Hour tick */
<> 139:856d2700e60b 287 #define _RTCC_IF_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
<> 139:856d2700e60b 288 #define _RTCC_IF_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
<> 139:856d2700e60b 289 #define _RTCC_IF_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 290 #define RTCC_IF_HOURTICK_DEFAULT (_RTCC_IF_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 291 #define RTCC_IF_DAYTICK (0x1UL << 8) /**< Day tick */
<> 139:856d2700e60b 292 #define _RTCC_IF_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
<> 139:856d2700e60b 293 #define _RTCC_IF_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
<> 139:856d2700e60b 294 #define _RTCC_IF_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 295 #define RTCC_IF_DAYTICK_DEFAULT (_RTCC_IF_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 296 #define RTCC_IF_DAYOWOF (0x1UL << 9) /**< Day of week overflow */
<> 139:856d2700e60b 297 #define _RTCC_IF_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
<> 139:856d2700e60b 298 #define _RTCC_IF_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
<> 139:856d2700e60b 299 #define _RTCC_IF_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 300 #define RTCC_IF_DAYOWOF_DEFAULT (_RTCC_IF_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 301 #define RTCC_IF_MONTHTICK (0x1UL << 10) /**< Month tick */
<> 139:856d2700e60b 302 #define _RTCC_IF_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
<> 139:856d2700e60b 303 #define _RTCC_IF_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
<> 139:856d2700e60b 304 #define _RTCC_IF_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 305 #define RTCC_IF_MONTHTICK_DEFAULT (_RTCC_IF_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IF */
<> 139:856d2700e60b 306
<> 139:856d2700e60b 307 /* Bit fields for RTCC IFS */
<> 139:856d2700e60b 308 #define _RTCC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFS */
<> 139:856d2700e60b 309 #define _RTCC_IFS_MASK 0x000007FFUL /**< Mask for RTCC_IFS */
<> 139:856d2700e60b 310 #define RTCC_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */
<> 139:856d2700e60b 311 #define _RTCC_IFS_OF_SHIFT 0 /**< Shift value for RTCC_OF */
<> 139:856d2700e60b 312 #define _RTCC_IFS_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */
<> 139:856d2700e60b 313 #define _RTCC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 314 #define RTCC_IFS_OF_DEFAULT (_RTCC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 315 #define RTCC_IFS_CC0 (0x1UL << 1) /**< Set CC0 Interrupt Flag */
<> 139:856d2700e60b 316 #define _RTCC_IFS_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */
<> 139:856d2700e60b 317 #define _RTCC_IFS_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */
<> 139:856d2700e60b 318 #define _RTCC_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 319 #define RTCC_IFS_CC0_DEFAULT (_RTCC_IFS_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 320 #define RTCC_IFS_CC1 (0x1UL << 2) /**< Set CC1 Interrupt Flag */
<> 139:856d2700e60b 321 #define _RTCC_IFS_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */
<> 139:856d2700e60b 322 #define _RTCC_IFS_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */
<> 139:856d2700e60b 323 #define _RTCC_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 324 #define RTCC_IFS_CC1_DEFAULT (_RTCC_IFS_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 325 #define RTCC_IFS_CC2 (0x1UL << 3) /**< Set CC2 Interrupt Flag */
<> 139:856d2700e60b 326 #define _RTCC_IFS_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */
<> 139:856d2700e60b 327 #define _RTCC_IFS_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
<> 139:856d2700e60b 328 #define _RTCC_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 329 #define RTCC_IFS_CC2_DEFAULT (_RTCC_IFS_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 330 #define RTCC_IFS_OSCFAIL (0x1UL << 4) /**< Set OSCFAIL Interrupt Flag */
<> 139:856d2700e60b 331 #define _RTCC_IFS_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
<> 139:856d2700e60b 332 #define _RTCC_IFS_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
<> 139:856d2700e60b 333 #define _RTCC_IFS_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 334 #define RTCC_IFS_OSCFAIL_DEFAULT (_RTCC_IFS_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 335 #define RTCC_IFS_CNTTICK (0x1UL << 5) /**< Set CNTTICK Interrupt Flag */
<> 139:856d2700e60b 336 #define _RTCC_IFS_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
<> 139:856d2700e60b 337 #define _RTCC_IFS_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
<> 139:856d2700e60b 338 #define _RTCC_IFS_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 339 #define RTCC_IFS_CNTTICK_DEFAULT (_RTCC_IFS_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 340 #define RTCC_IFS_MINTICK (0x1UL << 6) /**< Set MINTICK Interrupt Flag */
<> 139:856d2700e60b 341 #define _RTCC_IFS_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
<> 139:856d2700e60b 342 #define _RTCC_IFS_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
<> 139:856d2700e60b 343 #define _RTCC_IFS_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 344 #define RTCC_IFS_MINTICK_DEFAULT (_RTCC_IFS_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 345 #define RTCC_IFS_HOURTICK (0x1UL << 7) /**< Set HOURTICK Interrupt Flag */
<> 139:856d2700e60b 346 #define _RTCC_IFS_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
<> 139:856d2700e60b 347 #define _RTCC_IFS_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
<> 139:856d2700e60b 348 #define _RTCC_IFS_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 349 #define RTCC_IFS_HOURTICK_DEFAULT (_RTCC_IFS_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 350 #define RTCC_IFS_DAYTICK (0x1UL << 8) /**< Set DAYTICK Interrupt Flag */
<> 139:856d2700e60b 351 #define _RTCC_IFS_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
<> 139:856d2700e60b 352 #define _RTCC_IFS_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
<> 139:856d2700e60b 353 #define _RTCC_IFS_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 354 #define RTCC_IFS_DAYTICK_DEFAULT (_RTCC_IFS_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 355 #define RTCC_IFS_DAYOWOF (0x1UL << 9) /**< Set DAYOWOF Interrupt Flag */
<> 139:856d2700e60b 356 #define _RTCC_IFS_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
<> 139:856d2700e60b 357 #define _RTCC_IFS_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
<> 139:856d2700e60b 358 #define _RTCC_IFS_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 359 #define RTCC_IFS_DAYOWOF_DEFAULT (_RTCC_IFS_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 360 #define RTCC_IFS_MONTHTICK (0x1UL << 10) /**< Set MONTHTICK Interrupt Flag */
<> 139:856d2700e60b 361 #define _RTCC_IFS_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
<> 139:856d2700e60b 362 #define _RTCC_IFS_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
<> 139:856d2700e60b 363 #define _RTCC_IFS_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 364 #define RTCC_IFS_MONTHTICK_DEFAULT (_RTCC_IFS_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFS */
<> 139:856d2700e60b 365
<> 139:856d2700e60b 366 /* Bit fields for RTCC IFC */
<> 139:856d2700e60b 367 #define _RTCC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFC */
<> 139:856d2700e60b 368 #define _RTCC_IFC_MASK 0x000007FFUL /**< Mask for RTCC_IFC */
<> 139:856d2700e60b 369 #define RTCC_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */
<> 139:856d2700e60b 370 #define _RTCC_IFC_OF_SHIFT 0 /**< Shift value for RTCC_OF */
<> 139:856d2700e60b 371 #define _RTCC_IFC_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */
<> 139:856d2700e60b 372 #define _RTCC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 373 #define RTCC_IFC_OF_DEFAULT (_RTCC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 374 #define RTCC_IFC_CC0 (0x1UL << 1) /**< Clear CC0 Interrupt Flag */
<> 139:856d2700e60b 375 #define _RTCC_IFC_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */
<> 139:856d2700e60b 376 #define _RTCC_IFC_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */
<> 139:856d2700e60b 377 #define _RTCC_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 378 #define RTCC_IFC_CC0_DEFAULT (_RTCC_IFC_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 379 #define RTCC_IFC_CC1 (0x1UL << 2) /**< Clear CC1 Interrupt Flag */
<> 139:856d2700e60b 380 #define _RTCC_IFC_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */
<> 139:856d2700e60b 381 #define _RTCC_IFC_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */
<> 139:856d2700e60b 382 #define _RTCC_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 383 #define RTCC_IFC_CC1_DEFAULT (_RTCC_IFC_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 384 #define RTCC_IFC_CC2 (0x1UL << 3) /**< Clear CC2 Interrupt Flag */
<> 139:856d2700e60b 385 #define _RTCC_IFC_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */
<> 139:856d2700e60b 386 #define _RTCC_IFC_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
<> 139:856d2700e60b 387 #define _RTCC_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 388 #define RTCC_IFC_CC2_DEFAULT (_RTCC_IFC_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 389 #define RTCC_IFC_OSCFAIL (0x1UL << 4) /**< Clear OSCFAIL Interrupt Flag */
<> 139:856d2700e60b 390 #define _RTCC_IFC_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
<> 139:856d2700e60b 391 #define _RTCC_IFC_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
<> 139:856d2700e60b 392 #define _RTCC_IFC_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 393 #define RTCC_IFC_OSCFAIL_DEFAULT (_RTCC_IFC_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 394 #define RTCC_IFC_CNTTICK (0x1UL << 5) /**< Clear CNTTICK Interrupt Flag */
<> 139:856d2700e60b 395 #define _RTCC_IFC_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
<> 139:856d2700e60b 396 #define _RTCC_IFC_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
<> 139:856d2700e60b 397 #define _RTCC_IFC_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 398 #define RTCC_IFC_CNTTICK_DEFAULT (_RTCC_IFC_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 399 #define RTCC_IFC_MINTICK (0x1UL << 6) /**< Clear MINTICK Interrupt Flag */
<> 139:856d2700e60b 400 #define _RTCC_IFC_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
<> 139:856d2700e60b 401 #define _RTCC_IFC_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
<> 139:856d2700e60b 402 #define _RTCC_IFC_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 403 #define RTCC_IFC_MINTICK_DEFAULT (_RTCC_IFC_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 404 #define RTCC_IFC_HOURTICK (0x1UL << 7) /**< Clear HOURTICK Interrupt Flag */
<> 139:856d2700e60b 405 #define _RTCC_IFC_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
<> 139:856d2700e60b 406 #define _RTCC_IFC_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
<> 139:856d2700e60b 407 #define _RTCC_IFC_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 408 #define RTCC_IFC_HOURTICK_DEFAULT (_RTCC_IFC_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 409 #define RTCC_IFC_DAYTICK (0x1UL << 8) /**< Clear DAYTICK Interrupt Flag */
<> 139:856d2700e60b 410 #define _RTCC_IFC_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
<> 139:856d2700e60b 411 #define _RTCC_IFC_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
<> 139:856d2700e60b 412 #define _RTCC_IFC_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 413 #define RTCC_IFC_DAYTICK_DEFAULT (_RTCC_IFC_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 414 #define RTCC_IFC_DAYOWOF (0x1UL << 9) /**< Clear DAYOWOF Interrupt Flag */
<> 139:856d2700e60b 415 #define _RTCC_IFC_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
<> 139:856d2700e60b 416 #define _RTCC_IFC_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
<> 139:856d2700e60b 417 #define _RTCC_IFC_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 418 #define RTCC_IFC_DAYOWOF_DEFAULT (_RTCC_IFC_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 419 #define RTCC_IFC_MONTHTICK (0x1UL << 10) /**< Clear MONTHTICK Interrupt Flag */
<> 139:856d2700e60b 420 #define _RTCC_IFC_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
<> 139:856d2700e60b 421 #define _RTCC_IFC_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
<> 139:856d2700e60b 422 #define _RTCC_IFC_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 423 #define RTCC_IFC_MONTHTICK_DEFAULT (_RTCC_IFC_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFC */
<> 139:856d2700e60b 424
<> 139:856d2700e60b 425 /* Bit fields for RTCC IEN */
<> 139:856d2700e60b 426 #define _RTCC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_IEN */
<> 139:856d2700e60b 427 #define _RTCC_IEN_MASK 0x000007FFUL /**< Mask for RTCC_IEN */
<> 139:856d2700e60b 428 #define RTCC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */
<> 139:856d2700e60b 429 #define _RTCC_IEN_OF_SHIFT 0 /**< Shift value for RTCC_OF */
<> 139:856d2700e60b 430 #define _RTCC_IEN_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */
<> 139:856d2700e60b 431 #define _RTCC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 432 #define RTCC_IEN_OF_DEFAULT (_RTCC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 433 #define RTCC_IEN_CC0 (0x1UL << 1) /**< CC0 Interrupt Enable */
<> 139:856d2700e60b 434 #define _RTCC_IEN_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */
<> 139:856d2700e60b 435 #define _RTCC_IEN_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */
<> 139:856d2700e60b 436 #define _RTCC_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 437 #define RTCC_IEN_CC0_DEFAULT (_RTCC_IEN_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 438 #define RTCC_IEN_CC1 (0x1UL << 2) /**< CC1 Interrupt Enable */
<> 139:856d2700e60b 439 #define _RTCC_IEN_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */
<> 139:856d2700e60b 440 #define _RTCC_IEN_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */
<> 139:856d2700e60b 441 #define _RTCC_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 442 #define RTCC_IEN_CC1_DEFAULT (_RTCC_IEN_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 443 #define RTCC_IEN_CC2 (0x1UL << 3) /**< CC2 Interrupt Enable */
<> 139:856d2700e60b 444 #define _RTCC_IEN_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */
<> 139:856d2700e60b 445 #define _RTCC_IEN_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
<> 139:856d2700e60b 446 #define _RTCC_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 447 #define RTCC_IEN_CC2_DEFAULT (_RTCC_IEN_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 448 #define RTCC_IEN_OSCFAIL (0x1UL << 4) /**< OSCFAIL Interrupt Enable */
<> 139:856d2700e60b 449 #define _RTCC_IEN_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
<> 139:856d2700e60b 450 #define _RTCC_IEN_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
<> 139:856d2700e60b 451 #define _RTCC_IEN_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 452 #define RTCC_IEN_OSCFAIL_DEFAULT (_RTCC_IEN_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 453 #define RTCC_IEN_CNTTICK (0x1UL << 5) /**< CNTTICK Interrupt Enable */
<> 139:856d2700e60b 454 #define _RTCC_IEN_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
<> 139:856d2700e60b 455 #define _RTCC_IEN_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
<> 139:856d2700e60b 456 #define _RTCC_IEN_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 457 #define RTCC_IEN_CNTTICK_DEFAULT (_RTCC_IEN_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 458 #define RTCC_IEN_MINTICK (0x1UL << 6) /**< MINTICK Interrupt Enable */
<> 139:856d2700e60b 459 #define _RTCC_IEN_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
<> 139:856d2700e60b 460 #define _RTCC_IEN_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
<> 139:856d2700e60b 461 #define _RTCC_IEN_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 462 #define RTCC_IEN_MINTICK_DEFAULT (_RTCC_IEN_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 463 #define RTCC_IEN_HOURTICK (0x1UL << 7) /**< HOURTICK Interrupt Enable */
<> 139:856d2700e60b 464 #define _RTCC_IEN_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
<> 139:856d2700e60b 465 #define _RTCC_IEN_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
<> 139:856d2700e60b 466 #define _RTCC_IEN_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 467 #define RTCC_IEN_HOURTICK_DEFAULT (_RTCC_IEN_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 468 #define RTCC_IEN_DAYTICK (0x1UL << 8) /**< DAYTICK Interrupt Enable */
<> 139:856d2700e60b 469 #define _RTCC_IEN_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
<> 139:856d2700e60b 470 #define _RTCC_IEN_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
<> 139:856d2700e60b 471 #define _RTCC_IEN_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 472 #define RTCC_IEN_DAYTICK_DEFAULT (_RTCC_IEN_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 473 #define RTCC_IEN_DAYOWOF (0x1UL << 9) /**< DAYOWOF Interrupt Enable */
<> 139:856d2700e60b 474 #define _RTCC_IEN_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
<> 139:856d2700e60b 475 #define _RTCC_IEN_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
<> 139:856d2700e60b 476 #define _RTCC_IEN_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 477 #define RTCC_IEN_DAYOWOF_DEFAULT (_RTCC_IEN_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 478 #define RTCC_IEN_MONTHTICK (0x1UL << 10) /**< MONTHTICK Interrupt Enable */
<> 139:856d2700e60b 479 #define _RTCC_IEN_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
<> 139:856d2700e60b 480 #define _RTCC_IEN_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
<> 139:856d2700e60b 481 #define _RTCC_IEN_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 482 #define RTCC_IEN_MONTHTICK_DEFAULT (_RTCC_IEN_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IEN */
<> 139:856d2700e60b 483
<> 139:856d2700e60b 484 /* Bit fields for RTCC STATUS */
<> 139:856d2700e60b 485 #define _RTCC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RTCC_STATUS */
<> 139:856d2700e60b 486 #define _RTCC_STATUS_MASK 0x00000000UL /**< Mask for RTCC_STATUS */
<> 139:856d2700e60b 487
<> 139:856d2700e60b 488 /* Bit fields for RTCC CMD */
<> 139:856d2700e60b 489 #define _RTCC_CMD_RESETVALUE 0x00000000UL /**< Default value for RTCC_CMD */
<> 139:856d2700e60b 490 #define _RTCC_CMD_MASK 0x00000001UL /**< Mask for RTCC_CMD */
<> 139:856d2700e60b 491 #define RTCC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear RTCC_STATUS register. */
<> 139:856d2700e60b 492 #define _RTCC_CMD_CLRSTATUS_SHIFT 0 /**< Shift value for RTCC_CLRSTATUS */
<> 139:856d2700e60b 493 #define _RTCC_CMD_CLRSTATUS_MASK 0x1UL /**< Bit mask for RTCC_CLRSTATUS */
<> 139:856d2700e60b 494 #define _RTCC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */
<> 139:856d2700e60b 495 #define RTCC_CMD_CLRSTATUS_DEFAULT (_RTCC_CMD_CLRSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CMD */
<> 139:856d2700e60b 496
<> 139:856d2700e60b 497 /* Bit fields for RTCC SYNCBUSY */
<> 139:856d2700e60b 498 #define _RTCC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTCC_SYNCBUSY */
<> 139:856d2700e60b 499 #define _RTCC_SYNCBUSY_MASK 0x00000020UL /**< Mask for RTCC_SYNCBUSY */
<> 139:856d2700e60b 500 #define RTCC_SYNCBUSY_CMD (0x1UL << 5) /**< CMD Register Busy */
<> 139:856d2700e60b 501 #define _RTCC_SYNCBUSY_CMD_SHIFT 5 /**< Shift value for RTCC_CMD */
<> 139:856d2700e60b 502 #define _RTCC_SYNCBUSY_CMD_MASK 0x20UL /**< Bit mask for RTCC_CMD */
<> 139:856d2700e60b 503 #define _RTCC_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */
<> 139:856d2700e60b 504 #define RTCC_SYNCBUSY_CMD_DEFAULT (_RTCC_SYNCBUSY_CMD_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */
<> 139:856d2700e60b 505
<> 139:856d2700e60b 506 /* Bit fields for RTCC POWERDOWN */
<> 139:856d2700e60b 507 #define _RTCC_POWERDOWN_RESETVALUE 0x00000000UL /**< Default value for RTCC_POWERDOWN */
<> 139:856d2700e60b 508 #define _RTCC_POWERDOWN_MASK 0x00000001UL /**< Mask for RTCC_POWERDOWN */
<> 139:856d2700e60b 509 #define RTCC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM power-down */
<> 139:856d2700e60b 510 #define _RTCC_POWERDOWN_RAM_SHIFT 0 /**< Shift value for RTCC_RAM */
<> 139:856d2700e60b 511 #define _RTCC_POWERDOWN_RAM_MASK 0x1UL /**< Bit mask for RTCC_RAM */
<> 139:856d2700e60b 512 #define _RTCC_POWERDOWN_RAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_POWERDOWN */
<> 139:856d2700e60b 513 #define RTCC_POWERDOWN_RAM_DEFAULT (_RTCC_POWERDOWN_RAM_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_POWERDOWN */
<> 139:856d2700e60b 514
<> 139:856d2700e60b 515 /* Bit fields for RTCC LOCK */
<> 139:856d2700e60b 516 #define _RTCC_LOCK_RESETVALUE 0x00000000UL /**< Default value for RTCC_LOCK */
<> 139:856d2700e60b 517 #define _RTCC_LOCK_MASK 0x0000FFFFUL /**< Mask for RTCC_LOCK */
<> 139:856d2700e60b 518 #define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */
<> 139:856d2700e60b 519 #define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */
<> 139:856d2700e60b 520 #define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */
<> 139:856d2700e60b 521 #define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */
<> 139:856d2700e60b 522 #define _RTCC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_LOCK */
<> 139:856d2700e60b 523 #define _RTCC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_LOCK */
<> 139:856d2700e60b 524 #define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */
<> 139:856d2700e60b 525 #define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */
<> 139:856d2700e60b 526 #define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */
<> 139:856d2700e60b 527 #define RTCC_LOCK_LOCKKEY_UNLOCKED (_RTCC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RTCC_LOCK */
<> 139:856d2700e60b 528 #define RTCC_LOCK_LOCKKEY_LOCKED (_RTCC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RTCC_LOCK */
<> 139:856d2700e60b 529 #define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */
<> 139:856d2700e60b 530
<> 139:856d2700e60b 531 /* Bit fields for RTCC EM4WUEN */
<> 139:856d2700e60b 532 #define _RTCC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_EM4WUEN */
<> 139:856d2700e60b 533 #define _RTCC_EM4WUEN_MASK 0x00000001UL /**< Mask for RTCC_EM4WUEN */
<> 139:856d2700e60b 534 #define RTCC_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up enable */
<> 139:856d2700e60b 535 #define _RTCC_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for RTCC_EM4WU */
<> 139:856d2700e60b 536 #define _RTCC_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for RTCC_EM4WU */
<> 139:856d2700e60b 537 #define _RTCC_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_EM4WUEN */
<> 139:856d2700e60b 538 #define RTCC_EM4WUEN_EM4WU_DEFAULT (_RTCC_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_EM4WUEN */
<> 139:856d2700e60b 539
<> 139:856d2700e60b 540 /* Bit fields for RTCC CC_CTRL */
<> 139:856d2700e60b 541 #define _RTCC_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CTRL */
<> 139:856d2700e60b 542 #define _RTCC_CC_CTRL_MASK 0x0003FBFFUL /**< Mask for RTCC_CC_CTRL */
<> 139:856d2700e60b 543 #define _RTCC_CC_CTRL_MODE_SHIFT 0 /**< Shift value for CC_MODE */
<> 139:856d2700e60b 544 #define _RTCC_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for CC_MODE */
<> 139:856d2700e60b 545 #define _RTCC_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
<> 139:856d2700e60b 546 #define _RTCC_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for RTCC_CC_CTRL */
<> 139:856d2700e60b 547 #define _RTCC_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for RTCC_CC_CTRL */
<> 139:856d2700e60b 548 #define _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for RTCC_CC_CTRL */
<> 139:856d2700e60b 549 #define RTCC_CC_CTRL_MODE_DEFAULT (_RTCC_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
<> 139:856d2700e60b 550 #define RTCC_CC_CTRL_MODE_OFF (_RTCC_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for RTCC_CC_CTRL */
<> 139:856d2700e60b 551 #define RTCC_CC_CTRL_MODE_INPUTCAPTURE (_RTCC_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for RTCC_CC_CTRL */
<> 139:856d2700e60b 552 #define RTCC_CC_CTRL_MODE_OUTPUTCOMPARE (_RTCC_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for RTCC_CC_CTRL */
<> 139:856d2700e60b 553 #define _RTCC_CC_CTRL_CMOA_SHIFT 2 /**< Shift value for CC_CMOA */
<> 139:856d2700e60b 554 #define _RTCC_CC_CTRL_CMOA_MASK 0xCUL /**< Bit mask for CC_CMOA */
<> 139:856d2700e60b 555 #define _RTCC_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
<> 139:856d2700e60b 556 #define _RTCC_CC_CTRL_CMOA_PULSE 0x00000000UL /**< Mode PULSE for RTCC_CC_CTRL */
<> 139:856d2700e60b 557 #define _RTCC_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for RTCC_CC_CTRL */
<> 139:856d2700e60b 558 #define _RTCC_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for RTCC_CC_CTRL */
<> 139:856d2700e60b 559 #define _RTCC_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for RTCC_CC_CTRL */
<> 139:856d2700e60b 560 #define RTCC_CC_CTRL_CMOA_DEFAULT (_RTCC_CC_CTRL_CMOA_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
<> 139:856d2700e60b 561 #define RTCC_CC_CTRL_CMOA_PULSE (_RTCC_CC_CTRL_CMOA_PULSE << 2) /**< Shifted mode PULSE for RTCC_CC_CTRL */
<> 139:856d2700e60b 562 #define RTCC_CC_CTRL_CMOA_TOGGLE (_RTCC_CC_CTRL_CMOA_TOGGLE << 2) /**< Shifted mode TOGGLE for RTCC_CC_CTRL */
<> 139:856d2700e60b 563 #define RTCC_CC_CTRL_CMOA_CLEAR (_RTCC_CC_CTRL_CMOA_CLEAR << 2) /**< Shifted mode CLEAR for RTCC_CC_CTRL */
<> 139:856d2700e60b 564 #define RTCC_CC_CTRL_CMOA_SET (_RTCC_CC_CTRL_CMOA_SET << 2) /**< Shifted mode SET for RTCC_CC_CTRL */
<> 139:856d2700e60b 565 #define _RTCC_CC_CTRL_ICEDGE_SHIFT 4 /**< Shift value for CC_ICEDGE */
<> 139:856d2700e60b 566 #define _RTCC_CC_CTRL_ICEDGE_MASK 0x30UL /**< Bit mask for CC_ICEDGE */
<> 139:856d2700e60b 567 #define _RTCC_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
<> 139:856d2700e60b 568 #define _RTCC_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for RTCC_CC_CTRL */
<> 139:856d2700e60b 569 #define _RTCC_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for RTCC_CC_CTRL */
<> 139:856d2700e60b 570 #define _RTCC_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for RTCC_CC_CTRL */
<> 139:856d2700e60b 571 #define _RTCC_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for RTCC_CC_CTRL */
<> 139:856d2700e60b 572 #define RTCC_CC_CTRL_ICEDGE_DEFAULT (_RTCC_CC_CTRL_ICEDGE_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
<> 139:856d2700e60b 573 #define RTCC_CC_CTRL_ICEDGE_RISING (_RTCC_CC_CTRL_ICEDGE_RISING << 4) /**< Shifted mode RISING for RTCC_CC_CTRL */
<> 139:856d2700e60b 574 #define RTCC_CC_CTRL_ICEDGE_FALLING (_RTCC_CC_CTRL_ICEDGE_FALLING << 4) /**< Shifted mode FALLING for RTCC_CC_CTRL */
<> 139:856d2700e60b 575 #define RTCC_CC_CTRL_ICEDGE_BOTH (_RTCC_CC_CTRL_ICEDGE_BOTH << 4) /**< Shifted mode BOTH for RTCC_CC_CTRL */
<> 139:856d2700e60b 576 #define RTCC_CC_CTRL_ICEDGE_NONE (_RTCC_CC_CTRL_ICEDGE_NONE << 4) /**< Shifted mode NONE for RTCC_CC_CTRL */
<> 139:856d2700e60b 577 #define _RTCC_CC_CTRL_PRSSEL_SHIFT 6 /**< Shift value for CC_PRSSEL */
<> 139:856d2700e60b 578 #define _RTCC_CC_CTRL_PRSSEL_MASK 0x3C0UL /**< Bit mask for CC_PRSSEL */
<> 139:856d2700e60b 579 #define _RTCC_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
<> 139:856d2700e60b 580 #define _RTCC_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for RTCC_CC_CTRL */
<> 139:856d2700e60b 581 #define _RTCC_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for RTCC_CC_CTRL */
<> 139:856d2700e60b 582 #define _RTCC_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for RTCC_CC_CTRL */
<> 139:856d2700e60b 583 #define _RTCC_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for RTCC_CC_CTRL */
<> 139:856d2700e60b 584 #define _RTCC_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for RTCC_CC_CTRL */
<> 139:856d2700e60b 585 #define _RTCC_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for RTCC_CC_CTRL */
<> 139:856d2700e60b 586 #define _RTCC_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for RTCC_CC_CTRL */
<> 139:856d2700e60b 587 #define _RTCC_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for RTCC_CC_CTRL */
<> 139:856d2700e60b 588 #define _RTCC_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for RTCC_CC_CTRL */
<> 139:856d2700e60b 589 #define _RTCC_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for RTCC_CC_CTRL */
<> 139:856d2700e60b 590 #define _RTCC_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for RTCC_CC_CTRL */
<> 139:856d2700e60b 591 #define _RTCC_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for RTCC_CC_CTRL */
<> 139:856d2700e60b 592 #define RTCC_CC_CTRL_PRSSEL_DEFAULT (_RTCC_CC_CTRL_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
<> 139:856d2700e60b 593 #define RTCC_CC_CTRL_PRSSEL_PRSCH0 (_RTCC_CC_CTRL_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for RTCC_CC_CTRL */
<> 139:856d2700e60b 594 #define RTCC_CC_CTRL_PRSSEL_PRSCH1 (_RTCC_CC_CTRL_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for RTCC_CC_CTRL */
<> 139:856d2700e60b 595 #define RTCC_CC_CTRL_PRSSEL_PRSCH2 (_RTCC_CC_CTRL_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for RTCC_CC_CTRL */
<> 139:856d2700e60b 596 #define RTCC_CC_CTRL_PRSSEL_PRSCH3 (_RTCC_CC_CTRL_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for RTCC_CC_CTRL */
<> 139:856d2700e60b 597 #define RTCC_CC_CTRL_PRSSEL_PRSCH4 (_RTCC_CC_CTRL_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for RTCC_CC_CTRL */
<> 139:856d2700e60b 598 #define RTCC_CC_CTRL_PRSSEL_PRSCH5 (_RTCC_CC_CTRL_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for RTCC_CC_CTRL */
<> 139:856d2700e60b 599 #define RTCC_CC_CTRL_PRSSEL_PRSCH6 (_RTCC_CC_CTRL_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for RTCC_CC_CTRL */
<> 139:856d2700e60b 600 #define RTCC_CC_CTRL_PRSSEL_PRSCH7 (_RTCC_CC_CTRL_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for RTCC_CC_CTRL */
<> 139:856d2700e60b 601 #define RTCC_CC_CTRL_PRSSEL_PRSCH8 (_RTCC_CC_CTRL_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for RTCC_CC_CTRL */
<> 139:856d2700e60b 602 #define RTCC_CC_CTRL_PRSSEL_PRSCH9 (_RTCC_CC_CTRL_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for RTCC_CC_CTRL */
<> 139:856d2700e60b 603 #define RTCC_CC_CTRL_PRSSEL_PRSCH10 (_RTCC_CC_CTRL_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for RTCC_CC_CTRL */
<> 139:856d2700e60b 604 #define RTCC_CC_CTRL_PRSSEL_PRSCH11 (_RTCC_CC_CTRL_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for RTCC_CC_CTRL */
<> 139:856d2700e60b 605 #define RTCC_CC_CTRL_COMPBASE (0x1UL << 11) /**< Capture compare channel comparison base. */
<> 139:856d2700e60b 606 #define _RTCC_CC_CTRL_COMPBASE_SHIFT 11 /**< Shift value for CC_COMPBASE */
<> 139:856d2700e60b 607 #define _RTCC_CC_CTRL_COMPBASE_MASK 0x800UL /**< Bit mask for CC_COMPBASE */
<> 139:856d2700e60b 608 #define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
<> 139:856d2700e60b 609 #define _RTCC_CC_CTRL_COMPBASE_CNT 0x00000000UL /**< Mode CNT for RTCC_CC_CTRL */
<> 139:856d2700e60b 610 #define _RTCC_CC_CTRL_COMPBASE_PRECNT 0x00000001UL /**< Mode PRECNT for RTCC_CC_CTRL */
<> 139:856d2700e60b 611 #define RTCC_CC_CTRL_COMPBASE_DEFAULT (_RTCC_CC_CTRL_COMPBASE_DEFAULT << 11) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
<> 139:856d2700e60b 612 #define RTCC_CC_CTRL_COMPBASE_CNT (_RTCC_CC_CTRL_COMPBASE_CNT << 11) /**< Shifted mode CNT for RTCC_CC_CTRL */
<> 139:856d2700e60b 613 #define RTCC_CC_CTRL_COMPBASE_PRECNT (_RTCC_CC_CTRL_COMPBASE_PRECNT << 11) /**< Shifted mode PRECNT for RTCC_CC_CTRL */
<> 139:856d2700e60b 614 #define _RTCC_CC_CTRL_COMPMASK_SHIFT 12 /**< Shift value for CC_COMPMASK */
<> 139:856d2700e60b 615 #define _RTCC_CC_CTRL_COMPMASK_MASK 0x1F000UL /**< Bit mask for CC_COMPMASK */
<> 139:856d2700e60b 616 #define _RTCC_CC_CTRL_COMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
<> 139:856d2700e60b 617 #define RTCC_CC_CTRL_COMPMASK_DEFAULT (_RTCC_CC_CTRL_COMPMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
<> 139:856d2700e60b 618 #define RTCC_CC_CTRL_DAYCC (0x1UL << 17) /**< Day Capture/Compare selection */
<> 139:856d2700e60b 619 #define _RTCC_CC_CTRL_DAYCC_SHIFT 17 /**< Shift value for CC_DAYCC */
<> 139:856d2700e60b 620 #define _RTCC_CC_CTRL_DAYCC_MASK 0x20000UL /**< Bit mask for CC_DAYCC */
<> 139:856d2700e60b 621 #define _RTCC_CC_CTRL_DAYCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
<> 139:856d2700e60b 622 #define _RTCC_CC_CTRL_DAYCC_MONTH 0x00000000UL /**< Mode MONTH for RTCC_CC_CTRL */
<> 139:856d2700e60b 623 #define _RTCC_CC_CTRL_DAYCC_WEEK 0x00000001UL /**< Mode WEEK for RTCC_CC_CTRL */
<> 139:856d2700e60b 624 #define RTCC_CC_CTRL_DAYCC_DEFAULT (_RTCC_CC_CTRL_DAYCC_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
<> 139:856d2700e60b 625 #define RTCC_CC_CTRL_DAYCC_MONTH (_RTCC_CC_CTRL_DAYCC_MONTH << 17) /**< Shifted mode MONTH for RTCC_CC_CTRL */
<> 139:856d2700e60b 626 #define RTCC_CC_CTRL_DAYCC_WEEK (_RTCC_CC_CTRL_DAYCC_WEEK << 17) /**< Shifted mode WEEK for RTCC_CC_CTRL */
<> 139:856d2700e60b 627
<> 139:856d2700e60b 628 /* Bit fields for RTCC CC_CCV */
<> 139:856d2700e60b 629 #define _RTCC_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CCV */
<> 139:856d2700e60b 630 #define _RTCC_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_CCV */
<> 139:856d2700e60b 631 #define _RTCC_CC_CCV_CCV_SHIFT 0 /**< Shift value for CC_CCV */
<> 139:856d2700e60b 632 #define _RTCC_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for CC_CCV */
<> 139:856d2700e60b 633 #define _RTCC_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CCV */
<> 139:856d2700e60b 634 #define RTCC_CC_CCV_CCV_DEFAULT (_RTCC_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CCV */
<> 139:856d2700e60b 635
<> 139:856d2700e60b 636 /* Bit fields for RTCC CC_TIME */
<> 139:856d2700e60b 637 #define _RTCC_CC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_TIME */
<> 139:856d2700e60b 638 #define _RTCC_CC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_CC_TIME */
<> 139:856d2700e60b 639 #define _RTCC_CC_TIME_SECU_SHIFT 0 /**< Shift value for CC_SECU */
<> 139:856d2700e60b 640 #define _RTCC_CC_TIME_SECU_MASK 0xFUL /**< Bit mask for CC_SECU */
<> 139:856d2700e60b 641 #define _RTCC_CC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
<> 139:856d2700e60b 642 #define RTCC_CC_TIME_SECU_DEFAULT (_RTCC_CC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
<> 139:856d2700e60b 643 #define _RTCC_CC_TIME_SECT_SHIFT 4 /**< Shift value for CC_SECT */
<> 139:856d2700e60b 644 #define _RTCC_CC_TIME_SECT_MASK 0x70UL /**< Bit mask for CC_SECT */
<> 139:856d2700e60b 645 #define _RTCC_CC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
<> 139:856d2700e60b 646 #define RTCC_CC_TIME_SECT_DEFAULT (_RTCC_CC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
<> 139:856d2700e60b 647 #define _RTCC_CC_TIME_MINU_SHIFT 8 /**< Shift value for CC_MINU */
<> 139:856d2700e60b 648 #define _RTCC_CC_TIME_MINU_MASK 0xF00UL /**< Bit mask for CC_MINU */
<> 139:856d2700e60b 649 #define _RTCC_CC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
<> 139:856d2700e60b 650 #define RTCC_CC_TIME_MINU_DEFAULT (_RTCC_CC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
<> 139:856d2700e60b 651 #define _RTCC_CC_TIME_MINT_SHIFT 12 /**< Shift value for CC_MINT */
<> 139:856d2700e60b 652 #define _RTCC_CC_TIME_MINT_MASK 0x7000UL /**< Bit mask for CC_MINT */
<> 139:856d2700e60b 653 #define _RTCC_CC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
<> 139:856d2700e60b 654 #define RTCC_CC_TIME_MINT_DEFAULT (_RTCC_CC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
<> 139:856d2700e60b 655 #define _RTCC_CC_TIME_HOURU_SHIFT 16 /**< Shift value for CC_HOURU */
<> 139:856d2700e60b 656 #define _RTCC_CC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for CC_HOURU */
<> 139:856d2700e60b 657 #define _RTCC_CC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
<> 139:856d2700e60b 658 #define RTCC_CC_TIME_HOURU_DEFAULT (_RTCC_CC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
<> 139:856d2700e60b 659 #define _RTCC_CC_TIME_HOURT_SHIFT 20 /**< Shift value for CC_HOURT */
<> 139:856d2700e60b 660 #define _RTCC_CC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for CC_HOURT */
<> 139:856d2700e60b 661 #define _RTCC_CC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
<> 139:856d2700e60b 662 #define RTCC_CC_TIME_HOURT_DEFAULT (_RTCC_CC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
<> 139:856d2700e60b 663
<> 139:856d2700e60b 664 /* Bit fields for RTCC CC_DATE */
<> 139:856d2700e60b 665 #define _RTCC_CC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_DATE */
<> 139:856d2700e60b 666 #define _RTCC_CC_DATE_MASK 0x00001F3FUL /**< Mask for RTCC_CC_DATE */
<> 139:856d2700e60b 667 #define _RTCC_CC_DATE_DAYU_SHIFT 0 /**< Shift value for CC_DAYU */
<> 139:856d2700e60b 668 #define _RTCC_CC_DATE_DAYU_MASK 0xFUL /**< Bit mask for CC_DAYU */
<> 139:856d2700e60b 669 #define _RTCC_CC_DATE_DAYU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
<> 139:856d2700e60b 670 #define RTCC_CC_DATE_DAYU_DEFAULT (_RTCC_CC_DATE_DAYU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
<> 139:856d2700e60b 671 #define _RTCC_CC_DATE_DAYT_SHIFT 4 /**< Shift value for CC_DAYT */
<> 139:856d2700e60b 672 #define _RTCC_CC_DATE_DAYT_MASK 0x30UL /**< Bit mask for CC_DAYT */
<> 139:856d2700e60b 673 #define _RTCC_CC_DATE_DAYT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
<> 139:856d2700e60b 674 #define RTCC_CC_DATE_DAYT_DEFAULT (_RTCC_CC_DATE_DAYT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
<> 139:856d2700e60b 675 #define _RTCC_CC_DATE_MONTHU_SHIFT 8 /**< Shift value for CC_MONTHU */
<> 139:856d2700e60b 676 #define _RTCC_CC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for CC_MONTHU */
<> 139:856d2700e60b 677 #define _RTCC_CC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
<> 139:856d2700e60b 678 #define RTCC_CC_DATE_MONTHU_DEFAULT (_RTCC_CC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
<> 139:856d2700e60b 679 #define RTCC_CC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */
<> 139:856d2700e60b 680 #define _RTCC_CC_DATE_MONTHT_SHIFT 12 /**< Shift value for CC_MONTHT */
<> 139:856d2700e60b 681 #define _RTCC_CC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for CC_MONTHT */
<> 139:856d2700e60b 682 #define _RTCC_CC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
<> 139:856d2700e60b 683 #define RTCC_CC_DATE_MONTHT_DEFAULT (_RTCC_CC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
<> 139:856d2700e60b 684
<> 139:856d2700e60b 685 /* Bit fields for RTCC RET_REG */
<> 139:856d2700e60b 686 #define _RTCC_RET_REG_RESETVALUE 0x00000000UL /**< Default value for RTCC_RET_REG */
<> 139:856d2700e60b 687 #define _RTCC_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for RTCC_RET_REG */
<> 139:856d2700e60b 688 #define _RTCC_RET_REG_REG_SHIFT 0 /**< Shift value for RET_REG */
<> 139:856d2700e60b 689 #define _RTCC_RET_REG_REG_MASK 0xFFFFFFFFUL /**< Bit mask for RET_REG */
<> 139:856d2700e60b 690 #define _RTCC_RET_REG_REG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_RET_REG */
<> 139:856d2700e60b 691 #define RTCC_RET_REG_REG_DEFAULT (_RTCC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_RET_REG */
<> 139:856d2700e60b 692
<> 139:856d2700e60b 693 /** @} End of group EFM32PG12B_RTCC */
<> 139:856d2700e60b 694 /** @} End of group Parts */
<> 139:856d2700e60b 695