mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32PG12_STK3402/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_msc.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
139:856d2700e60b 
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 139:856d2700e60b 1 /**************************************************************************//**
<> 139:856d2700e60b 2 * @file efm32pg12b_msc.h
<> 139:856d2700e60b 3 * @brief EFM32PG12B_MSC register and bit field definitions
<> 139:856d2700e60b 4 * @version 5.1.2
<> 139:856d2700e60b 5 ******************************************************************************
<> 139:856d2700e60b 6 * @section License
<> 139:856d2700e60b 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 139:856d2700e60b 8 ******************************************************************************
<> 139:856d2700e60b 9 *
<> 139:856d2700e60b 10 * Permission is granted to anyone to use this software for any purpose,
<> 139:856d2700e60b 11 * including commercial applications, and to alter it and redistribute it
<> 139:856d2700e60b 12 * freely, subject to the following restrictions:
<> 139:856d2700e60b 13 *
<> 139:856d2700e60b 14 * 1. The origin of this software must not be misrepresented; you must not
<> 139:856d2700e60b 15 * claim that you wrote the original software.@n
<> 139:856d2700e60b 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 139:856d2700e60b 17 * misrepresented as being the original software.@n
<> 139:856d2700e60b 18 * 3. This notice may not be removed or altered from any source distribution.
<> 139:856d2700e60b 19 *
<> 139:856d2700e60b 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 139:856d2700e60b 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 139:856d2700e60b 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 139:856d2700e60b 23 * kind, including, but not limited to, any implied warranties of
<> 139:856d2700e60b 24 * merchantability or fitness for any particular purpose or warranties against
<> 139:856d2700e60b 25 * infringement of any proprietary rights of a third party.
<> 139:856d2700e60b 26 *
<> 139:856d2700e60b 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 139:856d2700e60b 28 * incidental, or special damages, or any other relief, or for any claim by
<> 139:856d2700e60b 29 * any third party, arising from your use of this Software.
<> 139:856d2700e60b 30 *
<> 139:856d2700e60b 31 *****************************************************************************/
<> 139:856d2700e60b 32 /**************************************************************************//**
<> 139:856d2700e60b 33 * @addtogroup Parts
<> 139:856d2700e60b 34 * @{
<> 139:856d2700e60b 35 ******************************************************************************/
<> 139:856d2700e60b 36 /**************************************************************************//**
<> 139:856d2700e60b 37 * @defgroup EFM32PG12B_MSC
<> 139:856d2700e60b 38 * @{
<> 139:856d2700e60b 39 * @brief EFM32PG12B_MSC Register Declaration
<> 139:856d2700e60b 40 *****************************************************************************/
<> 139:856d2700e60b 41 typedef struct
<> 139:856d2700e60b 42 {
<> 139:856d2700e60b 43 __IOM uint32_t CTRL; /**< Memory System Control Register */
<> 139:856d2700e60b 44 __IOM uint32_t READCTRL; /**< Read Control Register */
<> 139:856d2700e60b 45 __IOM uint32_t WRITECTRL; /**< Write Control Register */
<> 139:856d2700e60b 46 __IOM uint32_t WRITECMD; /**< Write Command Register */
<> 139:856d2700e60b 47 __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */
<> 139:856d2700e60b 48 uint32_t RESERVED0[1]; /**< Reserved for future use **/
<> 139:856d2700e60b 49 __IOM uint32_t WDATA; /**< Write Data Register */
<> 139:856d2700e60b 50 __IM uint32_t STATUS; /**< Status Register */
<> 139:856d2700e60b 51
<> 139:856d2700e60b 52 uint32_t RESERVED1[4]; /**< Reserved for future use **/
<> 139:856d2700e60b 53 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 139:856d2700e60b 54 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 139:856d2700e60b 55 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 139:856d2700e60b 56 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 139:856d2700e60b 57 __IOM uint32_t LOCK; /**< Configuration Lock Register */
<> 139:856d2700e60b 58 __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */
<> 139:856d2700e60b 59 __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */
<> 139:856d2700e60b 60 __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */
<> 139:856d2700e60b 61
<> 139:856d2700e60b 62 uint32_t RESERVED2[1]; /**< Reserved for future use **/
<> 139:856d2700e60b 63 __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */
<> 139:856d2700e60b 64
<> 139:856d2700e60b 65 uint32_t RESERVED3[1]; /**< Reserved for future use **/
<> 139:856d2700e60b 66 __IOM uint32_t STARTUP; /**< Startup Control */
<> 139:856d2700e60b 67
<> 139:856d2700e60b 68 uint32_t RESERVED4[4]; /**< Reserved for future use **/
<> 139:856d2700e60b 69 __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */
<> 139:856d2700e60b 70 __IOM uint32_t CMD; /**< Command Register */
<> 139:856d2700e60b 71
<> 139:856d2700e60b 72 uint32_t RESERVED5[6]; /**< Reserved for future use **/
<> 139:856d2700e60b 73 __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader read and write enable, write once register */
<> 139:856d2700e60b 74 __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */
<> 139:856d2700e60b 75 __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */
<> 139:856d2700e60b 76
<> 139:856d2700e60b 77 uint32_t RESERVED6[25]; /**< Reserved for future use **/
<> 139:856d2700e60b 78 __IOM uint32_t RAMCTRL; /**< RAM Control enable Register */
<> 139:856d2700e60b 79 } MSC_TypeDef; /** @} */
<> 139:856d2700e60b 80
<> 139:856d2700e60b 81 /**************************************************************************//**
<> 139:856d2700e60b 82 * @defgroup EFM32PG12B_MSC_BitFields
<> 139:856d2700e60b 83 * @{
<> 139:856d2700e60b 84 *****************************************************************************/
<> 139:856d2700e60b 85
<> 139:856d2700e60b 86 /* Bit fields for MSC CTRL */
<> 139:856d2700e60b 87 #define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */
<> 139:856d2700e60b 88 #define _MSC_CTRL_MASK 0x0000001FUL /**< Mask for MSC_CTRL */
<> 139:856d2700e60b 89 #define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */
<> 139:856d2700e60b 90 #define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */
<> 139:856d2700e60b 91 #define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */
<> 139:856d2700e60b 92 #define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */
<> 139:856d2700e60b 93 #define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */
<> 139:856d2700e60b 94 #define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */
<> 139:856d2700e60b 95 #define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */
<> 139:856d2700e60b 96 #define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */
<> 139:856d2700e60b 97 #define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
<> 139:856d2700e60b 98 #define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */
<> 139:856d2700e60b 99 #define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up On Demand During Wake Up */
<> 139:856d2700e60b 100 #define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */
<> 139:856d2700e60b 101 #define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */
<> 139:856d2700e60b 102 #define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
<> 139:856d2700e60b 103 #define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */
<> 139:856d2700e60b 104 #define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */
<> 139:856d2700e60b 105 #define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */
<> 139:856d2700e60b 106 #define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */
<> 139:856d2700e60b 107 #define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
<> 139:856d2700e60b 108 #define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */
<> 139:856d2700e60b 109 #define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */
<> 139:856d2700e60b 110 #define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */
<> 139:856d2700e60b 111 #define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */
<> 139:856d2700e60b 112 #define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
<> 139:856d2700e60b 113 #define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */
<> 139:856d2700e60b 114
<> 139:856d2700e60b 115 /* Bit fields for MSC READCTRL */
<> 139:856d2700e60b 116 #define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */
<> 139:856d2700e60b 117 #define _MSC_READCTRL_MASK 0x13000338UL /**< Mask for MSC_READCTRL */
<> 139:856d2700e60b 118 #define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */
<> 139:856d2700e60b 119 #define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */
<> 139:856d2700e60b 120 #define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */
<> 139:856d2700e60b 121 #define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
<> 139:856d2700e60b 122 #define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */
<> 139:856d2700e60b 123 #define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */
<> 139:856d2700e60b 124 #define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */
<> 139:856d2700e60b 125 #define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */
<> 139:856d2700e60b 126 #define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
<> 139:856d2700e60b 127 #define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */
<> 139:856d2700e60b 128 #define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */
<> 139:856d2700e60b 129 #define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */
<> 139:856d2700e60b 130 #define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */
<> 139:856d2700e60b 131 #define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
<> 139:856d2700e60b 132 #define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */
<> 139:856d2700e60b 133 #define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */
<> 139:856d2700e60b 134 #define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */
<> 139:856d2700e60b 135 #define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */
<> 139:856d2700e60b 136 #define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */
<> 139:856d2700e60b 137 #define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */
<> 139:856d2700e60b 138 #define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */
<> 139:856d2700e60b 139 #define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */
<> 139:856d2700e60b 140 #define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */
<> 139:856d2700e60b 141 #define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
<> 139:856d2700e60b 142 #define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */
<> 139:856d2700e60b 143 #define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */
<> 139:856d2700e60b 144 #define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */
<> 139:856d2700e60b 145 #define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */
<> 139:856d2700e60b 146 #define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */
<> 139:856d2700e60b 147 #define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */
<> 139:856d2700e60b 148 #define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */
<> 139:856d2700e60b 149 #define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */
<> 139:856d2700e60b 150 #define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */
<> 139:856d2700e60b 151 #define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */
<> 139:856d2700e60b 152 #define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */
<> 139:856d2700e60b 153 #define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */
<> 139:856d2700e60b 154 #define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */
<> 139:856d2700e60b 155 #define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */
<> 139:856d2700e60b 156 #define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */
<> 139:856d2700e60b 157 #define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */
<> 139:856d2700e60b 158 #define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
<> 139:856d2700e60b 159 #define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */
<> 139:856d2700e60b 160
<> 139:856d2700e60b 161 /* Bit fields for MSC WRITECTRL */
<> 139:856d2700e60b 162 #define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */
<> 139:856d2700e60b 163 #define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */
<> 139:856d2700e60b 164 #define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */
<> 139:856d2700e60b 165 #define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */
<> 139:856d2700e60b 166 #define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */
<> 139:856d2700e60b 167 #define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
<> 139:856d2700e60b 168 #define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
<> 139:856d2700e60b 169 #define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */
<> 139:856d2700e60b 170 #define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */
<> 139:856d2700e60b 171 #define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */
<> 139:856d2700e60b 172 #define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
<> 139:856d2700e60b 173 #define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
<> 139:856d2700e60b 174 #define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */
<> 139:856d2700e60b 175 #define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */
<> 139:856d2700e60b 176 #define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */
<> 139:856d2700e60b 177 #define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
<> 139:856d2700e60b 178 #define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
<> 139:856d2700e60b 179
<> 139:856d2700e60b 180 /* Bit fields for MSC WRITECMD */
<> 139:856d2700e60b 181 #define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */
<> 139:856d2700e60b 182 #define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */
<> 139:856d2700e60b 183 #define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB into ADDR */
<> 139:856d2700e60b 184 #define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */
<> 139:856d2700e60b 185 #define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */
<> 139:856d2700e60b 186 #define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 139:856d2700e60b 187 #define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 139:856d2700e60b 188 #define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */
<> 139:856d2700e60b 189 #define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */
<> 139:856d2700e60b 190 #define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */
<> 139:856d2700e60b 191 #define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 139:856d2700e60b 192 #define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 139:856d2700e60b 193 #define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */
<> 139:856d2700e60b 194 #define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */
<> 139:856d2700e60b 195 #define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */
<> 139:856d2700e60b 196 #define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 139:856d2700e60b 197 #define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 139:856d2700e60b 198 #define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */
<> 139:856d2700e60b 199 #define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */
<> 139:856d2700e60b 200 #define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */
<> 139:856d2700e60b 201 #define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 139:856d2700e60b 202 #define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 139:856d2700e60b 203 #define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */
<> 139:856d2700e60b 204 #define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */
<> 139:856d2700e60b 205 #define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */
<> 139:856d2700e60b 206 #define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 139:856d2700e60b 207 #define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 139:856d2700e60b 208 #define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */
<> 139:856d2700e60b 209 #define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */
<> 139:856d2700e60b 210 #define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */
<> 139:856d2700e60b 211 #define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 139:856d2700e60b 212 #define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 139:856d2700e60b 213 #define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */
<> 139:856d2700e60b 214 #define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */
<> 139:856d2700e60b 215 #define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */
<> 139:856d2700e60b 216 #define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 139:856d2700e60b 217 #define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 139:856d2700e60b 218 #define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass erase region 1 */
<> 139:856d2700e60b 219 #define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */
<> 139:856d2700e60b 220 #define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */
<> 139:856d2700e60b 221 #define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 139:856d2700e60b 222 #define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 139:856d2700e60b 223 #define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */
<> 139:856d2700e60b 224 #define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */
<> 139:856d2700e60b 225 #define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */
<> 139:856d2700e60b 226 #define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
<> 139:856d2700e60b 227 #define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */
<> 139:856d2700e60b 228
<> 139:856d2700e60b 229 /* Bit fields for MSC ADDRB */
<> 139:856d2700e60b 230 #define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */
<> 139:856d2700e60b 231 #define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */
<> 139:856d2700e60b 232 #define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */
<> 139:856d2700e60b 233 #define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */
<> 139:856d2700e60b 234 #define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */
<> 139:856d2700e60b 235 #define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */
<> 139:856d2700e60b 236
<> 139:856d2700e60b 237 /* Bit fields for MSC WDATA */
<> 139:856d2700e60b 238 #define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */
<> 139:856d2700e60b 239 #define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */
<> 139:856d2700e60b 240 #define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */
<> 139:856d2700e60b 241 #define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */
<> 139:856d2700e60b 242 #define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */
<> 139:856d2700e60b 243 #define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */
<> 139:856d2700e60b 244
<> 139:856d2700e60b 245 /* Bit fields for MSC STATUS */
<> 139:856d2700e60b 246 #define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */
<> 139:856d2700e60b 247 #define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */
<> 139:856d2700e60b 248 #define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */
<> 139:856d2700e60b 249 #define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */
<> 139:856d2700e60b 250 #define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */
<> 139:856d2700e60b 251 #define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
<> 139:856d2700e60b 252 #define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 139:856d2700e60b 253 #define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */
<> 139:856d2700e60b 254 #define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */
<> 139:856d2700e60b 255 #define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */
<> 139:856d2700e60b 256 #define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
<> 139:856d2700e60b 257 #define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 139:856d2700e60b 258 #define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */
<> 139:856d2700e60b 259 #define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */
<> 139:856d2700e60b 260 #define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */
<> 139:856d2700e60b 261 #define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
<> 139:856d2700e60b 262 #define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 139:856d2700e60b 263 #define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */
<> 139:856d2700e60b 264 #define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */
<> 139:856d2700e60b 265 #define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */
<> 139:856d2700e60b 266 #define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */
<> 139:856d2700e60b 267 #define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 139:856d2700e60b 268 #define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */
<> 139:856d2700e60b 269 #define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */
<> 139:856d2700e60b 270 #define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */
<> 139:856d2700e60b 271 #define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
<> 139:856d2700e60b 272 #define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 139:856d2700e60b 273 #define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */
<> 139:856d2700e60b 274 #define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */
<> 139:856d2700e60b 275 #define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */
<> 139:856d2700e60b 276 #define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
<> 139:856d2700e60b 277 #define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 139:856d2700e60b 278 #define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */
<> 139:856d2700e60b 279 #define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */
<> 139:856d2700e60b 280 #define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */
<> 139:856d2700e60b 281 #define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
<> 139:856d2700e60b 282 #define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 139:856d2700e60b 283 #define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */
<> 139:856d2700e60b 284 #define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */
<> 139:856d2700e60b 285 #define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */
<> 139:856d2700e60b 286 #define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
<> 139:856d2700e60b 287 #define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 139:856d2700e60b 288 #define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */
<> 139:856d2700e60b 289 #define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */
<> 139:856d2700e60b 290 #define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
<> 139:856d2700e60b 291 #define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 139:856d2700e60b 292 #define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */
<> 139:856d2700e60b 293 #define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */
<> 139:856d2700e60b 294 #define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
<> 139:856d2700e60b 295 #define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */
<> 139:856d2700e60b 296
<> 139:856d2700e60b 297 /* Bit fields for MSC IF */
<> 139:856d2700e60b 298 #define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */
<> 139:856d2700e60b 299 #define _MSC_IF_MASK 0x0000017FUL /**< Mask for MSC_IF */
<> 139:856d2700e60b 300 #define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */
<> 139:856d2700e60b 301 #define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
<> 139:856d2700e60b 302 #define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
<> 139:856d2700e60b 303 #define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
<> 139:856d2700e60b 304 #define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */
<> 139:856d2700e60b 305 #define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */
<> 139:856d2700e60b 306 #define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
<> 139:856d2700e60b 307 #define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
<> 139:856d2700e60b 308 #define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
<> 139:856d2700e60b 309 #define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */
<> 139:856d2700e60b 310 #define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */
<> 139:856d2700e60b 311 #define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
<> 139:856d2700e60b 312 #define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
<> 139:856d2700e60b 313 #define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
<> 139:856d2700e60b 314 #define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */
<> 139:856d2700e60b 315 #define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */
<> 139:856d2700e60b 316 #define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
<> 139:856d2700e60b 317 #define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
<> 139:856d2700e60b 318 #define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
<> 139:856d2700e60b 319 #define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */
<> 139:856d2700e60b 320 #define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */
<> 139:856d2700e60b 321 #define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
<> 139:856d2700e60b 322 #define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
<> 139:856d2700e60b 323 #define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
<> 139:856d2700e60b 324 #define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */
<> 139:856d2700e60b 325 #define MSC_IF_ICACHERR (0x1UL << 5) /**< iCache RAM Parity Error Flag */
<> 139:856d2700e60b 326 #define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
<> 139:856d2700e60b 327 #define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
<> 139:856d2700e60b 328 #define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
<> 139:856d2700e60b 329 #define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */
<> 139:856d2700e60b 330 #define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash controller write buffer overflow */
<> 139:856d2700e60b 331 #define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */
<> 139:856d2700e60b 332 #define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */
<> 139:856d2700e60b 333 #define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
<> 139:856d2700e60b 334 #define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */
<> 139:856d2700e60b 335 #define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */
<> 139:856d2700e60b 336 #define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */
<> 139:856d2700e60b 337 #define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */
<> 139:856d2700e60b 338 #define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
<> 139:856d2700e60b 339 #define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */
<> 139:856d2700e60b 340
<> 139:856d2700e60b 341 /* Bit fields for MSC IFS */
<> 139:856d2700e60b 342 #define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */
<> 139:856d2700e60b 343 #define _MSC_IFS_MASK 0x0000017FUL /**< Mask for MSC_IFS */
<> 139:856d2700e60b 344 #define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */
<> 139:856d2700e60b 345 #define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
<> 139:856d2700e60b 346 #define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
<> 139:856d2700e60b 347 #define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
<> 139:856d2700e60b 348 #define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */
<> 139:856d2700e60b 349 #define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */
<> 139:856d2700e60b 350 #define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
<> 139:856d2700e60b 351 #define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
<> 139:856d2700e60b 352 #define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
<> 139:856d2700e60b 353 #define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */
<> 139:856d2700e60b 354 #define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */
<> 139:856d2700e60b 355 #define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
<> 139:856d2700e60b 356 #define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
<> 139:856d2700e60b 357 #define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
<> 139:856d2700e60b 358 #define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */
<> 139:856d2700e60b 359 #define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */
<> 139:856d2700e60b 360 #define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
<> 139:856d2700e60b 361 #define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
<> 139:856d2700e60b 362 #define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
<> 139:856d2700e60b 363 #define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */
<> 139:856d2700e60b 364 #define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */
<> 139:856d2700e60b 365 #define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
<> 139:856d2700e60b 366 #define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
<> 139:856d2700e60b 367 #define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
<> 139:856d2700e60b 368 #define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */
<> 139:856d2700e60b 369 #define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */
<> 139:856d2700e60b 370 #define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
<> 139:856d2700e60b 371 #define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
<> 139:856d2700e60b 372 #define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
<> 139:856d2700e60b 373 #define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */
<> 139:856d2700e60b 374 #define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */
<> 139:856d2700e60b 375 #define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */
<> 139:856d2700e60b 376 #define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */
<> 139:856d2700e60b 377 #define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
<> 139:856d2700e60b 378 #define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */
<> 139:856d2700e60b 379 #define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */
<> 139:856d2700e60b 380 #define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */
<> 139:856d2700e60b 381 #define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */
<> 139:856d2700e60b 382 #define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
<> 139:856d2700e60b 383 #define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */
<> 139:856d2700e60b 384
<> 139:856d2700e60b 385 /* Bit fields for MSC IFC */
<> 139:856d2700e60b 386 #define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */
<> 139:856d2700e60b 387 #define _MSC_IFC_MASK 0x0000017FUL /**< Mask for MSC_IFC */
<> 139:856d2700e60b 388 #define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */
<> 139:856d2700e60b 389 #define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
<> 139:856d2700e60b 390 #define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
<> 139:856d2700e60b 391 #define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
<> 139:856d2700e60b 392 #define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */
<> 139:856d2700e60b 393 #define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */
<> 139:856d2700e60b 394 #define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
<> 139:856d2700e60b 395 #define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
<> 139:856d2700e60b 396 #define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
<> 139:856d2700e60b 397 #define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */
<> 139:856d2700e60b 398 #define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */
<> 139:856d2700e60b 399 #define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
<> 139:856d2700e60b 400 #define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
<> 139:856d2700e60b 401 #define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
<> 139:856d2700e60b 402 #define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */
<> 139:856d2700e60b 403 #define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */
<> 139:856d2700e60b 404 #define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
<> 139:856d2700e60b 405 #define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
<> 139:856d2700e60b 406 #define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
<> 139:856d2700e60b 407 #define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */
<> 139:856d2700e60b 408 #define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */
<> 139:856d2700e60b 409 #define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
<> 139:856d2700e60b 410 #define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
<> 139:856d2700e60b 411 #define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
<> 139:856d2700e60b 412 #define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */
<> 139:856d2700e60b 413 #define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */
<> 139:856d2700e60b 414 #define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
<> 139:856d2700e60b 415 #define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
<> 139:856d2700e60b 416 #define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
<> 139:856d2700e60b 417 #define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */
<> 139:856d2700e60b 418 #define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */
<> 139:856d2700e60b 419 #define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */
<> 139:856d2700e60b 420 #define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */
<> 139:856d2700e60b 421 #define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
<> 139:856d2700e60b 422 #define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */
<> 139:856d2700e60b 423 #define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */
<> 139:856d2700e60b 424 #define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */
<> 139:856d2700e60b 425 #define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */
<> 139:856d2700e60b 426 #define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
<> 139:856d2700e60b 427 #define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */
<> 139:856d2700e60b 428
<> 139:856d2700e60b 429 /* Bit fields for MSC IEN */
<> 139:856d2700e60b 430 #define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */
<> 139:856d2700e60b 431 #define _MSC_IEN_MASK 0x0000017FUL /**< Mask for MSC_IEN */
<> 139:856d2700e60b 432 #define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */
<> 139:856d2700e60b 433 #define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
<> 139:856d2700e60b 434 #define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
<> 139:856d2700e60b 435 #define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
<> 139:856d2700e60b 436 #define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */
<> 139:856d2700e60b 437 #define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */
<> 139:856d2700e60b 438 #define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
<> 139:856d2700e60b 439 #define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
<> 139:856d2700e60b 440 #define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
<> 139:856d2700e60b 441 #define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */
<> 139:856d2700e60b 442 #define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */
<> 139:856d2700e60b 443 #define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
<> 139:856d2700e60b 444 #define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
<> 139:856d2700e60b 445 #define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
<> 139:856d2700e60b 446 #define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */
<> 139:856d2700e60b 447 #define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */
<> 139:856d2700e60b 448 #define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
<> 139:856d2700e60b 449 #define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
<> 139:856d2700e60b 450 #define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
<> 139:856d2700e60b 451 #define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */
<> 139:856d2700e60b 452 #define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */
<> 139:856d2700e60b 453 #define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
<> 139:856d2700e60b 454 #define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
<> 139:856d2700e60b 455 #define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
<> 139:856d2700e60b 456 #define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */
<> 139:856d2700e60b 457 #define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */
<> 139:856d2700e60b 458 #define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
<> 139:856d2700e60b 459 #define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
<> 139:856d2700e60b 460 #define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
<> 139:856d2700e60b 461 #define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */
<> 139:856d2700e60b 462 #define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */
<> 139:856d2700e60b 463 #define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */
<> 139:856d2700e60b 464 #define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */
<> 139:856d2700e60b 465 #define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
<> 139:856d2700e60b 466 #define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */
<> 139:856d2700e60b 467 #define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */
<> 139:856d2700e60b 468 #define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */
<> 139:856d2700e60b 469 #define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */
<> 139:856d2700e60b 470 #define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
<> 139:856d2700e60b 471 #define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */
<> 139:856d2700e60b 472
<> 139:856d2700e60b 473 /* Bit fields for MSC LOCK */
<> 139:856d2700e60b 474 #define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */
<> 139:856d2700e60b 475 #define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */
<> 139:856d2700e60b 476 #define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
<> 139:856d2700e60b 477 #define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
<> 139:856d2700e60b 478 #define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
<> 139:856d2700e60b 479 #define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
<> 139:856d2700e60b 480 #define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */
<> 139:856d2700e60b 481 #define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */
<> 139:856d2700e60b 482 #define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
<> 139:856d2700e60b 483 #define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
<> 139:856d2700e60b 484 #define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
<> 139:856d2700e60b 485 #define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
<> 139:856d2700e60b 486 #define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */
<> 139:856d2700e60b 487 #define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
<> 139:856d2700e60b 488
<> 139:856d2700e60b 489 /* Bit fields for MSC CACHECMD */
<> 139:856d2700e60b 490 #define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */
<> 139:856d2700e60b 491 #define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */
<> 139:856d2700e60b 492 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */
<> 139:856d2700e60b 493 #define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */
<> 139:856d2700e60b 494 #define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */
<> 139:856d2700e60b 495 #define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */
<> 139:856d2700e60b 496 #define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */
<> 139:856d2700e60b 497 #define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */
<> 139:856d2700e60b 498 #define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */
<> 139:856d2700e60b 499 #define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */
<> 139:856d2700e60b 500 #define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */
<> 139:856d2700e60b 501 #define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */
<> 139:856d2700e60b 502 #define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */
<> 139:856d2700e60b 503 #define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */
<> 139:856d2700e60b 504 #define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */
<> 139:856d2700e60b 505 #define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */
<> 139:856d2700e60b 506 #define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */
<> 139:856d2700e60b 507
<> 139:856d2700e60b 508 /* Bit fields for MSC CACHEHITS */
<> 139:856d2700e60b 509 #define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */
<> 139:856d2700e60b 510 #define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */
<> 139:856d2700e60b 511 #define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */
<> 139:856d2700e60b 512 #define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */
<> 139:856d2700e60b 513 #define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */
<> 139:856d2700e60b 514 #define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */
<> 139:856d2700e60b 515
<> 139:856d2700e60b 516 /* Bit fields for MSC CACHEMISSES */
<> 139:856d2700e60b 517 #define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */
<> 139:856d2700e60b 518 #define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */
<> 139:856d2700e60b 519 #define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */
<> 139:856d2700e60b 520 #define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */
<> 139:856d2700e60b 521 #define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */
<> 139:856d2700e60b 522 #define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */
<> 139:856d2700e60b 523
<> 139:856d2700e60b 524 /* Bit fields for MSC MASSLOCK */
<> 139:856d2700e60b 525 #define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */
<> 139:856d2700e60b 526 #define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */
<> 139:856d2700e60b 527 #define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
<> 139:856d2700e60b 528 #define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
<> 139:856d2700e60b 529 #define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
<> 139:856d2700e60b 530 #define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */
<> 139:856d2700e60b 531 #define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */
<> 139:856d2700e60b 532 #define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */
<> 139:856d2700e60b 533 #define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */
<> 139:856d2700e60b 534 #define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
<> 139:856d2700e60b 535 #define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
<> 139:856d2700e60b 536 #define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */
<> 139:856d2700e60b 537 #define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */
<> 139:856d2700e60b 538 #define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */
<> 139:856d2700e60b 539
<> 139:856d2700e60b 540 /* Bit fields for MSC STARTUP */
<> 139:856d2700e60b 541 #define _MSC_STARTUP_RESETVALUE 0x1300104DUL /**< Default value for MSC_STARTUP */
<> 139:856d2700e60b 542 #define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */
<> 139:856d2700e60b 543 #define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */
<> 139:856d2700e60b 544 #define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */
<> 139:856d2700e60b 545 #define _MSC_STARTUP_STDLY0_DEFAULT 0x0000004DUL /**< Mode DEFAULT for MSC_STARTUP */
<> 139:856d2700e60b 546 #define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */
<> 139:856d2700e60b 547 #define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */
<> 139:856d2700e60b 548 #define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */
<> 139:856d2700e60b 549 #define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
<> 139:856d2700e60b 550 #define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */
<> 139:856d2700e60b 551 #define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */
<> 139:856d2700e60b 552 #define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */
<> 139:856d2700e60b 553 #define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */
<> 139:856d2700e60b 554 #define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
<> 139:856d2700e60b 555 #define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */
<> 139:856d2700e60b 556 #define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */
<> 139:856d2700e60b 557 #define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */
<> 139:856d2700e60b 558 #define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */
<> 139:856d2700e60b 559 #define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
<> 139:856d2700e60b 560 #define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */
<> 139:856d2700e60b 561 #define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */
<> 139:856d2700e60b 562 #define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */
<> 139:856d2700e60b 563 #define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */
<> 139:856d2700e60b 564 #define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */
<> 139:856d2700e60b 565 #define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */
<> 139:856d2700e60b 566 #define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */
<> 139:856d2700e60b 567 #define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */
<> 139:856d2700e60b 568 #define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
<> 139:856d2700e60b 569 #define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */
<> 139:856d2700e60b 570
<> 139:856d2700e60b 571 /* Bit fields for MSC BANKSWITCHLOCK */
<> 139:856d2700e60b 572 #define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */
<> 139:856d2700e60b 573 #define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */
<> 139:856d2700e60b 574 #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */
<> 139:856d2700e60b 575 #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */
<> 139:856d2700e60b 576 #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */
<> 139:856d2700e60b 577 #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */
<> 139:856d2700e60b 578 #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */
<> 139:856d2700e60b 579 #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */
<> 139:856d2700e60b 580 #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */
<> 139:856d2700e60b 581 #define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */
<> 139:856d2700e60b 582 #define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */
<> 139:856d2700e60b 583 #define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */
<> 139:856d2700e60b 584 #define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */
<> 139:856d2700e60b 585 #define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */
<> 139:856d2700e60b 586
<> 139:856d2700e60b 587 /* Bit fields for MSC CMD */
<> 139:856d2700e60b 588 #define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */
<> 139:856d2700e60b 589 #define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */
<> 139:856d2700e60b 590 #define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */
<> 139:856d2700e60b 591 #define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */
<> 139:856d2700e60b 592 #define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */
<> 139:856d2700e60b 593 #define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
<> 139:856d2700e60b 594 #define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */
<> 139:856d2700e60b 595 #define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */
<> 139:856d2700e60b 596 #define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */
<> 139:856d2700e60b 597 #define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */
<> 139:856d2700e60b 598 #define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
<> 139:856d2700e60b 599 #define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */
<> 139:856d2700e60b 600
<> 139:856d2700e60b 601 /* Bit fields for MSC BOOTLOADERCTRL */
<> 139:856d2700e60b 602 #define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */
<> 139:856d2700e60b 603 #define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */
<> 139:856d2700e60b 604 #define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Enable */
<> 139:856d2700e60b 605 #define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */
<> 139:856d2700e60b 606 #define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */
<> 139:856d2700e60b 607 #define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */
<> 139:856d2700e60b 608 #define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */
<> 139:856d2700e60b 609 #define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Eanble */
<> 139:856d2700e60b 610 #define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */
<> 139:856d2700e60b 611 #define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */
<> 139:856d2700e60b 612 #define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */
<> 139:856d2700e60b 613 #define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */
<> 139:856d2700e60b 614
<> 139:856d2700e60b 615 /* Bit fields for MSC AAPUNLOCKCMD */
<> 139:856d2700e60b 616 #define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */
<> 139:856d2700e60b 617 #define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */
<> 139:856d2700e60b 618 #define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software unlock AAP command */
<> 139:856d2700e60b 619 #define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */
<> 139:856d2700e60b 620 #define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */
<> 139:856d2700e60b 621 #define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */
<> 139:856d2700e60b 622 #define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */
<> 139:856d2700e60b 623
<> 139:856d2700e60b 624 /* Bit fields for MSC CACHECONFIG0 */
<> 139:856d2700e60b 625 #define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */
<> 139:856d2700e60b 626 #define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */
<> 139:856d2700e60b 627 #define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */
<> 139:856d2700e60b 628 #define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */
<> 139:856d2700e60b 629 #define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */
<> 139:856d2700e60b 630 #define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */
<> 139:856d2700e60b 631 #define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */
<> 139:856d2700e60b 632 #define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */
<> 139:856d2700e60b 633 #define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */
<> 139:856d2700e60b 634 #define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */
<> 139:856d2700e60b 635 #define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */
<> 139:856d2700e60b 636 #define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */
<> 139:856d2700e60b 637
<> 139:856d2700e60b 638 /* Bit fields for MSC RAMCTRL */
<> 139:856d2700e60b 639 #define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */
<> 139:856d2700e60b 640 #define _MSC_RAMCTRL_MASK 0x00090101UL /**< Mask for MSC_RAMCTRL */
<> 139:856d2700e60b 641 #define MSC_RAMCTRL_RAMCACHEEN (0x1UL << 0) /**< RAM CACHE Enable */
<> 139:856d2700e60b 642 #define _MSC_RAMCTRL_RAMCACHEEN_SHIFT 0 /**< Shift value for MSC_RAMCACHEEN */
<> 139:856d2700e60b 643 #define _MSC_RAMCTRL_RAMCACHEEN_MASK 0x1UL /**< Bit mask for MSC_RAMCACHEEN */
<> 139:856d2700e60b 644 #define _MSC_RAMCTRL_RAMCACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */
<> 139:856d2700e60b 645 #define MSC_RAMCTRL_RAMCACHEEN_DEFAULT (_MSC_RAMCTRL_RAMCACHEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
<> 139:856d2700e60b 646 #define MSC_RAMCTRL_RAM1CACHEEN (0x1UL << 8) /**< RAM1 CACHE Enable */
<> 139:856d2700e60b 647 #define _MSC_RAMCTRL_RAM1CACHEEN_SHIFT 8 /**< Shift value for MSC_RAM1CACHEEN */
<> 139:856d2700e60b 648 #define _MSC_RAMCTRL_RAM1CACHEEN_MASK 0x100UL /**< Bit mask for MSC_RAM1CACHEEN */
<> 139:856d2700e60b 649 #define _MSC_RAMCTRL_RAM1CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */
<> 139:856d2700e60b 650 #define MSC_RAMCTRL_RAM1CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM1CACHEEN_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
<> 139:856d2700e60b 651 #define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */
<> 139:856d2700e60b 652 #define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */
<> 139:856d2700e60b 653 #define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */
<> 139:856d2700e60b 654 #define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */
<> 139:856d2700e60b 655 #define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
<> 139:856d2700e60b 656 #define MSC_RAMCTRL_RAMSEQCACHEEN (0x1UL << 19) /**< RAMSEQ CACHE Enable */
<> 139:856d2700e60b 657 #define _MSC_RAMCTRL_RAMSEQCACHEEN_SHIFT 19 /**< Shift value for MSC_RAMSEQCACHEEN */
<> 139:856d2700e60b 658 #define _MSC_RAMCTRL_RAMSEQCACHEEN_MASK 0x80000UL /**< Bit mask for MSC_RAMSEQCACHEEN */
<> 139:856d2700e60b 659 #define _MSC_RAMCTRL_RAMSEQCACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */
<> 139:856d2700e60b 660 #define MSC_RAMCTRL_RAMSEQCACHEEN_DEFAULT (_MSC_RAMCTRL_RAMSEQCACHEEN_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
<> 139:856d2700e60b 661
<> 139:856d2700e60b 662 /** @} End of group EFM32PG12B_MSC */
<> 139:856d2700e60b 663 /** @} End of group Parts */
<> 139:856d2700e60b 664