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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32PG12_STK3402/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_i2c.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
139:856d2700e60b 
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 139:856d2700e60b 1 /**************************************************************************//**
<> 139:856d2700e60b 2 * @file efm32pg12b_i2c.h
<> 139:856d2700e60b 3 * @brief EFM32PG12B_I2C register and bit field definitions
<> 139:856d2700e60b 4 * @version 5.1.2
<> 139:856d2700e60b 5 ******************************************************************************
<> 139:856d2700e60b 6 * @section License
<> 139:856d2700e60b 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 139:856d2700e60b 8 ******************************************************************************
<> 139:856d2700e60b 9 *
<> 139:856d2700e60b 10 * Permission is granted to anyone to use this software for any purpose,
<> 139:856d2700e60b 11 * including commercial applications, and to alter it and redistribute it
<> 139:856d2700e60b 12 * freely, subject to the following restrictions:
<> 139:856d2700e60b 13 *
<> 139:856d2700e60b 14 * 1. The origin of this software must not be misrepresented; you must not
<> 139:856d2700e60b 15 * claim that you wrote the original software.@n
<> 139:856d2700e60b 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 139:856d2700e60b 17 * misrepresented as being the original software.@n
<> 139:856d2700e60b 18 * 3. This notice may not be removed or altered from any source distribution.
<> 139:856d2700e60b 19 *
<> 139:856d2700e60b 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 139:856d2700e60b 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 139:856d2700e60b 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 139:856d2700e60b 23 * kind, including, but not limited to, any implied warranties of
<> 139:856d2700e60b 24 * merchantability or fitness for any particular purpose or warranties against
<> 139:856d2700e60b 25 * infringement of any proprietary rights of a third party.
<> 139:856d2700e60b 26 *
<> 139:856d2700e60b 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 139:856d2700e60b 28 * incidental, or special damages, or any other relief, or for any claim by
<> 139:856d2700e60b 29 * any third party, arising from your use of this Software.
<> 139:856d2700e60b 30 *
<> 139:856d2700e60b 31 *****************************************************************************/
<> 139:856d2700e60b 32 /**************************************************************************//**
<> 139:856d2700e60b 33 * @addtogroup Parts
<> 139:856d2700e60b 34 * @{
<> 139:856d2700e60b 35 ******************************************************************************/
<> 139:856d2700e60b 36 /**************************************************************************//**
<> 139:856d2700e60b 37 * @defgroup EFM32PG12B_I2C
<> 139:856d2700e60b 38 * @{
<> 139:856d2700e60b 39 * @brief EFM32PG12B_I2C Register Declaration
<> 139:856d2700e60b 40 *****************************************************************************/
<> 139:856d2700e60b 41 typedef struct
<> 139:856d2700e60b 42 {
<> 139:856d2700e60b 43 __IOM uint32_t CTRL; /**< Control Register */
<> 139:856d2700e60b 44 __IOM uint32_t CMD; /**< Command Register */
<> 139:856d2700e60b 45 __IM uint32_t STATE; /**< State Register */
<> 139:856d2700e60b 46 __IM uint32_t STATUS; /**< Status Register */
<> 139:856d2700e60b 47 __IOM uint32_t CLKDIV; /**< Clock Division Register */
<> 139:856d2700e60b 48 __IOM uint32_t SADDR; /**< Slave Address Register */
<> 139:856d2700e60b 49 __IOM uint32_t SADDRMASK; /**< Slave Address Mask Register */
<> 139:856d2700e60b 50 __IM uint32_t RXDATA; /**< Receive Buffer Data Register */
<> 139:856d2700e60b 51 __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */
<> 139:856d2700e60b 52 __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */
<> 139:856d2700e60b 53 __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */
<> 139:856d2700e60b 54 __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
<> 139:856d2700e60b 55 __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */
<> 139:856d2700e60b 56 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 139:856d2700e60b 57 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 139:856d2700e60b 58 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 139:856d2700e60b 59 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 139:856d2700e60b 60 __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
<> 139:856d2700e60b 61 __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
<> 139:856d2700e60b 62 } I2C_TypeDef; /** @} */
<> 139:856d2700e60b 63
<> 139:856d2700e60b 64 /**************************************************************************//**
<> 139:856d2700e60b 65 * @defgroup EFM32PG12B_I2C_BitFields
<> 139:856d2700e60b 66 * @{
<> 139:856d2700e60b 67 *****************************************************************************/
<> 139:856d2700e60b 68
<> 139:856d2700e60b 69 /* Bit fields for I2C CTRL */
<> 139:856d2700e60b 70 #define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */
<> 139:856d2700e60b 71 #define _I2C_CTRL_MASK 0x0007B3FFUL /**< Mask for I2C_CTRL */
<> 139:856d2700e60b 72 #define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */
<> 139:856d2700e60b 73 #define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */
<> 139:856d2700e60b 74 #define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */
<> 139:856d2700e60b 75 #define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 76 #define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 77 #define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */
<> 139:856d2700e60b 78 #define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */
<> 139:856d2700e60b 79 #define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */
<> 139:856d2700e60b 80 #define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 81 #define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 82 #define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */
<> 139:856d2700e60b 83 #define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */
<> 139:856d2700e60b 84 #define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */
<> 139:856d2700e60b 85 #define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 86 #define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 87 #define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */
<> 139:856d2700e60b 88 #define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */
<> 139:856d2700e60b 89 #define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */
<> 139:856d2700e60b 90 #define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 91 #define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 92 #define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */
<> 139:856d2700e60b 93 #define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */
<> 139:856d2700e60b 94 #define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */
<> 139:856d2700e60b 95 #define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 96 #define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 97 #define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */
<> 139:856d2700e60b 98 #define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */
<> 139:856d2700e60b 99 #define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */
<> 139:856d2700e60b 100 #define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 101 #define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 102 #define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */
<> 139:856d2700e60b 103 #define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */
<> 139:856d2700e60b 104 #define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */
<> 139:856d2700e60b 105 #define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 106 #define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 107 #define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */
<> 139:856d2700e60b 108 #define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */
<> 139:856d2700e60b 109 #define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */
<> 139:856d2700e60b 110 #define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 111 #define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */
<> 139:856d2700e60b 112 #define _I2C_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for I2C_CTRL */
<> 139:856d2700e60b 113 #define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 114 #define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */
<> 139:856d2700e60b 115 #define I2C_CTRL_TXBIL_HALFFULL (_I2C_CTRL_TXBIL_HALFFULL << 7) /**< Shifted mode HALFFULL for I2C_CTRL */
<> 139:856d2700e60b 116 #define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */
<> 139:856d2700e60b 117 #define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */
<> 139:856d2700e60b 118 #define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 119 #define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */
<> 139:856d2700e60b 120 #define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */
<> 139:856d2700e60b 121 #define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */
<> 139:856d2700e60b 122 #define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 123 #define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */
<> 139:856d2700e60b 124 #define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */
<> 139:856d2700e60b 125 #define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */
<> 139:856d2700e60b 126 #define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */
<> 139:856d2700e60b 127 #define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */
<> 139:856d2700e60b 128 #define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 129 #define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
<> 139:856d2700e60b 130 #define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
<> 139:856d2700e60b 131 #define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
<> 139:856d2700e60b 132 #define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
<> 139:856d2700e60b 133 #define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 134 #define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */
<> 139:856d2700e60b 135 #define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */
<> 139:856d2700e60b 136 #define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */
<> 139:856d2700e60b 137 #define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */
<> 139:856d2700e60b 138 #define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */
<> 139:856d2700e60b 139 #define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */
<> 139:856d2700e60b 140 #define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */
<> 139:856d2700e60b 141 #define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 142 #define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 143 #define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */
<> 139:856d2700e60b 144 #define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */
<> 139:856d2700e60b 145 #define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 146 #define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
<> 139:856d2700e60b 147 #define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
<> 139:856d2700e60b 148 #define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
<> 139:856d2700e60b 149 #define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
<> 139:856d2700e60b 150 #define _I2C_CTRL_CLTO_320PCC 0x00000004UL /**< Mode 320PCC for I2C_CTRL */
<> 139:856d2700e60b 151 #define _I2C_CTRL_CLTO_1024PCC 0x00000005UL /**< Mode 1024PCC for I2C_CTRL */
<> 139:856d2700e60b 152 #define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 139:856d2700e60b 153 #define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */
<> 139:856d2700e60b 154 #define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */
<> 139:856d2700e60b 155 #define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */
<> 139:856d2700e60b 156 #define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */
<> 139:856d2700e60b 157 #define I2C_CTRL_CLTO_320PCC (_I2C_CTRL_CLTO_320PCC << 16) /**< Shifted mode 320PCC for I2C_CTRL */
<> 139:856d2700e60b 158 #define I2C_CTRL_CLTO_1024PCC (_I2C_CTRL_CLTO_1024PCC << 16) /**< Shifted mode 1024PCC for I2C_CTRL */
<> 139:856d2700e60b 159
<> 139:856d2700e60b 160 /* Bit fields for I2C CMD */
<> 139:856d2700e60b 161 #define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */
<> 139:856d2700e60b 162 #define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */
<> 139:856d2700e60b 163 #define I2C_CMD_START (0x1UL << 0) /**< Send start condition */
<> 139:856d2700e60b 164 #define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */
<> 139:856d2700e60b 165 #define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */
<> 139:856d2700e60b 166 #define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 139:856d2700e60b 167 #define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */
<> 139:856d2700e60b 168 #define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */
<> 139:856d2700e60b 169 #define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */
<> 139:856d2700e60b 170 #define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */
<> 139:856d2700e60b 171 #define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 139:856d2700e60b 172 #define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */
<> 139:856d2700e60b 173 #define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */
<> 139:856d2700e60b 174 #define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */
<> 139:856d2700e60b 175 #define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */
<> 139:856d2700e60b 176 #define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 139:856d2700e60b 177 #define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */
<> 139:856d2700e60b 178 #define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */
<> 139:856d2700e60b 179 #define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */
<> 139:856d2700e60b 180 #define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */
<> 139:856d2700e60b 181 #define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 139:856d2700e60b 182 #define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */
<> 139:856d2700e60b 183 #define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */
<> 139:856d2700e60b 184 #define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */
<> 139:856d2700e60b 185 #define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */
<> 139:856d2700e60b 186 #define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 139:856d2700e60b 187 #define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */
<> 139:856d2700e60b 188 #define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */
<> 139:856d2700e60b 189 #define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */
<> 139:856d2700e60b 190 #define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */
<> 139:856d2700e60b 191 #define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 139:856d2700e60b 192 #define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */
<> 139:856d2700e60b 193 #define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
<> 139:856d2700e60b 194 #define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */
<> 139:856d2700e60b 195 #define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */
<> 139:856d2700e60b 196 #define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 139:856d2700e60b 197 #define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */
<> 139:856d2700e60b 198 #define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */
<> 139:856d2700e60b 199 #define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */
<> 139:856d2700e60b 200 #define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */
<> 139:856d2700e60b 201 #define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 139:856d2700e60b 202 #define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */
<> 139:856d2700e60b 203
<> 139:856d2700e60b 204 /* Bit fields for I2C STATE */
<> 139:856d2700e60b 205 #define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */
<> 139:856d2700e60b 206 #define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */
<> 139:856d2700e60b 207 #define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */
<> 139:856d2700e60b 208 #define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */
<> 139:856d2700e60b 209 #define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */
<> 139:856d2700e60b 210 #define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */
<> 139:856d2700e60b 211 #define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */
<> 139:856d2700e60b 212 #define I2C_STATE_MASTER (0x1UL << 1) /**< Master */
<> 139:856d2700e60b 213 #define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */
<> 139:856d2700e60b 214 #define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */
<> 139:856d2700e60b 215 #define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
<> 139:856d2700e60b 216 #define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */
<> 139:856d2700e60b 217 #define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */
<> 139:856d2700e60b 218 #define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */
<> 139:856d2700e60b 219 #define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */
<> 139:856d2700e60b 220 #define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
<> 139:856d2700e60b 221 #define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */
<> 139:856d2700e60b 222 #define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */
<> 139:856d2700e60b 223 #define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */
<> 139:856d2700e60b 224 #define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */
<> 139:856d2700e60b 225 #define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
<> 139:856d2700e60b 226 #define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */
<> 139:856d2700e60b 227 #define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */
<> 139:856d2700e60b 228 #define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */
<> 139:856d2700e60b 229 #define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */
<> 139:856d2700e60b 230 #define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
<> 139:856d2700e60b 231 #define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */
<> 139:856d2700e60b 232 #define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */
<> 139:856d2700e60b 233 #define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */
<> 139:856d2700e60b 234 #define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
<> 139:856d2700e60b 235 #define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */
<> 139:856d2700e60b 236 #define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */
<> 139:856d2700e60b 237 #define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */
<> 139:856d2700e60b 238 #define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */
<> 139:856d2700e60b 239 #define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */
<> 139:856d2700e60b 240 #define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */
<> 139:856d2700e60b 241 #define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */
<> 139:856d2700e60b 242 #define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */
<> 139:856d2700e60b 243 #define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */
<> 139:856d2700e60b 244 #define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */
<> 139:856d2700e60b 245 #define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */
<> 139:856d2700e60b 246 #define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */
<> 139:856d2700e60b 247 #define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */
<> 139:856d2700e60b 248 #define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */
<> 139:856d2700e60b 249 #define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */
<> 139:856d2700e60b 250
<> 139:856d2700e60b 251 /* Bit fields for I2C STATUS */
<> 139:856d2700e60b 252 #define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */
<> 139:856d2700e60b 253 #define _I2C_STATUS_MASK 0x000003FFUL /**< Mask for I2C_STATUS */
<> 139:856d2700e60b 254 #define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */
<> 139:856d2700e60b 255 #define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */
<> 139:856d2700e60b 256 #define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */
<> 139:856d2700e60b 257 #define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 139:856d2700e60b 258 #define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 139:856d2700e60b 259 #define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */
<> 139:856d2700e60b 260 #define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */
<> 139:856d2700e60b 261 #define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */
<> 139:856d2700e60b 262 #define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 139:856d2700e60b 263 #define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 139:856d2700e60b 264 #define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */
<> 139:856d2700e60b 265 #define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */
<> 139:856d2700e60b 266 #define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */
<> 139:856d2700e60b 267 #define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 139:856d2700e60b 268 #define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 139:856d2700e60b 269 #define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */
<> 139:856d2700e60b 270 #define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */
<> 139:856d2700e60b 271 #define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */
<> 139:856d2700e60b 272 #define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 139:856d2700e60b 273 #define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 139:856d2700e60b 274 #define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */
<> 139:856d2700e60b 275 #define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */
<> 139:856d2700e60b 276 #define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */
<> 139:856d2700e60b 277 #define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 139:856d2700e60b 278 #define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 139:856d2700e60b 279 #define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */
<> 139:856d2700e60b 280 #define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */
<> 139:856d2700e60b 281 #define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */
<> 139:856d2700e60b 282 #define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 139:856d2700e60b 283 #define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 139:856d2700e60b 284 #define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */
<> 139:856d2700e60b 285 #define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */
<> 139:856d2700e60b 286 #define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */
<> 139:856d2700e60b 287 #define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 139:856d2700e60b 288 #define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 139:856d2700e60b 289 #define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */
<> 139:856d2700e60b 290 #define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */
<> 139:856d2700e60b 291 #define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */
<> 139:856d2700e60b 292 #define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */
<> 139:856d2700e60b 293 #define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 139:856d2700e60b 294 #define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */
<> 139:856d2700e60b 295 #define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */
<> 139:856d2700e60b 296 #define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */
<> 139:856d2700e60b 297 #define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 139:856d2700e60b 298 #define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 139:856d2700e60b 299 #define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */
<> 139:856d2700e60b 300 #define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */
<> 139:856d2700e60b 301 #define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */
<> 139:856d2700e60b 302 #define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 139:856d2700e60b 303 #define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 139:856d2700e60b 304
<> 139:856d2700e60b 305 /* Bit fields for I2C CLKDIV */
<> 139:856d2700e60b 306 #define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */
<> 139:856d2700e60b 307 #define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */
<> 139:856d2700e60b 308 #define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */
<> 139:856d2700e60b 309 #define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */
<> 139:856d2700e60b 310 #define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */
<> 139:856d2700e60b 311 #define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */
<> 139:856d2700e60b 312
<> 139:856d2700e60b 313 /* Bit fields for I2C SADDR */
<> 139:856d2700e60b 314 #define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */
<> 139:856d2700e60b 315 #define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */
<> 139:856d2700e60b 316 #define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */
<> 139:856d2700e60b 317 #define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */
<> 139:856d2700e60b 318 #define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */
<> 139:856d2700e60b 319 #define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */
<> 139:856d2700e60b 320
<> 139:856d2700e60b 321 /* Bit fields for I2C SADDRMASK */
<> 139:856d2700e60b 322 #define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */
<> 139:856d2700e60b 323 #define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */
<> 139:856d2700e60b 324 #define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */
<> 139:856d2700e60b 325 #define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */
<> 139:856d2700e60b 326 #define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */
<> 139:856d2700e60b 327 #define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */
<> 139:856d2700e60b 328
<> 139:856d2700e60b 329 /* Bit fields for I2C RXDATA */
<> 139:856d2700e60b 330 #define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */
<> 139:856d2700e60b 331 #define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */
<> 139:856d2700e60b 332 #define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */
<> 139:856d2700e60b 333 #define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */
<> 139:856d2700e60b 334 #define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */
<> 139:856d2700e60b 335 #define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */
<> 139:856d2700e60b 336
<> 139:856d2700e60b 337 /* Bit fields for I2C RXDOUBLE */
<> 139:856d2700e60b 338 #define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */
<> 139:856d2700e60b 339 #define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */
<> 139:856d2700e60b 340 #define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */
<> 139:856d2700e60b 341 #define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */
<> 139:856d2700e60b 342 #define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */
<> 139:856d2700e60b 343 #define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
<> 139:856d2700e60b 344 #define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */
<> 139:856d2700e60b 345 #define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */
<> 139:856d2700e60b 346 #define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */
<> 139:856d2700e60b 347 #define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
<> 139:856d2700e60b 348
<> 139:856d2700e60b 349 /* Bit fields for I2C RXDATAP */
<> 139:856d2700e60b 350 #define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */
<> 139:856d2700e60b 351 #define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */
<> 139:856d2700e60b 352 #define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */
<> 139:856d2700e60b 353 #define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */
<> 139:856d2700e60b 354 #define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */
<> 139:856d2700e60b 355 #define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */
<> 139:856d2700e60b 356
<> 139:856d2700e60b 357 /* Bit fields for I2C RXDOUBLEP */
<> 139:856d2700e60b 358 #define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */
<> 139:856d2700e60b 359 #define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */
<> 139:856d2700e60b 360 #define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */
<> 139:856d2700e60b 361 #define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */
<> 139:856d2700e60b 362 #define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */
<> 139:856d2700e60b 363 #define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
<> 139:856d2700e60b 364 #define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */
<> 139:856d2700e60b 365 #define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */
<> 139:856d2700e60b 366 #define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */
<> 139:856d2700e60b 367 #define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
<> 139:856d2700e60b 368
<> 139:856d2700e60b 369 /* Bit fields for I2C TXDATA */
<> 139:856d2700e60b 370 #define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */
<> 139:856d2700e60b 371 #define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */
<> 139:856d2700e60b 372 #define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */
<> 139:856d2700e60b 373 #define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */
<> 139:856d2700e60b 374 #define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */
<> 139:856d2700e60b 375 #define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */
<> 139:856d2700e60b 376
<> 139:856d2700e60b 377 /* Bit fields for I2C TXDOUBLE */
<> 139:856d2700e60b 378 #define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */
<> 139:856d2700e60b 379 #define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */
<> 139:856d2700e60b 380 #define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */
<> 139:856d2700e60b 381 #define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */
<> 139:856d2700e60b 382 #define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */
<> 139:856d2700e60b 383 #define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
<> 139:856d2700e60b 384 #define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */
<> 139:856d2700e60b 385 #define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */
<> 139:856d2700e60b 386 #define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */
<> 139:856d2700e60b 387 #define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
<> 139:856d2700e60b 388
<> 139:856d2700e60b 389 /* Bit fields for I2C IF */
<> 139:856d2700e60b 390 #define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */
<> 139:856d2700e60b 391 #define _I2C_IF_MASK 0x0007FFFFUL /**< Mask for I2C_IF */
<> 139:856d2700e60b 392 #define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */
<> 139:856d2700e60b 393 #define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */
<> 139:856d2700e60b 394 #define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */
<> 139:856d2700e60b 395 #define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 396 #define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 397 #define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */
<> 139:856d2700e60b 398 #define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
<> 139:856d2700e60b 399 #define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
<> 139:856d2700e60b 400 #define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 401 #define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 402 #define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */
<> 139:856d2700e60b 403 #define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
<> 139:856d2700e60b 404 #define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
<> 139:856d2700e60b 405 #define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 406 #define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 407 #define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */
<> 139:856d2700e60b 408 #define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
<> 139:856d2700e60b 409 #define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
<> 139:856d2700e60b 410 #define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 411 #define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 412 #define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */
<> 139:856d2700e60b 413 #define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
<> 139:856d2700e60b 414 #define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
<> 139:856d2700e60b 415 #define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 416 #define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 417 #define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */
<> 139:856d2700e60b 418 #define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
<> 139:856d2700e60b 419 #define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
<> 139:856d2700e60b 420 #define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 421 #define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 422 #define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */
<> 139:856d2700e60b 423 #define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
<> 139:856d2700e60b 424 #define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
<> 139:856d2700e60b 425 #define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 426 #define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 427 #define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */
<> 139:856d2700e60b 428 #define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
<> 139:856d2700e60b 429 #define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
<> 139:856d2700e60b 430 #define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 431 #define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 432 #define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */
<> 139:856d2700e60b 433 #define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
<> 139:856d2700e60b 434 #define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
<> 139:856d2700e60b 435 #define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 436 #define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 437 #define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */
<> 139:856d2700e60b 438 #define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
<> 139:856d2700e60b 439 #define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
<> 139:856d2700e60b 440 #define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 441 #define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 442 #define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */
<> 139:856d2700e60b 443 #define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
<> 139:856d2700e60b 444 #define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
<> 139:856d2700e60b 445 #define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 446 #define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 447 #define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */
<> 139:856d2700e60b 448 #define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
<> 139:856d2700e60b 449 #define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
<> 139:856d2700e60b 450 #define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 451 #define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 452 #define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */
<> 139:856d2700e60b 453 #define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
<> 139:856d2700e60b 454 #define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
<> 139:856d2700e60b 455 #define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 456 #define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 457 #define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */
<> 139:856d2700e60b 458 #define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
<> 139:856d2700e60b 459 #define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
<> 139:856d2700e60b 460 #define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 461 #define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 462 #define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */
<> 139:856d2700e60b 463 #define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
<> 139:856d2700e60b 464 #define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
<> 139:856d2700e60b 465 #define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 466 #define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 467 #define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */
<> 139:856d2700e60b 468 #define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
<> 139:856d2700e60b 469 #define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
<> 139:856d2700e60b 470 #define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 471 #define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 472 #define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP condition Interrupt Flag */
<> 139:856d2700e60b 473 #define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
<> 139:856d2700e60b 474 #define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
<> 139:856d2700e60b 475 #define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 476 #define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 477 #define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */
<> 139:856d2700e60b 478 #define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
<> 139:856d2700e60b 479 #define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
<> 139:856d2700e60b 480 #define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 481 #define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 482 #define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */
<> 139:856d2700e60b 483 #define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
<> 139:856d2700e60b 484 #define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
<> 139:856d2700e60b 485 #define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 486 #define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */
<> 139:856d2700e60b 487
<> 139:856d2700e60b 488 /* Bit fields for I2C IFS */
<> 139:856d2700e60b 489 #define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */
<> 139:856d2700e60b 490 #define _I2C_IFS_MASK 0x0007FFCFUL /**< Mask for I2C_IFS */
<> 139:856d2700e60b 491 #define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */
<> 139:856d2700e60b 492 #define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */
<> 139:856d2700e60b 493 #define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */
<> 139:856d2700e60b 494 #define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 495 #define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 496 #define I2C_IFS_RSTART (0x1UL << 1) /**< Set RSTART Interrupt Flag */
<> 139:856d2700e60b 497 #define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
<> 139:856d2700e60b 498 #define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
<> 139:856d2700e60b 499 #define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 500 #define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 501 #define I2C_IFS_ADDR (0x1UL << 2) /**< Set ADDR Interrupt Flag */
<> 139:856d2700e60b 502 #define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
<> 139:856d2700e60b 503 #define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
<> 139:856d2700e60b 504 #define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 505 #define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 506 #define I2C_IFS_TXC (0x1UL << 3) /**< Set TXC Interrupt Flag */
<> 139:856d2700e60b 507 #define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
<> 139:856d2700e60b 508 #define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
<> 139:856d2700e60b 509 #define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 510 #define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 511 #define I2C_IFS_ACK (0x1UL << 6) /**< Set ACK Interrupt Flag */
<> 139:856d2700e60b 512 #define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
<> 139:856d2700e60b 513 #define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
<> 139:856d2700e60b 514 #define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 515 #define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 516 #define I2C_IFS_NACK (0x1UL << 7) /**< Set NACK Interrupt Flag */
<> 139:856d2700e60b 517 #define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
<> 139:856d2700e60b 518 #define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
<> 139:856d2700e60b 519 #define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 520 #define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 521 #define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */
<> 139:856d2700e60b 522 #define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
<> 139:856d2700e60b 523 #define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
<> 139:856d2700e60b 524 #define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 525 #define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 526 #define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set ARBLOST Interrupt Flag */
<> 139:856d2700e60b 527 #define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
<> 139:856d2700e60b 528 #define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
<> 139:856d2700e60b 529 #define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 530 #define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 531 #define I2C_IFS_BUSERR (0x1UL << 10) /**< Set BUSERR Interrupt Flag */
<> 139:856d2700e60b 532 #define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
<> 139:856d2700e60b 533 #define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
<> 139:856d2700e60b 534 #define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 535 #define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 536 #define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set BUSHOLD Interrupt Flag */
<> 139:856d2700e60b 537 #define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
<> 139:856d2700e60b 538 #define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
<> 139:856d2700e60b 539 #define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 540 #define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 541 #define I2C_IFS_TXOF (0x1UL << 12) /**< Set TXOF Interrupt Flag */
<> 139:856d2700e60b 542 #define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
<> 139:856d2700e60b 543 #define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
<> 139:856d2700e60b 544 #define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 545 #define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 546 #define I2C_IFS_RXUF (0x1UL << 13) /**< Set RXUF Interrupt Flag */
<> 139:856d2700e60b 547 #define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
<> 139:856d2700e60b 548 #define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
<> 139:856d2700e60b 549 #define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 550 #define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 551 #define I2C_IFS_BITO (0x1UL << 14) /**< Set BITO Interrupt Flag */
<> 139:856d2700e60b 552 #define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
<> 139:856d2700e60b 553 #define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
<> 139:856d2700e60b 554 #define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 555 #define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 556 #define I2C_IFS_CLTO (0x1UL << 15) /**< Set CLTO Interrupt Flag */
<> 139:856d2700e60b 557 #define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
<> 139:856d2700e60b 558 #define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
<> 139:856d2700e60b 559 #define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 560 #define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 561 #define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */
<> 139:856d2700e60b 562 #define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
<> 139:856d2700e60b 563 #define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
<> 139:856d2700e60b 564 #define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 565 #define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 566 #define I2C_IFS_RXFULL (0x1UL << 17) /**< Set RXFULL Interrupt Flag */
<> 139:856d2700e60b 567 #define _I2C_IFS_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
<> 139:856d2700e60b 568 #define _I2C_IFS_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
<> 139:856d2700e60b 569 #define _I2C_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 570 #define I2C_IFS_RXFULL_DEFAULT (_I2C_IFS_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 571 #define I2C_IFS_CLERR (0x1UL << 18) /**< Set CLERR Interrupt Flag */
<> 139:856d2700e60b 572 #define _I2C_IFS_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
<> 139:856d2700e60b 573 #define _I2C_IFS_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
<> 139:856d2700e60b 574 #define _I2C_IFS_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 575 #define I2C_IFS_CLERR_DEFAULT (_I2C_IFS_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFS */
<> 139:856d2700e60b 576
<> 139:856d2700e60b 577 /* Bit fields for I2C IFC */
<> 139:856d2700e60b 578 #define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */
<> 139:856d2700e60b 579 #define _I2C_IFC_MASK 0x0007FFCFUL /**< Mask for I2C_IFC */
<> 139:856d2700e60b 580 #define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */
<> 139:856d2700e60b 581 #define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */
<> 139:856d2700e60b 582 #define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */
<> 139:856d2700e60b 583 #define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 584 #define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 585 #define I2C_IFC_RSTART (0x1UL << 1) /**< Clear RSTART Interrupt Flag */
<> 139:856d2700e60b 586 #define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
<> 139:856d2700e60b 587 #define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
<> 139:856d2700e60b 588 #define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 589 #define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 590 #define I2C_IFC_ADDR (0x1UL << 2) /**< Clear ADDR Interrupt Flag */
<> 139:856d2700e60b 591 #define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
<> 139:856d2700e60b 592 #define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
<> 139:856d2700e60b 593 #define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 594 #define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 595 #define I2C_IFC_TXC (0x1UL << 3) /**< Clear TXC Interrupt Flag */
<> 139:856d2700e60b 596 #define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
<> 139:856d2700e60b 597 #define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
<> 139:856d2700e60b 598 #define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 599 #define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 600 #define I2C_IFC_ACK (0x1UL << 6) /**< Clear ACK Interrupt Flag */
<> 139:856d2700e60b 601 #define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
<> 139:856d2700e60b 602 #define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
<> 139:856d2700e60b 603 #define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 604 #define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 605 #define I2C_IFC_NACK (0x1UL << 7) /**< Clear NACK Interrupt Flag */
<> 139:856d2700e60b 606 #define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
<> 139:856d2700e60b 607 #define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
<> 139:856d2700e60b 608 #define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 609 #define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 610 #define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */
<> 139:856d2700e60b 611 #define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
<> 139:856d2700e60b 612 #define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
<> 139:856d2700e60b 613 #define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 614 #define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 615 #define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear ARBLOST Interrupt Flag */
<> 139:856d2700e60b 616 #define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
<> 139:856d2700e60b 617 #define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
<> 139:856d2700e60b 618 #define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 619 #define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 620 #define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear BUSERR Interrupt Flag */
<> 139:856d2700e60b 621 #define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
<> 139:856d2700e60b 622 #define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
<> 139:856d2700e60b 623 #define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 624 #define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 625 #define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear BUSHOLD Interrupt Flag */
<> 139:856d2700e60b 626 #define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
<> 139:856d2700e60b 627 #define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
<> 139:856d2700e60b 628 #define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 629 #define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 630 #define I2C_IFC_TXOF (0x1UL << 12) /**< Clear TXOF Interrupt Flag */
<> 139:856d2700e60b 631 #define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
<> 139:856d2700e60b 632 #define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
<> 139:856d2700e60b 633 #define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 634 #define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 635 #define I2C_IFC_RXUF (0x1UL << 13) /**< Clear RXUF Interrupt Flag */
<> 139:856d2700e60b 636 #define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
<> 139:856d2700e60b 637 #define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
<> 139:856d2700e60b 638 #define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 639 #define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 640 #define I2C_IFC_BITO (0x1UL << 14) /**< Clear BITO Interrupt Flag */
<> 139:856d2700e60b 641 #define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
<> 139:856d2700e60b 642 #define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
<> 139:856d2700e60b 643 #define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 644 #define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 645 #define I2C_IFC_CLTO (0x1UL << 15) /**< Clear CLTO Interrupt Flag */
<> 139:856d2700e60b 646 #define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
<> 139:856d2700e60b 647 #define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
<> 139:856d2700e60b 648 #define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 649 #define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 650 #define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */
<> 139:856d2700e60b 651 #define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
<> 139:856d2700e60b 652 #define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
<> 139:856d2700e60b 653 #define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 654 #define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 655 #define I2C_IFC_RXFULL (0x1UL << 17) /**< Clear RXFULL Interrupt Flag */
<> 139:856d2700e60b 656 #define _I2C_IFC_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
<> 139:856d2700e60b 657 #define _I2C_IFC_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
<> 139:856d2700e60b 658 #define _I2C_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 659 #define I2C_IFC_RXFULL_DEFAULT (_I2C_IFC_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 660 #define I2C_IFC_CLERR (0x1UL << 18) /**< Clear CLERR Interrupt Flag */
<> 139:856d2700e60b 661 #define _I2C_IFC_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
<> 139:856d2700e60b 662 #define _I2C_IFC_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
<> 139:856d2700e60b 663 #define _I2C_IFC_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 664 #define I2C_IFC_CLERR_DEFAULT (_I2C_IFC_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFC */
<> 139:856d2700e60b 665
<> 139:856d2700e60b 666 /* Bit fields for I2C IEN */
<> 139:856d2700e60b 667 #define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */
<> 139:856d2700e60b 668 #define _I2C_IEN_MASK 0x0007FFFFUL /**< Mask for I2C_IEN */
<> 139:856d2700e60b 669 #define I2C_IEN_START (0x1UL << 0) /**< START Interrupt Enable */
<> 139:856d2700e60b 670 #define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */
<> 139:856d2700e60b 671 #define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */
<> 139:856d2700e60b 672 #define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 673 #define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 674 #define I2C_IEN_RSTART (0x1UL << 1) /**< RSTART Interrupt Enable */
<> 139:856d2700e60b 675 #define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
<> 139:856d2700e60b 676 #define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
<> 139:856d2700e60b 677 #define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 678 #define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 679 #define I2C_IEN_ADDR (0x1UL << 2) /**< ADDR Interrupt Enable */
<> 139:856d2700e60b 680 #define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
<> 139:856d2700e60b 681 #define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
<> 139:856d2700e60b 682 #define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 683 #define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 684 #define I2C_IEN_TXC (0x1UL << 3) /**< TXC Interrupt Enable */
<> 139:856d2700e60b 685 #define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
<> 139:856d2700e60b 686 #define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
<> 139:856d2700e60b 687 #define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 688 #define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 689 #define I2C_IEN_TXBL (0x1UL << 4) /**< TXBL Interrupt Enable */
<> 139:856d2700e60b 690 #define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
<> 139:856d2700e60b 691 #define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
<> 139:856d2700e60b 692 #define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 693 #define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 694 #define I2C_IEN_RXDATAV (0x1UL << 5) /**< RXDATAV Interrupt Enable */
<> 139:856d2700e60b 695 #define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
<> 139:856d2700e60b 696 #define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
<> 139:856d2700e60b 697 #define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 698 #define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 699 #define I2C_IEN_ACK (0x1UL << 6) /**< ACK Interrupt Enable */
<> 139:856d2700e60b 700 #define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
<> 139:856d2700e60b 701 #define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
<> 139:856d2700e60b 702 #define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 703 #define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 704 #define I2C_IEN_NACK (0x1UL << 7) /**< NACK Interrupt Enable */
<> 139:856d2700e60b 705 #define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
<> 139:856d2700e60b 706 #define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
<> 139:856d2700e60b 707 #define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 708 #define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 709 #define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */
<> 139:856d2700e60b 710 #define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
<> 139:856d2700e60b 711 #define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
<> 139:856d2700e60b 712 #define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 713 #define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 714 #define I2C_IEN_ARBLOST (0x1UL << 9) /**< ARBLOST Interrupt Enable */
<> 139:856d2700e60b 715 #define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
<> 139:856d2700e60b 716 #define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
<> 139:856d2700e60b 717 #define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 718 #define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 719 #define I2C_IEN_BUSERR (0x1UL << 10) /**< BUSERR Interrupt Enable */
<> 139:856d2700e60b 720 #define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
<> 139:856d2700e60b 721 #define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
<> 139:856d2700e60b 722 #define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 723 #define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 724 #define I2C_IEN_BUSHOLD (0x1UL << 11) /**< BUSHOLD Interrupt Enable */
<> 139:856d2700e60b 725 #define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
<> 139:856d2700e60b 726 #define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
<> 139:856d2700e60b 727 #define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 728 #define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 729 #define I2C_IEN_TXOF (0x1UL << 12) /**< TXOF Interrupt Enable */
<> 139:856d2700e60b 730 #define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
<> 139:856d2700e60b 731 #define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
<> 139:856d2700e60b 732 #define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 733 #define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 734 #define I2C_IEN_RXUF (0x1UL << 13) /**< RXUF Interrupt Enable */
<> 139:856d2700e60b 735 #define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
<> 139:856d2700e60b 736 #define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
<> 139:856d2700e60b 737 #define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 738 #define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 739 #define I2C_IEN_BITO (0x1UL << 14) /**< BITO Interrupt Enable */
<> 139:856d2700e60b 740 #define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
<> 139:856d2700e60b 741 #define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
<> 139:856d2700e60b 742 #define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 743 #define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 744 #define I2C_IEN_CLTO (0x1UL << 15) /**< CLTO Interrupt Enable */
<> 139:856d2700e60b 745 #define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
<> 139:856d2700e60b 746 #define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
<> 139:856d2700e60b 747 #define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 748 #define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 749 #define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */
<> 139:856d2700e60b 750 #define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
<> 139:856d2700e60b 751 #define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
<> 139:856d2700e60b 752 #define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 753 #define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 754 #define I2C_IEN_RXFULL (0x1UL << 17) /**< RXFULL Interrupt Enable */
<> 139:856d2700e60b 755 #define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
<> 139:856d2700e60b 756 #define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
<> 139:856d2700e60b 757 #define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 758 #define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 759 #define I2C_IEN_CLERR (0x1UL << 18) /**< CLERR Interrupt Enable */
<> 139:856d2700e60b 760 #define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
<> 139:856d2700e60b 761 #define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
<> 139:856d2700e60b 762 #define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 763 #define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */
<> 139:856d2700e60b 764
<> 139:856d2700e60b 765 /* Bit fields for I2C ROUTEPEN */
<> 139:856d2700e60b 766 #define _I2C_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTEPEN */
<> 139:856d2700e60b 767 #define _I2C_ROUTEPEN_MASK 0x00000003UL /**< Mask for I2C_ROUTEPEN */
<> 139:856d2700e60b 768 #define I2C_ROUTEPEN_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */
<> 139:856d2700e60b 769 #define _I2C_ROUTEPEN_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */
<> 139:856d2700e60b 770 #define _I2C_ROUTEPEN_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */
<> 139:856d2700e60b 771 #define _I2C_ROUTEPEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */
<> 139:856d2700e60b 772 #define I2C_ROUTEPEN_SDAPEN_DEFAULT (_I2C_ROUTEPEN_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */
<> 139:856d2700e60b 773 #define I2C_ROUTEPEN_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */
<> 139:856d2700e60b 774 #define _I2C_ROUTEPEN_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */
<> 139:856d2700e60b 775 #define _I2C_ROUTEPEN_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */
<> 139:856d2700e60b 776 #define _I2C_ROUTEPEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */
<> 139:856d2700e60b 777 #define I2C_ROUTEPEN_SCLPEN_DEFAULT (_I2C_ROUTEPEN_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */
<> 139:856d2700e60b 778
<> 139:856d2700e60b 779 /* Bit fields for I2C ROUTELOC0 */
<> 139:856d2700e60b 780 #define _I2C_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTELOC0 */
<> 139:856d2700e60b 781 #define _I2C_ROUTELOC0_MASK 0x00001F1FUL /**< Mask for I2C_ROUTELOC0 */
<> 139:856d2700e60b 782 #define _I2C_ROUTELOC0_SDALOC_SHIFT 0 /**< Shift value for I2C_SDALOC */
<> 139:856d2700e60b 783 #define _I2C_ROUTELOC0_SDALOC_MASK 0x1FUL /**< Bit mask for I2C_SDALOC */
<> 139:856d2700e60b 784 #define _I2C_ROUTELOC0_SDALOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 785 #define _I2C_ROUTELOC0_SDALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */
<> 139:856d2700e60b 786 #define _I2C_ROUTELOC0_SDALOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 787 #define _I2C_ROUTELOC0_SDALOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 788 #define _I2C_ROUTELOC0_SDALOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 789 #define _I2C_ROUTELOC0_SDALOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 790 #define _I2C_ROUTELOC0_SDALOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 791 #define _I2C_ROUTELOC0_SDALOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 792 #define _I2C_ROUTELOC0_SDALOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 793 #define _I2C_ROUTELOC0_SDALOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 794 #define _I2C_ROUTELOC0_SDALOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 795 #define _I2C_ROUTELOC0_SDALOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 796 #define _I2C_ROUTELOC0_SDALOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 797 #define _I2C_ROUTELOC0_SDALOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 798 #define _I2C_ROUTELOC0_SDALOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 799 #define _I2C_ROUTELOC0_SDALOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 800 #define _I2C_ROUTELOC0_SDALOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 801 #define _I2C_ROUTELOC0_SDALOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 802 #define _I2C_ROUTELOC0_SDALOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 803 #define _I2C_ROUTELOC0_SDALOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 804 #define _I2C_ROUTELOC0_SDALOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 805 #define _I2C_ROUTELOC0_SDALOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 806 #define _I2C_ROUTELOC0_SDALOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 807 #define _I2C_ROUTELOC0_SDALOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 808 #define _I2C_ROUTELOC0_SDALOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 809 #define _I2C_ROUTELOC0_SDALOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 810 #define _I2C_ROUTELOC0_SDALOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 811 #define _I2C_ROUTELOC0_SDALOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 812 #define _I2C_ROUTELOC0_SDALOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 813 #define _I2C_ROUTELOC0_SDALOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 814 #define _I2C_ROUTELOC0_SDALOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 815 #define _I2C_ROUTELOC0_SDALOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 816 #define _I2C_ROUTELOC0_SDALOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 817 #define I2C_ROUTELOC0_SDALOC_LOC0 (_I2C_ROUTELOC0_SDALOC_LOC0 << 0) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 818 #define I2C_ROUTELOC0_SDALOC_DEFAULT (_I2C_ROUTELOC0_SDALOC_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */
<> 139:856d2700e60b 819 #define I2C_ROUTELOC0_SDALOC_LOC1 (_I2C_ROUTELOC0_SDALOC_LOC1 << 0) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 820 #define I2C_ROUTELOC0_SDALOC_LOC2 (_I2C_ROUTELOC0_SDALOC_LOC2 << 0) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 821 #define I2C_ROUTELOC0_SDALOC_LOC3 (_I2C_ROUTELOC0_SDALOC_LOC3 << 0) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 822 #define I2C_ROUTELOC0_SDALOC_LOC4 (_I2C_ROUTELOC0_SDALOC_LOC4 << 0) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 823 #define I2C_ROUTELOC0_SDALOC_LOC5 (_I2C_ROUTELOC0_SDALOC_LOC5 << 0) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 824 #define I2C_ROUTELOC0_SDALOC_LOC6 (_I2C_ROUTELOC0_SDALOC_LOC6 << 0) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 825 #define I2C_ROUTELOC0_SDALOC_LOC7 (_I2C_ROUTELOC0_SDALOC_LOC7 << 0) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 826 #define I2C_ROUTELOC0_SDALOC_LOC8 (_I2C_ROUTELOC0_SDALOC_LOC8 << 0) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 827 #define I2C_ROUTELOC0_SDALOC_LOC9 (_I2C_ROUTELOC0_SDALOC_LOC9 << 0) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 828 #define I2C_ROUTELOC0_SDALOC_LOC10 (_I2C_ROUTELOC0_SDALOC_LOC10 << 0) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 829 #define I2C_ROUTELOC0_SDALOC_LOC11 (_I2C_ROUTELOC0_SDALOC_LOC11 << 0) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 830 #define I2C_ROUTELOC0_SDALOC_LOC12 (_I2C_ROUTELOC0_SDALOC_LOC12 << 0) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 831 #define I2C_ROUTELOC0_SDALOC_LOC13 (_I2C_ROUTELOC0_SDALOC_LOC13 << 0) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 832 #define I2C_ROUTELOC0_SDALOC_LOC14 (_I2C_ROUTELOC0_SDALOC_LOC14 << 0) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 833 #define I2C_ROUTELOC0_SDALOC_LOC15 (_I2C_ROUTELOC0_SDALOC_LOC15 << 0) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 834 #define I2C_ROUTELOC0_SDALOC_LOC16 (_I2C_ROUTELOC0_SDALOC_LOC16 << 0) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 835 #define I2C_ROUTELOC0_SDALOC_LOC17 (_I2C_ROUTELOC0_SDALOC_LOC17 << 0) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 836 #define I2C_ROUTELOC0_SDALOC_LOC18 (_I2C_ROUTELOC0_SDALOC_LOC18 << 0) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 837 #define I2C_ROUTELOC0_SDALOC_LOC19 (_I2C_ROUTELOC0_SDALOC_LOC19 << 0) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 838 #define I2C_ROUTELOC0_SDALOC_LOC20 (_I2C_ROUTELOC0_SDALOC_LOC20 << 0) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 839 #define I2C_ROUTELOC0_SDALOC_LOC21 (_I2C_ROUTELOC0_SDALOC_LOC21 << 0) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 840 #define I2C_ROUTELOC0_SDALOC_LOC22 (_I2C_ROUTELOC0_SDALOC_LOC22 << 0) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 841 #define I2C_ROUTELOC0_SDALOC_LOC23 (_I2C_ROUTELOC0_SDALOC_LOC23 << 0) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 842 #define I2C_ROUTELOC0_SDALOC_LOC24 (_I2C_ROUTELOC0_SDALOC_LOC24 << 0) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 843 #define I2C_ROUTELOC0_SDALOC_LOC25 (_I2C_ROUTELOC0_SDALOC_LOC25 << 0) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 844 #define I2C_ROUTELOC0_SDALOC_LOC26 (_I2C_ROUTELOC0_SDALOC_LOC26 << 0) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 845 #define I2C_ROUTELOC0_SDALOC_LOC27 (_I2C_ROUTELOC0_SDALOC_LOC27 << 0) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 846 #define I2C_ROUTELOC0_SDALOC_LOC28 (_I2C_ROUTELOC0_SDALOC_LOC28 << 0) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 847 #define I2C_ROUTELOC0_SDALOC_LOC29 (_I2C_ROUTELOC0_SDALOC_LOC29 << 0) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 848 #define I2C_ROUTELOC0_SDALOC_LOC30 (_I2C_ROUTELOC0_SDALOC_LOC30 << 0) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 849 #define I2C_ROUTELOC0_SDALOC_LOC31 (_I2C_ROUTELOC0_SDALOC_LOC31 << 0) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 850 #define _I2C_ROUTELOC0_SCLLOC_SHIFT 8 /**< Shift value for I2C_SCLLOC */
<> 139:856d2700e60b 851 #define _I2C_ROUTELOC0_SCLLOC_MASK 0x1F00UL /**< Bit mask for I2C_SCLLOC */
<> 139:856d2700e60b 852 #define _I2C_ROUTELOC0_SCLLOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 853 #define _I2C_ROUTELOC0_SCLLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */
<> 139:856d2700e60b 854 #define _I2C_ROUTELOC0_SCLLOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 855 #define _I2C_ROUTELOC0_SCLLOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 856 #define _I2C_ROUTELOC0_SCLLOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 857 #define _I2C_ROUTELOC0_SCLLOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 858 #define _I2C_ROUTELOC0_SCLLOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 859 #define _I2C_ROUTELOC0_SCLLOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 860 #define _I2C_ROUTELOC0_SCLLOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 861 #define _I2C_ROUTELOC0_SCLLOC_LOC8 0x00000008UL /**< Mode LOC8 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 862 #define _I2C_ROUTELOC0_SCLLOC_LOC9 0x00000009UL /**< Mode LOC9 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 863 #define _I2C_ROUTELOC0_SCLLOC_LOC10 0x0000000AUL /**< Mode LOC10 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 864 #define _I2C_ROUTELOC0_SCLLOC_LOC11 0x0000000BUL /**< Mode LOC11 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 865 #define _I2C_ROUTELOC0_SCLLOC_LOC12 0x0000000CUL /**< Mode LOC12 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 866 #define _I2C_ROUTELOC0_SCLLOC_LOC13 0x0000000DUL /**< Mode LOC13 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 867 #define _I2C_ROUTELOC0_SCLLOC_LOC14 0x0000000EUL /**< Mode LOC14 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 868 #define _I2C_ROUTELOC0_SCLLOC_LOC15 0x0000000FUL /**< Mode LOC15 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 869 #define _I2C_ROUTELOC0_SCLLOC_LOC16 0x00000010UL /**< Mode LOC16 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 870 #define _I2C_ROUTELOC0_SCLLOC_LOC17 0x00000011UL /**< Mode LOC17 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 871 #define _I2C_ROUTELOC0_SCLLOC_LOC18 0x00000012UL /**< Mode LOC18 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 872 #define _I2C_ROUTELOC0_SCLLOC_LOC19 0x00000013UL /**< Mode LOC19 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 873 #define _I2C_ROUTELOC0_SCLLOC_LOC20 0x00000014UL /**< Mode LOC20 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 874 #define _I2C_ROUTELOC0_SCLLOC_LOC21 0x00000015UL /**< Mode LOC21 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 875 #define _I2C_ROUTELOC0_SCLLOC_LOC22 0x00000016UL /**< Mode LOC22 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 876 #define _I2C_ROUTELOC0_SCLLOC_LOC23 0x00000017UL /**< Mode LOC23 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 877 #define _I2C_ROUTELOC0_SCLLOC_LOC24 0x00000018UL /**< Mode LOC24 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 878 #define _I2C_ROUTELOC0_SCLLOC_LOC25 0x00000019UL /**< Mode LOC25 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 879 #define _I2C_ROUTELOC0_SCLLOC_LOC26 0x0000001AUL /**< Mode LOC26 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 880 #define _I2C_ROUTELOC0_SCLLOC_LOC27 0x0000001BUL /**< Mode LOC27 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 881 #define _I2C_ROUTELOC0_SCLLOC_LOC28 0x0000001CUL /**< Mode LOC28 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 882 #define _I2C_ROUTELOC0_SCLLOC_LOC29 0x0000001DUL /**< Mode LOC29 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 883 #define _I2C_ROUTELOC0_SCLLOC_LOC30 0x0000001EUL /**< Mode LOC30 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 884 #define _I2C_ROUTELOC0_SCLLOC_LOC31 0x0000001FUL /**< Mode LOC31 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 885 #define I2C_ROUTELOC0_SCLLOC_LOC0 (_I2C_ROUTELOC0_SCLLOC_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 886 #define I2C_ROUTELOC0_SCLLOC_DEFAULT (_I2C_ROUTELOC0_SCLLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */
<> 139:856d2700e60b 887 #define I2C_ROUTELOC0_SCLLOC_LOC1 (_I2C_ROUTELOC0_SCLLOC_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 888 #define I2C_ROUTELOC0_SCLLOC_LOC2 (_I2C_ROUTELOC0_SCLLOC_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 889 #define I2C_ROUTELOC0_SCLLOC_LOC3 (_I2C_ROUTELOC0_SCLLOC_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 890 #define I2C_ROUTELOC0_SCLLOC_LOC4 (_I2C_ROUTELOC0_SCLLOC_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 891 #define I2C_ROUTELOC0_SCLLOC_LOC5 (_I2C_ROUTELOC0_SCLLOC_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 892 #define I2C_ROUTELOC0_SCLLOC_LOC6 (_I2C_ROUTELOC0_SCLLOC_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 893 #define I2C_ROUTELOC0_SCLLOC_LOC7 (_I2C_ROUTELOC0_SCLLOC_LOC7 << 8) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 894 #define I2C_ROUTELOC0_SCLLOC_LOC8 (_I2C_ROUTELOC0_SCLLOC_LOC8 << 8) /**< Shifted mode LOC8 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 895 #define I2C_ROUTELOC0_SCLLOC_LOC9 (_I2C_ROUTELOC0_SCLLOC_LOC9 << 8) /**< Shifted mode LOC9 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 896 #define I2C_ROUTELOC0_SCLLOC_LOC10 (_I2C_ROUTELOC0_SCLLOC_LOC10 << 8) /**< Shifted mode LOC10 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 897 #define I2C_ROUTELOC0_SCLLOC_LOC11 (_I2C_ROUTELOC0_SCLLOC_LOC11 << 8) /**< Shifted mode LOC11 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 898 #define I2C_ROUTELOC0_SCLLOC_LOC12 (_I2C_ROUTELOC0_SCLLOC_LOC12 << 8) /**< Shifted mode LOC12 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 899 #define I2C_ROUTELOC0_SCLLOC_LOC13 (_I2C_ROUTELOC0_SCLLOC_LOC13 << 8) /**< Shifted mode LOC13 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 900 #define I2C_ROUTELOC0_SCLLOC_LOC14 (_I2C_ROUTELOC0_SCLLOC_LOC14 << 8) /**< Shifted mode LOC14 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 901 #define I2C_ROUTELOC0_SCLLOC_LOC15 (_I2C_ROUTELOC0_SCLLOC_LOC15 << 8) /**< Shifted mode LOC15 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 902 #define I2C_ROUTELOC0_SCLLOC_LOC16 (_I2C_ROUTELOC0_SCLLOC_LOC16 << 8) /**< Shifted mode LOC16 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 903 #define I2C_ROUTELOC0_SCLLOC_LOC17 (_I2C_ROUTELOC0_SCLLOC_LOC17 << 8) /**< Shifted mode LOC17 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 904 #define I2C_ROUTELOC0_SCLLOC_LOC18 (_I2C_ROUTELOC0_SCLLOC_LOC18 << 8) /**< Shifted mode LOC18 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 905 #define I2C_ROUTELOC0_SCLLOC_LOC19 (_I2C_ROUTELOC0_SCLLOC_LOC19 << 8) /**< Shifted mode LOC19 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 906 #define I2C_ROUTELOC0_SCLLOC_LOC20 (_I2C_ROUTELOC0_SCLLOC_LOC20 << 8) /**< Shifted mode LOC20 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 907 #define I2C_ROUTELOC0_SCLLOC_LOC21 (_I2C_ROUTELOC0_SCLLOC_LOC21 << 8) /**< Shifted mode LOC21 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 908 #define I2C_ROUTELOC0_SCLLOC_LOC22 (_I2C_ROUTELOC0_SCLLOC_LOC22 << 8) /**< Shifted mode LOC22 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 909 #define I2C_ROUTELOC0_SCLLOC_LOC23 (_I2C_ROUTELOC0_SCLLOC_LOC23 << 8) /**< Shifted mode LOC23 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 910 #define I2C_ROUTELOC0_SCLLOC_LOC24 (_I2C_ROUTELOC0_SCLLOC_LOC24 << 8) /**< Shifted mode LOC24 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 911 #define I2C_ROUTELOC0_SCLLOC_LOC25 (_I2C_ROUTELOC0_SCLLOC_LOC25 << 8) /**< Shifted mode LOC25 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 912 #define I2C_ROUTELOC0_SCLLOC_LOC26 (_I2C_ROUTELOC0_SCLLOC_LOC26 << 8) /**< Shifted mode LOC26 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 913 #define I2C_ROUTELOC0_SCLLOC_LOC27 (_I2C_ROUTELOC0_SCLLOC_LOC27 << 8) /**< Shifted mode LOC27 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 914 #define I2C_ROUTELOC0_SCLLOC_LOC28 (_I2C_ROUTELOC0_SCLLOC_LOC28 << 8) /**< Shifted mode LOC28 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 915 #define I2C_ROUTELOC0_SCLLOC_LOC29 (_I2C_ROUTELOC0_SCLLOC_LOC29 << 8) /**< Shifted mode LOC29 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 916 #define I2C_ROUTELOC0_SCLLOC_LOC30 (_I2C_ROUTELOC0_SCLLOC_LOC30 << 8) /**< Shifted mode LOC30 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 917 #define I2C_ROUTELOC0_SCLLOC_LOC31 (_I2C_ROUTELOC0_SCLLOC_LOC31 << 8) /**< Shifted mode LOC31 for I2C_ROUTELOC0 */
<> 139:856d2700e60b 918
<> 139:856d2700e60b 919 /** @} End of group EFM32PG12B_I2C */
<> 139:856d2700e60b 920 /** @} End of group Parts */
<> 139:856d2700e60b 921