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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32PG12_STK3402/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_gpcrc.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
139:856d2700e60b 
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 139:856d2700e60b 1 /**************************************************************************//**
<> 139:856d2700e60b 2 * @file efm32pg12b_gpcrc.h
<> 139:856d2700e60b 3 * @brief EFM32PG12B_GPCRC register and bit field definitions
<> 139:856d2700e60b 4 * @version 5.1.2
<> 139:856d2700e60b 5 ******************************************************************************
<> 139:856d2700e60b 6 * @section License
<> 139:856d2700e60b 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 139:856d2700e60b 8 ******************************************************************************
<> 139:856d2700e60b 9 *
<> 139:856d2700e60b 10 * Permission is granted to anyone to use this software for any purpose,
<> 139:856d2700e60b 11 * including commercial applications, and to alter it and redistribute it
<> 139:856d2700e60b 12 * freely, subject to the following restrictions:
<> 139:856d2700e60b 13 *
<> 139:856d2700e60b 14 * 1. The origin of this software must not be misrepresented; you must not
<> 139:856d2700e60b 15 * claim that you wrote the original software.@n
<> 139:856d2700e60b 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 139:856d2700e60b 17 * misrepresented as being the original software.@n
<> 139:856d2700e60b 18 * 3. This notice may not be removed or altered from any source distribution.
<> 139:856d2700e60b 19 *
<> 139:856d2700e60b 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 139:856d2700e60b 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 139:856d2700e60b 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 139:856d2700e60b 23 * kind, including, but not limited to, any implied warranties of
<> 139:856d2700e60b 24 * merchantability or fitness for any particular purpose or warranties against
<> 139:856d2700e60b 25 * infringement of any proprietary rights of a third party.
<> 139:856d2700e60b 26 *
<> 139:856d2700e60b 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 139:856d2700e60b 28 * incidental, or special damages, or any other relief, or for any claim by
<> 139:856d2700e60b 29 * any third party, arising from your use of this Software.
<> 139:856d2700e60b 30 *
<> 139:856d2700e60b 31 *****************************************************************************/
<> 139:856d2700e60b 32 /**************************************************************************//**
<> 139:856d2700e60b 33 * @addtogroup Parts
<> 139:856d2700e60b 34 * @{
<> 139:856d2700e60b 35 ******************************************************************************/
<> 139:856d2700e60b 36 /**************************************************************************//**
<> 139:856d2700e60b 37 * @defgroup EFM32PG12B_GPCRC
<> 139:856d2700e60b 38 * @{
<> 139:856d2700e60b 39 * @brief EFM32PG12B_GPCRC Register Declaration
<> 139:856d2700e60b 40 *****************************************************************************/
<> 139:856d2700e60b 41 typedef struct
<> 139:856d2700e60b 42 {
<> 139:856d2700e60b 43 __IOM uint32_t CTRL; /**< Control Register */
<> 139:856d2700e60b 44 __IOM uint32_t CMD; /**< Command Register */
<> 139:856d2700e60b 45 __IOM uint32_t INIT; /**< CRC Init Value */
<> 139:856d2700e60b 46 __IOM uint32_t POLY; /**< CRC Polynomial Value */
<> 139:856d2700e60b 47 __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */
<> 139:856d2700e60b 48 __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */
<> 139:856d2700e60b 49 __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */
<> 139:856d2700e60b 50 __IM uint32_t DATA; /**< CRC Data Register */
<> 139:856d2700e60b 51 __IM uint32_t DATAREV; /**< CRC Data Reverse Register */
<> 139:856d2700e60b 52 __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */
<> 139:856d2700e60b 53 } GPCRC_TypeDef; /** @} */
<> 139:856d2700e60b 54
<> 139:856d2700e60b 55 /**************************************************************************//**
<> 139:856d2700e60b 56 * @defgroup EFM32PG12B_GPCRC_BitFields
<> 139:856d2700e60b 57 * @{
<> 139:856d2700e60b 58 *****************************************************************************/
<> 139:856d2700e60b 59
<> 139:856d2700e60b 60 /* Bit fields for GPCRC CTRL */
<> 139:856d2700e60b 61 #define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */
<> 139:856d2700e60b 62 #define _GPCRC_CTRL_MASK 0x00002711UL /**< Mask for GPCRC_CTRL */
<> 139:856d2700e60b 63 #define GPCRC_CTRL_EN (0x1UL << 0) /**< CRC Functionality Enable */
<> 139:856d2700e60b 64 #define _GPCRC_CTRL_EN_SHIFT 0 /**< Shift value for GPCRC_EN */
<> 139:856d2700e60b 65 #define _GPCRC_CTRL_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */
<> 139:856d2700e60b 66 #define _GPCRC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
<> 139:856d2700e60b 67 #define _GPCRC_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_CTRL */
<> 139:856d2700e60b 68 #define _GPCRC_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_CTRL */
<> 139:856d2700e60b 69 #define GPCRC_CTRL_EN_DEFAULT (_GPCRC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CTRL */
<> 139:856d2700e60b 70 #define GPCRC_CTRL_EN_DISABLE (_GPCRC_CTRL_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_CTRL */
<> 139:856d2700e60b 71 #define GPCRC_CTRL_EN_ENABLE (_GPCRC_CTRL_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_CTRL */
<> 139:856d2700e60b 72 #define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */
<> 139:856d2700e60b 73 #define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */
<> 139:856d2700e60b 74 #define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */
<> 139:856d2700e60b 75 #define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
<> 139:856d2700e60b 76 #define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */
<> 139:856d2700e60b 77 #define _GPCRC_CTRL_POLYSEL_16 0x00000001UL /**< Mode 16 for GPCRC_CTRL */
<> 139:856d2700e60b 78 #define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */
<> 139:856d2700e60b 79 #define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */
<> 139:856d2700e60b 80 #define GPCRC_CTRL_POLYSEL_16 (_GPCRC_CTRL_POLYSEL_16 << 4) /**< Shifted mode 16 for GPCRC_CTRL */
<> 139:856d2700e60b 81 #define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */
<> 139:856d2700e60b 82 #define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */
<> 139:856d2700e60b 83 #define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */
<> 139:856d2700e60b 84 #define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
<> 139:856d2700e60b 85 #define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */
<> 139:856d2700e60b 86 #define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */
<> 139:856d2700e60b 87 #define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */
<> 139:856d2700e60b 88 #define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */
<> 139:856d2700e60b 89 #define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
<> 139:856d2700e60b 90 #define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */
<> 139:856d2700e60b 91 #define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */
<> 139:856d2700e60b 92 #define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */
<> 139:856d2700e60b 93 #define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */
<> 139:856d2700e60b 94 #define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */
<> 139:856d2700e60b 95 #define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */
<> 139:856d2700e60b 96 #define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */
<> 139:856d2700e60b 97 #define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */
<> 139:856d2700e60b 98 #define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
<> 139:856d2700e60b 99 #define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */
<> 139:856d2700e60b 100 #define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */
<> 139:856d2700e60b 101 #define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */
<> 139:856d2700e60b 102 #define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */
<> 139:856d2700e60b 103 #define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */
<> 139:856d2700e60b 104 #define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */
<> 139:856d2700e60b 105 #define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */
<> 139:856d2700e60b 106 #define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */
<> 139:856d2700e60b 107 #define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
<> 139:856d2700e60b 108 #define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */
<> 139:856d2700e60b 109
<> 139:856d2700e60b 110 /* Bit fields for GPCRC CMD */
<> 139:856d2700e60b 111 #define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */
<> 139:856d2700e60b 112 #define _GPCRC_CMD_MASK 0x00000001UL /**< Mask for GPCRC_CMD */
<> 139:856d2700e60b 113 #define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */
<> 139:856d2700e60b 114 #define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */
<> 139:856d2700e60b 115 #define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */
<> 139:856d2700e60b 116 #define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */
<> 139:856d2700e60b 117 #define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */
<> 139:856d2700e60b 118
<> 139:856d2700e60b 119 /* Bit fields for GPCRC INIT */
<> 139:856d2700e60b 120 #define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */
<> 139:856d2700e60b 121 #define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */
<> 139:856d2700e60b 122 #define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */
<> 139:856d2700e60b 123 #define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */
<> 139:856d2700e60b 124 #define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */
<> 139:856d2700e60b 125 #define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */
<> 139:856d2700e60b 126
<> 139:856d2700e60b 127 /* Bit fields for GPCRC POLY */
<> 139:856d2700e60b 128 #define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */
<> 139:856d2700e60b 129 #define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */
<> 139:856d2700e60b 130 #define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */
<> 139:856d2700e60b 131 #define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */
<> 139:856d2700e60b 132 #define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */
<> 139:856d2700e60b 133 #define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */
<> 139:856d2700e60b 134
<> 139:856d2700e60b 135 /* Bit fields for GPCRC INPUTDATA */
<> 139:856d2700e60b 136 #define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */
<> 139:856d2700e60b 137 #define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */
<> 139:856d2700e60b 138 #define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */
<> 139:856d2700e60b 139 #define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */
<> 139:856d2700e60b 140 #define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */
<> 139:856d2700e60b 141 #define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */
<> 139:856d2700e60b 142
<> 139:856d2700e60b 143 /* Bit fields for GPCRC INPUTDATAHWORD */
<> 139:856d2700e60b 144 #define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */
<> 139:856d2700e60b 145 #define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */
<> 139:856d2700e60b 146 #define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */
<> 139:856d2700e60b 147 #define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */
<> 139:856d2700e60b 148 #define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */
<> 139:856d2700e60b 149 #define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD */
<> 139:856d2700e60b 150
<> 139:856d2700e60b 151 /* Bit fields for GPCRC INPUTDATABYTE */
<> 139:856d2700e60b 152 #define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */
<> 139:856d2700e60b 153 #define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */
<> 139:856d2700e60b 154 #define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */
<> 139:856d2700e60b 155 #define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */
<> 139:856d2700e60b 156 #define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */
<> 139:856d2700e60b 157 #define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE */
<> 139:856d2700e60b 158
<> 139:856d2700e60b 159 /* Bit fields for GPCRC DATA */
<> 139:856d2700e60b 160 #define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */
<> 139:856d2700e60b 161 #define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */
<> 139:856d2700e60b 162 #define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */
<> 139:856d2700e60b 163 #define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */
<> 139:856d2700e60b 164 #define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */
<> 139:856d2700e60b 165 #define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */
<> 139:856d2700e60b 166
<> 139:856d2700e60b 167 /* Bit fields for GPCRC DATAREV */
<> 139:856d2700e60b 168 #define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */
<> 139:856d2700e60b 169 #define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */
<> 139:856d2700e60b 170 #define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */
<> 139:856d2700e60b 171 #define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */
<> 139:856d2700e60b 172 #define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */
<> 139:856d2700e60b 173 #define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */
<> 139:856d2700e60b 174
<> 139:856d2700e60b 175 /* Bit fields for GPCRC DATABYTEREV */
<> 139:856d2700e60b 176 #define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */
<> 139:856d2700e60b 177 #define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */
<> 139:856d2700e60b 178 #define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */
<> 139:856d2700e60b 179 #define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */
<> 139:856d2700e60b 180 #define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */
<> 139:856d2700e60b 181 #define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */
<> 139:856d2700e60b 182
<> 139:856d2700e60b 183 /** @} End of group EFM32PG12B_GPCRC */
<> 139:856d2700e60b 184 /** @} End of group Parts */
<> 139:856d2700e60b 185