mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32PG12_STK3402/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_etm.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
139:856d2700e60b 
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 139:856d2700e60b 1 /**************************************************************************//**
<> 139:856d2700e60b 2 * @file efm32pg12b_etm.h
<> 139:856d2700e60b 3 * @brief EFM32PG12B_ETM register and bit field definitions
<> 139:856d2700e60b 4 * @version 5.1.2
<> 139:856d2700e60b 5 ******************************************************************************
<> 139:856d2700e60b 6 * @section License
<> 139:856d2700e60b 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 139:856d2700e60b 8 ******************************************************************************
<> 139:856d2700e60b 9 *
<> 139:856d2700e60b 10 * Permission is granted to anyone to use this software for any purpose,
<> 139:856d2700e60b 11 * including commercial applications, and to alter it and redistribute it
<> 139:856d2700e60b 12 * freely, subject to the following restrictions:
<> 139:856d2700e60b 13 *
<> 139:856d2700e60b 14 * 1. The origin of this software must not be misrepresented; you must not
<> 139:856d2700e60b 15 * claim that you wrote the original software.@n
<> 139:856d2700e60b 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 139:856d2700e60b 17 * misrepresented as being the original software.@n
<> 139:856d2700e60b 18 * 3. This notice may not be removed or altered from any source distribution.
<> 139:856d2700e60b 19 *
<> 139:856d2700e60b 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 139:856d2700e60b 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 139:856d2700e60b 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 139:856d2700e60b 23 * kind, including, but not limited to, any implied warranties of
<> 139:856d2700e60b 24 * merchantability or fitness for any particular purpose or warranties against
<> 139:856d2700e60b 25 * infringement of any proprietary rights of a third party.
<> 139:856d2700e60b 26 *
<> 139:856d2700e60b 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 139:856d2700e60b 28 * incidental, or special damages, or any other relief, or for any claim by
<> 139:856d2700e60b 29 * any third party, arising from your use of this Software.
<> 139:856d2700e60b 30 *
<> 139:856d2700e60b 31 *****************************************************************************/
<> 139:856d2700e60b 32 /**************************************************************************//**
<> 139:856d2700e60b 33 * @addtogroup Parts
<> 139:856d2700e60b 34 * @{
<> 139:856d2700e60b 35 ******************************************************************************/
<> 139:856d2700e60b 36 /**************************************************************************//**
<> 139:856d2700e60b 37 * @defgroup EFM32PG12B_ETM
<> 139:856d2700e60b 38 * @{
<> 139:856d2700e60b 39 * @brief EFM32PG12B_ETM Register Declaration
<> 139:856d2700e60b 40 *****************************************************************************/
<> 139:856d2700e60b 41 typedef struct
<> 139:856d2700e60b 42 {
<> 139:856d2700e60b 43 __IOM uint32_t ETMCR; /**< Main Control Register */
<> 139:856d2700e60b 44 __IM uint32_t ETMCCR; /**< Configuration Code Register */
<> 139:856d2700e60b 45 __IOM uint32_t ETMTRIGGER; /**< ETM Trigger Event Register */
<> 139:856d2700e60b 46 uint32_t RESERVED0[1]; /**< Reserved for future use **/
<> 139:856d2700e60b 47 __IOM uint32_t ETMSR; /**< ETM Status Register */
<> 139:856d2700e60b 48 __IM uint32_t ETMSCR; /**< ETM System Configuration Register */
<> 139:856d2700e60b 49 uint32_t RESERVED1[2]; /**< Reserved for future use **/
<> 139:856d2700e60b 50 __IOM uint32_t ETMTEEVR; /**< ETM TraceEnable Event Register */
<> 139:856d2700e60b 51 __IOM uint32_t ETMTECR1; /**< ETM Trace control Register */
<> 139:856d2700e60b 52 uint32_t RESERVED2[1]; /**< Reserved for future use **/
<> 139:856d2700e60b 53 __IOM uint32_t ETMFFLR; /**< ETM Fifo Full Level Register */
<> 139:856d2700e60b 54 uint32_t RESERVED3[68]; /**< Reserved for future use **/
<> 139:856d2700e60b 55 __IOM uint32_t ETMCNTRLDVR1; /**< Counter Reload Value */
<> 139:856d2700e60b 56 uint32_t RESERVED4[39]; /**< Reserved for future use **/
<> 139:856d2700e60b 57 __IOM uint32_t ETMSYNCFR; /**< Synchronisation Frequency Register */
<> 139:856d2700e60b 58 __IM uint32_t ETMIDR; /**< ID Register */
<> 139:856d2700e60b 59 __IM uint32_t ETMCCER; /**< Configuration Code Extension Register */
<> 139:856d2700e60b 60 uint32_t RESERVED5[1]; /**< Reserved for future use **/
<> 139:856d2700e60b 61 __IOM uint32_t ETMTESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register */
<> 139:856d2700e60b 62 uint32_t RESERVED6[1]; /**< Reserved for future use **/
<> 139:856d2700e60b 63 __IOM uint32_t ETMTSEVR; /**< Timestamp Event Register */
<> 139:856d2700e60b 64 uint32_t RESERVED7[1]; /**< Reserved for future use **/
<> 139:856d2700e60b 65 __IOM uint32_t ETMTRACEIDR; /**< CoreSight Trace ID Register */
<> 139:856d2700e60b 66 uint32_t RESERVED8[1]; /**< Reserved for future use **/
<> 139:856d2700e60b 67 __IM uint32_t ETMIDR2; /**< ETM ID Register 2 */
<> 139:856d2700e60b 68 uint32_t RESERVED9[66]; /**< Reserved for future use **/
<> 139:856d2700e60b 69 __IM uint32_t ETMPDSR; /**< Device Power-down Status Register */
<> 139:856d2700e60b 70 uint32_t RESERVED10[754]; /**< Reserved for future use **/
<> 139:856d2700e60b 71 __IOM uint32_t ETMISCIN; /**< Integration Test Miscellaneous Inputs Register */
<> 139:856d2700e60b 72 uint32_t RESERVED11[1]; /**< Reserved for future use **/
<> 139:856d2700e60b 73 __IOM uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register */
<> 139:856d2700e60b 74 uint32_t RESERVED12[1]; /**< Reserved for future use **/
<> 139:856d2700e60b 75 __IM uint32_t ETMITATBCTR2; /**< ETM Integration Test ATB Control 2 Register */
<> 139:856d2700e60b 76 uint32_t RESERVED13[1]; /**< Reserved for future use **/
<> 139:856d2700e60b 77 __IOM uint32_t ETMITATBCTR0; /**< ETM Integration Test ATB Control 0 Register */
<> 139:856d2700e60b 78 uint32_t RESERVED14[1]; /**< Reserved for future use **/
<> 139:856d2700e60b 79 __IOM uint32_t ETMITCTRL; /**< ETM Integration Control Register */
<> 139:856d2700e60b 80 uint32_t RESERVED15[39]; /**< Reserved for future use **/
<> 139:856d2700e60b 81 __IOM uint32_t ETMCLAIMSET; /**< ETM Claim Tag Set Register */
<> 139:856d2700e60b 82 __IOM uint32_t ETMCLAIMCLR; /**< ETM Claim Tag Clear Register */
<> 139:856d2700e60b 83 uint32_t RESERVED16[2]; /**< Reserved for future use **/
<> 139:856d2700e60b 84 __IOM uint32_t ETMLAR; /**< ETM Lock Access Register */
<> 139:856d2700e60b 85 __IM uint32_t ETMLSR; /**< Lock Status Register */
<> 139:856d2700e60b 86 __IM uint32_t ETMAUTHSTATUS; /**< ETM Authentication Status Register */
<> 139:856d2700e60b 87 uint32_t RESERVED17[4]; /**< Reserved for future use **/
<> 139:856d2700e60b 88 __IM uint32_t ETMDEVTYPE; /**< CoreSight Device Type Register */
<> 139:856d2700e60b 89 __IM uint32_t ETMPIDR4; /**< Peripheral ID4 Register */
<> 139:856d2700e60b 90 __OM uint32_t ETMPIDR5; /**< Peripheral ID5 Register */
<> 139:856d2700e60b 91 __OM uint32_t ETMPIDR6; /**< Peripheral ID6 Register */
<> 139:856d2700e60b 92 __OM uint32_t ETMPIDR7; /**< Peripheral ID7 Register */
<> 139:856d2700e60b 93 __IM uint32_t ETMPIDR0; /**< Peripheral ID0 Register */
<> 139:856d2700e60b 94 __IM uint32_t ETMPIDR1; /**< Peripheral ID1 Register */
<> 139:856d2700e60b 95 __IM uint32_t ETMPIDR2; /**< Peripheral ID2 Register */
<> 139:856d2700e60b 96 __IM uint32_t ETMPIDR3; /**< Peripheral ID3 Register */
<> 139:856d2700e60b 97 __IM uint32_t ETMCIDR0; /**< Component ID0 Register */
<> 139:856d2700e60b 98 __IM uint32_t ETMCIDR1; /**< Component ID1 Register */
<> 139:856d2700e60b 99 __IM uint32_t ETMCIDR2; /**< Component ID2 Register */
<> 139:856d2700e60b 100 __IM uint32_t ETMCIDR3; /**< Component ID3 Register */
<> 139:856d2700e60b 101 } ETM_TypeDef; /** @} */
<> 139:856d2700e60b 102
<> 139:856d2700e60b 103 /**************************************************************************//**
<> 139:856d2700e60b 104 * @defgroup EFM32PG12B_ETM_BitFields
<> 139:856d2700e60b 105 * @{
<> 139:856d2700e60b 106 *****************************************************************************/
<> 139:856d2700e60b 107
<> 139:856d2700e60b 108 /* Bit fields for ETM ETMCR */
<> 139:856d2700e60b 109 #define _ETM_ETMCR_RESETVALUE 0x00000411UL /**< Default value for ETM_ETMCR */
<> 139:856d2700e60b 110 #define _ETM_ETMCR_MASK 0x10632FF1UL /**< Mask for ETM_ETMCR */
<> 139:856d2700e60b 111 #define ETM_ETMCR_POWERDWN (0x1UL << 0) /**< ETM Control in low power mode */
<> 139:856d2700e60b 112 #define _ETM_ETMCR_POWERDWN_SHIFT 0 /**< Shift value for ETM_POWERDWN */
<> 139:856d2700e60b 113 #define _ETM_ETMCR_POWERDWN_MASK 0x1UL /**< Bit mask for ETM_POWERDWN */
<> 139:856d2700e60b 114 #define _ETM_ETMCR_POWERDWN_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 115 #define ETM_ETMCR_POWERDWN_DEFAULT (_ETM_ETMCR_POWERDWN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 116 #define _ETM_ETMCR_PORTSIZE_SHIFT 4 /**< Shift value for ETM_PORTSIZE */
<> 139:856d2700e60b 117 #define _ETM_ETMCR_PORTSIZE_MASK 0x70UL /**< Bit mask for ETM_PORTSIZE */
<> 139:856d2700e60b 118 #define _ETM_ETMCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 119 #define ETM_ETMCR_PORTSIZE_DEFAULT (_ETM_ETMCR_PORTSIZE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 120 #define ETM_ETMCR_STALL (0x1UL << 7) /**< Stall Processor */
<> 139:856d2700e60b 121 #define _ETM_ETMCR_STALL_SHIFT 7 /**< Shift value for ETM_STALL */
<> 139:856d2700e60b 122 #define _ETM_ETMCR_STALL_MASK 0x80UL /**< Bit mask for ETM_STALL */
<> 139:856d2700e60b 123 #define _ETM_ETMCR_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 124 #define ETM_ETMCR_STALL_DEFAULT (_ETM_ETMCR_STALL_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 125 #define ETM_ETMCR_BRANCHOUTPUT (0x1UL << 8) /**< Branch Output */
<> 139:856d2700e60b 126 #define _ETM_ETMCR_BRANCHOUTPUT_SHIFT 8 /**< Shift value for ETM_BRANCHOUTPUT */
<> 139:856d2700e60b 127 #define _ETM_ETMCR_BRANCHOUTPUT_MASK 0x100UL /**< Bit mask for ETM_BRANCHOUTPUT */
<> 139:856d2700e60b 128 #define _ETM_ETMCR_BRANCHOUTPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 129 #define ETM_ETMCR_BRANCHOUTPUT_DEFAULT (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 130 #define ETM_ETMCR_DBGREQCTRL (0x1UL << 9) /**< Debug Request Control */
<> 139:856d2700e60b 131 #define _ETM_ETMCR_DBGREQCTRL_SHIFT 9 /**< Shift value for ETM_DBGREQCTRL */
<> 139:856d2700e60b 132 #define _ETM_ETMCR_DBGREQCTRL_MASK 0x200UL /**< Bit mask for ETM_DBGREQCTRL */
<> 139:856d2700e60b 133 #define _ETM_ETMCR_DBGREQCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 134 #define ETM_ETMCR_DBGREQCTRL_DEFAULT (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 135 #define ETM_ETMCR_ETMPROG (0x1UL << 10) /**< ETM Programming */
<> 139:856d2700e60b 136 #define _ETM_ETMCR_ETMPROG_SHIFT 10 /**< Shift value for ETM_ETMPROG */
<> 139:856d2700e60b 137 #define _ETM_ETMCR_ETMPROG_MASK 0x400UL /**< Bit mask for ETM_ETMPROG */
<> 139:856d2700e60b 138 #define _ETM_ETMCR_ETMPROG_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 139 #define ETM_ETMCR_ETMPROG_DEFAULT (_ETM_ETMCR_ETMPROG_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 140 #define ETM_ETMCR_ETMPORTSEL (0x1UL << 11) /**< ETM Port Selection */
<> 139:856d2700e60b 141 #define _ETM_ETMCR_ETMPORTSEL_SHIFT 11 /**< Shift value for ETM_ETMPORTSEL */
<> 139:856d2700e60b 142 #define _ETM_ETMCR_ETMPORTSEL_MASK 0x800UL /**< Bit mask for ETM_ETMPORTSEL */
<> 139:856d2700e60b 143 #define _ETM_ETMCR_ETMPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 144 #define _ETM_ETMCR_ETMPORTSEL_ETMLOW 0x00000000UL /**< Mode ETMLOW for ETM_ETMCR */
<> 139:856d2700e60b 145 #define _ETM_ETMCR_ETMPORTSEL_ETMHIGH 0x00000001UL /**< Mode ETMHIGH for ETM_ETMCR */
<> 139:856d2700e60b 146 #define ETM_ETMCR_ETMPORTSEL_DEFAULT (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 147 #define ETM_ETMCR_ETMPORTSEL_ETMLOW (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11) /**< Shifted mode ETMLOW for ETM_ETMCR */
<> 139:856d2700e60b 148 #define ETM_ETMCR_ETMPORTSEL_ETMHIGH (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11) /**< Shifted mode ETMHIGH for ETM_ETMCR */
<> 139:856d2700e60b 149 #define ETM_ETMCR_PORTMODE2 (0x1UL << 13) /**< Port Mode[2] */
<> 139:856d2700e60b 150 #define _ETM_ETMCR_PORTMODE2_SHIFT 13 /**< Shift value for ETM_PORTMODE2 */
<> 139:856d2700e60b 151 #define _ETM_ETMCR_PORTMODE2_MASK 0x2000UL /**< Bit mask for ETM_PORTMODE2 */
<> 139:856d2700e60b 152 #define _ETM_ETMCR_PORTMODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 153 #define ETM_ETMCR_PORTMODE2_DEFAULT (_ETM_ETMCR_PORTMODE2_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 154 #define _ETM_ETMCR_PORTMODE_SHIFT 16 /**< Shift value for ETM_PORTMODE */
<> 139:856d2700e60b 155 #define _ETM_ETMCR_PORTMODE_MASK 0x30000UL /**< Bit mask for ETM_PORTMODE */
<> 139:856d2700e60b 156 #define _ETM_ETMCR_PORTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 157 #define ETM_ETMCR_PORTMODE_DEFAULT (_ETM_ETMCR_PORTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 158 #define _ETM_ETMCR_EPORTSIZE_SHIFT 21 /**< Shift value for ETM_EPORTSIZE */
<> 139:856d2700e60b 159 #define _ETM_ETMCR_EPORTSIZE_MASK 0x600000UL /**< Bit mask for ETM_EPORTSIZE */
<> 139:856d2700e60b 160 #define _ETM_ETMCR_EPORTSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 161 #define ETM_ETMCR_EPORTSIZE_DEFAULT (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 162 #define ETM_ETMCR_TSTAMPEN (0x1UL << 28) /**< Time Stamp Enable */
<> 139:856d2700e60b 163 #define _ETM_ETMCR_TSTAMPEN_SHIFT 28 /**< Shift value for ETM_TSTAMPEN */
<> 139:856d2700e60b 164 #define _ETM_ETMCR_TSTAMPEN_MASK 0x10000000UL /**< Bit mask for ETM_TSTAMPEN */
<> 139:856d2700e60b 165 #define _ETM_ETMCR_TSTAMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 166 #define ETM_ETMCR_TSTAMPEN_DEFAULT (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCR */
<> 139:856d2700e60b 167
<> 139:856d2700e60b 168 /* Bit fields for ETM ETMCCR */
<> 139:856d2700e60b 169 #define _ETM_ETMCCR_RESETVALUE 0x8C802000UL /**< Default value for ETM_ETMCCR */
<> 139:856d2700e60b 170 #define _ETM_ETMCCR_MASK 0x8FFFFFFFUL /**< Mask for ETM_ETMCCR */
<> 139:856d2700e60b 171 #define _ETM_ETMCCR_ADRCMPPAIR_SHIFT 0 /**< Shift value for ETM_ADRCMPPAIR */
<> 139:856d2700e60b 172 #define _ETM_ETMCCR_ADRCMPPAIR_MASK 0xFUL /**< Bit mask for ETM_ADRCMPPAIR */
<> 139:856d2700e60b 173 #define _ETM_ETMCCR_ADRCMPPAIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 174 #define ETM_ETMCCR_ADRCMPPAIR_DEFAULT (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 175 #define _ETM_ETMCCR_DATACMPNUM_SHIFT 4 /**< Shift value for ETM_DATACMPNUM */
<> 139:856d2700e60b 176 #define _ETM_ETMCCR_DATACMPNUM_MASK 0xF0UL /**< Bit mask for ETM_DATACMPNUM */
<> 139:856d2700e60b 177 #define _ETM_ETMCCR_DATACMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 178 #define ETM_ETMCCR_DATACMPNUM_DEFAULT (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 179 #define _ETM_ETMCCR_MMDECCNT_SHIFT 8 /**< Shift value for ETM_MMDECCNT */
<> 139:856d2700e60b 180 #define _ETM_ETMCCR_MMDECCNT_MASK 0x1F00UL /**< Bit mask for ETM_MMDECCNT */
<> 139:856d2700e60b 181 #define _ETM_ETMCCR_MMDECCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 182 #define ETM_ETMCCR_MMDECCNT_DEFAULT (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 183 #define _ETM_ETMCCR_COUNTNUM_SHIFT 13 /**< Shift value for ETM_COUNTNUM */
<> 139:856d2700e60b 184 #define _ETM_ETMCCR_COUNTNUM_MASK 0xE000UL /**< Bit mask for ETM_COUNTNUM */
<> 139:856d2700e60b 185 #define _ETM_ETMCCR_COUNTNUM_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 186 #define ETM_ETMCCR_COUNTNUM_DEFAULT (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 187 #define ETM_ETMCCR_SEQPRES (0x1UL << 16) /**< Sequencer Present */
<> 139:856d2700e60b 188 #define _ETM_ETMCCR_SEQPRES_SHIFT 16 /**< Shift value for ETM_SEQPRES */
<> 139:856d2700e60b 189 #define _ETM_ETMCCR_SEQPRES_MASK 0x10000UL /**< Bit mask for ETM_SEQPRES */
<> 139:856d2700e60b 190 #define _ETM_ETMCCR_SEQPRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 191 #define ETM_ETMCCR_SEQPRES_DEFAULT (_ETM_ETMCCR_SEQPRES_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 192 #define _ETM_ETMCCR_EXTINPNUM_SHIFT 17 /**< Shift value for ETM_EXTINPNUM */
<> 139:856d2700e60b 193 #define _ETM_ETMCCR_EXTINPNUM_MASK 0xE0000UL /**< Bit mask for ETM_EXTINPNUM */
<> 139:856d2700e60b 194 #define _ETM_ETMCCR_EXTINPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 195 #define _ETM_ETMCCR_EXTINPNUM_ZERO 0x00000000UL /**< Mode ZERO for ETM_ETMCCR */
<> 139:856d2700e60b 196 #define _ETM_ETMCCR_EXTINPNUM_ONE 0x00000001UL /**< Mode ONE for ETM_ETMCCR */
<> 139:856d2700e60b 197 #define _ETM_ETMCCR_EXTINPNUM_TWO 0x00000002UL /**< Mode TWO for ETM_ETMCCR */
<> 139:856d2700e60b 198 #define ETM_ETMCCR_EXTINPNUM_DEFAULT (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 199 #define ETM_ETMCCR_EXTINPNUM_ZERO (_ETM_ETMCCR_EXTINPNUM_ZERO << 17) /**< Shifted mode ZERO for ETM_ETMCCR */
<> 139:856d2700e60b 200 #define ETM_ETMCCR_EXTINPNUM_ONE (_ETM_ETMCCR_EXTINPNUM_ONE << 17) /**< Shifted mode ONE for ETM_ETMCCR */
<> 139:856d2700e60b 201 #define ETM_ETMCCR_EXTINPNUM_TWO (_ETM_ETMCCR_EXTINPNUM_TWO << 17) /**< Shifted mode TWO for ETM_ETMCCR */
<> 139:856d2700e60b 202 #define _ETM_ETMCCR_EXTOUTNUM_SHIFT 20 /**< Shift value for ETM_EXTOUTNUM */
<> 139:856d2700e60b 203 #define _ETM_ETMCCR_EXTOUTNUM_MASK 0x700000UL /**< Bit mask for ETM_EXTOUTNUM */
<> 139:856d2700e60b 204 #define _ETM_ETMCCR_EXTOUTNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 205 #define ETM_ETMCCR_EXTOUTNUM_DEFAULT (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 206 #define ETM_ETMCCR_FIFOFULLPRES (0x1UL << 23) /**< FIFIO FULL present */
<> 139:856d2700e60b 207 #define _ETM_ETMCCR_FIFOFULLPRES_SHIFT 23 /**< Shift value for ETM_FIFOFULLPRES */
<> 139:856d2700e60b 208 #define _ETM_ETMCCR_FIFOFULLPRES_MASK 0x800000UL /**< Bit mask for ETM_FIFOFULLPRES */
<> 139:856d2700e60b 209 #define _ETM_ETMCCR_FIFOFULLPRES_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 210 #define ETM_ETMCCR_FIFOFULLPRES_DEFAULT (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 211 #define _ETM_ETMCCR_IDCOMPNUM_SHIFT 24 /**< Shift value for ETM_IDCOMPNUM */
<> 139:856d2700e60b 212 #define _ETM_ETMCCR_IDCOMPNUM_MASK 0x3000000UL /**< Bit mask for ETM_IDCOMPNUM */
<> 139:856d2700e60b 213 #define _ETM_ETMCCR_IDCOMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 214 #define ETM_ETMCCR_IDCOMPNUM_DEFAULT (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 215 #define ETM_ETMCCR_TRACESS (0x1UL << 26) /**< Trace Start/Stop Block Present */
<> 139:856d2700e60b 216 #define _ETM_ETMCCR_TRACESS_SHIFT 26 /**< Shift value for ETM_TRACESS */
<> 139:856d2700e60b 217 #define _ETM_ETMCCR_TRACESS_MASK 0x4000000UL /**< Bit mask for ETM_TRACESS */
<> 139:856d2700e60b 218 #define _ETM_ETMCCR_TRACESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 219 #define ETM_ETMCCR_TRACESS_DEFAULT (_ETM_ETMCCR_TRACESS_DEFAULT << 26) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 220 #define ETM_ETMCCR_MMACCESS (0x1UL << 27) /**< Coprocessor and Memeory Access */
<> 139:856d2700e60b 221 #define _ETM_ETMCCR_MMACCESS_SHIFT 27 /**< Shift value for ETM_MMACCESS */
<> 139:856d2700e60b 222 #define _ETM_ETMCCR_MMACCESS_MASK 0x8000000UL /**< Bit mask for ETM_MMACCESS */
<> 139:856d2700e60b 223 #define _ETM_ETMCCR_MMACCESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 224 #define ETM_ETMCCR_MMACCESS_DEFAULT (_ETM_ETMCCR_MMACCESS_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 225 #define ETM_ETMCCR_ETMID (0x1UL << 31) /**< ETM ID Register Present */
<> 139:856d2700e60b 226 #define _ETM_ETMCCR_ETMID_SHIFT 31 /**< Shift value for ETM_ETMID */
<> 139:856d2700e60b 227 #define _ETM_ETMCCR_ETMID_MASK 0x80000000UL /**< Bit mask for ETM_ETMID */
<> 139:856d2700e60b 228 #define _ETM_ETMCCR_ETMID_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 229 #define ETM_ETMCCR_ETMID_DEFAULT (_ETM_ETMCCR_ETMID_DEFAULT << 31) /**< Shifted mode DEFAULT for ETM_ETMCCR */
<> 139:856d2700e60b 230
<> 139:856d2700e60b 231 /* Bit fields for ETM ETMTRIGGER */
<> 139:856d2700e60b 232 #define _ETM_ETMTRIGGER_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRIGGER */
<> 139:856d2700e60b 233 #define _ETM_ETMTRIGGER_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTRIGGER */
<> 139:856d2700e60b 234 #define _ETM_ETMTRIGGER_RESA_SHIFT 0 /**< Shift value for ETM_RESA */
<> 139:856d2700e60b 235 #define _ETM_ETMTRIGGER_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */
<> 139:856d2700e60b 236 #define _ETM_ETMTRIGGER_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
<> 139:856d2700e60b 237 #define ETM_ETMTRIGGER_RESA_DEFAULT (_ETM_ETMTRIGGER_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
<> 139:856d2700e60b 238 #define _ETM_ETMTRIGGER_RESB_SHIFT 7 /**< Shift value for ETM_RESB */
<> 139:856d2700e60b 239 #define _ETM_ETMTRIGGER_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */
<> 139:856d2700e60b 240 #define _ETM_ETMTRIGGER_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
<> 139:856d2700e60b 241 #define ETM_ETMTRIGGER_RESB_DEFAULT (_ETM_ETMTRIGGER_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
<> 139:856d2700e60b 242 #define _ETM_ETMTRIGGER_ETMFCN_SHIFT 14 /**< Shift value for ETM_ETMFCN */
<> 139:856d2700e60b 243 #define _ETM_ETMTRIGGER_ETMFCN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCN */
<> 139:856d2700e60b 244 #define _ETM_ETMTRIGGER_ETMFCN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
<> 139:856d2700e60b 245 #define ETM_ETMTRIGGER_ETMFCN_DEFAULT (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
<> 139:856d2700e60b 246
<> 139:856d2700e60b 247 /* Bit fields for ETM ETMSR */
<> 139:856d2700e60b 248 #define _ETM_ETMSR_RESETVALUE 0x00000002UL /**< Default value for ETM_ETMSR */
<> 139:856d2700e60b 249 #define _ETM_ETMSR_MASK 0x0000000FUL /**< Mask for ETM_ETMSR */
<> 139:856d2700e60b 250 #define ETM_ETMSR_ETHOF (0x1UL << 0) /**< ETM Overflow */
<> 139:856d2700e60b 251 #define _ETM_ETMSR_ETHOF_SHIFT 0 /**< Shift value for ETM_ETHOF */
<> 139:856d2700e60b 252 #define _ETM_ETMSR_ETHOF_MASK 0x1UL /**< Bit mask for ETM_ETHOF */
<> 139:856d2700e60b 253 #define _ETM_ETMSR_ETHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
<> 139:856d2700e60b 254 #define ETM_ETMSR_ETHOF_DEFAULT (_ETM_ETMSR_ETHOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSR */
<> 139:856d2700e60b 255 #define ETM_ETMSR_ETMPROGBIT (0x1UL << 1) /**< ETM Programming Bit Status */
<> 139:856d2700e60b 256 #define _ETM_ETMSR_ETMPROGBIT_SHIFT 1 /**< Shift value for ETM_ETMPROGBIT */
<> 139:856d2700e60b 257 #define _ETM_ETMSR_ETMPROGBIT_MASK 0x2UL /**< Bit mask for ETM_ETMPROGBIT */
<> 139:856d2700e60b 258 #define _ETM_ETMSR_ETMPROGBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSR */
<> 139:856d2700e60b 259 #define ETM_ETMSR_ETMPROGBIT_DEFAULT (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMSR */
<> 139:856d2700e60b 260 #define ETM_ETMSR_TRACESTAT (0x1UL << 2) /**< Trace Start/Stop Status */
<> 139:856d2700e60b 261 #define _ETM_ETMSR_TRACESTAT_SHIFT 2 /**< Shift value for ETM_TRACESTAT */
<> 139:856d2700e60b 262 #define _ETM_ETMSR_TRACESTAT_MASK 0x4UL /**< Bit mask for ETM_TRACESTAT */
<> 139:856d2700e60b 263 #define _ETM_ETMSR_TRACESTAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
<> 139:856d2700e60b 264 #define ETM_ETMSR_TRACESTAT_DEFAULT (_ETM_ETMSR_TRACESTAT_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMSR */
<> 139:856d2700e60b 265 #define ETM_ETMSR_TRIGBIT (0x1UL << 3) /**< Trigger Bit */
<> 139:856d2700e60b 266 #define _ETM_ETMSR_TRIGBIT_SHIFT 3 /**< Shift value for ETM_TRIGBIT */
<> 139:856d2700e60b 267 #define _ETM_ETMSR_TRIGBIT_MASK 0x8UL /**< Bit mask for ETM_TRIGBIT */
<> 139:856d2700e60b 268 #define _ETM_ETMSR_TRIGBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
<> 139:856d2700e60b 269 #define ETM_ETMSR_TRIGBIT_DEFAULT (_ETM_ETMSR_TRIGBIT_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMSR */
<> 139:856d2700e60b 270
<> 139:856d2700e60b 271 /* Bit fields for ETM ETMSCR */
<> 139:856d2700e60b 272 #define _ETM_ETMSCR_RESETVALUE 0x00020D09UL /**< Default value for ETM_ETMSCR */
<> 139:856d2700e60b 273 #define _ETM_ETMSCR_MASK 0x00027F0FUL /**< Mask for ETM_ETMSCR */
<> 139:856d2700e60b 274 #define _ETM_ETMSCR_MAXPORTSIZE_SHIFT 0 /**< Shift value for ETM_MAXPORTSIZE */
<> 139:856d2700e60b 275 #define _ETM_ETMSCR_MAXPORTSIZE_MASK 0x7UL /**< Bit mask for ETM_MAXPORTSIZE */
<> 139:856d2700e60b 276 #define _ETM_ETMSCR_MAXPORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
<> 139:856d2700e60b 277 #define ETM_ETMSCR_MAXPORTSIZE_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSCR */
<> 139:856d2700e60b 278 #define ETM_ETMSCR_FIFOFULL (0x1UL << 8) /**< FIFO FULL Supported */
<> 139:856d2700e60b 279 #define _ETM_ETMSCR_FIFOFULL_SHIFT 8 /**< Shift value for ETM_FIFOFULL */
<> 139:856d2700e60b 280 #define _ETM_ETMSCR_FIFOFULL_MASK 0x100UL /**< Bit mask for ETM_FIFOFULL */
<> 139:856d2700e60b 281 #define _ETM_ETMSCR_FIFOFULL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
<> 139:856d2700e60b 282 #define ETM_ETMSCR_FIFOFULL_DEFAULT (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMSCR */
<> 139:856d2700e60b 283 #define ETM_ETMSCR_MAXPORTSIZE3 (0x1UL << 9) /**< Max Port Size[3] */
<> 139:856d2700e60b 284 #define _ETM_ETMSCR_MAXPORTSIZE3_SHIFT 9 /**< Shift value for ETM_MAXPORTSIZE3 */
<> 139:856d2700e60b 285 #define _ETM_ETMSCR_MAXPORTSIZE3_MASK 0x200UL /**< Bit mask for ETM_MAXPORTSIZE3 */
<> 139:856d2700e60b 286 #define _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */
<> 139:856d2700e60b 287 #define ETM_ETMSCR_MAXPORTSIZE3_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMSCR */
<> 139:856d2700e60b 288 #define ETM_ETMSCR_PORTSIZE (0x1UL << 10) /**< Port Size Supported */
<> 139:856d2700e60b 289 #define _ETM_ETMSCR_PORTSIZE_SHIFT 10 /**< Shift value for ETM_PORTSIZE */
<> 139:856d2700e60b 290 #define _ETM_ETMSCR_PORTSIZE_MASK 0x400UL /**< Bit mask for ETM_PORTSIZE */
<> 139:856d2700e60b 291 #define _ETM_ETMSCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
<> 139:856d2700e60b 292 #define ETM_ETMSCR_PORTSIZE_DEFAULT (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMSCR */
<> 139:856d2700e60b 293 #define ETM_ETMSCR_PORTMODE (0x1UL << 11) /**< Port Mode Supported */
<> 139:856d2700e60b 294 #define _ETM_ETMSCR_PORTMODE_SHIFT 11 /**< Shift value for ETM_PORTMODE */
<> 139:856d2700e60b 295 #define _ETM_ETMSCR_PORTMODE_MASK 0x800UL /**< Bit mask for ETM_PORTMODE */
<> 139:856d2700e60b 296 #define _ETM_ETMSCR_PORTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
<> 139:856d2700e60b 297 #define ETM_ETMSCR_PORTMODE_DEFAULT (_ETM_ETMSCR_PORTMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMSCR */
<> 139:856d2700e60b 298 #define _ETM_ETMSCR_PROCNUM_SHIFT 12 /**< Shift value for ETM_PROCNUM */
<> 139:856d2700e60b 299 #define _ETM_ETMSCR_PROCNUM_MASK 0x7000UL /**< Bit mask for ETM_PROCNUM */
<> 139:856d2700e60b 300 #define _ETM_ETMSCR_PROCNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */
<> 139:856d2700e60b 301 #define ETM_ETMSCR_PROCNUM_DEFAULT (_ETM_ETMSCR_PROCNUM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMSCR */
<> 139:856d2700e60b 302 #define ETM_ETMSCR_NOFETCHCOMP (0x1UL << 17) /**< No Fetch Comparison */
<> 139:856d2700e60b 303 #define _ETM_ETMSCR_NOFETCHCOMP_SHIFT 17 /**< Shift value for ETM_NOFETCHCOMP */
<> 139:856d2700e60b 304 #define _ETM_ETMSCR_NOFETCHCOMP_MASK 0x20000UL /**< Bit mask for ETM_NOFETCHCOMP */
<> 139:856d2700e60b 305 #define _ETM_ETMSCR_NOFETCHCOMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
<> 139:856d2700e60b 306 #define ETM_ETMSCR_NOFETCHCOMP_DEFAULT (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMSCR */
<> 139:856d2700e60b 307
<> 139:856d2700e60b 308 /* Bit fields for ETM ETMTEEVR */
<> 139:856d2700e60b 309 #define _ETM_ETMTEEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTEEVR */
<> 139:856d2700e60b 310 #define _ETM_ETMTEEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTEEVR */
<> 139:856d2700e60b 311 #define _ETM_ETMTEEVR_RESA_SHIFT 0 /**< Shift value for ETM_RESA */
<> 139:856d2700e60b 312 #define _ETM_ETMTEEVR_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */
<> 139:856d2700e60b 313 #define _ETM_ETMTEEVR_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
<> 139:856d2700e60b 314 #define ETM_ETMTEEVR_RESA_DEFAULT (_ETM_ETMTEEVR_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
<> 139:856d2700e60b 315 #define _ETM_ETMTEEVR_RESB_SHIFT 7 /**< Shift value for ETM_RESB */
<> 139:856d2700e60b 316 #define _ETM_ETMTEEVR_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */
<> 139:856d2700e60b 317 #define _ETM_ETMTEEVR_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
<> 139:856d2700e60b 318 #define ETM_ETMTEEVR_RESB_DEFAULT (_ETM_ETMTEEVR_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
<> 139:856d2700e60b 319 #define _ETM_ETMTEEVR_ETMFCNEN_SHIFT 14 /**< Shift value for ETM_ETMFCNEN */
<> 139:856d2700e60b 320 #define _ETM_ETMTEEVR_ETMFCNEN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEN */
<> 139:856d2700e60b 321 #define _ETM_ETMTEEVR_ETMFCNEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
<> 139:856d2700e60b 322 #define ETM_ETMTEEVR_ETMFCNEN_DEFAULT (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
<> 139:856d2700e60b 323
<> 139:856d2700e60b 324 /* Bit fields for ETM ETMTECR1 */
<> 139:856d2700e60b 325 #define _ETM_ETMTECR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTECR1 */
<> 139:856d2700e60b 326 #define _ETM_ETMTECR1_MASK 0x03FFFFFFUL /**< Mask for ETM_ETMTECR1 */
<> 139:856d2700e60b 327 #define _ETM_ETMTECR1_ADRCMP_SHIFT 0 /**< Shift value for ETM_ADRCMP */
<> 139:856d2700e60b 328 #define _ETM_ETMTECR1_ADRCMP_MASK 0xFFUL /**< Bit mask for ETM_ADRCMP */
<> 139:856d2700e60b 329 #define _ETM_ETMTECR1_ADRCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
<> 139:856d2700e60b 330 #define ETM_ETMTECR1_ADRCMP_DEFAULT (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
<> 139:856d2700e60b 331 #define _ETM_ETMTECR1_MEMMAP_SHIFT 8 /**< Shift value for ETM_MEMMAP */
<> 139:856d2700e60b 332 #define _ETM_ETMTECR1_MEMMAP_MASK 0xFFFF00UL /**< Bit mask for ETM_MEMMAP */
<> 139:856d2700e60b 333 #define _ETM_ETMTECR1_MEMMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
<> 139:856d2700e60b 334 #define ETM_ETMTECR1_MEMMAP_DEFAULT (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
<> 139:856d2700e60b 335 #define ETM_ETMTECR1_INCEXCTL (0x1UL << 24) /**< Trace Include/Exclude Flag */
<> 139:856d2700e60b 336 #define _ETM_ETMTECR1_INCEXCTL_SHIFT 24 /**< Shift value for ETM_INCEXCTL */
<> 139:856d2700e60b 337 #define _ETM_ETMTECR1_INCEXCTL_MASK 0x1000000UL /**< Bit mask for ETM_INCEXCTL */
<> 139:856d2700e60b 338 #define _ETM_ETMTECR1_INCEXCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
<> 139:856d2700e60b 339 #define _ETM_ETMTECR1_INCEXCTL_INC 0x00000000UL /**< Mode INC for ETM_ETMTECR1 */
<> 139:856d2700e60b 340 #define _ETM_ETMTECR1_INCEXCTL_EXC 0x00000001UL /**< Mode EXC for ETM_ETMTECR1 */
<> 139:856d2700e60b 341 #define ETM_ETMTECR1_INCEXCTL_DEFAULT (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
<> 139:856d2700e60b 342 #define ETM_ETMTECR1_INCEXCTL_INC (_ETM_ETMTECR1_INCEXCTL_INC << 24) /**< Shifted mode INC for ETM_ETMTECR1 */
<> 139:856d2700e60b 343 #define ETM_ETMTECR1_INCEXCTL_EXC (_ETM_ETMTECR1_INCEXCTL_EXC << 24) /**< Shifted mode EXC for ETM_ETMTECR1 */
<> 139:856d2700e60b 344 #define ETM_ETMTECR1_TCE (0x1UL << 25) /**< Trace Control Enable */
<> 139:856d2700e60b 345 #define _ETM_ETMTECR1_TCE_SHIFT 25 /**< Shift value for ETM_TCE */
<> 139:856d2700e60b 346 #define _ETM_ETMTECR1_TCE_MASK 0x2000000UL /**< Bit mask for ETM_TCE */
<> 139:856d2700e60b 347 #define _ETM_ETMTECR1_TCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
<> 139:856d2700e60b 348 #define _ETM_ETMTECR1_TCE_EN 0x00000000UL /**< Mode EN for ETM_ETMTECR1 */
<> 139:856d2700e60b 349 #define _ETM_ETMTECR1_TCE_DIS 0x00000001UL /**< Mode DIS for ETM_ETMTECR1 */
<> 139:856d2700e60b 350 #define ETM_ETMTECR1_TCE_DEFAULT (_ETM_ETMTECR1_TCE_DEFAULT << 25) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
<> 139:856d2700e60b 351 #define ETM_ETMTECR1_TCE_EN (_ETM_ETMTECR1_TCE_EN << 25) /**< Shifted mode EN for ETM_ETMTECR1 */
<> 139:856d2700e60b 352 #define ETM_ETMTECR1_TCE_DIS (_ETM_ETMTECR1_TCE_DIS << 25) /**< Shifted mode DIS for ETM_ETMTECR1 */
<> 139:856d2700e60b 353
<> 139:856d2700e60b 354 /* Bit fields for ETM ETMFFLR */
<> 139:856d2700e60b 355 #define _ETM_ETMFFLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMFFLR */
<> 139:856d2700e60b 356 #define _ETM_ETMFFLR_MASK 0x000000FFUL /**< Mask for ETM_ETMFFLR */
<> 139:856d2700e60b 357 #define _ETM_ETMFFLR_BYTENUM_SHIFT 0 /**< Shift value for ETM_BYTENUM */
<> 139:856d2700e60b 358 #define _ETM_ETMFFLR_BYTENUM_MASK 0xFFUL /**< Bit mask for ETM_BYTENUM */
<> 139:856d2700e60b 359 #define _ETM_ETMFFLR_BYTENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMFFLR */
<> 139:856d2700e60b 360 #define ETM_ETMFFLR_BYTENUM_DEFAULT (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMFFLR */
<> 139:856d2700e60b 361
<> 139:856d2700e60b 362 /* Bit fields for ETM ETMCNTRLDVR1 */
<> 139:856d2700e60b 363 #define _ETM_ETMCNTRLDVR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCNTRLDVR1 */
<> 139:856d2700e60b 364 #define _ETM_ETMCNTRLDVR1_MASK 0x0000FFFFUL /**< Mask for ETM_ETMCNTRLDVR1 */
<> 139:856d2700e60b 365 #define _ETM_ETMCNTRLDVR1_COUNT_SHIFT 0 /**< Shift value for ETM_COUNT */
<> 139:856d2700e60b 366 #define _ETM_ETMCNTRLDVR1_COUNT_MASK 0xFFFFUL /**< Bit mask for ETM_COUNT */
<> 139:856d2700e60b 367 #define _ETM_ETMCNTRLDVR1_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCNTRLDVR1 */
<> 139:856d2700e60b 368 #define ETM_ETMCNTRLDVR1_COUNT_DEFAULT (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCNTRLDVR1 */
<> 139:856d2700e60b 369
<> 139:856d2700e60b 370 /* Bit fields for ETM ETMSYNCFR */
<> 139:856d2700e60b 371 #define _ETM_ETMSYNCFR_RESETVALUE 0x00000400UL /**< Default value for ETM_ETMSYNCFR */
<> 139:856d2700e60b 372 #define _ETM_ETMSYNCFR_MASK 0x00000FFFUL /**< Mask for ETM_ETMSYNCFR */
<> 139:856d2700e60b 373 #define _ETM_ETMSYNCFR_FREQ_SHIFT 0 /**< Shift value for ETM_FREQ */
<> 139:856d2700e60b 374 #define _ETM_ETMSYNCFR_FREQ_MASK 0xFFFUL /**< Bit mask for ETM_FREQ */
<> 139:856d2700e60b 375 #define _ETM_ETMSYNCFR_FREQ_DEFAULT 0x00000400UL /**< Mode DEFAULT for ETM_ETMSYNCFR */
<> 139:856d2700e60b 376 #define ETM_ETMSYNCFR_FREQ_DEFAULT (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSYNCFR */
<> 139:856d2700e60b 377
<> 139:856d2700e60b 378 /* Bit fields for ETM ETMIDR */
<> 139:856d2700e60b 379 #define _ETM_ETMIDR_RESETVALUE 0x4114F253UL /**< Default value for ETM_ETMIDR */
<> 139:856d2700e60b 380 #define _ETM_ETMIDR_MASK 0xFF1DFFFFUL /**< Mask for ETM_ETMIDR */
<> 139:856d2700e60b 381 #define _ETM_ETMIDR_IMPVER_SHIFT 0 /**< Shift value for ETM_IMPVER */
<> 139:856d2700e60b 382 #define _ETM_ETMIDR_IMPVER_MASK 0xFUL /**< Bit mask for ETM_IMPVER */
<> 139:856d2700e60b 383 #define _ETM_ETMIDR_IMPVER_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMIDR */
<> 139:856d2700e60b 384 #define ETM_ETMIDR_IMPVER_DEFAULT (_ETM_ETMIDR_IMPVER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR */
<> 139:856d2700e60b 385 #define _ETM_ETMIDR_ETMMINVER_SHIFT 4 /**< Shift value for ETM_ETMMINVER */
<> 139:856d2700e60b 386 #define _ETM_ETMIDR_ETMMINVER_MASK 0xF0UL /**< Bit mask for ETM_ETMMINVER */
<> 139:856d2700e60b 387 #define _ETM_ETMIDR_ETMMINVER_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMIDR */
<> 139:856d2700e60b 388 #define ETM_ETMIDR_ETMMINVER_DEFAULT (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMIDR */
<> 139:856d2700e60b 389 #define _ETM_ETMIDR_ETMMAJVER_SHIFT 8 /**< Shift value for ETM_ETMMAJVER */
<> 139:856d2700e60b 390 #define _ETM_ETMIDR_ETMMAJVER_MASK 0xF00UL /**< Bit mask for ETM_ETMMAJVER */
<> 139:856d2700e60b 391 #define _ETM_ETMIDR_ETMMAJVER_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETM_ETMIDR */
<> 139:856d2700e60b 392 #define ETM_ETMIDR_ETMMAJVER_DEFAULT (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMIDR */
<> 139:856d2700e60b 393 #define _ETM_ETMIDR_PROCFAM_SHIFT 12 /**< Shift value for ETM_PROCFAM */
<> 139:856d2700e60b 394 #define _ETM_ETMIDR_PROCFAM_MASK 0xF000UL /**< Bit mask for ETM_PROCFAM */
<> 139:856d2700e60b 395 #define _ETM_ETMIDR_PROCFAM_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMIDR */
<> 139:856d2700e60b 396 #define ETM_ETMIDR_PROCFAM_DEFAULT (_ETM_ETMIDR_PROCFAM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMIDR */
<> 139:856d2700e60b 397 #define ETM_ETMIDR_LPCF (0x1UL << 16) /**< Load PC First */
<> 139:856d2700e60b 398 #define _ETM_ETMIDR_LPCF_SHIFT 16 /**< Shift value for ETM_LPCF */
<> 139:856d2700e60b 399 #define _ETM_ETMIDR_LPCF_MASK 0x10000UL /**< Bit mask for ETM_LPCF */
<> 139:856d2700e60b 400 #define _ETM_ETMIDR_LPCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */
<> 139:856d2700e60b 401 #define ETM_ETMIDR_LPCF_DEFAULT (_ETM_ETMIDR_LPCF_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMIDR */
<> 139:856d2700e60b 402 #define ETM_ETMIDR_THUMBT (0x1UL << 18) /**< 32-bit Thumb Instruction Tracing */
<> 139:856d2700e60b 403 #define _ETM_ETMIDR_THUMBT_SHIFT 18 /**< Shift value for ETM_THUMBT */
<> 139:856d2700e60b 404 #define _ETM_ETMIDR_THUMBT_MASK 0x40000UL /**< Bit mask for ETM_THUMBT */
<> 139:856d2700e60b 405 #define _ETM_ETMIDR_THUMBT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */
<> 139:856d2700e60b 406 #define ETM_ETMIDR_THUMBT_DEFAULT (_ETM_ETMIDR_THUMBT_DEFAULT << 18) /**< Shifted mode DEFAULT for ETM_ETMIDR */
<> 139:856d2700e60b 407 #define ETM_ETMIDR_SECEXT (0x1UL << 19) /**< Security Extension Support */
<> 139:856d2700e60b 408 #define _ETM_ETMIDR_SECEXT_SHIFT 19 /**< Shift value for ETM_SECEXT */
<> 139:856d2700e60b 409 #define _ETM_ETMIDR_SECEXT_MASK 0x80000UL /**< Bit mask for ETM_SECEXT */
<> 139:856d2700e60b 410 #define _ETM_ETMIDR_SECEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */
<> 139:856d2700e60b 411 #define ETM_ETMIDR_SECEXT_DEFAULT (_ETM_ETMIDR_SECEXT_DEFAULT << 19) /**< Shifted mode DEFAULT for ETM_ETMIDR */
<> 139:856d2700e60b 412 #define ETM_ETMIDR_BPE (0x1UL << 20) /**< Branch Packet Encoding */
<> 139:856d2700e60b 413 #define _ETM_ETMIDR_BPE_SHIFT 20 /**< Shift value for ETM_BPE */
<> 139:856d2700e60b 414 #define _ETM_ETMIDR_BPE_MASK 0x100000UL /**< Bit mask for ETM_BPE */
<> 139:856d2700e60b 415 #define _ETM_ETMIDR_BPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */
<> 139:856d2700e60b 416 #define ETM_ETMIDR_BPE_DEFAULT (_ETM_ETMIDR_BPE_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMIDR */
<> 139:856d2700e60b 417 #define _ETM_ETMIDR_IMPCODE_SHIFT 24 /**< Shift value for ETM_IMPCODE */
<> 139:856d2700e60b 418 #define _ETM_ETMIDR_IMPCODE_MASK 0xFF000000UL /**< Bit mask for ETM_IMPCODE */
<> 139:856d2700e60b 419 #define _ETM_ETMIDR_IMPCODE_DEFAULT 0x00000041UL /**< Mode DEFAULT for ETM_ETMIDR */
<> 139:856d2700e60b 420 #define ETM_ETMIDR_IMPCODE_DEFAULT (_ETM_ETMIDR_IMPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMIDR */
<> 139:856d2700e60b 421
<> 139:856d2700e60b 422 /* Bit fields for ETM ETMCCER */
<> 139:856d2700e60b 423 #define _ETM_ETMCCER_RESETVALUE 0x18541800UL /**< Default value for ETM_ETMCCER */
<> 139:856d2700e60b 424 #define _ETM_ETMCCER_MASK 0x387FFFFBUL /**< Mask for ETM_ETMCCER */
<> 139:856d2700e60b 425 #define _ETM_ETMCCER_EXTINPSEL_SHIFT 0 /**< Shift value for ETM_EXTINPSEL */
<> 139:856d2700e60b 426 #define _ETM_ETMCCER_EXTINPSEL_MASK 0x3UL /**< Bit mask for ETM_EXTINPSEL */
<> 139:856d2700e60b 427 #define _ETM_ETMCCER_EXTINPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 428 #define ETM_ETMCCER_EXTINPSEL_DEFAULT (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 429 #define _ETM_ETMCCER_EXTINPBUS_SHIFT 3 /**< Shift value for ETM_EXTINPBUS */
<> 139:856d2700e60b 430 #define _ETM_ETMCCER_EXTINPBUS_MASK 0x7F8UL /**< Bit mask for ETM_EXTINPBUS */
<> 139:856d2700e60b 431 #define _ETM_ETMCCER_EXTINPBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 432 #define ETM_ETMCCER_EXTINPBUS_DEFAULT (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 433 #define ETM_ETMCCER_READREGS (0x1UL << 11) /**< Readable Registers */
<> 139:856d2700e60b 434 #define _ETM_ETMCCER_READREGS_SHIFT 11 /**< Shift value for ETM_READREGS */
<> 139:856d2700e60b 435 #define _ETM_ETMCCER_READREGS_MASK 0x800UL /**< Bit mask for ETM_READREGS */
<> 139:856d2700e60b 436 #define _ETM_ETMCCER_READREGS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 437 #define ETM_ETMCCER_READREGS_DEFAULT (_ETM_ETMCCER_READREGS_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 438 #define ETM_ETMCCER_DADDRCMP (0x1UL << 12) /**< Data Address comparisons */
<> 139:856d2700e60b 439 #define _ETM_ETMCCER_DADDRCMP_SHIFT 12 /**< Shift value for ETM_DADDRCMP */
<> 139:856d2700e60b 440 #define _ETM_ETMCCER_DADDRCMP_MASK 0x1000UL /**< Bit mask for ETM_DADDRCMP */
<> 139:856d2700e60b 441 #define _ETM_ETMCCER_DADDRCMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 442 #define ETM_ETMCCER_DADDRCMP_DEFAULT (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 443 #define _ETM_ETMCCER_INSTRES_SHIFT 13 /**< Shift value for ETM_INSTRES */
<> 139:856d2700e60b 444 #define _ETM_ETMCCER_INSTRES_MASK 0xE000UL /**< Bit mask for ETM_INSTRES */
<> 139:856d2700e60b 445 #define _ETM_ETMCCER_INSTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 446 #define ETM_ETMCCER_INSTRES_DEFAULT (_ETM_ETMCCER_INSTRES_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 447 #define _ETM_ETMCCER_EICEWPNT_SHIFT 16 /**< Shift value for ETM_EICEWPNT */
<> 139:856d2700e60b 448 #define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL /**< Bit mask for ETM_EICEWPNT */
<> 139:856d2700e60b 449 #define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 450 #define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 451 #define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /**< Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */
<> 139:856d2700e60b 452 #define _ETM_ETMCCER_TEICEWPNT_SHIFT 20 /**< Shift value for ETM_TEICEWPNT */
<> 139:856d2700e60b 453 #define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL /**< Bit mask for ETM_TEICEWPNT */
<> 139:856d2700e60b 454 #define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 455 #define ETM_ETMCCER_TEICEWPNT_DEFAULT (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 456 #define ETM_ETMCCER_EICEIMP (0x1UL << 21) /**< EmbeddedICE Behavior control Implemented */
<> 139:856d2700e60b 457 #define _ETM_ETMCCER_EICEIMP_SHIFT 21 /**< Shift value for ETM_EICEIMP */
<> 139:856d2700e60b 458 #define _ETM_ETMCCER_EICEIMP_MASK 0x200000UL /**< Bit mask for ETM_EICEIMP */
<> 139:856d2700e60b 459 #define _ETM_ETMCCER_EICEIMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 460 #define ETM_ETMCCER_EICEIMP_DEFAULT (_ETM_ETMCCER_EICEIMP_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 461 #define ETM_ETMCCER_TIMP (0x1UL << 22) /**< Timestamping Implemented */
<> 139:856d2700e60b 462 #define _ETM_ETMCCER_TIMP_SHIFT 22 /**< Shift value for ETM_TIMP */
<> 139:856d2700e60b 463 #define _ETM_ETMCCER_TIMP_MASK 0x400000UL /**< Bit mask for ETM_TIMP */
<> 139:856d2700e60b 464 #define _ETM_ETMCCER_TIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 465 #define ETM_ETMCCER_TIMP_DEFAULT (_ETM_ETMCCER_TIMP_DEFAULT << 22) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 466 #define ETM_ETMCCER_RFCNT (0x1UL << 27) /**< Reduced Function Counter */
<> 139:856d2700e60b 467 #define _ETM_ETMCCER_RFCNT_SHIFT 27 /**< Shift value for ETM_RFCNT */
<> 139:856d2700e60b 468 #define _ETM_ETMCCER_RFCNT_MASK 0x8000000UL /**< Bit mask for ETM_RFCNT */
<> 139:856d2700e60b 469 #define _ETM_ETMCCER_RFCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 470 #define ETM_ETMCCER_RFCNT_DEFAULT (_ETM_ETMCCER_RFCNT_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 471 #define ETM_ETMCCER_TENC (0x1UL << 28) /**< Timestamp Encoding */
<> 139:856d2700e60b 472 #define _ETM_ETMCCER_TENC_SHIFT 28 /**< Shift value for ETM_TENC */
<> 139:856d2700e60b 473 #define _ETM_ETMCCER_TENC_MASK 0x10000000UL /**< Bit mask for ETM_TENC */
<> 139:856d2700e60b 474 #define _ETM_ETMCCER_TENC_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 475 #define ETM_ETMCCER_TENC_DEFAULT (_ETM_ETMCCER_TENC_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 476 #define ETM_ETMCCER_TSIZE (0x1UL << 29) /**< Timestamp Size */
<> 139:856d2700e60b 477 #define _ETM_ETMCCER_TSIZE_SHIFT 29 /**< Shift value for ETM_TSIZE */
<> 139:856d2700e60b 478 #define _ETM_ETMCCER_TSIZE_MASK 0x20000000UL /**< Bit mask for ETM_TSIZE */
<> 139:856d2700e60b 479 #define _ETM_ETMCCER_TSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 480 #define ETM_ETMCCER_TSIZE_DEFAULT (_ETM_ETMCCER_TSIZE_DEFAULT << 29) /**< Shifted mode DEFAULT for ETM_ETMCCER */
<> 139:856d2700e60b 481
<> 139:856d2700e60b 482 /* Bit fields for ETM ETMTESSEICR */
<> 139:856d2700e60b 483 #define _ETM_ETMTESSEICR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTESSEICR */
<> 139:856d2700e60b 484 #define _ETM_ETMTESSEICR_MASK 0x000F000FUL /**< Mask for ETM_ETMTESSEICR */
<> 139:856d2700e60b 485 #define _ETM_ETMTESSEICR_STARTRSEL_SHIFT 0 /**< Shift value for ETM_STARTRSEL */
<> 139:856d2700e60b 486 #define _ETM_ETMTESSEICR_STARTRSEL_MASK 0xFUL /**< Bit mask for ETM_STARTRSEL */
<> 139:856d2700e60b 487 #define _ETM_ETMTESSEICR_STARTRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */
<> 139:856d2700e60b 488 #define ETM_ETMTESSEICR_STARTRSEL_DEFAULT (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */
<> 139:856d2700e60b 489 #define _ETM_ETMTESSEICR_STOPRSEL_SHIFT 16 /**< Shift value for ETM_STOPRSEL */
<> 139:856d2700e60b 490 #define _ETM_ETMTESSEICR_STOPRSEL_MASK 0xF0000UL /**< Bit mask for ETM_STOPRSEL */
<> 139:856d2700e60b 491 #define _ETM_ETMTESSEICR_STOPRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */
<> 139:856d2700e60b 492 #define ETM_ETMTESSEICR_STOPRSEL_DEFAULT (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */
<> 139:856d2700e60b 493
<> 139:856d2700e60b 494 /* Bit fields for ETM ETMTSEVR */
<> 139:856d2700e60b 495 #define _ETM_ETMTSEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTSEVR */
<> 139:856d2700e60b 496 #define _ETM_ETMTSEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTSEVR */
<> 139:856d2700e60b 497 #define _ETM_ETMTSEVR_RESAEVT_SHIFT 0 /**< Shift value for ETM_RESAEVT */
<> 139:856d2700e60b 498 #define _ETM_ETMTSEVR_RESAEVT_MASK 0x7FUL /**< Bit mask for ETM_RESAEVT */
<> 139:856d2700e60b 499 #define _ETM_ETMTSEVR_RESAEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
<> 139:856d2700e60b 500 #define ETM_ETMTSEVR_RESAEVT_DEFAULT (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
<> 139:856d2700e60b 501 #define _ETM_ETMTSEVR_RESBEVT_SHIFT 7 /**< Shift value for ETM_RESBEVT */
<> 139:856d2700e60b 502 #define _ETM_ETMTSEVR_RESBEVT_MASK 0x3F80UL /**< Bit mask for ETM_RESBEVT */
<> 139:856d2700e60b 503 #define _ETM_ETMTSEVR_RESBEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
<> 139:856d2700e60b 504 #define ETM_ETMTSEVR_RESBEVT_DEFAULT (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
<> 139:856d2700e60b 505 #define _ETM_ETMTSEVR_ETMFCNEVT_SHIFT 14 /**< Shift value for ETM_ETMFCNEVT */
<> 139:856d2700e60b 506 #define _ETM_ETMTSEVR_ETMFCNEVT_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEVT */
<> 139:856d2700e60b 507 #define _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
<> 139:856d2700e60b 508 #define ETM_ETMTSEVR_ETMFCNEVT_DEFAULT (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
<> 139:856d2700e60b 509
<> 139:856d2700e60b 510 /* Bit fields for ETM ETMTRACEIDR */
<> 139:856d2700e60b 511 #define _ETM_ETMTRACEIDR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRACEIDR */
<> 139:856d2700e60b 512 #define _ETM_ETMTRACEIDR_MASK 0x0000007FUL /**< Mask for ETM_ETMTRACEIDR */
<> 139:856d2700e60b 513 #define _ETM_ETMTRACEIDR_TRACEID_SHIFT 0 /**< Shift value for ETM_TRACEID */
<> 139:856d2700e60b 514 #define _ETM_ETMTRACEIDR_TRACEID_MASK 0x7FUL /**< Bit mask for ETM_TRACEID */
<> 139:856d2700e60b 515 #define _ETM_ETMTRACEIDR_TRACEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRACEIDR */
<> 139:856d2700e60b 516 #define ETM_ETMTRACEIDR_TRACEID_DEFAULT (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRACEIDR */
<> 139:856d2700e60b 517
<> 139:856d2700e60b 518 /* Bit fields for ETM ETMIDR2 */
<> 139:856d2700e60b 519 #define _ETM_ETMIDR2_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMIDR2 */
<> 139:856d2700e60b 520 #define _ETM_ETMIDR2_MASK 0x00000003UL /**< Mask for ETM_ETMIDR2 */
<> 139:856d2700e60b 521 #define ETM_ETMIDR2_RFE (0x1UL << 0) /**< RFE Transfer Order */
<> 139:856d2700e60b 522 #define _ETM_ETMIDR2_RFE_SHIFT 0 /**< Shift value for ETM_RFE */
<> 139:856d2700e60b 523 #define _ETM_ETMIDR2_RFE_MASK 0x1UL /**< Bit mask for ETM_RFE */
<> 139:856d2700e60b 524 #define _ETM_ETMIDR2_RFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */
<> 139:856d2700e60b 525 #define _ETM_ETMIDR2_RFE_PC 0x00000000UL /**< Mode PC for ETM_ETMIDR2 */
<> 139:856d2700e60b 526 #define _ETM_ETMIDR2_RFE_CPSR 0x00000001UL /**< Mode CPSR for ETM_ETMIDR2 */
<> 139:856d2700e60b 527 #define ETM_ETMIDR2_RFE_DEFAULT (_ETM_ETMIDR2_RFE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */
<> 139:856d2700e60b 528 #define ETM_ETMIDR2_RFE_PC (_ETM_ETMIDR2_RFE_PC << 0) /**< Shifted mode PC for ETM_ETMIDR2 */
<> 139:856d2700e60b 529 #define ETM_ETMIDR2_RFE_CPSR (_ETM_ETMIDR2_RFE_CPSR << 0) /**< Shifted mode CPSR for ETM_ETMIDR2 */
<> 139:856d2700e60b 530 #define ETM_ETMIDR2_SWP (0x1UL << 1) /**< SWP Transfer Order */
<> 139:856d2700e60b 531 #define _ETM_ETMIDR2_SWP_SHIFT 1 /**< Shift value for ETM_SWP */
<> 139:856d2700e60b 532 #define _ETM_ETMIDR2_SWP_MASK 0x2UL /**< Bit mask for ETM_SWP */
<> 139:856d2700e60b 533 #define _ETM_ETMIDR2_SWP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */
<> 139:856d2700e60b 534 #define _ETM_ETMIDR2_SWP_LOAD 0x00000000UL /**< Mode LOAD for ETM_ETMIDR2 */
<> 139:856d2700e60b 535 #define _ETM_ETMIDR2_SWP_STORE 0x00000001UL /**< Mode STORE for ETM_ETMIDR2 */
<> 139:856d2700e60b 536 #define ETM_ETMIDR2_SWP_DEFAULT (_ETM_ETMIDR2_SWP_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */
<> 139:856d2700e60b 537 #define ETM_ETMIDR2_SWP_LOAD (_ETM_ETMIDR2_SWP_LOAD << 1) /**< Shifted mode LOAD for ETM_ETMIDR2 */
<> 139:856d2700e60b 538 #define ETM_ETMIDR2_SWP_STORE (_ETM_ETMIDR2_SWP_STORE << 1) /**< Shifted mode STORE for ETM_ETMIDR2 */
<> 139:856d2700e60b 539
<> 139:856d2700e60b 540 /* Bit fields for ETM ETMPDSR */
<> 139:856d2700e60b 541 #define _ETM_ETMPDSR_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMPDSR */
<> 139:856d2700e60b 542 #define _ETM_ETMPDSR_MASK 0x00000001UL /**< Mask for ETM_ETMPDSR */
<> 139:856d2700e60b 543 #define ETM_ETMPDSR_ETMUP (0x1UL << 0) /**< ETM Powered Up */
<> 139:856d2700e60b 544 #define _ETM_ETMPDSR_ETMUP_SHIFT 0 /**< Shift value for ETM_ETMUP */
<> 139:856d2700e60b 545 #define _ETM_ETMPDSR_ETMUP_MASK 0x1UL /**< Bit mask for ETM_ETMUP */
<> 139:856d2700e60b 546 #define _ETM_ETMPDSR_ETMUP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPDSR */
<> 139:856d2700e60b 547 #define ETM_ETMPDSR_ETMUP_DEFAULT (_ETM_ETMPDSR_ETMUP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPDSR */
<> 139:856d2700e60b 548
<> 139:856d2700e60b 549 /* Bit fields for ETM ETMISCIN */
<> 139:856d2700e60b 550 #define _ETM_ETMISCIN_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMISCIN */
<> 139:856d2700e60b 551 #define _ETM_ETMISCIN_MASK 0x00000013UL /**< Mask for ETM_ETMISCIN */
<> 139:856d2700e60b 552 #define _ETM_ETMISCIN_EXTIN_SHIFT 0 /**< Shift value for ETM_EXTIN */
<> 139:856d2700e60b 553 #define _ETM_ETMISCIN_EXTIN_MASK 0x3UL /**< Bit mask for ETM_EXTIN */
<> 139:856d2700e60b 554 #define _ETM_ETMISCIN_EXTIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */
<> 139:856d2700e60b 555 #define ETM_ETMISCIN_EXTIN_DEFAULT (_ETM_ETMISCIN_EXTIN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMISCIN */
<> 139:856d2700e60b 556 #define ETM_ETMISCIN_COREHALT (0x1UL << 4) /**< Core Halt */
<> 139:856d2700e60b 557 #define _ETM_ETMISCIN_COREHALT_SHIFT 4 /**< Shift value for ETM_COREHALT */
<> 139:856d2700e60b 558 #define _ETM_ETMISCIN_COREHALT_MASK 0x10UL /**< Bit mask for ETM_COREHALT */
<> 139:856d2700e60b 559 #define _ETM_ETMISCIN_COREHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */
<> 139:856d2700e60b 560 #define ETM_ETMISCIN_COREHALT_DEFAULT (_ETM_ETMISCIN_COREHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMISCIN */
<> 139:856d2700e60b 561
<> 139:856d2700e60b 562 /* Bit fields for ETM ITTRIGOUT */
<> 139:856d2700e60b 563 #define _ETM_ITTRIGOUT_RESETVALUE 0x00000000UL /**< Default value for ETM_ITTRIGOUT */
<> 139:856d2700e60b 564 #define _ETM_ITTRIGOUT_MASK 0x00000001UL /**< Mask for ETM_ITTRIGOUT */
<> 139:856d2700e60b 565 #define ETM_ITTRIGOUT_TRIGGEROUT (0x1UL << 0) /**< Trigger output value */
<> 139:856d2700e60b 566 #define _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT 0 /**< Shift value for ETM_TRIGGEROUT */
<> 139:856d2700e60b 567 #define _ETM_ITTRIGOUT_TRIGGEROUT_MASK 0x1UL /**< Bit mask for ETM_TRIGGEROUT */
<> 139:856d2700e60b 568 #define _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ITTRIGOUT */
<> 139:856d2700e60b 569 #define ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ITTRIGOUT */
<> 139:856d2700e60b 570
<> 139:856d2700e60b 571 /* Bit fields for ETM ETMITATBCTR2 */
<> 139:856d2700e60b 572 #define _ETM_ETMITATBCTR2_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMITATBCTR2 */
<> 139:856d2700e60b 573 #define _ETM_ETMITATBCTR2_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR2 */
<> 139:856d2700e60b 574 #define ETM_ETMITATBCTR2_ATREADY (0x1UL << 0) /**< ATREADY Input Value */
<> 139:856d2700e60b 575 #define _ETM_ETMITATBCTR2_ATREADY_SHIFT 0 /**< Shift value for ETM_ATREADY */
<> 139:856d2700e60b 576 #define _ETM_ETMITATBCTR2_ATREADY_MASK 0x1UL /**< Bit mask for ETM_ATREADY */
<> 139:856d2700e60b 577 #define _ETM_ETMITATBCTR2_ATREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMITATBCTR2 */
<> 139:856d2700e60b 578 #define ETM_ETMITATBCTR2_ATREADY_DEFAULT (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR2 */
<> 139:856d2700e60b 579
<> 139:856d2700e60b 580 /* Bit fields for ETM ETMITATBCTR0 */
<> 139:856d2700e60b 581 #define _ETM_ETMITATBCTR0_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITATBCTR0 */
<> 139:856d2700e60b 582 #define _ETM_ETMITATBCTR0_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR0 */
<> 139:856d2700e60b 583 #define ETM_ETMITATBCTR0_ATVALID (0x1UL << 0) /**< ATVALID Output Value */
<> 139:856d2700e60b 584 #define _ETM_ETMITATBCTR0_ATVALID_SHIFT 0 /**< Shift value for ETM_ATVALID */
<> 139:856d2700e60b 585 #define _ETM_ETMITATBCTR0_ATVALID_MASK 0x1UL /**< Bit mask for ETM_ATVALID */
<> 139:856d2700e60b 586 #define _ETM_ETMITATBCTR0_ATVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITATBCTR0 */
<> 139:856d2700e60b 587 #define ETM_ETMITATBCTR0_ATVALID_DEFAULT (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR0 */
<> 139:856d2700e60b 588
<> 139:856d2700e60b 589 /* Bit fields for ETM ETMITCTRL */
<> 139:856d2700e60b 590 #define _ETM_ETMITCTRL_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITCTRL */
<> 139:856d2700e60b 591 #define _ETM_ETMITCTRL_MASK 0x00000001UL /**< Mask for ETM_ETMITCTRL */
<> 139:856d2700e60b 592 #define ETM_ETMITCTRL_ITEN (0x1UL << 0) /**< Integration Mode Enable */
<> 139:856d2700e60b 593 #define _ETM_ETMITCTRL_ITEN_SHIFT 0 /**< Shift value for ETM_ITEN */
<> 139:856d2700e60b 594 #define _ETM_ETMITCTRL_ITEN_MASK 0x1UL /**< Bit mask for ETM_ITEN */
<> 139:856d2700e60b 595 #define _ETM_ETMITCTRL_ITEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITCTRL */
<> 139:856d2700e60b 596 #define ETM_ETMITCTRL_ITEN_DEFAULT (_ETM_ETMITCTRL_ITEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITCTRL */
<> 139:856d2700e60b 597
<> 139:856d2700e60b 598 /* Bit fields for ETM ETMCLAIMSET */
<> 139:856d2700e60b 599 #define _ETM_ETMCLAIMSET_RESETVALUE 0x0000000FUL /**< Default value for ETM_ETMCLAIMSET */
<> 139:856d2700e60b 600 #define _ETM_ETMCLAIMSET_MASK 0x000000FFUL /**< Mask for ETM_ETMCLAIMSET */
<> 139:856d2700e60b 601 #define _ETM_ETMCLAIMSET_SETTAG_SHIFT 0 /**< Shift value for ETM_SETTAG */
<> 139:856d2700e60b 602 #define _ETM_ETMCLAIMSET_SETTAG_MASK 0xFFUL /**< Bit mask for ETM_SETTAG */
<> 139:856d2700e60b 603 #define _ETM_ETMCLAIMSET_SETTAG_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMCLAIMSET */
<> 139:856d2700e60b 604 #define ETM_ETMCLAIMSET_SETTAG_DEFAULT (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMSET */
<> 139:856d2700e60b 605
<> 139:856d2700e60b 606 /* Bit fields for ETM ETMCLAIMCLR */
<> 139:856d2700e60b 607 #define _ETM_ETMCLAIMCLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCLAIMCLR */
<> 139:856d2700e60b 608 #define _ETM_ETMCLAIMCLR_MASK 0x00000001UL /**< Mask for ETM_ETMCLAIMCLR */
<> 139:856d2700e60b 609 #define ETM_ETMCLAIMCLR_CLRTAG (0x1UL << 0) /**< Tag Bits */
<> 139:856d2700e60b 610 #define _ETM_ETMCLAIMCLR_CLRTAG_SHIFT 0 /**< Shift value for ETM_CLRTAG */
<> 139:856d2700e60b 611 #define _ETM_ETMCLAIMCLR_CLRTAG_MASK 0x1UL /**< Bit mask for ETM_CLRTAG */
<> 139:856d2700e60b 612 #define _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCLAIMCLR */
<> 139:856d2700e60b 613 #define ETM_ETMCLAIMCLR_CLRTAG_DEFAULT (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMCLR */
<> 139:856d2700e60b 614
<> 139:856d2700e60b 615 /* Bit fields for ETM ETMLAR */
<> 139:856d2700e60b 616 #define _ETM_ETMLAR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMLAR */
<> 139:856d2700e60b 617 #define _ETM_ETMLAR_MASK 0x00000001UL /**< Mask for ETM_ETMLAR */
<> 139:856d2700e60b 618 #define ETM_ETMLAR_KEY (0x1UL << 0) /**< Key Value */
<> 139:856d2700e60b 619 #define _ETM_ETMLAR_KEY_SHIFT 0 /**< Shift value for ETM_KEY */
<> 139:856d2700e60b 620 #define _ETM_ETMLAR_KEY_MASK 0x1UL /**< Bit mask for ETM_KEY */
<> 139:856d2700e60b 621 #define _ETM_ETMLAR_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMLAR */
<> 139:856d2700e60b 622 #define ETM_ETMLAR_KEY_DEFAULT (_ETM_ETMLAR_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLAR */
<> 139:856d2700e60b 623
<> 139:856d2700e60b 624 /* Bit fields for ETM ETMLSR */
<> 139:856d2700e60b 625 #define _ETM_ETMLSR_RESETVALUE 0x00000003UL /**< Default value for ETM_ETMLSR */
<> 139:856d2700e60b 626 #define _ETM_ETMLSR_MASK 0x00000003UL /**< Mask for ETM_ETMLSR */
<> 139:856d2700e60b 627 #define ETM_ETMLSR_LOCKIMP (0x1UL << 0) /**< ETM Locking Implemented */
<> 139:856d2700e60b 628 #define _ETM_ETMLSR_LOCKIMP_SHIFT 0 /**< Shift value for ETM_LOCKIMP */
<> 139:856d2700e60b 629 #define _ETM_ETMLSR_LOCKIMP_MASK 0x1UL /**< Bit mask for ETM_LOCKIMP */
<> 139:856d2700e60b 630 #define _ETM_ETMLSR_LOCKIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */
<> 139:856d2700e60b 631 #define ETM_ETMLSR_LOCKIMP_DEFAULT (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLSR */
<> 139:856d2700e60b 632 #define ETM_ETMLSR_LOCKED (0x1UL << 1) /**< ETM locked */
<> 139:856d2700e60b 633 #define _ETM_ETMLSR_LOCKED_SHIFT 1 /**< Shift value for ETM_LOCKED */
<> 139:856d2700e60b 634 #define _ETM_ETMLSR_LOCKED_MASK 0x2UL /**< Bit mask for ETM_LOCKED */
<> 139:856d2700e60b 635 #define _ETM_ETMLSR_LOCKED_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */
<> 139:856d2700e60b 636 #define ETM_ETMLSR_LOCKED_DEFAULT (_ETM_ETMLSR_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMLSR */
<> 139:856d2700e60b 637
<> 139:856d2700e60b 638 /* Bit fields for ETM ETMAUTHSTATUS */
<> 139:856d2700e60b 639 #define _ETM_ETMAUTHSTATUS_RESETVALUE 0x000000C0UL /**< Default value for ETM_ETMAUTHSTATUS */
<> 139:856d2700e60b 640 #define _ETM_ETMAUTHSTATUS_MASK 0x000000FFUL /**< Mask for ETM_ETMAUTHSTATUS */
<> 139:856d2700e60b 641 #define _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT 0 /**< Shift value for ETM_NONSECINVDBG */
<> 139:856d2700e60b 642 #define _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK 0x3UL /**< Bit mask for ETM_NONSECINVDBG */
<> 139:856d2700e60b 643 #define _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
<> 139:856d2700e60b 644 #define ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
<> 139:856d2700e60b 645 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT 2 /**< Shift value for ETM_NONSECNONINVDBG */
<> 139:856d2700e60b 646 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK 0xCUL /**< Bit mask for ETM_NONSECNONINVDBG */
<> 139:856d2700e60b 647 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
<> 139:856d2700e60b 648 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE 0x00000002UL /**< Mode DISABLE for ETM_ETMAUTHSTATUS */
<> 139:856d2700e60b 649 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE 0x00000003UL /**< Mode ENABLE for ETM_ETMAUTHSTATUS */
<> 139:856d2700e60b 650 #define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
<> 139:856d2700e60b 651 #define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2) /**< Shifted mode DISABLE for ETM_ETMAUTHSTATUS */
<> 139:856d2700e60b 652 #define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2) /**< Shifted mode ENABLE for ETM_ETMAUTHSTATUS */
<> 139:856d2700e60b 653 #define _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT 4 /**< Shift value for ETM_SECINVDBG */
<> 139:856d2700e60b 654 #define _ETM_ETMAUTHSTATUS_SECINVDBG_MASK 0x30UL /**< Bit mask for ETM_SECINVDBG */
<> 139:856d2700e60b 655 #define _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
<> 139:856d2700e60b 656 #define ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
<> 139:856d2700e60b 657 #define _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT 6 /**< Shift value for ETM_SECNONINVDBG */
<> 139:856d2700e60b 658 #define _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK 0xC0UL /**< Bit mask for ETM_SECNONINVDBG */
<> 139:856d2700e60b 659 #define _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
<> 139:856d2700e60b 660 #define ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
<> 139:856d2700e60b 661
<> 139:856d2700e60b 662 /* Bit fields for ETM ETMDEVTYPE */
<> 139:856d2700e60b 663 #define _ETM_ETMDEVTYPE_RESETVALUE 0x00000013UL /**< Default value for ETM_ETMDEVTYPE */
<> 139:856d2700e60b 664 #define _ETM_ETMDEVTYPE_MASK 0x000000FFUL /**< Mask for ETM_ETMDEVTYPE */
<> 139:856d2700e60b 665 #define _ETM_ETMDEVTYPE_TRACESRC_SHIFT 0 /**< Shift value for ETM_TRACESRC */
<> 139:856d2700e60b 666 #define _ETM_ETMDEVTYPE_TRACESRC_MASK 0xFUL /**< Bit mask for ETM_TRACESRC */
<> 139:856d2700e60b 667 #define _ETM_ETMDEVTYPE_TRACESRC_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */
<> 139:856d2700e60b 668 #define ETM_ETMDEVTYPE_TRACESRC_DEFAULT (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */
<> 139:856d2700e60b 669 #define _ETM_ETMDEVTYPE_PROCTRACE_SHIFT 4 /**< Shift value for ETM_PROCTRACE */
<> 139:856d2700e60b 670 #define _ETM_ETMDEVTYPE_PROCTRACE_MASK 0xF0UL /**< Bit mask for ETM_PROCTRACE */
<> 139:856d2700e60b 671 #define _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */
<> 139:856d2700e60b 672 #define ETM_ETMDEVTYPE_PROCTRACE_DEFAULT (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */
<> 139:856d2700e60b 673
<> 139:856d2700e60b 674 /* Bit fields for ETM ETMPIDR4 */
<> 139:856d2700e60b 675 #define _ETM_ETMPIDR4_RESETVALUE 0x00000004UL /**< Default value for ETM_ETMPIDR4 */
<> 139:856d2700e60b 676 #define _ETM_ETMPIDR4_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR4 */
<> 139:856d2700e60b 677 #define _ETM_ETMPIDR4_CONTCODE_SHIFT 0 /**< Shift value for ETM_CONTCODE */
<> 139:856d2700e60b 678 #define _ETM_ETMPIDR4_CONTCODE_MASK 0xFUL /**< Bit mask for ETM_CONTCODE */
<> 139:856d2700e60b 679 #define _ETM_ETMPIDR4_CONTCODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMPIDR4 */
<> 139:856d2700e60b 680 #define ETM_ETMPIDR4_CONTCODE_DEFAULT (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */
<> 139:856d2700e60b 681 #define _ETM_ETMPIDR4_COUNT_SHIFT 4 /**< Shift value for ETM_COUNT */
<> 139:856d2700e60b 682 #define _ETM_ETMPIDR4_COUNT_MASK 0xF0UL /**< Bit mask for ETM_COUNT */
<> 139:856d2700e60b 683 #define _ETM_ETMPIDR4_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR4 */
<> 139:856d2700e60b 684 #define ETM_ETMPIDR4_COUNT_DEFAULT (_ETM_ETMPIDR4_COUNT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */
<> 139:856d2700e60b 685
<> 139:856d2700e60b 686 /* Bit fields for ETM ETMPIDR5 */
<> 139:856d2700e60b 687 #define _ETM_ETMPIDR5_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR5 */
<> 139:856d2700e60b 688 #define _ETM_ETMPIDR5_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR5 */
<> 139:856d2700e60b 689
<> 139:856d2700e60b 690 /* Bit fields for ETM ETMPIDR6 */
<> 139:856d2700e60b 691 #define _ETM_ETMPIDR6_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR6 */
<> 139:856d2700e60b 692 #define _ETM_ETMPIDR6_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR6 */
<> 139:856d2700e60b 693
<> 139:856d2700e60b 694 /* Bit fields for ETM ETMPIDR7 */
<> 139:856d2700e60b 695 #define _ETM_ETMPIDR7_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR7 */
<> 139:856d2700e60b 696 #define _ETM_ETMPIDR7_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR7 */
<> 139:856d2700e60b 697
<> 139:856d2700e60b 698 /* Bit fields for ETM ETMPIDR0 */
<> 139:856d2700e60b 699 #define _ETM_ETMPIDR0_RESETVALUE 0x00000025UL /**< Default value for ETM_ETMPIDR0 */
<> 139:856d2700e60b 700 #define _ETM_ETMPIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR0 */
<> 139:856d2700e60b 701 #define _ETM_ETMPIDR0_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */
<> 139:856d2700e60b 702 #define _ETM_ETMPIDR0_PARTNUM_MASK 0xFFUL /**< Bit mask for ETM_PARTNUM */
<> 139:856d2700e60b 703 #define _ETM_ETMPIDR0_PARTNUM_DEFAULT 0x00000025UL /**< Mode DEFAULT for ETM_ETMPIDR0 */
<> 139:856d2700e60b 704 #define ETM_ETMPIDR0_PARTNUM_DEFAULT (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR0 */
<> 139:856d2700e60b 705
<> 139:856d2700e60b 706 /* Bit fields for ETM ETMPIDR1 */
<> 139:856d2700e60b 707 #define _ETM_ETMPIDR1_RESETVALUE 0x000000B9UL /**< Default value for ETM_ETMPIDR1 */
<> 139:856d2700e60b 708 #define _ETM_ETMPIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR1 */
<> 139:856d2700e60b 709 #define _ETM_ETMPIDR1_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */
<> 139:856d2700e60b 710 #define _ETM_ETMPIDR1_PARTNUM_MASK 0xFUL /**< Bit mask for ETM_PARTNUM */
<> 139:856d2700e60b 711 #define _ETM_ETMPIDR1_PARTNUM_DEFAULT 0x00000009UL /**< Mode DEFAULT for ETM_ETMPIDR1 */
<> 139:856d2700e60b 712 #define ETM_ETMPIDR1_PARTNUM_DEFAULT (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */
<> 139:856d2700e60b 713 #define _ETM_ETMPIDR1_IDCODE_SHIFT 4 /**< Shift value for ETM_IDCODE */
<> 139:856d2700e60b 714 #define _ETM_ETMPIDR1_IDCODE_MASK 0xF0UL /**< Bit mask for ETM_IDCODE */
<> 139:856d2700e60b 715 #define _ETM_ETMPIDR1_IDCODE_DEFAULT 0x0000000BUL /**< Mode DEFAULT for ETM_ETMPIDR1 */
<> 139:856d2700e60b 716 #define ETM_ETMPIDR1_IDCODE_DEFAULT (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */
<> 139:856d2700e60b 717
<> 139:856d2700e60b 718 /* Bit fields for ETM ETMPIDR2 */
<> 139:856d2700e60b 719 #define _ETM_ETMPIDR2_RESETVALUE 0x0000000BUL /**< Default value for ETM_ETMPIDR2 */
<> 139:856d2700e60b 720 #define _ETM_ETMPIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR2 */
<> 139:856d2700e60b 721 #define _ETM_ETMPIDR2_IDCODE_SHIFT 0 /**< Shift value for ETM_IDCODE */
<> 139:856d2700e60b 722 #define _ETM_ETMPIDR2_IDCODE_MASK 0x7UL /**< Bit mask for ETM_IDCODE */
<> 139:856d2700e60b 723 #define _ETM_ETMPIDR2_IDCODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
<> 139:856d2700e60b 724 #define ETM_ETMPIDR2_IDCODE_DEFAULT (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
<> 139:856d2700e60b 725 #define ETM_ETMPIDR2_ALWAYS1 (0x1UL << 3) /**< Always 1 */
<> 139:856d2700e60b 726 #define _ETM_ETMPIDR2_ALWAYS1_SHIFT 3 /**< Shift value for ETM_ALWAYS1 */
<> 139:856d2700e60b 727 #define _ETM_ETMPIDR2_ALWAYS1_MASK 0x8UL /**< Bit mask for ETM_ALWAYS1 */
<> 139:856d2700e60b 728 #define _ETM_ETMPIDR2_ALWAYS1_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
<> 139:856d2700e60b 729 #define ETM_ETMPIDR2_ALWAYS1_DEFAULT (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
<> 139:856d2700e60b 730 #define _ETM_ETMPIDR2_REV_SHIFT 4 /**< Shift value for ETM_REV */
<> 139:856d2700e60b 731 #define _ETM_ETMPIDR2_REV_MASK 0xF0UL /**< Bit mask for ETM_REV */
<> 139:856d2700e60b 732 #define _ETM_ETMPIDR2_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
<> 139:856d2700e60b 733 #define ETM_ETMPIDR2_REV_DEFAULT (_ETM_ETMPIDR2_REV_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
<> 139:856d2700e60b 734
<> 139:856d2700e60b 735 /* Bit fields for ETM ETMPIDR3 */
<> 139:856d2700e60b 736 #define _ETM_ETMPIDR3_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR3 */
<> 139:856d2700e60b 737 #define _ETM_ETMPIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR3 */
<> 139:856d2700e60b 738 #define _ETM_ETMPIDR3_CUSTMOD_SHIFT 0 /**< Shift value for ETM_CUSTMOD */
<> 139:856d2700e60b 739 #define _ETM_ETMPIDR3_CUSTMOD_MASK 0xFUL /**< Bit mask for ETM_CUSTMOD */
<> 139:856d2700e60b 740 #define _ETM_ETMPIDR3_CUSTMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */
<> 139:856d2700e60b 741 #define ETM_ETMPIDR3_CUSTMOD_DEFAULT (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */
<> 139:856d2700e60b 742 #define _ETM_ETMPIDR3_REVAND_SHIFT 4 /**< Shift value for ETM_REVAND */
<> 139:856d2700e60b 743 #define _ETM_ETMPIDR3_REVAND_MASK 0xF0UL /**< Bit mask for ETM_REVAND */
<> 139:856d2700e60b 744 #define _ETM_ETMPIDR3_REVAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */
<> 139:856d2700e60b 745 #define ETM_ETMPIDR3_REVAND_DEFAULT (_ETM_ETMPIDR3_REVAND_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */
<> 139:856d2700e60b 746
<> 139:856d2700e60b 747 /* Bit fields for ETM ETMCIDR0 */
<> 139:856d2700e60b 748 #define _ETM_ETMCIDR0_RESETVALUE 0x0000000DUL /**< Default value for ETM_ETMCIDR0 */
<> 139:856d2700e60b 749 #define _ETM_ETMCIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR0 */
<> 139:856d2700e60b 750 #define _ETM_ETMCIDR0_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
<> 139:856d2700e60b 751 #define _ETM_ETMCIDR0_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
<> 139:856d2700e60b 752 #define _ETM_ETMCIDR0_PREAMB_DEFAULT 0x0000000DUL /**< Mode DEFAULT for ETM_ETMCIDR0 */
<> 139:856d2700e60b 753 #define ETM_ETMCIDR0_PREAMB_DEFAULT (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR0 */
<> 139:856d2700e60b 754
<> 139:856d2700e60b 755 /* Bit fields for ETM ETMCIDR1 */
<> 139:856d2700e60b 756 #define _ETM_ETMCIDR1_RESETVALUE 0x00000090UL /**< Default value for ETM_ETMCIDR1 */
<> 139:856d2700e60b 757 #define _ETM_ETMCIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR1 */
<> 139:856d2700e60b 758 #define _ETM_ETMCIDR1_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
<> 139:856d2700e60b 759 #define _ETM_ETMCIDR1_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
<> 139:856d2700e60b 760 #define _ETM_ETMCIDR1_PREAMB_DEFAULT 0x00000090UL /**< Mode DEFAULT for ETM_ETMCIDR1 */
<> 139:856d2700e60b 761 #define ETM_ETMCIDR1_PREAMB_DEFAULT (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR1 */
<> 139:856d2700e60b 762
<> 139:856d2700e60b 763 /* Bit fields for ETM ETMCIDR2 */
<> 139:856d2700e60b 764 #define _ETM_ETMCIDR2_RESETVALUE 0x00000005UL /**< Default value for ETM_ETMCIDR2 */
<> 139:856d2700e60b 765 #define _ETM_ETMCIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR2 */
<> 139:856d2700e60b 766 #define _ETM_ETMCIDR2_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
<> 139:856d2700e60b 767 #define _ETM_ETMCIDR2_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
<> 139:856d2700e60b 768 #define _ETM_ETMCIDR2_PREAMB_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMCIDR2 */
<> 139:856d2700e60b 769 #define ETM_ETMCIDR2_PREAMB_DEFAULT (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR2 */
<> 139:856d2700e60b 770
<> 139:856d2700e60b 771 /* Bit fields for ETM ETMCIDR3 */
<> 139:856d2700e60b 772 #define _ETM_ETMCIDR3_RESETVALUE 0x000000B1UL /**< Default value for ETM_ETMCIDR3 */
<> 139:856d2700e60b 773 #define _ETM_ETMCIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR3 */
<> 139:856d2700e60b 774 #define _ETM_ETMCIDR3_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
<> 139:856d2700e60b 775 #define _ETM_ETMCIDR3_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
<> 139:856d2700e60b 776 #define _ETM_ETMCIDR3_PREAMB_DEFAULT 0x000000B1UL /**< Mode DEFAULT for ETM_ETMCIDR3 */
<> 139:856d2700e60b 777 #define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */
<> 139:856d2700e60b 778
<> 139:856d2700e60b 779 /** @} End of group EFM32PG12B_ETM */
<> 139:856d2700e60b 780 /** @} End of group Parts */
<> 139:856d2700e60b 781