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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32PG12_STK3402/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b_devinfo.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
139:856d2700e60b 
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 139:856d2700e60b 1 /**************************************************************************//**
<> 139:856d2700e60b 2 * @file efm32pg12b_devinfo.h
<> 139:856d2700e60b 3 * @brief EFM32PG12B_DEVINFO register and bit field definitions
<> 139:856d2700e60b 4 * @version 5.1.2
<> 139:856d2700e60b 5 ******************************************************************************
<> 139:856d2700e60b 6 * @section License
<> 139:856d2700e60b 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 139:856d2700e60b 8 ******************************************************************************
<> 139:856d2700e60b 9 *
<> 139:856d2700e60b 10 * Permission is granted to anyone to use this software for any purpose,
<> 139:856d2700e60b 11 * including commercial applications, and to alter it and redistribute it
<> 139:856d2700e60b 12 * freely, subject to the following restrictions:
<> 139:856d2700e60b 13 *
<> 139:856d2700e60b 14 * 1. The origin of this software must not be misrepresented; you must not
<> 139:856d2700e60b 15 * claim that you wrote the original software.@n
<> 139:856d2700e60b 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 139:856d2700e60b 17 * misrepresented as being the original software.@n
<> 139:856d2700e60b 18 * 3. This notice may not be removed or altered from any source distribution.
<> 139:856d2700e60b 19 *
<> 139:856d2700e60b 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 139:856d2700e60b 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 139:856d2700e60b 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 139:856d2700e60b 23 * kind, including, but not limited to, any implied warranties of
<> 139:856d2700e60b 24 * merchantability or fitness for any particular purpose or warranties against
<> 139:856d2700e60b 25 * infringement of any proprietary rights of a third party.
<> 139:856d2700e60b 26 *
<> 139:856d2700e60b 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 139:856d2700e60b 28 * incidental, or special damages, or any other relief, or for any claim by
<> 139:856d2700e60b 29 * any third party, arising from your use of this Software.
<> 139:856d2700e60b 30 *
<> 139:856d2700e60b 31 *****************************************************************************/
<> 139:856d2700e60b 32 /**************************************************************************//**
<> 139:856d2700e60b 33 * @addtogroup Parts
<> 139:856d2700e60b 34 * @{
<> 139:856d2700e60b 35 ******************************************************************************/
<> 139:856d2700e60b 36 /**************************************************************************//**
<> 139:856d2700e60b 37 * @defgroup EFM32PG12B_DEVINFO
<> 139:856d2700e60b 38 * @{
<> 139:856d2700e60b 39 *****************************************************************************/
<> 139:856d2700e60b 40
<> 139:856d2700e60b 41 typedef struct
<> 139:856d2700e60b 42 {
<> 139:856d2700e60b 43 __IM uint32_t CAL; /**< CRC of DI-page and calibration temperature */
<> 139:856d2700e60b 44 uint32_t RESERVED0[7]; /**< Reserved for future use **/
<> 139:856d2700e60b 45 __IM uint32_t EXTINFO; /**< External Component description */
<> 139:856d2700e60b 46 uint32_t RESERVED1[1]; /**< Reserved for future use **/
<> 139:856d2700e60b 47 __IM uint32_t EUI48L; /**< EUI48 OUI and Unique identifier */
<> 139:856d2700e60b 48 __IM uint32_t EUI48H; /**< OUI */
<> 139:856d2700e60b 49 __IM uint32_t CUSTOMINFO; /**< Custom information */
<> 139:856d2700e60b 50 __IM uint32_t MEMINFO; /**< Flash page size and misc. chip information */
<> 139:856d2700e60b 51 uint32_t RESERVED2[2]; /**< Reserved for future use **/
<> 139:856d2700e60b 52 __IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
<> 139:856d2700e60b 53 __IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */
<> 139:856d2700e60b 54 __IM uint32_t MSIZE; /**< Flash and SRAM Memory size in kB */
<> 139:856d2700e60b 55 __IM uint32_t PART; /**< Part description */
<> 139:856d2700e60b 56 __IM uint32_t DEVINFOREV; /**< Device information page revision */
<> 139:856d2700e60b 57 __IM uint32_t EMUTEMP; /**< EMU Temperature Calibration Information */
<> 139:856d2700e60b 58 uint32_t RESERVED3[2]; /**< Reserved for future use **/
<> 139:856d2700e60b 59 __IM uint32_t ADC0CAL0; /**< ADC0 calibration register 0 */
<> 139:856d2700e60b 60 __IM uint32_t ADC0CAL1; /**< ADC0 calibration register 1 */
<> 139:856d2700e60b 61 __IM uint32_t ADC0CAL2; /**< ADC0 calibration register 2 */
<> 139:856d2700e60b 62 __IM uint32_t ADC0CAL3; /**< ADC0 calibration register 3 */
<> 139:856d2700e60b 63 uint32_t RESERVED4[4]; /**< Reserved for future use **/
<> 139:856d2700e60b 64 __IM uint32_t HFRCOCAL0; /**< HFRCO Calibration Register (4 MHz) */
<> 139:856d2700e60b 65 uint32_t RESERVED5[2]; /**< Reserved for future use **/
<> 139:856d2700e60b 66 __IM uint32_t HFRCOCAL3; /**< HFRCO Calibration Register (7 MHz) */
<> 139:856d2700e60b 67 uint32_t RESERVED6[2]; /**< Reserved for future use **/
<> 139:856d2700e60b 68 __IM uint32_t HFRCOCAL6; /**< HFRCO Calibration Register (13 MHz) */
<> 139:856d2700e60b 69 __IM uint32_t HFRCOCAL7; /**< HFRCO Calibration Register (16 MHz) */
<> 139:856d2700e60b 70 __IM uint32_t HFRCOCAL8; /**< HFRCO Calibration Register (19 MHz) */
<> 139:856d2700e60b 71 uint32_t RESERVED7[1]; /**< Reserved for future use **/
<> 139:856d2700e60b 72 __IM uint32_t HFRCOCAL10; /**< HFRCO Calibration Register (26 MHz) */
<> 139:856d2700e60b 73 __IM uint32_t HFRCOCAL11; /**< HFRCO Calibration Register (32 MHz) */
<> 139:856d2700e60b 74 __IM uint32_t HFRCOCAL12; /**< HFRCO Calibration Register (38 MHz) */
<> 139:856d2700e60b 75 uint32_t RESERVED8[11]; /**< Reserved for future use **/
<> 139:856d2700e60b 76 __IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO Calibration Register (4 MHz) */
<> 139:856d2700e60b 77 uint32_t RESERVED9[2]; /**< Reserved for future use **/
<> 139:856d2700e60b 78 __IM uint32_t AUXHFRCOCAL3; /**< AUXHFRCO Calibration Register (7 MHz) */
<> 139:856d2700e60b 79 uint32_t RESERVED10[2]; /**< Reserved for future use **/
<> 139:856d2700e60b 80 __IM uint32_t AUXHFRCOCAL6; /**< AUXHFRCO Calibration Register (13 MHz) */
<> 139:856d2700e60b 81 __IM uint32_t AUXHFRCOCAL7; /**< AUXHFRCO Calibration Register (16 MHz) */
<> 139:856d2700e60b 82 __IM uint32_t AUXHFRCOCAL8; /**< AUXHFRCO Calibration Register (19 MHz) */
<> 139:856d2700e60b 83 uint32_t RESERVED11[1]; /**< Reserved for future use **/
<> 139:856d2700e60b 84 __IM uint32_t AUXHFRCOCAL10; /**< AUXHFRCO Calibration Register (26 MHz) */
<> 139:856d2700e60b 85 __IM uint32_t AUXHFRCOCAL11; /**< AUXHFRCO Calibration Register (32 MHz) */
<> 139:856d2700e60b 86 __IM uint32_t AUXHFRCOCAL12; /**< AUXHFRCO Calibration Register (38 MHz) */
<> 139:856d2700e60b 87 uint32_t RESERVED12[11]; /**< Reserved for future use **/
<> 139:856d2700e60b 88 __IM uint32_t VMONCAL0; /**< VMON Calibration Register 0 */
<> 139:856d2700e60b 89 __IM uint32_t VMONCAL1; /**< VMON Calibration Register 1 */
<> 139:856d2700e60b 90 __IM uint32_t VMONCAL2; /**< VMON Calibration Register 2 */
<> 139:856d2700e60b 91 uint32_t RESERVED13[3]; /**< Reserved for future use **/
<> 139:856d2700e60b 92 __IM uint32_t IDAC0CAL0; /**< IDAC0 Calibration Register 0 */
<> 139:856d2700e60b 93 __IM uint32_t IDAC0CAL1; /**< IDAC0 Calibration Register 1 */
<> 139:856d2700e60b 94 uint32_t RESERVED14[2]; /**< Reserved for future use **/
<> 139:856d2700e60b 95 __IM uint32_t DCDCLNVCTRL0; /**< DCDC Low-noise VREF Trim Register 0 */
<> 139:856d2700e60b 96 __IM uint32_t DCDCLPVCTRL0; /**< DCDC Low-power VREF Trim Register 0 */
<> 139:856d2700e60b 97 __IM uint32_t DCDCLPVCTRL1; /**< DCDC Low-power VREF Trim Register 1 */
<> 139:856d2700e60b 98 __IM uint32_t DCDCLPVCTRL2; /**< DCDC Low-power VREF Trim Register 2 */
<> 139:856d2700e60b 99 __IM uint32_t DCDCLPVCTRL3; /**< DCDC Low-power VREF Trim Register 3 */
<> 139:856d2700e60b 100 __IM uint32_t DCDCLPCMPHYSSEL0; /**< DCDC LPCMPHYSSEL Trim Register 0 */
<> 139:856d2700e60b 101 __IM uint32_t DCDCLPCMPHYSSEL1; /**< DCDC LPCMPHYSSEL Trim Register 1 */
<> 139:856d2700e60b 102 __IM uint32_t VDAC0MAINCAL; /**< VDAC0 Cals for Main Path */
<> 139:856d2700e60b 103 __IM uint32_t VDAC0ALTCAL; /**< VDAC0 Cals for Alternate Path */
<> 139:856d2700e60b 104 __IM uint32_t VDAC0CH1CAL; /**< VDAC0 CH1 Error Cal */
<> 139:856d2700e60b 105 __IM uint32_t OPA0CAL0; /**< OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */
<> 139:856d2700e60b 106 __IM uint32_t OPA0CAL1; /**< OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */
<> 139:856d2700e60b 107 __IM uint32_t OPA0CAL2; /**< OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */
<> 139:856d2700e60b 108 __IM uint32_t OPA0CAL3; /**< OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */
<> 139:856d2700e60b 109 __IM uint32_t OPA1CAL0; /**< OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */
<> 139:856d2700e60b 110 __IM uint32_t OPA1CAL1; /**< OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */
<> 139:856d2700e60b 111 __IM uint32_t OPA1CAL2; /**< OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */
<> 139:856d2700e60b 112 __IM uint32_t OPA1CAL3; /**< OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */
<> 139:856d2700e60b 113 __IM uint32_t OPA2CAL0; /**< OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */
<> 139:856d2700e60b 114 __IM uint32_t OPA2CAL1; /**< OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */
<> 139:856d2700e60b 115 __IM uint32_t OPA2CAL2; /**< OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */
<> 139:856d2700e60b 116 __IM uint32_t OPA2CAL3; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */
<> 139:856d2700e60b 117 __IM uint32_t CSENGAINCAL; /**< Cap Sense Gain Adjustment */
<> 139:856d2700e60b 118 uint32_t RESERVED15[3]; /**< Reserved for future use **/
<> 139:856d2700e60b 119 __IM uint32_t OPA0CAL4; /**< OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */
<> 139:856d2700e60b 120 __IM uint32_t OPA0CAL5; /**< OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */
<> 139:856d2700e60b 121 __IM uint32_t OPA0CAL6; /**< OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */
<> 139:856d2700e60b 122 __IM uint32_t OPA0CAL7; /**< OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */
<> 139:856d2700e60b 123 __IM uint32_t OPA1CAL4; /**< OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */
<> 139:856d2700e60b 124 __IM uint32_t OPA1CAL5; /**< OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */
<> 139:856d2700e60b 125 __IM uint32_t OPA1CAL6; /**< OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */
<> 139:856d2700e60b 126 __IM uint32_t OPA1CAL7; /**< OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */
<> 139:856d2700e60b 127 __IM uint32_t OPA2CAL4; /**< OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */
<> 139:856d2700e60b 128 __IM uint32_t OPA2CAL5; /**< OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */
<> 139:856d2700e60b 129 __IM uint32_t OPA2CAL6; /**< OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */
<> 139:856d2700e60b 130 __IM uint32_t OPA2CAL7; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */
<> 139:856d2700e60b 131 } DEVINFO_TypeDef; /** @} */
<> 139:856d2700e60b 132
<> 139:856d2700e60b 133 /**************************************************************************//**
<> 139:856d2700e60b 134 * @defgroup EFM32PG12B_DEVINFO_BitFields
<> 139:856d2700e60b 135 * @{
<> 139:856d2700e60b 136 *****************************************************************************/
<> 139:856d2700e60b 137
<> 139:856d2700e60b 138 /* Bit fields for DEVINFO CAL */
<> 139:856d2700e60b 139 #define _DEVINFO_CAL_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_CAL */
<> 139:856d2700e60b 140 #define _DEVINFO_CAL_CRC_SHIFT 0 /**< Shift value for CRC */
<> 139:856d2700e60b 141 #define _DEVINFO_CAL_CRC_MASK 0xFFFFUL /**< Bit mask for CRC */
<> 139:856d2700e60b 142 #define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Shift value for TEMP */
<> 139:856d2700e60b 143 #define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL /**< Bit mask for TEMP */
<> 139:856d2700e60b 144
<> 139:856d2700e60b 145 /* Bit fields for DEVINFO EXTINFO */
<> 139:856d2700e60b 146 #define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */
<> 139:856d2700e60b 147 #define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for TYPE */
<> 139:856d2700e60b 148 #define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for TYPE */
<> 139:856d2700e60b 149 #define _DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL /**< Mode IS25LQ040B for DEVINFO_EXTINFO */
<> 139:856d2700e60b 150 #define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */
<> 139:856d2700e60b 151 #define DEVINFO_EXTINFO_TYPE_IS25LQ040B (_DEVINFO_EXTINFO_TYPE_IS25LQ040B << 0) /**< Shifted mode IS25LQ040B for DEVINFO_EXTINFO */
<> 139:856d2700e60b 152 #define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */
<> 139:856d2700e60b 153 #define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for CONNECTION */
<> 139:856d2700e60b 154 #define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for CONNECTION */
<> 139:856d2700e60b 155 #define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000001UL /**< Mode SPI for DEVINFO_EXTINFO */
<> 139:856d2700e60b 156 #define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */
<> 139:856d2700e60b 157 #define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */
<> 139:856d2700e60b 158 #define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */
<> 139:856d2700e60b 159 #define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for REV */
<> 139:856d2700e60b 160 #define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for REV */
<> 139:856d2700e60b 161 #define _DEVINFO_EXTINFO_REV_REV1 0x00000001UL /**< Mode REV1 for DEVINFO_EXTINFO */
<> 139:856d2700e60b 162 #define _DEVINFO_EXTINFO_REV_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */
<> 139:856d2700e60b 163 #define DEVINFO_EXTINFO_REV_REV1 (_DEVINFO_EXTINFO_REV_REV1 << 16) /**< Shifted mode REV1 for DEVINFO_EXTINFO */
<> 139:856d2700e60b 164 #define DEVINFO_EXTINFO_REV_NONE (_DEVINFO_EXTINFO_REV_NONE << 16) /**< Shifted mode NONE for DEVINFO_EXTINFO */
<> 139:856d2700e60b 165
<> 139:856d2700e60b 166 /* Bit fields for DEVINFO EUI48L */
<> 139:856d2700e60b 167 #define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */
<> 139:856d2700e60b 168 #define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for UNIQUEID */
<> 139:856d2700e60b 169 #define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for UNIQUEID */
<> 139:856d2700e60b 170 #define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for OUI48L */
<> 139:856d2700e60b 171 #define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for OUI48L */
<> 139:856d2700e60b 172
<> 139:856d2700e60b 173 /* Bit fields for DEVINFO EUI48H */
<> 139:856d2700e60b 174 #define _DEVINFO_EUI48H_MASK 0x0000FFFFUL /**< Mask for DEVINFO_EUI48H */
<> 139:856d2700e60b 175 #define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for OUI48H */
<> 139:856d2700e60b 176 #define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for OUI48H */
<> 139:856d2700e60b 177
<> 139:856d2700e60b 178 /* Bit fields for DEVINFO CUSTOMINFO */
<> 139:856d2700e60b 179 #define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */
<> 139:856d2700e60b 180 #define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for PARTNO */
<> 139:856d2700e60b 181 #define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for PARTNO */
<> 139:856d2700e60b 182
<> 139:856d2700e60b 183 /* Bit fields for DEVINFO MEMINFO */
<> 139:856d2700e60b 184 #define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */
<> 139:856d2700e60b 185 #define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0 /**< Shift value for TEMPGRADE */
<> 139:856d2700e60b 186 #define _DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for TEMPGRADE */
<> 139:856d2700e60b 187 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_MEMINFO */
<> 139:856d2700e60b 188 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_MEMINFO */
<> 139:856d2700e60b 189 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_MEMINFO */
<> 139:856d2700e60b 190 #define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_MEMINFO */
<> 139:856d2700e60b 191 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO85 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_MEMINFO */
<> 139:856d2700e60b 192 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO125 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_MEMINFO */
<> 139:856d2700e60b 193 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO105 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_MEMINFO */
<> 139:856d2700e60b 194 #define DEVINFO_MEMINFO_TEMPGRADE_N0TO70 (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_MEMINFO */
<> 139:856d2700e60b 195 #define _DEVINFO_MEMINFO_PKGTYPE_SHIFT 8 /**< Shift value for PKGTYPE */
<> 139:856d2700e60b 196 #define _DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for PKGTYPE */
<> 139:856d2700e60b 197 #define _DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_MEMINFO */
<> 139:856d2700e60b 198 #define _DEVINFO_MEMINFO_PKGTYPE_BGA 0x0000004CUL /**< Mode BGA for DEVINFO_MEMINFO */
<> 139:856d2700e60b 199 #define _DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_MEMINFO */
<> 139:856d2700e60b 200 #define _DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_MEMINFO */
<> 139:856d2700e60b 201 #define DEVINFO_MEMINFO_PKGTYPE_WLCSP (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_MEMINFO */
<> 139:856d2700e60b 202 #define DEVINFO_MEMINFO_PKGTYPE_BGA (_DEVINFO_MEMINFO_PKGTYPE_BGA << 8) /**< Shifted mode BGA for DEVINFO_MEMINFO */
<> 139:856d2700e60b 203 #define DEVINFO_MEMINFO_PKGTYPE_QFN (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_MEMINFO */
<> 139:856d2700e60b 204 #define DEVINFO_MEMINFO_PKGTYPE_QFP (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_MEMINFO */
<> 139:856d2700e60b 205 #define _DEVINFO_MEMINFO_PINCOUNT_SHIFT 16 /**< Shift value for PINCOUNT */
<> 139:856d2700e60b 206 #define _DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for PINCOUNT */
<> 139:856d2700e60b 207 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Shift value for FLASH_PAGE_SIZE */
<> 139:856d2700e60b 208 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Bit mask for FLASH_PAGE_SIZE */
<> 139:856d2700e60b 209
<> 139:856d2700e60b 210 /* Bit fields for DEVINFO UNIQUEL */
<> 139:856d2700e60b 211 #define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEL */
<> 139:856d2700e60b 212 #define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0 /**< Shift value for UNIQUEL */
<> 139:856d2700e60b 213 #define _DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEL */
<> 139:856d2700e60b 214
<> 139:856d2700e60b 215 /* Bit fields for DEVINFO UNIQUEH */
<> 139:856d2700e60b 216 #define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEH */
<> 139:856d2700e60b 217 #define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0 /**< Shift value for UNIQUEH */
<> 139:856d2700e60b 218 #define _DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEH */
<> 139:856d2700e60b 219
<> 139:856d2700e60b 220 /* Bit fields for DEVINFO MSIZE */
<> 139:856d2700e60b 221 #define _DEVINFO_MSIZE_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MSIZE */
<> 139:856d2700e60b 222 #define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for FLASH */
<> 139:856d2700e60b 223 #define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for FLASH */
<> 139:856d2700e60b 224 #define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for SRAM */
<> 139:856d2700e60b 225 #define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Bit mask for SRAM */
<> 139:856d2700e60b 226
<> 139:856d2700e60b 227 /* Bit fields for DEVINFO PART */
<> 139:856d2700e60b 228 #define _DEVINFO_PART_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_PART */
<> 139:856d2700e60b 229 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Shift value for DEVICE_NUMBER */
<> 139:856d2700e60b 230 #define _DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL /**< Bit mask for DEVICE_NUMBER */
<> 139:856d2700e60b 231 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Shift value for DEVICE_FAMILY */
<> 139:856d2700e60b 232 #define _DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL /**< Bit mask for DEVICE_FAMILY */
<> 139:856d2700e60b 233 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_PART */
<> 139:856d2700e60b 234 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_PART */
<> 139:856d2700e60b 235 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_PART */
<> 139:856d2700e60b 236 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_PART */
<> 139:856d2700e60b 237 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_PART */
<> 139:856d2700e60b 238 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_PART */
<> 139:856d2700e60b 239 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_PART */
<> 139:856d2700e60b 240 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_PART */
<> 139:856d2700e60b 241 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_PART */
<> 139:856d2700e60b 242 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_PART */
<> 139:856d2700e60b 243 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P 0x0000001CUL /**< Mode EFR32MG2P for DEVINFO_PART */
<> 139:856d2700e60b 244 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_PART */
<> 139:856d2700e60b 245 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_PART */
<> 139:856d2700e60b 246 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_PART */
<> 139:856d2700e60b 247 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_PART */
<> 139:856d2700e60b 248 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_PART */
<> 139:856d2700e60b 249 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_PART */
<> 139:856d2700e60b 250 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_PART */
<> 139:856d2700e60b 251 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_PART */
<> 139:856d2700e60b 252 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_PART */
<> 139:856d2700e60b 253 #define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */
<> 139:856d2700e60b 254 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */
<> 139:856d2700e60b 255 #define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL /**< Mode GG for DEVINFO_PART */
<> 139:856d2700e60b 256 #define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */
<> 139:856d2700e60b 257 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_PART */
<> 139:856d2700e60b 258 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_PART */
<> 139:856d2700e60b 259 #define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL /**< Mode LG for DEVINFO_PART */
<> 139:856d2700e60b 260 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */
<> 139:856d2700e60b 261 #define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL /**< Mode WG for DEVINFO_PART */
<> 139:856d2700e60b 262 #define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL /**< Mode ZG for DEVINFO_PART */
<> 139:856d2700e60b 263 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_PART */
<> 139:856d2700e60b 264 #define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */
<> 139:856d2700e60b 265 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_PART */
<> 139:856d2700e60b 266 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_PART */
<> 139:856d2700e60b 267 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */
<> 139:856d2700e60b 268 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_PART */
<> 139:856d2700e60b 269 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_PART */
<> 139:856d2700e60b 270 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_PART */
<> 139:856d2700e60b 271 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_PART */
<> 139:856d2700e60b 272 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_PART */
<> 139:856d2700e60b 273 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_PART */
<> 139:856d2700e60b 274 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_PART */
<> 139:856d2700e60b 275 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_PART */
<> 139:856d2700e60b 276 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_PART */
<> 139:856d2700e60b 277 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_PART */
<> 139:856d2700e60b 278 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_PART */
<> 139:856d2700e60b 279 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_PART */
<> 139:856d2700e60b 280 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_PART */
<> 139:856d2700e60b 281 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_PART */
<> 139:856d2700e60b 282 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_PART */
<> 139:856d2700e60b 283 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P << 16) /**< Shifted mode EFR32MG2P for DEVINFO_PART */
<> 139:856d2700e60b 284 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_PART */
<> 139:856d2700e60b 285 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_PART */
<> 139:856d2700e60b 286 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_PART */
<> 139:856d2700e60b 287 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_PART */
<> 139:856d2700e60b 288 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_PART */
<> 139:856d2700e60b 289 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_PART */
<> 139:856d2700e60b 290 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_PART */
<> 139:856d2700e60b 291 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_PART */
<> 139:856d2700e60b 292 #define DEVINFO_PART_DEVICE_FAMILY_EFM32G (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_PART */
<> 139:856d2700e60b 293 #define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */
<> 139:856d2700e60b 294 #define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */
<> 139:856d2700e60b 295 #define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16) /**< Shifted mode GG for DEVINFO_PART */
<> 139:856d2700e60b 296 #define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */
<> 139:856d2700e60b 297 #define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_PART */
<> 139:856d2700e60b 298 #define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_PART */
<> 139:856d2700e60b 299 #define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16) /**< Shifted mode LG for DEVINFO_PART */
<> 139:856d2700e60b 300 #define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */
<> 139:856d2700e60b 301 #define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16) /**< Shifted mode WG for DEVINFO_PART */
<> 139:856d2700e60b 302 #define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16) /**< Shifted mode ZG for DEVINFO_PART */
<> 139:856d2700e60b 303 #define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_PART */
<> 139:856d2700e60b 304 #define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */
<> 139:856d2700e60b 305 #define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_PART */
<> 139:856d2700e60b 306 #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */
<> 139:856d2700e60b 307 #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */
<> 139:856d2700e60b 308 #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_PART */
<> 139:856d2700e60b 309 #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_PART */
<> 139:856d2700e60b 310 #define DEVINFO_PART_DEVICE_FAMILY_EZR32LG (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_PART */
<> 139:856d2700e60b 311 #define DEVINFO_PART_DEVICE_FAMILY_EZR32WG (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_PART */
<> 139:856d2700e60b 312 #define DEVINFO_PART_DEVICE_FAMILY_EZR32HG (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_PART */
<> 139:856d2700e60b 313 #define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Shift value for PROD_REV */
<> 139:856d2700e60b 314 #define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Bit mask for PROD_REV */
<> 139:856d2700e60b 315
<> 139:856d2700e60b 316 /* Bit fields for DEVINFO DEVINFOREV */
<> 139:856d2700e60b 317 #define _DEVINFO_DEVINFOREV_MASK 0x000000FFUL /**< Mask for DEVINFO_DEVINFOREV */
<> 139:856d2700e60b 318 #define _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT 0 /**< Shift value for DEVINFOREV */
<> 139:856d2700e60b 319 #define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK 0xFFUL /**< Bit mask for DEVINFOREV */
<> 139:856d2700e60b 320
<> 139:856d2700e60b 321 /* Bit fields for DEVINFO EMUTEMP */
<> 139:856d2700e60b 322 #define _DEVINFO_EMUTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_EMUTEMP */
<> 139:856d2700e60b 323 #define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0 /**< Shift value for EMUTEMPROOM */
<> 139:856d2700e60b 324 #define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL /**< Bit mask for EMUTEMPROOM */
<> 139:856d2700e60b 325
<> 139:856d2700e60b 326 /* Bit fields for DEVINFO ADC0CAL0 */
<> 139:856d2700e60b 327 #define _DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL0 */
<> 139:856d2700e60b 328 #define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0 /**< Shift value for OFFSET1V25 */
<> 139:856d2700e60b 329 #define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL /**< Bit mask for OFFSET1V25 */
<> 139:856d2700e60b 330 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4 /**< Shift value for NEGSEOFFSET1V25 */
<> 139:856d2700e60b 331 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET1V25 */
<> 139:856d2700e60b 332 #define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8 /**< Shift value for GAIN1V25 */
<> 139:856d2700e60b 333 #define _DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL /**< Bit mask for GAIN1V25 */
<> 139:856d2700e60b 334 #define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16 /**< Shift value for OFFSET2V5 */
<> 139:856d2700e60b 335 #define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL /**< Bit mask for OFFSET2V5 */
<> 139:856d2700e60b 336 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20 /**< Shift value for NEGSEOFFSET2V5 */
<> 139:856d2700e60b 337 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET2V5 */
<> 139:856d2700e60b 338 #define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24 /**< Shift value for GAIN2V5 */
<> 139:856d2700e60b 339 #define _DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL /**< Bit mask for GAIN2V5 */
<> 139:856d2700e60b 340
<> 139:856d2700e60b 341 /* Bit fields for DEVINFO ADC0CAL1 */
<> 139:856d2700e60b 342 #define _DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL1 */
<> 139:856d2700e60b 343 #define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0 /**< Shift value for OFFSETVDD */
<> 139:856d2700e60b 344 #define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL /**< Bit mask for OFFSETVDD */
<> 139:856d2700e60b 345 #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4 /**< Shift value for NEGSEOFFSETVDD */
<> 139:856d2700e60b 346 #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSETVDD */
<> 139:856d2700e60b 347 #define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8 /**< Shift value for GAINVDD */
<> 139:856d2700e60b 348 #define _DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL /**< Bit mask for GAINVDD */
<> 139:856d2700e60b 349 #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16 /**< Shift value for OFFSET5VDIFF */
<> 139:856d2700e60b 350 #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL /**< Bit mask for OFFSET5VDIFF */
<> 139:856d2700e60b 351 #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20 /**< Shift value for NEGSEOFFSET5VDIFF */
<> 139:856d2700e60b 352 #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET5VDIFF */
<> 139:856d2700e60b 353 #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24 /**< Shift value for GAIN5VDIFF */
<> 139:856d2700e60b 354 #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL /**< Bit mask for GAIN5VDIFF */
<> 139:856d2700e60b 355
<> 139:856d2700e60b 356 /* Bit fields for DEVINFO ADC0CAL2 */
<> 139:856d2700e60b 357 #define _DEVINFO_ADC0CAL2_MASK 0x000000FFUL /**< Mask for DEVINFO_ADC0CAL2 */
<> 139:856d2700e60b 358 #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0 /**< Shift value for OFFSET2XVDD */
<> 139:856d2700e60b 359 #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL /**< Bit mask for OFFSET2XVDD */
<> 139:856d2700e60b 360 #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4 /**< Shift value for NEGSEOFFSET2XVDD */
<> 139:856d2700e60b 361 #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET2XVDD */
<> 139:856d2700e60b 362
<> 139:856d2700e60b 363 /* Bit fields for DEVINFO ADC0CAL3 */
<> 139:856d2700e60b 364 #define _DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL /**< Mask for DEVINFO_ADC0CAL3 */
<> 139:856d2700e60b 365 #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4 /**< Shift value for TEMPREAD1V25 */
<> 139:856d2700e60b 366 #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL /**< Bit mask for TEMPREAD1V25 */
<> 139:856d2700e60b 367
<> 139:856d2700e60b 368 /* Bit fields for DEVINFO HFRCOCAL0 */
<> 139:856d2700e60b 369 #define _DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL0 */
<> 139:856d2700e60b 370 #define _DEVINFO_HFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */
<> 139:856d2700e60b 371 #define _DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
<> 139:856d2700e60b 372 #define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
<> 139:856d2700e60b 373 #define _DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
<> 139:856d2700e60b 374 #define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
<> 139:856d2700e60b 375 #define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
<> 139:856d2700e60b 376 #define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
<> 139:856d2700e60b 377 #define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
<> 139:856d2700e60b 378 #define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
<> 139:856d2700e60b 379 #define _DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
<> 139:856d2700e60b 380 #define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
<> 139:856d2700e60b 381 #define _DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
<> 139:856d2700e60b 382 #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
<> 139:856d2700e60b 383 #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
<> 139:856d2700e60b 384 #define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
<> 139:856d2700e60b 385 #define _DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
<> 139:856d2700e60b 386
<> 139:856d2700e60b 387 /* Bit fields for DEVINFO HFRCOCAL3 */
<> 139:856d2700e60b 388 #define _DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL3 */
<> 139:856d2700e60b 389 #define _DEVINFO_HFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */
<> 139:856d2700e60b 390 #define _DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
<> 139:856d2700e60b 391 #define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
<> 139:856d2700e60b 392 #define _DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
<> 139:856d2700e60b 393 #define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
<> 139:856d2700e60b 394 #define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
<> 139:856d2700e60b 395 #define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
<> 139:856d2700e60b 396 #define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
<> 139:856d2700e60b 397 #define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
<> 139:856d2700e60b 398 #define _DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
<> 139:856d2700e60b 399 #define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
<> 139:856d2700e60b 400 #define _DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
<> 139:856d2700e60b 401 #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
<> 139:856d2700e60b 402 #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
<> 139:856d2700e60b 403 #define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
<> 139:856d2700e60b 404 #define _DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
<> 139:856d2700e60b 405
<> 139:856d2700e60b 406 /* Bit fields for DEVINFO HFRCOCAL6 */
<> 139:856d2700e60b 407 #define _DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL6 */
<> 139:856d2700e60b 408 #define _DEVINFO_HFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */
<> 139:856d2700e60b 409 #define _DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
<> 139:856d2700e60b 410 #define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
<> 139:856d2700e60b 411 #define _DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
<> 139:856d2700e60b 412 #define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
<> 139:856d2700e60b 413 #define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
<> 139:856d2700e60b 414 #define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
<> 139:856d2700e60b 415 #define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
<> 139:856d2700e60b 416 #define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
<> 139:856d2700e60b 417 #define _DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
<> 139:856d2700e60b 418 #define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
<> 139:856d2700e60b 419 #define _DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
<> 139:856d2700e60b 420 #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
<> 139:856d2700e60b 421 #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
<> 139:856d2700e60b 422 #define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
<> 139:856d2700e60b 423 #define _DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
<> 139:856d2700e60b 424
<> 139:856d2700e60b 425 /* Bit fields for DEVINFO HFRCOCAL7 */
<> 139:856d2700e60b 426 #define _DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL7 */
<> 139:856d2700e60b 427 #define _DEVINFO_HFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */
<> 139:856d2700e60b 428 #define _DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
<> 139:856d2700e60b 429 #define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
<> 139:856d2700e60b 430 #define _DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
<> 139:856d2700e60b 431 #define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
<> 139:856d2700e60b 432 #define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
<> 139:856d2700e60b 433 #define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
<> 139:856d2700e60b 434 #define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
<> 139:856d2700e60b 435 #define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
<> 139:856d2700e60b 436 #define _DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
<> 139:856d2700e60b 437 #define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
<> 139:856d2700e60b 438 #define _DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
<> 139:856d2700e60b 439 #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
<> 139:856d2700e60b 440 #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
<> 139:856d2700e60b 441 #define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
<> 139:856d2700e60b 442 #define _DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
<> 139:856d2700e60b 443
<> 139:856d2700e60b 444 /* Bit fields for DEVINFO HFRCOCAL8 */
<> 139:856d2700e60b 445 #define _DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL8 */
<> 139:856d2700e60b 446 #define _DEVINFO_HFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */
<> 139:856d2700e60b 447 #define _DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
<> 139:856d2700e60b 448 #define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
<> 139:856d2700e60b 449 #define _DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
<> 139:856d2700e60b 450 #define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
<> 139:856d2700e60b 451 #define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
<> 139:856d2700e60b 452 #define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
<> 139:856d2700e60b 453 #define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
<> 139:856d2700e60b 454 #define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
<> 139:856d2700e60b 455 #define _DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
<> 139:856d2700e60b 456 #define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
<> 139:856d2700e60b 457 #define _DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
<> 139:856d2700e60b 458 #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
<> 139:856d2700e60b 459 #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
<> 139:856d2700e60b 460 #define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
<> 139:856d2700e60b 461 #define _DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
<> 139:856d2700e60b 462
<> 139:856d2700e60b 463 /* Bit fields for DEVINFO HFRCOCAL10 */
<> 139:856d2700e60b 464 #define _DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL10 */
<> 139:856d2700e60b 465 #define _DEVINFO_HFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */
<> 139:856d2700e60b 466 #define _DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
<> 139:856d2700e60b 467 #define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
<> 139:856d2700e60b 468 #define _DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
<> 139:856d2700e60b 469 #define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
<> 139:856d2700e60b 470 #define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
<> 139:856d2700e60b 471 #define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
<> 139:856d2700e60b 472 #define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
<> 139:856d2700e60b 473 #define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
<> 139:856d2700e60b 474 #define _DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
<> 139:856d2700e60b 475 #define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
<> 139:856d2700e60b 476 #define _DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
<> 139:856d2700e60b 477 #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
<> 139:856d2700e60b 478 #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
<> 139:856d2700e60b 479 #define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
<> 139:856d2700e60b 480 #define _DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
<> 139:856d2700e60b 481
<> 139:856d2700e60b 482 /* Bit fields for DEVINFO HFRCOCAL11 */
<> 139:856d2700e60b 483 #define _DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL11 */
<> 139:856d2700e60b 484 #define _DEVINFO_HFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */
<> 139:856d2700e60b 485 #define _DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
<> 139:856d2700e60b 486 #define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
<> 139:856d2700e60b 487 #define _DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
<> 139:856d2700e60b 488 #define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
<> 139:856d2700e60b 489 #define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
<> 139:856d2700e60b 490 #define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
<> 139:856d2700e60b 491 #define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
<> 139:856d2700e60b 492 #define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
<> 139:856d2700e60b 493 #define _DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
<> 139:856d2700e60b 494 #define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
<> 139:856d2700e60b 495 #define _DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
<> 139:856d2700e60b 496 #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
<> 139:856d2700e60b 497 #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
<> 139:856d2700e60b 498 #define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
<> 139:856d2700e60b 499 #define _DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
<> 139:856d2700e60b 500
<> 139:856d2700e60b 501 /* Bit fields for DEVINFO HFRCOCAL12 */
<> 139:856d2700e60b 502 #define _DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL12 */
<> 139:856d2700e60b 503 #define _DEVINFO_HFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */
<> 139:856d2700e60b 504 #define _DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
<> 139:856d2700e60b 505 #define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
<> 139:856d2700e60b 506 #define _DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
<> 139:856d2700e60b 507 #define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
<> 139:856d2700e60b 508 #define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
<> 139:856d2700e60b 509 #define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
<> 139:856d2700e60b 510 #define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
<> 139:856d2700e60b 511 #define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
<> 139:856d2700e60b 512 #define _DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
<> 139:856d2700e60b 513 #define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
<> 139:856d2700e60b 514 #define _DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
<> 139:856d2700e60b 515 #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
<> 139:856d2700e60b 516 #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
<> 139:856d2700e60b 517 #define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
<> 139:856d2700e60b 518 #define _DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
<> 139:856d2700e60b 519
<> 139:856d2700e60b 520 /* Bit fields for DEVINFO AUXHFRCOCAL0 */
<> 139:856d2700e60b 521 #define _DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL0 */
<> 139:856d2700e60b 522 #define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */
<> 139:856d2700e60b 523 #define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
<> 139:856d2700e60b 524 #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
<> 139:856d2700e60b 525 #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
<> 139:856d2700e60b 526 #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
<> 139:856d2700e60b 527 #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
<> 139:856d2700e60b 528 #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
<> 139:856d2700e60b 529 #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
<> 139:856d2700e60b 530 #define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
<> 139:856d2700e60b 531 #define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
<> 139:856d2700e60b 532 #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
<> 139:856d2700e60b 533 #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
<> 139:856d2700e60b 534 #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
<> 139:856d2700e60b 535 #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
<> 139:856d2700e60b 536 #define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
<> 139:856d2700e60b 537 #define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
<> 139:856d2700e60b 538
<> 139:856d2700e60b 539 /* Bit fields for DEVINFO AUXHFRCOCAL3 */
<> 139:856d2700e60b 540 #define _DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL3 */
<> 139:856d2700e60b 541 #define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */
<> 139:856d2700e60b 542 #define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
<> 139:856d2700e60b 543 #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
<> 139:856d2700e60b 544 #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
<> 139:856d2700e60b 545 #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
<> 139:856d2700e60b 546 #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
<> 139:856d2700e60b 547 #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
<> 139:856d2700e60b 548 #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
<> 139:856d2700e60b 549 #define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
<> 139:856d2700e60b 550 #define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
<> 139:856d2700e60b 551 #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
<> 139:856d2700e60b 552 #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
<> 139:856d2700e60b 553 #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
<> 139:856d2700e60b 554 #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
<> 139:856d2700e60b 555 #define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
<> 139:856d2700e60b 556 #define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
<> 139:856d2700e60b 557
<> 139:856d2700e60b 558 /* Bit fields for DEVINFO AUXHFRCOCAL6 */
<> 139:856d2700e60b 559 #define _DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL6 */
<> 139:856d2700e60b 560 #define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */
<> 139:856d2700e60b 561 #define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
<> 139:856d2700e60b 562 #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
<> 139:856d2700e60b 563 #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
<> 139:856d2700e60b 564 #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
<> 139:856d2700e60b 565 #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
<> 139:856d2700e60b 566 #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
<> 139:856d2700e60b 567 #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
<> 139:856d2700e60b 568 #define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
<> 139:856d2700e60b 569 #define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
<> 139:856d2700e60b 570 #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
<> 139:856d2700e60b 571 #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
<> 139:856d2700e60b 572 #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
<> 139:856d2700e60b 573 #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
<> 139:856d2700e60b 574 #define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
<> 139:856d2700e60b 575 #define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
<> 139:856d2700e60b 576
<> 139:856d2700e60b 577 /* Bit fields for DEVINFO AUXHFRCOCAL7 */
<> 139:856d2700e60b 578 #define _DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL7 */
<> 139:856d2700e60b 579 #define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */
<> 139:856d2700e60b 580 #define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
<> 139:856d2700e60b 581 #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
<> 139:856d2700e60b 582 #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
<> 139:856d2700e60b 583 #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
<> 139:856d2700e60b 584 #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
<> 139:856d2700e60b 585 #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
<> 139:856d2700e60b 586 #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
<> 139:856d2700e60b 587 #define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
<> 139:856d2700e60b 588 #define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
<> 139:856d2700e60b 589 #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
<> 139:856d2700e60b 590 #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
<> 139:856d2700e60b 591 #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
<> 139:856d2700e60b 592 #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
<> 139:856d2700e60b 593 #define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
<> 139:856d2700e60b 594 #define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
<> 139:856d2700e60b 595
<> 139:856d2700e60b 596 /* Bit fields for DEVINFO AUXHFRCOCAL8 */
<> 139:856d2700e60b 597 #define _DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL8 */
<> 139:856d2700e60b 598 #define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */
<> 139:856d2700e60b 599 #define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
<> 139:856d2700e60b 600 #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
<> 139:856d2700e60b 601 #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
<> 139:856d2700e60b 602 #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
<> 139:856d2700e60b 603 #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
<> 139:856d2700e60b 604 #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
<> 139:856d2700e60b 605 #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
<> 139:856d2700e60b 606 #define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
<> 139:856d2700e60b 607 #define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
<> 139:856d2700e60b 608 #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
<> 139:856d2700e60b 609 #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
<> 139:856d2700e60b 610 #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
<> 139:856d2700e60b 611 #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
<> 139:856d2700e60b 612 #define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
<> 139:856d2700e60b 613 #define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
<> 139:856d2700e60b 614
<> 139:856d2700e60b 615 /* Bit fields for DEVINFO AUXHFRCOCAL10 */
<> 139:856d2700e60b 616 #define _DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL10 */
<> 139:856d2700e60b 617 #define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */
<> 139:856d2700e60b 618 #define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
<> 139:856d2700e60b 619 #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
<> 139:856d2700e60b 620 #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
<> 139:856d2700e60b 621 #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
<> 139:856d2700e60b 622 #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
<> 139:856d2700e60b 623 #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
<> 139:856d2700e60b 624 #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
<> 139:856d2700e60b 625 #define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
<> 139:856d2700e60b 626 #define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
<> 139:856d2700e60b 627 #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
<> 139:856d2700e60b 628 #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
<> 139:856d2700e60b 629 #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
<> 139:856d2700e60b 630 #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
<> 139:856d2700e60b 631 #define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
<> 139:856d2700e60b 632 #define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
<> 139:856d2700e60b 633
<> 139:856d2700e60b 634 /* Bit fields for DEVINFO AUXHFRCOCAL11 */
<> 139:856d2700e60b 635 #define _DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL11 */
<> 139:856d2700e60b 636 #define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */
<> 139:856d2700e60b 637 #define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
<> 139:856d2700e60b 638 #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
<> 139:856d2700e60b 639 #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
<> 139:856d2700e60b 640 #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
<> 139:856d2700e60b 641 #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
<> 139:856d2700e60b 642 #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
<> 139:856d2700e60b 643 #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
<> 139:856d2700e60b 644 #define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
<> 139:856d2700e60b 645 #define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
<> 139:856d2700e60b 646 #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
<> 139:856d2700e60b 647 #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
<> 139:856d2700e60b 648 #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
<> 139:856d2700e60b 649 #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
<> 139:856d2700e60b 650 #define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
<> 139:856d2700e60b 651 #define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
<> 139:856d2700e60b 652
<> 139:856d2700e60b 653 /* Bit fields for DEVINFO AUXHFRCOCAL12 */
<> 139:856d2700e60b 654 #define _DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL12 */
<> 139:856d2700e60b 655 #define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */
<> 139:856d2700e60b 656 #define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
<> 139:856d2700e60b 657 #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
<> 139:856d2700e60b 658 #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
<> 139:856d2700e60b 659 #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
<> 139:856d2700e60b 660 #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
<> 139:856d2700e60b 661 #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
<> 139:856d2700e60b 662 #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
<> 139:856d2700e60b 663 #define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
<> 139:856d2700e60b 664 #define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
<> 139:856d2700e60b 665 #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
<> 139:856d2700e60b 666 #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
<> 139:856d2700e60b 667 #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
<> 139:856d2700e60b 668 #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
<> 139:856d2700e60b 669 #define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
<> 139:856d2700e60b 670 #define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
<> 139:856d2700e60b 671
<> 139:856d2700e60b 672 /* Bit fields for DEVINFO VMONCAL0 */
<> 139:856d2700e60b 673 #define _DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL0 */
<> 139:856d2700e60b 674 #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0 /**< Shift value for AVDD1V86THRESFINE */
<> 139:856d2700e60b 675 #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for AVDD1V86THRESFINE */
<> 139:856d2700e60b 676 #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for AVDD1V86THRESCOARSE */
<> 139:856d2700e60b 677 #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for AVDD1V86THRESCOARSE */
<> 139:856d2700e60b 678 #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8 /**< Shift value for AVDD2V98THRESFINE */
<> 139:856d2700e60b 679 #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for AVDD2V98THRESFINE */
<> 139:856d2700e60b 680 #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for AVDD2V98THRESCOARSE */
<> 139:856d2700e60b 681 #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for AVDD2V98THRESCOARSE */
<> 139:856d2700e60b 682 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16 /**< Shift value for ALTAVDD1V86THRESFINE */
<> 139:856d2700e60b 683 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for ALTAVDD1V86THRESFINE */
<> 139:856d2700e60b 684 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for ALTAVDD1V86THRESCOARSE */
<> 139:856d2700e60b 685 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for ALTAVDD1V86THRESCOARSE */
<> 139:856d2700e60b 686 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24 /**< Shift value for ALTAVDD2V98THRESFINE */
<> 139:856d2700e60b 687 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for ALTAVDD2V98THRESFINE */
<> 139:856d2700e60b 688 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for ALTAVDD2V98THRESCOARSE */
<> 139:856d2700e60b 689 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for ALTAVDD2V98THRESCOARSE */
<> 139:856d2700e60b 690
<> 139:856d2700e60b 691 /* Bit fields for DEVINFO VMONCAL1 */
<> 139:856d2700e60b 692 #define _DEVINFO_VMONCAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL1 */
<> 139:856d2700e60b 693 #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0 /**< Shift value for DVDD1V86THRESFINE */
<> 139:856d2700e60b 694 #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for DVDD1V86THRESFINE */
<> 139:856d2700e60b 695 #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for DVDD1V86THRESCOARSE */
<> 139:856d2700e60b 696 #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for DVDD1V86THRESCOARSE */
<> 139:856d2700e60b 697 #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8 /**< Shift value for DVDD2V98THRESFINE */
<> 139:856d2700e60b 698 #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for DVDD2V98THRESFINE */
<> 139:856d2700e60b 699 #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for DVDD2V98THRESCOARSE */
<> 139:856d2700e60b 700 #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for DVDD2V98THRESCOARSE */
<> 139:856d2700e60b 701 #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16 /**< Shift value for IO01V86THRESFINE */
<> 139:856d2700e60b 702 #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL /**< Bit mask for IO01V86THRESFINE */
<> 139:856d2700e60b 703 #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20 /**< Shift value for IO01V86THRESCOARSE */
<> 139:856d2700e60b 704 #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for IO01V86THRESCOARSE */
<> 139:856d2700e60b 705 #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24 /**< Shift value for IO02V98THRESFINE */
<> 139:856d2700e60b 706 #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL /**< Bit mask for IO02V98THRESFINE */
<> 139:856d2700e60b 707 #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28 /**< Shift value for IO02V98THRESCOARSE */
<> 139:856d2700e60b 708 #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for IO02V98THRESCOARSE */
<> 139:856d2700e60b 709
<> 139:856d2700e60b 710 /* Bit fields for DEVINFO VMONCAL2 */
<> 139:856d2700e60b 711 #define _DEVINFO_VMONCAL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL2 */
<> 139:856d2700e60b 712 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT 0 /**< Shift value for PAVDD1V86THRESFINE */
<> 139:856d2700e60b 713 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for PAVDD1V86THRESFINE */
<> 139:856d2700e60b 714 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for PAVDD1V86THRESCOARSE */
<> 139:856d2700e60b 715 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for PAVDD1V86THRESCOARSE */
<> 139:856d2700e60b 716 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT 8 /**< Shift value for PAVDD2V98THRESFINE */
<> 139:856d2700e60b 717 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for PAVDD2V98THRESFINE */
<> 139:856d2700e60b 718 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for PAVDD2V98THRESCOARSE */
<> 139:856d2700e60b 719 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for PAVDD2V98THRESCOARSE */
<> 139:856d2700e60b 720 #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT 16 /**< Shift value for FVDD1V86THRESFINE */
<> 139:856d2700e60b 721 #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for FVDD1V86THRESFINE */
<> 139:856d2700e60b 722 #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for FVDD1V86THRESCOARSE */
<> 139:856d2700e60b 723 #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for FVDD1V86THRESCOARSE */
<> 139:856d2700e60b 724 #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT 24 /**< Shift value for FVDD2V98THRESFINE */
<> 139:856d2700e60b 725 #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for FVDD2V98THRESFINE */
<> 139:856d2700e60b 726 #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for FVDD2V98THRESCOARSE */
<> 139:856d2700e60b 727 #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for FVDD2V98THRESCOARSE */
<> 139:856d2700e60b 728
<> 139:856d2700e60b 729 /* Bit fields for DEVINFO IDAC0CAL0 */
<> 139:856d2700e60b 730 #define _DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL0 */
<> 139:856d2700e60b 731 #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0 /**< Shift value for SOURCERANGE0TUNING */
<> 139:856d2700e60b 732 #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL /**< Bit mask for SOURCERANGE0TUNING */
<> 139:856d2700e60b 733 #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8 /**< Shift value for SOURCERANGE1TUNING */
<> 139:856d2700e60b 734 #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SOURCERANGE1TUNING */
<> 139:856d2700e60b 735 #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16 /**< Shift value for SOURCERANGE2TUNING */
<> 139:856d2700e60b 736 #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SOURCERANGE2TUNING */
<> 139:856d2700e60b 737 #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24 /**< Shift value for SOURCERANGE3TUNING */
<> 139:856d2700e60b 738 #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SOURCERANGE3TUNING */
<> 139:856d2700e60b 739
<> 139:856d2700e60b 740 /* Bit fields for DEVINFO IDAC0CAL1 */
<> 139:856d2700e60b 741 #define _DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL1 */
<> 139:856d2700e60b 742 #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0 /**< Shift value for SINKRANGE0TUNING */
<> 139:856d2700e60b 743 #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL /**< Bit mask for SINKRANGE0TUNING */
<> 139:856d2700e60b 744 #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8 /**< Shift value for SINKRANGE1TUNING */
<> 139:856d2700e60b 745 #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SINKRANGE1TUNING */
<> 139:856d2700e60b 746 #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16 /**< Shift value for SINKRANGE2TUNING */
<> 139:856d2700e60b 747 #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SINKRANGE2TUNING */
<> 139:856d2700e60b 748 #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24 /**< Shift value for SINKRANGE3TUNING */
<> 139:856d2700e60b 749 #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SINKRANGE3TUNING */
<> 139:856d2700e60b 750
<> 139:856d2700e60b 751 /* Bit fields for DEVINFO DCDCLNVCTRL0 */
<> 139:856d2700e60b 752 #define _DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLNVCTRL0 */
<> 139:856d2700e60b 753 #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0 /**< Shift value for 1V2LNATT0 */
<> 139:856d2700e60b 754 #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL /**< Bit mask for 1V2LNATT0 */
<> 139:856d2700e60b 755 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8 /**< Shift value for 1V8LNATT0 */
<> 139:856d2700e60b 756 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL /**< Bit mask for 1V8LNATT0 */
<> 139:856d2700e60b 757 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16 /**< Shift value for 1V8LNATT1 */
<> 139:856d2700e60b 758 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL /**< Bit mask for 1V8LNATT1 */
<> 139:856d2700e60b 759 #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24 /**< Shift value for 3V0LNATT1 */
<> 139:856d2700e60b 760 #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL /**< Bit mask for 3V0LNATT1 */
<> 139:856d2700e60b 761
<> 139:856d2700e60b 762 /* Bit fields for DEVINFO DCDCLPVCTRL0 */
<> 139:856d2700e60b 763 #define _DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL0 */
<> 139:856d2700e60b 764 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS0 */
<> 139:856d2700e60b 765 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS0 */
<> 139:856d2700e60b 766 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS0 */
<> 139:856d2700e60b 767 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS0 */
<> 139:856d2700e60b 768 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS1 */
<> 139:856d2700e60b 769 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS1 */
<> 139:856d2700e60b 770 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS1 */
<> 139:856d2700e60b 771 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS1 */
<> 139:856d2700e60b 772
<> 139:856d2700e60b 773 /* Bit fields for DEVINFO DCDCLPVCTRL1 */
<> 139:856d2700e60b 774 #define _DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL1 */
<> 139:856d2700e60b 775 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS2 */
<> 139:856d2700e60b 776 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS2 */
<> 139:856d2700e60b 777 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS2 */
<> 139:856d2700e60b 778 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS2 */
<> 139:856d2700e60b 779 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS3 */
<> 139:856d2700e60b 780 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS3 */
<> 139:856d2700e60b 781 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS3 */
<> 139:856d2700e60b 782 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS3 */
<> 139:856d2700e60b 783
<> 139:856d2700e60b 784 /* Bit fields for DEVINFO DCDCLPVCTRL2 */
<> 139:856d2700e60b 785 #define _DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL2 */
<> 139:856d2700e60b 786 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS0 */
<> 139:856d2700e60b 787 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS0 */
<> 139:856d2700e60b 788 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS0 */
<> 139:856d2700e60b 789 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS0 */
<> 139:856d2700e60b 790 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS1 */
<> 139:856d2700e60b 791 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS1 */
<> 139:856d2700e60b 792 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS1 */
<> 139:856d2700e60b 793 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS1 */
<> 139:856d2700e60b 794
<> 139:856d2700e60b 795 /* Bit fields for DEVINFO DCDCLPVCTRL3 */
<> 139:856d2700e60b 796 #define _DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL3 */
<> 139:856d2700e60b 797 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS2 */
<> 139:856d2700e60b 798 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS2 */
<> 139:856d2700e60b 799 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS2 */
<> 139:856d2700e60b 800 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS2 */
<> 139:856d2700e60b 801 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS3 */
<> 139:856d2700e60b 802 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS3 */
<> 139:856d2700e60b 803 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS3 */
<> 139:856d2700e60b 804 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS3 */
<> 139:856d2700e60b 805
<> 139:856d2700e60b 806 /* Bit fields for DEVINFO DCDCLPCMPHYSSEL0 */
<> 139:856d2700e60b 807 #define _DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL0 */
<> 139:856d2700e60b 808 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPATT0 */
<> 139:856d2700e60b 809 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPATT0 */
<> 139:856d2700e60b 810 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPATT1 */
<> 139:856d2700e60b 811 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPATT1 */
<> 139:856d2700e60b 812
<> 139:856d2700e60b 813 /* Bit fields for DEVINFO DCDCLPCMPHYSSEL1 */
<> 139:856d2700e60b 814 #define _DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL1 */
<> 139:856d2700e60b 815 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPCMPBIAS0 */
<> 139:856d2700e60b 816 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPCMPBIAS0 */
<> 139:856d2700e60b 817 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPCMPBIAS1 */
<> 139:856d2700e60b 818 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS1 */
<> 139:856d2700e60b 819 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16 /**< Shift value for LPCMPHYSSELLPCMPBIAS2 */
<> 139:856d2700e60b 820 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS2 */
<> 139:856d2700e60b 821 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24 /**< Shift value for LPCMPHYSSELLPCMPBIAS3 */
<> 139:856d2700e60b 822 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS3 */
<> 139:856d2700e60b 823
<> 139:856d2700e60b 824 /* Bit fields for DEVINFO VDAC0MAINCAL */
<> 139:856d2700e60b 825 #define _DEVINFO_VDAC0MAINCAL_MASK 0x3FFFFFFFUL /**< Mask for DEVINFO_VDAC0MAINCAL */
<> 139:856d2700e60b 826 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT 0 /**< Shift value for GAINERRTRIM1V25LN */
<> 139:856d2700e60b 827 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK 0x3FUL /**< Bit mask for GAINERRTRIM1V25LN */
<> 139:856d2700e60b 828 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_SHIFT 6 /**< Shift value for GAINERRTRIM2V5LN */
<> 139:856d2700e60b 829 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_MASK 0xFC0UL /**< Bit mask for GAINERRTRIM2V5LN */
<> 139:856d2700e60b 830 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_SHIFT 12 /**< Shift value for GAINERRTRIM1V25 */
<> 139:856d2700e60b 831 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_MASK 0x3F000UL /**< Bit mask for GAINERRTRIM1V25 */
<> 139:856d2700e60b 832 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_SHIFT 18 /**< Shift value for GAINERRTRIM2V5 */
<> 139:856d2700e60b 833 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_MASK 0xFC0000UL /**< Bit mask for GAINERRTRIM2V5 */
<> 139:856d2700e60b 834 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_SHIFT 24 /**< Shift value for GAINERRTRIMVDDANAEXTPIN */
<> 139:856d2700e60b 835 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_MASK 0x3F000000UL /**< Bit mask for GAINERRTRIMVDDANAEXTPIN */
<> 139:856d2700e60b 836
<> 139:856d2700e60b 837 /* Bit fields for DEVINFO VDAC0ALTCAL */
<> 139:856d2700e60b 838 #define _DEVINFO_VDAC0ALTCAL_MASK 0x3FFFFFFFUL /**< Mask for DEVINFO_VDAC0ALTCAL */
<> 139:856d2700e60b 839 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_SHIFT 0 /**< Shift value for GAINERRTRIM1V25LNALT */
<> 139:856d2700e60b 840 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_MASK 0x3FUL /**< Bit mask for GAINERRTRIM1V25LNALT */
<> 139:856d2700e60b 841 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_SHIFT 6 /**< Shift value for GAINERRTRIM2V5LNALT */
<> 139:856d2700e60b 842 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_MASK 0xFC0UL /**< Bit mask for GAINERRTRIM2V5LNALT */
<> 139:856d2700e60b 843 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_SHIFT 12 /**< Shift value for GAINERRTRIM1V25ALT */
<> 139:856d2700e60b 844 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_MASK 0x3F000UL /**< Bit mask for GAINERRTRIM1V25ALT */
<> 139:856d2700e60b 845 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_SHIFT 18 /**< Shift value for GAINERRTRIM2V5ALT */
<> 139:856d2700e60b 846 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_MASK 0xFC0000UL /**< Bit mask for GAINERRTRIM2V5ALT */
<> 139:856d2700e60b 847 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_SHIFT 24 /**< Shift value for GAINERRTRIMVDDANAEXTPINALT */
<> 139:856d2700e60b 848 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_MASK 0x3F000000UL /**< Bit mask for GAINERRTRIMVDDANAEXTPINALT */
<> 139:856d2700e60b 849
<> 139:856d2700e60b 850 /* Bit fields for DEVINFO VDAC0CH1CAL */
<> 139:856d2700e60b 851 #define _DEVINFO_VDAC0CH1CAL_MASK 0x00000FF7UL /**< Mask for DEVINFO_VDAC0CH1CAL */
<> 139:856d2700e60b 852 #define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT 0 /**< Shift value for OFFSETTRIM */
<> 139:856d2700e60b 853 #define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK 0x7UL /**< Bit mask for OFFSETTRIM */
<> 139:856d2700e60b 854 #define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_SHIFT 4 /**< Shift value for GAINERRTRIMCH1A */
<> 139:856d2700e60b 855 #define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_MASK 0xF0UL /**< Bit mask for GAINERRTRIMCH1A */
<> 139:856d2700e60b 856 #define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_SHIFT 8 /**< Shift value for GAINERRTRIMCH1B */
<> 139:856d2700e60b 857 #define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_MASK 0xF00UL /**< Bit mask for GAINERRTRIMCH1B */
<> 139:856d2700e60b 858
<> 139:856d2700e60b 859 /* Bit fields for DEVINFO OPA0CAL0 */
<> 139:856d2700e60b 860 #define _DEVINFO_OPA0CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL0 */
<> 139:856d2700e60b 861 #define _DEVINFO_OPA0CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 862 #define _DEVINFO_OPA0CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 863 #define _DEVINFO_OPA0CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 864 #define _DEVINFO_OPA0CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 865 #define _DEVINFO_OPA0CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 866 #define _DEVINFO_OPA0CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 867 #define _DEVINFO_OPA0CAL0_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 868 #define _DEVINFO_OPA0CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 869 #define _DEVINFO_OPA0CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 870 #define _DEVINFO_OPA0CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 871 #define _DEVINFO_OPA0CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 872 #define _DEVINFO_OPA0CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 873 #define _DEVINFO_OPA0CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 874 #define _DEVINFO_OPA0CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 875
<> 139:856d2700e60b 876 /* Bit fields for DEVINFO OPA0CAL1 */
<> 139:856d2700e60b 877 #define _DEVINFO_OPA0CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL1 */
<> 139:856d2700e60b 878 #define _DEVINFO_OPA0CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 879 #define _DEVINFO_OPA0CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 880 #define _DEVINFO_OPA0CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 881 #define _DEVINFO_OPA0CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 882 #define _DEVINFO_OPA0CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 883 #define _DEVINFO_OPA0CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 884 #define _DEVINFO_OPA0CAL1_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 885 #define _DEVINFO_OPA0CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 886 #define _DEVINFO_OPA0CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 887 #define _DEVINFO_OPA0CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 888 #define _DEVINFO_OPA0CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 889 #define _DEVINFO_OPA0CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 890 #define _DEVINFO_OPA0CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 891 #define _DEVINFO_OPA0CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 892
<> 139:856d2700e60b 893 /* Bit fields for DEVINFO OPA0CAL2 */
<> 139:856d2700e60b 894 #define _DEVINFO_OPA0CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL2 */
<> 139:856d2700e60b 895 #define _DEVINFO_OPA0CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 896 #define _DEVINFO_OPA0CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 897 #define _DEVINFO_OPA0CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 898 #define _DEVINFO_OPA0CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 899 #define _DEVINFO_OPA0CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 900 #define _DEVINFO_OPA0CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 901 #define _DEVINFO_OPA0CAL2_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 902 #define _DEVINFO_OPA0CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 903 #define _DEVINFO_OPA0CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 904 #define _DEVINFO_OPA0CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 905 #define _DEVINFO_OPA0CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 906 #define _DEVINFO_OPA0CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 907 #define _DEVINFO_OPA0CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 908 #define _DEVINFO_OPA0CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 909
<> 139:856d2700e60b 910 /* Bit fields for DEVINFO OPA0CAL3 */
<> 139:856d2700e60b 911 #define _DEVINFO_OPA0CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL3 */
<> 139:856d2700e60b 912 #define _DEVINFO_OPA0CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 913 #define _DEVINFO_OPA0CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 914 #define _DEVINFO_OPA0CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 915 #define _DEVINFO_OPA0CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 916 #define _DEVINFO_OPA0CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 917 #define _DEVINFO_OPA0CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 918 #define _DEVINFO_OPA0CAL3_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 919 #define _DEVINFO_OPA0CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 920 #define _DEVINFO_OPA0CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 921 #define _DEVINFO_OPA0CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 922 #define _DEVINFO_OPA0CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 923 #define _DEVINFO_OPA0CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 924 #define _DEVINFO_OPA0CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 925 #define _DEVINFO_OPA0CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 926
<> 139:856d2700e60b 927 /* Bit fields for DEVINFO OPA1CAL0 */
<> 139:856d2700e60b 928 #define _DEVINFO_OPA1CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL0 */
<> 139:856d2700e60b 929 #define _DEVINFO_OPA1CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 930 #define _DEVINFO_OPA1CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 931 #define _DEVINFO_OPA1CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 932 #define _DEVINFO_OPA1CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 933 #define _DEVINFO_OPA1CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 934 #define _DEVINFO_OPA1CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 935 #define _DEVINFO_OPA1CAL0_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 936 #define _DEVINFO_OPA1CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 937 #define _DEVINFO_OPA1CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 938 #define _DEVINFO_OPA1CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 939 #define _DEVINFO_OPA1CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 940 #define _DEVINFO_OPA1CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 941 #define _DEVINFO_OPA1CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 942 #define _DEVINFO_OPA1CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 943
<> 139:856d2700e60b 944 /* Bit fields for DEVINFO OPA1CAL1 */
<> 139:856d2700e60b 945 #define _DEVINFO_OPA1CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL1 */
<> 139:856d2700e60b 946 #define _DEVINFO_OPA1CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 947 #define _DEVINFO_OPA1CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 948 #define _DEVINFO_OPA1CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 949 #define _DEVINFO_OPA1CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 950 #define _DEVINFO_OPA1CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 951 #define _DEVINFO_OPA1CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 952 #define _DEVINFO_OPA1CAL1_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 953 #define _DEVINFO_OPA1CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 954 #define _DEVINFO_OPA1CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 955 #define _DEVINFO_OPA1CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 956 #define _DEVINFO_OPA1CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 957 #define _DEVINFO_OPA1CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 958 #define _DEVINFO_OPA1CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 959 #define _DEVINFO_OPA1CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 960
<> 139:856d2700e60b 961 /* Bit fields for DEVINFO OPA1CAL2 */
<> 139:856d2700e60b 962 #define _DEVINFO_OPA1CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL2 */
<> 139:856d2700e60b 963 #define _DEVINFO_OPA1CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 964 #define _DEVINFO_OPA1CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 965 #define _DEVINFO_OPA1CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 966 #define _DEVINFO_OPA1CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 967 #define _DEVINFO_OPA1CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 968 #define _DEVINFO_OPA1CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 969 #define _DEVINFO_OPA1CAL2_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 970 #define _DEVINFO_OPA1CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 971 #define _DEVINFO_OPA1CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 972 #define _DEVINFO_OPA1CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 973 #define _DEVINFO_OPA1CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 974 #define _DEVINFO_OPA1CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 975 #define _DEVINFO_OPA1CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 976 #define _DEVINFO_OPA1CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 977
<> 139:856d2700e60b 978 /* Bit fields for DEVINFO OPA1CAL3 */
<> 139:856d2700e60b 979 #define _DEVINFO_OPA1CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL3 */
<> 139:856d2700e60b 980 #define _DEVINFO_OPA1CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 981 #define _DEVINFO_OPA1CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 982 #define _DEVINFO_OPA1CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 983 #define _DEVINFO_OPA1CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 984 #define _DEVINFO_OPA1CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 985 #define _DEVINFO_OPA1CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 986 #define _DEVINFO_OPA1CAL3_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 987 #define _DEVINFO_OPA1CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 988 #define _DEVINFO_OPA1CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 989 #define _DEVINFO_OPA1CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 990 #define _DEVINFO_OPA1CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 991 #define _DEVINFO_OPA1CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 992 #define _DEVINFO_OPA1CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 993 #define _DEVINFO_OPA1CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 994
<> 139:856d2700e60b 995 /* Bit fields for DEVINFO OPA2CAL0 */
<> 139:856d2700e60b 996 #define _DEVINFO_OPA2CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL0 */
<> 139:856d2700e60b 997 #define _DEVINFO_OPA2CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 998 #define _DEVINFO_OPA2CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 999 #define _DEVINFO_OPA2CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 1000 #define _DEVINFO_OPA2CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 1001 #define _DEVINFO_OPA2CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 1002 #define _DEVINFO_OPA2CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 1003 #define _DEVINFO_OPA2CAL0_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 1004 #define _DEVINFO_OPA2CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 1005 #define _DEVINFO_OPA2CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 1006 #define _DEVINFO_OPA2CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 1007 #define _DEVINFO_OPA2CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 1008 #define _DEVINFO_OPA2CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 1009 #define _DEVINFO_OPA2CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 1010 #define _DEVINFO_OPA2CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 1011
<> 139:856d2700e60b 1012 /* Bit fields for DEVINFO OPA2CAL1 */
<> 139:856d2700e60b 1013 #define _DEVINFO_OPA2CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL1 */
<> 139:856d2700e60b 1014 #define _DEVINFO_OPA2CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 1015 #define _DEVINFO_OPA2CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 1016 #define _DEVINFO_OPA2CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 1017 #define _DEVINFO_OPA2CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 1018 #define _DEVINFO_OPA2CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 1019 #define _DEVINFO_OPA2CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 1020 #define _DEVINFO_OPA2CAL1_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 1021 #define _DEVINFO_OPA2CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 1022 #define _DEVINFO_OPA2CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 1023 #define _DEVINFO_OPA2CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 1024 #define _DEVINFO_OPA2CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 1025 #define _DEVINFO_OPA2CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 1026 #define _DEVINFO_OPA2CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 1027 #define _DEVINFO_OPA2CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 1028
<> 139:856d2700e60b 1029 /* Bit fields for DEVINFO OPA2CAL2 */
<> 139:856d2700e60b 1030 #define _DEVINFO_OPA2CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL2 */
<> 139:856d2700e60b 1031 #define _DEVINFO_OPA2CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 1032 #define _DEVINFO_OPA2CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 1033 #define _DEVINFO_OPA2CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 1034 #define _DEVINFO_OPA2CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 1035 #define _DEVINFO_OPA2CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 1036 #define _DEVINFO_OPA2CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 1037 #define _DEVINFO_OPA2CAL2_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 1038 #define _DEVINFO_OPA2CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 1039 #define _DEVINFO_OPA2CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 1040 #define _DEVINFO_OPA2CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 1041 #define _DEVINFO_OPA2CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 1042 #define _DEVINFO_OPA2CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 1043 #define _DEVINFO_OPA2CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 1044 #define _DEVINFO_OPA2CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 1045
<> 139:856d2700e60b 1046 /* Bit fields for DEVINFO OPA2CAL3 */
<> 139:856d2700e60b 1047 #define _DEVINFO_OPA2CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL3 */
<> 139:856d2700e60b 1048 #define _DEVINFO_OPA2CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 1049 #define _DEVINFO_OPA2CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 1050 #define _DEVINFO_OPA2CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 1051 #define _DEVINFO_OPA2CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 1052 #define _DEVINFO_OPA2CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 1053 #define _DEVINFO_OPA2CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 1054 #define _DEVINFO_OPA2CAL3_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 1055 #define _DEVINFO_OPA2CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 1056 #define _DEVINFO_OPA2CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 1057 #define _DEVINFO_OPA2CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 1058 #define _DEVINFO_OPA2CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 1059 #define _DEVINFO_OPA2CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 1060 #define _DEVINFO_OPA2CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 1061 #define _DEVINFO_OPA2CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 1062
<> 139:856d2700e60b 1063 /* Bit fields for DEVINFO CSENGAINCAL */
<> 139:856d2700e60b 1064 #define _DEVINFO_CSENGAINCAL_MASK 0x000000FFUL /**< Mask for DEVINFO_CSENGAINCAL */
<> 139:856d2700e60b 1065 #define _DEVINFO_CSENGAINCAL_GAINCAL_SHIFT 0 /**< Shift value for GAINCAL */
<> 139:856d2700e60b 1066 #define _DEVINFO_CSENGAINCAL_GAINCAL_MASK 0xFFUL /**< Bit mask for GAINCAL */
<> 139:856d2700e60b 1067
<> 139:856d2700e60b 1068 /* Bit fields for DEVINFO OPA0CAL4 */
<> 139:856d2700e60b 1069 #define _DEVINFO_OPA0CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL4 */
<> 139:856d2700e60b 1070 #define _DEVINFO_OPA0CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 1071 #define _DEVINFO_OPA0CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 1072 #define _DEVINFO_OPA0CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 1073 #define _DEVINFO_OPA0CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 1074 #define _DEVINFO_OPA0CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 1075 #define _DEVINFO_OPA0CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 1076 #define _DEVINFO_OPA0CAL4_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 1077 #define _DEVINFO_OPA0CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 1078 #define _DEVINFO_OPA0CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 1079 #define _DEVINFO_OPA0CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 1080 #define _DEVINFO_OPA0CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 1081 #define _DEVINFO_OPA0CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 1082 #define _DEVINFO_OPA0CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 1083 #define _DEVINFO_OPA0CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 1084
<> 139:856d2700e60b 1085 /* Bit fields for DEVINFO OPA0CAL5 */
<> 139:856d2700e60b 1086 #define _DEVINFO_OPA0CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL5 */
<> 139:856d2700e60b 1087 #define _DEVINFO_OPA0CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 1088 #define _DEVINFO_OPA0CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 1089 #define _DEVINFO_OPA0CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 1090 #define _DEVINFO_OPA0CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 1091 #define _DEVINFO_OPA0CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 1092 #define _DEVINFO_OPA0CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 1093 #define _DEVINFO_OPA0CAL5_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 1094 #define _DEVINFO_OPA0CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 1095 #define _DEVINFO_OPA0CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 1096 #define _DEVINFO_OPA0CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 1097 #define _DEVINFO_OPA0CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 1098 #define _DEVINFO_OPA0CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 1099 #define _DEVINFO_OPA0CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 1100 #define _DEVINFO_OPA0CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 1101
<> 139:856d2700e60b 1102 /* Bit fields for DEVINFO OPA0CAL6 */
<> 139:856d2700e60b 1103 #define _DEVINFO_OPA0CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL6 */
<> 139:856d2700e60b 1104 #define _DEVINFO_OPA0CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 1105 #define _DEVINFO_OPA0CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 1106 #define _DEVINFO_OPA0CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 1107 #define _DEVINFO_OPA0CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 1108 #define _DEVINFO_OPA0CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 1109 #define _DEVINFO_OPA0CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 1110 #define _DEVINFO_OPA0CAL6_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 1111 #define _DEVINFO_OPA0CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 1112 #define _DEVINFO_OPA0CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 1113 #define _DEVINFO_OPA0CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 1114 #define _DEVINFO_OPA0CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 1115 #define _DEVINFO_OPA0CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 1116 #define _DEVINFO_OPA0CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 1117 #define _DEVINFO_OPA0CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 1118
<> 139:856d2700e60b 1119 /* Bit fields for DEVINFO OPA0CAL7 */
<> 139:856d2700e60b 1120 #define _DEVINFO_OPA0CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL7 */
<> 139:856d2700e60b 1121 #define _DEVINFO_OPA0CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 1122 #define _DEVINFO_OPA0CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 1123 #define _DEVINFO_OPA0CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 1124 #define _DEVINFO_OPA0CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 1125 #define _DEVINFO_OPA0CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 1126 #define _DEVINFO_OPA0CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 1127 #define _DEVINFO_OPA0CAL7_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 1128 #define _DEVINFO_OPA0CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 1129 #define _DEVINFO_OPA0CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 1130 #define _DEVINFO_OPA0CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 1131 #define _DEVINFO_OPA0CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 1132 #define _DEVINFO_OPA0CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 1133 #define _DEVINFO_OPA0CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 1134 #define _DEVINFO_OPA0CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 1135
<> 139:856d2700e60b 1136 /* Bit fields for DEVINFO OPA1CAL4 */
<> 139:856d2700e60b 1137 #define _DEVINFO_OPA1CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL4 */
<> 139:856d2700e60b 1138 #define _DEVINFO_OPA1CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 1139 #define _DEVINFO_OPA1CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 1140 #define _DEVINFO_OPA1CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 1141 #define _DEVINFO_OPA1CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 1142 #define _DEVINFO_OPA1CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 1143 #define _DEVINFO_OPA1CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 1144 #define _DEVINFO_OPA1CAL4_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 1145 #define _DEVINFO_OPA1CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 1146 #define _DEVINFO_OPA1CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 1147 #define _DEVINFO_OPA1CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 1148 #define _DEVINFO_OPA1CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 1149 #define _DEVINFO_OPA1CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 1150 #define _DEVINFO_OPA1CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 1151 #define _DEVINFO_OPA1CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 1152
<> 139:856d2700e60b 1153 /* Bit fields for DEVINFO OPA1CAL5 */
<> 139:856d2700e60b 1154 #define _DEVINFO_OPA1CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL5 */
<> 139:856d2700e60b 1155 #define _DEVINFO_OPA1CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 1156 #define _DEVINFO_OPA1CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 1157 #define _DEVINFO_OPA1CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 1158 #define _DEVINFO_OPA1CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 1159 #define _DEVINFO_OPA1CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 1160 #define _DEVINFO_OPA1CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 1161 #define _DEVINFO_OPA1CAL5_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 1162 #define _DEVINFO_OPA1CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 1163 #define _DEVINFO_OPA1CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 1164 #define _DEVINFO_OPA1CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 1165 #define _DEVINFO_OPA1CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 1166 #define _DEVINFO_OPA1CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 1167 #define _DEVINFO_OPA1CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 1168 #define _DEVINFO_OPA1CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 1169
<> 139:856d2700e60b 1170 /* Bit fields for DEVINFO OPA1CAL6 */
<> 139:856d2700e60b 1171 #define _DEVINFO_OPA1CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL6 */
<> 139:856d2700e60b 1172 #define _DEVINFO_OPA1CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 1173 #define _DEVINFO_OPA1CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 1174 #define _DEVINFO_OPA1CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 1175 #define _DEVINFO_OPA1CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 1176 #define _DEVINFO_OPA1CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 1177 #define _DEVINFO_OPA1CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 1178 #define _DEVINFO_OPA1CAL6_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 1179 #define _DEVINFO_OPA1CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 1180 #define _DEVINFO_OPA1CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 1181 #define _DEVINFO_OPA1CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 1182 #define _DEVINFO_OPA1CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 1183 #define _DEVINFO_OPA1CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 1184 #define _DEVINFO_OPA1CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 1185 #define _DEVINFO_OPA1CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 1186
<> 139:856d2700e60b 1187 /* Bit fields for DEVINFO OPA1CAL7 */
<> 139:856d2700e60b 1188 #define _DEVINFO_OPA1CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL7 */
<> 139:856d2700e60b 1189 #define _DEVINFO_OPA1CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 1190 #define _DEVINFO_OPA1CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 1191 #define _DEVINFO_OPA1CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 1192 #define _DEVINFO_OPA1CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 1193 #define _DEVINFO_OPA1CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 1194 #define _DEVINFO_OPA1CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 1195 #define _DEVINFO_OPA1CAL7_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 1196 #define _DEVINFO_OPA1CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 1197 #define _DEVINFO_OPA1CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 1198 #define _DEVINFO_OPA1CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 1199 #define _DEVINFO_OPA1CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 1200 #define _DEVINFO_OPA1CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 1201 #define _DEVINFO_OPA1CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 1202 #define _DEVINFO_OPA1CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 1203
<> 139:856d2700e60b 1204 /* Bit fields for DEVINFO OPA2CAL4 */
<> 139:856d2700e60b 1205 #define _DEVINFO_OPA2CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL4 */
<> 139:856d2700e60b 1206 #define _DEVINFO_OPA2CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 1207 #define _DEVINFO_OPA2CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 1208 #define _DEVINFO_OPA2CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 1209 #define _DEVINFO_OPA2CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 1210 #define _DEVINFO_OPA2CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 1211 #define _DEVINFO_OPA2CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 1212 #define _DEVINFO_OPA2CAL4_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 1213 #define _DEVINFO_OPA2CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 1214 #define _DEVINFO_OPA2CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 1215 #define _DEVINFO_OPA2CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 1216 #define _DEVINFO_OPA2CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 1217 #define _DEVINFO_OPA2CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 1218 #define _DEVINFO_OPA2CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 1219 #define _DEVINFO_OPA2CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 1220
<> 139:856d2700e60b 1221 /* Bit fields for DEVINFO OPA2CAL5 */
<> 139:856d2700e60b 1222 #define _DEVINFO_OPA2CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL5 */
<> 139:856d2700e60b 1223 #define _DEVINFO_OPA2CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 1224 #define _DEVINFO_OPA2CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 1225 #define _DEVINFO_OPA2CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 1226 #define _DEVINFO_OPA2CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 1227 #define _DEVINFO_OPA2CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 1228 #define _DEVINFO_OPA2CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 1229 #define _DEVINFO_OPA2CAL5_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 1230 #define _DEVINFO_OPA2CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 1231 #define _DEVINFO_OPA2CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 1232 #define _DEVINFO_OPA2CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 1233 #define _DEVINFO_OPA2CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 1234 #define _DEVINFO_OPA2CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 1235 #define _DEVINFO_OPA2CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 1236 #define _DEVINFO_OPA2CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 1237
<> 139:856d2700e60b 1238 /* Bit fields for DEVINFO OPA2CAL6 */
<> 139:856d2700e60b 1239 #define _DEVINFO_OPA2CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL6 */
<> 139:856d2700e60b 1240 #define _DEVINFO_OPA2CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 1241 #define _DEVINFO_OPA2CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 1242 #define _DEVINFO_OPA2CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 1243 #define _DEVINFO_OPA2CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 1244 #define _DEVINFO_OPA2CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 1245 #define _DEVINFO_OPA2CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 1246 #define _DEVINFO_OPA2CAL6_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 1247 #define _DEVINFO_OPA2CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 1248 #define _DEVINFO_OPA2CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 1249 #define _DEVINFO_OPA2CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 1250 #define _DEVINFO_OPA2CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 1251 #define _DEVINFO_OPA2CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 1252 #define _DEVINFO_OPA2CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 1253 #define _DEVINFO_OPA2CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 1254
<> 139:856d2700e60b 1255 /* Bit fields for DEVINFO OPA2CAL7 */
<> 139:856d2700e60b 1256 #define _DEVINFO_OPA2CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL7 */
<> 139:856d2700e60b 1257 #define _DEVINFO_OPA2CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */
<> 139:856d2700e60b 1258 #define _DEVINFO_OPA2CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */
<> 139:856d2700e60b 1259 #define _DEVINFO_OPA2CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */
<> 139:856d2700e60b 1260 #define _DEVINFO_OPA2CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */
<> 139:856d2700e60b 1261 #define _DEVINFO_OPA2CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */
<> 139:856d2700e60b 1262 #define _DEVINFO_OPA2CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */
<> 139:856d2700e60b 1263 #define _DEVINFO_OPA2CAL7_GM_SHIFT 13 /**< Shift value for GM */
<> 139:856d2700e60b 1264 #define _DEVINFO_OPA2CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */
<> 139:856d2700e60b 1265 #define _DEVINFO_OPA2CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */
<> 139:856d2700e60b 1266 #define _DEVINFO_OPA2CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */
<> 139:856d2700e60b 1267 #define _DEVINFO_OPA2CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */
<> 139:856d2700e60b 1268 #define _DEVINFO_OPA2CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */
<> 139:856d2700e60b 1269 #define _DEVINFO_OPA2CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */
<> 139:856d2700e60b 1270 #define _DEVINFO_OPA2CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */
<> 139:856d2700e60b 1271
<> 139:856d2700e60b 1272 /** @} End of group EFM32PG12B_DEVINFO */
<> 139:856d2700e60b 1273 /** @} End of group Parts */
<> 139:856d2700e60b 1274