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TARGET_EFM32PG12_STK3402/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/efm32pg12b500f512gl125.h@140:97feb9bacc10, 2017-04-12 (annotated)
- Committer:
- <>
- Date:
- Wed Apr 12 16:07:08 2017 +0100
- Revision:
- 140:97feb9bacc10
- Parent:
- 139:856d2700e60b
Release 140 of the mbed library
Ports for Upcoming Targets
3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841
3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992
Fixes and Changes
3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951
4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021
3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979
3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the https://github.com/ARMmbed/mbed-os/pull/3990
4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003
4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012
4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020
4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065
4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014
4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030
4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109
3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 139:856d2700e60b | 1 | /**************************************************************************//** |
<> | 139:856d2700e60b | 2 | * @file efm32pg12b500f512gl125.h |
<> | 139:856d2700e60b | 3 | * @brief CMSIS Cortex-M Peripheral Access Layer Header File |
<> | 139:856d2700e60b | 4 | * for EFM32PG12B500F512GL125 |
<> | 139:856d2700e60b | 5 | * @version 5.1.2 |
<> | 139:856d2700e60b | 6 | ****************************************************************************** |
<> | 139:856d2700e60b | 7 | * @section License |
<> | 139:856d2700e60b | 8 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
<> | 139:856d2700e60b | 9 | ****************************************************************************** |
<> | 139:856d2700e60b | 10 | * |
<> | 139:856d2700e60b | 11 | * Permission is granted to anyone to use this software for any purpose, |
<> | 139:856d2700e60b | 12 | * including commercial applications, and to alter it and redistribute it |
<> | 139:856d2700e60b | 13 | * freely, subject to the following restrictions: |
<> | 139:856d2700e60b | 14 | * |
<> | 139:856d2700e60b | 15 | * 1. The origin of this software must not be misrepresented; you must not |
<> | 139:856d2700e60b | 16 | * claim that you wrote the original software.@n |
<> | 139:856d2700e60b | 17 | * 2. Altered source versions must be plainly marked as such, and must not be |
<> | 139:856d2700e60b | 18 | * misrepresented as being the original software.@n |
<> | 139:856d2700e60b | 19 | * 3. This notice may not be removed or altered from any source distribution. |
<> | 139:856d2700e60b | 20 | * |
<> | 139:856d2700e60b | 21 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
<> | 139:856d2700e60b | 22 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
<> | 139:856d2700e60b | 23 | * providing the Software "AS IS", with no express or implied warranties of any |
<> | 139:856d2700e60b | 24 | * kind, including, but not limited to, any implied warranties of |
<> | 139:856d2700e60b | 25 | * merchantability or fitness for any particular purpose or warranties against |
<> | 139:856d2700e60b | 26 | * infringement of any proprietary rights of a third party. |
<> | 139:856d2700e60b | 27 | * |
<> | 139:856d2700e60b | 28 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
<> | 139:856d2700e60b | 29 | * incidental, or special damages, or any other relief, or for any claim by |
<> | 139:856d2700e60b | 30 | * any third party, arising from your use of this Software. |
<> | 139:856d2700e60b | 31 | * |
<> | 139:856d2700e60b | 32 | *****************************************************************************/ |
<> | 139:856d2700e60b | 33 | |
<> | 139:856d2700e60b | 34 | #ifndef EFM32PG12B500F512GL125_H |
<> | 139:856d2700e60b | 35 | #define EFM32PG12B500F512GL125_H |
<> | 139:856d2700e60b | 36 | |
<> | 139:856d2700e60b | 37 | #ifdef __cplusplus |
<> | 139:856d2700e60b | 38 | extern "C" { |
<> | 139:856d2700e60b | 39 | #endif |
<> | 139:856d2700e60b | 40 | |
<> | 139:856d2700e60b | 41 | /**************************************************************************//** |
<> | 139:856d2700e60b | 42 | * @addtogroup Parts |
<> | 139:856d2700e60b | 43 | * @{ |
<> | 139:856d2700e60b | 44 | *****************************************************************************/ |
<> | 139:856d2700e60b | 45 | |
<> | 139:856d2700e60b | 46 | /**************************************************************************//** |
<> | 139:856d2700e60b | 47 | * @defgroup EFM32PG12B500F512GL125 EFM32PG12B500F512GL125 |
<> | 139:856d2700e60b | 48 | * @{ |
<> | 139:856d2700e60b | 49 | *****************************************************************************/ |
<> | 139:856d2700e60b | 50 | |
<> | 139:856d2700e60b | 51 | /** Interrupt Number Definition */ |
<> | 139:856d2700e60b | 52 | typedef enum IRQn |
<> | 139:856d2700e60b | 53 | { |
<> | 139:856d2700e60b | 54 | /****** Cortex-M4 Processor Exceptions Numbers ********************************************/ |
<> | 139:856d2700e60b | 55 | NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ |
<> | 139:856d2700e60b | 56 | HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ |
<> | 139:856d2700e60b | 57 | MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ |
<> | 139:856d2700e60b | 58 | BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ |
<> | 139:856d2700e60b | 59 | UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ |
<> | 139:856d2700e60b | 60 | SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ |
<> | 139:856d2700e60b | 61 | DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ |
<> | 139:856d2700e60b | 62 | PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ |
<> | 139:856d2700e60b | 63 | SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ |
<> | 139:856d2700e60b | 64 | |
<> | 139:856d2700e60b | 65 | /****** EFM32PG12B Peripheral Interrupt Numbers ********************************************/ |
<> | 139:856d2700e60b | 66 | |
<> | 139:856d2700e60b | 67 | EMU_IRQn = 0, /*!< 0 EFM32 EMU Interrupt */ |
<> | 139:856d2700e60b | 68 | WDOG0_IRQn = 2, /*!< 2 EFM32 WDOG0 Interrupt */ |
<> | 139:856d2700e60b | 69 | WDOG1_IRQn = 3, /*!< 3 EFM32 WDOG1 Interrupt */ |
<> | 139:856d2700e60b | 70 | LDMA_IRQn = 9, /*!< 9 EFM32 LDMA Interrupt */ |
<> | 139:856d2700e60b | 71 | GPIO_EVEN_IRQn = 10, /*!< 10 EFM32 GPIO_EVEN Interrupt */ |
<> | 139:856d2700e60b | 72 | TIMER0_IRQn = 11, /*!< 11 EFM32 TIMER0 Interrupt */ |
<> | 139:856d2700e60b | 73 | USART0_RX_IRQn = 12, /*!< 12 EFM32 USART0_RX Interrupt */ |
<> | 139:856d2700e60b | 74 | USART0_TX_IRQn = 13, /*!< 13 EFM32 USART0_TX Interrupt */ |
<> | 139:856d2700e60b | 75 | ACMP0_IRQn = 14, /*!< 14 EFM32 ACMP0 Interrupt */ |
<> | 139:856d2700e60b | 76 | ADC0_IRQn = 15, /*!< 15 EFM32 ADC0 Interrupt */ |
<> | 139:856d2700e60b | 77 | IDAC0_IRQn = 16, /*!< 16 EFM32 IDAC0 Interrupt */ |
<> | 139:856d2700e60b | 78 | I2C0_IRQn = 17, /*!< 17 EFM32 I2C0 Interrupt */ |
<> | 139:856d2700e60b | 79 | GPIO_ODD_IRQn = 18, /*!< 18 EFM32 GPIO_ODD Interrupt */ |
<> | 139:856d2700e60b | 80 | TIMER1_IRQn = 19, /*!< 19 EFM32 TIMER1 Interrupt */ |
<> | 139:856d2700e60b | 81 | USART1_RX_IRQn = 20, /*!< 20 EFM32 USART1_RX Interrupt */ |
<> | 139:856d2700e60b | 82 | USART1_TX_IRQn = 21, /*!< 21 EFM32 USART1_TX Interrupt */ |
<> | 139:856d2700e60b | 83 | LEUART0_IRQn = 22, /*!< 22 EFM32 LEUART0 Interrupt */ |
<> | 139:856d2700e60b | 84 | PCNT0_IRQn = 23, /*!< 23 EFM32 PCNT0 Interrupt */ |
<> | 139:856d2700e60b | 85 | CMU_IRQn = 24, /*!< 24 EFM32 CMU Interrupt */ |
<> | 139:856d2700e60b | 86 | MSC_IRQn = 25, /*!< 25 EFM32 MSC Interrupt */ |
<> | 139:856d2700e60b | 87 | CRYPTO0_IRQn = 26, /*!< 26 EFM32 CRYPTO0 Interrupt */ |
<> | 139:856d2700e60b | 88 | LETIMER0_IRQn = 27, /*!< 27 EFM32 LETIMER0 Interrupt */ |
<> | 139:856d2700e60b | 89 | RTCC_IRQn = 30, /*!< 30 EFM32 RTCC Interrupt */ |
<> | 139:856d2700e60b | 90 | CRYOTIMER_IRQn = 32, /*!< 32 EFM32 CRYOTIMER Interrupt */ |
<> | 139:856d2700e60b | 91 | FPUEH_IRQn = 34, /*!< 34 EFM32 FPUEH Interrupt */ |
<> | 139:856d2700e60b | 92 | SMU_IRQn = 35, /*!< 35 EFM32 SMU Interrupt */ |
<> | 139:856d2700e60b | 93 | WTIMER0_IRQn = 36, /*!< 36 EFM32 WTIMER0 Interrupt */ |
<> | 139:856d2700e60b | 94 | WTIMER1_IRQn = 37, /*!< 37 EFM32 WTIMER1 Interrupt */ |
<> | 139:856d2700e60b | 95 | PCNT1_IRQn = 38, /*!< 38 EFM32 PCNT1 Interrupt */ |
<> | 139:856d2700e60b | 96 | PCNT2_IRQn = 39, /*!< 39 EFM32 PCNT2 Interrupt */ |
<> | 139:856d2700e60b | 97 | USART2_RX_IRQn = 40, /*!< 40 EFM32 USART2_RX Interrupt */ |
<> | 139:856d2700e60b | 98 | USART2_TX_IRQn = 41, /*!< 41 EFM32 USART2_TX Interrupt */ |
<> | 139:856d2700e60b | 99 | I2C1_IRQn = 42, /*!< 42 EFM32 I2C1 Interrupt */ |
<> | 139:856d2700e60b | 100 | USART3_RX_IRQn = 43, /*!< 43 EFM32 USART3_RX Interrupt */ |
<> | 139:856d2700e60b | 101 | USART3_TX_IRQn = 44, /*!< 44 EFM32 USART3_TX Interrupt */ |
<> | 139:856d2700e60b | 102 | VDAC0_IRQn = 45, /*!< 45 EFM32 VDAC0 Interrupt */ |
<> | 139:856d2700e60b | 103 | CSEN_IRQn = 46, /*!< 46 EFM32 CSEN Interrupt */ |
<> | 139:856d2700e60b | 104 | LESENSE_IRQn = 47, /*!< 47 EFM32 LESENSE Interrupt */ |
<> | 139:856d2700e60b | 105 | CRYPTO1_IRQn = 48, /*!< 48 EFM32 CRYPTO1 Interrupt */ |
<> | 139:856d2700e60b | 106 | TRNG0_IRQn = 49, /*!< 49 EFM32 TRNG0 Interrupt */ |
<> | 139:856d2700e60b | 107 | } IRQn_Type; |
<> | 139:856d2700e60b | 108 | |
<> | 139:856d2700e60b | 109 | #define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ |
<> | 139:856d2700e60b | 110 | |
<> | 139:856d2700e60b | 111 | /**************************************************************************//** |
<> | 139:856d2700e60b | 112 | * @defgroup EFM32PG12B500F512GL125_Core EFM32PG12B500F512GL125 Core |
<> | 139:856d2700e60b | 113 | * @{ |
<> | 139:856d2700e60b | 114 | * @brief Processor and Core Peripheral Section |
<> | 139:856d2700e60b | 115 | *****************************************************************************/ |
<> | 139:856d2700e60b | 116 | #define __MPU_PRESENT 1 /**< Presence of MPU */ |
<> | 139:856d2700e60b | 117 | #define __FPU_PRESENT 1 /**< Presence of FPU */ |
<> | 139:856d2700e60b | 118 | #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ |
<> | 139:856d2700e60b | 119 | #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ |
<> | 139:856d2700e60b | 120 | #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ |
<> | 139:856d2700e60b | 121 | |
<> | 139:856d2700e60b | 122 | /** @} End of group EFM32PG12B500F512GL125_Core */ |
<> | 139:856d2700e60b | 123 | |
<> | 139:856d2700e60b | 124 | /**************************************************************************//** |
<> | 139:856d2700e60b | 125 | * @defgroup EFM32PG12B500F512GL125_Part EFM32PG12B500F512GL125 Part |
<> | 139:856d2700e60b | 126 | * @{ |
<> | 139:856d2700e60b | 127 | ******************************************************************************/ |
<> | 139:856d2700e60b | 128 | |
<> | 139:856d2700e60b | 129 | /** Part family */ |
<> | 139:856d2700e60b | 130 | #define _EFM32_PEARL_FAMILY 1 /**< PEARL Gecko MCU Family */ |
<> | 139:856d2700e60b | 131 | #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ |
<> | 139:856d2700e60b | 132 | #define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ |
<> | 139:856d2700e60b | 133 | #define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ |
<> | 139:856d2700e60b | 134 | #define _SILICON_LABS_32B_SERIES_1_CONFIG_2 /**< Series 1, Configuration 2 */ |
<> | 139:856d2700e60b | 135 | #define _SILICON_LABS_32B_SERIES_1_CONFIG 2 /**< Series 1, Configuration 2 */ |
<> | 139:856d2700e60b | 136 | #define _SILICON_LABS_GECKO_INTERNAL_SDID 84 /** Silicon Labs internal use only, may change any time */ |
<> | 139:856d2700e60b | 137 | #define _SILICON_LABS_GECKO_INTERNAL_SDID_84 /** Silicon Labs internal use only, may change any time */ |
<> | 139:856d2700e60b | 138 | #define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ |
<> | 139:856d2700e60b | 139 | #define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ |
<> | 139:856d2700e60b | 140 | #define _SILICON_LABS_32B_PLATFORM_2_GEN_2 /**< @deprecated Platform 2, generation 2 */ |
<> | 139:856d2700e60b | 141 | #define _SILICON_LABS_32B_PLATFORM_2_GEN 2 /**< @deprecated Platform 2, generation 2 */ |
<> | 139:856d2700e60b | 142 | |
<> | 139:856d2700e60b | 143 | /* If part number is not defined as compiler option, define it */ |
<> | 139:856d2700e60b | 144 | #if !defined(EFM32PG12B500F512GL125) |
<> | 139:856d2700e60b | 145 | #define EFM32PG12B500F512GL125 1 /**< PEARL Gecko Part */ |
<> | 139:856d2700e60b | 146 | #endif |
<> | 139:856d2700e60b | 147 | |
<> | 139:856d2700e60b | 148 | /** Configure part number */ |
<> | 139:856d2700e60b | 149 | #define PART_NUMBER "EFM32PG12B500F512GL125" /**< Part Number */ |
<> | 139:856d2700e60b | 150 | |
<> | 139:856d2700e60b | 151 | /** Memory Base addresses and limits */ |
<> | 139:856d2700e60b | 152 | #define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ |
<> | 139:856d2700e60b | 153 | #define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ |
<> | 139:856d2700e60b | 154 | #define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ |
<> | 139:856d2700e60b | 155 | #define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ |
<> | 139:856d2700e60b | 156 | #define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ |
<> | 139:856d2700e60b | 157 | #define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ |
<> | 139:856d2700e60b | 158 | #define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ |
<> | 139:856d2700e60b | 159 | #define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ |
<> | 139:856d2700e60b | 160 | #define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ |
<> | 139:856d2700e60b | 161 | #define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ |
<> | 139:856d2700e60b | 162 | #define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ |
<> | 139:856d2700e60b | 163 | #define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ |
<> | 139:856d2700e60b | 164 | #define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ |
<> | 139:856d2700e60b | 165 | #define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ |
<> | 139:856d2700e60b | 166 | #define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ |
<> | 139:856d2700e60b | 167 | #define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ |
<> | 139:856d2700e60b | 168 | #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ |
<> | 139:856d2700e60b | 169 | #define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ |
<> | 139:856d2700e60b | 170 | #define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ |
<> | 139:856d2700e60b | 171 | #define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ |
<> | 139:856d2700e60b | 172 | #define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ |
<> | 139:856d2700e60b | 173 | #define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ |
<> | 139:856d2700e60b | 174 | #define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ |
<> | 139:856d2700e60b | 175 | #define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ |
<> | 139:856d2700e60b | 176 | #define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ |
<> | 139:856d2700e60b | 177 | #define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ |
<> | 139:856d2700e60b | 178 | #define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ |
<> | 139:856d2700e60b | 179 | #define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ |
<> | 139:856d2700e60b | 180 | #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ |
<> | 139:856d2700e60b | 181 | #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ |
<> | 139:856d2700e60b | 182 | #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ |
<> | 139:856d2700e60b | 183 | #define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ |
<> | 139:856d2700e60b | 184 | #define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ |
<> | 139:856d2700e60b | 185 | #define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ |
<> | 139:856d2700e60b | 186 | #define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ |
<> | 139:856d2700e60b | 187 | #define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ |
<> | 139:856d2700e60b | 188 | #define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ |
<> | 139:856d2700e60b | 189 | #define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ |
<> | 139:856d2700e60b | 190 | #define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ |
<> | 139:856d2700e60b | 191 | #define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ |
<> | 139:856d2700e60b | 192 | #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ |
<> | 139:856d2700e60b | 193 | #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ |
<> | 139:856d2700e60b | 194 | #define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ |
<> | 139:856d2700e60b | 195 | #define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ |
<> | 139:856d2700e60b | 196 | #define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ |
<> | 139:856d2700e60b | 197 | #define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ |
<> | 139:856d2700e60b | 198 | #define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ |
<> | 139:856d2700e60b | 199 | #define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ |
<> | 139:856d2700e60b | 200 | #define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ |
<> | 139:856d2700e60b | 201 | #define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ |
<> | 139:856d2700e60b | 202 | #define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ |
<> | 139:856d2700e60b | 203 | #define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ |
<> | 139:856d2700e60b | 204 | #define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ |
<> | 139:856d2700e60b | 205 | #define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ |
<> | 139:856d2700e60b | 206 | #define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ |
<> | 139:856d2700e60b | 207 | #define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ |
<> | 139:856d2700e60b | 208 | #define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ |
<> | 139:856d2700e60b | 209 | #define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ |
<> | 139:856d2700e60b | 210 | #define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ |
<> | 139:856d2700e60b | 211 | #define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ |
<> | 139:856d2700e60b | 212 | #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ |
<> | 139:856d2700e60b | 213 | #define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ |
<> | 139:856d2700e60b | 214 | #define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ |
<> | 139:856d2700e60b | 215 | #define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ |
<> | 139:856d2700e60b | 216 | #define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ |
<> | 139:856d2700e60b | 217 | #define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ |
<> | 139:856d2700e60b | 218 | #define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ |
<> | 139:856d2700e60b | 219 | #define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ |
<> | 139:856d2700e60b | 220 | #define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ |
<> | 139:856d2700e60b | 221 | #define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ |
<> | 139:856d2700e60b | 222 | #define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ |
<> | 139:856d2700e60b | 223 | #define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ |
<> | 139:856d2700e60b | 224 | #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ |
<> | 139:856d2700e60b | 225 | #define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ |
<> | 139:856d2700e60b | 226 | #define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ |
<> | 139:856d2700e60b | 227 | #define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ |
<> | 139:856d2700e60b | 228 | |
<> | 139:856d2700e60b | 229 | /** Bit banding area */ |
<> | 139:856d2700e60b | 230 | #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ |
<> | 139:856d2700e60b | 231 | #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ |
<> | 139:856d2700e60b | 232 | |
<> | 139:856d2700e60b | 233 | /** Flash and SRAM limits for EFM32PG12B500F512GL125 */ |
<> | 139:856d2700e60b | 234 | #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ |
<> | 139:856d2700e60b | 235 | #define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ |
<> | 139:856d2700e60b | 236 | #define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size (interleaving off) */ |
<> | 139:856d2700e60b | 237 | #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ |
<> | 139:856d2700e60b | 238 | #define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */ |
<> | 139:856d2700e60b | 239 | #define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ |
<> | 139:856d2700e60b | 240 | #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ |
<> | 139:856d2700e60b | 241 | #define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ |
<> | 139:856d2700e60b | 242 | #define EXT_IRQ_COUNT 51 /**< Number of External (NVIC) interrupts */ |
<> | 139:856d2700e60b | 243 | |
<> | 139:856d2700e60b | 244 | /** AF channels connect the different on-chip peripherals with the af-mux */ |
<> | 139:856d2700e60b | 245 | #define AFCHAN_MAX 136 |
<> | 139:856d2700e60b | 246 | #define AFCHANLOC_MAX 32 |
<> | 139:856d2700e60b | 247 | /** Analog AF channels */ |
<> | 139:856d2700e60b | 248 | #define AFACHAN_MAX 125 |
<> | 139:856d2700e60b | 249 | |
<> | 139:856d2700e60b | 250 | /* Part number capabilities */ |
<> | 139:856d2700e60b | 251 | |
<> | 139:856d2700e60b | 252 | #define CRYPTO_PRESENT /**< CRYPTO is available in this part */ |
<> | 139:856d2700e60b | 253 | #define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ |
<> | 139:856d2700e60b | 254 | #define TIMER_PRESENT /**< TIMER is available in this part */ |
<> | 139:856d2700e60b | 255 | #define TIMER_COUNT 2 /**< 2 TIMERs available */ |
<> | 139:856d2700e60b | 256 | #define WTIMER_PRESENT /**< WTIMER is available in this part */ |
<> | 139:856d2700e60b | 257 | #define WTIMER_COUNT 2 /**< 2 WTIMERs available */ |
<> | 139:856d2700e60b | 258 | #define USART_PRESENT /**< USART is available in this part */ |
<> | 139:856d2700e60b | 259 | #define USART_COUNT 4 /**< 4 USARTs available */ |
<> | 139:856d2700e60b | 260 | #define LEUART_PRESENT /**< LEUART is available in this part */ |
<> | 139:856d2700e60b | 261 | #define LEUART_COUNT 1 /**< 1 LEUARTs available */ |
<> | 139:856d2700e60b | 262 | #define LETIMER_PRESENT /**< LETIMER is available in this part */ |
<> | 139:856d2700e60b | 263 | #define LETIMER_COUNT 1 /**< 1 LETIMERs available */ |
<> | 139:856d2700e60b | 264 | #define PCNT_PRESENT /**< PCNT is available in this part */ |
<> | 139:856d2700e60b | 265 | #define PCNT_COUNT 3 /**< 3 PCNTs available */ |
<> | 139:856d2700e60b | 266 | #define I2C_PRESENT /**< I2C is available in this part */ |
<> | 139:856d2700e60b | 267 | #define I2C_COUNT 2 /**< 2 I2Cs available */ |
<> | 139:856d2700e60b | 268 | #define ADC_PRESENT /**< ADC is available in this part */ |
<> | 139:856d2700e60b | 269 | #define ADC_COUNT 1 /**< 1 ADCs available */ |
<> | 139:856d2700e60b | 270 | #define ACMP_PRESENT /**< ACMP is available in this part */ |
<> | 139:856d2700e60b | 271 | #define ACMP_COUNT 2 /**< 2 ACMPs available */ |
<> | 139:856d2700e60b | 272 | #define IDAC_PRESENT /**< IDAC is available in this part */ |
<> | 139:856d2700e60b | 273 | #define IDAC_COUNT 1 /**< 1 IDACs available */ |
<> | 139:856d2700e60b | 274 | #define VDAC_PRESENT /**< VDAC is available in this part */ |
<> | 139:856d2700e60b | 275 | #define VDAC_COUNT 1 /**< 1 VDACs available */ |
<> | 139:856d2700e60b | 276 | #define WDOG_PRESENT /**< WDOG is available in this part */ |
<> | 139:856d2700e60b | 277 | #define WDOG_COUNT 2 /**< 2 WDOGs available */ |
<> | 139:856d2700e60b | 278 | #define TRNG_PRESENT /**< TRNG is available in this part */ |
<> | 139:856d2700e60b | 279 | #define TRNG_COUNT 1 /**< 1 TRNGs available */ |
<> | 139:856d2700e60b | 280 | #define SYSTICK_PRESENT |
<> | 139:856d2700e60b | 281 | #define SYSTICK_COUNT 1 |
<> | 139:856d2700e60b | 282 | #define MSC_PRESENT |
<> | 139:856d2700e60b | 283 | #define MSC_COUNT 1 |
<> | 139:856d2700e60b | 284 | #define EMU_PRESENT |
<> | 139:856d2700e60b | 285 | #define EMU_COUNT 1 |
<> | 139:856d2700e60b | 286 | #define RMU_PRESENT |
<> | 139:856d2700e60b | 287 | #define RMU_COUNT 1 |
<> | 139:856d2700e60b | 288 | #define CMU_PRESENT |
<> | 139:856d2700e60b | 289 | #define CMU_COUNT 1 |
<> | 139:856d2700e60b | 290 | #define GPIO_PRESENT |
<> | 139:856d2700e60b | 291 | #define GPIO_COUNT 1 |
<> | 139:856d2700e60b | 292 | #define PRS_PRESENT |
<> | 139:856d2700e60b | 293 | #define PRS_COUNT 1 |
<> | 139:856d2700e60b | 294 | #define LDMA_PRESENT |
<> | 139:856d2700e60b | 295 | #define LDMA_COUNT 1 |
<> | 139:856d2700e60b | 296 | #define FPUEH_PRESENT |
<> | 139:856d2700e60b | 297 | #define FPUEH_COUNT 1 |
<> | 139:856d2700e60b | 298 | #define GPCRC_PRESENT |
<> | 139:856d2700e60b | 299 | #define GPCRC_COUNT 1 |
<> | 139:856d2700e60b | 300 | #define CRYOTIMER_PRESENT |
<> | 139:856d2700e60b | 301 | #define CRYOTIMER_COUNT 1 |
<> | 139:856d2700e60b | 302 | #define CSEN_PRESENT |
<> | 139:856d2700e60b | 303 | #define CSEN_COUNT 1 |
<> | 139:856d2700e60b | 304 | #define LESENSE_PRESENT |
<> | 139:856d2700e60b | 305 | #define LESENSE_COUNT 1 |
<> | 139:856d2700e60b | 306 | #define RTCC_PRESENT |
<> | 139:856d2700e60b | 307 | #define RTCC_COUNT 1 |
<> | 139:856d2700e60b | 308 | #define ETM_PRESENT |
<> | 139:856d2700e60b | 309 | #define ETM_COUNT 1 |
<> | 139:856d2700e60b | 310 | #define BOOTLOADER_PRESENT |
<> | 139:856d2700e60b | 311 | #define BOOTLOADER_COUNT 1 |
<> | 139:856d2700e60b | 312 | #define SMU_PRESENT |
<> | 139:856d2700e60b | 313 | #define SMU_COUNT 1 |
<> | 139:856d2700e60b | 314 | |
<> | 139:856d2700e60b | 315 | #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ |
<> | 139:856d2700e60b | 316 | #include "system_efm32pg12b.h" /* System Header File */ |
<> | 139:856d2700e60b | 317 | |
<> | 139:856d2700e60b | 318 | /** @} End of group EFM32PG12B500F512GL125_Part */ |
<> | 139:856d2700e60b | 319 | |
<> | 139:856d2700e60b | 320 | /**************************************************************************//** |
<> | 139:856d2700e60b | 321 | * @defgroup EFM32PG12B500F512GL125_Peripheral_TypeDefs EFM32PG12B500F512GL125 Peripheral TypeDefs |
<> | 139:856d2700e60b | 322 | * @{ |
<> | 139:856d2700e60b | 323 | * @brief Device Specific Peripheral Register Structures |
<> | 139:856d2700e60b | 324 | *****************************************************************************/ |
<> | 139:856d2700e60b | 325 | |
<> | 139:856d2700e60b | 326 | #include "efm32pg12b_msc.h" |
<> | 139:856d2700e60b | 327 | #include "efm32pg12b_emu.h" |
<> | 139:856d2700e60b | 328 | #include "efm32pg12b_rmu.h" |
<> | 139:856d2700e60b | 329 | #include "efm32pg12b_cmu.h" |
<> | 139:856d2700e60b | 330 | #include "efm32pg12b_crypto.h" |
<> | 139:856d2700e60b | 331 | #include "efm32pg12b_gpio_p.h" |
<> | 139:856d2700e60b | 332 | #include "efm32pg12b_gpio.h" |
<> | 139:856d2700e60b | 333 | #include "efm32pg12b_prs_ch.h" |
<> | 139:856d2700e60b | 334 | #include "efm32pg12b_prs.h" |
<> | 139:856d2700e60b | 335 | #include "efm32pg12b_ldma_ch.h" |
<> | 139:856d2700e60b | 336 | #include "efm32pg12b_ldma.h" |
<> | 139:856d2700e60b | 337 | #include "efm32pg12b_fpueh.h" |
<> | 139:856d2700e60b | 338 | #include "efm32pg12b_gpcrc.h" |
<> | 139:856d2700e60b | 339 | #include "efm32pg12b_timer_cc.h" |
<> | 139:856d2700e60b | 340 | #include "efm32pg12b_timer.h" |
<> | 139:856d2700e60b | 341 | #include "efm32pg12b_usart.h" |
<> | 139:856d2700e60b | 342 | #include "efm32pg12b_leuart.h" |
<> | 139:856d2700e60b | 343 | #include "efm32pg12b_letimer.h" |
<> | 139:856d2700e60b | 344 | #include "efm32pg12b_cryotimer.h" |
<> | 139:856d2700e60b | 345 | #include "efm32pg12b_pcnt.h" |
<> | 139:856d2700e60b | 346 | #include "efm32pg12b_i2c.h" |
<> | 139:856d2700e60b | 347 | #include "efm32pg12b_adc.h" |
<> | 139:856d2700e60b | 348 | #include "efm32pg12b_acmp.h" |
<> | 139:856d2700e60b | 349 | #include "efm32pg12b_idac.h" |
<> | 139:856d2700e60b | 350 | #include "efm32pg12b_vdac_opa.h" |
<> | 139:856d2700e60b | 351 | #include "efm32pg12b_vdac.h" |
<> | 139:856d2700e60b | 352 | #include "efm32pg12b_csen.h" |
<> | 139:856d2700e60b | 353 | #include "efm32pg12b_lesense_st.h" |
<> | 139:856d2700e60b | 354 | #include "efm32pg12b_lesense_buf.h" |
<> | 139:856d2700e60b | 355 | #include "efm32pg12b_lesense_ch.h" |
<> | 139:856d2700e60b | 356 | #include "efm32pg12b_lesense.h" |
<> | 139:856d2700e60b | 357 | #include "efm32pg12b_rtcc_cc.h" |
<> | 139:856d2700e60b | 358 | #include "efm32pg12b_rtcc_ret.h" |
<> | 139:856d2700e60b | 359 | #include "efm32pg12b_rtcc.h" |
<> | 139:856d2700e60b | 360 | #include "efm32pg12b_wdog_pch.h" |
<> | 139:856d2700e60b | 361 | #include "efm32pg12b_wdog.h" |
<> | 139:856d2700e60b | 362 | #include "efm32pg12b_etm.h" |
<> | 139:856d2700e60b | 363 | #include "efm32pg12b_smu.h" |
<> | 139:856d2700e60b | 364 | #include "efm32pg12b_trng.h" |
<> | 139:856d2700e60b | 365 | #include "efm32pg12b_dma_descriptor.h" |
<> | 139:856d2700e60b | 366 | #include "efm32pg12b_devinfo.h" |
<> | 139:856d2700e60b | 367 | #include "efm32pg12b_romtable.h" |
<> | 139:856d2700e60b | 368 | |
<> | 139:856d2700e60b | 369 | /** @} End of group EFM32PG12B500F512GL125_Peripheral_TypeDefs */ |
<> | 139:856d2700e60b | 370 | |
<> | 139:856d2700e60b | 371 | /**************************************************************************//** |
<> | 139:856d2700e60b | 372 | * @defgroup EFM32PG12B500F512GL125_Peripheral_Base EFM32PG12B500F512GL125 Peripheral Memory Map |
<> | 139:856d2700e60b | 373 | * @{ |
<> | 139:856d2700e60b | 374 | *****************************************************************************/ |
<> | 139:856d2700e60b | 375 | |
<> | 139:856d2700e60b | 376 | #define MSC_BASE (0x400E0000UL) /**< MSC base address */ |
<> | 139:856d2700e60b | 377 | #define EMU_BASE (0x400E3000UL) /**< EMU base address */ |
<> | 139:856d2700e60b | 378 | #define RMU_BASE (0x400E5000UL) /**< RMU base address */ |
<> | 139:856d2700e60b | 379 | #define CMU_BASE (0x400E4000UL) /**< CMU base address */ |
<> | 139:856d2700e60b | 380 | #define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ |
<> | 139:856d2700e60b | 381 | #define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ |
<> | 139:856d2700e60b | 382 | #define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ |
<> | 139:856d2700e60b | 383 | #define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ |
<> | 139:856d2700e60b | 384 | #define PRS_BASE (0x400E6000UL) /**< PRS base address */ |
<> | 139:856d2700e60b | 385 | #define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ |
<> | 139:856d2700e60b | 386 | #define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ |
<> | 139:856d2700e60b | 387 | #define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ |
<> | 139:856d2700e60b | 388 | #define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ |
<> | 139:856d2700e60b | 389 | #define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ |
<> | 139:856d2700e60b | 390 | #define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ |
<> | 139:856d2700e60b | 391 | #define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ |
<> | 139:856d2700e60b | 392 | #define USART0_BASE (0x40010000UL) /**< USART0 base address */ |
<> | 139:856d2700e60b | 393 | #define USART1_BASE (0x40010400UL) /**< USART1 base address */ |
<> | 139:856d2700e60b | 394 | #define USART2_BASE (0x40010800UL) /**< USART2 base address */ |
<> | 139:856d2700e60b | 395 | #define USART3_BASE (0x40010C00UL) /**< USART3 base address */ |
<> | 139:856d2700e60b | 396 | #define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ |
<> | 139:856d2700e60b | 397 | #define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ |
<> | 139:856d2700e60b | 398 | #define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ |
<> | 139:856d2700e60b | 399 | #define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ |
<> | 139:856d2700e60b | 400 | #define PCNT1_BASE (0x4004E400UL) /**< PCNT1 base address */ |
<> | 139:856d2700e60b | 401 | #define PCNT2_BASE (0x4004E800UL) /**< PCNT2 base address */ |
<> | 139:856d2700e60b | 402 | #define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ |
<> | 139:856d2700e60b | 403 | #define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ |
<> | 139:856d2700e60b | 404 | #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ |
<> | 139:856d2700e60b | 405 | #define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ |
<> | 139:856d2700e60b | 406 | #define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ |
<> | 139:856d2700e60b | 407 | #define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ |
<> | 139:856d2700e60b | 408 | #define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ |
<> | 139:856d2700e60b | 409 | #define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ |
<> | 139:856d2700e60b | 410 | #define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ |
<> | 139:856d2700e60b | 411 | #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ |
<> | 139:856d2700e60b | 412 | #define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ |
<> | 139:856d2700e60b | 413 | #define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ |
<> | 139:856d2700e60b | 414 | #define ETM_BASE (0xE0041000UL) /**< ETM base address */ |
<> | 139:856d2700e60b | 415 | #define SMU_BASE (0x40022000UL) /**< SMU base address */ |
<> | 139:856d2700e60b | 416 | #define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ |
<> | 139:856d2700e60b | 417 | #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ |
<> | 139:856d2700e60b | 418 | #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ |
<> | 139:856d2700e60b | 419 | #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ |
<> | 139:856d2700e60b | 420 | #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ |
<> | 139:856d2700e60b | 421 | |
<> | 139:856d2700e60b | 422 | /** @} End of group EFM32PG12B500F512GL125_Peripheral_Base */ |
<> | 139:856d2700e60b | 423 | |
<> | 139:856d2700e60b | 424 | /**************************************************************************//** |
<> | 139:856d2700e60b | 425 | * @defgroup EFM32PG12B500F512GL125_Peripheral_Declaration EFM32PG12B500F512GL125 Peripheral Declarations |
<> | 139:856d2700e60b | 426 | * @{ |
<> | 139:856d2700e60b | 427 | *****************************************************************************/ |
<> | 139:856d2700e60b | 428 | |
<> | 139:856d2700e60b | 429 | #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ |
<> | 139:856d2700e60b | 430 | #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ |
<> | 139:856d2700e60b | 431 | #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ |
<> | 139:856d2700e60b | 432 | #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ |
<> | 139:856d2700e60b | 433 | #define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ |
<> | 139:856d2700e60b | 434 | #define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ |
<> | 139:856d2700e60b | 435 | #define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ |
<> | 139:856d2700e60b | 436 | #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ |
<> | 139:856d2700e60b | 437 | #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ |
<> | 139:856d2700e60b | 438 | #define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ |
<> | 139:856d2700e60b | 439 | #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ |
<> | 139:856d2700e60b | 440 | #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ |
<> | 139:856d2700e60b | 441 | #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ |
<> | 139:856d2700e60b | 442 | #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ |
<> | 139:856d2700e60b | 443 | #define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ |
<> | 139:856d2700e60b | 444 | #define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ |
<> | 139:856d2700e60b | 445 | #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ |
<> | 139:856d2700e60b | 446 | #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ |
<> | 139:856d2700e60b | 447 | #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ |
<> | 139:856d2700e60b | 448 | #define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ |
<> | 139:856d2700e60b | 449 | #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ |
<> | 139:856d2700e60b | 450 | #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ |
<> | 139:856d2700e60b | 451 | #define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ |
<> | 139:856d2700e60b | 452 | #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ |
<> | 139:856d2700e60b | 453 | #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ |
<> | 139:856d2700e60b | 454 | #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ |
<> | 139:856d2700e60b | 455 | #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ |
<> | 139:856d2700e60b | 456 | #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ |
<> | 139:856d2700e60b | 457 | #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ |
<> | 139:856d2700e60b | 458 | #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ |
<> | 139:856d2700e60b | 459 | #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ |
<> | 139:856d2700e60b | 460 | #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ |
<> | 139:856d2700e60b | 461 | #define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ |
<> | 139:856d2700e60b | 462 | #define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ |
<> | 139:856d2700e60b | 463 | #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ |
<> | 139:856d2700e60b | 464 | #define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ |
<> | 139:856d2700e60b | 465 | #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ |
<> | 139:856d2700e60b | 466 | #define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ |
<> | 139:856d2700e60b | 467 | #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ |
<> | 139:856d2700e60b | 468 | #define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ |
<> | 139:856d2700e60b | 469 | #define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ |
<> | 139:856d2700e60b | 470 | #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ |
<> | 139:856d2700e60b | 471 | #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ |
<> | 139:856d2700e60b | 472 | |
<> | 139:856d2700e60b | 473 | /** @} End of group EFM32PG12B500F512GL125_Peripheral_Declaration */ |
<> | 139:856d2700e60b | 474 | |
<> | 139:856d2700e60b | 475 | /**************************************************************************//** |
<> | 139:856d2700e60b | 476 | * @defgroup EFM32PG12B500F512GL125_Peripheral_Offsets EFM32PG12B500F512GL125 Peripheral Offsets |
<> | 139:856d2700e60b | 477 | * @{ |
<> | 139:856d2700e60b | 478 | *****************************************************************************/ |
<> | 139:856d2700e60b | 479 | |
<> | 139:856d2700e60b | 480 | #define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ |
<> | 139:856d2700e60b | 481 | #define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ |
<> | 139:856d2700e60b | 482 | #define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ |
<> | 139:856d2700e60b | 483 | #define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ |
<> | 139:856d2700e60b | 484 | #define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ |
<> | 139:856d2700e60b | 485 | #define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ |
<> | 139:856d2700e60b | 486 | #define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ |
<> | 139:856d2700e60b | 487 | #define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ |
<> | 139:856d2700e60b | 488 | #define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ |
<> | 139:856d2700e60b | 489 | #define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ |
<> | 139:856d2700e60b | 490 | #define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ |
<> | 139:856d2700e60b | 491 | #define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ |
<> | 139:856d2700e60b | 492 | #define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ |
<> | 139:856d2700e60b | 493 | #define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ |
<> | 139:856d2700e60b | 494 | |
<> | 139:856d2700e60b | 495 | /** @} End of group EFM32PG12B500F512GL125_Peripheral_Offsets */ |
<> | 139:856d2700e60b | 496 | |
<> | 139:856d2700e60b | 497 | |
<> | 139:856d2700e60b | 498 | /**************************************************************************//** |
<> | 139:856d2700e60b | 499 | * @defgroup EFM32PG12B500F512GL125_BitFields EFM32PG12B500F512GL125 Bit Fields |
<> | 139:856d2700e60b | 500 | * @{ |
<> | 139:856d2700e60b | 501 | *****************************************************************************/ |
<> | 139:856d2700e60b | 502 | |
<> | 139:856d2700e60b | 503 | #include "efm32pg12b_prs_signals.h" |
<> | 139:856d2700e60b | 504 | #include "efm32pg12b_dmareq.h" |
<> | 139:856d2700e60b | 505 | |
<> | 139:856d2700e60b | 506 | /**************************************************************************//** |
<> | 139:856d2700e60b | 507 | * @defgroup EFM32PG12B500F512GL125_WTIMER_BitFields EFM32PG12B500F512GL125_WTIMER Bit Fields |
<> | 139:856d2700e60b | 508 | * @{ |
<> | 139:856d2700e60b | 509 | *****************************************************************************/ |
<> | 139:856d2700e60b | 510 | |
<> | 139:856d2700e60b | 511 | /* Bit fields for WTIMER CTRL */ |
<> | 139:856d2700e60b | 512 | #define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 513 | #define _WTIMER_CTRL_MASK 0x3F032FFBUL /**< Mask for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 514 | #define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ |
<> | 139:856d2700e60b | 515 | #define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ |
<> | 139:856d2700e60b | 516 | #define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 517 | #define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 518 | #define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 519 | #define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 520 | #define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 521 | #define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 522 | #define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 523 | #define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 524 | #define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 525 | #define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 526 | #define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ |
<> | 139:856d2700e60b | 527 | #define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ |
<> | 139:856d2700e60b | 528 | #define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ |
<> | 139:856d2700e60b | 529 | #define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 530 | #define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 531 | #define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ |
<> | 139:856d2700e60b | 532 | #define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ |
<> | 139:856d2700e60b | 533 | #define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ |
<> | 139:856d2700e60b | 534 | #define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 535 | #define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 536 | #define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ |
<> | 139:856d2700e60b | 537 | #define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ |
<> | 139:856d2700e60b | 538 | #define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ |
<> | 139:856d2700e60b | 539 | #define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 540 | #define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 541 | #define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 542 | #define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 543 | #define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 544 | #define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 545 | #define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ |
<> | 139:856d2700e60b | 546 | #define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ |
<> | 139:856d2700e60b | 547 | #define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ |
<> | 139:856d2700e60b | 548 | #define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 549 | #define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 550 | #define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ |
<> | 139:856d2700e60b | 551 | #define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ |
<> | 139:856d2700e60b | 552 | #define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ |
<> | 139:856d2700e60b | 553 | #define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 554 | #define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 555 | #define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ |
<> | 139:856d2700e60b | 556 | #define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ |
<> | 139:856d2700e60b | 557 | #define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 558 | #define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 559 | #define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 560 | #define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 561 | #define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 562 | #define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 563 | #define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 564 | #define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 565 | #define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 566 | #define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 567 | #define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ |
<> | 139:856d2700e60b | 568 | #define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ |
<> | 139:856d2700e60b | 569 | #define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 570 | #define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 571 | #define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 572 | #define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 573 | #define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 574 | #define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 575 | #define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 576 | #define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 577 | #define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 578 | #define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 579 | #define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ |
<> | 139:856d2700e60b | 580 | #define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ |
<> | 139:856d2700e60b | 581 | #define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ |
<> | 139:856d2700e60b | 582 | #define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 583 | #define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 584 | #define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ |
<> | 139:856d2700e60b | 585 | #define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ |
<> | 139:856d2700e60b | 586 | #define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 587 | #define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 588 | #define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 589 | #define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 590 | #define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 591 | #define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 592 | #define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 593 | #define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 594 | #define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ |
<> | 139:856d2700e60b | 595 | #define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ |
<> | 139:856d2700e60b | 596 | #define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 597 | #define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 598 | #define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 599 | #define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 600 | #define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 601 | #define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 602 | #define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 603 | #define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 604 | #define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 605 | #define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 606 | #define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 607 | #define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 608 | #define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 609 | #define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 610 | #define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 611 | #define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 612 | #define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 613 | #define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 614 | #define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 615 | #define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 616 | #define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 617 | #define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 618 | #define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 619 | #define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 620 | #define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ |
<> | 139:856d2700e60b | 621 | #define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ |
<> | 139:856d2700e60b | 622 | #define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ |
<> | 139:856d2700e60b | 623 | #define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 624 | #define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 625 | #define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output initial State */ |
<> | 139:856d2700e60b | 626 | #define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ |
<> | 139:856d2700e60b | 627 | #define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ |
<> | 139:856d2700e60b | 628 | #define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 629 | #define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ |
<> | 139:856d2700e60b | 630 | |
<> | 139:856d2700e60b | 631 | /* Bit fields for WTIMER CMD */ |
<> | 139:856d2700e60b | 632 | #define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ |
<> | 139:856d2700e60b | 633 | #define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ |
<> | 139:856d2700e60b | 634 | #define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ |
<> | 139:856d2700e60b | 635 | #define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ |
<> | 139:856d2700e60b | 636 | #define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ |
<> | 139:856d2700e60b | 637 | #define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ |
<> | 139:856d2700e60b | 638 | #define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ |
<> | 139:856d2700e60b | 639 | #define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ |
<> | 139:856d2700e60b | 640 | #define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ |
<> | 139:856d2700e60b | 641 | #define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ |
<> | 139:856d2700e60b | 642 | #define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ |
<> | 139:856d2700e60b | 643 | #define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ |
<> | 139:856d2700e60b | 644 | |
<> | 139:856d2700e60b | 645 | /* Bit fields for WTIMER STATUS */ |
<> | 139:856d2700e60b | 646 | #define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 647 | #define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 648 | #define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ |
<> | 139:856d2700e60b | 649 | #define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ |
<> | 139:856d2700e60b | 650 | #define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ |
<> | 139:856d2700e60b | 651 | #define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 652 | #define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 653 | #define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ |
<> | 139:856d2700e60b | 654 | #define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ |
<> | 139:856d2700e60b | 655 | #define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ |
<> | 139:856d2700e60b | 656 | #define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 657 | #define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 658 | #define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 659 | #define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 660 | #define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 661 | #define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 662 | #define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ |
<> | 139:856d2700e60b | 663 | #define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ |
<> | 139:856d2700e60b | 664 | #define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ |
<> | 139:856d2700e60b | 665 | #define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 666 | #define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 667 | #define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ |
<> | 139:856d2700e60b | 668 | #define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ |
<> | 139:856d2700e60b | 669 | #define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ |
<> | 139:856d2700e60b | 670 | #define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 671 | #define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 672 | #define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ |
<> | 139:856d2700e60b | 673 | #define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ |
<> | 139:856d2700e60b | 674 | #define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ |
<> | 139:856d2700e60b | 675 | #define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 676 | #define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 677 | #define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ |
<> | 139:856d2700e60b | 678 | #define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ |
<> | 139:856d2700e60b | 679 | #define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ |
<> | 139:856d2700e60b | 680 | #define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 681 | #define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 682 | #define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ |
<> | 139:856d2700e60b | 683 | #define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ |
<> | 139:856d2700e60b | 684 | #define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ |
<> | 139:856d2700e60b | 685 | #define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 686 | #define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 687 | #define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ |
<> | 139:856d2700e60b | 688 | #define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ |
<> | 139:856d2700e60b | 689 | #define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ |
<> | 139:856d2700e60b | 690 | #define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 691 | #define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 692 | #define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ |
<> | 139:856d2700e60b | 693 | #define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ |
<> | 139:856d2700e60b | 694 | #define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ |
<> | 139:856d2700e60b | 695 | #define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 696 | #define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 697 | #define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ |
<> | 139:856d2700e60b | 698 | #define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ |
<> | 139:856d2700e60b | 699 | #define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ |
<> | 139:856d2700e60b | 700 | #define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 701 | #define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 702 | #define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ |
<> | 139:856d2700e60b | 703 | #define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ |
<> | 139:856d2700e60b | 704 | #define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ |
<> | 139:856d2700e60b | 705 | #define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 706 | #define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 707 | #define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ |
<> | 139:856d2700e60b | 708 | #define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ |
<> | 139:856d2700e60b | 709 | #define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ |
<> | 139:856d2700e60b | 710 | #define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 711 | #define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 712 | #define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 713 | #define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 714 | #define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 715 | #define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 716 | #define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ |
<> | 139:856d2700e60b | 717 | #define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ |
<> | 139:856d2700e60b | 718 | #define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ |
<> | 139:856d2700e60b | 719 | #define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 720 | #define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 721 | #define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 722 | #define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 723 | #define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 724 | #define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 725 | #define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ |
<> | 139:856d2700e60b | 726 | #define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ |
<> | 139:856d2700e60b | 727 | #define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ |
<> | 139:856d2700e60b | 728 | #define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 729 | #define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 730 | #define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 731 | #define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 732 | #define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 733 | #define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 734 | #define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ |
<> | 139:856d2700e60b | 735 | #define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ |
<> | 139:856d2700e60b | 736 | #define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ |
<> | 139:856d2700e60b | 737 | #define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 738 | #define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 739 | #define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 740 | #define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 741 | #define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 742 | #define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ |
<> | 139:856d2700e60b | 743 | |
<> | 139:856d2700e60b | 744 | /* Bit fields for WTIMER IF */ |
<> | 139:856d2700e60b | 745 | #define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ |
<> | 139:856d2700e60b | 746 | #define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ |
<> | 139:856d2700e60b | 747 | #define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ |
<> | 139:856d2700e60b | 748 | #define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ |
<> | 139:856d2700e60b | 749 | #define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ |
<> | 139:856d2700e60b | 750 | #define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 751 | #define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 752 | #define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ |
<> | 139:856d2700e60b | 753 | #define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ |
<> | 139:856d2700e60b | 754 | #define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ |
<> | 139:856d2700e60b | 755 | #define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 756 | #define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 757 | #define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ |
<> | 139:856d2700e60b | 758 | #define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ |
<> | 139:856d2700e60b | 759 | #define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ |
<> | 139:856d2700e60b | 760 | #define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 761 | #define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 762 | #define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ |
<> | 139:856d2700e60b | 763 | #define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ |
<> | 139:856d2700e60b | 764 | #define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ |
<> | 139:856d2700e60b | 765 | #define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 766 | #define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 767 | #define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ |
<> | 139:856d2700e60b | 768 | #define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ |
<> | 139:856d2700e60b | 769 | #define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ |
<> | 139:856d2700e60b | 770 | #define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 771 | #define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 772 | #define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ |
<> | 139:856d2700e60b | 773 | #define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ |
<> | 139:856d2700e60b | 774 | #define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ |
<> | 139:856d2700e60b | 775 | #define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 776 | #define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 777 | #define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ |
<> | 139:856d2700e60b | 778 | #define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ |
<> | 139:856d2700e60b | 779 | #define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ |
<> | 139:856d2700e60b | 780 | #define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 781 | #define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 782 | #define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ |
<> | 139:856d2700e60b | 783 | #define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ |
<> | 139:856d2700e60b | 784 | #define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ |
<> | 139:856d2700e60b | 785 | #define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 786 | #define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 787 | #define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ |
<> | 139:856d2700e60b | 788 | #define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ |
<> | 139:856d2700e60b | 789 | #define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ |
<> | 139:856d2700e60b | 790 | #define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 791 | #define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 792 | #define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ |
<> | 139:856d2700e60b | 793 | #define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ |
<> | 139:856d2700e60b | 794 | #define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ |
<> | 139:856d2700e60b | 795 | #define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 796 | #define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 797 | #define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ |
<> | 139:856d2700e60b | 798 | #define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ |
<> | 139:856d2700e60b | 799 | #define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ |
<> | 139:856d2700e60b | 800 | #define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 801 | #define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ |
<> | 139:856d2700e60b | 802 | |
<> | 139:856d2700e60b | 803 | /* Bit fields for WTIMER IFS */ |
<> | 139:856d2700e60b | 804 | #define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ |
<> | 139:856d2700e60b | 805 | #define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ |
<> | 139:856d2700e60b | 806 | #define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ |
<> | 139:856d2700e60b | 807 | #define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ |
<> | 139:856d2700e60b | 808 | #define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ |
<> | 139:856d2700e60b | 809 | #define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 810 | #define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 811 | #define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ |
<> | 139:856d2700e60b | 812 | #define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ |
<> | 139:856d2700e60b | 813 | #define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ |
<> | 139:856d2700e60b | 814 | #define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 815 | #define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 816 | #define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ |
<> | 139:856d2700e60b | 817 | #define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ |
<> | 139:856d2700e60b | 818 | #define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ |
<> | 139:856d2700e60b | 819 | #define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 820 | #define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 821 | #define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ |
<> | 139:856d2700e60b | 822 | #define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ |
<> | 139:856d2700e60b | 823 | #define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ |
<> | 139:856d2700e60b | 824 | #define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 825 | #define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 826 | #define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ |
<> | 139:856d2700e60b | 827 | #define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ |
<> | 139:856d2700e60b | 828 | #define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ |
<> | 139:856d2700e60b | 829 | #define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 830 | #define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 831 | #define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ |
<> | 139:856d2700e60b | 832 | #define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ |
<> | 139:856d2700e60b | 833 | #define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ |
<> | 139:856d2700e60b | 834 | #define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 835 | #define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 836 | #define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ |
<> | 139:856d2700e60b | 837 | #define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ |
<> | 139:856d2700e60b | 838 | #define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ |
<> | 139:856d2700e60b | 839 | #define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 840 | #define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 841 | #define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ |
<> | 139:856d2700e60b | 842 | #define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ |
<> | 139:856d2700e60b | 843 | #define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ |
<> | 139:856d2700e60b | 844 | #define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 845 | #define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 846 | #define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ |
<> | 139:856d2700e60b | 847 | #define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ |
<> | 139:856d2700e60b | 848 | #define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ |
<> | 139:856d2700e60b | 849 | #define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 850 | #define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 851 | #define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ |
<> | 139:856d2700e60b | 852 | #define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ |
<> | 139:856d2700e60b | 853 | #define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ |
<> | 139:856d2700e60b | 854 | #define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 855 | #define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 856 | #define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ |
<> | 139:856d2700e60b | 857 | #define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ |
<> | 139:856d2700e60b | 858 | #define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ |
<> | 139:856d2700e60b | 859 | #define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 860 | #define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ |
<> | 139:856d2700e60b | 861 | |
<> | 139:856d2700e60b | 862 | /* Bit fields for WTIMER IFC */ |
<> | 139:856d2700e60b | 863 | #define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ |
<> | 139:856d2700e60b | 864 | #define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ |
<> | 139:856d2700e60b | 865 | #define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ |
<> | 139:856d2700e60b | 866 | #define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ |
<> | 139:856d2700e60b | 867 | #define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ |
<> | 139:856d2700e60b | 868 | #define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 869 | #define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 870 | #define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ |
<> | 139:856d2700e60b | 871 | #define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ |
<> | 139:856d2700e60b | 872 | #define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ |
<> | 139:856d2700e60b | 873 | #define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 874 | #define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 875 | #define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ |
<> | 139:856d2700e60b | 876 | #define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ |
<> | 139:856d2700e60b | 877 | #define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ |
<> | 139:856d2700e60b | 878 | #define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 879 | #define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 880 | #define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ |
<> | 139:856d2700e60b | 881 | #define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ |
<> | 139:856d2700e60b | 882 | #define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ |
<> | 139:856d2700e60b | 883 | #define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 884 | #define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 885 | #define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ |
<> | 139:856d2700e60b | 886 | #define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ |
<> | 139:856d2700e60b | 887 | #define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ |
<> | 139:856d2700e60b | 888 | #define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 889 | #define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 890 | #define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ |
<> | 139:856d2700e60b | 891 | #define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ |
<> | 139:856d2700e60b | 892 | #define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ |
<> | 139:856d2700e60b | 893 | #define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 894 | #define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 895 | #define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ |
<> | 139:856d2700e60b | 896 | #define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ |
<> | 139:856d2700e60b | 897 | #define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ |
<> | 139:856d2700e60b | 898 | #define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 899 | #define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 900 | #define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ |
<> | 139:856d2700e60b | 901 | #define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ |
<> | 139:856d2700e60b | 902 | #define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ |
<> | 139:856d2700e60b | 903 | #define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 904 | #define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 905 | #define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ |
<> | 139:856d2700e60b | 906 | #define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ |
<> | 139:856d2700e60b | 907 | #define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ |
<> | 139:856d2700e60b | 908 | #define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 909 | #define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 910 | #define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ |
<> | 139:856d2700e60b | 911 | #define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ |
<> | 139:856d2700e60b | 912 | #define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ |
<> | 139:856d2700e60b | 913 | #define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 914 | #define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 915 | #define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ |
<> | 139:856d2700e60b | 916 | #define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ |
<> | 139:856d2700e60b | 917 | #define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ |
<> | 139:856d2700e60b | 918 | #define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 919 | #define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ |
<> | 139:856d2700e60b | 920 | |
<> | 139:856d2700e60b | 921 | /* Bit fields for WTIMER IEN */ |
<> | 139:856d2700e60b | 922 | #define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ |
<> | 139:856d2700e60b | 923 | #define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ |
<> | 139:856d2700e60b | 924 | #define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ |
<> | 139:856d2700e60b | 925 | #define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ |
<> | 139:856d2700e60b | 926 | #define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ |
<> | 139:856d2700e60b | 927 | #define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 928 | #define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 929 | #define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ |
<> | 139:856d2700e60b | 930 | #define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ |
<> | 139:856d2700e60b | 931 | #define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ |
<> | 139:856d2700e60b | 932 | #define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 933 | #define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 934 | #define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ |
<> | 139:856d2700e60b | 935 | #define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ |
<> | 139:856d2700e60b | 936 | #define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ |
<> | 139:856d2700e60b | 937 | #define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 938 | #define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 939 | #define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ |
<> | 139:856d2700e60b | 940 | #define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ |
<> | 139:856d2700e60b | 941 | #define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ |
<> | 139:856d2700e60b | 942 | #define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 943 | #define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 944 | #define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ |
<> | 139:856d2700e60b | 945 | #define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ |
<> | 139:856d2700e60b | 946 | #define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ |
<> | 139:856d2700e60b | 947 | #define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 948 | #define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 949 | #define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ |
<> | 139:856d2700e60b | 950 | #define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ |
<> | 139:856d2700e60b | 951 | #define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ |
<> | 139:856d2700e60b | 952 | #define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 953 | #define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 954 | #define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ |
<> | 139:856d2700e60b | 955 | #define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ |
<> | 139:856d2700e60b | 956 | #define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ |
<> | 139:856d2700e60b | 957 | #define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 958 | #define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 959 | #define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ |
<> | 139:856d2700e60b | 960 | #define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ |
<> | 139:856d2700e60b | 961 | #define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ |
<> | 139:856d2700e60b | 962 | #define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 963 | #define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 964 | #define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ |
<> | 139:856d2700e60b | 965 | #define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ |
<> | 139:856d2700e60b | 966 | #define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ |
<> | 139:856d2700e60b | 967 | #define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 968 | #define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 969 | #define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ |
<> | 139:856d2700e60b | 970 | #define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ |
<> | 139:856d2700e60b | 971 | #define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ |
<> | 139:856d2700e60b | 972 | #define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 973 | #define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 974 | #define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ |
<> | 139:856d2700e60b | 975 | #define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ |
<> | 139:856d2700e60b | 976 | #define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ |
<> | 139:856d2700e60b | 977 | #define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 978 | #define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ |
<> | 139:856d2700e60b | 979 | |
<> | 139:856d2700e60b | 980 | /* Bit fields for WTIMER TOP */ |
<> | 139:856d2700e60b | 981 | #define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ |
<> | 139:856d2700e60b | 982 | #define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ |
<> | 139:856d2700e60b | 983 | #define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ |
<> | 139:856d2700e60b | 984 | #define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ |
<> | 139:856d2700e60b | 985 | #define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ |
<> | 139:856d2700e60b | 986 | #define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ |
<> | 139:856d2700e60b | 987 | |
<> | 139:856d2700e60b | 988 | /* Bit fields for WTIMER TOPB */ |
<> | 139:856d2700e60b | 989 | #define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ |
<> | 139:856d2700e60b | 990 | #define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ |
<> | 139:856d2700e60b | 991 | #define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ |
<> | 139:856d2700e60b | 992 | #define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ |
<> | 139:856d2700e60b | 993 | #define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ |
<> | 139:856d2700e60b | 994 | #define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ |
<> | 139:856d2700e60b | 995 | |
<> | 139:856d2700e60b | 996 | /* Bit fields for WTIMER CNT */ |
<> | 139:856d2700e60b | 997 | #define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ |
<> | 139:856d2700e60b | 998 | #define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ |
<> | 139:856d2700e60b | 999 | #define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ |
<> | 139:856d2700e60b | 1000 | #define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ |
<> | 139:856d2700e60b | 1001 | #define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ |
<> | 139:856d2700e60b | 1002 | #define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ |
<> | 139:856d2700e60b | 1003 | |
<> | 139:856d2700e60b | 1004 | /* Bit fields for WTIMER LOCK */ |
<> | 139:856d2700e60b | 1005 | #define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ |
<> | 139:856d2700e60b | 1006 | #define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ |
<> | 139:856d2700e60b | 1007 | #define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ |
<> | 139:856d2700e60b | 1008 | #define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ |
<> | 139:856d2700e60b | 1009 | #define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ |
<> | 139:856d2700e60b | 1010 | #define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ |
<> | 139:856d2700e60b | 1011 | #define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ |
<> | 139:856d2700e60b | 1012 | #define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ |
<> | 139:856d2700e60b | 1013 | #define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ |
<> | 139:856d2700e60b | 1014 | #define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ |
<> | 139:856d2700e60b | 1015 | #define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ |
<> | 139:856d2700e60b | 1016 | #define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ |
<> | 139:856d2700e60b | 1017 | #define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ |
<> | 139:856d2700e60b | 1018 | #define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ |
<> | 139:856d2700e60b | 1019 | |
<> | 139:856d2700e60b | 1020 | /* Bit fields for WTIMER ROUTEPEN */ |
<> | 139:856d2700e60b | 1021 | #define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ |
<> | 139:856d2700e60b | 1022 | #define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ |
<> | 139:856d2700e60b | 1023 | #define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ |
<> | 139:856d2700e60b | 1024 | #define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ |
<> | 139:856d2700e60b | 1025 | #define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ |
<> | 139:856d2700e60b | 1026 | #define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ |
<> | 139:856d2700e60b | 1027 | #define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ |
<> | 139:856d2700e60b | 1028 | #define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ |
<> | 139:856d2700e60b | 1029 | #define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ |
<> | 139:856d2700e60b | 1030 | #define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ |
<> | 139:856d2700e60b | 1031 | #define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ |
<> | 139:856d2700e60b | 1032 | #define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ |
<> | 139:856d2700e60b | 1033 | #define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ |
<> | 139:856d2700e60b | 1034 | #define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ |
<> | 139:856d2700e60b | 1035 | #define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ |
<> | 139:856d2700e60b | 1036 | #define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ |
<> | 139:856d2700e60b | 1037 | #define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ |
<> | 139:856d2700e60b | 1038 | #define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ |
<> | 139:856d2700e60b | 1039 | #define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ |
<> | 139:856d2700e60b | 1040 | #define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ |
<> | 139:856d2700e60b | 1041 | #define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ |
<> | 139:856d2700e60b | 1042 | #define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ |
<> | 139:856d2700e60b | 1043 | #define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ |
<> | 139:856d2700e60b | 1044 | #define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ |
<> | 139:856d2700e60b | 1045 | #define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ |
<> | 139:856d2700e60b | 1046 | #define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ |
<> | 139:856d2700e60b | 1047 | #define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ |
<> | 139:856d2700e60b | 1048 | #define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ |
<> | 139:856d2700e60b | 1049 | #define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ |
<> | 139:856d2700e60b | 1050 | #define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ |
<> | 139:856d2700e60b | 1051 | #define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ |
<> | 139:856d2700e60b | 1052 | #define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ |
<> | 139:856d2700e60b | 1053 | #define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ |
<> | 139:856d2700e60b | 1054 | #define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ |
<> | 139:856d2700e60b | 1055 | #define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ |
<> | 139:856d2700e60b | 1056 | #define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ |
<> | 139:856d2700e60b | 1057 | #define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ |
<> | 139:856d2700e60b | 1058 | |
<> | 139:856d2700e60b | 1059 | /* Bit fields for WTIMER ROUTELOC0 */ |
<> | 139:856d2700e60b | 1060 | #define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1061 | #define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1062 | #define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ |
<> | 139:856d2700e60b | 1063 | #define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ |
<> | 139:856d2700e60b | 1064 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1065 | #define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1066 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1067 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1068 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1069 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1070 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1071 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1072 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1073 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1074 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1075 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1076 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1077 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1078 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1079 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1080 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1081 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1082 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1083 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1084 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1085 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1086 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1087 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1088 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1089 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1090 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1091 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1092 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1093 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1094 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1095 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1096 | #define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1097 | #define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1098 | #define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1099 | #define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1100 | #define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1101 | #define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1102 | #define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1103 | #define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1104 | #define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1105 | #define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1106 | #define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1107 | #define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1108 | #define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1109 | #define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1110 | #define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1111 | #define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1112 | #define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1113 | #define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1114 | #define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1115 | #define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1116 | #define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1117 | #define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1118 | #define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1119 | #define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1120 | #define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1121 | #define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1122 | #define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1123 | #define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1124 | #define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1125 | #define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1126 | #define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1127 | #define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1128 | #define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1129 | #define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1130 | #define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ |
<> | 139:856d2700e60b | 1131 | #define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ |
<> | 139:856d2700e60b | 1132 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1133 | #define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1134 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1135 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1136 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1137 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1138 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1139 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1140 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1141 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1142 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1143 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1144 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1145 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1146 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1147 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1148 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1149 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1150 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1151 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1152 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1153 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1154 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1155 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1156 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1157 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1158 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1159 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1160 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1161 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1162 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1163 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1164 | #define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1165 | #define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1166 | #define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1167 | #define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1168 | #define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1169 | #define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1170 | #define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1171 | #define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1172 | #define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1173 | #define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1174 | #define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1175 | #define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1176 | #define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1177 | #define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1178 | #define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1179 | #define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1180 | #define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1181 | #define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1182 | #define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1183 | #define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1184 | #define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1185 | #define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1186 | #define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1187 | #define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1188 | #define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1189 | #define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1190 | #define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1191 | #define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1192 | #define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1193 | #define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1194 | #define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1195 | #define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1196 | #define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1197 | #define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1198 | #define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ |
<> | 139:856d2700e60b | 1199 | #define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ |
<> | 139:856d2700e60b | 1200 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1201 | #define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1202 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1203 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1204 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1205 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1206 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1207 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1208 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1209 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1210 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1211 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1212 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1213 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1214 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1215 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1216 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1217 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1218 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1219 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1220 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1221 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1222 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1223 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1224 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1225 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1226 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1227 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1228 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1229 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1230 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1231 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1232 | #define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1233 | #define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1234 | #define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1235 | #define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1236 | #define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1237 | #define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1238 | #define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1239 | #define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1240 | #define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1241 | #define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1242 | #define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1243 | #define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1244 | #define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1245 | #define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1246 | #define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1247 | #define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1248 | #define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1249 | #define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1250 | #define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1251 | #define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1252 | #define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1253 | #define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1254 | #define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1255 | #define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1256 | #define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1257 | #define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1258 | #define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1259 | #define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1260 | #define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1261 | #define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1262 | #define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1263 | #define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1264 | #define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1265 | #define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1266 | #define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ |
<> | 139:856d2700e60b | 1267 | #define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ |
<> | 139:856d2700e60b | 1268 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1269 | #define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1270 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1271 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1272 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1273 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1274 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1275 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1276 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1277 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1278 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1279 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1280 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1281 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1282 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1283 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1284 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1285 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1286 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1287 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1288 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1289 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1290 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1291 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1292 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1293 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1294 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1295 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1296 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1297 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1298 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1299 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1300 | #define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1301 | #define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1302 | #define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1303 | #define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1304 | #define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1305 | #define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1306 | #define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1307 | #define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1308 | #define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1309 | #define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1310 | #define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1311 | #define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1312 | #define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1313 | #define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1314 | #define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1315 | #define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1316 | #define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1317 | #define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1318 | #define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1319 | #define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1320 | #define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1321 | #define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1322 | #define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1323 | #define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1324 | #define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1325 | #define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1326 | #define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1327 | #define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1328 | #define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1329 | #define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1330 | #define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1331 | #define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1332 | #define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1333 | #define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ |
<> | 139:856d2700e60b | 1334 | |
<> | 139:856d2700e60b | 1335 | /* Bit fields for WTIMER ROUTELOC2 */ |
<> | 139:856d2700e60b | 1336 | #define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1337 | #define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1338 | #define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ |
<> | 139:856d2700e60b | 1339 | #define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ |
<> | 139:856d2700e60b | 1340 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1341 | #define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1342 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1343 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1344 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1345 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1346 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1347 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1348 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1349 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1350 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1351 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1352 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1353 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1354 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1355 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1356 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1357 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1358 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1359 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1360 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1361 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1362 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1363 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1364 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1365 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1366 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1367 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1368 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1369 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1370 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1371 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1372 | #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1373 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1374 | #define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1375 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1376 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1377 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1378 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1379 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1380 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1381 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1382 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1383 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1384 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1385 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1386 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1387 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1388 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1389 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1390 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1391 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1392 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1393 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1394 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1395 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1396 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1397 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1398 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1399 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1400 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1401 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1402 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1403 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1404 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1405 | #define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1406 | #define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ |
<> | 139:856d2700e60b | 1407 | #define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ |
<> | 139:856d2700e60b | 1408 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1409 | #define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1410 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1411 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1412 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1413 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1414 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1415 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1416 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1417 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1418 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1419 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1420 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1421 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1422 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1423 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1424 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1425 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1426 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1427 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1428 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1429 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1430 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1431 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1432 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1433 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1434 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1435 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1436 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1437 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1438 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1439 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1440 | #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1441 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1442 | #define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1443 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1444 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1445 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1446 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1447 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1448 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1449 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1450 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1451 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1452 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1453 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1454 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1455 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1456 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1457 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1458 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1459 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1460 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1461 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1462 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1463 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1464 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1465 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1466 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1467 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1468 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1469 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1470 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1471 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1472 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1473 | #define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1474 | #define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ |
<> | 139:856d2700e60b | 1475 | #define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ |
<> | 139:856d2700e60b | 1476 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1477 | #define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1478 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1479 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1480 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1481 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1482 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1483 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1484 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1485 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1486 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1487 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1488 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1489 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1490 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1491 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1492 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1493 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1494 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1495 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1496 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1497 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1498 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1499 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1500 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1501 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1502 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1503 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1504 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1505 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1506 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1507 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1508 | #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1509 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1510 | #define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1511 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1512 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1513 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1514 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1515 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1516 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1517 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1518 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1519 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1520 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1521 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1522 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1523 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1524 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1525 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1526 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1527 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1528 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1529 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1530 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1531 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1532 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1533 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1534 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1535 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1536 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1537 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1538 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1539 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1540 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1541 | #define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ |
<> | 139:856d2700e60b | 1542 | |
<> | 139:856d2700e60b | 1543 | /* Bit fields for WTIMER CC_CTRL */ |
<> | 139:856d2700e60b | 1544 | #define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1545 | #define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1546 | #define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ |
<> | 139:856d2700e60b | 1547 | #define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ |
<> | 139:856d2700e60b | 1548 | #define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1549 | #define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1550 | #define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1551 | #define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1552 | #define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1553 | #define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1554 | #define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1555 | #define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1556 | #define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1557 | #define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1558 | #define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ |
<> | 139:856d2700e60b | 1559 | #define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ |
<> | 139:856d2700e60b | 1560 | #define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ |
<> | 139:856d2700e60b | 1561 | #define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1562 | #define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1563 | #define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ |
<> | 139:856d2700e60b | 1564 | #define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ |
<> | 139:856d2700e60b | 1565 | #define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ |
<> | 139:856d2700e60b | 1566 | #define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1567 | #define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1568 | #define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ |
<> | 139:856d2700e60b | 1569 | #define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ |
<> | 139:856d2700e60b | 1570 | #define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1571 | #define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1572 | #define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1573 | #define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1574 | #define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1575 | #define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1576 | #define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1577 | #define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1578 | #define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1579 | #define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1580 | #define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ |
<> | 139:856d2700e60b | 1581 | #define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ |
<> | 139:856d2700e60b | 1582 | #define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1583 | #define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1584 | #define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1585 | #define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1586 | #define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1587 | #define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1588 | #define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1589 | #define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1590 | #define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1591 | #define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1592 | #define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ |
<> | 139:856d2700e60b | 1593 | #define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ |
<> | 139:856d2700e60b | 1594 | #define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1595 | #define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1596 | #define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1597 | #define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1598 | #define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1599 | #define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1600 | #define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1601 | #define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1602 | #define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1603 | #define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1604 | #define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ |
<> | 139:856d2700e60b | 1605 | #define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ |
<> | 139:856d2700e60b | 1606 | #define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1607 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1608 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1609 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1610 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1611 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1612 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1613 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1614 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1615 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1616 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1617 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1618 | #define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1619 | #define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1620 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1621 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1622 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1623 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1624 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1625 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1626 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1627 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1628 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1629 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1630 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1631 | #define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1632 | #define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ |
<> | 139:856d2700e60b | 1633 | #define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ |
<> | 139:856d2700e60b | 1634 | #define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1635 | #define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1636 | #define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1637 | #define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1638 | #define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1639 | #define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1640 | #define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1641 | #define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1642 | #define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1643 | #define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1644 | #define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ |
<> | 139:856d2700e60b | 1645 | #define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ |
<> | 139:856d2700e60b | 1646 | #define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1647 | #define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1648 | #define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1649 | #define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1650 | #define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1651 | #define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1652 | #define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1653 | #define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1654 | #define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1655 | #define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1656 | #define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ |
<> | 139:856d2700e60b | 1657 | #define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ |
<> | 139:856d2700e60b | 1658 | #define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ |
<> | 139:856d2700e60b | 1659 | #define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1660 | #define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1661 | #define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1662 | #define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1663 | #define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1664 | #define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1665 | #define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ |
<> | 139:856d2700e60b | 1666 | #define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ |
<> | 139:856d2700e60b | 1667 | #define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ |
<> | 139:856d2700e60b | 1668 | #define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1669 | #define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1670 | #define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1671 | #define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1672 | #define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1673 | #define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1674 | #define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ |
<> | 139:856d2700e60b | 1675 | #define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ |
<> | 139:856d2700e60b | 1676 | #define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ |
<> | 139:856d2700e60b | 1677 | #define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1678 | #define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1679 | #define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1680 | #define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1681 | #define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1682 | #define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ |
<> | 139:856d2700e60b | 1683 | |
<> | 139:856d2700e60b | 1684 | /* Bit fields for WTIMER CC_CCV */ |
<> | 139:856d2700e60b | 1685 | #define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ |
<> | 139:856d2700e60b | 1686 | #define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ |
<> | 139:856d2700e60b | 1687 | #define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ |
<> | 139:856d2700e60b | 1688 | #define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ |
<> | 139:856d2700e60b | 1689 | #define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ |
<> | 139:856d2700e60b | 1690 | #define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ |
<> | 139:856d2700e60b | 1691 | |
<> | 139:856d2700e60b | 1692 | /* Bit fields for WTIMER CC_CCVP */ |
<> | 139:856d2700e60b | 1693 | #define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ |
<> | 139:856d2700e60b | 1694 | #define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ |
<> | 139:856d2700e60b | 1695 | #define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ |
<> | 139:856d2700e60b | 1696 | #define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ |
<> | 139:856d2700e60b | 1697 | #define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ |
<> | 139:856d2700e60b | 1698 | #define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ |
<> | 139:856d2700e60b | 1699 | |
<> | 139:856d2700e60b | 1700 | /* Bit fields for WTIMER CC_CCVB */ |
<> | 139:856d2700e60b | 1701 | #define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ |
<> | 139:856d2700e60b | 1702 | #define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ |
<> | 139:856d2700e60b | 1703 | #define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ |
<> | 139:856d2700e60b | 1704 | #define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ |
<> | 139:856d2700e60b | 1705 | #define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ |
<> | 139:856d2700e60b | 1706 | #define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ |
<> | 139:856d2700e60b | 1707 | |
<> | 139:856d2700e60b | 1708 | /* Bit fields for WTIMER DTCTRL */ |
<> | 139:856d2700e60b | 1709 | #define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1710 | #define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1711 | #define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ |
<> | 139:856d2700e60b | 1712 | #define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ |
<> | 139:856d2700e60b | 1713 | #define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ |
<> | 139:856d2700e60b | 1714 | #define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1715 | #define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1716 | #define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ |
<> | 139:856d2700e60b | 1717 | #define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ |
<> | 139:856d2700e60b | 1718 | #define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ |
<> | 139:856d2700e60b | 1719 | #define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1720 | #define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1721 | #define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1722 | #define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1723 | #define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1724 | #define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1725 | #define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ |
<> | 139:856d2700e60b | 1726 | #define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ |
<> | 139:856d2700e60b | 1727 | #define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ |
<> | 139:856d2700e60b | 1728 | #define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1729 | #define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1730 | #define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */ |
<> | 139:856d2700e60b | 1731 | #define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ |
<> | 139:856d2700e60b | 1732 | #define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ |
<> | 139:856d2700e60b | 1733 | #define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1734 | #define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1735 | #define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ |
<> | 139:856d2700e60b | 1736 | #define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ |
<> | 139:856d2700e60b | 1737 | #define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1738 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1739 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1740 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1741 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1742 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1743 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1744 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1745 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1746 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1747 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1748 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1749 | #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1750 | #define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1751 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1752 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1753 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1754 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1755 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1756 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1757 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1758 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1759 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1760 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1761 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1762 | #define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1763 | #define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ |
<> | 139:856d2700e60b | 1764 | #define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ |
<> | 139:856d2700e60b | 1765 | #define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ |
<> | 139:856d2700e60b | 1766 | #define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1767 | #define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1768 | #define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ |
<> | 139:856d2700e60b | 1769 | #define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ |
<> | 139:856d2700e60b | 1770 | #define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ |
<> | 139:856d2700e60b | 1771 | #define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1772 | #define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1773 | #define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ |
<> | 139:856d2700e60b | 1774 | #define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ |
<> | 139:856d2700e60b | 1775 | #define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ |
<> | 139:856d2700e60b | 1776 | #define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1777 | #define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ |
<> | 139:856d2700e60b | 1778 | |
<> | 139:856d2700e60b | 1779 | /* Bit fields for WTIMER DTTIME */ |
<> | 139:856d2700e60b | 1780 | #define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1781 | #define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1782 | #define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ |
<> | 139:856d2700e60b | 1783 | #define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ |
<> | 139:856d2700e60b | 1784 | #define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1785 | #define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1786 | #define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1787 | #define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1788 | #define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1789 | #define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1790 | #define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1791 | #define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1792 | #define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1793 | #define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1794 | #define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1795 | #define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1796 | #define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1797 | #define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1798 | #define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1799 | #define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1800 | #define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1801 | #define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1802 | #define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1803 | #define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1804 | #define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1805 | #define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1806 | #define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1807 | #define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1808 | #define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ |
<> | 139:856d2700e60b | 1809 | #define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ |
<> | 139:856d2700e60b | 1810 | #define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1811 | #define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1812 | #define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ |
<> | 139:856d2700e60b | 1813 | #define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ |
<> | 139:856d2700e60b | 1814 | #define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1815 | #define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ |
<> | 139:856d2700e60b | 1816 | |
<> | 139:856d2700e60b | 1817 | /* Bit fields for WTIMER DTFC */ |
<> | 139:856d2700e60b | 1818 | #define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1819 | #define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1820 | #define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ |
<> | 139:856d2700e60b | 1821 | #define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ |
<> | 139:856d2700e60b | 1822 | #define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1823 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1824 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1825 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1826 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1827 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1828 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1829 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1830 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1831 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1832 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1833 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1834 | #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1835 | #define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1836 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1837 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1838 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1839 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1840 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1841 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1842 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1843 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1844 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1845 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1846 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1847 | #define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1848 | #define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ |
<> | 139:856d2700e60b | 1849 | #define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ |
<> | 139:856d2700e60b | 1850 | #define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1851 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1852 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1853 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1854 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1855 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1856 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1857 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1858 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1859 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1860 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1861 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1862 | #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1863 | #define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1864 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1865 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1866 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1867 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1868 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1869 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1870 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1871 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1872 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1873 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1874 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1875 | #define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1876 | #define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ |
<> | 139:856d2700e60b | 1877 | #define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ |
<> | 139:856d2700e60b | 1878 | #define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1879 | #define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1880 | #define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1881 | #define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1882 | #define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1883 | #define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1884 | #define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1885 | #define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1886 | #define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1887 | #define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1888 | #define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ |
<> | 139:856d2700e60b | 1889 | #define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ |
<> | 139:856d2700e60b | 1890 | #define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ |
<> | 139:856d2700e60b | 1891 | #define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1892 | #define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1893 | #define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ |
<> | 139:856d2700e60b | 1894 | #define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ |
<> | 139:856d2700e60b | 1895 | #define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ |
<> | 139:856d2700e60b | 1896 | #define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1897 | #define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1898 | #define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ |
<> | 139:856d2700e60b | 1899 | #define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ |
<> | 139:856d2700e60b | 1900 | #define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ |
<> | 139:856d2700e60b | 1901 | #define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1902 | #define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1903 | #define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ |
<> | 139:856d2700e60b | 1904 | #define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ |
<> | 139:856d2700e60b | 1905 | #define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ |
<> | 139:856d2700e60b | 1906 | #define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1907 | #define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ |
<> | 139:856d2700e60b | 1908 | |
<> | 139:856d2700e60b | 1909 | /* Bit fields for WTIMER DTOGEN */ |
<> | 139:856d2700e60b | 1910 | #define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ |
<> | 139:856d2700e60b | 1911 | #define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ |
<> | 139:856d2700e60b | 1912 | #define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ |
<> | 139:856d2700e60b | 1913 | #define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ |
<> | 139:856d2700e60b | 1914 | #define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ |
<> | 139:856d2700e60b | 1915 | #define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ |
<> | 139:856d2700e60b | 1916 | #define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ |
<> | 139:856d2700e60b | 1917 | #define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ |
<> | 139:856d2700e60b | 1918 | #define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ |
<> | 139:856d2700e60b | 1919 | #define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ |
<> | 139:856d2700e60b | 1920 | #define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ |
<> | 139:856d2700e60b | 1921 | #define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ |
<> | 139:856d2700e60b | 1922 | #define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ |
<> | 139:856d2700e60b | 1923 | #define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ |
<> | 139:856d2700e60b | 1924 | #define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ |
<> | 139:856d2700e60b | 1925 | #define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ |
<> | 139:856d2700e60b | 1926 | #define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ |
<> | 139:856d2700e60b | 1927 | #define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ |
<> | 139:856d2700e60b | 1928 | #define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ |
<> | 139:856d2700e60b | 1929 | #define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ |
<> | 139:856d2700e60b | 1930 | #define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ |
<> | 139:856d2700e60b | 1931 | #define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ |
<> | 139:856d2700e60b | 1932 | #define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ |
<> | 139:856d2700e60b | 1933 | #define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ |
<> | 139:856d2700e60b | 1934 | #define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ |
<> | 139:856d2700e60b | 1935 | #define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ |
<> | 139:856d2700e60b | 1936 | #define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ |
<> | 139:856d2700e60b | 1937 | #define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ |
<> | 139:856d2700e60b | 1938 | #define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ |
<> | 139:856d2700e60b | 1939 | #define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ |
<> | 139:856d2700e60b | 1940 | #define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ |
<> | 139:856d2700e60b | 1941 | #define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ |
<> | 139:856d2700e60b | 1942 | |
<> | 139:856d2700e60b | 1943 | /* Bit fields for WTIMER DTFAULT */ |
<> | 139:856d2700e60b | 1944 | #define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ |
<> | 139:856d2700e60b | 1945 | #define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ |
<> | 139:856d2700e60b | 1946 | #define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ |
<> | 139:856d2700e60b | 1947 | #define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ |
<> | 139:856d2700e60b | 1948 | #define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ |
<> | 139:856d2700e60b | 1949 | #define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ |
<> | 139:856d2700e60b | 1950 | #define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ |
<> | 139:856d2700e60b | 1951 | #define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ |
<> | 139:856d2700e60b | 1952 | #define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ |
<> | 139:856d2700e60b | 1953 | #define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ |
<> | 139:856d2700e60b | 1954 | #define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ |
<> | 139:856d2700e60b | 1955 | #define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ |
<> | 139:856d2700e60b | 1956 | #define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ |
<> | 139:856d2700e60b | 1957 | #define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ |
<> | 139:856d2700e60b | 1958 | #define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ |
<> | 139:856d2700e60b | 1959 | #define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ |
<> | 139:856d2700e60b | 1960 | #define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ |
<> | 139:856d2700e60b | 1961 | #define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ |
<> | 139:856d2700e60b | 1962 | #define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ |
<> | 139:856d2700e60b | 1963 | #define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ |
<> | 139:856d2700e60b | 1964 | #define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ |
<> | 139:856d2700e60b | 1965 | #define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ |
<> | 139:856d2700e60b | 1966 | |
<> | 139:856d2700e60b | 1967 | /* Bit fields for WTIMER DTFAULTC */ |
<> | 139:856d2700e60b | 1968 | #define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ |
<> | 139:856d2700e60b | 1969 | #define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ |
<> | 139:856d2700e60b | 1970 | #define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ |
<> | 139:856d2700e60b | 1971 | #define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ |
<> | 139:856d2700e60b | 1972 | #define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ |
<> | 139:856d2700e60b | 1973 | #define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ |
<> | 139:856d2700e60b | 1974 | #define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ |
<> | 139:856d2700e60b | 1975 | #define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ |
<> | 139:856d2700e60b | 1976 | #define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ |
<> | 139:856d2700e60b | 1977 | #define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ |
<> | 139:856d2700e60b | 1978 | #define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ |
<> | 139:856d2700e60b | 1979 | #define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ |
<> | 139:856d2700e60b | 1980 | #define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ |
<> | 139:856d2700e60b | 1981 | #define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ |
<> | 139:856d2700e60b | 1982 | #define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ |
<> | 139:856d2700e60b | 1983 | #define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ |
<> | 139:856d2700e60b | 1984 | #define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ |
<> | 139:856d2700e60b | 1985 | #define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ |
<> | 139:856d2700e60b | 1986 | #define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ |
<> | 139:856d2700e60b | 1987 | #define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ |
<> | 139:856d2700e60b | 1988 | #define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ |
<> | 139:856d2700e60b | 1989 | #define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ |
<> | 139:856d2700e60b | 1990 | |
<> | 139:856d2700e60b | 1991 | /* Bit fields for WTIMER DTLOCK */ |
<> | 139:856d2700e60b | 1992 | #define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ |
<> | 139:856d2700e60b | 1993 | #define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ |
<> | 139:856d2700e60b | 1994 | #define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ |
<> | 139:856d2700e60b | 1995 | #define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ |
<> | 139:856d2700e60b | 1996 | #define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ |
<> | 139:856d2700e60b | 1997 | #define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ |
<> | 139:856d2700e60b | 1998 | #define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ |
<> | 139:856d2700e60b | 1999 | #define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ |
<> | 139:856d2700e60b | 2000 | #define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ |
<> | 139:856d2700e60b | 2001 | #define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ |
<> | 139:856d2700e60b | 2002 | #define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ |
<> | 139:856d2700e60b | 2003 | #define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ |
<> | 139:856d2700e60b | 2004 | #define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ |
<> | 139:856d2700e60b | 2005 | #define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ |
<> | 139:856d2700e60b | 2006 | |
<> | 139:856d2700e60b | 2007 | /** @} End of group EFM32PG12B500F512GL125_WTIMER */ |
<> | 139:856d2700e60b | 2008 | |
<> | 139:856d2700e60b | 2009 | |
<> | 139:856d2700e60b | 2010 | |
<> | 139:856d2700e60b | 2011 | /**************************************************************************//** |
<> | 139:856d2700e60b | 2012 | * @defgroup EFM32PG12B500F512GL125_SYSTICK_BitFields EFM32PG12B500F512GL125_SYSTICK Bit Fields |
<> | 139:856d2700e60b | 2013 | * @{ |
<> | 139:856d2700e60b | 2014 | *****************************************************************************/ |
<> | 139:856d2700e60b | 2015 | |
<> | 139:856d2700e60b | 2016 | /** @} End of group EFM32PG12B500F512GL125_SYSTICK */ |
<> | 139:856d2700e60b | 2017 | |
<> | 139:856d2700e60b | 2018 | |
<> | 139:856d2700e60b | 2019 | |
<> | 139:856d2700e60b | 2020 | /**************************************************************************//** |
<> | 139:856d2700e60b | 2021 | * @defgroup EFM32PG12B500F512GL125_UNLOCK EFM32PG12B500F512GL125 Unlock Codes |
<> | 139:856d2700e60b | 2022 | * @{ |
<> | 139:856d2700e60b | 2023 | *****************************************************************************/ |
<> | 139:856d2700e60b | 2024 | #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ |
<> | 139:856d2700e60b | 2025 | #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ |
<> | 139:856d2700e60b | 2026 | #define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ |
<> | 139:856d2700e60b | 2027 | #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ |
<> | 139:856d2700e60b | 2028 | #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ |
<> | 139:856d2700e60b | 2029 | #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ |
<> | 139:856d2700e60b | 2030 | #define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ |
<> | 139:856d2700e60b | 2031 | |
<> | 139:856d2700e60b | 2032 | /** @} End of group EFM32PG12B500F512GL125_UNLOCK */ |
<> | 139:856d2700e60b | 2033 | |
<> | 139:856d2700e60b | 2034 | /** @} End of group EFM32PG12B500F512GL125_BitFields */ |
<> | 139:856d2700e60b | 2035 | |
<> | 139:856d2700e60b | 2036 | /**************************************************************************//** |
<> | 139:856d2700e60b | 2037 | * @defgroup EFM32PG12B500F512GL125_Alternate_Function EFM32PG12B500F512GL125 Alternate Function |
<> | 139:856d2700e60b | 2038 | * @{ |
<> | 139:856d2700e60b | 2039 | *****************************************************************************/ |
<> | 139:856d2700e60b | 2040 | |
<> | 139:856d2700e60b | 2041 | #include "efm32pg12b_af_ports.h" |
<> | 139:856d2700e60b | 2042 | #include "efm32pg12b_af_pins.h" |
<> | 139:856d2700e60b | 2043 | |
<> | 139:856d2700e60b | 2044 | /** @} End of group EFM32PG12B500F512GL125_Alternate_Function */ |
<> | 139:856d2700e60b | 2045 | |
<> | 139:856d2700e60b | 2046 | /** @} End of group EFM32PG12B500F512GL125 */ |
<> | 139:856d2700e60b | 2047 | |
<> | 139:856d2700e60b | 2048 | /** @} End of group Parts */ |
<> | 139:856d2700e60b | 2049 | |
<> | 139:856d2700e60b | 2050 | #ifdef __cplusplus |
<> | 139:856d2700e60b | 2051 | } |
<> | 139:856d2700e60b | 2052 | #endif |
<> | 139:856d2700e60b | 2053 | #endif /* EFM32PG12B500F512GL125_H */ |