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TARGET_NUCLEO_F334R8/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_spi.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:30:20 2017 +0100
Revision:: 143:86740a56073b
Parent:: 135:176b8275d35d
Child:: 167:84c0a372a020

Release 143 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	135:176b8275d35d	1	/**
<>	135:176b8275d35d	2	******************************************************************************
<>	135:176b8275d35d	3	* @file stm32f3xx_ll_spi.h
<>	135:176b8275d35d	4	* @author MCD Application Team
<>	135:176b8275d35d	5	* @version V1.4.0
<>	135:176b8275d35d	6	* @date 16-December-2016
<>	135:176b8275d35d	7	* @brief Header file of SPI LL module.
<>	135:176b8275d35d	8	******************************************************************************
<>	135:176b8275d35d	9	* @attention
<>	135:176b8275d35d	10	*
<>	135:176b8275d35d	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	135:176b8275d35d	12	*
<>	135:176b8275d35d	13	* Redistribution and use in source and binary forms, with or without modification,
<>	135:176b8275d35d	14	* are permitted provided that the following conditions are met:
<>	135:176b8275d35d	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	135:176b8275d35d	16	* this list of conditions and the following disclaimer.
<>	135:176b8275d35d	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	135:176b8275d35d	18	* this list of conditions and the following disclaimer in the documentation
<>	135:176b8275d35d	19	* and/or other materials provided with the distribution.
<>	135:176b8275d35d	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	135:176b8275d35d	21	* may be used to endorse or promote products derived from this software
<>	135:176b8275d35d	22	* without specific prior written permission.
<>	135:176b8275d35d	23	*
<>	135:176b8275d35d	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	135:176b8275d35d	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	135:176b8275d35d	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	135:176b8275d35d	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	135:176b8275d35d	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	135:176b8275d35d	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	135:176b8275d35d	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	135:176b8275d35d	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	135:176b8275d35d	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	135:176b8275d35d	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	135:176b8275d35d	34	*
<>	135:176b8275d35d	35	******************************************************************************
<>	135:176b8275d35d	36	*/
<>	135:176b8275d35d	37
<>	135:176b8275d35d	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	135:176b8275d35d	39	#ifndef __STM32F3xx_LL_SPI_H
<>	135:176b8275d35d	40	#define __STM32F3xx_LL_SPI_H
<>	135:176b8275d35d	41
<>	135:176b8275d35d	42	#ifdef __cplusplus
<>	135:176b8275d35d	43	extern "C" {
<>	135:176b8275d35d	44	#endif
<>	135:176b8275d35d	45
<>	135:176b8275d35d	46	/* Includes ------------------------------------------------------------------*/
<>	135:176b8275d35d	47	#include "stm32f3xx.h"
<>	135:176b8275d35d	48
<>	135:176b8275d35d	49	/** @addtogroup STM32F3xx_LL_Driver
<>	135:176b8275d35d	50	* @{
<>	135:176b8275d35d	51	*/
<>	135:176b8275d35d	52
<>	135:176b8275d35d	53	#if defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3) \|\| defined (SPI4)
<>	135:176b8275d35d	54
<>	135:176b8275d35d	55	/** @defgroup SPI_LL SPI
<>	135:176b8275d35d	56	* @{
<>	135:176b8275d35d	57	*/
<>	135:176b8275d35d	58
<>	135:176b8275d35d	59	/* Private types -------------------------------------------------------------*/
<>	135:176b8275d35d	60	/* Private variables ---------------------------------------------------------*/
<>	135:176b8275d35d	61	/* Private macros ------------------------------------------------------------*/
<>	135:176b8275d35d	62
<>	135:176b8275d35d	63	/* Exported types ------------------------------------------------------------*/
<>	135:176b8275d35d	64	#if defined(USE_FULL_LL_DRIVER)
<>	135:176b8275d35d	65	/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
<>	135:176b8275d35d	66	* @{
<>	135:176b8275d35d	67	*/
<>	135:176b8275d35d	68
<>	135:176b8275d35d	69	/**
<>	135:176b8275d35d	70	* @brief SPI Init structures definition
<>	135:176b8275d35d	71	*/
<>	135:176b8275d35d	72	typedef struct
<>	135:176b8275d35d	73	{
<>	135:176b8275d35d	74	uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
<>	135:176b8275d35d	75	This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
<>	135:176b8275d35d	76
<>	135:176b8275d35d	77	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
<>	135:176b8275d35d	78
<>	135:176b8275d35d	79	uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
<>	135:176b8275d35d	80	This parameter can be a value of @ref SPI_LL_EC_MODE.
<>	135:176b8275d35d	81
<>	135:176b8275d35d	82	This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
<>	135:176b8275d35d	83
<>	135:176b8275d35d	84	uint32_t DataWidth; /*!< Specifies the SPI data width.
<>	135:176b8275d35d	85	This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
<>	135:176b8275d35d	86
<>	135:176b8275d35d	87	This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
<>	135:176b8275d35d	88
<>	135:176b8275d35d	89	uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
<>	135:176b8275d35d	90	This parameter can be a value of @ref SPI_LL_EC_POLARITY.
<>	135:176b8275d35d	91
<>	135:176b8275d35d	92	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
<>	135:176b8275d35d	93
<>	135:176b8275d35d	94	uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
<>	135:176b8275d35d	95	This parameter can be a value of @ref SPI_LL_EC_PHASE.
<>	135:176b8275d35d	96
<>	135:176b8275d35d	97	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
<>	135:176b8275d35d	98
<>	135:176b8275d35d	99	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
<>	135:176b8275d35d	100	This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
<>	135:176b8275d35d	101
<>	135:176b8275d35d	102	This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
<>	135:176b8275d35d	103
<>	135:176b8275d35d	104	uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
<>	135:176b8275d35d	105	This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
<>	135:176b8275d35d	106	@note The communication clock is derived from the master clock. The slave clock does not need to be set.
<>	135:176b8275d35d	107
<>	135:176b8275d35d	108	This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
<>	135:176b8275d35d	109
<>	135:176b8275d35d	110	uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
<>	135:176b8275d35d	111	This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
<>	135:176b8275d35d	112
<>	135:176b8275d35d	113	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
<>	135:176b8275d35d	114
<>	135:176b8275d35d	115	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
<>	135:176b8275d35d	116	This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
<>	135:176b8275d35d	117
<>	135:176b8275d35d	118	This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
<>	135:176b8275d35d	119
<>	135:176b8275d35d	120	uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
<>	135:176b8275d35d	121	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
<>	135:176b8275d35d	122
<>	135:176b8275d35d	123	This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
<>	135:176b8275d35d	124
<>	135:176b8275d35d	125	} LL_SPI_InitTypeDef;
<>	135:176b8275d35d	126
<>	135:176b8275d35d	127	/**
<>	135:176b8275d35d	128	* @}
<>	135:176b8275d35d	129	*/
<>	135:176b8275d35d	130	#endif /* USE_FULL_LL_DRIVER */
<>	135:176b8275d35d	131
<>	135:176b8275d35d	132	/* Exported constants --------------------------------------------------------*/
<>	135:176b8275d35d	133	/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
<>	135:176b8275d35d	134	* @{
<>	135:176b8275d35d	135	*/
<>	135:176b8275d35d	136
<>	135:176b8275d35d	137	/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
<>	135:176b8275d35d	138	* @brief Flags defines which can be used with LL_SPI_ReadReg function
<>	135:176b8275d35d	139	* @{
<>	135:176b8275d35d	140	*/
<>	135:176b8275d35d	141	#define LL_SPI_SR_RXNE SPI_SR_RXNE /!< Rx buffer not empty flag /
<>	135:176b8275d35d	142	#define LL_SPI_SR_TXE SPI_SR_TXE /!< Tx buffer empty flag /
<>	135:176b8275d35d	143	#define LL_SPI_SR_BSY SPI_SR_BSY /!< Busy flag /
<>	135:176b8275d35d	144	#define LL_SPI_SR_UDR SPI_SR_UDR /!< Underrun flag /
<>	135:176b8275d35d	145	#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /!< CRC error flag /
<>	135:176b8275d35d	146	#define LL_SPI_SR_MODF SPI_SR_MODF /!< Mode fault flag /
<>	135:176b8275d35d	147	#define LL_SPI_SR_OVR SPI_SR_OVR /!< Overrun flag /
<>	135:176b8275d35d	148	#define LL_SPI_SR_FRE SPI_SR_FRE /!< TI mode frame format error flag /
<>	135:176b8275d35d	149	/**
<>	135:176b8275d35d	150	* @}
<>	135:176b8275d35d	151	*/
<>	135:176b8275d35d	152
<>	135:176b8275d35d	153	/** @defgroup SPI_LL_EC_IT IT Defines
<>	135:176b8275d35d	154	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
<>	135:176b8275d35d	155	* @{
<>	135:176b8275d35d	156	*/
<>	135:176b8275d35d	157	#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
<>	135:176b8275d35d	158	#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
<>	135:176b8275d35d	159	#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /!< Error interrupt enable /
<>	135:176b8275d35d	160	/**
<>	135:176b8275d35d	161	* @}
<>	135:176b8275d35d	162	*/
<>	135:176b8275d35d	163
<>	135:176b8275d35d	164	/** @defgroup SPI_LL_EC_MODE Operation Mode
<>	135:176b8275d35d	165	* @{
<>	135:176b8275d35d	166	*/
<>	135:176b8275d35d	167	#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI) /!< Master configuration /
<>	135:176b8275d35d	168	#define LL_SPI_MODE_SLAVE 0x00000000U /!< Slave configuration /
<>	135:176b8275d35d	169	/**
<>	135:176b8275d35d	170	* @}
<>	135:176b8275d35d	171	*/
<>	135:176b8275d35d	172
<>	135:176b8275d35d	173	/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
<>	135:176b8275d35d	174	* @{
<>	135:176b8275d35d	175	*/
<>	135:176b8275d35d	176	#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /!< Motorola mode. Used as default value /
<>	135:176b8275d35d	177	#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /!< TI mode /
<>	135:176b8275d35d	178	/**
<>	135:176b8275d35d	179	* @}
<>	135:176b8275d35d	180	*/
<>	135:176b8275d35d	181
<>	135:176b8275d35d	182	/** @defgroup SPI_LL_EC_PHASE Clock Phase
<>	135:176b8275d35d	183	* @{
<>	135:176b8275d35d	184	*/
<>	135:176b8275d35d	185	#define LL_SPI_PHASE_1EDGE 0x00000000U /!< First clock transition is the first data capture edge /
<>	135:176b8275d35d	186	#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /!< Second clock transition is the first data capture edge /
<>	135:176b8275d35d	187	/**
<>	135:176b8275d35d	188	* @}
<>	135:176b8275d35d	189	*/
<>	135:176b8275d35d	190
<>	135:176b8275d35d	191	/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
<>	135:176b8275d35d	192	* @{
<>	135:176b8275d35d	193	*/
<>	135:176b8275d35d	194	#define LL_SPI_POLARITY_LOW 0x00000000U /!< Clock to 0 when idle /
<>	135:176b8275d35d	195	#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /!< Clock to 1 when idle /
<>	135:176b8275d35d	196	/**
<>	135:176b8275d35d	197	* @}
<>	135:176b8275d35d	198	*/
<>	135:176b8275d35d	199
<>	135:176b8275d35d	200	/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
<>	135:176b8275d35d	201	* @{
<>	135:176b8275d35d	202	*/
<>	135:176b8275d35d	203	#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /!< BaudRate control equal to fPCLK/2 /
<>	135:176b8275d35d	204	#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/4 /
<>	135:176b8275d35d	205	#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/8 /
<>	135:176b8275d35d	206	#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/16 /
<>	135:176b8275d35d	207	#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /!< BaudRate control equal to fPCLK/32 /
<>	135:176b8275d35d	208	#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/64 /
<>	135:176b8275d35d	209	#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 \| SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/128 /
<>	135:176b8275d35d	210	#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 \| SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/256 /
<>	135:176b8275d35d	211	/**
<>	135:176b8275d35d	212	* @}
<>	135:176b8275d35d	213	*/
<>	135:176b8275d35d	214
<>	135:176b8275d35d	215	/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
<>	135:176b8275d35d	216	* @{
<>	135:176b8275d35d	217	*/
<>	135:176b8275d35d	218	#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /!< Data is transmitted/received with the LSB first /
<>	135:176b8275d35d	219	#define LL_SPI_MSB_FIRST 0x00000000U /!< Data is transmitted/received with the MSB first /
<>	135:176b8275d35d	220	/**
<>	135:176b8275d35d	221	* @}
<>	135:176b8275d35d	222	*/
<>	135:176b8275d35d	223
<>	135:176b8275d35d	224	/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
<>	135:176b8275d35d	225	* @{
<>	135:176b8275d35d	226	*/
<>	135:176b8275d35d	227	#define LL_SPI_FULL_DUPLEX 0x00000000U /!< Full-Duplex mode. Rx and Tx transfer on 2 lines /
<>	135:176b8275d35d	228	#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /!< Simplex Rx mode. Rx transfer only on 1 line /
<>	135:176b8275d35d	229	#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /!< Half-Duplex Rx mode. Rx transfer on 1 line /
<>	135:176b8275d35d	230	#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE) /!< Half-Duplex Tx mode. Tx transfer on 1 line /
<>	135:176b8275d35d	231	/**
<>	135:176b8275d35d	232	* @}
<>	135:176b8275d35d	233	*/
<>	135:176b8275d35d	234
<>	135:176b8275d35d	235	/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
<>	135:176b8275d35d	236	* @{
<>	135:176b8275d35d	237	*/
<>	135:176b8275d35d	238	#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /!< NSS managed internally. NSS pin not used and free /
<>	135:176b8275d35d	239	#define LL_SPI_NSS_HARD_INPUT 0x00000000U /!< NSS pin used in Input. Only used in Master mode /
<>	135:176b8275d35d	240	#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /!< NSS pin used in Output. Only used in Slave mode as chip select /
<>	135:176b8275d35d	241	/**
<>	135:176b8275d35d	242	* @}
<>	135:176b8275d35d	243	*/
<>	135:176b8275d35d	244
<>	135:176b8275d35d	245	/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
<>	135:176b8275d35d	246	* @{
<>	135:176b8275d35d	247	*/
<>	135:176b8275d35d	248	#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 4 bits /
<>	135:176b8275d35d	249	#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /!< Data length for SPI transfer: 5 bits /
<>	135:176b8275d35d	250	#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 6 bits /
<>	135:176b8275d35d	251	#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 7 bits /
<>	135:176b8275d35d	252	#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 8 bits /
<>	135:176b8275d35d	253	#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /!< Data length for SPI transfer: 9 bits /
<>	135:176b8275d35d	254	#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 10 bits /
<>	135:176b8275d35d	255	#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 11 bits /
<>	135:176b8275d35d	256	#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 12 bits /
<>	135:176b8275d35d	257	#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2) /!< Data length for SPI transfer: 13 bits /
<>	135:176b8275d35d	258	#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 14 bits /
<>	135:176b8275d35d	259	#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 15 bits /
<>	135:176b8275d35d	260	#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 16 bits /
<>	135:176b8275d35d	261	/**
<>	135:176b8275d35d	262	* @}
<>	135:176b8275d35d	263	*/
<>	135:176b8275d35d	264	#if defined(USE_FULL_LL_DRIVER)
<>	135:176b8275d35d	265
<>	135:176b8275d35d	266	/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
<>	135:176b8275d35d	267	* @{
<>	135:176b8275d35d	268	*/
<>	135:176b8275d35d	269	#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /!< CRC calculation disabled /
<>	135:176b8275d35d	270	#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /!< CRC calculation enabled /
<>	135:176b8275d35d	271	/**
<>	135:176b8275d35d	272	* @}
<>	135:176b8275d35d	273	*/
<>	135:176b8275d35d	274	#endif /* USE_FULL_LL_DRIVER */
<>	135:176b8275d35d	275
<>	135:176b8275d35d	276	/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
<>	135:176b8275d35d	277	* @{
<>	135:176b8275d35d	278	*/
<>	135:176b8275d35d	279	#define LL_SPI_CRC_8BIT 0x00000000U /!< 8-bit CRC length /
<>	135:176b8275d35d	280	#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /!< 16-bit CRC length /
<>	135:176b8275d35d	281	/**
<>	135:176b8275d35d	282	* @}
<>	135:176b8275d35d	283	*/
<>	135:176b8275d35d	284
<>	135:176b8275d35d	285	/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
<>	135:176b8275d35d	286	* @{
<>	135:176b8275d35d	287	*/
<>	135:176b8275d35d	288	#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) /
<>	135:176b8275d35d	289	#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) /
<>	135:176b8275d35d	290	/**
<>	135:176b8275d35d	291	* @}
<>	135:176b8275d35d	292	*/
<>	135:176b8275d35d	293
<>	135:176b8275d35d	294	/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
<>	135:176b8275d35d	295	* @{
<>	135:176b8275d35d	296	*/
<>	135:176b8275d35d	297	#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /!< FIFO reception empty /
<>	135:176b8275d35d	298	#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /!< FIFO reception 1/4 /
<>	135:176b8275d35d	299	#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /!< FIFO reception 1/2 /
<>	135:176b8275d35d	300	#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 \| SPI_SR_FRLVL_0) /!< FIFO reception full /
<>	135:176b8275d35d	301	/**
<>	135:176b8275d35d	302	* @}
<>	135:176b8275d35d	303	*/
<>	135:176b8275d35d	304
<>	135:176b8275d35d	305	/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
<>	135:176b8275d35d	306	* @{
<>	135:176b8275d35d	307	*/
<>	135:176b8275d35d	308	#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /!< FIFO transmission empty /
<>	135:176b8275d35d	309	#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /!< FIFO transmission 1/4 /
<>	135:176b8275d35d	310	#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /!< FIFO transmission 1/2 /
<>	135:176b8275d35d	311	#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 \| SPI_SR_FTLVL_0) /!< FIFO transmission full /
<>	135:176b8275d35d	312	/**
<>	135:176b8275d35d	313	* @}
<>	135:176b8275d35d	314	*/
<>	135:176b8275d35d	315
<>	135:176b8275d35d	316	/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
<>	135:176b8275d35d	317	* @{
<>	135:176b8275d35d	318	*/
<>	135:176b8275d35d	319	#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /!< Select DMA parity Even /
<>	135:176b8275d35d	320	#define LL_SPI_DMA_PARITY_ODD 0x00000001U /!< Select DMA parity Odd /
<>	135:176b8275d35d	321
<>	135:176b8275d35d	322	/**
<>	135:176b8275d35d	323	* @}
<>	135:176b8275d35d	324	*/
<>	135:176b8275d35d	325
<>	135:176b8275d35d	326	/**
<>	135:176b8275d35d	327	* @}
<>	135:176b8275d35d	328	*/
<>	135:176b8275d35d	329
<>	135:176b8275d35d	330	/* Exported macro ------------------------------------------------------------*/
<>	135:176b8275d35d	331	/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
<>	135:176b8275d35d	332	* @{
<>	135:176b8275d35d	333	*/
<>	135:176b8275d35d	334
<>	135:176b8275d35d	335	/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
<>	135:176b8275d35d	336	* @{
<>	135:176b8275d35d	337	*/
<>	135:176b8275d35d	338
<>	135:176b8275d35d	339	/**
<>	135:176b8275d35d	340	* @brief Write a value in SPI register
<>	135:176b8275d35d	341	* @param __INSTANCE__ SPI Instance
<>	135:176b8275d35d	342	* @param __REG__ Register to be written
<>	135:176b8275d35d	343	* @param __VALUE__ Value to be written in the register
<>	135:176b8275d35d	344	* @retval None
<>	135:176b8275d35d	345	*/
<>	135:176b8275d35d	346	#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	135:176b8275d35d	347
<>	135:176b8275d35d	348	/**
<>	135:176b8275d35d	349	* @brief Read a value in SPI register
<>	135:176b8275d35d	350	* @param __INSTANCE__ SPI Instance
<>	135:176b8275d35d	351	* @param __REG__ Register to be read
<>	135:176b8275d35d	352	* @retval Register value
<>	135:176b8275d35d	353	*/
<>	135:176b8275d35d	354	#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	135:176b8275d35d	355	/**
<>	135:176b8275d35d	356	* @}
<>	135:176b8275d35d	357	*/
<>	135:176b8275d35d	358
<>	135:176b8275d35d	359	/**
<>	135:176b8275d35d	360	* @}
<>	135:176b8275d35d	361	*/
<>	135:176b8275d35d	362
<>	135:176b8275d35d	363	/* Exported functions --------------------------------------------------------*/
<>	135:176b8275d35d	364	/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
<>	135:176b8275d35d	365	* @{
<>	135:176b8275d35d	366	*/
<>	135:176b8275d35d	367
<>	135:176b8275d35d	368	/** @defgroup SPI_LL_EF_Configuration Configuration
<>	135:176b8275d35d	369	* @{
<>	135:176b8275d35d	370	*/
<>	135:176b8275d35d	371
<>	135:176b8275d35d	372	/**
<>	135:176b8275d35d	373	* @brief Enable SPI peripheral
<>	135:176b8275d35d	374	* @rmtoll CR1 SPE LL_SPI_Enable
<>	135:176b8275d35d	375	* @param SPIx SPI Instance
<>	135:176b8275d35d	376	* @retval None
<>	135:176b8275d35d	377	*/
<>	135:176b8275d35d	378	__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	379	{
<>	135:176b8275d35d	380	SET_BIT(SPIx->CR1, SPI_CR1_SPE);
<>	135:176b8275d35d	381	}
<>	135:176b8275d35d	382
<>	135:176b8275d35d	383	/**
<>	135:176b8275d35d	384	* @brief Disable SPI peripheral
<>	135:176b8275d35d	385	* @note When disabling the SPI, follow the procedure described in the Reference Manual.
<>	135:176b8275d35d	386	* @rmtoll CR1 SPE LL_SPI_Disable
<>	135:176b8275d35d	387	* @param SPIx SPI Instance
<>	135:176b8275d35d	388	* @retval None
<>	135:176b8275d35d	389	*/
<>	135:176b8275d35d	390	__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	391	{
<>	135:176b8275d35d	392	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
<>	135:176b8275d35d	393	}
<>	135:176b8275d35d	394
<>	135:176b8275d35d	395	/**
<>	135:176b8275d35d	396	* @brief Check if SPI peripheral is enabled
<>	135:176b8275d35d	397	* @rmtoll CR1 SPE LL_SPI_IsEnabled
<>	135:176b8275d35d	398	* @param SPIx SPI Instance
<>	135:176b8275d35d	399	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	400	*/
<>	135:176b8275d35d	401	__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	402	{
<>	135:176b8275d35d	403	return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
<>	135:176b8275d35d	404	}
<>	135:176b8275d35d	405
<>	135:176b8275d35d	406	/**
<>	135:176b8275d35d	407	* @brief Set SPI operation mode to Master or Slave
<>	135:176b8275d35d	408	* @note This bit should not be changed when communication is ongoing.
<>	135:176b8275d35d	409	* @rmtoll CR1 MSTR LL_SPI_SetMode\n
<>	135:176b8275d35d	410	* CR1 SSI LL_SPI_SetMode
<>	135:176b8275d35d	411	* @param SPIx SPI Instance
<>	135:176b8275d35d	412	* @param Mode This parameter can be one of the following values:
<>	135:176b8275d35d	413	* @arg @ref LL_SPI_MODE_MASTER
<>	135:176b8275d35d	414	* @arg @ref LL_SPI_MODE_SLAVE
<>	135:176b8275d35d	415	* @retval None
<>	135:176b8275d35d	416	*/
<>	135:176b8275d35d	417	__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
<>	135:176b8275d35d	418	{
<>	135:176b8275d35d	419	MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI, Mode);
<>	135:176b8275d35d	420	}
<>	135:176b8275d35d	421
<>	135:176b8275d35d	422	/**
<>	135:176b8275d35d	423	* @brief Get SPI operation mode (Master or Slave)
<>	135:176b8275d35d	424	* @rmtoll CR1 MSTR LL_SPI_GetMode\n
<>	135:176b8275d35d	425	* CR1 SSI LL_SPI_GetMode
<>	135:176b8275d35d	426	* @param SPIx SPI Instance
<>	135:176b8275d35d	427	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	428	* @arg @ref LL_SPI_MODE_MASTER
<>	135:176b8275d35d	429	* @arg @ref LL_SPI_MODE_SLAVE
<>	135:176b8275d35d	430	*/
<>	135:176b8275d35d	431	__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	432	{
<>	135:176b8275d35d	433	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI));
<>	135:176b8275d35d	434	}
<>	135:176b8275d35d	435
<>	135:176b8275d35d	436	/**
<>	135:176b8275d35d	437	* @brief Set serial protocol used
<>	135:176b8275d35d	438	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<>	135:176b8275d35d	439	* @rmtoll CR2 FRF LL_SPI_SetStandard
<>	135:176b8275d35d	440	* @param SPIx SPI Instance
<>	135:176b8275d35d	441	* @param Standard This parameter can be one of the following values:
<>	135:176b8275d35d	442	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
<>	135:176b8275d35d	443	* @arg @ref LL_SPI_PROTOCOL_TI
<>	135:176b8275d35d	444	* @retval None
<>	135:176b8275d35d	445	*/
<>	135:176b8275d35d	446	__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
<>	135:176b8275d35d	447	{
<>	135:176b8275d35d	448	MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
<>	135:176b8275d35d	449	}
<>	135:176b8275d35d	450
<>	135:176b8275d35d	451	/**
<>	135:176b8275d35d	452	* @brief Get serial protocol used
<>	135:176b8275d35d	453	* @rmtoll CR2 FRF LL_SPI_GetStandard
<>	135:176b8275d35d	454	* @param SPIx SPI Instance
<>	135:176b8275d35d	455	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	456	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
<>	135:176b8275d35d	457	* @arg @ref LL_SPI_PROTOCOL_TI
<>	135:176b8275d35d	458	*/
<>	135:176b8275d35d	459	__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	460	{
<>	135:176b8275d35d	461	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
<>	135:176b8275d35d	462	}
<>	135:176b8275d35d	463
<>	135:176b8275d35d	464	/**
<>	135:176b8275d35d	465	* @brief Set clock phase
<>	135:176b8275d35d	466	* @note This bit should not be changed when communication is ongoing.
<>	135:176b8275d35d	467	* This bit is not used in SPI TI mode.
<>	135:176b8275d35d	468	* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
<>	135:176b8275d35d	469	* @param SPIx SPI Instance
<>	135:176b8275d35d	470	* @param ClockPhase This parameter can be one of the following values:
<>	135:176b8275d35d	471	* @arg @ref LL_SPI_PHASE_1EDGE
<>	135:176b8275d35d	472	* @arg @ref LL_SPI_PHASE_2EDGE
<>	135:176b8275d35d	473	* @retval None
<>	135:176b8275d35d	474	*/
<>	135:176b8275d35d	475	__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
<>	135:176b8275d35d	476	{
<>	135:176b8275d35d	477	MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
<>	135:176b8275d35d	478	}
<>	135:176b8275d35d	479
<>	135:176b8275d35d	480	/**
<>	135:176b8275d35d	481	* @brief Get clock phase
<>	135:176b8275d35d	482	* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
<>	135:176b8275d35d	483	* @param SPIx SPI Instance
<>	135:176b8275d35d	484	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	485	* @arg @ref LL_SPI_PHASE_1EDGE
<>	135:176b8275d35d	486	* @arg @ref LL_SPI_PHASE_2EDGE
<>	135:176b8275d35d	487	*/
<>	135:176b8275d35d	488	__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	489	{
<>	135:176b8275d35d	490	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
<>	135:176b8275d35d	491	}
<>	135:176b8275d35d	492
<>	135:176b8275d35d	493	/**
<>	135:176b8275d35d	494	* @brief Set clock polarity
<>	135:176b8275d35d	495	* @note This bit should not be changed when communication is ongoing.
<>	135:176b8275d35d	496	* This bit is not used in SPI TI mode.
<>	135:176b8275d35d	497	* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
<>	135:176b8275d35d	498	* @param SPIx SPI Instance
<>	135:176b8275d35d	499	* @param ClockPolarity This parameter can be one of the following values:
<>	135:176b8275d35d	500	* @arg @ref LL_SPI_POLARITY_LOW
<>	135:176b8275d35d	501	* @arg @ref LL_SPI_POLARITY_HIGH
<>	135:176b8275d35d	502	* @retval None
<>	135:176b8275d35d	503	*/
<>	135:176b8275d35d	504	__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
<>	135:176b8275d35d	505	{
<>	135:176b8275d35d	506	MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
<>	135:176b8275d35d	507	}
<>	135:176b8275d35d	508
<>	135:176b8275d35d	509	/**
<>	135:176b8275d35d	510	* @brief Get clock polarity
<>	135:176b8275d35d	511	* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
<>	135:176b8275d35d	512	* @param SPIx SPI Instance
<>	135:176b8275d35d	513	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	514	* @arg @ref LL_SPI_POLARITY_LOW
<>	135:176b8275d35d	515	* @arg @ref LL_SPI_POLARITY_HIGH
<>	135:176b8275d35d	516	*/
<>	135:176b8275d35d	517	__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	518	{
<>	135:176b8275d35d	519	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
<>	135:176b8275d35d	520	}
<>	135:176b8275d35d	521
<>	135:176b8275d35d	522	/**
<>	135:176b8275d35d	523	* @brief Set baud rate prescaler
<>	135:176b8275d35d	524	* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
<>	135:176b8275d35d	525	* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
<>	135:176b8275d35d	526	* @param SPIx SPI Instance
<>	135:176b8275d35d	527	* @param BaudRate This parameter can be one of the following values:
<>	135:176b8275d35d	528	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
<>	135:176b8275d35d	529	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
<>	135:176b8275d35d	530	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
<>	135:176b8275d35d	531	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
<>	135:176b8275d35d	532	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
<>	135:176b8275d35d	533	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
<>	135:176b8275d35d	534	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
<>	135:176b8275d35d	535	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
<>	135:176b8275d35d	536	* @retval None
<>	135:176b8275d35d	537	*/
<>	135:176b8275d35d	538	__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
<>	135:176b8275d35d	539	{
<>	135:176b8275d35d	540	MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
<>	135:176b8275d35d	541	}
<>	135:176b8275d35d	542
<>	135:176b8275d35d	543	/**
<>	135:176b8275d35d	544	* @brief Get baud rate prescaler
<>	135:176b8275d35d	545	* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
<>	135:176b8275d35d	546	* @param SPIx SPI Instance
<>	135:176b8275d35d	547	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	548	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
<>	135:176b8275d35d	549	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
<>	135:176b8275d35d	550	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
<>	135:176b8275d35d	551	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
<>	135:176b8275d35d	552	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
<>	135:176b8275d35d	553	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
<>	135:176b8275d35d	554	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
<>	135:176b8275d35d	555	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
<>	135:176b8275d35d	556	*/
<>	135:176b8275d35d	557	__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	558	{
<>	135:176b8275d35d	559	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
<>	135:176b8275d35d	560	}
<>	135:176b8275d35d	561
<>	135:176b8275d35d	562	/**
<>	135:176b8275d35d	563	* @brief Set transfer bit order
<>	135:176b8275d35d	564	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
<>	135:176b8275d35d	565	* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
<>	135:176b8275d35d	566	* @param SPIx SPI Instance
<>	135:176b8275d35d	567	* @param BitOrder This parameter can be one of the following values:
<>	135:176b8275d35d	568	* @arg @ref LL_SPI_LSB_FIRST
<>	135:176b8275d35d	569	* @arg @ref LL_SPI_MSB_FIRST
<>	135:176b8275d35d	570	* @retval None
<>	135:176b8275d35d	571	*/
<>	135:176b8275d35d	572	__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
<>	135:176b8275d35d	573	{
<>	135:176b8275d35d	574	MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
<>	135:176b8275d35d	575	}
<>	135:176b8275d35d	576
<>	135:176b8275d35d	577	/**
<>	135:176b8275d35d	578	* @brief Get transfer bit order
<>	135:176b8275d35d	579	* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
<>	135:176b8275d35d	580	* @param SPIx SPI Instance
<>	135:176b8275d35d	581	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	582	* @arg @ref LL_SPI_LSB_FIRST
<>	135:176b8275d35d	583	* @arg @ref LL_SPI_MSB_FIRST
<>	135:176b8275d35d	584	*/
<>	135:176b8275d35d	585	__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	586	{
<>	135:176b8275d35d	587	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
<>	135:176b8275d35d	588	}
<>	135:176b8275d35d	589
<>	135:176b8275d35d	590	/**
<>	135:176b8275d35d	591	* @brief Set transfer direction mode
<>	135:176b8275d35d	592	* @note For Half-Duplex mode, Rx Direction is set by default.
<>	135:176b8275d35d	593	* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
<>	135:176b8275d35d	594	* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
<>	135:176b8275d35d	595	* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
<>	135:176b8275d35d	596	* CR1 BIDIOE LL_SPI_SetTransferDirection
<>	135:176b8275d35d	597	* @param SPIx SPI Instance
<>	135:176b8275d35d	598	* @param TransferDirection This parameter can be one of the following values:
<>	135:176b8275d35d	599	* @arg @ref LL_SPI_FULL_DUPLEX
<>	135:176b8275d35d	600	* @arg @ref LL_SPI_SIMPLEX_RX
<>	135:176b8275d35d	601	* @arg @ref LL_SPI_HALF_DUPLEX_RX
<>	135:176b8275d35d	602	* @arg @ref LL_SPI_HALF_DUPLEX_TX
<>	135:176b8275d35d	603	* @retval None
<>	135:176b8275d35d	604	*/
<>	135:176b8275d35d	605	__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
<>	135:176b8275d35d	606	{
<>	135:176b8275d35d	607	MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE, TransferDirection);
<>	135:176b8275d35d	608	}
<>	135:176b8275d35d	609
<>	135:176b8275d35d	610	/**
<>	135:176b8275d35d	611	* @brief Get transfer direction mode
<>	135:176b8275d35d	612	* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
<>	135:176b8275d35d	613	* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
<>	135:176b8275d35d	614	* CR1 BIDIOE LL_SPI_GetTransferDirection
<>	135:176b8275d35d	615	* @param SPIx SPI Instance
<>	135:176b8275d35d	616	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	617	* @arg @ref LL_SPI_FULL_DUPLEX
<>	135:176b8275d35d	618	* @arg @ref LL_SPI_SIMPLEX_RX
<>	135:176b8275d35d	619	* @arg @ref LL_SPI_HALF_DUPLEX_RX
<>	135:176b8275d35d	620	* @arg @ref LL_SPI_HALF_DUPLEX_TX
<>	135:176b8275d35d	621	*/
<>	135:176b8275d35d	622	__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	623	{
<>	135:176b8275d35d	624	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE));
<>	135:176b8275d35d	625	}
<>	135:176b8275d35d	626
<>	135:176b8275d35d	627	/**
<>	135:176b8275d35d	628	* @brief Set frame data width
<>	135:176b8275d35d	629	* @rmtoll CR2 DS LL_SPI_SetDataWidth
<>	135:176b8275d35d	630	* @param SPIx SPI Instance
<>	135:176b8275d35d	631	* @param DataWidth This parameter can be one of the following values:
<>	135:176b8275d35d	632	* @arg @ref LL_SPI_DATAWIDTH_4BIT
<>	135:176b8275d35d	633	* @arg @ref LL_SPI_DATAWIDTH_5BIT
<>	135:176b8275d35d	634	* @arg @ref LL_SPI_DATAWIDTH_6BIT
<>	135:176b8275d35d	635	* @arg @ref LL_SPI_DATAWIDTH_7BIT
<>	135:176b8275d35d	636	* @arg @ref LL_SPI_DATAWIDTH_8BIT
<>	135:176b8275d35d	637	* @arg @ref LL_SPI_DATAWIDTH_9BIT
<>	135:176b8275d35d	638	* @arg @ref LL_SPI_DATAWIDTH_10BIT
<>	135:176b8275d35d	639	* @arg @ref LL_SPI_DATAWIDTH_11BIT
<>	135:176b8275d35d	640	* @arg @ref LL_SPI_DATAWIDTH_12BIT
<>	135:176b8275d35d	641	* @arg @ref LL_SPI_DATAWIDTH_13BIT
<>	135:176b8275d35d	642	* @arg @ref LL_SPI_DATAWIDTH_14BIT
<>	135:176b8275d35d	643	* @arg @ref LL_SPI_DATAWIDTH_15BIT
<>	135:176b8275d35d	644	* @arg @ref LL_SPI_DATAWIDTH_16BIT
<>	135:176b8275d35d	645	* @retval None
<>	135:176b8275d35d	646	*/
<>	135:176b8275d35d	647	__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
<>	135:176b8275d35d	648	{
<>	135:176b8275d35d	649	MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
<>	135:176b8275d35d	650	}
<>	135:176b8275d35d	651
<>	135:176b8275d35d	652	/**
<>	135:176b8275d35d	653	* @brief Get frame data width
<>	135:176b8275d35d	654	* @rmtoll CR2 DS LL_SPI_GetDataWidth
<>	135:176b8275d35d	655	* @param SPIx SPI Instance
<>	135:176b8275d35d	656	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	657	* @arg @ref LL_SPI_DATAWIDTH_4BIT
<>	135:176b8275d35d	658	* @arg @ref LL_SPI_DATAWIDTH_5BIT
<>	135:176b8275d35d	659	* @arg @ref LL_SPI_DATAWIDTH_6BIT
<>	135:176b8275d35d	660	* @arg @ref LL_SPI_DATAWIDTH_7BIT
<>	135:176b8275d35d	661	* @arg @ref LL_SPI_DATAWIDTH_8BIT
<>	135:176b8275d35d	662	* @arg @ref LL_SPI_DATAWIDTH_9BIT
<>	135:176b8275d35d	663	* @arg @ref LL_SPI_DATAWIDTH_10BIT
<>	135:176b8275d35d	664	* @arg @ref LL_SPI_DATAWIDTH_11BIT
<>	135:176b8275d35d	665	* @arg @ref LL_SPI_DATAWIDTH_12BIT
<>	135:176b8275d35d	666	* @arg @ref LL_SPI_DATAWIDTH_13BIT
<>	135:176b8275d35d	667	* @arg @ref LL_SPI_DATAWIDTH_14BIT
<>	135:176b8275d35d	668	* @arg @ref LL_SPI_DATAWIDTH_15BIT
<>	135:176b8275d35d	669	* @arg @ref LL_SPI_DATAWIDTH_16BIT
<>	135:176b8275d35d	670	*/
<>	135:176b8275d35d	671	__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	672	{
<>	135:176b8275d35d	673	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
<>	135:176b8275d35d	674	}
<>	135:176b8275d35d	675
<>	135:176b8275d35d	676	/**
<>	135:176b8275d35d	677	* @brief Set threshold of RXFIFO that triggers an RXNE event
<>	135:176b8275d35d	678	* @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
<>	135:176b8275d35d	679	* @param SPIx SPI Instance
<>	135:176b8275d35d	680	* @param Threshold This parameter can be one of the following values:
<>	135:176b8275d35d	681	* @arg @ref LL_SPI_RX_FIFO_TH_HALF
<>	135:176b8275d35d	682	* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
<>	135:176b8275d35d	683	* @retval None
<>	135:176b8275d35d	684	*/
<>	135:176b8275d35d	685	__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
<>	135:176b8275d35d	686	{
<>	135:176b8275d35d	687	MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
<>	135:176b8275d35d	688	}
<>	135:176b8275d35d	689
<>	135:176b8275d35d	690	/**
<>	135:176b8275d35d	691	* @brief Get threshold of RXFIFO that triggers an RXNE event
<>	135:176b8275d35d	692	* @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
<>	135:176b8275d35d	693	* @param SPIx SPI Instance
<>	135:176b8275d35d	694	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	695	* @arg @ref LL_SPI_RX_FIFO_TH_HALF
<>	135:176b8275d35d	696	* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
<>	135:176b8275d35d	697	*/
<>	135:176b8275d35d	698	__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	699	{
<>	135:176b8275d35d	700	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
<>	135:176b8275d35d	701	}
<>	135:176b8275d35d	702
<>	135:176b8275d35d	703	/**
<>	135:176b8275d35d	704	* @}
<>	135:176b8275d35d	705	*/
<>	135:176b8275d35d	706
<>	135:176b8275d35d	707	/** @defgroup SPI_LL_EF_CRC_Management CRC Management
<>	135:176b8275d35d	708	* @{
<>	135:176b8275d35d	709	*/
<>	135:176b8275d35d	710
<>	135:176b8275d35d	711	/**
<>	135:176b8275d35d	712	* @brief Enable CRC
<>	135:176b8275d35d	713	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<>	135:176b8275d35d	714	* @rmtoll CR1 CRCEN LL_SPI_EnableCRC
<>	135:176b8275d35d	715	* @param SPIx SPI Instance
<>	135:176b8275d35d	716	* @retval None
<>	135:176b8275d35d	717	*/
<>	135:176b8275d35d	718	__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	719	{
<>	135:176b8275d35d	720	SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
<>	135:176b8275d35d	721	}
<>	135:176b8275d35d	722
<>	135:176b8275d35d	723	/**
<>	135:176b8275d35d	724	* @brief Disable CRC
<>	135:176b8275d35d	725	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<>	135:176b8275d35d	726	* @rmtoll CR1 CRCEN LL_SPI_DisableCRC
<>	135:176b8275d35d	727	* @param SPIx SPI Instance
<>	135:176b8275d35d	728	* @retval None
<>	135:176b8275d35d	729	*/
<>	135:176b8275d35d	730	__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	731	{
<>	135:176b8275d35d	732	CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
<>	135:176b8275d35d	733	}
<>	135:176b8275d35d	734
<>	135:176b8275d35d	735	/**
<>	135:176b8275d35d	736	* @brief Check if CRC is enabled
<>	135:176b8275d35d	737	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<>	135:176b8275d35d	738	* @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
<>	135:176b8275d35d	739	* @param SPIx SPI Instance
<>	135:176b8275d35d	740	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	741	*/
<>	135:176b8275d35d	742	__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	743	{
<>	135:176b8275d35d	744	return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
<>	135:176b8275d35d	745	}
<>	135:176b8275d35d	746
<>	135:176b8275d35d	747	/**
<>	135:176b8275d35d	748	* @brief Set CRC Length
<>	135:176b8275d35d	749	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<>	135:176b8275d35d	750	* @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
<>	135:176b8275d35d	751	* @param SPIx SPI Instance
<>	135:176b8275d35d	752	* @param CRCLength This parameter can be one of the following values:
<>	135:176b8275d35d	753	* @arg @ref LL_SPI_CRC_8BIT
<>	135:176b8275d35d	754	* @arg @ref LL_SPI_CRC_16BIT
<>	135:176b8275d35d	755	* @retval None
<>	135:176b8275d35d	756	*/
<>	135:176b8275d35d	757	__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
<>	135:176b8275d35d	758	{
<>	135:176b8275d35d	759	MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
<>	135:176b8275d35d	760	}
<>	135:176b8275d35d	761
<>	135:176b8275d35d	762	/**
<>	135:176b8275d35d	763	* @brief Get CRC Length
<>	135:176b8275d35d	764	* @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
<>	135:176b8275d35d	765	* @param SPIx SPI Instance
<>	135:176b8275d35d	766	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	767	* @arg @ref LL_SPI_CRC_8BIT
<>	135:176b8275d35d	768	* @arg @ref LL_SPI_CRC_16BIT
<>	135:176b8275d35d	769	*/
<>	135:176b8275d35d	770	__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	771	{
<>	135:176b8275d35d	772	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
<>	135:176b8275d35d	773	}
<>	135:176b8275d35d	774
<>	135:176b8275d35d	775	/**
<>	135:176b8275d35d	776	* @brief Set CRCNext to transfer CRC on the line
<>	135:176b8275d35d	777	* @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
<>	135:176b8275d35d	778	* @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
<>	135:176b8275d35d	779	* @param SPIx SPI Instance
<>	135:176b8275d35d	780	* @retval None
<>	135:176b8275d35d	781	*/
<>	135:176b8275d35d	782	__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	783	{
<>	135:176b8275d35d	784	SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
<>	135:176b8275d35d	785	}
<>	135:176b8275d35d	786
<>	135:176b8275d35d	787	/**
<>	135:176b8275d35d	788	* @brief Set polynomial for CRC calculation
<>	135:176b8275d35d	789	* @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
<>	135:176b8275d35d	790	* @param SPIx SPI Instance
<>	135:176b8275d35d	791	* @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<>	135:176b8275d35d	792	* @retval None
<>	135:176b8275d35d	793	*/
<>	135:176b8275d35d	794	__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
<>	135:176b8275d35d	795	{
<>	135:176b8275d35d	796	WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
<>	135:176b8275d35d	797	}
<>	135:176b8275d35d	798
<>	135:176b8275d35d	799	/**
<>	135:176b8275d35d	800	* @brief Get polynomial for CRC calculation
<>	135:176b8275d35d	801	* @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
<>	135:176b8275d35d	802	* @param SPIx SPI Instance
<>	135:176b8275d35d	803	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<>	135:176b8275d35d	804	*/
<>	135:176b8275d35d	805	__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	806	{
<>	135:176b8275d35d	807	return (uint32_t)(READ_REG(SPIx->CRCPR));
<>	135:176b8275d35d	808	}
<>	135:176b8275d35d	809
<>	135:176b8275d35d	810	/**
<>	135:176b8275d35d	811	* @brief Get Rx CRC
<>	135:176b8275d35d	812	* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
<>	135:176b8275d35d	813	* @param SPIx SPI Instance
<>	135:176b8275d35d	814	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<>	135:176b8275d35d	815	*/
<>	135:176b8275d35d	816	__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	817	{
<>	135:176b8275d35d	818	return (uint32_t)(READ_REG(SPIx->RXCRCR));
<>	135:176b8275d35d	819	}
<>	135:176b8275d35d	820
<>	135:176b8275d35d	821	/**
<>	135:176b8275d35d	822	* @brief Get Tx CRC
<>	135:176b8275d35d	823	* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
<>	135:176b8275d35d	824	* @param SPIx SPI Instance
<>	135:176b8275d35d	825	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<>	135:176b8275d35d	826	*/
<>	135:176b8275d35d	827	__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	828	{
<>	135:176b8275d35d	829	return (uint32_t)(READ_REG(SPIx->TXCRCR));
<>	135:176b8275d35d	830	}
<>	135:176b8275d35d	831
<>	135:176b8275d35d	832	/**
<>	135:176b8275d35d	833	* @}
<>	135:176b8275d35d	834	*/
<>	135:176b8275d35d	835
<>	135:176b8275d35d	836	/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
<>	135:176b8275d35d	837	* @{
<>	135:176b8275d35d	838	*/
<>	135:176b8275d35d	839
<>	135:176b8275d35d	840	/**
<>	135:176b8275d35d	841	* @brief Set NSS mode
<>	135:176b8275d35d	842	* @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
<>	135:176b8275d35d	843	* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
<>	135:176b8275d35d	844	* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
<>	135:176b8275d35d	845	* @param SPIx SPI Instance
<>	135:176b8275d35d	846	* @param NSS This parameter can be one of the following values:
<>	135:176b8275d35d	847	* @arg @ref LL_SPI_NSS_SOFT
<>	135:176b8275d35d	848	* @arg @ref LL_SPI_NSS_HARD_INPUT
<>	135:176b8275d35d	849	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
<>	135:176b8275d35d	850	* @retval None
<>	135:176b8275d35d	851	*/
<>	135:176b8275d35d	852	__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
<>	135:176b8275d35d	853	{
<>	135:176b8275d35d	854	MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
<>	135:176b8275d35d	855	MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
<>	135:176b8275d35d	856	}
<>	135:176b8275d35d	857
<>	135:176b8275d35d	858	/**
<>	135:176b8275d35d	859	* @brief Get NSS mode
<>	135:176b8275d35d	860	* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
<>	135:176b8275d35d	861	* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
<>	135:176b8275d35d	862	* @param SPIx SPI Instance
<>	135:176b8275d35d	863	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	864	* @arg @ref LL_SPI_NSS_SOFT
<>	135:176b8275d35d	865	* @arg @ref LL_SPI_NSS_HARD_INPUT
<>	135:176b8275d35d	866	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
<>	135:176b8275d35d	867	*/
<>	135:176b8275d35d	868	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	869	{
<>	135:176b8275d35d	870	register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
<>	135:176b8275d35d	871	register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
<>	135:176b8275d35d	872	return (Ssm \| Ssoe);
<>	135:176b8275d35d	873	}
<>	135:176b8275d35d	874
<>	135:176b8275d35d	875	/**
<>	135:176b8275d35d	876	* @brief Enable NSS pulse management
<>	135:176b8275d35d	877	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
<>	135:176b8275d35d	878	* @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
<>	135:176b8275d35d	879	* @param SPIx SPI Instance
<>	135:176b8275d35d	880	* @retval None
<>	135:176b8275d35d	881	*/
<>	135:176b8275d35d	882	__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	883	{
<>	135:176b8275d35d	884	SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
<>	135:176b8275d35d	885	}
<>	135:176b8275d35d	886
<>	135:176b8275d35d	887	/**
<>	135:176b8275d35d	888	* @brief Disable NSS pulse management
<>	135:176b8275d35d	889	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
<>	135:176b8275d35d	890	* @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
<>	135:176b8275d35d	891	* @param SPIx SPI Instance
<>	135:176b8275d35d	892	* @retval None
<>	135:176b8275d35d	893	*/
<>	135:176b8275d35d	894	__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	895	{
<>	135:176b8275d35d	896	CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
<>	135:176b8275d35d	897	}
<>	135:176b8275d35d	898
<>	135:176b8275d35d	899	/**
<>	135:176b8275d35d	900	* @brief Check if NSS pulse is enabled
<>	135:176b8275d35d	901	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
<>	135:176b8275d35d	902	* @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
<>	135:176b8275d35d	903	* @param SPIx SPI Instance
<>	135:176b8275d35d	904	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	905	*/
<>	135:176b8275d35d	906	__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	907	{
<>	135:176b8275d35d	908	return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP));
<>	135:176b8275d35d	909	}
<>	135:176b8275d35d	910
<>	135:176b8275d35d	911	/**
<>	135:176b8275d35d	912	* @}
<>	135:176b8275d35d	913	*/
<>	135:176b8275d35d	914
<>	135:176b8275d35d	915	/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
<>	135:176b8275d35d	916	* @{
<>	135:176b8275d35d	917	*/
<>	135:176b8275d35d	918
<>	135:176b8275d35d	919	/**
<>	135:176b8275d35d	920	* @brief Check if Rx buffer is not empty
<>	135:176b8275d35d	921	* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
<>	135:176b8275d35d	922	* @param SPIx SPI Instance
<>	135:176b8275d35d	923	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	924	*/
<>	135:176b8275d35d	925	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	926	{
<>	135:176b8275d35d	927	return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
<>	135:176b8275d35d	928	}
<>	135:176b8275d35d	929
<>	135:176b8275d35d	930	/**
<>	135:176b8275d35d	931	* @brief Check if Tx buffer is empty
<>	135:176b8275d35d	932	* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
<>	135:176b8275d35d	933	* @param SPIx SPI Instance
<>	135:176b8275d35d	934	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	935	*/
<>	135:176b8275d35d	936	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	937	{
<>	135:176b8275d35d	938	return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
<>	135:176b8275d35d	939	}
<>	135:176b8275d35d	940
<>	135:176b8275d35d	941	/**
<>	135:176b8275d35d	942	* @brief Get CRC error flag
<>	135:176b8275d35d	943	* @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
<>	135:176b8275d35d	944	* @param SPIx SPI Instance
<>	135:176b8275d35d	945	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	946	*/
<>	135:176b8275d35d	947	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	948	{
<>	135:176b8275d35d	949	return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
<>	135:176b8275d35d	950	}
<>	135:176b8275d35d	951
<>	135:176b8275d35d	952	/**
<>	135:176b8275d35d	953	* @brief Get mode fault error flag
<>	135:176b8275d35d	954	* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
<>	135:176b8275d35d	955	* @param SPIx SPI Instance
<>	135:176b8275d35d	956	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	957	*/
<>	135:176b8275d35d	958	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	959	{
<>	135:176b8275d35d	960	return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
<>	135:176b8275d35d	961	}
<>	135:176b8275d35d	962
<>	135:176b8275d35d	963	/**
<>	135:176b8275d35d	964	* @brief Get overrun error flag
<>	135:176b8275d35d	965	* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
<>	135:176b8275d35d	966	* @param SPIx SPI Instance
<>	135:176b8275d35d	967	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	968	*/
<>	135:176b8275d35d	969	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	970	{
<>	135:176b8275d35d	971	return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
<>	135:176b8275d35d	972	}
<>	135:176b8275d35d	973
<>	135:176b8275d35d	974	/**
<>	135:176b8275d35d	975	* @brief Get busy flag
<>	135:176b8275d35d	976	* @note The BSY flag is cleared under any one of the following conditions:
<>	135:176b8275d35d	977	* -When the SPI is correctly disabled
<>	135:176b8275d35d	978	* -When a fault is detected in Master mode (MODF bit set to 1)
<>	135:176b8275d35d	979	* -In Master mode, when it finishes a data transmission and no new data is ready to be
<>	135:176b8275d35d	980	* sent
<>	135:176b8275d35d	981	* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
<>	135:176b8275d35d	982	* each data transfer.
<>	135:176b8275d35d	983	* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
<>	135:176b8275d35d	984	* @param SPIx SPI Instance
<>	135:176b8275d35d	985	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	986	*/
<>	135:176b8275d35d	987	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	988	{
<>	135:176b8275d35d	989	return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
<>	135:176b8275d35d	990	}
<>	135:176b8275d35d	991
<>	135:176b8275d35d	992	/**
<>	135:176b8275d35d	993	* @brief Get frame format error flag
<>	135:176b8275d35d	994	* @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
<>	135:176b8275d35d	995	* @param SPIx SPI Instance
<>	135:176b8275d35d	996	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	997	*/
<>	135:176b8275d35d	998	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	999	{
<>	135:176b8275d35d	1000	return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
<>	135:176b8275d35d	1001	}
<>	135:176b8275d35d	1002
<>	135:176b8275d35d	1003	/**
<>	135:176b8275d35d	1004	* @brief Get FIFO reception Level
<>	135:176b8275d35d	1005	* @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
<>	135:176b8275d35d	1006	* @param SPIx SPI Instance
<>	135:176b8275d35d	1007	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	1008	* @arg @ref LL_SPI_RX_FIFO_EMPTY
<>	135:176b8275d35d	1009	* @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
<>	135:176b8275d35d	1010	* @arg @ref LL_SPI_RX_FIFO_HALF_FULL
<>	135:176b8275d35d	1011	* @arg @ref LL_SPI_RX_FIFO_FULL
<>	135:176b8275d35d	1012	*/
<>	135:176b8275d35d	1013	__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1014	{
<>	135:176b8275d35d	1015	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
<>	135:176b8275d35d	1016	}
<>	135:176b8275d35d	1017
<>	135:176b8275d35d	1018	/**
<>	135:176b8275d35d	1019	* @brief Get FIFO Transmission Level
<>	135:176b8275d35d	1020	* @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
<>	135:176b8275d35d	1021	* @param SPIx SPI Instance
<>	135:176b8275d35d	1022	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	1023	* @arg @ref LL_SPI_TX_FIFO_EMPTY
<>	135:176b8275d35d	1024	* @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
<>	135:176b8275d35d	1025	* @arg @ref LL_SPI_TX_FIFO_HALF_FULL
<>	135:176b8275d35d	1026	* @arg @ref LL_SPI_TX_FIFO_FULL
<>	135:176b8275d35d	1027	*/
<>	135:176b8275d35d	1028	__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1029	{
<>	135:176b8275d35d	1030	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
<>	135:176b8275d35d	1031	}
<>	135:176b8275d35d	1032
<>	135:176b8275d35d	1033	/**
<>	135:176b8275d35d	1034	* @brief Clear CRC error flag
<>	135:176b8275d35d	1035	* @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
<>	135:176b8275d35d	1036	* @param SPIx SPI Instance
<>	135:176b8275d35d	1037	* @retval None
<>	135:176b8275d35d	1038	*/
<>	135:176b8275d35d	1039	__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1040	{
<>	135:176b8275d35d	1041	CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
<>	135:176b8275d35d	1042	}
<>	135:176b8275d35d	1043
<>	135:176b8275d35d	1044	/**
<>	135:176b8275d35d	1045	* @brief Clear mode fault error flag
<>	135:176b8275d35d	1046	* @note Clearing this flag is done by a read access to the SPIx_SR
<>	135:176b8275d35d	1047	* register followed by a write access to the SPIx_CR1 register
<>	135:176b8275d35d	1048	* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
<>	135:176b8275d35d	1049	* @param SPIx SPI Instance
<>	135:176b8275d35d	1050	* @retval None
<>	135:176b8275d35d	1051	*/
<>	135:176b8275d35d	1052	__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1053	{
<>	135:176b8275d35d	1054	__IO uint32_t tmpreg;
<>	135:176b8275d35d	1055	tmpreg = SPIx->SR;
<>	135:176b8275d35d	1056	(void) tmpreg;
<>	135:176b8275d35d	1057	tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
<>	135:176b8275d35d	1058	(void) tmpreg;
<>	135:176b8275d35d	1059	}
<>	135:176b8275d35d	1060
<>	135:176b8275d35d	1061	/**
<>	135:176b8275d35d	1062	* @brief Clear overrun error flag
<>	135:176b8275d35d	1063	* @note Clearing this flag is done by a read access to the SPIx_DR
<>	135:176b8275d35d	1064	* register followed by a read access to the SPIx_SR register
<>	135:176b8275d35d	1065	* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
<>	135:176b8275d35d	1066	* @param SPIx SPI Instance
<>	135:176b8275d35d	1067	* @retval None
<>	135:176b8275d35d	1068	*/
<>	135:176b8275d35d	1069	__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1070	{
<>	135:176b8275d35d	1071	__IO uint32_t tmpreg;
<>	135:176b8275d35d	1072	tmpreg = SPIx->DR;
<>	135:176b8275d35d	1073	(void) tmpreg;
<>	135:176b8275d35d	1074	tmpreg = SPIx->SR;
<>	135:176b8275d35d	1075	(void) tmpreg;
<>	135:176b8275d35d	1076	}
<>	135:176b8275d35d	1077
<>	135:176b8275d35d	1078	/**
<>	135:176b8275d35d	1079	* @brief Clear frame format error flag
<>	135:176b8275d35d	1080	* @note Clearing this flag is done by reading SPIx_SR register
<>	135:176b8275d35d	1081	* @rmtoll SR FRE LL_SPI_ClearFlag_FRE
<>	135:176b8275d35d	1082	* @param SPIx SPI Instance
<>	135:176b8275d35d	1083	* @retval None
<>	135:176b8275d35d	1084	*/
<>	135:176b8275d35d	1085	__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1086	{
<>	135:176b8275d35d	1087	__IO uint32_t tmpreg;
<>	135:176b8275d35d	1088	tmpreg = SPIx->SR;
<>	135:176b8275d35d	1089	(void) tmpreg;
<>	135:176b8275d35d	1090	}
<>	135:176b8275d35d	1091
<>	135:176b8275d35d	1092	/**
<>	135:176b8275d35d	1093	* @}
<>	135:176b8275d35d	1094	*/
<>	135:176b8275d35d	1095
<>	135:176b8275d35d	1096	/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
<>	135:176b8275d35d	1097	* @{
<>	135:176b8275d35d	1098	*/
<>	135:176b8275d35d	1099
<>	135:176b8275d35d	1100	/**
<>	135:176b8275d35d	1101	* @brief Enable error interrupt
<>	135:176b8275d35d	1102	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
<>	135:176b8275d35d	1103	* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
<>	135:176b8275d35d	1104	* @param SPIx SPI Instance
<>	135:176b8275d35d	1105	* @retval None
<>	135:176b8275d35d	1106	*/
<>	135:176b8275d35d	1107	__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1108	{
<>	135:176b8275d35d	1109	SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
<>	135:176b8275d35d	1110	}
<>	135:176b8275d35d	1111
<>	135:176b8275d35d	1112	/**
<>	135:176b8275d35d	1113	* @brief Enable Rx buffer not empty interrupt
<>	135:176b8275d35d	1114	* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
<>	135:176b8275d35d	1115	* @param SPIx SPI Instance
<>	135:176b8275d35d	1116	* @retval None
<>	135:176b8275d35d	1117	*/
<>	135:176b8275d35d	1118	__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1119	{
<>	135:176b8275d35d	1120	SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
<>	135:176b8275d35d	1121	}
<>	135:176b8275d35d	1122
<>	135:176b8275d35d	1123	/**
<>	135:176b8275d35d	1124	* @brief Enable Tx buffer empty interrupt
<>	135:176b8275d35d	1125	* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
<>	135:176b8275d35d	1126	* @param SPIx SPI Instance
<>	135:176b8275d35d	1127	* @retval None
<>	135:176b8275d35d	1128	*/
<>	135:176b8275d35d	1129	__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1130	{
<>	135:176b8275d35d	1131	SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
<>	135:176b8275d35d	1132	}
<>	135:176b8275d35d	1133
<>	135:176b8275d35d	1134	/**
<>	135:176b8275d35d	1135	* @brief Disable error interrupt
<>	135:176b8275d35d	1136	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
<>	135:176b8275d35d	1137	* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
<>	135:176b8275d35d	1138	* @param SPIx SPI Instance
<>	135:176b8275d35d	1139	* @retval None
<>	135:176b8275d35d	1140	*/
<>	135:176b8275d35d	1141	__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1142	{
<>	135:176b8275d35d	1143	CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
<>	135:176b8275d35d	1144	}
<>	135:176b8275d35d	1145
<>	135:176b8275d35d	1146	/**
<>	135:176b8275d35d	1147	* @brief Disable Rx buffer not empty interrupt
<>	135:176b8275d35d	1148	* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
<>	135:176b8275d35d	1149	* @param SPIx SPI Instance
<>	135:176b8275d35d	1150	* @retval None
<>	135:176b8275d35d	1151	*/
<>	135:176b8275d35d	1152	__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1153	{
<>	135:176b8275d35d	1154	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
<>	135:176b8275d35d	1155	}
<>	135:176b8275d35d	1156
<>	135:176b8275d35d	1157	/**
<>	135:176b8275d35d	1158	* @brief Disable Tx buffer empty interrupt
<>	135:176b8275d35d	1159	* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
<>	135:176b8275d35d	1160	* @param SPIx SPI Instance
<>	135:176b8275d35d	1161	* @retval None
<>	135:176b8275d35d	1162	*/
<>	135:176b8275d35d	1163	__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1164	{
<>	135:176b8275d35d	1165	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
<>	135:176b8275d35d	1166	}
<>	135:176b8275d35d	1167
<>	135:176b8275d35d	1168	/**
<>	135:176b8275d35d	1169	* @brief Check if error interrupt is enabled
<>	135:176b8275d35d	1170	* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
<>	135:176b8275d35d	1171	* @param SPIx SPI Instance
<>	135:176b8275d35d	1172	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1173	*/
<>	135:176b8275d35d	1174	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1175	{
<>	135:176b8275d35d	1176	return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
<>	135:176b8275d35d	1177	}
<>	135:176b8275d35d	1178
<>	135:176b8275d35d	1179	/**
<>	135:176b8275d35d	1180	* @brief Check if Rx buffer not empty interrupt is enabled
<>	135:176b8275d35d	1181	* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
<>	135:176b8275d35d	1182	* @param SPIx SPI Instance
<>	135:176b8275d35d	1183	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1184	*/
<>	135:176b8275d35d	1185	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1186	{
<>	135:176b8275d35d	1187	return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
<>	135:176b8275d35d	1188	}
<>	135:176b8275d35d	1189
<>	135:176b8275d35d	1190	/**
<>	135:176b8275d35d	1191	* @brief Check if Tx buffer empty interrupt
<>	135:176b8275d35d	1192	* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
<>	135:176b8275d35d	1193	* @param SPIx SPI Instance
<>	135:176b8275d35d	1194	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1195	*/
<>	135:176b8275d35d	1196	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1197	{
<>	135:176b8275d35d	1198	return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
<>	135:176b8275d35d	1199	}
<>	135:176b8275d35d	1200
<>	135:176b8275d35d	1201	/**
<>	135:176b8275d35d	1202	* @}
<>	135:176b8275d35d	1203	*/
<>	135:176b8275d35d	1204
<>	135:176b8275d35d	1205	/** @defgroup SPI_LL_EF_DMA_Management DMA Management
<>	135:176b8275d35d	1206	* @{
<>	135:176b8275d35d	1207	*/
<>	135:176b8275d35d	1208
<>	135:176b8275d35d	1209	/**
<>	135:176b8275d35d	1210	* @brief Enable DMA Rx
<>	135:176b8275d35d	1211	* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
<>	135:176b8275d35d	1212	* @param SPIx SPI Instance
<>	135:176b8275d35d	1213	* @retval None
<>	135:176b8275d35d	1214	*/
<>	135:176b8275d35d	1215	__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1216	{
<>	135:176b8275d35d	1217	SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
<>	135:176b8275d35d	1218	}
<>	135:176b8275d35d	1219
<>	135:176b8275d35d	1220	/**
<>	135:176b8275d35d	1221	* @brief Disable DMA Rx
<>	135:176b8275d35d	1222	* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
<>	135:176b8275d35d	1223	* @param SPIx SPI Instance
<>	135:176b8275d35d	1224	* @retval None
<>	135:176b8275d35d	1225	*/
<>	135:176b8275d35d	1226	__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1227	{
<>	135:176b8275d35d	1228	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
<>	135:176b8275d35d	1229	}
<>	135:176b8275d35d	1230
<>	135:176b8275d35d	1231	/**
<>	135:176b8275d35d	1232	* @brief Check if DMA Rx is enabled
<>	135:176b8275d35d	1233	* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
<>	135:176b8275d35d	1234	* @param SPIx SPI Instance
<>	135:176b8275d35d	1235	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1236	*/
<>	135:176b8275d35d	1237	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1238	{
<>	135:176b8275d35d	1239	return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
<>	135:176b8275d35d	1240	}
<>	135:176b8275d35d	1241
<>	135:176b8275d35d	1242	/**
<>	135:176b8275d35d	1243	* @brief Enable DMA Tx
<>	135:176b8275d35d	1244	* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
<>	135:176b8275d35d	1245	* @param SPIx SPI Instance
<>	135:176b8275d35d	1246	* @retval None
<>	135:176b8275d35d	1247	*/
<>	135:176b8275d35d	1248	__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1249	{
<>	135:176b8275d35d	1250	SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
<>	135:176b8275d35d	1251	}
<>	135:176b8275d35d	1252
<>	135:176b8275d35d	1253	/**
<>	135:176b8275d35d	1254	* @brief Disable DMA Tx
<>	135:176b8275d35d	1255	* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
<>	135:176b8275d35d	1256	* @param SPIx SPI Instance
<>	135:176b8275d35d	1257	* @retval None
<>	135:176b8275d35d	1258	*/
<>	135:176b8275d35d	1259	__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1260	{
<>	135:176b8275d35d	1261	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
<>	135:176b8275d35d	1262	}
<>	135:176b8275d35d	1263
<>	135:176b8275d35d	1264	/**
<>	135:176b8275d35d	1265	* @brief Check if DMA Tx is enabled
<>	135:176b8275d35d	1266	* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
<>	135:176b8275d35d	1267	* @param SPIx SPI Instance
<>	135:176b8275d35d	1268	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1269	*/
<>	135:176b8275d35d	1270	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1271	{
<>	135:176b8275d35d	1272	return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
<>	135:176b8275d35d	1273	}
<>	135:176b8275d35d	1274
<>	135:176b8275d35d	1275	/**
<>	135:176b8275d35d	1276	* @brief Set parity of Last DMA reception
<>	135:176b8275d35d	1277	* @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
<>	135:176b8275d35d	1278	* @param SPIx SPI Instance
<>	135:176b8275d35d	1279	* @param Parity This parameter can be one of the following values:
<>	135:176b8275d35d	1280	* @arg @ref LL_SPI_DMA_PARITY_ODD
<>	135:176b8275d35d	1281	* @arg @ref LL_SPI_DMA_PARITY_EVEN
<>	135:176b8275d35d	1282	* @retval None
<>	135:176b8275d35d	1283	*/
<>	135:176b8275d35d	1284	__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
<>	135:176b8275d35d	1285	{
<>	135:176b8275d35d	1286	MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << POSITION_VAL(SPI_CR2_LDMARX)));
<>	135:176b8275d35d	1287	}
<>	135:176b8275d35d	1288
<>	135:176b8275d35d	1289	/**
<>	135:176b8275d35d	1290	* @brief Get parity configuration for Last DMA reception
<>	135:176b8275d35d	1291	* @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
<>	135:176b8275d35d	1292	* @param SPIx SPI Instance
<>	135:176b8275d35d	1293	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	1294	* @arg @ref LL_SPI_DMA_PARITY_ODD
<>	135:176b8275d35d	1295	* @arg @ref LL_SPI_DMA_PARITY_EVEN
<>	135:176b8275d35d	1296	*/
<>	135:176b8275d35d	1297	__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1298	{
<>	135:176b8275d35d	1299	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> POSITION_VAL(SPI_CR2_LDMARX));
<>	135:176b8275d35d	1300	}
<>	135:176b8275d35d	1301
<>	135:176b8275d35d	1302	/**
<>	135:176b8275d35d	1303	* @brief Set parity of Last DMA transmission
<>	135:176b8275d35d	1304	* @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
<>	135:176b8275d35d	1305	* @param SPIx SPI Instance
<>	135:176b8275d35d	1306	* @param Parity This parameter can be one of the following values:
<>	135:176b8275d35d	1307	* @arg @ref LL_SPI_DMA_PARITY_ODD
<>	135:176b8275d35d	1308	* @arg @ref LL_SPI_DMA_PARITY_EVEN
<>	135:176b8275d35d	1309	* @retval None
<>	135:176b8275d35d	1310	*/
<>	135:176b8275d35d	1311	__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
<>	135:176b8275d35d	1312	{
<>	135:176b8275d35d	1313	MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << POSITION_VAL(SPI_CR2_LDMATX)));
<>	135:176b8275d35d	1314	}
<>	135:176b8275d35d	1315
<>	135:176b8275d35d	1316	/**
<>	135:176b8275d35d	1317	* @brief Get parity configuration for Last DMA transmission
<>	135:176b8275d35d	1318	* @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
<>	135:176b8275d35d	1319	* @param SPIx SPI Instance
<>	135:176b8275d35d	1320	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	1321	* @arg @ref LL_SPI_DMA_PARITY_ODD
<>	135:176b8275d35d	1322	* @arg @ref LL_SPI_DMA_PARITY_EVEN
<>	135:176b8275d35d	1323	*/
<>	135:176b8275d35d	1324	__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1325	{
<>	135:176b8275d35d	1326	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> POSITION_VAL(SPI_CR2_LDMATX));
<>	135:176b8275d35d	1327	}
<>	135:176b8275d35d	1328
<>	135:176b8275d35d	1329	/**
<>	135:176b8275d35d	1330	* @brief Get the data register address used for DMA transfer
<>	135:176b8275d35d	1331	* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
<>	135:176b8275d35d	1332	* @param SPIx SPI Instance
<>	135:176b8275d35d	1333	* @retval Address of data register
<>	135:176b8275d35d	1334	*/
<>	135:176b8275d35d	1335	__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1336	{
<>	135:176b8275d35d	1337	return (uint32_t) & (SPIx->DR);
<>	135:176b8275d35d	1338	}
<>	135:176b8275d35d	1339
<>	135:176b8275d35d	1340	/**
<>	135:176b8275d35d	1341	* @}
<>	135:176b8275d35d	1342	*/
<>	135:176b8275d35d	1343
<>	135:176b8275d35d	1344	/** @defgroup SPI_LL_EF_DATA_Management DATA Management
<>	135:176b8275d35d	1345	* @{
<>	135:176b8275d35d	1346	*/
<>	135:176b8275d35d	1347
<>	135:176b8275d35d	1348	/**
<>	135:176b8275d35d	1349	* @brief Read 8-Bits in the data register
<>	135:176b8275d35d	1350	* @rmtoll DR DR LL_SPI_ReceiveData8
<>	135:176b8275d35d	1351	* @param SPIx SPI Instance
<>	135:176b8275d35d	1352	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
<>	135:176b8275d35d	1353	*/
<>	135:176b8275d35d	1354	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1355	{
<>	135:176b8275d35d	1356	return (uint8_t)(READ_REG(SPIx->DR));
<>	135:176b8275d35d	1357	}
<>	135:176b8275d35d	1358
<>	135:176b8275d35d	1359	/**
<>	135:176b8275d35d	1360	* @brief Read 16-Bits in the data register
<>	135:176b8275d35d	1361	* @rmtoll DR DR LL_SPI_ReceiveData16
<>	135:176b8275d35d	1362	* @param SPIx SPI Instance
<>	135:176b8275d35d	1363	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
<>	135:176b8275d35d	1364	*/
<>	135:176b8275d35d	1365	__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1366	{
<>	135:176b8275d35d	1367	return (uint16_t)(READ_REG(SPIx->DR));
<>	135:176b8275d35d	1368	}
<>	135:176b8275d35d	1369
<>	135:176b8275d35d	1370	/**
<>	135:176b8275d35d	1371	* @brief Write 8-Bits in the data register
<>	135:176b8275d35d	1372	* @rmtoll DR DR LL_SPI_TransmitData8
<>	135:176b8275d35d	1373	* @param SPIx SPI Instance
<>	135:176b8275d35d	1374	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
<>	135:176b8275d35d	1375	* @retval None
<>	135:176b8275d35d	1376	*/
<>	135:176b8275d35d	1377	__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
<>	135:176b8275d35d	1378	{
<>	135:176b8275d35d	1379	((__IO uint8_t )&SPIx->DR) = TxData;
<>	135:176b8275d35d	1380	}
<>	135:176b8275d35d	1381
<>	135:176b8275d35d	1382	/**
<>	135:176b8275d35d	1383	* @brief Write 16-Bits in the data register
<>	135:176b8275d35d	1384	* @rmtoll DR DR LL_SPI_TransmitData16
<>	135:176b8275d35d	1385	* @param SPIx SPI Instance
<>	135:176b8275d35d	1386	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
<>	135:176b8275d35d	1387	* @retval None
<>	135:176b8275d35d	1388	*/
<>	135:176b8275d35d	1389	__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
<>	135:176b8275d35d	1390	{
<>	135:176b8275d35d	1391	((__IO uint16_t )&SPIx->DR) = TxData;
<>	135:176b8275d35d	1392	}
<>	135:176b8275d35d	1393
<>	135:176b8275d35d	1394	/**
<>	135:176b8275d35d	1395	* @}
<>	135:176b8275d35d	1396	*/
<>	135:176b8275d35d	1397	#if defined(USE_FULL_LL_DRIVER)
<>	135:176b8275d35d	1398	/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
<>	135:176b8275d35d	1399	* @{
<>	135:176b8275d35d	1400	*/
<>	135:176b8275d35d	1401
<>	135:176b8275d35d	1402	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
<>	135:176b8275d35d	1403	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct);
<>	135:176b8275d35d	1404	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
<>	135:176b8275d35d	1405
<>	135:176b8275d35d	1406	/**
<>	135:176b8275d35d	1407	* @}
<>	135:176b8275d35d	1408	*/
<>	135:176b8275d35d	1409	#endif /* USE_FULL_LL_DRIVER */
<>	135:176b8275d35d	1410	/**
<>	135:176b8275d35d	1411	* @}
<>	135:176b8275d35d	1412	*/
<>	135:176b8275d35d	1413
<>	135:176b8275d35d	1414	/**
<>	135:176b8275d35d	1415	* @}
<>	135:176b8275d35d	1416	*/
<>	135:176b8275d35d	1417
<>	135:176b8275d35d	1418	#if defined(SPI_I2S_SUPPORT)
<>	135:176b8275d35d	1419	/** @defgroup I2S_LL I2S
<>	135:176b8275d35d	1420	* @{
<>	135:176b8275d35d	1421	*/
<>	135:176b8275d35d	1422
<>	135:176b8275d35d	1423	/* Private variables ---------------------------------------------------------*/
<>	135:176b8275d35d	1424	/* Private constants ---------------------------------------------------------*/
<>	135:176b8275d35d	1425	/* Private macros ------------------------------------------------------------*/
<>	135:176b8275d35d	1426
<>	135:176b8275d35d	1427	/* Exported types ------------------------------------------------------------*/
<>	135:176b8275d35d	1428	#if defined(USE_FULL_LL_DRIVER)
<>	135:176b8275d35d	1429	/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
<>	135:176b8275d35d	1430	* @{
<>	135:176b8275d35d	1431	*/
<>	135:176b8275d35d	1432
<>	135:176b8275d35d	1433	/**
<>	135:176b8275d35d	1434	* @brief I2S Init structure definition
<>	135:176b8275d35d	1435	*/
<>	135:176b8275d35d	1436
<>	135:176b8275d35d	1437	typedef struct
<>	135:176b8275d35d	1438	{
<>	135:176b8275d35d	1439	uint32_t Mode; /*!< Specifies the I2S operating mode.
<>	135:176b8275d35d	1440	This parameter can be a value of @ref I2S_LL_EC_MODE
<>	135:176b8275d35d	1441
<>	135:176b8275d35d	1442	This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
<>	135:176b8275d35d	1443
<>	135:176b8275d35d	1444	uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
<>	135:176b8275d35d	1445	This parameter can be a value of @ref I2S_LL_EC_STANDARD
<>	135:176b8275d35d	1446
<>	135:176b8275d35d	1447	This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
<>	135:176b8275d35d	1448
<>	135:176b8275d35d	1449
<>	135:176b8275d35d	1450	uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
<>	135:176b8275d35d	1451	This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
<>	135:176b8275d35d	1452
<>	135:176b8275d35d	1453	This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
<>	135:176b8275d35d	1454
<>	135:176b8275d35d	1455
<>	135:176b8275d35d	1456	uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
<>	135:176b8275d35d	1457	This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
<>	135:176b8275d35d	1458
<>	135:176b8275d35d	1459	This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
<>	135:176b8275d35d	1460
<>	135:176b8275d35d	1461
<>	135:176b8275d35d	1462	uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
<>	135:176b8275d35d	1463	This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
<>	135:176b8275d35d	1464
<>	135:176b8275d35d	1465	Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
<>	135:176b8275d35d	1466	and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
<>	135:176b8275d35d	1467
<>	135:176b8275d35d	1468
<>	135:176b8275d35d	1469	uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
<>	135:176b8275d35d	1470	This parameter can be a value of @ref I2S_LL_EC_POLARITY
<>	135:176b8275d35d	1471
<>	135:176b8275d35d	1472	This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
<>	135:176b8275d35d	1473
<>	135:176b8275d35d	1474	} LL_I2S_InitTypeDef;
<>	135:176b8275d35d	1475
<>	135:176b8275d35d	1476	/**
<>	135:176b8275d35d	1477	* @}
<>	135:176b8275d35d	1478	*/
<>	135:176b8275d35d	1479	#endif /USE_FULL_LL_DRIVER/
<>	135:176b8275d35d	1480
<>	135:176b8275d35d	1481	/* Exported constants --------------------------------------------------------*/
<>	135:176b8275d35d	1482	/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
<>	135:176b8275d35d	1483	* @{
<>	135:176b8275d35d	1484	*/
<>	135:176b8275d35d	1485
<>	135:176b8275d35d	1486	/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
<>	135:176b8275d35d	1487	* @brief Flags defines which can be used with LL_I2S_ReadReg function
<>	135:176b8275d35d	1488	* @{
<>	135:176b8275d35d	1489	*/
<>	135:176b8275d35d	1490	#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /!< Rx buffer not empty flag /
<>	135:176b8275d35d	1491	#define LL_I2S_SR_TXE LL_SPI_SR_TXE /!< Tx buffer empty flag /
<>	135:176b8275d35d	1492	#define LL_I2S_SR_BSY LL_SPI_SR_BSY /!< Busy flag /
<>	135:176b8275d35d	1493	#define LL_I2S_SR_UDR LL_SPI_SR_UDR /!< Underrun flag /
<>	135:176b8275d35d	1494	#define LL_I2S_SR_OVR LL_SPI_SR_OVR /!< Overrun flag /
<>	135:176b8275d35d	1495	#define LL_I2S_SR_FRE LL_SPI_SR_FRE /!< TI mode frame format error flag /
<>	135:176b8275d35d	1496	/**
<>	135:176b8275d35d	1497	* @}
<>	135:176b8275d35d	1498	*/
<>	135:176b8275d35d	1499
<>	135:176b8275d35d	1500	/** @defgroup SPI_LL_EC_IT IT Defines
<>	135:176b8275d35d	1501	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
<>	135:176b8275d35d	1502	* @{
<>	135:176b8275d35d	1503	*/
<>	135:176b8275d35d	1504	#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
<>	135:176b8275d35d	1505	#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
<>	135:176b8275d35d	1506	#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /!< Error interrupt enable /
<>	135:176b8275d35d	1507	/**
<>	135:176b8275d35d	1508	* @}
<>	135:176b8275d35d	1509	*/
<>	135:176b8275d35d	1510
<>	135:176b8275d35d	1511	/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
<>	135:176b8275d35d	1512	* @{
<>	135:176b8275d35d	1513	*/
<>	135:176b8275d35d	1514	#define LL_I2S_DATAFORMAT_16B 0x00000000U /!< Data length 16 bits, Channel lenght 16bit /
<>	135:176b8275d35d	1515	#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /!< Data length 16 bits, Channel lenght 32bit /
<>	135:176b8275d35d	1516	#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_0) /!< Data length 24 bits, Channel lenght 32bit /
<>	135:176b8275d35d	1517	#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_1) /!< Data length 16 bits, Channel lenght 32bit /
<>	135:176b8275d35d	1518	/**
<>	135:176b8275d35d	1519	* @}
<>	135:176b8275d35d	1520	*/
<>	135:176b8275d35d	1521
<>	135:176b8275d35d	1522	/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
<>	135:176b8275d35d	1523	* @{
<>	135:176b8275d35d	1524	*/
<>	135:176b8275d35d	1525	#define LL_I2S_POLARITY_LOW 0x00000000U /!< Clock steady state is low level /
<>	135:176b8275d35d	1526	#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /!< Clock steady state is high level /
<>	135:176b8275d35d	1527	/**
<>	135:176b8275d35d	1528	* @}
<>	135:176b8275d35d	1529	*/
<>	135:176b8275d35d	1530
<>	135:176b8275d35d	1531	/** @defgroup I2S_LL_EC_STANDARD I2s Standard
<>	135:176b8275d35d	1532	* @{
<>	135:176b8275d35d	1533	*/
<>	135:176b8275d35d	1534	#define LL_I2S_STANDARD_PHILIPS 0x00000000U /!< I2S standard philips /
<>	135:176b8275d35d	1535	#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /!< MSB justified standard (left justified) /
<>	135:176b8275d35d	1536	#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /!< LSB justified standard (right justified) /
<>	135:176b8275d35d	1537	#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1) /!< PCM standard, short frame synchronization /
<>	135:176b8275d35d	1538	#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1 \| SPI_I2SCFGR_PCMSYNC) /!< PCM standard, long frame synchronization /
<>	135:176b8275d35d	1539	/**
<>	135:176b8275d35d	1540	* @}
<>	135:176b8275d35d	1541	*/
<>	135:176b8275d35d	1542
<>	135:176b8275d35d	1543	/** @defgroup I2S_LL_EC_MODE Operation Mode
<>	135:176b8275d35d	1544	* @{
<>	135:176b8275d35d	1545	*/
<>	135:176b8275d35d	1546	#define LL_I2S_MODE_SLAVE_TX 0x00000000U /!< Slave Tx configuration /
<>	135:176b8275d35d	1547	#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /!< Slave Rx configuration /
<>	135:176b8275d35d	1548	#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /!< Master Tx configuration /
<>	135:176b8275d35d	1549	#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 \| SPI_I2SCFGR_I2SCFG_1) /!< Master Rx configuration /
<>	135:176b8275d35d	1550	/**
<>	135:176b8275d35d	1551	* @}
<>	135:176b8275d35d	1552	*/
<>	135:176b8275d35d	1553
<>	135:176b8275d35d	1554	/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
<>	135:176b8275d35d	1555	* @{
<>	135:176b8275d35d	1556	*/
<>	135:176b8275d35d	1557	#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /!< Odd factor: Real divider value is = I2SDIV 2 */
<>	135:176b8275d35d	1558	#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /!< Odd factor: Real divider value is = (I2SDIV 2)+1 */
<>	135:176b8275d35d	1559	/**
<>	135:176b8275d35d	1560	* @}
<>	135:176b8275d35d	1561	*/
<>	135:176b8275d35d	1562
<>	135:176b8275d35d	1563	#if defined(USE_FULL_LL_DRIVER)
<>	135:176b8275d35d	1564
<>	135:176b8275d35d	1565	/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
<>	135:176b8275d35d	1566	* @{
<>	135:176b8275d35d	1567	*/
<>	135:176b8275d35d	1568	#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /!< Master clock output is disabled /
<>	135:176b8275d35d	1569	#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /!< Master clock output is enabled /
<>	135:176b8275d35d	1570	/**
<>	135:176b8275d35d	1571	* @}
<>	135:176b8275d35d	1572	*/
<>	135:176b8275d35d	1573
<>	135:176b8275d35d	1574	/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
<>	135:176b8275d35d	1575	* @{
<>	135:176b8275d35d	1576	*/
<>	135:176b8275d35d	1577
<>	135:176b8275d35d	1578	#define LL_I2S_AUDIOFREQ_192K 192000U /!< Audio Frequency configuration 192000 Hz /
<>	135:176b8275d35d	1579	#define LL_I2S_AUDIOFREQ_96K 96000U /!< Audio Frequency configuration 96000 Hz /
<>	135:176b8275d35d	1580	#define LL_I2S_AUDIOFREQ_48K 48000U /!< Audio Frequency configuration 48000 Hz /
<>	135:176b8275d35d	1581	#define LL_I2S_AUDIOFREQ_44K 44100U /!< Audio Frequency configuration 44100 Hz /
<>	135:176b8275d35d	1582	#define LL_I2S_AUDIOFREQ_32K 32000U /!< Audio Frequency configuration 32000 Hz /
<>	135:176b8275d35d	1583	#define LL_I2S_AUDIOFREQ_22K 22050U /!< Audio Frequency configuration 22050 Hz /
<>	135:176b8275d35d	1584	#define LL_I2S_AUDIOFREQ_16K 16000U /!< Audio Frequency configuration 16000 Hz /
<>	135:176b8275d35d	1585	#define LL_I2S_AUDIOFREQ_11K 11025U /!< Audio Frequency configuration 11025 Hz /
<>	135:176b8275d35d	1586	#define LL_I2S_AUDIOFREQ_8K 8000U /!< Audio Frequency configuration 8000 Hz /
<>	135:176b8275d35d	1587	#define LL_I2S_AUDIOFREQ_DEFAULT 2U /!< Audio Freq not specified. Register I2SDIV = 2 /
<>	135:176b8275d35d	1588	/**
<>	135:176b8275d35d	1589	* @}
<>	135:176b8275d35d	1590	*/
<>	135:176b8275d35d	1591	#endif /* USE_FULL_LL_DRIVER */
<>	135:176b8275d35d	1592
<>	135:176b8275d35d	1593	/**
<>	135:176b8275d35d	1594	* @}
<>	135:176b8275d35d	1595	*/
<>	135:176b8275d35d	1596
<>	135:176b8275d35d	1597	/* Exported macro ------------------------------------------------------------*/
<>	135:176b8275d35d	1598	/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
<>	135:176b8275d35d	1599	* @{
<>	135:176b8275d35d	1600	*/
<>	135:176b8275d35d	1601
<>	135:176b8275d35d	1602	/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
<>	135:176b8275d35d	1603	* @{
<>	135:176b8275d35d	1604	*/
<>	135:176b8275d35d	1605
<>	135:176b8275d35d	1606	/**
<>	135:176b8275d35d	1607	* @brief Write a value in I2S register
<>	135:176b8275d35d	1608	* @param __INSTANCE__ I2S Instance
<>	135:176b8275d35d	1609	* @param __REG__ Register to be written
<>	135:176b8275d35d	1610	* @param __VALUE__ Value to be written in the register
<>	135:176b8275d35d	1611	* @retval None
<>	135:176b8275d35d	1612	*/
<>	135:176b8275d35d	1613	#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	135:176b8275d35d	1614
<>	135:176b8275d35d	1615	/**
<>	135:176b8275d35d	1616	* @brief Read a value in I2S register
<>	135:176b8275d35d	1617	* @param __INSTANCE__ I2S Instance
<>	135:176b8275d35d	1618	* @param __REG__ Register to be read
<>	135:176b8275d35d	1619	* @retval Register value
<>	135:176b8275d35d	1620	*/
<>	135:176b8275d35d	1621	#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	135:176b8275d35d	1622	/**
<>	135:176b8275d35d	1623	* @}
<>	135:176b8275d35d	1624	*/
<>	135:176b8275d35d	1625
<>	135:176b8275d35d	1626	/**
<>	135:176b8275d35d	1627	* @}
<>	135:176b8275d35d	1628	*/
<>	135:176b8275d35d	1629
<>	135:176b8275d35d	1630
<>	135:176b8275d35d	1631	/* Exported functions --------------------------------------------------------*/
<>	135:176b8275d35d	1632
<>	135:176b8275d35d	1633	/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
<>	135:176b8275d35d	1634	* @{
<>	135:176b8275d35d	1635	*/
<>	135:176b8275d35d	1636
<>	135:176b8275d35d	1637	/** @defgroup I2S_LL_EF_Configuration Configuration
<>	135:176b8275d35d	1638	* @{
<>	135:176b8275d35d	1639	*/
<>	135:176b8275d35d	1640
<>	135:176b8275d35d	1641	/**
<>	135:176b8275d35d	1642	* @brief Select I2S mode and Enable I2S peripheral
<>	135:176b8275d35d	1643	* @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
<>	135:176b8275d35d	1644	* I2SCFGR I2SE LL_I2S_Enable
<>	135:176b8275d35d	1645	* @param SPIx SPI Instance
<>	135:176b8275d35d	1646	* @retval None
<>	135:176b8275d35d	1647	*/
<>	135:176b8275d35d	1648	__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1649	{
<>	135:176b8275d35d	1650	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
<>	135:176b8275d35d	1651	}
<>	135:176b8275d35d	1652
<>	135:176b8275d35d	1653	/**
<>	135:176b8275d35d	1654	* @brief Disable I2S peripheral
<>	135:176b8275d35d	1655	* @rmtoll I2SCFGR I2SE LL_I2S_Disable
<>	135:176b8275d35d	1656	* @param SPIx SPI Instance
<>	135:176b8275d35d	1657	* @retval None
<>	135:176b8275d35d	1658	*/
<>	135:176b8275d35d	1659	__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1660	{
<>	135:176b8275d35d	1661	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
<>	135:176b8275d35d	1662	}
<>	135:176b8275d35d	1663
<>	135:176b8275d35d	1664	/**
<>	135:176b8275d35d	1665	* @brief Check if I2S peripheral is enabled
<>	135:176b8275d35d	1666	* @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
<>	135:176b8275d35d	1667	* @param SPIx SPI Instance
<>	135:176b8275d35d	1668	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1669	*/
<>	135:176b8275d35d	1670	__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1671	{
<>	135:176b8275d35d	1672	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
<>	135:176b8275d35d	1673	}
<>	135:176b8275d35d	1674
<>	135:176b8275d35d	1675	/**
<>	135:176b8275d35d	1676	* @brief Set I2S data frame length
<>	135:176b8275d35d	1677	* @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
<>	135:176b8275d35d	1678	* I2SCFGR CHLEN LL_I2S_SetDataFormat
<>	135:176b8275d35d	1679	* @param SPIx SPI Instance
<>	135:176b8275d35d	1680	* @param DataFormat This parameter can be one of the following values:
<>	135:176b8275d35d	1681	* @arg @ref LL_I2S_DATAFORMAT_16B
<>	135:176b8275d35d	1682	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
<>	135:176b8275d35d	1683	* @arg @ref LL_I2S_DATAFORMAT_24B
<>	135:176b8275d35d	1684	* @arg @ref LL_I2S_DATAFORMAT_32B
<>	135:176b8275d35d	1685	* @retval None
<>	135:176b8275d35d	1686	*/
<>	135:176b8275d35d	1687	__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
<>	135:176b8275d35d	1688	{
<>	135:176b8275d35d	1689	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN, DataFormat);
<>	135:176b8275d35d	1690	}
<>	135:176b8275d35d	1691
<>	135:176b8275d35d	1692	/**
<>	135:176b8275d35d	1693	* @brief Get I2S data frame length
<>	135:176b8275d35d	1694	* @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
<>	135:176b8275d35d	1695	* I2SCFGR CHLEN LL_I2S_GetDataFormat
<>	135:176b8275d35d	1696	* @param SPIx SPI Instance
<>	135:176b8275d35d	1697	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	1698	* @arg @ref LL_I2S_DATAFORMAT_16B
<>	135:176b8275d35d	1699	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
<>	135:176b8275d35d	1700	* @arg @ref LL_I2S_DATAFORMAT_24B
<>	135:176b8275d35d	1701	* @arg @ref LL_I2S_DATAFORMAT_32B
<>	135:176b8275d35d	1702	*/
<>	135:176b8275d35d	1703	__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1704	{
<>	135:176b8275d35d	1705	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN));
<>	135:176b8275d35d	1706	}
<>	135:176b8275d35d	1707
<>	135:176b8275d35d	1708	/**
<>	135:176b8275d35d	1709	* @brief Set I2S clock polarity
<>	135:176b8275d35d	1710	* @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
<>	135:176b8275d35d	1711	* @param SPIx SPI Instance
<>	135:176b8275d35d	1712	* @param ClockPolarity This parameter can be one of the following values:
<>	135:176b8275d35d	1713	* @arg @ref LL_I2S_POLARITY_LOW
<>	135:176b8275d35d	1714	* @arg @ref LL_I2S_POLARITY_HIGH
<>	135:176b8275d35d	1715	* @retval None
<>	135:176b8275d35d	1716	*/
<>	135:176b8275d35d	1717	__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
<>	135:176b8275d35d	1718	{
<>	135:176b8275d35d	1719	SET_BIT(SPIx->I2SCFGR, ClockPolarity);
<>	135:176b8275d35d	1720	}
<>	135:176b8275d35d	1721
<>	135:176b8275d35d	1722	/**
<>	135:176b8275d35d	1723	* @brief Get I2S clock polarity
<>	135:176b8275d35d	1724	* @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
<>	135:176b8275d35d	1725	* @param SPIx SPI Instance
<>	135:176b8275d35d	1726	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	1727	* @arg @ref LL_I2S_POLARITY_LOW
<>	135:176b8275d35d	1728	* @arg @ref LL_I2S_POLARITY_HIGH
<>	135:176b8275d35d	1729	*/
<>	135:176b8275d35d	1730	__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1731	{
<>	135:176b8275d35d	1732	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
<>	135:176b8275d35d	1733	}
<>	135:176b8275d35d	1734
<>	135:176b8275d35d	1735	/**
<>	135:176b8275d35d	1736	* @brief Set I2S standard protocol
<>	135:176b8275d35d	1737	* @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
<>	135:176b8275d35d	1738	* I2SCFGR PCMSYNC LL_I2S_SetStandard
<>	135:176b8275d35d	1739	* @param SPIx SPI Instance
<>	135:176b8275d35d	1740	* @param Standard This parameter can be one of the following values:
<>	135:176b8275d35d	1741	* @arg @ref LL_I2S_STANDARD_PHILIPS
<>	135:176b8275d35d	1742	* @arg @ref LL_I2S_STANDARD_MSB
<>	135:176b8275d35d	1743	* @arg @ref LL_I2S_STANDARD_LSB
<>	135:176b8275d35d	1744	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
<>	135:176b8275d35d	1745	* @arg @ref LL_I2S_STANDARD_PCM_LONG
<>	135:176b8275d35d	1746	* @retval None
<>	135:176b8275d35d	1747	*/
<>	135:176b8275d35d	1748	__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
<>	135:176b8275d35d	1749	{
<>	135:176b8275d35d	1750	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC, Standard);
<>	135:176b8275d35d	1751	}
<>	135:176b8275d35d	1752
<>	135:176b8275d35d	1753	/**
<>	135:176b8275d35d	1754	* @brief Get I2S standard protocol
<>	135:176b8275d35d	1755	* @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
<>	135:176b8275d35d	1756	* I2SCFGR PCMSYNC LL_I2S_GetStandard
<>	135:176b8275d35d	1757	* @param SPIx SPI Instance
<>	135:176b8275d35d	1758	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	1759	* @arg @ref LL_I2S_STANDARD_PHILIPS
<>	135:176b8275d35d	1760	* @arg @ref LL_I2S_STANDARD_MSB
<>	135:176b8275d35d	1761	* @arg @ref LL_I2S_STANDARD_LSB
<>	135:176b8275d35d	1762	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
<>	135:176b8275d35d	1763	* @arg @ref LL_I2S_STANDARD_PCM_LONG
<>	135:176b8275d35d	1764	*/
<>	135:176b8275d35d	1765	__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1766	{
<>	135:176b8275d35d	1767	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC));
<>	135:176b8275d35d	1768	}
<>	135:176b8275d35d	1769
<>	135:176b8275d35d	1770	/**
<>	135:176b8275d35d	1771	* @brief Set I2S transfer mode
<>	135:176b8275d35d	1772	* @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
<>	135:176b8275d35d	1773	* @param SPIx SPI Instance
<>	135:176b8275d35d	1774	* @param Mode This parameter can be one of the following values:
<>	135:176b8275d35d	1775	* @arg @ref LL_I2S_MODE_SLAVE_TX
<>	135:176b8275d35d	1776	* @arg @ref LL_I2S_MODE_SLAVE_RX
<>	135:176b8275d35d	1777	* @arg @ref LL_I2S_MODE_MASTER_TX
<>	135:176b8275d35d	1778	* @arg @ref LL_I2S_MODE_MASTER_RX
<>	135:176b8275d35d	1779	* @retval None
<>	135:176b8275d35d	1780	*/
<>	135:176b8275d35d	1781	__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
<>	135:176b8275d35d	1782	{
<>	135:176b8275d35d	1783	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
<>	135:176b8275d35d	1784	}
<>	135:176b8275d35d	1785
<>	135:176b8275d35d	1786	/**
<>	135:176b8275d35d	1787	* @brief Get I2S transfer mode
<>	135:176b8275d35d	1788	* @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
<>	135:176b8275d35d	1789	* @param SPIx SPI Instance
<>	135:176b8275d35d	1790	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	1791	* @arg @ref LL_I2S_MODE_SLAVE_TX
<>	135:176b8275d35d	1792	* @arg @ref LL_I2S_MODE_SLAVE_RX
<>	135:176b8275d35d	1793	* @arg @ref LL_I2S_MODE_MASTER_TX
<>	135:176b8275d35d	1794	* @arg @ref LL_I2S_MODE_MASTER_RX
<>	135:176b8275d35d	1795	*/
<>	135:176b8275d35d	1796	__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1797	{
<>	135:176b8275d35d	1798	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
<>	135:176b8275d35d	1799	}
<>	135:176b8275d35d	1800
<>	135:176b8275d35d	1801	/**
<>	135:176b8275d35d	1802	* @brief Set I2S linear prescaler
<>	135:176b8275d35d	1803	* @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
<>	135:176b8275d35d	1804	* @param SPIx SPI Instance
<>	135:176b8275d35d	1805	* @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
<>	135:176b8275d35d	1806	* @retval None
<>	135:176b8275d35d	1807	*/
<>	135:176b8275d35d	1808	__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
<>	135:176b8275d35d	1809	{
<>	135:176b8275d35d	1810	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
<>	135:176b8275d35d	1811	}
<>	135:176b8275d35d	1812
<>	135:176b8275d35d	1813	/**
<>	135:176b8275d35d	1814	* @brief Get I2S linear prescaler
<>	135:176b8275d35d	1815	* @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
<>	135:176b8275d35d	1816	* @param SPIx SPI Instance
<>	135:176b8275d35d	1817	* @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
<>	135:176b8275d35d	1818	*/
<>	135:176b8275d35d	1819	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1820	{
<>	135:176b8275d35d	1821	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
<>	135:176b8275d35d	1822	}
<>	135:176b8275d35d	1823
<>	135:176b8275d35d	1824	/**
<>	135:176b8275d35d	1825	* @brief Set I2S parity prescaler
<>	135:176b8275d35d	1826	* @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
<>	135:176b8275d35d	1827	* @param SPIx SPI Instance
<>	135:176b8275d35d	1828	* @param PrescalerParity This parameter can be one of the following values:
<>	135:176b8275d35d	1829	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
<>	135:176b8275d35d	1830	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
<>	135:176b8275d35d	1831	* @retval None
<>	135:176b8275d35d	1832	*/
<>	135:176b8275d35d	1833	__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
<>	135:176b8275d35d	1834	{
<>	135:176b8275d35d	1835	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
<>	135:176b8275d35d	1836	}
<>	135:176b8275d35d	1837
<>	135:176b8275d35d	1838	/**
<>	135:176b8275d35d	1839	* @brief Get I2S parity prescaler
<>	135:176b8275d35d	1840	* @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
<>	135:176b8275d35d	1841	* @param SPIx SPI Instance
<>	135:176b8275d35d	1842	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	1843	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
<>	135:176b8275d35d	1844	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
<>	135:176b8275d35d	1845	*/
<>	135:176b8275d35d	1846	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1847	{
<>	135:176b8275d35d	1848	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
<>	135:176b8275d35d	1849	}
<>	135:176b8275d35d	1850
<>	135:176b8275d35d	1851	/**
<>	135:176b8275d35d	1852	* @brief Enable the master clock ouput (Pin MCK)
<>	135:176b8275d35d	1853	* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
<>	135:176b8275d35d	1854	* @param SPIx SPI Instance
<>	135:176b8275d35d	1855	* @retval None
<>	135:176b8275d35d	1856	*/
<>	135:176b8275d35d	1857	__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1858	{
<>	135:176b8275d35d	1859	SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
<>	135:176b8275d35d	1860	}
<>	135:176b8275d35d	1861
<>	135:176b8275d35d	1862	/**
<>	135:176b8275d35d	1863	* @brief Disable the master clock ouput (Pin MCK)
<>	135:176b8275d35d	1864	* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
<>	135:176b8275d35d	1865	* @param SPIx SPI Instance
<>	135:176b8275d35d	1866	* @retval None
<>	135:176b8275d35d	1867	*/
<>	135:176b8275d35d	1868	__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1869	{
<>	135:176b8275d35d	1870	CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
<>	135:176b8275d35d	1871	}
<>	135:176b8275d35d	1872
<>	135:176b8275d35d	1873	/**
<>	135:176b8275d35d	1874	* @brief Check if the master clock ouput (Pin MCK) is enabled
<>	135:176b8275d35d	1875	* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
<>	135:176b8275d35d	1876	* @param SPIx SPI Instance
<>	135:176b8275d35d	1877	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1878	*/
<>	135:176b8275d35d	1879	__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1880	{
<>	135:176b8275d35d	1881	return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
<>	135:176b8275d35d	1882	}
<>	135:176b8275d35d	1883
<>	135:176b8275d35d	1884	/**
<>	135:176b8275d35d	1885	* @}
<>	135:176b8275d35d	1886	*/
<>	135:176b8275d35d	1887
<>	135:176b8275d35d	1888	/** @defgroup I2S_LL_EF_FLAG FLAG Management
<>	135:176b8275d35d	1889	* @{
<>	135:176b8275d35d	1890	*/
<>	135:176b8275d35d	1891
<>	135:176b8275d35d	1892	/**
<>	135:176b8275d35d	1893	* @brief Check if Rx buffer is not empty
<>	135:176b8275d35d	1894	* @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
<>	135:176b8275d35d	1895	* @param SPIx SPI Instance
<>	135:176b8275d35d	1896	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1897	*/
<>	135:176b8275d35d	1898	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1899	{
<>	135:176b8275d35d	1900	return LL_SPI_IsActiveFlag_RXNE(SPIx);
<>	135:176b8275d35d	1901	}
<>	135:176b8275d35d	1902
<>	135:176b8275d35d	1903	/**
<>	135:176b8275d35d	1904	* @brief Check if Tx buffer is empty
<>	135:176b8275d35d	1905	* @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
<>	135:176b8275d35d	1906	* @param SPIx SPI Instance
<>	135:176b8275d35d	1907	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1908	*/
<>	135:176b8275d35d	1909	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1910	{
<>	135:176b8275d35d	1911	return LL_SPI_IsActiveFlag_TXE(SPIx);
<>	135:176b8275d35d	1912	}
<>	135:176b8275d35d	1913
<>	135:176b8275d35d	1914	/**
<>	135:176b8275d35d	1915	* @brief Get busy flag
<>	135:176b8275d35d	1916	* @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
<>	135:176b8275d35d	1917	* @param SPIx SPI Instance
<>	135:176b8275d35d	1918	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1919	*/
<>	135:176b8275d35d	1920	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1921	{
<>	135:176b8275d35d	1922	return LL_SPI_IsActiveFlag_BSY(SPIx);
<>	135:176b8275d35d	1923	}
<>	135:176b8275d35d	1924
<>	135:176b8275d35d	1925	/**
<>	135:176b8275d35d	1926	* @brief Get overrun error flag
<>	135:176b8275d35d	1927	* @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
<>	135:176b8275d35d	1928	* @param SPIx SPI Instance
<>	135:176b8275d35d	1929	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1930	*/
<>	135:176b8275d35d	1931	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1932	{
<>	135:176b8275d35d	1933	return LL_SPI_IsActiveFlag_OVR(SPIx);
<>	135:176b8275d35d	1934	}
<>	135:176b8275d35d	1935
<>	135:176b8275d35d	1936	/**
<>	135:176b8275d35d	1937	* @brief Get underrun error flag
<>	135:176b8275d35d	1938	* @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
<>	135:176b8275d35d	1939	* @param SPIx SPI Instance
<>	135:176b8275d35d	1940	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1941	*/
<>	135:176b8275d35d	1942	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1943	{
<>	135:176b8275d35d	1944	return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
<>	135:176b8275d35d	1945	}
<>	135:176b8275d35d	1946
<>	135:176b8275d35d	1947	/**
<>	135:176b8275d35d	1948	* @brief Get frame format error flag
<>	135:176b8275d35d	1949	* @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
<>	135:176b8275d35d	1950	* @param SPIx SPI Instance
<>	135:176b8275d35d	1951	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1952	*/
<>	135:176b8275d35d	1953	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1954	{
<>	135:176b8275d35d	1955	return LL_SPI_IsActiveFlag_FRE(SPIx);
<>	135:176b8275d35d	1956	}
<>	135:176b8275d35d	1957
<>	135:176b8275d35d	1958	/**
<>	135:176b8275d35d	1959	* @brief Get channel side flag.
<>	135:176b8275d35d	1960	* @note 0: Channel Left has to be transmitted or has been received\n
<>	135:176b8275d35d	1961	* 1: Channel Right has to be transmitted or has been received\n
<>	135:176b8275d35d	1962	* It has no significance in PCM mode.
<>	135:176b8275d35d	1963	* @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
<>	135:176b8275d35d	1964	* @param SPIx SPI Instance
<>	135:176b8275d35d	1965	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1966	*/
<>	135:176b8275d35d	1967	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1968	{
<>	135:176b8275d35d	1969	return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
<>	135:176b8275d35d	1970	}
<>	135:176b8275d35d	1971
<>	135:176b8275d35d	1972	/**
<>	135:176b8275d35d	1973	* @brief Clear overrun error flag
<>	135:176b8275d35d	1974	* @rmtoll SR OVR LL_I2S_ClearFlag_OVR
<>	135:176b8275d35d	1975	* @param SPIx SPI Instance
<>	135:176b8275d35d	1976	* @retval None
<>	135:176b8275d35d	1977	*/
<>	135:176b8275d35d	1978	__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1979	{
<>	135:176b8275d35d	1980	LL_SPI_ClearFlag_OVR(SPIx);
<>	135:176b8275d35d	1981	}
<>	135:176b8275d35d	1982
<>	135:176b8275d35d	1983	/**
<>	135:176b8275d35d	1984	* @brief Clear underrun error flag
<>	135:176b8275d35d	1985	* @rmtoll SR UDR LL_I2S_ClearFlag_UDR
<>	135:176b8275d35d	1986	* @param SPIx SPI Instance
<>	135:176b8275d35d	1987	* @retval None
<>	135:176b8275d35d	1988	*/
<>	135:176b8275d35d	1989	__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	1990	{
<>	135:176b8275d35d	1991	__IO uint32_t tmpreg;
<>	135:176b8275d35d	1992	tmpreg = SPIx->SR;
<>	135:176b8275d35d	1993	(void)tmpreg;
<>	135:176b8275d35d	1994	}
<>	135:176b8275d35d	1995
<>	135:176b8275d35d	1996	/**
<>	135:176b8275d35d	1997	* @brief Clear frame format error flag
<>	135:176b8275d35d	1998	* @rmtoll SR FRE LL_I2S_ClearFlag_FRE
<>	135:176b8275d35d	1999	* @param SPIx SPI Instance
<>	135:176b8275d35d	2000	* @retval None
<>	135:176b8275d35d	2001	*/
<>	135:176b8275d35d	2002	__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	2003	{
<>	135:176b8275d35d	2004	LL_SPI_ClearFlag_FRE(SPIx);
<>	135:176b8275d35d	2005	}
<>	135:176b8275d35d	2006
<>	135:176b8275d35d	2007	/**
<>	135:176b8275d35d	2008	* @}
<>	135:176b8275d35d	2009	*/
<>	135:176b8275d35d	2010
<>	135:176b8275d35d	2011	/** @defgroup I2S_LL_EF_IT Interrupt Management
<>	135:176b8275d35d	2012	* @{
<>	135:176b8275d35d	2013	*/
<>	135:176b8275d35d	2014
<>	135:176b8275d35d	2015	/**
<>	135:176b8275d35d	2016	* @brief Enable error IT
<>	135:176b8275d35d	2017	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
<>	135:176b8275d35d	2018	* @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
<>	135:176b8275d35d	2019	* @param SPIx SPI Instance
<>	135:176b8275d35d	2020	* @retval None
<>	135:176b8275d35d	2021	*/
<>	135:176b8275d35d	2022	__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	2023	{
<>	135:176b8275d35d	2024	LL_SPI_EnableIT_ERR(SPIx);
<>	135:176b8275d35d	2025	}
<>	135:176b8275d35d	2026
<>	135:176b8275d35d	2027	/**
<>	135:176b8275d35d	2028	* @brief Enable Rx buffer not empty IT
<>	135:176b8275d35d	2029	* @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
<>	135:176b8275d35d	2030	* @param SPIx SPI Instance
<>	135:176b8275d35d	2031	* @retval None
<>	135:176b8275d35d	2032	*/
<>	135:176b8275d35d	2033	__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	2034	{
<>	135:176b8275d35d	2035	LL_SPI_EnableIT_RXNE(SPIx);
<>	135:176b8275d35d	2036	}
<>	135:176b8275d35d	2037
<>	135:176b8275d35d	2038	/**
<>	135:176b8275d35d	2039	* @brief Enable Tx buffer empty IT
<>	135:176b8275d35d	2040	* @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
<>	135:176b8275d35d	2041	* @param SPIx SPI Instance
<>	135:176b8275d35d	2042	* @retval None
<>	135:176b8275d35d	2043	*/
<>	135:176b8275d35d	2044	__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	2045	{
<>	135:176b8275d35d	2046	LL_SPI_EnableIT_TXE(SPIx);
<>	135:176b8275d35d	2047	}
<>	135:176b8275d35d	2048
<>	135:176b8275d35d	2049	/**
<>	135:176b8275d35d	2050	* @brief Disable error IT
<>	135:176b8275d35d	2051	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
<>	135:176b8275d35d	2052	* @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
<>	135:176b8275d35d	2053	* @param SPIx SPI Instance
<>	135:176b8275d35d	2054	* @retval None
<>	135:176b8275d35d	2055	*/
<>	135:176b8275d35d	2056	__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	2057	{
<>	135:176b8275d35d	2058	LL_SPI_DisableIT_ERR(SPIx);
<>	135:176b8275d35d	2059	}
<>	135:176b8275d35d	2060
<>	135:176b8275d35d	2061	/**
<>	135:176b8275d35d	2062	* @brief Disable Rx buffer not empty IT
<>	135:176b8275d35d	2063	* @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
<>	135:176b8275d35d	2064	* @param SPIx SPI Instance
<>	135:176b8275d35d	2065	* @retval None
<>	135:176b8275d35d	2066	*/
<>	135:176b8275d35d	2067	__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	2068	{
<>	135:176b8275d35d	2069	LL_SPI_DisableIT_RXNE(SPIx);
<>	135:176b8275d35d	2070	}
<>	135:176b8275d35d	2071
<>	135:176b8275d35d	2072	/**
<>	135:176b8275d35d	2073	* @brief Disable Tx buffer empty IT
<>	135:176b8275d35d	2074	* @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
<>	135:176b8275d35d	2075	* @param SPIx SPI Instance
<>	135:176b8275d35d	2076	* @retval None
<>	135:176b8275d35d	2077	*/
<>	135:176b8275d35d	2078	__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	2079	{
<>	135:176b8275d35d	2080	LL_SPI_DisableIT_TXE(SPIx);
<>	135:176b8275d35d	2081	}
<>	135:176b8275d35d	2082
<>	135:176b8275d35d	2083	/**
<>	135:176b8275d35d	2084	* @brief Check if ERR IT is enabled
<>	135:176b8275d35d	2085	* @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
<>	135:176b8275d35d	2086	* @param SPIx SPI Instance
<>	135:176b8275d35d	2087	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	2088	*/
<>	135:176b8275d35d	2089	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	2090	{
<>	135:176b8275d35d	2091	return LL_SPI_IsEnabledIT_ERR(SPIx);
<>	135:176b8275d35d	2092	}
<>	135:176b8275d35d	2093
<>	135:176b8275d35d	2094	/**
<>	135:176b8275d35d	2095	* @brief Check if RXNE IT is enabled
<>	135:176b8275d35d	2096	* @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
<>	135:176b8275d35d	2097	* @param SPIx SPI Instance
<>	135:176b8275d35d	2098	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	2099	*/
<>	135:176b8275d35d	2100	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	2101	{
<>	135:176b8275d35d	2102	return LL_SPI_IsEnabledIT_RXNE(SPIx);
<>	135:176b8275d35d	2103	}
<>	135:176b8275d35d	2104
<>	135:176b8275d35d	2105	/**
<>	135:176b8275d35d	2106	* @brief Check if TXE IT is enabled
<>	135:176b8275d35d	2107	* @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
<>	135:176b8275d35d	2108	* @param SPIx SPI Instance
<>	135:176b8275d35d	2109	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	2110	*/
<>	135:176b8275d35d	2111	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	2112	{
<>	135:176b8275d35d	2113	return LL_SPI_IsEnabledIT_TXE(SPIx);
<>	135:176b8275d35d	2114	}
<>	135:176b8275d35d	2115
<>	135:176b8275d35d	2116	/**
<>	135:176b8275d35d	2117	* @}
<>	135:176b8275d35d	2118	*/
<>	135:176b8275d35d	2119
<>	135:176b8275d35d	2120	/** @defgroup I2S_LL_EF_DMA DMA Management
<>	135:176b8275d35d	2121	* @{
<>	135:176b8275d35d	2122	*/
<>	135:176b8275d35d	2123
<>	135:176b8275d35d	2124	/**
<>	135:176b8275d35d	2125	* @brief Enable DMA Rx
<>	135:176b8275d35d	2126	* @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
<>	135:176b8275d35d	2127	* @param SPIx SPI Instance
<>	135:176b8275d35d	2128	* @retval None
<>	135:176b8275d35d	2129	*/
<>	135:176b8275d35d	2130	__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	2131	{
<>	135:176b8275d35d	2132	LL_SPI_EnableDMAReq_RX(SPIx);
<>	135:176b8275d35d	2133	}
<>	135:176b8275d35d	2134
<>	135:176b8275d35d	2135	/**
<>	135:176b8275d35d	2136	* @brief Disable DMA Rx
<>	135:176b8275d35d	2137	* @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
<>	135:176b8275d35d	2138	* @param SPIx SPI Instance
<>	135:176b8275d35d	2139	* @retval None
<>	135:176b8275d35d	2140	*/
<>	135:176b8275d35d	2141	__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	2142	{
<>	135:176b8275d35d	2143	LL_SPI_DisableDMAReq_RX(SPIx);
<>	135:176b8275d35d	2144	}
<>	135:176b8275d35d	2145
<>	135:176b8275d35d	2146	/**
<>	135:176b8275d35d	2147	* @brief Check if DMA Rx is enabled
<>	135:176b8275d35d	2148	* @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
<>	135:176b8275d35d	2149	* @param SPIx SPI Instance
<>	135:176b8275d35d	2150	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	2151	*/
<>	135:176b8275d35d	2152	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	2153	{
<>	135:176b8275d35d	2154	return LL_SPI_IsEnabledDMAReq_RX(SPIx);
<>	135:176b8275d35d	2155	}
<>	135:176b8275d35d	2156
<>	135:176b8275d35d	2157	/**
<>	135:176b8275d35d	2158	* @brief Enable DMA Tx
<>	135:176b8275d35d	2159	* @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
<>	135:176b8275d35d	2160	* @param SPIx SPI Instance
<>	135:176b8275d35d	2161	* @retval None
<>	135:176b8275d35d	2162	*/
<>	135:176b8275d35d	2163	__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	2164	{
<>	135:176b8275d35d	2165	LL_SPI_EnableDMAReq_TX(SPIx);
<>	135:176b8275d35d	2166	}
<>	135:176b8275d35d	2167
<>	135:176b8275d35d	2168	/**
<>	135:176b8275d35d	2169	* @brief Disable DMA Tx
<>	135:176b8275d35d	2170	* @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
<>	135:176b8275d35d	2171	* @param SPIx SPI Instance
<>	135:176b8275d35d	2172	* @retval None
<>	135:176b8275d35d	2173	*/
<>	135:176b8275d35d	2174	__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	2175	{
<>	135:176b8275d35d	2176	LL_SPI_DisableDMAReq_TX(SPIx);
<>	135:176b8275d35d	2177	}
<>	135:176b8275d35d	2178
<>	135:176b8275d35d	2179	/**
<>	135:176b8275d35d	2180	* @brief Check if DMA Tx is enabled
<>	135:176b8275d35d	2181	* @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
<>	135:176b8275d35d	2182	* @param SPIx SPI Instance
<>	135:176b8275d35d	2183	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	2184	*/
<>	135:176b8275d35d	2185	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	2186	{
<>	135:176b8275d35d	2187	return LL_SPI_IsEnabledDMAReq_TX(SPIx);
<>	135:176b8275d35d	2188	}
<>	135:176b8275d35d	2189
<>	135:176b8275d35d	2190	/**
<>	135:176b8275d35d	2191	* @}
<>	135:176b8275d35d	2192	*/
<>	135:176b8275d35d	2193
<>	135:176b8275d35d	2194	/** @defgroup I2S_LL_EF_DATA DATA Management
<>	135:176b8275d35d	2195	* @{
<>	135:176b8275d35d	2196	*/
<>	135:176b8275d35d	2197
<>	135:176b8275d35d	2198	/**
<>	135:176b8275d35d	2199	* @brief Read 16-Bits in data register
<>	135:176b8275d35d	2200	* @rmtoll DR DR LL_I2S_ReceiveData16
<>	135:176b8275d35d	2201	* @param SPIx SPI Instance
<>	135:176b8275d35d	2202	* @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
<>	135:176b8275d35d	2203	*/
<>	135:176b8275d35d	2204	__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
<>	135:176b8275d35d	2205	{
<>	135:176b8275d35d	2206	return LL_SPI_ReceiveData16(SPIx);
<>	135:176b8275d35d	2207	}
<>	135:176b8275d35d	2208
<>	135:176b8275d35d	2209	/**
<>	135:176b8275d35d	2210	* @brief Write 16-Bits in data register
<>	135:176b8275d35d	2211	* @rmtoll DR DR LL_I2S_TransmitData16
<>	135:176b8275d35d	2212	* @param SPIx SPI Instance
<>	135:176b8275d35d	2213	* @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
<>	135:176b8275d35d	2214	* @retval None
<>	135:176b8275d35d	2215	*/
<>	135:176b8275d35d	2216	__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
<>	135:176b8275d35d	2217	{
<>	135:176b8275d35d	2218	LL_SPI_TransmitData16(SPIx, TxData);
<>	135:176b8275d35d	2219	}
<>	135:176b8275d35d	2220
<>	135:176b8275d35d	2221	/**
<>	135:176b8275d35d	2222	* @}
<>	135:176b8275d35d	2223	*/
<>	135:176b8275d35d	2224
<>	135:176b8275d35d	2225	#if defined(USE_FULL_LL_DRIVER)
<>	135:176b8275d35d	2226	/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
<>	135:176b8275d35d	2227	* @{
<>	135:176b8275d35d	2228	*/
<>	135:176b8275d35d	2229
<>	135:176b8275d35d	2230	ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
<>	135:176b8275d35d	2231	ErrorStatus LL_I2S_Init(SPI_TypeDef SPIx, LL_I2S_InitTypeDef I2S_InitStruct);
<>	135:176b8275d35d	2232	void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
<>	135:176b8275d35d	2233	void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
<>	135:176b8275d35d	2234	#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
<>	135:176b8275d35d	2235	ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef I2Sxext, LL_I2S_InitTypeDef I2S_InitStruct);
<>	135:176b8275d35d	2236	#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
<>	135:176b8275d35d	2237
<>	135:176b8275d35d	2238	/**
<>	135:176b8275d35d	2239	* @}
<>	135:176b8275d35d	2240	*/
<>	135:176b8275d35d	2241	#endif /* USE_FULL_LL_DRIVER */
<>	135:176b8275d35d	2242
<>	135:176b8275d35d	2243	/**
<>	135:176b8275d35d	2244	* @}
<>	135:176b8275d35d	2245	*/
<>	135:176b8275d35d	2246
<>	135:176b8275d35d	2247	/**
<>	135:176b8275d35d	2248	* @}
<>	135:176b8275d35d	2249	*/
<>	135:176b8275d35d	2250	#endif /* SPI_I2S_SUPPORT */
<>	135:176b8275d35d	2251
<>	135:176b8275d35d	2252	#endif /* defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3) \|\| defined (SPI4) */
<>	135:176b8275d35d	2253
<>	135:176b8275d35d	2254	/**
<>	135:176b8275d35d	2255	* @}
<>	135:176b8275d35d	2256	*/
<>	135:176b8275d35d	2257
<>	135:176b8275d35d	2258	#ifdef __cplusplus
<>	135:176b8275d35d	2259	}
<>	135:176b8275d35d	2260	#endif
<>	135:176b8275d35d	2261
<>	135:176b8275d35d	2262	#endif /* __STM32F3xx_LL_SPI_H */
<>	135:176b8275d35d	2263
<>	135:176b8275d35d	2264	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/