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TARGET_NUCLEO_F334R8/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_pwr.h@143:86740a56073b, 2017-05-26 (annotated)
- Committer:
- AnnaBridge
- Date:
- Fri May 26 12:30:20 2017 +0100
- Revision:
- 143:86740a56073b
- Parent:
- 135:176b8275d35d
- Child:
- 168:b9e159c1930a
Release 143 of the mbed library.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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<> | 135:176b8275d35d | 1 | /** |
<> | 135:176b8275d35d | 2 | ****************************************************************************** |
<> | 135:176b8275d35d | 3 | * @file stm32f3xx_ll_pwr.h |
<> | 135:176b8275d35d | 4 | * @author MCD Application Team |
<> | 135:176b8275d35d | 5 | * @version V1.4.0 |
<> | 135:176b8275d35d | 6 | * @date 16-December-2016 |
<> | 135:176b8275d35d | 7 | * @brief Header file of PWR LL module. |
<> | 135:176b8275d35d | 8 | ****************************************************************************** |
<> | 135:176b8275d35d | 9 | * @attention |
<> | 135:176b8275d35d | 10 | * |
<> | 135:176b8275d35d | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 135:176b8275d35d | 12 | * |
<> | 135:176b8275d35d | 13 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 135:176b8275d35d | 14 | * are permitted provided that the following conditions are met: |
<> | 135:176b8275d35d | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 135:176b8275d35d | 16 | * this list of conditions and the following disclaimer. |
<> | 135:176b8275d35d | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 135:176b8275d35d | 18 | * this list of conditions and the following disclaimer in the documentation |
<> | 135:176b8275d35d | 19 | * and/or other materials provided with the distribution. |
<> | 135:176b8275d35d | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 135:176b8275d35d | 21 | * may be used to endorse or promote products derived from this software |
<> | 135:176b8275d35d | 22 | * without specific prior written permission. |
<> | 135:176b8275d35d | 23 | * |
<> | 135:176b8275d35d | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 135:176b8275d35d | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 135:176b8275d35d | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 135:176b8275d35d | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 135:176b8275d35d | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 135:176b8275d35d | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 135:176b8275d35d | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 135:176b8275d35d | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 135:176b8275d35d | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 135:176b8275d35d | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 135:176b8275d35d | 34 | * |
<> | 135:176b8275d35d | 35 | ****************************************************************************** |
<> | 135:176b8275d35d | 36 | */ |
<> | 135:176b8275d35d | 37 | |
<> | 135:176b8275d35d | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
<> | 135:176b8275d35d | 39 | #ifndef __STM32F3xx_LL_PWR_H |
<> | 135:176b8275d35d | 40 | #define __STM32F3xx_LL_PWR_H |
<> | 135:176b8275d35d | 41 | |
<> | 135:176b8275d35d | 42 | #ifdef __cplusplus |
<> | 135:176b8275d35d | 43 | extern "C" { |
<> | 135:176b8275d35d | 44 | #endif |
<> | 135:176b8275d35d | 45 | |
<> | 135:176b8275d35d | 46 | /* Includes ------------------------------------------------------------------*/ |
<> | 135:176b8275d35d | 47 | #include "stm32f3xx.h" |
<> | 135:176b8275d35d | 48 | |
<> | 135:176b8275d35d | 49 | /** @addtogroup STM32F3xx_LL_Driver |
<> | 135:176b8275d35d | 50 | * @{ |
<> | 135:176b8275d35d | 51 | */ |
<> | 135:176b8275d35d | 52 | |
<> | 135:176b8275d35d | 53 | #if defined(PWR) |
<> | 135:176b8275d35d | 54 | |
<> | 135:176b8275d35d | 55 | /** @defgroup PWR_LL PWR |
<> | 135:176b8275d35d | 56 | * @{ |
<> | 135:176b8275d35d | 57 | */ |
<> | 135:176b8275d35d | 58 | |
<> | 135:176b8275d35d | 59 | /* Private types -------------------------------------------------------------*/ |
<> | 135:176b8275d35d | 60 | /* Private variables ---------------------------------------------------------*/ |
<> | 135:176b8275d35d | 61 | /* Private constants ---------------------------------------------------------*/ |
<> | 135:176b8275d35d | 62 | /* Private macros ------------------------------------------------------------*/ |
<> | 135:176b8275d35d | 63 | /* Exported types ------------------------------------------------------------*/ |
<> | 135:176b8275d35d | 64 | /* Exported constants --------------------------------------------------------*/ |
<> | 135:176b8275d35d | 65 | /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants |
<> | 135:176b8275d35d | 66 | * @{ |
<> | 135:176b8275d35d | 67 | */ |
<> | 135:176b8275d35d | 68 | |
<> | 135:176b8275d35d | 69 | /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines |
<> | 135:176b8275d35d | 70 | * @brief Flags defines which can be used with LL_PWR_WriteReg function |
<> | 135:176b8275d35d | 71 | * @{ |
<> | 135:176b8275d35d | 72 | */ |
<> | 135:176b8275d35d | 73 | #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ |
<> | 135:176b8275d35d | 74 | #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ |
<> | 135:176b8275d35d | 75 | /** |
<> | 135:176b8275d35d | 76 | * @} |
<> | 135:176b8275d35d | 77 | */ |
<> | 135:176b8275d35d | 78 | |
<> | 135:176b8275d35d | 79 | /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines |
<> | 135:176b8275d35d | 80 | * @brief Flags defines which can be used with LL_PWR_ReadReg function |
<> | 135:176b8275d35d | 81 | * @{ |
<> | 135:176b8275d35d | 82 | */ |
<> | 135:176b8275d35d | 83 | #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ |
<> | 135:176b8275d35d | 84 | #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ |
<> | 135:176b8275d35d | 85 | #if defined(PWR_PVD_SUPPORT) |
<> | 135:176b8275d35d | 86 | #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ |
<> | 135:176b8275d35d | 87 | #endif /* PWR_PVD_SUPPORT */ |
<> | 135:176b8275d35d | 88 | #if defined(PWR_CSR_VREFINTRDYF) |
<> | 135:176b8275d35d | 89 | #define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */ |
<> | 135:176b8275d35d | 90 | #endif /* PWR_CSR_VREFINTRDYF */ |
<> | 135:176b8275d35d | 91 | #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ |
<> | 135:176b8275d35d | 92 | #define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ |
<> | 135:176b8275d35d | 93 | #if defined(PWR_CSR_EWUP3) |
<> | 135:176b8275d35d | 94 | #define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ |
<> | 135:176b8275d35d | 95 | #endif /* PWR_CSR_EWUP3 */ |
<> | 135:176b8275d35d | 96 | /** |
<> | 135:176b8275d35d | 97 | * @} |
<> | 135:176b8275d35d | 98 | */ |
<> | 135:176b8275d35d | 99 | |
<> | 135:176b8275d35d | 100 | |
<> | 135:176b8275d35d | 101 | /** @defgroup PWR_LL_EC_MODE_PWR Mode Power |
<> | 135:176b8275d35d | 102 | * @{ |
<> | 135:176b8275d35d | 103 | */ |
<> | 135:176b8275d35d | 104 | #define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ |
<> | 135:176b8275d35d | 105 | #define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (ith low power regulator ON) when the CPU enters deepsleep */ |
<> | 135:176b8275d35d | 106 | #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ |
<> | 135:176b8275d35d | 107 | /** |
<> | 135:176b8275d35d | 108 | * @} |
<> | 135:176b8275d35d | 109 | */ |
<> | 135:176b8275d35d | 110 | |
<> | 135:176b8275d35d | 111 | #if defined(PWR_CR_LPDS) |
<> | 135:176b8275d35d | 112 | /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode |
<> | 135:176b8275d35d | 113 | * @{ |
<> | 135:176b8275d35d | 114 | */ |
<> | 135:176b8275d35d | 115 | #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage regulator in main mode during deepsleep mode */ |
<> | 135:176b8275d35d | 116 | #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage regulator in low-power mode during deepsleep mode */ |
<> | 135:176b8275d35d | 117 | /** |
<> | 135:176b8275d35d | 118 | * @} |
<> | 135:176b8275d35d | 119 | */ |
<> | 135:176b8275d35d | 120 | #endif /* PWR_CR_LPDS */ |
<> | 135:176b8275d35d | 121 | |
<> | 135:176b8275d35d | 122 | #if defined(PWR_PVD_SUPPORT) |
<> | 135:176b8275d35d | 123 | /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level |
<> | 135:176b8275d35d | 124 | * @{ |
<> | 135:176b8275d35d | 125 | */ |
<> | 135:176b8275d35d | 126 | #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */ |
<> | 135:176b8275d35d | 127 | #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */ |
<> | 135:176b8275d35d | 128 | #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */ |
<> | 135:176b8275d35d | 129 | #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */ |
<> | 135:176b8275d35d | 130 | #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */ |
<> | 135:176b8275d35d | 131 | #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */ |
<> | 135:176b8275d35d | 132 | #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */ |
<> | 135:176b8275d35d | 133 | #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */ |
<> | 135:176b8275d35d | 134 | /** |
<> | 135:176b8275d35d | 135 | * @} |
<> | 135:176b8275d35d | 136 | */ |
<> | 135:176b8275d35d | 137 | #endif /* PWR_PVD_SUPPORT */ |
<> | 135:176b8275d35d | 138 | /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins |
<> | 135:176b8275d35d | 139 | * @{ |
<> | 135:176b8275d35d | 140 | */ |
<> | 135:176b8275d35d | 141 | #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ |
<> | 135:176b8275d35d | 142 | #define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */ |
<> | 135:176b8275d35d | 143 | #if defined(PWR_CSR_EWUP3) |
<> | 135:176b8275d35d | 144 | #define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */ |
<> | 135:176b8275d35d | 145 | #endif /* PWR_CSR_EWUP3 */ |
<> | 135:176b8275d35d | 146 | /** |
<> | 135:176b8275d35d | 147 | * @} |
<> | 135:176b8275d35d | 148 | */ |
<> | 135:176b8275d35d | 149 | |
<> | 135:176b8275d35d | 150 | /** @defgroup PWR_LL_EC_SDADC_ANALOG_X SDADC Analogx |
<> | 135:176b8275d35d | 151 | * @{ |
<> | 135:176b8275d35d | 152 | */ |
<> | 135:176b8275d35d | 153 | #if defined(SDADC1) |
<> | 135:176b8275d35d | 154 | #define LL_PWR_SDADC_ANALOG1 (PWR_CR_ENSD1) /*!< Enable SDADC1 */ |
<> | 135:176b8275d35d | 155 | #endif /* SDADC1 */ |
<> | 135:176b8275d35d | 156 | #if defined(SDADC2) |
<> | 135:176b8275d35d | 157 | #define LL_PWR_SDADC_ANALOG2 (PWR_CR_ENSD2) /*!< Enable SDADC2 */ |
<> | 135:176b8275d35d | 158 | #endif /* SDADC2 */ |
<> | 135:176b8275d35d | 159 | #if defined(SDADC3) |
<> | 135:176b8275d35d | 160 | #define LL_PWR_SDADC_ANALOG3 (PWR_CR_ENSD3) /*!< Enable SDADC3 */ |
<> | 135:176b8275d35d | 161 | #endif /* SDADC3 */ |
<> | 135:176b8275d35d | 162 | /** |
<> | 135:176b8275d35d | 163 | * @} |
<> | 135:176b8275d35d | 164 | */ |
<> | 135:176b8275d35d | 165 | /** |
<> | 135:176b8275d35d | 166 | * @} |
<> | 135:176b8275d35d | 167 | */ |
<> | 135:176b8275d35d | 168 | |
<> | 135:176b8275d35d | 169 | |
<> | 135:176b8275d35d | 170 | /* Exported macro ------------------------------------------------------------*/ |
<> | 135:176b8275d35d | 171 | /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros |
<> | 135:176b8275d35d | 172 | * @{ |
<> | 135:176b8275d35d | 173 | */ |
<> | 135:176b8275d35d | 174 | |
<> | 135:176b8275d35d | 175 | /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros |
<> | 135:176b8275d35d | 176 | * @{ |
<> | 135:176b8275d35d | 177 | */ |
<> | 135:176b8275d35d | 178 | |
<> | 135:176b8275d35d | 179 | /** |
<> | 135:176b8275d35d | 180 | * @brief Write a value in PWR register |
<> | 135:176b8275d35d | 181 | * @param __REG__ Register to be written |
<> | 135:176b8275d35d | 182 | * @param __VALUE__ Value to be written in the register |
<> | 135:176b8275d35d | 183 | * @retval None |
<> | 135:176b8275d35d | 184 | */ |
<> | 135:176b8275d35d | 185 | #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) |
<> | 135:176b8275d35d | 186 | |
<> | 135:176b8275d35d | 187 | /** |
<> | 135:176b8275d35d | 188 | * @brief Read a value in PWR register |
<> | 135:176b8275d35d | 189 | * @param __REG__ Register to be read |
<> | 135:176b8275d35d | 190 | * @retval Register value |
<> | 135:176b8275d35d | 191 | */ |
<> | 135:176b8275d35d | 192 | #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) |
<> | 135:176b8275d35d | 193 | /** |
<> | 135:176b8275d35d | 194 | * @} |
<> | 135:176b8275d35d | 195 | */ |
<> | 135:176b8275d35d | 196 | |
<> | 135:176b8275d35d | 197 | /** |
<> | 135:176b8275d35d | 198 | * @} |
<> | 135:176b8275d35d | 199 | */ |
<> | 135:176b8275d35d | 200 | |
<> | 135:176b8275d35d | 201 | /* Exported functions --------------------------------------------------------*/ |
<> | 135:176b8275d35d | 202 | /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions |
<> | 135:176b8275d35d | 203 | * @{ |
<> | 135:176b8275d35d | 204 | */ |
<> | 135:176b8275d35d | 205 | |
<> | 135:176b8275d35d | 206 | /** @defgroup PWR_LL_EF_Configuration Configuration |
<> | 135:176b8275d35d | 207 | * @{ |
<> | 135:176b8275d35d | 208 | */ |
<> | 135:176b8275d35d | 209 | /** |
<> | 135:176b8275d35d | 210 | * @brief Enables the SDADC peripheral functionality |
<> | 135:176b8275d35d | 211 | * @rmtoll CR ENSD1 LL_PWR_EnableSDADC\n |
<> | 135:176b8275d35d | 212 | * CR ENSD2 LL_PWR_EnableSDADC\n |
<> | 135:176b8275d35d | 213 | * CR ENSD3 LL_PWR_EnableSDADC |
<> | 135:176b8275d35d | 214 | * @param Analogx This parameter can be a combination of the following values: |
<> | 135:176b8275d35d | 215 | * @arg @ref LL_PWR_SDADC_ANALOG1 |
<> | 135:176b8275d35d | 216 | * @arg @ref LL_PWR_SDADC_ANALOG2 |
<> | 135:176b8275d35d | 217 | * @arg @ref LL_PWR_SDADC_ANALOG3 |
<> | 135:176b8275d35d | 218 | * @retval None |
<> | 135:176b8275d35d | 219 | */ |
<> | 135:176b8275d35d | 220 | __STATIC_INLINE void LL_PWR_EnableSDADC(uint32_t Analogx) |
<> | 135:176b8275d35d | 221 | { |
<> | 135:176b8275d35d | 222 | SET_BIT(PWR->CR, Analogx); |
<> | 135:176b8275d35d | 223 | } |
<> | 135:176b8275d35d | 224 | |
<> | 135:176b8275d35d | 225 | /** |
<> | 135:176b8275d35d | 226 | * @brief Disables the SDADC peripheral functionality |
<> | 135:176b8275d35d | 227 | * @rmtoll CR ENSD1 LL_PWR_EnableSDADC\n |
<> | 135:176b8275d35d | 228 | * CR ENSD2 LL_PWR_EnableSDADC\n |
<> | 135:176b8275d35d | 229 | * CR ENSD3 LL_PWR_EnableSDADC |
<> | 135:176b8275d35d | 230 | * @param Analogx This parameter can be a combination of the following values: |
<> | 135:176b8275d35d | 231 | * @arg @ref LL_PWR_SDADC_ANALOG1 |
<> | 135:176b8275d35d | 232 | * @arg @ref LL_PWR_SDADC_ANALOG2 |
<> | 135:176b8275d35d | 233 | * @arg @ref LL_PWR_SDADC_ANALOG3 |
<> | 135:176b8275d35d | 234 | * @retval None |
<> | 135:176b8275d35d | 235 | */ |
<> | 135:176b8275d35d | 236 | __STATIC_INLINE void LL_PWR_DisableSDADC(uint32_t Analogx) |
<> | 135:176b8275d35d | 237 | { |
<> | 135:176b8275d35d | 238 | CLEAR_BIT(PWR->CR, Analogx); |
<> | 135:176b8275d35d | 239 | } |
<> | 135:176b8275d35d | 240 | |
<> | 135:176b8275d35d | 241 | /** |
<> | 135:176b8275d35d | 242 | * @brief Check if SDADCx has been enabled or not |
<> | 135:176b8275d35d | 243 | * @rmtoll CR ENSD1 LL_PWR_IsEnabledSDADC\n |
<> | 135:176b8275d35d | 244 | * CR ENSD2 LL_PWR_IsEnabledSDADC\n |
<> | 135:176b8275d35d | 245 | * CR ENSD3 LL_PWR_IsEnabledSDADC |
<> | 135:176b8275d35d | 246 | * @param Analogx This parameter can be a combination of the following values: |
<> | 135:176b8275d35d | 247 | * @arg @ref LL_PWR_SDADC_ANALOG1 |
<> | 135:176b8275d35d | 248 | * @arg @ref LL_PWR_SDADC_ANALOG2 |
<> | 135:176b8275d35d | 249 | * @arg @ref LL_PWR_SDADC_ANALOG3 |
<> | 135:176b8275d35d | 250 | * @retval None |
<> | 135:176b8275d35d | 251 | */ |
<> | 135:176b8275d35d | 252 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledSDADC(uint32_t Analogx) |
<> | 135:176b8275d35d | 253 | { |
<> | 135:176b8275d35d | 254 | return (READ_BIT(PWR->CR, Analogx) == (Analogx)); |
<> | 135:176b8275d35d | 255 | } |
<> | 135:176b8275d35d | 256 | |
<> | 135:176b8275d35d | 257 | /** |
<> | 135:176b8275d35d | 258 | * @brief Enable access to the backup domain |
<> | 135:176b8275d35d | 259 | * @rmtoll CR DBP LL_PWR_EnableBkUpAccess |
<> | 135:176b8275d35d | 260 | * @retval None |
<> | 135:176b8275d35d | 261 | */ |
<> | 135:176b8275d35d | 262 | __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) |
<> | 135:176b8275d35d | 263 | { |
<> | 135:176b8275d35d | 264 | SET_BIT(PWR->CR, PWR_CR_DBP); |
<> | 135:176b8275d35d | 265 | } |
<> | 135:176b8275d35d | 266 | |
<> | 135:176b8275d35d | 267 | /** |
<> | 135:176b8275d35d | 268 | * @brief Disable access to the backup domain |
<> | 135:176b8275d35d | 269 | * @rmtoll CR DBP LL_PWR_DisableBkUpAccess |
<> | 135:176b8275d35d | 270 | * @retval None |
<> | 135:176b8275d35d | 271 | */ |
<> | 135:176b8275d35d | 272 | __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) |
<> | 135:176b8275d35d | 273 | { |
<> | 135:176b8275d35d | 274 | CLEAR_BIT(PWR->CR, PWR_CR_DBP); |
<> | 135:176b8275d35d | 275 | } |
<> | 135:176b8275d35d | 276 | |
<> | 135:176b8275d35d | 277 | /** |
<> | 135:176b8275d35d | 278 | * @brief Check if the backup domain is enabled |
<> | 135:176b8275d35d | 279 | * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess |
<> | 135:176b8275d35d | 280 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 281 | */ |
<> | 135:176b8275d35d | 282 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) |
<> | 135:176b8275d35d | 283 | { |
<> | 135:176b8275d35d | 284 | return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); |
<> | 135:176b8275d35d | 285 | } |
<> | 135:176b8275d35d | 286 | |
<> | 135:176b8275d35d | 287 | #if defined(PWR_CR_LPDS) |
<> | 135:176b8275d35d | 288 | /** |
<> | 135:176b8275d35d | 289 | * @brief Set voltage regulator mode during deep sleep mode |
<> | 135:176b8275d35d | 290 | * @rmtoll CR LPDS LL_PWR_SetRegulModeDS |
<> | 135:176b8275d35d | 291 | * @param RegulMode This parameter can be one of the following values: |
<> | 135:176b8275d35d | 292 | * @arg @ref LL_PWR_REGU_DSMODE_MAIN |
<> | 135:176b8275d35d | 293 | * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER |
<> | 135:176b8275d35d | 294 | * @retval None |
<> | 135:176b8275d35d | 295 | */ |
<> | 135:176b8275d35d | 296 | __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) |
<> | 135:176b8275d35d | 297 | { |
<> | 135:176b8275d35d | 298 | MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); |
<> | 135:176b8275d35d | 299 | } |
<> | 135:176b8275d35d | 300 | |
<> | 135:176b8275d35d | 301 | /** |
<> | 135:176b8275d35d | 302 | * @brief Get voltage regulator mode during deep sleep mode |
<> | 135:176b8275d35d | 303 | * @rmtoll CR LPDS LL_PWR_GetRegulModeDS |
<> | 135:176b8275d35d | 304 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 305 | * @arg @ref LL_PWR_REGU_DSMODE_MAIN |
<> | 135:176b8275d35d | 306 | * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER |
<> | 135:176b8275d35d | 307 | */ |
<> | 135:176b8275d35d | 308 | __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) |
<> | 135:176b8275d35d | 309 | { |
<> | 135:176b8275d35d | 310 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); |
<> | 135:176b8275d35d | 311 | } |
<> | 135:176b8275d35d | 312 | #endif /* PWR_CR_LPDS */ |
<> | 135:176b8275d35d | 313 | |
<> | 135:176b8275d35d | 314 | /** |
<> | 135:176b8275d35d | 315 | * @brief Set power down mode when CPU enters deepsleep |
<> | 135:176b8275d35d | 316 | * @rmtoll CR PDDS LL_PWR_SetPowerMode\n |
<> | 135:176b8275d35d | 317 | * @rmtoll CR LPDS LL_PWR_SetPowerMode |
<> | 135:176b8275d35d | 318 | * @param PDMode This parameter can be one of the following values: |
<> | 135:176b8275d35d | 319 | * @arg @ref LL_PWR_MODE_STOP_MAINREGU |
<> | 135:176b8275d35d | 320 | * @arg @ref LL_PWR_MODE_STOP_LPREGU |
<> | 135:176b8275d35d | 321 | * @arg @ref LL_PWR_MODE_STANDBY |
<> | 135:176b8275d35d | 322 | * @retval None |
<> | 135:176b8275d35d | 323 | */ |
<> | 135:176b8275d35d | 324 | __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) |
<> | 135:176b8275d35d | 325 | { |
<> | 135:176b8275d35d | 326 | MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode); |
<> | 135:176b8275d35d | 327 | } |
<> | 135:176b8275d35d | 328 | |
<> | 135:176b8275d35d | 329 | /** |
<> | 135:176b8275d35d | 330 | * @brief Get power down mode when CPU enters deepsleep |
<> | 135:176b8275d35d | 331 | * @rmtoll CR PDDS LL_PWR_GetPowerMode\n |
<> | 135:176b8275d35d | 332 | * @rmtoll CR LPDS LL_PWR_GetPowerMode |
<> | 135:176b8275d35d | 333 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 334 | * @arg @ref LL_PWR_MODE_STOP_MAINREGU |
<> | 135:176b8275d35d | 335 | * @arg @ref LL_PWR_MODE_STOP_LPREGU |
<> | 135:176b8275d35d | 336 | * @arg @ref LL_PWR_MODE_STANDBY |
<> | 135:176b8275d35d | 337 | */ |
<> | 135:176b8275d35d | 338 | __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) |
<> | 135:176b8275d35d | 339 | { |
<> | 135:176b8275d35d | 340 | return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); |
<> | 135:176b8275d35d | 341 | } |
<> | 135:176b8275d35d | 342 | |
<> | 135:176b8275d35d | 343 | #if defined(PWR_PVD_SUPPORT) |
<> | 135:176b8275d35d | 344 | /** |
<> | 135:176b8275d35d | 345 | * @brief Configure the voltage threshold detected by the Power Voltage Detector |
<> | 135:176b8275d35d | 346 | * @rmtoll CR PLS LL_PWR_SetPVDLevel |
<> | 135:176b8275d35d | 347 | * @param PVDLevel This parameter can be one of the following values: |
<> | 135:176b8275d35d | 348 | * @arg @ref LL_PWR_PVDLEVEL_0 |
<> | 135:176b8275d35d | 349 | * @arg @ref LL_PWR_PVDLEVEL_1 |
<> | 135:176b8275d35d | 350 | * @arg @ref LL_PWR_PVDLEVEL_2 |
<> | 135:176b8275d35d | 351 | * @arg @ref LL_PWR_PVDLEVEL_3 |
<> | 135:176b8275d35d | 352 | * @arg @ref LL_PWR_PVDLEVEL_4 |
<> | 135:176b8275d35d | 353 | * @arg @ref LL_PWR_PVDLEVEL_5 |
<> | 135:176b8275d35d | 354 | * @arg @ref LL_PWR_PVDLEVEL_6 |
<> | 135:176b8275d35d | 355 | * @arg @ref LL_PWR_PVDLEVEL_7 |
<> | 135:176b8275d35d | 356 | * @retval None |
<> | 135:176b8275d35d | 357 | */ |
<> | 135:176b8275d35d | 358 | __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) |
<> | 135:176b8275d35d | 359 | { |
<> | 135:176b8275d35d | 360 | MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); |
<> | 135:176b8275d35d | 361 | } |
<> | 135:176b8275d35d | 362 | |
<> | 135:176b8275d35d | 363 | /** |
<> | 135:176b8275d35d | 364 | * @brief Get the voltage threshold detection |
<> | 135:176b8275d35d | 365 | * @rmtoll CR PLS LL_PWR_GetPVDLevel |
<> | 135:176b8275d35d | 366 | * @retval Returned value can be one of the following values: |
<> | 135:176b8275d35d | 367 | * @arg @ref LL_PWR_PVDLEVEL_0 |
<> | 135:176b8275d35d | 368 | * @arg @ref LL_PWR_PVDLEVEL_1 |
<> | 135:176b8275d35d | 369 | * @arg @ref LL_PWR_PVDLEVEL_2 |
<> | 135:176b8275d35d | 370 | * @arg @ref LL_PWR_PVDLEVEL_3 |
<> | 135:176b8275d35d | 371 | * @arg @ref LL_PWR_PVDLEVEL_4 |
<> | 135:176b8275d35d | 372 | * @arg @ref LL_PWR_PVDLEVEL_5 |
<> | 135:176b8275d35d | 373 | * @arg @ref LL_PWR_PVDLEVEL_6 |
<> | 135:176b8275d35d | 374 | * @arg @ref LL_PWR_PVDLEVEL_7 |
<> | 135:176b8275d35d | 375 | */ |
<> | 135:176b8275d35d | 376 | __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) |
<> | 135:176b8275d35d | 377 | { |
<> | 135:176b8275d35d | 378 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); |
<> | 135:176b8275d35d | 379 | } |
<> | 135:176b8275d35d | 380 | |
<> | 135:176b8275d35d | 381 | /** |
<> | 135:176b8275d35d | 382 | * @brief Enable Power Voltage Detector |
<> | 135:176b8275d35d | 383 | * @rmtoll CR PVDE LL_PWR_EnablePVD |
<> | 135:176b8275d35d | 384 | * @retval None |
<> | 135:176b8275d35d | 385 | */ |
<> | 135:176b8275d35d | 386 | __STATIC_INLINE void LL_PWR_EnablePVD(void) |
<> | 135:176b8275d35d | 387 | { |
<> | 135:176b8275d35d | 388 | SET_BIT(PWR->CR, PWR_CR_PVDE); |
<> | 135:176b8275d35d | 389 | } |
<> | 135:176b8275d35d | 390 | |
<> | 135:176b8275d35d | 391 | /** |
<> | 135:176b8275d35d | 392 | * @brief Disable Power Voltage Detector |
<> | 135:176b8275d35d | 393 | * @rmtoll CR PVDE LL_PWR_DisablePVD |
<> | 135:176b8275d35d | 394 | * @retval None |
<> | 135:176b8275d35d | 395 | */ |
<> | 135:176b8275d35d | 396 | __STATIC_INLINE void LL_PWR_DisablePVD(void) |
<> | 135:176b8275d35d | 397 | { |
<> | 135:176b8275d35d | 398 | CLEAR_BIT(PWR->CR, PWR_CR_PVDE); |
<> | 135:176b8275d35d | 399 | } |
<> | 135:176b8275d35d | 400 | |
<> | 135:176b8275d35d | 401 | /** |
<> | 135:176b8275d35d | 402 | * @brief Check if Power Voltage Detector is enabled |
<> | 135:176b8275d35d | 403 | * @rmtoll CR PVDE LL_PWR_IsEnabledPVD |
<> | 135:176b8275d35d | 404 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 405 | */ |
<> | 135:176b8275d35d | 406 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) |
<> | 135:176b8275d35d | 407 | { |
<> | 135:176b8275d35d | 408 | return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); |
<> | 135:176b8275d35d | 409 | } |
<> | 135:176b8275d35d | 410 | #endif /* PWR_PVD_SUPPORT */ |
<> | 135:176b8275d35d | 411 | |
<> | 135:176b8275d35d | 412 | /** |
<> | 135:176b8275d35d | 413 | * @brief Enable the WakeUp PINx functionality |
<> | 135:176b8275d35d | 414 | * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n |
<> | 135:176b8275d35d | 415 | * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n |
<> | 135:176b8275d35d | 416 | * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin |
<> | 135:176b8275d35d | 417 | * @param WakeUpPin This parameter can be one of the following values: |
<> | 135:176b8275d35d | 418 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
<> | 135:176b8275d35d | 419 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
<> | 135:176b8275d35d | 420 | * @arg @ref LL_PWR_WAKEUP_PIN3 (*) |
<> | 135:176b8275d35d | 421 | * |
<> | 135:176b8275d35d | 422 | * (*) not available on all devices |
<> | 135:176b8275d35d | 423 | * @retval None |
<> | 135:176b8275d35d | 424 | */ |
<> | 135:176b8275d35d | 425 | __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) |
<> | 135:176b8275d35d | 426 | { |
<> | 135:176b8275d35d | 427 | SET_BIT(PWR->CSR, WakeUpPin); |
<> | 135:176b8275d35d | 428 | } |
<> | 135:176b8275d35d | 429 | |
<> | 135:176b8275d35d | 430 | /** |
<> | 135:176b8275d35d | 431 | * @brief Disable the WakeUp PINx functionality |
<> | 135:176b8275d35d | 432 | * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n |
<> | 135:176b8275d35d | 433 | * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n |
<> | 135:176b8275d35d | 434 | * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin |
<> | 135:176b8275d35d | 435 | * @param WakeUpPin This parameter can be one of the following values: |
<> | 135:176b8275d35d | 436 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
<> | 135:176b8275d35d | 437 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
<> | 135:176b8275d35d | 438 | * @arg @ref LL_PWR_WAKEUP_PIN3 (*) |
<> | 135:176b8275d35d | 439 | * |
<> | 135:176b8275d35d | 440 | * (*) not available on all devices |
<> | 135:176b8275d35d | 441 | * @retval None |
<> | 135:176b8275d35d | 442 | */ |
<> | 135:176b8275d35d | 443 | __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) |
<> | 135:176b8275d35d | 444 | { |
<> | 135:176b8275d35d | 445 | CLEAR_BIT(PWR->CSR, WakeUpPin); |
<> | 135:176b8275d35d | 446 | } |
<> | 135:176b8275d35d | 447 | |
<> | 135:176b8275d35d | 448 | /** |
<> | 135:176b8275d35d | 449 | * @brief Check if the WakeUp PINx functionality is enabled |
<> | 135:176b8275d35d | 450 | * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n |
<> | 135:176b8275d35d | 451 | * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n |
<> | 135:176b8275d35d | 452 | * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin |
<> | 135:176b8275d35d | 453 | * @param WakeUpPin This parameter can be one of the following values: |
<> | 135:176b8275d35d | 454 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
<> | 135:176b8275d35d | 455 | * @arg @ref LL_PWR_WAKEUP_PIN2 |
<> | 135:176b8275d35d | 456 | * @arg @ref LL_PWR_WAKEUP_PIN3 (*) |
<> | 135:176b8275d35d | 457 | * |
<> | 135:176b8275d35d | 458 | * (*) not available on all devices |
<> | 135:176b8275d35d | 459 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 460 | */ |
<> | 135:176b8275d35d | 461 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) |
<> | 135:176b8275d35d | 462 | { |
<> | 135:176b8275d35d | 463 | return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); |
<> | 135:176b8275d35d | 464 | } |
<> | 135:176b8275d35d | 465 | |
<> | 135:176b8275d35d | 466 | |
<> | 135:176b8275d35d | 467 | /** |
<> | 135:176b8275d35d | 468 | * @} |
<> | 135:176b8275d35d | 469 | */ |
<> | 135:176b8275d35d | 470 | |
<> | 135:176b8275d35d | 471 | /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management |
<> | 135:176b8275d35d | 472 | * @{ |
<> | 135:176b8275d35d | 473 | */ |
<> | 135:176b8275d35d | 474 | |
<> | 135:176b8275d35d | 475 | /** |
<> | 135:176b8275d35d | 476 | * @brief Get Wake-up Flag |
<> | 135:176b8275d35d | 477 | * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU |
<> | 135:176b8275d35d | 478 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 479 | */ |
<> | 135:176b8275d35d | 480 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) |
<> | 135:176b8275d35d | 481 | { |
<> | 135:176b8275d35d | 482 | return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); |
<> | 135:176b8275d35d | 483 | } |
<> | 135:176b8275d35d | 484 | |
<> | 135:176b8275d35d | 485 | /** |
<> | 135:176b8275d35d | 486 | * @brief Get Standby Flag |
<> | 135:176b8275d35d | 487 | * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB |
<> | 135:176b8275d35d | 488 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 489 | */ |
<> | 135:176b8275d35d | 490 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) |
<> | 135:176b8275d35d | 491 | { |
<> | 135:176b8275d35d | 492 | return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); |
<> | 135:176b8275d35d | 493 | } |
<> | 135:176b8275d35d | 494 | |
<> | 135:176b8275d35d | 495 | #if defined(PWR_PVD_SUPPORT) |
<> | 135:176b8275d35d | 496 | /** |
<> | 135:176b8275d35d | 497 | * @brief Indicate whether VDD voltage is below the selected PVD threshold |
<> | 135:176b8275d35d | 498 | * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO |
<> | 135:176b8275d35d | 499 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 500 | */ |
<> | 135:176b8275d35d | 501 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) |
<> | 135:176b8275d35d | 502 | { |
<> | 135:176b8275d35d | 503 | return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); |
<> | 135:176b8275d35d | 504 | } |
<> | 135:176b8275d35d | 505 | #endif /* PWR_PVD_SUPPORT */ |
<> | 135:176b8275d35d | 506 | |
<> | 135:176b8275d35d | 507 | #if defined(PWR_CSR_VREFINTRDYF) |
<> | 135:176b8275d35d | 508 | /** |
<> | 135:176b8275d35d | 509 | * @brief Get Internal Reference VrefInt Flag |
<> | 135:176b8275d35d | 510 | * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY |
<> | 135:176b8275d35d | 511 | * @retval State of bit (1 or 0). |
<> | 135:176b8275d35d | 512 | */ |
<> | 135:176b8275d35d | 513 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void) |
<> | 135:176b8275d35d | 514 | { |
<> | 135:176b8275d35d | 515 | return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF)); |
<> | 135:176b8275d35d | 516 | } |
<> | 135:176b8275d35d | 517 | #endif /* PWR_CSR_VREFINTRDYF */ |
<> | 135:176b8275d35d | 518 | /** |
<> | 135:176b8275d35d | 519 | * @brief Clear Standby Flag |
<> | 135:176b8275d35d | 520 | * @rmtoll CR CSBF LL_PWR_ClearFlag_SB |
<> | 135:176b8275d35d | 521 | * @retval None |
<> | 135:176b8275d35d | 522 | */ |
<> | 135:176b8275d35d | 523 | __STATIC_INLINE void LL_PWR_ClearFlag_SB(void) |
<> | 135:176b8275d35d | 524 | { |
<> | 135:176b8275d35d | 525 | SET_BIT(PWR->CR, PWR_CR_CSBF); |
<> | 135:176b8275d35d | 526 | } |
<> | 135:176b8275d35d | 527 | |
<> | 135:176b8275d35d | 528 | /** |
<> | 135:176b8275d35d | 529 | * @brief Clear Wake-up Flags |
<> | 135:176b8275d35d | 530 | * @rmtoll CR CWUF LL_PWR_ClearFlag_WU |
<> | 135:176b8275d35d | 531 | * @retval None |
<> | 135:176b8275d35d | 532 | */ |
<> | 135:176b8275d35d | 533 | __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) |
<> | 135:176b8275d35d | 534 | { |
<> | 135:176b8275d35d | 535 | SET_BIT(PWR->CR, PWR_CR_CWUF); |
<> | 135:176b8275d35d | 536 | } |
<> | 135:176b8275d35d | 537 | #if defined(USE_FULL_LL_DRIVER) |
<> | 135:176b8275d35d | 538 | /** @defgroup PWR_LL_EF_Init De-initialization function |
<> | 135:176b8275d35d | 539 | * @{ |
<> | 135:176b8275d35d | 540 | */ |
<> | 135:176b8275d35d | 541 | ErrorStatus LL_PWR_DeInit(void); |
<> | 135:176b8275d35d | 542 | /** |
<> | 135:176b8275d35d | 543 | * @} |
<> | 135:176b8275d35d | 544 | */ |
<> | 135:176b8275d35d | 545 | #endif /* USE_FULL_LL_DRIVER */ |
<> | 135:176b8275d35d | 546 | |
<> | 135:176b8275d35d | 547 | /** |
<> | 135:176b8275d35d | 548 | * @} |
<> | 135:176b8275d35d | 549 | */ |
<> | 135:176b8275d35d | 550 | |
<> | 135:176b8275d35d | 551 | /** |
<> | 135:176b8275d35d | 552 | * @} |
<> | 135:176b8275d35d | 553 | */ |
<> | 135:176b8275d35d | 554 | |
<> | 135:176b8275d35d | 555 | /** |
<> | 135:176b8275d35d | 556 | * @} |
<> | 135:176b8275d35d | 557 | */ |
<> | 135:176b8275d35d | 558 | |
<> | 135:176b8275d35d | 559 | #endif /* defined(PWR) */ |
<> | 135:176b8275d35d | 560 | |
<> | 135:176b8275d35d | 561 | /** |
<> | 135:176b8275d35d | 562 | * @} |
<> | 135:176b8275d35d | 563 | */ |
<> | 135:176b8275d35d | 564 | |
<> | 135:176b8275d35d | 565 | #ifdef __cplusplus |
<> | 135:176b8275d35d | 566 | } |
<> | 135:176b8275d35d | 567 | #endif |
<> | 135:176b8275d35d | 568 | |
<> | 135:176b8275d35d | 569 | #endif /* __STM32F3xx_LL_PWR_H */ |
<> | 135:176b8275d35d | 570 | |
<> | 135:176b8275d35d | 571 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |