mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F334R8/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_i2c.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:30:20 2017 +0100
Revision:: 143:86740a56073b
Parent:: 135:176b8275d35d
Child:: 168:b9e159c1930a

Release 143 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	135:176b8275d35d	1	/**
<>	135:176b8275d35d	2	******************************************************************************
<>	135:176b8275d35d	3	* @file stm32f3xx_ll_i2c.h
<>	135:176b8275d35d	4	* @author MCD Application Team
<>	135:176b8275d35d	5	* @version V1.4.0
<>	135:176b8275d35d	6	* @date 16-December-2016
<>	135:176b8275d35d	7	* @brief Header file of I2C LL module.
<>	135:176b8275d35d	8	******************************************************************************
<>	135:176b8275d35d	9	* @attention
<>	135:176b8275d35d	10	*
<>	135:176b8275d35d	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	135:176b8275d35d	12	*
<>	135:176b8275d35d	13	* Redistribution and use in source and binary forms, with or without modification,
<>	135:176b8275d35d	14	* are permitted provided that the following conditions are met:
<>	135:176b8275d35d	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	135:176b8275d35d	16	* this list of conditions and the following disclaimer.
<>	135:176b8275d35d	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	135:176b8275d35d	18	* this list of conditions and the following disclaimer in the documentation
<>	135:176b8275d35d	19	* and/or other materials provided with the distribution.
<>	135:176b8275d35d	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	135:176b8275d35d	21	* may be used to endorse or promote products derived from this software
<>	135:176b8275d35d	22	* without specific prior written permission.
<>	135:176b8275d35d	23	*
<>	135:176b8275d35d	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	135:176b8275d35d	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	135:176b8275d35d	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	135:176b8275d35d	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	135:176b8275d35d	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	135:176b8275d35d	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	135:176b8275d35d	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	135:176b8275d35d	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	135:176b8275d35d	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	135:176b8275d35d	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	135:176b8275d35d	34	*
<>	135:176b8275d35d	35	******************************************************************************
<>	135:176b8275d35d	36	*/
<>	135:176b8275d35d	37
<>	135:176b8275d35d	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	135:176b8275d35d	39	#ifndef __STM32F3xx_LL_I2C_H
<>	135:176b8275d35d	40	#define __STM32F3xx_LL_I2C_H
<>	135:176b8275d35d	41
<>	135:176b8275d35d	42	#ifdef __cplusplus
<>	135:176b8275d35d	43	extern "C" {
<>	135:176b8275d35d	44	#endif
<>	135:176b8275d35d	45
<>	135:176b8275d35d	46	/* Includes ------------------------------------------------------------------*/
<>	135:176b8275d35d	47	#include "stm32f3xx.h"
<>	135:176b8275d35d	48
<>	135:176b8275d35d	49	/** @addtogroup STM32F3xx_LL_Driver
<>	135:176b8275d35d	50	* @{
<>	135:176b8275d35d	51	*/
<>	135:176b8275d35d	52
<>	135:176b8275d35d	53	#if defined (I2C1) \|\| defined (I2C2) \|\| defined (I2C3)
<>	135:176b8275d35d	54
<>	135:176b8275d35d	55	/** @defgroup I2C_LL I2C
<>	135:176b8275d35d	56	* @{
<>	135:176b8275d35d	57	*/
<>	135:176b8275d35d	58
<>	135:176b8275d35d	59	/* Private types -------------------------------------------------------------*/
<>	135:176b8275d35d	60	/* Private variables ---------------------------------------------------------*/
<>	135:176b8275d35d	61
<>	135:176b8275d35d	62	/* Private constants ---------------------------------------------------------*/
<>	135:176b8275d35d	63	/** @defgroup I2C_LL_Private_Constants I2C Private Constants
<>	135:176b8275d35d	64	* @{
<>	135:176b8275d35d	65	*/
<>	135:176b8275d35d	66	/**
<>	135:176b8275d35d	67	* @}
<>	135:176b8275d35d	68	*/
<>	135:176b8275d35d	69
<>	135:176b8275d35d	70	/* Private macros ------------------------------------------------------------*/
<>	135:176b8275d35d	71	#if defined(USE_FULL_LL_DRIVER)
<>	135:176b8275d35d	72	/** @defgroup I2C_LL_Private_Macros I2C Private Macros
<>	135:176b8275d35d	73	* @{
<>	135:176b8275d35d	74	*/
<>	135:176b8275d35d	75	/**
<>	135:176b8275d35d	76	* @}
<>	135:176b8275d35d	77	*/
<>	135:176b8275d35d	78	#endif /USE_FULL_LL_DRIVER/
<>	135:176b8275d35d	79
<>	135:176b8275d35d	80	/* Exported types ------------------------------------------------------------*/
<>	135:176b8275d35d	81	#if defined(USE_FULL_LL_DRIVER)
<>	135:176b8275d35d	82	/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
<>	135:176b8275d35d	83	* @{
<>	135:176b8275d35d	84	*/
<>	135:176b8275d35d	85	typedef struct
<>	135:176b8275d35d	86	{
<>	135:176b8275d35d	87	uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
<>	135:176b8275d35d	88	This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
<>	135:176b8275d35d	89
<>	135:176b8275d35d	90	This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
<>	135:176b8275d35d	91
<>	135:176b8275d35d	92	uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
<>	135:176b8275d35d	93	This parameter must be set by referring to the STM32CubeMX Tool and
<>	135:176b8275d35d	94	the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
<>	135:176b8275d35d	95
<>	135:176b8275d35d	96	This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
<>	135:176b8275d35d	97
<>	135:176b8275d35d	98	uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
<>	135:176b8275d35d	99	This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
<>	135:176b8275d35d	100
<>	135:176b8275d35d	101	This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
<>	135:176b8275d35d	102
<>	135:176b8275d35d	103	uint32_t DigitalFilter; /*!< Configures the digital noise filter.
<>	135:176b8275d35d	104	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
<>	135:176b8275d35d	105
<>	135:176b8275d35d	106	This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
<>	135:176b8275d35d	107
<>	135:176b8275d35d	108	uint32_t OwnAddress1; /*!< Specifies the device own address 1.
<>	135:176b8275d35d	109	This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
<>	135:176b8275d35d	110
<>	135:176b8275d35d	111	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
<>	135:176b8275d35d	112
<>	135:176b8275d35d	113	uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
<>	135:176b8275d35d	114	This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
<>	135:176b8275d35d	115
<>	135:176b8275d35d	116	This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
<>	135:176b8275d35d	117
<>	135:176b8275d35d	118	uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
<>	135:176b8275d35d	119	This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
<>	135:176b8275d35d	120
<>	135:176b8275d35d	121	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
<>	135:176b8275d35d	122	} LL_I2C_InitTypeDef;
<>	135:176b8275d35d	123	/**
<>	135:176b8275d35d	124	* @}
<>	135:176b8275d35d	125	*/
<>	135:176b8275d35d	126	#endif /USE_FULL_LL_DRIVER/
<>	135:176b8275d35d	127
<>	135:176b8275d35d	128	/* Exported constants --------------------------------------------------------*/
<>	135:176b8275d35d	129	/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
<>	135:176b8275d35d	130	* @{
<>	135:176b8275d35d	131	*/
<>	135:176b8275d35d	132
<>	135:176b8275d35d	133	/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
<>	135:176b8275d35d	134	* @brief Flags defines which can be used with LL_I2C_WriteReg function
<>	135:176b8275d35d	135	* @{
<>	135:176b8275d35d	136	*/
<>	135:176b8275d35d	137	#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /!< Address Matched flag /
<>	135:176b8275d35d	138	#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /!< Not Acknowledge flag /
<>	135:176b8275d35d	139	#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /!< Stop detection flag /
<>	135:176b8275d35d	140	#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /!< Bus error flag /
<>	135:176b8275d35d	141	#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /!< Arbitration Lost flag /
<>	135:176b8275d35d	142	#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /!< Overrun/Underrun flag /
<>	135:176b8275d35d	143	#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /!< PEC error flag /
<>	135:176b8275d35d	144	#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /!< Timeout detection flag /
<>	135:176b8275d35d	145	#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /!< Alert flag /
<>	135:176b8275d35d	146	/**
<>	135:176b8275d35d	147	* @}
<>	135:176b8275d35d	148	*/
<>	135:176b8275d35d	149
<>	135:176b8275d35d	150	/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
<>	135:176b8275d35d	151	* @brief Flags defines which can be used with LL_I2C_ReadReg function
<>	135:176b8275d35d	152	* @{
<>	135:176b8275d35d	153	*/
<>	135:176b8275d35d	154	#define LL_I2C_ISR_TXE I2C_ISR_TXE /!< Transmit data register empty /
<>	135:176b8275d35d	155	#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /!< Transmit interrupt status /
<>	135:176b8275d35d	156	#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /!< Receive data register not empty /
<>	135:176b8275d35d	157	#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /!< Address matched (slave mode) /
<>	135:176b8275d35d	158	#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /!< Not Acknowledge received flag /
<>	135:176b8275d35d	159	#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /!< Stop detection flag /
<>	135:176b8275d35d	160	#define LL_I2C_ISR_TC I2C_ISR_TC /!< Transfer Complete (master mode) /
<>	135:176b8275d35d	161	#define LL_I2C_ISR_TCR I2C_ISR_TCR /!< Transfer Complete Reload /
<>	135:176b8275d35d	162	#define LL_I2C_ISR_BERR I2C_ISR_BERR /!< Bus error /
<>	135:176b8275d35d	163	#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /!< Arbitration lost /
<>	135:176b8275d35d	164	#define LL_I2C_ISR_OVR I2C_ISR_OVR /!< Overrun/Underrun (slave mode) /
<>	135:176b8275d35d	165	#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /!< PEC Error in reception (SMBus mode) /
<>	135:176b8275d35d	166	#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /!< Timeout detection flag (SMBus mode) /
<>	135:176b8275d35d	167	#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /!< SMBus alert (SMBus mode) /
<>	135:176b8275d35d	168	#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /!< Bus busy /
<>	135:176b8275d35d	169	/**
<>	135:176b8275d35d	170	* @}
<>	135:176b8275d35d	171	*/
<>	135:176b8275d35d	172
<>	135:176b8275d35d	173	/** @defgroup I2C_LL_EC_IT IT Defines
<>	135:176b8275d35d	174	* @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
<>	135:176b8275d35d	175	* @{
<>	135:176b8275d35d	176	*/
<>	135:176b8275d35d	177	#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /!< TX Interrupt enable /
<>	135:176b8275d35d	178	#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /!< RX Interrupt enable /
<>	135:176b8275d35d	179	#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /!< Address match Interrupt enable (slave only) /
<>	135:176b8275d35d	180	#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /!< Not acknowledge received Interrupt enable /
<>	135:176b8275d35d	181	#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /!< STOP detection Interrupt enable /
<>	135:176b8275d35d	182	#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /!< Transfer Complete interrupt enable /
<>	135:176b8275d35d	183	#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /!< Error interrupts enable /
<>	135:176b8275d35d	184	/**
<>	135:176b8275d35d	185	* @}
<>	135:176b8275d35d	186	*/
<>	135:176b8275d35d	187
<>	135:176b8275d35d	188	/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
<>	135:176b8275d35d	189	* @{
<>	135:176b8275d35d	190	*/
<>	135:176b8275d35d	191	#define LL_I2C_MODE_I2C ((uint32_t)0x00000000U) /!< I2C Master or Slave mode /
<>	135:176b8275d35d	192	#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /!< SMBus Host address acknowledge /
<>	135:176b8275d35d	193	#define LL_I2C_MODE_SMBUS_DEVICE ((uint32_t)0x00000000U) /!< SMBus Device default mode (Default address not acknowledge) /
<>	135:176b8275d35d	194	#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /!< SMBus Device Default address acknowledge /
<>	135:176b8275d35d	195	/**
<>	135:176b8275d35d	196	* @}
<>	135:176b8275d35d	197	*/
<>	135:176b8275d35d	198
<>	135:176b8275d35d	199	/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
<>	135:176b8275d35d	200	* @{
<>	135:176b8275d35d	201	*/
<>	135:176b8275d35d	202	#define LL_I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U) /!< Analog filter is enabled. /
<>	135:176b8275d35d	203	#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /!< Analog filter is disabled. /
<>	135:176b8275d35d	204	/**
<>	135:176b8275d35d	205	* @}
<>	135:176b8275d35d	206	*/
<>	135:176b8275d35d	207
<>	135:176b8275d35d	208	/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
<>	135:176b8275d35d	209	* @{
<>	135:176b8275d35d	210	*/
<>	135:176b8275d35d	211	#define LL_I2C_ADDRESSING_MODE_7BIT ((uint32_t) 0x00000000U) /!< Master operates in 7-bit addressing mode. /
<>	135:176b8275d35d	212	#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /!< Master operates in 10-bit addressing mode./
<>	135:176b8275d35d	213	/**
<>	135:176b8275d35d	214	* @}
<>	135:176b8275d35d	215	*/
<>	135:176b8275d35d	216
<>	135:176b8275d35d	217	/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
<>	135:176b8275d35d	218	* @{
<>	135:176b8275d35d	219	*/
<>	135:176b8275d35d	220	#define LL_I2C_OWNADDRESS1_7BIT ((uint32_t)0x00000000U) /!< Own address 1 is a 7-bit address. /
<>	135:176b8275d35d	221	#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /!< Own address 1 is a 10-bit address./
<>	135:176b8275d35d	222	/**
<>	135:176b8275d35d	223	* @}
<>	135:176b8275d35d	224	*/
<>	135:176b8275d35d	225
<>	135:176b8275d35d	226	/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
<>	135:176b8275d35d	227	* @{
<>	135:176b8275d35d	228	*/
<>	135:176b8275d35d	229	#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /!< Own Address2 No mask. /
<>	135:176b8275d35d	230	#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /!< Only Address2 bits[7:2] are compared. /
<>	135:176b8275d35d	231	#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /!< Only Address2 bits[7:3] are compared. /
<>	135:176b8275d35d	232	#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /!< Only Address2 bits[7:4] are compared. /
<>	135:176b8275d35d	233	#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /!< Only Address2 bits[7:5] are compared. /
<>	135:176b8275d35d	234	#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /!< Only Address2 bits[7:6] are compared. /
<>	135:176b8275d35d	235	#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /!< Only Address2 bits[7] are compared. /
<>	135:176b8275d35d	236	#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /!< No comparison is done. All Address2 are acknowledged./
<>	135:176b8275d35d	237	/**
<>	135:176b8275d35d	238	* @}
<>	135:176b8275d35d	239	*/
<>	135:176b8275d35d	240
<>	135:176b8275d35d	241	/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
<>	135:176b8275d35d	242	* @{
<>	135:176b8275d35d	243	*/
<>	135:176b8275d35d	244	#define LL_I2C_ACK ((uint32_t) 0x00000000U) /!< ACK is sent after current received byte. /
<>	135:176b8275d35d	245	#define LL_I2C_NACK I2C_CR2_NACK /!< NACK is sent after current received byte./
<>	135:176b8275d35d	246	/**
<>	135:176b8275d35d	247	* @}
<>	135:176b8275d35d	248	*/
<>	135:176b8275d35d	249
<>	135:176b8275d35d	250	/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
<>	135:176b8275d35d	251	* @{
<>	135:176b8275d35d	252	*/
<>	135:176b8275d35d	253	#define LL_I2C_ADDRSLAVE_7BIT ((uint32_t)0x00000000U) /!< Slave Address in 7-bit. /
<>	135:176b8275d35d	254	#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /!< Slave Address in 10-bit./
<>	135:176b8275d35d	255	/**
<>	135:176b8275d35d	256	* @}
<>	135:176b8275d35d	257	*/
<>	135:176b8275d35d	258
<>	135:176b8275d35d	259	/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
<>	135:176b8275d35d	260	* @{
<>	135:176b8275d35d	261	*/
<>	135:176b8275d35d	262	#define LL_I2C_REQUEST_WRITE ((uint32_t)0x00000000U) /!< Master request a write transfer. /
<>	135:176b8275d35d	263	#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /!< Master request a read transfer. /
<>	135:176b8275d35d	264	/**
<>	135:176b8275d35d	265	* @}
<>	135:176b8275d35d	266	*/
<>	135:176b8275d35d	267
<>	135:176b8275d35d	268	/** @defgroup I2C_LL_EC_MODE Transfer End Mode
<>	135:176b8275d35d	269	* @{
<>	135:176b8275d35d	270	*/
<>	135:176b8275d35d	271	#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /!< Enable I2C Reload mode. /
<>	135:176b8275d35d	272	#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /!< Enable I2C Automatic end mode with no HW PEC comparison. /
<>	135:176b8275d35d	273	#define LL_I2C_MODE_SOFTEND ((uint32_t)0x00000000U) /!< Enable I2C Software end mode with no HW PEC comparison. /
<>	135:176b8275d35d	274	#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /!< Enable SMBUS Automatic end mode with HW PEC comparison. /
<>	135:176b8275d35d	275	#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /!< Enable SMBUS Automatic end mode with HW PEC comparison. /
<>	135:176b8275d35d	276	#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /!< Enable SMBUS Software end mode with HW PEC comparison. /
<>	135:176b8275d35d	277	#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND \| I2C_CR2_PECBYTE) /!< Enable SMBUS Automatic end mode with HW PEC comparison. /
<>	135:176b8275d35d	278	#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND \| I2C_CR2_PECBYTE) /!< Enable SMBUS Software end mode with HW PEC comparison. /
<>	135:176b8275d35d	279	/**
<>	135:176b8275d35d	280	* @}
<>	135:176b8275d35d	281	*/
<>	135:176b8275d35d	282
<>	135:176b8275d35d	283	/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
<>	135:176b8275d35d	284	* @{
<>	135:176b8275d35d	285	*/
<>	135:176b8275d35d	286	#define LL_I2C_GENERATE_NOSTARTSTOP ((uint32_t)0x00000000U) /!< Don't Generate Stop and Start condition. /
<>	135:176b8275d35d	287	#define LL_I2C_GENERATE_STOP I2C_CR2_STOP /!< Generate Stop condition (Size should be set to 0). /
<>	135:176b8275d35d	288	#define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START \| I2C_CR2_RD_WRN) /!< Generate Start for read request. /
<>	135:176b8275d35d	289	#define LL_I2C_GENERATE_START_WRITE I2C_CR2_START /!< Generate Start for write request. /
<>	135:176b8275d35d	290	#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START \| I2C_CR2_RD_WRN) /!< Generate Restart for read request, slave 7Bit address. /
<>	135:176b8275d35d	291	#define LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START /!< Generate Restart for write request, slave 7Bit address. /
<>	135:176b8275d35d	292	#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START \| I2C_CR2_RD_WRN \| I2C_CR2_HEAD10R) /!< Generate Restart for read request, slave 10Bit address. /
<>	135:176b8275d35d	293	#define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START /!< Generate Restart for write request, slave 10Bit address./
<>	135:176b8275d35d	294	/**
<>	135:176b8275d35d	295	* @}
<>	135:176b8275d35d	296	*/
<>	135:176b8275d35d	297
<>	135:176b8275d35d	298	/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
<>	135:176b8275d35d	299	* @{
<>	135:176b8275d35d	300	*/
<>	135:176b8275d35d	301	#define LL_I2C_DIRECTION_WRITE ((uint32_t)0x00000000U) /!< Write transfer request by master, slave enters receiver mode. /
<>	135:176b8275d35d	302	#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /!< Read transfer request by master, slave enters transmitter mode./
<>	135:176b8275d35d	303	/**
<>	135:176b8275d35d	304	* @}
<>	135:176b8275d35d	305	*/
<>	135:176b8275d35d	306
<>	135:176b8275d35d	307	/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
<>	135:176b8275d35d	308	* @{
<>	135:176b8275d35d	309	*/
<>	135:176b8275d35d	310	#define LL_I2C_DMA_REG_DATA_TRANSMIT ((uint32_t)0x00000000U) /!< Get address of data register used for transmission /
<>	135:176b8275d35d	311	#define LL_I2C_DMA_REG_DATA_RECEIVE ((uint32_t)0x00000001U) /!< Get address of data register used for reception /
<>	135:176b8275d35d	312	/**
<>	135:176b8275d35d	313	* @}
<>	135:176b8275d35d	314	*/
<>	135:176b8275d35d	315
<>	135:176b8275d35d	316	/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
<>	135:176b8275d35d	317	* @{
<>	135:176b8275d35d	318	*/
<>	135:176b8275d35d	319	#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW ((uint32_t) 0x00000000U) /!< TimeoutA is used to detect SCL low level timeout. /
<>	135:176b8275d35d	320	#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /!< TimeoutA is used to detect both SCL and SDA high level timeout./
<>	135:176b8275d35d	321	/**
<>	135:176b8275d35d	322	* @}
<>	135:176b8275d35d	323	*/
<>	135:176b8275d35d	324
<>	135:176b8275d35d	325	/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
<>	135:176b8275d35d	326	* @{
<>	135:176b8275d35d	327	*/
<>	135:176b8275d35d	328	#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /!< TimeoutA enable bit /
<>	135:176b8275d35d	329	#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /!< TimeoutB (extended clock) enable bit /
<>	135:176b8275d35d	330	#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN \| I2C_TIMEOUTR_TEXTEN) /!< TimeoutA and TimeoutB (extended clock) enable bits /
<>	135:176b8275d35d	331	/**
<>	135:176b8275d35d	332	* @}
<>	135:176b8275d35d	333	*/
<>	135:176b8275d35d	334
<>	135:176b8275d35d	335	/**
<>	135:176b8275d35d	336	* @}
<>	135:176b8275d35d	337	*/
<>	135:176b8275d35d	338
<>	135:176b8275d35d	339	/* Exported macro ------------------------------------------------------------*/
<>	135:176b8275d35d	340	/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
<>	135:176b8275d35d	341	* @{
<>	135:176b8275d35d	342	*/
<>	135:176b8275d35d	343
<>	135:176b8275d35d	344	/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
<>	135:176b8275d35d	345	* @{
<>	135:176b8275d35d	346	*/
<>	135:176b8275d35d	347
<>	135:176b8275d35d	348	/**
<>	135:176b8275d35d	349	* @brief Write a value in I2C register
<>	135:176b8275d35d	350	* @param __INSTANCE__ I2C Instance
<>	135:176b8275d35d	351	* @param __REG__ Register to be written
<>	135:176b8275d35d	352	* @param __VALUE__ Value to be written in the register
<>	135:176b8275d35d	353	* @retval None
<>	135:176b8275d35d	354	*/
<>	135:176b8275d35d	355	#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	135:176b8275d35d	356
<>	135:176b8275d35d	357	/**
<>	135:176b8275d35d	358	* @brief Read a value in I2C register
<>	135:176b8275d35d	359	* @param __INSTANCE__ I2C Instance
<>	135:176b8275d35d	360	* @param __REG__ Register to be read
<>	135:176b8275d35d	361	* @retval Register value
<>	135:176b8275d35d	362	*/
<>	135:176b8275d35d	363	#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	135:176b8275d35d	364	/**
<>	135:176b8275d35d	365	* @}
<>	135:176b8275d35d	366	*/
<>	135:176b8275d35d	367
<>	135:176b8275d35d	368	/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
<>	135:176b8275d35d	369	* @{
<>	135:176b8275d35d	370	*/
<>	135:176b8275d35d	371	/**
<>	135:176b8275d35d	372	* @brief Configure the SDA setup, hold time and the SCL high, low period.
<>	135:176b8275d35d	373	* @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
<>	135:176b8275d35d	374	* @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
<>	135:176b8275d35d	375	* @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
<>	135:176b8275d35d	376	* @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
<>	135:176b8275d35d	377	* @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
<>	135:176b8275d35d	378	* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
<>	135:176b8275d35d	379	*/
<>	135:176b8275d35d	380	#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
<>	135:176b8275d35d	381	((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) \| \
<>	135:176b8275d35d	382	(((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) \| \
<>	135:176b8275d35d	383	(((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) \| \
<>	135:176b8275d35d	384	(((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) \| \
<>	135:176b8275d35d	385	(((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
<>	135:176b8275d35d	386	/**
<>	135:176b8275d35d	387	* @}
<>	135:176b8275d35d	388	*/
<>	135:176b8275d35d	389
<>	135:176b8275d35d	390	/**
<>	135:176b8275d35d	391	* @}
<>	135:176b8275d35d	392	*/
<>	135:176b8275d35d	393
<>	135:176b8275d35d	394	/* Exported functions --------------------------------------------------------*/
<>	135:176b8275d35d	395	/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
<>	135:176b8275d35d	396	* @{
<>	135:176b8275d35d	397	*/
<>	135:176b8275d35d	398
<>	135:176b8275d35d	399	/** @defgroup I2C_LL_EF_Configuration Configuration
<>	135:176b8275d35d	400	* @{
<>	135:176b8275d35d	401	*/
<>	135:176b8275d35d	402
<>	135:176b8275d35d	403	/**
<>	135:176b8275d35d	404	* @brief Enable I2C peripheral (PE = 1).
<>	135:176b8275d35d	405	* @rmtoll CR1 PE LL_I2C_Enable
<>	135:176b8275d35d	406	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	407	* @retval None
<>	135:176b8275d35d	408	*/
<>	135:176b8275d35d	409	__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	410	{
<>	135:176b8275d35d	411	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
<>	135:176b8275d35d	412	}
<>	135:176b8275d35d	413
<>	135:176b8275d35d	414	/**
<>	135:176b8275d35d	415	* @brief Disable I2C peripheral (PE = 0).
<>	135:176b8275d35d	416	* @note When PE = 0, the I2C SCL and SDA lines are released.
<>	135:176b8275d35d	417	* Internal state machines and status bits are put back to their reset value.
<>	135:176b8275d35d	418	* When cleared, PE must be kept low for at least 3 APB clock cycles.
<>	135:176b8275d35d	419	* @rmtoll CR1 PE LL_I2C_Disable
<>	135:176b8275d35d	420	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	421	* @retval None
<>	135:176b8275d35d	422	*/
<>	135:176b8275d35d	423	__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	424	{
<>	135:176b8275d35d	425	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
<>	135:176b8275d35d	426	}
<>	135:176b8275d35d	427
<>	135:176b8275d35d	428	/**
<>	135:176b8275d35d	429	* @brief Check if the I2C peripheral is enabled or disabled.
<>	135:176b8275d35d	430	* @rmtoll CR1 PE LL_I2C_IsEnabled
<>	135:176b8275d35d	431	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	432	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	433	*/
<>	135:176b8275d35d	434	__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	435	{
<>	135:176b8275d35d	436	return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
<>	135:176b8275d35d	437	}
<>	135:176b8275d35d	438
<>	135:176b8275d35d	439	/**
<>	135:176b8275d35d	440	* @brief Configure Noise Filters (Analog and Digital).
<>	135:176b8275d35d	441	* @note If the analog filter is also enabled, the digital filter is added to analog filter.
<>	135:176b8275d35d	442	* The filters can only be programmed when the I2C is disabled (PE = 0).
<>	135:176b8275d35d	443	* @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
<>	135:176b8275d35d	444	* CR1 DNF LL_I2C_ConfigFilters
<>	135:176b8275d35d	445	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	446	* @param AnalogFilter This parameter can be one of the following values:
<>	135:176b8275d35d	447	* @arg @ref LL_I2C_ANALOGFILTER_ENABLE
<>	135:176b8275d35d	448	* @arg @ref LL_I2C_ANALOGFILTER_DISABLE
<>	135:176b8275d35d	449	* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
<>	135:176b8275d35d	450	* This parameter is used to configure the digital noise filter on SDA and SCL input.
<>	135:176b8275d35d	451	* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
<>	135:176b8275d35d	452	* @retval None
<>	135:176b8275d35d	453	*/
<>	135:176b8275d35d	454	__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
<>	135:176b8275d35d	455	{
<>	135:176b8275d35d	456	MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF \| I2C_CR1_DNF, AnalogFilter \| (DigitalFilter << I2C_CR1_DNF_Pos));
<>	135:176b8275d35d	457	}
<>	135:176b8275d35d	458
<>	135:176b8275d35d	459	/**
<>	135:176b8275d35d	460	* @brief Configure Digital Noise Filter.
<>	135:176b8275d35d	461	* @note If the analog filter is also enabled, the digital filter is added to analog filter.
<>	135:176b8275d35d	462	* This filter can only be programmed when the I2C is disabled (PE = 0).
<>	135:176b8275d35d	463	* @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
<>	135:176b8275d35d	464	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	465	* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
<>	135:176b8275d35d	466	* This parameter is used to configure the digital noise filter on SDA and SCL input.
<>	135:176b8275d35d	467	* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
<>	135:176b8275d35d	468	* @retval None
<>	135:176b8275d35d	469	*/
<>	135:176b8275d35d	470	__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
<>	135:176b8275d35d	471	{
<>	135:176b8275d35d	472	MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
<>	135:176b8275d35d	473	}
<>	135:176b8275d35d	474
<>	135:176b8275d35d	475	/**
<>	135:176b8275d35d	476	* @brief Get the current Digital Noise Filter configuration.
<>	135:176b8275d35d	477	* @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
<>	135:176b8275d35d	478	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	479	* @retval Value between Min_Data=0x0 and Max_Data=0xF
<>	135:176b8275d35d	480	*/
<>	135:176b8275d35d	481	__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	482	{
<>	135:176b8275d35d	483	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
<>	135:176b8275d35d	484	}
<>	135:176b8275d35d	485
<>	135:176b8275d35d	486	/**
<>	135:176b8275d35d	487	* @brief Enable Analog Noise Filter.
<>	135:176b8275d35d	488	* @note This filter can only be programmed when the I2C is disabled (PE = 0).
<>	135:176b8275d35d	489	* @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
<>	135:176b8275d35d	490	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	491	* @retval None
<>	135:176b8275d35d	492	*/
<>	135:176b8275d35d	493	__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	494	{
<>	135:176b8275d35d	495	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
<>	135:176b8275d35d	496	}
<>	135:176b8275d35d	497
<>	135:176b8275d35d	498	/**
<>	135:176b8275d35d	499	* @brief Disable Analog Noise Filter.
<>	135:176b8275d35d	500	* @note This filter can only be programmed when the I2C is disabled (PE = 0).
<>	135:176b8275d35d	501	* @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
<>	135:176b8275d35d	502	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	503	* @retval None
<>	135:176b8275d35d	504	*/
<>	135:176b8275d35d	505	__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	506	{
<>	135:176b8275d35d	507	SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
<>	135:176b8275d35d	508	}
<>	135:176b8275d35d	509
<>	135:176b8275d35d	510	/**
<>	135:176b8275d35d	511	* @brief Check if Analog Noise Filter is enabled or disabled.
<>	135:176b8275d35d	512	* @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
<>	135:176b8275d35d	513	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	514	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	515	*/
<>	135:176b8275d35d	516	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	517	{
<>	135:176b8275d35d	518	return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF));
<>	135:176b8275d35d	519	}
<>	135:176b8275d35d	520
<>	135:176b8275d35d	521	/**
<>	135:176b8275d35d	522	* @brief Enable DMA transmission requests.
<>	135:176b8275d35d	523	* @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
<>	135:176b8275d35d	524	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	525	* @retval None
<>	135:176b8275d35d	526	*/
<>	135:176b8275d35d	527	__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	528	{
<>	135:176b8275d35d	529	SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
<>	135:176b8275d35d	530	}
<>	135:176b8275d35d	531
<>	135:176b8275d35d	532	/**
<>	135:176b8275d35d	533	* @brief Disable DMA transmission requests.
<>	135:176b8275d35d	534	* @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
<>	135:176b8275d35d	535	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	536	* @retval None
<>	135:176b8275d35d	537	*/
<>	135:176b8275d35d	538	__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	539	{
<>	135:176b8275d35d	540	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
<>	135:176b8275d35d	541	}
<>	135:176b8275d35d	542
<>	135:176b8275d35d	543	/**
<>	135:176b8275d35d	544	* @brief Check if DMA transmission requests are enabled or disabled.
<>	135:176b8275d35d	545	* @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
<>	135:176b8275d35d	546	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	547	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	548	*/
<>	135:176b8275d35d	549	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	550	{
<>	135:176b8275d35d	551	return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN));
<>	135:176b8275d35d	552	}
<>	135:176b8275d35d	553
<>	135:176b8275d35d	554	/**
<>	135:176b8275d35d	555	* @brief Enable DMA reception requests.
<>	135:176b8275d35d	556	* @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
<>	135:176b8275d35d	557	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	558	* @retval None
<>	135:176b8275d35d	559	*/
<>	135:176b8275d35d	560	__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	561	{
<>	135:176b8275d35d	562	SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
<>	135:176b8275d35d	563	}
<>	135:176b8275d35d	564
<>	135:176b8275d35d	565	/**
<>	135:176b8275d35d	566	* @brief Disable DMA reception requests.
<>	135:176b8275d35d	567	* @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
<>	135:176b8275d35d	568	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	569	* @retval None
<>	135:176b8275d35d	570	*/
<>	135:176b8275d35d	571	__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	572	{
<>	135:176b8275d35d	573	CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
<>	135:176b8275d35d	574	}
<>	135:176b8275d35d	575
<>	135:176b8275d35d	576	/**
<>	135:176b8275d35d	577	* @brief Check if DMA reception requests are enabled or disabled.
<>	135:176b8275d35d	578	* @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
<>	135:176b8275d35d	579	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	580	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	581	*/
<>	135:176b8275d35d	582	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	583	{
<>	135:176b8275d35d	584	return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN));
<>	135:176b8275d35d	585	}
<>	135:176b8275d35d	586
<>	135:176b8275d35d	587	/**
<>	135:176b8275d35d	588	* @brief Get the data register address used for DMA transfer
<>	135:176b8275d35d	589	* @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
<>	135:176b8275d35d	590	* RXDR RXDATA LL_I2C_DMA_GetRegAddr
<>	135:176b8275d35d	591	* @param I2Cx I2C Instance
<>	135:176b8275d35d	592	* @param Direction This parameter can be one of the following values:
<>	135:176b8275d35d	593	* @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
<>	135:176b8275d35d	594	* @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
<>	135:176b8275d35d	595	* @retval Address of data register
<>	135:176b8275d35d	596	*/
<>	135:176b8275d35d	597	__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
<>	135:176b8275d35d	598	{
<>	135:176b8275d35d	599	register uint32_t data_reg_addr = 0U;
<>	135:176b8275d35d	600
<>	135:176b8275d35d	601	if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
<>	135:176b8275d35d	602	{
<>	135:176b8275d35d	603	/* return address of TXDR register */
<>	135:176b8275d35d	604	data_reg_addr = (uint32_t) & (I2Cx->TXDR);
<>	135:176b8275d35d	605	}
<>	135:176b8275d35d	606	else
<>	135:176b8275d35d	607	{
<>	135:176b8275d35d	608	/* return address of RXDR register */
<>	135:176b8275d35d	609	data_reg_addr = (uint32_t) & (I2Cx->RXDR);
<>	135:176b8275d35d	610	}
<>	135:176b8275d35d	611
<>	135:176b8275d35d	612	return data_reg_addr;
<>	135:176b8275d35d	613	}
<>	135:176b8275d35d	614
<>	135:176b8275d35d	615	/**
<>	135:176b8275d35d	616	* @brief Enable Clock stretching.
<>	135:176b8275d35d	617	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	135:176b8275d35d	618	* @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
<>	135:176b8275d35d	619	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	620	* @retval None
<>	135:176b8275d35d	621	*/
<>	135:176b8275d35d	622	__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	623	{
<>	135:176b8275d35d	624	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
<>	135:176b8275d35d	625	}
<>	135:176b8275d35d	626
<>	135:176b8275d35d	627	/**
<>	135:176b8275d35d	628	* @brief Disable Clock stretching.
<>	135:176b8275d35d	629	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	135:176b8275d35d	630	* @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
<>	135:176b8275d35d	631	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	632	* @retval None
<>	135:176b8275d35d	633	*/
<>	135:176b8275d35d	634	__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	635	{
<>	135:176b8275d35d	636	SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
<>	135:176b8275d35d	637	}
<>	135:176b8275d35d	638
<>	135:176b8275d35d	639	/**
<>	135:176b8275d35d	640	* @brief Check if Clock stretching is enabled or disabled.
<>	135:176b8275d35d	641	* @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
<>	135:176b8275d35d	642	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	643	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	644	*/
<>	135:176b8275d35d	645	__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	646	{
<>	135:176b8275d35d	647	return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
<>	135:176b8275d35d	648	}
<>	135:176b8275d35d	649
<>	135:176b8275d35d	650	/**
<>	135:176b8275d35d	651	* @brief Enable hardware byte control in slave mode.
<>	135:176b8275d35d	652	* @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
<>	135:176b8275d35d	653	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	654	* @retval None
<>	135:176b8275d35d	655	*/
<>	135:176b8275d35d	656	__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	657	{
<>	135:176b8275d35d	658	SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
<>	135:176b8275d35d	659	}
<>	135:176b8275d35d	660
<>	135:176b8275d35d	661	/**
<>	135:176b8275d35d	662	* @brief Disable hardware byte control in slave mode.
<>	135:176b8275d35d	663	* @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
<>	135:176b8275d35d	664	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	665	* @retval None
<>	135:176b8275d35d	666	*/
<>	135:176b8275d35d	667	__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	668	{
<>	135:176b8275d35d	669	CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
<>	135:176b8275d35d	670	}
<>	135:176b8275d35d	671
<>	135:176b8275d35d	672	/**
<>	135:176b8275d35d	673	* @brief Check if hardware byte control in slave mode is enabled or disabled.
<>	135:176b8275d35d	674	* @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
<>	135:176b8275d35d	675	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	676	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	677	*/
<>	135:176b8275d35d	678	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	679	{
<>	135:176b8275d35d	680	return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC));
<>	135:176b8275d35d	681	}
<>	135:176b8275d35d	682
<>	135:176b8275d35d	683	/**
<>	135:176b8275d35d	684	* @brief Enable Wakeup from STOP.
<>	135:176b8275d35d	685	* @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	686	* WakeUpFromStop feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	687	* @note This bit can only be programmed when Digital Filter is disabled.
<>	135:176b8275d35d	688	* @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
<>	135:176b8275d35d	689	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	690	* @retval None
<>	135:176b8275d35d	691	*/
<>	135:176b8275d35d	692	__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	693	{
<>	135:176b8275d35d	694	SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
<>	135:176b8275d35d	695	}
<>	135:176b8275d35d	696
<>	135:176b8275d35d	697	/**
<>	135:176b8275d35d	698	* @brief Disable Wakeup from STOP.
<>	135:176b8275d35d	699	* @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	700	* WakeUpFromStop feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	701	* @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
<>	135:176b8275d35d	702	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	703	* @retval None
<>	135:176b8275d35d	704	*/
<>	135:176b8275d35d	705	__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	706	{
<>	135:176b8275d35d	707	CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
<>	135:176b8275d35d	708	}
<>	135:176b8275d35d	709
<>	135:176b8275d35d	710	/**
<>	135:176b8275d35d	711	* @brief Check if Wakeup from STOP is enabled or disabled.
<>	135:176b8275d35d	712	* @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	713	* WakeUpFromStop feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	714	* @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
<>	135:176b8275d35d	715	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	716	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	717	*/
<>	135:176b8275d35d	718	__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	719	{
<>	135:176b8275d35d	720	return (READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN));
<>	135:176b8275d35d	721	}
<>	135:176b8275d35d	722
<>	135:176b8275d35d	723	/**
<>	135:176b8275d35d	724	* @brief Enable General Call.
<>	135:176b8275d35d	725	* @note When enabled the Address 0x00 is ACKed.
<>	135:176b8275d35d	726	* @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
<>	135:176b8275d35d	727	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	728	* @retval None
<>	135:176b8275d35d	729	*/
<>	135:176b8275d35d	730	__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	731	{
<>	135:176b8275d35d	732	SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
<>	135:176b8275d35d	733	}
<>	135:176b8275d35d	734
<>	135:176b8275d35d	735	/**
<>	135:176b8275d35d	736	* @brief Disable General Call.
<>	135:176b8275d35d	737	* @note When disabled the Address 0x00 is NACKed.
<>	135:176b8275d35d	738	* @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
<>	135:176b8275d35d	739	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	740	* @retval None
<>	135:176b8275d35d	741	*/
<>	135:176b8275d35d	742	__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	743	{
<>	135:176b8275d35d	744	CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
<>	135:176b8275d35d	745	}
<>	135:176b8275d35d	746
<>	135:176b8275d35d	747	/**
<>	135:176b8275d35d	748	* @brief Check if General Call is enabled or disabled.
<>	135:176b8275d35d	749	* @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
<>	135:176b8275d35d	750	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	751	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	752	*/
<>	135:176b8275d35d	753	__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	754	{
<>	135:176b8275d35d	755	return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN));
<>	135:176b8275d35d	756	}
<>	135:176b8275d35d	757
<>	135:176b8275d35d	758	/**
<>	135:176b8275d35d	759	* @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
<>	135:176b8275d35d	760	* @note Changing this bit is not allowed, when the START bit is set.
<>	135:176b8275d35d	761	* @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
<>	135:176b8275d35d	762	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	763	* @param AddressingMode This parameter can be one of the following values:
<>	135:176b8275d35d	764	* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
<>	135:176b8275d35d	765	* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
<>	135:176b8275d35d	766	* @retval None
<>	135:176b8275d35d	767	*/
<>	135:176b8275d35d	768	__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
<>	135:176b8275d35d	769	{
<>	135:176b8275d35d	770	MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
<>	135:176b8275d35d	771	}
<>	135:176b8275d35d	772
<>	135:176b8275d35d	773	/**
<>	135:176b8275d35d	774	* @brief Get the Master addressing mode.
<>	135:176b8275d35d	775	* @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
<>	135:176b8275d35d	776	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	777	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	778	* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
<>	135:176b8275d35d	779	* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
<>	135:176b8275d35d	780	*/
<>	135:176b8275d35d	781	__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	782	{
<>	135:176b8275d35d	783	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
<>	135:176b8275d35d	784	}
<>	135:176b8275d35d	785
<>	135:176b8275d35d	786	/**
<>	135:176b8275d35d	787	* @brief Set the Own Address1.
<>	135:176b8275d35d	788	* @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
<>	135:176b8275d35d	789	* OAR1 OA1MODE LL_I2C_SetOwnAddress1
<>	135:176b8275d35d	790	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	791	* @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
<>	135:176b8275d35d	792	* @param OwnAddrSize This parameter can be one of the following values:
<>	135:176b8275d35d	793	* @arg @ref LL_I2C_OWNADDRESS1_7BIT
<>	135:176b8275d35d	794	* @arg @ref LL_I2C_OWNADDRESS1_10BIT
<>	135:176b8275d35d	795	* @retval None
<>	135:176b8275d35d	796	*/
<>	135:176b8275d35d	797	__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
<>	135:176b8275d35d	798	{
<>	135:176b8275d35d	799	MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 \| I2C_OAR1_OA1MODE, OwnAddress1 \| OwnAddrSize);
<>	135:176b8275d35d	800	}
<>	135:176b8275d35d	801
<>	135:176b8275d35d	802	/**
<>	135:176b8275d35d	803	* @brief Enable acknowledge on Own Address1 match address.
<>	135:176b8275d35d	804	* @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
<>	135:176b8275d35d	805	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	806	* @retval None
<>	135:176b8275d35d	807	*/
<>	135:176b8275d35d	808	__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	809	{
<>	135:176b8275d35d	810	SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
<>	135:176b8275d35d	811	}
<>	135:176b8275d35d	812
<>	135:176b8275d35d	813	/**
<>	135:176b8275d35d	814	* @brief Disable acknowledge on Own Address1 match address.
<>	135:176b8275d35d	815	* @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
<>	135:176b8275d35d	816	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	817	* @retval None
<>	135:176b8275d35d	818	*/
<>	135:176b8275d35d	819	__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	820	{
<>	135:176b8275d35d	821	CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
<>	135:176b8275d35d	822	}
<>	135:176b8275d35d	823
<>	135:176b8275d35d	824	/**
<>	135:176b8275d35d	825	* @brief Check if Own Address1 acknowledge is enabled or disabled.
<>	135:176b8275d35d	826	* @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
<>	135:176b8275d35d	827	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	828	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	829	*/
<>	135:176b8275d35d	830	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	831	{
<>	135:176b8275d35d	832	return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN));
<>	135:176b8275d35d	833	}
<>	135:176b8275d35d	834
<>	135:176b8275d35d	835	/**
<>	135:176b8275d35d	836	* @brief Set the 7bits Own Address2.
<>	135:176b8275d35d	837	* @note This action has no effect if own address2 is enabled.
<>	135:176b8275d35d	838	* @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
<>	135:176b8275d35d	839	* OAR2 OA2MSK LL_I2C_SetOwnAddress2
<>	135:176b8275d35d	840	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	841	* @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
<>	135:176b8275d35d	842	* @param OwnAddrMask This parameter can be one of the following values:
<>	135:176b8275d35d	843	* @arg @ref LL_I2C_OWNADDRESS2_NOMASK
<>	135:176b8275d35d	844	* @arg @ref LL_I2C_OWNADDRESS2_MASK01
<>	135:176b8275d35d	845	* @arg @ref LL_I2C_OWNADDRESS2_MASK02
<>	135:176b8275d35d	846	* @arg @ref LL_I2C_OWNADDRESS2_MASK03
<>	135:176b8275d35d	847	* @arg @ref LL_I2C_OWNADDRESS2_MASK04
<>	135:176b8275d35d	848	* @arg @ref LL_I2C_OWNADDRESS2_MASK05
<>	135:176b8275d35d	849	* @arg @ref LL_I2C_OWNADDRESS2_MASK06
<>	135:176b8275d35d	850	* @arg @ref LL_I2C_OWNADDRESS2_MASK07
<>	135:176b8275d35d	851	* @retval None
<>	135:176b8275d35d	852	*/
<>	135:176b8275d35d	853	__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
<>	135:176b8275d35d	854	{
<>	135:176b8275d35d	855	MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 \| I2C_OAR2_OA2MSK, OwnAddress2 \| OwnAddrMask);
<>	135:176b8275d35d	856	}
<>	135:176b8275d35d	857
<>	135:176b8275d35d	858	/**
<>	135:176b8275d35d	859	* @brief Enable acknowledge on Own Address2 match address.
<>	135:176b8275d35d	860	* @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
<>	135:176b8275d35d	861	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	862	* @retval None
<>	135:176b8275d35d	863	*/
<>	135:176b8275d35d	864	__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	865	{
<>	135:176b8275d35d	866	SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
<>	135:176b8275d35d	867	}
<>	135:176b8275d35d	868
<>	135:176b8275d35d	869	/**
<>	135:176b8275d35d	870	* @brief Disable acknowledge on Own Address2 match address.
<>	135:176b8275d35d	871	* @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
<>	135:176b8275d35d	872	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	873	* @retval None
<>	135:176b8275d35d	874	*/
<>	135:176b8275d35d	875	__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	876	{
<>	135:176b8275d35d	877	CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
<>	135:176b8275d35d	878	}
<>	135:176b8275d35d	879
<>	135:176b8275d35d	880	/**
<>	135:176b8275d35d	881	* @brief Check if Own Address1 acknowledge is enabled or disabled.
<>	135:176b8275d35d	882	* @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
<>	135:176b8275d35d	883	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	884	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	885	*/
<>	135:176b8275d35d	886	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	887	{
<>	135:176b8275d35d	888	return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN));
<>	135:176b8275d35d	889	}
<>	135:176b8275d35d	890
<>	135:176b8275d35d	891	/**
<>	135:176b8275d35d	892	* @brief Configure the SDA setup, hold time and the SCL high, low period.
<>	135:176b8275d35d	893	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	135:176b8275d35d	894	* @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
<>	135:176b8275d35d	895	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	896	* @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
<>	135:176b8275d35d	897	* @note This parameter is computed with the STM32CubeMX Tool.
<>	135:176b8275d35d	898	* @retval None
<>	135:176b8275d35d	899	*/
<>	135:176b8275d35d	900	__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
<>	135:176b8275d35d	901	{
<>	135:176b8275d35d	902	WRITE_REG(I2Cx->TIMINGR, Timing);
<>	135:176b8275d35d	903	}
<>	135:176b8275d35d	904
<>	135:176b8275d35d	905	/**
<>	135:176b8275d35d	906	* @brief Get the Timing Prescaler setting.
<>	135:176b8275d35d	907	* @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
<>	135:176b8275d35d	908	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	909	* @retval Value between Min_Data=0x0 and Max_Data=0xF
<>	135:176b8275d35d	910	*/
<>	135:176b8275d35d	911	__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	912	{
<>	135:176b8275d35d	913	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
<>	135:176b8275d35d	914	}
<>	135:176b8275d35d	915
<>	135:176b8275d35d	916	/**
<>	135:176b8275d35d	917	* @brief Get the SCL low period setting.
<>	135:176b8275d35d	918	* @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
<>	135:176b8275d35d	919	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	920	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	135:176b8275d35d	921	*/
<>	135:176b8275d35d	922	__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	923	{
<>	135:176b8275d35d	924	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
<>	135:176b8275d35d	925	}
<>	135:176b8275d35d	926
<>	135:176b8275d35d	927	/**
<>	135:176b8275d35d	928	* @brief Get the SCL high period setting.
<>	135:176b8275d35d	929	* @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
<>	135:176b8275d35d	930	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	931	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	135:176b8275d35d	932	*/
<>	135:176b8275d35d	933	__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	934	{
<>	135:176b8275d35d	935	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
<>	135:176b8275d35d	936	}
<>	135:176b8275d35d	937
<>	135:176b8275d35d	938	/**
<>	135:176b8275d35d	939	* @brief Get the SDA hold time.
<>	135:176b8275d35d	940	* @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
<>	135:176b8275d35d	941	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	942	* @retval Value between Min_Data=0x0 and Max_Data=0xF
<>	135:176b8275d35d	943	*/
<>	135:176b8275d35d	944	__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	945	{
<>	135:176b8275d35d	946	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
<>	135:176b8275d35d	947	}
<>	135:176b8275d35d	948
<>	135:176b8275d35d	949	/**
<>	135:176b8275d35d	950	* @brief Get the SDA setup time.
<>	135:176b8275d35d	951	* @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
<>	135:176b8275d35d	952	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	953	* @retval Value between Min_Data=0x0 and Max_Data=0xF
<>	135:176b8275d35d	954	*/
<>	135:176b8275d35d	955	__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	956	{
<>	135:176b8275d35d	957	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
<>	135:176b8275d35d	958	}
<>	135:176b8275d35d	959
<>	135:176b8275d35d	960	/**
<>	135:176b8275d35d	961	* @brief Configure peripheral mode.
<>	135:176b8275d35d	962	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	963	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	964	* @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
<>	135:176b8275d35d	965	* CR1 SMBDEN LL_I2C_SetMode
<>	135:176b8275d35d	966	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	967	* @param PeripheralMode This parameter can be one of the following values:
<>	135:176b8275d35d	968	* @arg @ref LL_I2C_MODE_I2C
<>	135:176b8275d35d	969	* @arg @ref LL_I2C_MODE_SMBUS_HOST
<>	135:176b8275d35d	970	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
<>	135:176b8275d35d	971	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
<>	135:176b8275d35d	972	* @retval None
<>	135:176b8275d35d	973	*/
<>	135:176b8275d35d	974	__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
<>	135:176b8275d35d	975	{
<>	135:176b8275d35d	976	MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN \| I2C_CR1_SMBDEN, PeripheralMode);
<>	135:176b8275d35d	977	}
<>	135:176b8275d35d	978
<>	135:176b8275d35d	979	/**
<>	135:176b8275d35d	980	* @brief Get peripheral mode.
<>	135:176b8275d35d	981	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	982	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	983	* @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
<>	135:176b8275d35d	984	* CR1 SMBDEN LL_I2C_GetMode
<>	135:176b8275d35d	985	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	986	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	987	* @arg @ref LL_I2C_MODE_I2C
<>	135:176b8275d35d	988	* @arg @ref LL_I2C_MODE_SMBUS_HOST
<>	135:176b8275d35d	989	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
<>	135:176b8275d35d	990	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
<>	135:176b8275d35d	991	*/
<>	135:176b8275d35d	992	__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	993	{
<>	135:176b8275d35d	994	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN \| I2C_CR1_SMBDEN));
<>	135:176b8275d35d	995	}
<>	135:176b8275d35d	996
<>	135:176b8275d35d	997	/**
<>	135:176b8275d35d	998	* @brief Enable SMBus alert (Host or Device mode)
<>	135:176b8275d35d	999	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1000	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1001	* @note SMBus Device mode:
<>	135:176b8275d35d	1002	* - SMBus Alert pin is drived low and
<>	135:176b8275d35d	1003	* Alert Response Address Header acknowledge is enabled.
<>	135:176b8275d35d	1004	* SMBus Host mode:
<>	135:176b8275d35d	1005	* - SMBus Alert pin management is supported.
<>	135:176b8275d35d	1006	* @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
<>	135:176b8275d35d	1007	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1008	* @retval None
<>	135:176b8275d35d	1009	*/
<>	135:176b8275d35d	1010	__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1011	{
<>	135:176b8275d35d	1012	SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
<>	135:176b8275d35d	1013	}
<>	135:176b8275d35d	1014
<>	135:176b8275d35d	1015	/**
<>	135:176b8275d35d	1016	* @brief Disable SMBus alert (Host or Device mode)
<>	135:176b8275d35d	1017	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1018	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1019	* @note SMBus Device mode:
<>	135:176b8275d35d	1020	* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
<>	135:176b8275d35d	1021	* Alert Response Address Header acknowledge is disabled.
<>	135:176b8275d35d	1022	* SMBus Host mode:
<>	135:176b8275d35d	1023	* - SMBus Alert pin management is not supported.
<>	135:176b8275d35d	1024	* @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
<>	135:176b8275d35d	1025	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1026	* @retval None
<>	135:176b8275d35d	1027	*/
<>	135:176b8275d35d	1028	__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1029	{
<>	135:176b8275d35d	1030	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
<>	135:176b8275d35d	1031	}
<>	135:176b8275d35d	1032
<>	135:176b8275d35d	1033	/**
<>	135:176b8275d35d	1034	* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
<>	135:176b8275d35d	1035	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1036	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1037	* @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
<>	135:176b8275d35d	1038	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1039	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1040	*/
<>	135:176b8275d35d	1041	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1042	{
<>	135:176b8275d35d	1043	return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN));
<>	135:176b8275d35d	1044	}
<>	135:176b8275d35d	1045
<>	135:176b8275d35d	1046	/**
<>	135:176b8275d35d	1047	* @brief Enable SMBus Packet Error Calculation (PEC).
<>	135:176b8275d35d	1048	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1049	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1050	* @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
<>	135:176b8275d35d	1051	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1052	* @retval None
<>	135:176b8275d35d	1053	*/
<>	135:176b8275d35d	1054	__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1055	{
<>	135:176b8275d35d	1056	SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
<>	135:176b8275d35d	1057	}
<>	135:176b8275d35d	1058
<>	135:176b8275d35d	1059	/**
<>	135:176b8275d35d	1060	* @brief Disable SMBus Packet Error Calculation (PEC).
<>	135:176b8275d35d	1061	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1062	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1063	* @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
<>	135:176b8275d35d	1064	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1065	* @retval None
<>	135:176b8275d35d	1066	*/
<>	135:176b8275d35d	1067	__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1068	{
<>	135:176b8275d35d	1069	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
<>	135:176b8275d35d	1070	}
<>	135:176b8275d35d	1071
<>	135:176b8275d35d	1072	/**
<>	135:176b8275d35d	1073	* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
<>	135:176b8275d35d	1074	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1075	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1076	* @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
<>	135:176b8275d35d	1077	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1078	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1079	*/
<>	135:176b8275d35d	1080	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1081	{
<>	135:176b8275d35d	1082	return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN));
<>	135:176b8275d35d	1083	}
<>	135:176b8275d35d	1084
<>	135:176b8275d35d	1085	/**
<>	135:176b8275d35d	1086	* @brief Configure the SMBus Clock Timeout.
<>	135:176b8275d35d	1087	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1088	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1089	* @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
<>	135:176b8275d35d	1090	* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
<>	135:176b8275d35d	1091	* TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
<>	135:176b8275d35d	1092	* TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
<>	135:176b8275d35d	1093	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1094	* @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
<>	135:176b8275d35d	1095	* @param TimeoutAMode This parameter can be one of the following values:
<>	135:176b8275d35d	1096	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
<>	135:176b8275d35d	1097	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
<>	135:176b8275d35d	1098	* @param TimeoutB
<>	135:176b8275d35d	1099	* @retval None
<>	135:176b8275d35d	1100	*/
<>	135:176b8275d35d	1101	__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
<>	135:176b8275d35d	1102	uint32_t TimeoutB)
<>	135:176b8275d35d	1103	{
<>	135:176b8275d35d	1104	MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA \| I2C_TIMEOUTR_TIDLE \| I2C_TIMEOUTR_TIMEOUTB,
<>	135:176b8275d35d	1105	TimeoutA \| TimeoutAMode \| (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
<>	135:176b8275d35d	1106	}
<>	135:176b8275d35d	1107
<>	135:176b8275d35d	1108	/**
<>	135:176b8275d35d	1109	* @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
<>	135:176b8275d35d	1110	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1111	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1112	* @note These bits can only be programmed when TimeoutA is disabled.
<>	135:176b8275d35d	1113	* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
<>	135:176b8275d35d	1114	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1115	* @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
<>	135:176b8275d35d	1116	* @retval None
<>	135:176b8275d35d	1117	*/
<>	135:176b8275d35d	1118	__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
<>	135:176b8275d35d	1119	{
<>	135:176b8275d35d	1120	WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
<>	135:176b8275d35d	1121	}
<>	135:176b8275d35d	1122
<>	135:176b8275d35d	1123	/**
<>	135:176b8275d35d	1124	* @brief Get the SMBus Clock TimeoutA setting.
<>	135:176b8275d35d	1125	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1126	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1127	* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
<>	135:176b8275d35d	1128	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1129	* @retval Value between Min_Data=0 and Max_Data=0xFFF
<>	135:176b8275d35d	1130	*/
<>	135:176b8275d35d	1131	__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1132	{
<>	135:176b8275d35d	1133	return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
<>	135:176b8275d35d	1134	}
<>	135:176b8275d35d	1135
<>	135:176b8275d35d	1136	/**
<>	135:176b8275d35d	1137	* @brief Set the SMBus Clock TimeoutA mode.
<>	135:176b8275d35d	1138	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1139	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1140	* @note This bit can only be programmed when TimeoutA is disabled.
<>	135:176b8275d35d	1141	* @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
<>	135:176b8275d35d	1142	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1143	* @param TimeoutAMode This parameter can be one of the following values:
<>	135:176b8275d35d	1144	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
<>	135:176b8275d35d	1145	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
<>	135:176b8275d35d	1146	* @retval None
<>	135:176b8275d35d	1147	*/
<>	135:176b8275d35d	1148	__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
<>	135:176b8275d35d	1149	{
<>	135:176b8275d35d	1150	WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
<>	135:176b8275d35d	1151	}
<>	135:176b8275d35d	1152
<>	135:176b8275d35d	1153	/**
<>	135:176b8275d35d	1154	* @brief Get the SMBus Clock TimeoutA mode.
<>	135:176b8275d35d	1155	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1156	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1157	* @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
<>	135:176b8275d35d	1158	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1159	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	1160	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
<>	135:176b8275d35d	1161	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
<>	135:176b8275d35d	1162	*/
<>	135:176b8275d35d	1163	__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1164	{
<>	135:176b8275d35d	1165	return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
<>	135:176b8275d35d	1166	}
<>	135:176b8275d35d	1167
<>	135:176b8275d35d	1168	/**
<>	135:176b8275d35d	1169	* @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
<>	135:176b8275d35d	1170	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1171	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1172	* @note These bits can only be programmed when TimeoutB is disabled.
<>	135:176b8275d35d	1173	* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
<>	135:176b8275d35d	1174	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1175	* @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
<>	135:176b8275d35d	1176	* @retval None
<>	135:176b8275d35d	1177	*/
<>	135:176b8275d35d	1178	__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
<>	135:176b8275d35d	1179	{
<>	135:176b8275d35d	1180	WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
<>	135:176b8275d35d	1181	}
<>	135:176b8275d35d	1182
<>	135:176b8275d35d	1183	/**
<>	135:176b8275d35d	1184	* @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
<>	135:176b8275d35d	1185	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1186	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1187	* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
<>	135:176b8275d35d	1188	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1189	* @retval Value between Min_Data=0 and Max_Data=0xFFF
<>	135:176b8275d35d	1190	*/
<>	135:176b8275d35d	1191	__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1192	{
<>	135:176b8275d35d	1193	return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
<>	135:176b8275d35d	1194	}
<>	135:176b8275d35d	1195
<>	135:176b8275d35d	1196	/**
<>	135:176b8275d35d	1197	* @brief Enable the SMBus Clock Timeout.
<>	135:176b8275d35d	1198	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1199	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1200	* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
<>	135:176b8275d35d	1201	* TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
<>	135:176b8275d35d	1202	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1203	* @param ClockTimeout This parameter can be one of the following values:
<>	135:176b8275d35d	1204	* @arg @ref LL_I2C_SMBUS_TIMEOUTA
<>	135:176b8275d35d	1205	* @arg @ref LL_I2C_SMBUS_TIMEOUTB
<>	135:176b8275d35d	1206	* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
<>	135:176b8275d35d	1207	* @retval None
<>	135:176b8275d35d	1208	*/
<>	135:176b8275d35d	1209	__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
<>	135:176b8275d35d	1210	{
<>	135:176b8275d35d	1211	SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
<>	135:176b8275d35d	1212	}
<>	135:176b8275d35d	1213
<>	135:176b8275d35d	1214	/**
<>	135:176b8275d35d	1215	* @brief Disable the SMBus Clock Timeout.
<>	135:176b8275d35d	1216	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1217	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1218	* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
<>	135:176b8275d35d	1219	* TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
<>	135:176b8275d35d	1220	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1221	* @param ClockTimeout This parameter can be one of the following values:
<>	135:176b8275d35d	1222	* @arg @ref LL_I2C_SMBUS_TIMEOUTA
<>	135:176b8275d35d	1223	* @arg @ref LL_I2C_SMBUS_TIMEOUTB
<>	135:176b8275d35d	1224	* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
<>	135:176b8275d35d	1225	* @retval None
<>	135:176b8275d35d	1226	*/
<>	135:176b8275d35d	1227	__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
<>	135:176b8275d35d	1228	{
<>	135:176b8275d35d	1229	CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
<>	135:176b8275d35d	1230	}
<>	135:176b8275d35d	1231
<>	135:176b8275d35d	1232	/**
<>	135:176b8275d35d	1233	* @brief Check if the SMBus Clock Timeout is enabled or disabled.
<>	135:176b8275d35d	1234	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1235	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1236	* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
<>	135:176b8275d35d	1237	* TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
<>	135:176b8275d35d	1238	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1239	* @param ClockTimeout This parameter can be one of the following values:
<>	135:176b8275d35d	1240	* @arg @ref LL_I2C_SMBUS_TIMEOUTA
<>	135:176b8275d35d	1241	* @arg @ref LL_I2C_SMBUS_TIMEOUTB
<>	135:176b8275d35d	1242	* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
<>	135:176b8275d35d	1243	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1244	*/
<>	135:176b8275d35d	1245	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
<>	135:176b8275d35d	1246	{
<>	135:176b8275d35d	1247	return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN \| I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout));
<>	135:176b8275d35d	1248	}
<>	135:176b8275d35d	1249
<>	135:176b8275d35d	1250	/**
<>	135:176b8275d35d	1251	* @}
<>	135:176b8275d35d	1252	*/
<>	135:176b8275d35d	1253
<>	135:176b8275d35d	1254	/** @defgroup I2C_LL_EF_IT_Management IT_Management
<>	135:176b8275d35d	1255	* @{
<>	135:176b8275d35d	1256	*/
<>	135:176b8275d35d	1257
<>	135:176b8275d35d	1258	/**
<>	135:176b8275d35d	1259	* @brief Enable TXIS interrupt.
<>	135:176b8275d35d	1260	* @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
<>	135:176b8275d35d	1261	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1262	* @retval None
<>	135:176b8275d35d	1263	*/
<>	135:176b8275d35d	1264	__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1265	{
<>	135:176b8275d35d	1266	SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
<>	135:176b8275d35d	1267	}
<>	135:176b8275d35d	1268
<>	135:176b8275d35d	1269	/**
<>	135:176b8275d35d	1270	* @brief Disable TXIS interrupt.
<>	135:176b8275d35d	1271	* @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
<>	135:176b8275d35d	1272	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1273	* @retval None
<>	135:176b8275d35d	1274	*/
<>	135:176b8275d35d	1275	__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1276	{
<>	135:176b8275d35d	1277	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
<>	135:176b8275d35d	1278	}
<>	135:176b8275d35d	1279
<>	135:176b8275d35d	1280	/**
<>	135:176b8275d35d	1281	* @brief Check if the TXIS Interrupt is enabled or disabled.
<>	135:176b8275d35d	1282	* @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
<>	135:176b8275d35d	1283	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1284	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1285	*/
<>	135:176b8275d35d	1286	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1287	{
<>	135:176b8275d35d	1288	return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE));
<>	135:176b8275d35d	1289	}
<>	135:176b8275d35d	1290
<>	135:176b8275d35d	1291	/**
<>	135:176b8275d35d	1292	* @brief Enable RXNE interrupt.
<>	135:176b8275d35d	1293	* @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
<>	135:176b8275d35d	1294	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1295	* @retval None
<>	135:176b8275d35d	1296	*/
<>	135:176b8275d35d	1297	__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1298	{
<>	135:176b8275d35d	1299	SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
<>	135:176b8275d35d	1300	}
<>	135:176b8275d35d	1301
<>	135:176b8275d35d	1302	/**
<>	135:176b8275d35d	1303	* @brief Disable RXNE interrupt.
<>	135:176b8275d35d	1304	* @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
<>	135:176b8275d35d	1305	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1306	* @retval None
<>	135:176b8275d35d	1307	*/
<>	135:176b8275d35d	1308	__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1309	{
<>	135:176b8275d35d	1310	CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
<>	135:176b8275d35d	1311	}
<>	135:176b8275d35d	1312
<>	135:176b8275d35d	1313	/**
<>	135:176b8275d35d	1314	* @brief Check if the RXNE Interrupt is enabled or disabled.
<>	135:176b8275d35d	1315	* @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
<>	135:176b8275d35d	1316	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1317	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1318	*/
<>	135:176b8275d35d	1319	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1320	{
<>	135:176b8275d35d	1321	return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE));
<>	135:176b8275d35d	1322	}
<>	135:176b8275d35d	1323
<>	135:176b8275d35d	1324	/**
<>	135:176b8275d35d	1325	* @brief Enable Address match interrupt (slave mode only).
<>	135:176b8275d35d	1326	* @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
<>	135:176b8275d35d	1327	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1328	* @retval None
<>	135:176b8275d35d	1329	*/
<>	135:176b8275d35d	1330	__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1331	{
<>	135:176b8275d35d	1332	SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
<>	135:176b8275d35d	1333	}
<>	135:176b8275d35d	1334
<>	135:176b8275d35d	1335	/**
<>	135:176b8275d35d	1336	* @brief Disable Address match interrupt (slave mode only).
<>	135:176b8275d35d	1337	* @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
<>	135:176b8275d35d	1338	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1339	* @retval None
<>	135:176b8275d35d	1340	*/
<>	135:176b8275d35d	1341	__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1342	{
<>	135:176b8275d35d	1343	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
<>	135:176b8275d35d	1344	}
<>	135:176b8275d35d	1345
<>	135:176b8275d35d	1346	/**
<>	135:176b8275d35d	1347	* @brief Check if Address match interrupt is enabled or disabled.
<>	135:176b8275d35d	1348	* @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
<>	135:176b8275d35d	1349	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1350	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1351	*/
<>	135:176b8275d35d	1352	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1353	{
<>	135:176b8275d35d	1354	return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE));
<>	135:176b8275d35d	1355	}
<>	135:176b8275d35d	1356
<>	135:176b8275d35d	1357	/**
<>	135:176b8275d35d	1358	* @brief Enable Not acknowledge received interrupt.
<>	135:176b8275d35d	1359	* @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
<>	135:176b8275d35d	1360	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1361	* @retval None
<>	135:176b8275d35d	1362	*/
<>	135:176b8275d35d	1363	__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1364	{
<>	135:176b8275d35d	1365	SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
<>	135:176b8275d35d	1366	}
<>	135:176b8275d35d	1367
<>	135:176b8275d35d	1368	/**
<>	135:176b8275d35d	1369	* @brief Disable Not acknowledge received interrupt.
<>	135:176b8275d35d	1370	* @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
<>	135:176b8275d35d	1371	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1372	* @retval None
<>	135:176b8275d35d	1373	*/
<>	135:176b8275d35d	1374	__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1375	{
<>	135:176b8275d35d	1376	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
<>	135:176b8275d35d	1377	}
<>	135:176b8275d35d	1378
<>	135:176b8275d35d	1379	/**
<>	135:176b8275d35d	1380	* @brief Check if Not acknowledge received interrupt is enabled or disabled.
<>	135:176b8275d35d	1381	* @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
<>	135:176b8275d35d	1382	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1383	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1384	*/
<>	135:176b8275d35d	1385	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1386	{
<>	135:176b8275d35d	1387	return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE));
<>	135:176b8275d35d	1388	}
<>	135:176b8275d35d	1389
<>	135:176b8275d35d	1390	/**
<>	135:176b8275d35d	1391	* @brief Enable STOP detection interrupt.
<>	135:176b8275d35d	1392	* @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
<>	135:176b8275d35d	1393	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1394	* @retval None
<>	135:176b8275d35d	1395	*/
<>	135:176b8275d35d	1396	__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1397	{
<>	135:176b8275d35d	1398	SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
<>	135:176b8275d35d	1399	}
<>	135:176b8275d35d	1400
<>	135:176b8275d35d	1401	/**
<>	135:176b8275d35d	1402	* @brief Disable STOP detection interrupt.
<>	135:176b8275d35d	1403	* @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
<>	135:176b8275d35d	1404	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1405	* @retval None
<>	135:176b8275d35d	1406	*/
<>	135:176b8275d35d	1407	__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1408	{
<>	135:176b8275d35d	1409	CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
<>	135:176b8275d35d	1410	}
<>	135:176b8275d35d	1411
<>	135:176b8275d35d	1412	/**
<>	135:176b8275d35d	1413	* @brief Check if STOP detection interrupt is enabled or disabled.
<>	135:176b8275d35d	1414	* @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
<>	135:176b8275d35d	1415	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1416	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1417	*/
<>	135:176b8275d35d	1418	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1419	{
<>	135:176b8275d35d	1420	return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE));
<>	135:176b8275d35d	1421	}
<>	135:176b8275d35d	1422
<>	135:176b8275d35d	1423	/**
<>	135:176b8275d35d	1424	* @brief Enable Transfer Complete interrupt.
<>	135:176b8275d35d	1425	* @note Any of these events will generate interrupt :
<>	135:176b8275d35d	1426	* Transfer Complete (TC)
<>	135:176b8275d35d	1427	* Transfer Complete Reload (TCR)
<>	135:176b8275d35d	1428	* @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
<>	135:176b8275d35d	1429	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1430	* @retval None
<>	135:176b8275d35d	1431	*/
<>	135:176b8275d35d	1432	__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1433	{
<>	135:176b8275d35d	1434	SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
<>	135:176b8275d35d	1435	}
<>	135:176b8275d35d	1436
<>	135:176b8275d35d	1437	/**
<>	135:176b8275d35d	1438	* @brief Disable Transfer Complete interrupt.
<>	135:176b8275d35d	1439	* @note Any of these events will generate interrupt :
<>	135:176b8275d35d	1440	* Transfer Complete (TC)
<>	135:176b8275d35d	1441	* Transfer Complete Reload (TCR)
<>	135:176b8275d35d	1442	* @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
<>	135:176b8275d35d	1443	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1444	* @retval None
<>	135:176b8275d35d	1445	*/
<>	135:176b8275d35d	1446	__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1447	{
<>	135:176b8275d35d	1448	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
<>	135:176b8275d35d	1449	}
<>	135:176b8275d35d	1450
<>	135:176b8275d35d	1451	/**
<>	135:176b8275d35d	1452	* @brief Check if Transfer Complete interrupt is enabled or disabled.
<>	135:176b8275d35d	1453	* @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
<>	135:176b8275d35d	1454	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1455	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1456	*/
<>	135:176b8275d35d	1457	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1458	{
<>	135:176b8275d35d	1459	return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE));
<>	135:176b8275d35d	1460	}
<>	135:176b8275d35d	1461
<>	135:176b8275d35d	1462	/**
<>	135:176b8275d35d	1463	* @brief Enable Error interrupts.
<>	135:176b8275d35d	1464	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1465	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1466	* @note Any of these errors will generate interrupt :
<>	135:176b8275d35d	1467	* Arbitration Loss (ARLO)
<>	135:176b8275d35d	1468	* Bus Error detection (BERR)
<>	135:176b8275d35d	1469	* Overrun/Underrun (OVR)
<>	135:176b8275d35d	1470	* SMBus Timeout detection (TIMEOUT)
<>	135:176b8275d35d	1471	* SMBus PEC error detection (PECERR)
<>	135:176b8275d35d	1472	* SMBus Alert pin event detection (ALERT)
<>	135:176b8275d35d	1473	* @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
<>	135:176b8275d35d	1474	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1475	* @retval None
<>	135:176b8275d35d	1476	*/
<>	135:176b8275d35d	1477	__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1478	{
<>	135:176b8275d35d	1479	SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
<>	135:176b8275d35d	1480	}
<>	135:176b8275d35d	1481
<>	135:176b8275d35d	1482	/**
<>	135:176b8275d35d	1483	* @brief Disable Error interrupts.
<>	135:176b8275d35d	1484	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1485	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1486	* @note Any of these errors will generate interrupt :
<>	135:176b8275d35d	1487	* Arbitration Loss (ARLO)
<>	135:176b8275d35d	1488	* Bus Error detection (BERR)
<>	135:176b8275d35d	1489	* Overrun/Underrun (OVR)
<>	135:176b8275d35d	1490	* SMBus Timeout detection (TIMEOUT)
<>	135:176b8275d35d	1491	* SMBus PEC error detection (PECERR)
<>	135:176b8275d35d	1492	* SMBus Alert pin event detection (ALERT)
<>	135:176b8275d35d	1493	* @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
<>	135:176b8275d35d	1494	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1495	* @retval None
<>	135:176b8275d35d	1496	*/
<>	135:176b8275d35d	1497	__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1498	{
<>	135:176b8275d35d	1499	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
<>	135:176b8275d35d	1500	}
<>	135:176b8275d35d	1501
<>	135:176b8275d35d	1502	/**
<>	135:176b8275d35d	1503	* @brief Check if Error interrupts are enabled or disabled.
<>	135:176b8275d35d	1504	* @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
<>	135:176b8275d35d	1505	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1506	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1507	*/
<>	135:176b8275d35d	1508	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1509	{
<>	135:176b8275d35d	1510	return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE));
<>	135:176b8275d35d	1511	}
<>	135:176b8275d35d	1512
<>	135:176b8275d35d	1513	/**
<>	135:176b8275d35d	1514	* @}
<>	135:176b8275d35d	1515	*/
<>	135:176b8275d35d	1516
<>	135:176b8275d35d	1517	/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
<>	135:176b8275d35d	1518	* @{
<>	135:176b8275d35d	1519	*/
<>	135:176b8275d35d	1520
<>	135:176b8275d35d	1521	/**
<>	135:176b8275d35d	1522	* @brief Indicate the status of Transmit data register empty flag.
<>	135:176b8275d35d	1523	* @note RESET: When next data is written in Transmit data register.
<>	135:176b8275d35d	1524	* SET: When Transmit data register is empty.
<>	135:176b8275d35d	1525	* @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
<>	135:176b8275d35d	1526	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1527	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1528	*/
<>	135:176b8275d35d	1529	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1530	{
<>	135:176b8275d35d	1531	return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE));
<>	135:176b8275d35d	1532	}
<>	135:176b8275d35d	1533
<>	135:176b8275d35d	1534	/**
<>	135:176b8275d35d	1535	* @brief Indicate the status of Transmit interrupt flag.
<>	135:176b8275d35d	1536	* @note RESET: When next data is written in Transmit data register.
<>	135:176b8275d35d	1537	* SET: When Transmit data register is empty.
<>	135:176b8275d35d	1538	* @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
<>	135:176b8275d35d	1539	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1540	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1541	*/
<>	135:176b8275d35d	1542	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1543	{
<>	135:176b8275d35d	1544	return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS));
<>	135:176b8275d35d	1545	}
<>	135:176b8275d35d	1546
<>	135:176b8275d35d	1547	/**
<>	135:176b8275d35d	1548	* @brief Indicate the status of Receive data register not empty flag.
<>	135:176b8275d35d	1549	* @note RESET: When Receive data register is read.
<>	135:176b8275d35d	1550	* SET: When the received data is copied in Receive data register.
<>	135:176b8275d35d	1551	* @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
<>	135:176b8275d35d	1552	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1553	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1554	*/
<>	135:176b8275d35d	1555	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1556	{
<>	135:176b8275d35d	1557	return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE));
<>	135:176b8275d35d	1558	}
<>	135:176b8275d35d	1559
<>	135:176b8275d35d	1560	/**
<>	135:176b8275d35d	1561	* @brief Indicate the status of Address matched flag (slave mode).
<>	135:176b8275d35d	1562	* @note RESET: Clear default value.
<>	135:176b8275d35d	1563	* SET: When the received slave address matched with one of the enabled slave address.
<>	135:176b8275d35d	1564	* @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
<>	135:176b8275d35d	1565	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1566	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1567	*/
<>	135:176b8275d35d	1568	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1569	{
<>	135:176b8275d35d	1570	return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR));
<>	135:176b8275d35d	1571	}
<>	135:176b8275d35d	1572
<>	135:176b8275d35d	1573	/**
<>	135:176b8275d35d	1574	* @brief Indicate the status of Not Acknowledge received flag.
<>	135:176b8275d35d	1575	* @note RESET: Clear default value.
<>	135:176b8275d35d	1576	* SET: When a NACK is received after a byte transmission.
<>	135:176b8275d35d	1577	* @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
<>	135:176b8275d35d	1578	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1579	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1580	*/
<>	135:176b8275d35d	1581	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1582	{
<>	135:176b8275d35d	1583	return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF));
<>	135:176b8275d35d	1584	}
<>	135:176b8275d35d	1585
<>	135:176b8275d35d	1586	/**
<>	135:176b8275d35d	1587	* @brief Indicate the status of Stop detection flag.
<>	135:176b8275d35d	1588	* @note RESET: Clear default value.
<>	135:176b8275d35d	1589	* SET: When a Stop condition is detected.
<>	135:176b8275d35d	1590	* @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
<>	135:176b8275d35d	1591	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1592	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1593	*/
<>	135:176b8275d35d	1594	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1595	{
<>	135:176b8275d35d	1596	return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF));
<>	135:176b8275d35d	1597	}
<>	135:176b8275d35d	1598
<>	135:176b8275d35d	1599	/**
<>	135:176b8275d35d	1600	* @brief Indicate the status of Transfer complete flag (master mode).
<>	135:176b8275d35d	1601	* @note RESET: Clear default value.
<>	135:176b8275d35d	1602	* SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
<>	135:176b8275d35d	1603	* @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
<>	135:176b8275d35d	1604	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1605	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1606	*/
<>	135:176b8275d35d	1607	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1608	{
<>	135:176b8275d35d	1609	return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC));
<>	135:176b8275d35d	1610	}
<>	135:176b8275d35d	1611
<>	135:176b8275d35d	1612	/**
<>	135:176b8275d35d	1613	* @brief Indicate the status of Transfer complete flag (master mode).
<>	135:176b8275d35d	1614	* @note RESET: Clear default value.
<>	135:176b8275d35d	1615	* SET: When RELOAD=1 and NBYTES date have been transferred.
<>	135:176b8275d35d	1616	* @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
<>	135:176b8275d35d	1617	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1618	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1619	*/
<>	135:176b8275d35d	1620	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1621	{
<>	135:176b8275d35d	1622	return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR));
<>	135:176b8275d35d	1623	}
<>	135:176b8275d35d	1624
<>	135:176b8275d35d	1625	/**
<>	135:176b8275d35d	1626	* @brief Indicate the status of Bus error flag.
<>	135:176b8275d35d	1627	* @note RESET: Clear default value.
<>	135:176b8275d35d	1628	* SET: When a misplaced Start or Stop condition is detected.
<>	135:176b8275d35d	1629	* @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
<>	135:176b8275d35d	1630	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1631	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1632	*/
<>	135:176b8275d35d	1633	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1634	{
<>	135:176b8275d35d	1635	return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR));
<>	135:176b8275d35d	1636	}
<>	135:176b8275d35d	1637
<>	135:176b8275d35d	1638	/**
<>	135:176b8275d35d	1639	* @brief Indicate the status of Arbitration lost flag.
<>	135:176b8275d35d	1640	* @note RESET: Clear default value.
<>	135:176b8275d35d	1641	* SET: When arbitration lost.
<>	135:176b8275d35d	1642	* @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
<>	135:176b8275d35d	1643	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1644	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1645	*/
<>	135:176b8275d35d	1646	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1647	{
<>	135:176b8275d35d	1648	return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO));
<>	135:176b8275d35d	1649	}
<>	135:176b8275d35d	1650
<>	135:176b8275d35d	1651	/**
<>	135:176b8275d35d	1652	* @brief Indicate the status of Overrun/Underrun flag (slave mode).
<>	135:176b8275d35d	1653	* @note RESET: Clear default value.
<>	135:176b8275d35d	1654	* SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
<>	135:176b8275d35d	1655	* @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
<>	135:176b8275d35d	1656	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1657	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1658	*/
<>	135:176b8275d35d	1659	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1660	{
<>	135:176b8275d35d	1661	return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR));
<>	135:176b8275d35d	1662	}
<>	135:176b8275d35d	1663
<>	135:176b8275d35d	1664	/**
<>	135:176b8275d35d	1665	* @brief Indicate the status of SMBus PEC error flag in reception.
<>	135:176b8275d35d	1666	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1667	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1668	* @note RESET: Clear default value.
<>	135:176b8275d35d	1669	* SET: When the received PEC does not match with the PEC register content.
<>	135:176b8275d35d	1670	* @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
<>	135:176b8275d35d	1671	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1672	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1673	*/
<>	135:176b8275d35d	1674	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1675	{
<>	135:176b8275d35d	1676	return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR));
<>	135:176b8275d35d	1677	}
<>	135:176b8275d35d	1678
<>	135:176b8275d35d	1679	/**
<>	135:176b8275d35d	1680	* @brief Indicate the status of SMBus Timeout detection flag.
<>	135:176b8275d35d	1681	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1682	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1683	* @note RESET: Clear default value.
<>	135:176b8275d35d	1684	* SET: When a timeout or extended clock timeout occurs.
<>	135:176b8275d35d	1685	* @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
<>	135:176b8275d35d	1686	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1687	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1688	*/
<>	135:176b8275d35d	1689	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1690	{
<>	135:176b8275d35d	1691	return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT));
<>	135:176b8275d35d	1692	}
<>	135:176b8275d35d	1693
<>	135:176b8275d35d	1694	/**
<>	135:176b8275d35d	1695	* @brief Indicate the status of SMBus alert flag.
<>	135:176b8275d35d	1696	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1697	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1698	* @note RESET: Clear default value.
<>	135:176b8275d35d	1699	* SET: When SMBus host configuration, SMBus alert enabled and
<>	135:176b8275d35d	1700	* a falling edge event occurs on SMBA pin.
<>	135:176b8275d35d	1701	* @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
<>	135:176b8275d35d	1702	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1703	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1704	*/
<>	135:176b8275d35d	1705	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1706	{
<>	135:176b8275d35d	1707	return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT));
<>	135:176b8275d35d	1708	}
<>	135:176b8275d35d	1709
<>	135:176b8275d35d	1710	/**
<>	135:176b8275d35d	1711	* @brief Indicate the status of Bus Busy flag.
<>	135:176b8275d35d	1712	* @note RESET: Clear default value.
<>	135:176b8275d35d	1713	* SET: When a Start condition is detected.
<>	135:176b8275d35d	1714	* @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
<>	135:176b8275d35d	1715	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1716	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1717	*/
<>	135:176b8275d35d	1718	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1719	{
<>	135:176b8275d35d	1720	return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY));
<>	135:176b8275d35d	1721	}
<>	135:176b8275d35d	1722
<>	135:176b8275d35d	1723	/**
<>	135:176b8275d35d	1724	* @brief Clear Address Matched flag.
<>	135:176b8275d35d	1725	* @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
<>	135:176b8275d35d	1726	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1727	* @retval None
<>	135:176b8275d35d	1728	*/
<>	135:176b8275d35d	1729	__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1730	{
<>	135:176b8275d35d	1731	SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
<>	135:176b8275d35d	1732	}
<>	135:176b8275d35d	1733
<>	135:176b8275d35d	1734	/**
<>	135:176b8275d35d	1735	* @brief Clear Not Acknowledge flag.
<>	135:176b8275d35d	1736	* @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
<>	135:176b8275d35d	1737	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1738	* @retval None
<>	135:176b8275d35d	1739	*/
<>	135:176b8275d35d	1740	__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1741	{
<>	135:176b8275d35d	1742	SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
<>	135:176b8275d35d	1743	}
<>	135:176b8275d35d	1744
<>	135:176b8275d35d	1745	/**
<>	135:176b8275d35d	1746	* @brief Clear Stop detection flag.
<>	135:176b8275d35d	1747	* @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
<>	135:176b8275d35d	1748	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1749	* @retval None
<>	135:176b8275d35d	1750	*/
<>	135:176b8275d35d	1751	__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1752	{
<>	135:176b8275d35d	1753	SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
<>	135:176b8275d35d	1754	}
<>	135:176b8275d35d	1755
<>	135:176b8275d35d	1756	/**
<>	135:176b8275d35d	1757	* @brief Clear Transmit data register empty flag (TXE).
<>	135:176b8275d35d	1758	* @note This bit can be clear by software in order to flush the transmit data register (TXDR).
<>	135:176b8275d35d	1759	* @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
<>	135:176b8275d35d	1760	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1761	* @retval None
<>	135:176b8275d35d	1762	*/
<>	135:176b8275d35d	1763	__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1764	{
<>	135:176b8275d35d	1765	WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
<>	135:176b8275d35d	1766	}
<>	135:176b8275d35d	1767
<>	135:176b8275d35d	1768	/**
<>	135:176b8275d35d	1769	* @brief Clear Bus error flag.
<>	135:176b8275d35d	1770	* @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
<>	135:176b8275d35d	1771	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1772	* @retval None
<>	135:176b8275d35d	1773	*/
<>	135:176b8275d35d	1774	__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1775	{
<>	135:176b8275d35d	1776	SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
<>	135:176b8275d35d	1777	}
<>	135:176b8275d35d	1778
<>	135:176b8275d35d	1779	/**
<>	135:176b8275d35d	1780	* @brief Clear Arbitration lost flag.
<>	135:176b8275d35d	1781	* @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
<>	135:176b8275d35d	1782	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1783	* @retval None
<>	135:176b8275d35d	1784	*/
<>	135:176b8275d35d	1785	__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1786	{
<>	135:176b8275d35d	1787	SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
<>	135:176b8275d35d	1788	}
<>	135:176b8275d35d	1789
<>	135:176b8275d35d	1790	/**
<>	135:176b8275d35d	1791	* @brief Clear Overrun/Underrun flag.
<>	135:176b8275d35d	1792	* @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
<>	135:176b8275d35d	1793	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1794	* @retval None
<>	135:176b8275d35d	1795	*/
<>	135:176b8275d35d	1796	__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1797	{
<>	135:176b8275d35d	1798	SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
<>	135:176b8275d35d	1799	}
<>	135:176b8275d35d	1800
<>	135:176b8275d35d	1801	/**
<>	135:176b8275d35d	1802	* @brief Clear SMBus PEC error flag.
<>	135:176b8275d35d	1803	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1804	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1805	* @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
<>	135:176b8275d35d	1806	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1807	* @retval None
<>	135:176b8275d35d	1808	*/
<>	135:176b8275d35d	1809	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1810	{
<>	135:176b8275d35d	1811	SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
<>	135:176b8275d35d	1812	}
<>	135:176b8275d35d	1813
<>	135:176b8275d35d	1814	/**
<>	135:176b8275d35d	1815	* @brief Clear SMBus Timeout detection flag.
<>	135:176b8275d35d	1816	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1817	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1818	* @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
<>	135:176b8275d35d	1819	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1820	* @retval None
<>	135:176b8275d35d	1821	*/
<>	135:176b8275d35d	1822	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1823	{
<>	135:176b8275d35d	1824	SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
<>	135:176b8275d35d	1825	}
<>	135:176b8275d35d	1826
<>	135:176b8275d35d	1827	/**
<>	135:176b8275d35d	1828	* @brief Clear SMBus Alert flag.
<>	135:176b8275d35d	1829	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	1830	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	1831	* @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
<>	135:176b8275d35d	1832	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1833	* @retval None
<>	135:176b8275d35d	1834	*/
<>	135:176b8275d35d	1835	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1836	{
<>	135:176b8275d35d	1837	SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
<>	135:176b8275d35d	1838	}
<>	135:176b8275d35d	1839
<>	135:176b8275d35d	1840	/**
<>	135:176b8275d35d	1841	* @}
<>	135:176b8275d35d	1842	*/
<>	135:176b8275d35d	1843
<>	135:176b8275d35d	1844	/** @defgroup I2C_LL_EF_Data_Management Data_Management
<>	135:176b8275d35d	1845	* @{
<>	135:176b8275d35d	1846	*/
<>	135:176b8275d35d	1847
<>	135:176b8275d35d	1848	/**
<>	135:176b8275d35d	1849	* @brief Enable automatic STOP condition generation (master mode).
<>	135:176b8275d35d	1850	* @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
<>	135:176b8275d35d	1851	* This bit has no effect in slave mode or when RELOAD bit is set.
<>	135:176b8275d35d	1852	* @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
<>	135:176b8275d35d	1853	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1854	* @retval None
<>	135:176b8275d35d	1855	*/
<>	135:176b8275d35d	1856	__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1857	{
<>	135:176b8275d35d	1858	SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
<>	135:176b8275d35d	1859	}
<>	135:176b8275d35d	1860
<>	135:176b8275d35d	1861	/**
<>	135:176b8275d35d	1862	* @brief Disable automatic STOP condition generation (master mode).
<>	135:176b8275d35d	1863	* @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
<>	135:176b8275d35d	1864	* @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
<>	135:176b8275d35d	1865	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1866	* @retval None
<>	135:176b8275d35d	1867	*/
<>	135:176b8275d35d	1868	__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1869	{
<>	135:176b8275d35d	1870	CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
<>	135:176b8275d35d	1871	}
<>	135:176b8275d35d	1872
<>	135:176b8275d35d	1873	/**
<>	135:176b8275d35d	1874	* @brief Check if automatic STOP condition is enabled or disabled.
<>	135:176b8275d35d	1875	* @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
<>	135:176b8275d35d	1876	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1877	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1878	*/
<>	135:176b8275d35d	1879	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1880	{
<>	135:176b8275d35d	1881	return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND));
<>	135:176b8275d35d	1882	}
<>	135:176b8275d35d	1883
<>	135:176b8275d35d	1884	/**
<>	135:176b8275d35d	1885	* @brief Enable reload mode (master mode).
<>	135:176b8275d35d	1886	* @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
<>	135:176b8275d35d	1887	* @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
<>	135:176b8275d35d	1888	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1889	* @retval None
<>	135:176b8275d35d	1890	*/
<>	135:176b8275d35d	1891	__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1892	{
<>	135:176b8275d35d	1893	SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
<>	135:176b8275d35d	1894	}
<>	135:176b8275d35d	1895
<>	135:176b8275d35d	1896	/**
<>	135:176b8275d35d	1897	* @brief Disable reload mode (master mode).
<>	135:176b8275d35d	1898	* @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
<>	135:176b8275d35d	1899	* @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
<>	135:176b8275d35d	1900	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1901	* @retval None
<>	135:176b8275d35d	1902	*/
<>	135:176b8275d35d	1903	__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1904	{
<>	135:176b8275d35d	1905	CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
<>	135:176b8275d35d	1906	}
<>	135:176b8275d35d	1907
<>	135:176b8275d35d	1908	/**
<>	135:176b8275d35d	1909	* @brief Check if reload mode is enabled or disabled.
<>	135:176b8275d35d	1910	* @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
<>	135:176b8275d35d	1911	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1912	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	1913	*/
<>	135:176b8275d35d	1914	__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1915	{
<>	135:176b8275d35d	1916	return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD));
<>	135:176b8275d35d	1917	}
<>	135:176b8275d35d	1918
<>	135:176b8275d35d	1919	/**
<>	135:176b8275d35d	1920	* @brief Configure the number of bytes for transfer.
<>	135:176b8275d35d	1921	* @note Changing these bits when START bit is set is not allowed.
<>	135:176b8275d35d	1922	* @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
<>	135:176b8275d35d	1923	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1924	* @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
<>	135:176b8275d35d	1925	* @retval None
<>	135:176b8275d35d	1926	*/
<>	135:176b8275d35d	1927	__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
<>	135:176b8275d35d	1928	{
<>	135:176b8275d35d	1929	MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
<>	135:176b8275d35d	1930	}
<>	135:176b8275d35d	1931
<>	135:176b8275d35d	1932	/**
<>	135:176b8275d35d	1933	* @brief Get the number of bytes configured for transfer.
<>	135:176b8275d35d	1934	* @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
<>	135:176b8275d35d	1935	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1936	* @retval Value between Min_Data=0x0 and Max_Data=0xFF
<>	135:176b8275d35d	1937	*/
<>	135:176b8275d35d	1938	__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1939	{
<>	135:176b8275d35d	1940	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
<>	135:176b8275d35d	1941	}
<>	135:176b8275d35d	1942
<>	135:176b8275d35d	1943	/**
<>	135:176b8275d35d	1944	* @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
<>	135:176b8275d35d	1945	* @note Usage in Slave mode only.
<>	135:176b8275d35d	1946	* @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
<>	135:176b8275d35d	1947	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1948	* @param TypeAcknowledge This parameter can be one of the following values:
<>	135:176b8275d35d	1949	* @arg @ref LL_I2C_ACK
<>	135:176b8275d35d	1950	* @arg @ref LL_I2C_NACK
<>	135:176b8275d35d	1951	* @retval None
<>	135:176b8275d35d	1952	*/
<>	135:176b8275d35d	1953	__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
<>	135:176b8275d35d	1954	{
<>	135:176b8275d35d	1955	MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
<>	135:176b8275d35d	1956	}
<>	135:176b8275d35d	1957
<>	135:176b8275d35d	1958	/**
<>	135:176b8275d35d	1959	* @brief Generate a START or RESTART condition
<>	135:176b8275d35d	1960	* @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
<>	135:176b8275d35d	1961	* This action has no effect when RELOAD is set.
<>	135:176b8275d35d	1962	* @rmtoll CR2 START LL_I2C_GenerateStartCondition
<>	135:176b8275d35d	1963	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1964	* @retval None
<>	135:176b8275d35d	1965	*/
<>	135:176b8275d35d	1966	__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1967	{
<>	135:176b8275d35d	1968	SET_BIT(I2Cx->CR2, I2C_CR2_START);
<>	135:176b8275d35d	1969	}
<>	135:176b8275d35d	1970
<>	135:176b8275d35d	1971	/**
<>	135:176b8275d35d	1972	* @brief Generate a STOP condition after the current byte transfer (master mode).
<>	135:176b8275d35d	1973	* @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
<>	135:176b8275d35d	1974	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1975	* @retval None
<>	135:176b8275d35d	1976	*/
<>	135:176b8275d35d	1977	__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1978	{
<>	135:176b8275d35d	1979	SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
<>	135:176b8275d35d	1980	}
<>	135:176b8275d35d	1981
<>	135:176b8275d35d	1982	/**
<>	135:176b8275d35d	1983	* @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
<>	135:176b8275d35d	1984	* @note The master sends the complete 10bit slave address read sequence :
<>	135:176b8275d35d	1985	* Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
<>	135:176b8275d35d	1986	* @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
<>	135:176b8275d35d	1987	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	1988	* @retval None
<>	135:176b8275d35d	1989	*/
<>	135:176b8275d35d	1990	__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	1991	{
<>	135:176b8275d35d	1992	CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
<>	135:176b8275d35d	1993	}
<>	135:176b8275d35d	1994
<>	135:176b8275d35d	1995	/**
<>	135:176b8275d35d	1996	* @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
<>	135:176b8275d35d	1997	* @note The master only sends the first 7 bits of 10bit address in Read direction.
<>	135:176b8275d35d	1998	* @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
<>	135:176b8275d35d	1999	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	2000	* @retval None
<>	135:176b8275d35d	2001	*/
<>	135:176b8275d35d	2002	__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	2003	{
<>	135:176b8275d35d	2004	SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
<>	135:176b8275d35d	2005	}
<>	135:176b8275d35d	2006
<>	135:176b8275d35d	2007	/**
<>	135:176b8275d35d	2008	* @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
<>	135:176b8275d35d	2009	* @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
<>	135:176b8275d35d	2010	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	2011	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	2012	*/
<>	135:176b8275d35d	2013	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	2014	{
<>	135:176b8275d35d	2015	return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R));
<>	135:176b8275d35d	2016	}
<>	135:176b8275d35d	2017
<>	135:176b8275d35d	2018	/**
<>	135:176b8275d35d	2019	* @brief Configure the transfer direction (master mode).
<>	135:176b8275d35d	2020	* @note Changing these bits when START bit is set is not allowed.
<>	135:176b8275d35d	2021	* @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
<>	135:176b8275d35d	2022	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	2023	* @param TransferRequest This parameter can be one of the following values:
<>	135:176b8275d35d	2024	* @arg @ref LL_I2C_REQUEST_WRITE
<>	135:176b8275d35d	2025	* @arg @ref LL_I2C_REQUEST_READ
<>	135:176b8275d35d	2026	* @retval None
<>	135:176b8275d35d	2027	*/
<>	135:176b8275d35d	2028	__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
<>	135:176b8275d35d	2029	{
<>	135:176b8275d35d	2030	MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
<>	135:176b8275d35d	2031	}
<>	135:176b8275d35d	2032
<>	135:176b8275d35d	2033	/**
<>	135:176b8275d35d	2034	* @brief Get the transfer direction requested (master mode).
<>	135:176b8275d35d	2035	* @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
<>	135:176b8275d35d	2036	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	2037	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	2038	* @arg @ref LL_I2C_REQUEST_WRITE
<>	135:176b8275d35d	2039	* @arg @ref LL_I2C_REQUEST_READ
<>	135:176b8275d35d	2040	*/
<>	135:176b8275d35d	2041	__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	2042	{
<>	135:176b8275d35d	2043	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
<>	135:176b8275d35d	2044	}
<>	135:176b8275d35d	2045
<>	135:176b8275d35d	2046	/**
<>	135:176b8275d35d	2047	* @brief Configure the slave address for transfer (master mode).
<>	135:176b8275d35d	2048	* @note Changing these bits when START bit is set is not allowed.
<>	135:176b8275d35d	2049	* @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
<>	135:176b8275d35d	2050	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	2051	* @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
<>	135:176b8275d35d	2052	* @retval None
<>	135:176b8275d35d	2053	*/
<>	135:176b8275d35d	2054	__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
<>	135:176b8275d35d	2055	{
<>	135:176b8275d35d	2056	MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
<>	135:176b8275d35d	2057	}
<>	135:176b8275d35d	2058
<>	135:176b8275d35d	2059	/**
<>	135:176b8275d35d	2060	* @brief Get the slave address programmed for transfer.
<>	135:176b8275d35d	2061	* @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
<>	135:176b8275d35d	2062	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	2063	* @retval Value between Min_Data=0x0 and Max_Data=0x3F
<>	135:176b8275d35d	2064	*/
<>	135:176b8275d35d	2065	__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	2066	{
<>	135:176b8275d35d	2067	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
<>	135:176b8275d35d	2068	}
<>	135:176b8275d35d	2069
<>	135:176b8275d35d	2070	/**
<>	135:176b8275d35d	2071	* @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
<>	135:176b8275d35d	2072	* @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
<>	135:176b8275d35d	2073	* CR2 ADD10 LL_I2C_HandleTransfer\n
<>	135:176b8275d35d	2074	* CR2 RD_WRN LL_I2C_HandleTransfer\n
<>	135:176b8275d35d	2075	* CR2 START LL_I2C_HandleTransfer\n
<>	135:176b8275d35d	2076	* CR2 STOP LL_I2C_HandleTransfer\n
<>	135:176b8275d35d	2077	* CR2 RELOAD LL_I2C_HandleTransfer\n
<>	135:176b8275d35d	2078	* CR2 NBYTES LL_I2C_HandleTransfer\n
<>	135:176b8275d35d	2079	* CR2 AUTOEND LL_I2C_HandleTransfer\n
<>	135:176b8275d35d	2080	* CR2 HEAD10R LL_I2C_HandleTransfer
<>	135:176b8275d35d	2081	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	2082	* @param SlaveAddr Specifies the slave address to be programmed.
<>	135:176b8275d35d	2083	* @param SlaveAddrSize This parameter can be one of the following values:
<>	135:176b8275d35d	2084	* @arg @ref LL_I2C_ADDRSLAVE_7BIT
<>	135:176b8275d35d	2085	* @arg @ref LL_I2C_ADDRSLAVE_10BIT
<>	135:176b8275d35d	2086	* @param TransferSize Specifies the number of bytes to be programmed.
<>	135:176b8275d35d	2087	* This parameter must be a value between Min_Data=0 and Max_Data=255.
<>	135:176b8275d35d	2088	* @param EndMode This parameter can be one of the following values:
<>	135:176b8275d35d	2089	* @arg @ref LL_I2C_MODE_RELOAD
<>	135:176b8275d35d	2090	* @arg @ref LL_I2C_MODE_AUTOEND
<>	135:176b8275d35d	2091	* @arg @ref LL_I2C_MODE_SOFTEND
<>	135:176b8275d35d	2092	* @arg @ref LL_I2C_MODE_SMBUS_RELOAD
<>	135:176b8275d35d	2093	* @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
<>	135:176b8275d35d	2094	* @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
<>	135:176b8275d35d	2095	* @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
<>	135:176b8275d35d	2096	* @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
<>	135:176b8275d35d	2097	* @param Request This parameter can be one of the following values:
<>	135:176b8275d35d	2098	* @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
<>	135:176b8275d35d	2099	* @arg @ref LL_I2C_GENERATE_STOP
<>	135:176b8275d35d	2100	* @arg @ref LL_I2C_GENERATE_START_READ
<>	135:176b8275d35d	2101	* @arg @ref LL_I2C_GENERATE_START_WRITE
<>	135:176b8275d35d	2102	* @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
<>	135:176b8275d35d	2103	* @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
<>	135:176b8275d35d	2104	* @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
<>	135:176b8275d35d	2105	* @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
<>	135:176b8275d35d	2106	* @retval None
<>	135:176b8275d35d	2107	*/
<>	135:176b8275d35d	2108	__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
<>	135:176b8275d35d	2109	uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
<>	135:176b8275d35d	2110	{
<>	135:176b8275d35d	2111	MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD \| I2C_CR2_ADD10 \| I2C_CR2_RD_WRN \| I2C_CR2_START \| I2C_CR2_STOP \| I2C_CR2_RELOAD \|
<>	135:176b8275d35d	2112	I2C_CR2_NBYTES \| I2C_CR2_AUTOEND \| I2C_CR2_HEAD10R,
<>	135:176b8275d35d	2113	SlaveAddr \| SlaveAddrSize \| TransferSize << I2C_CR2_NBYTES_Pos \| EndMode \| Request);
<>	135:176b8275d35d	2114	}
<>	135:176b8275d35d	2115
<>	135:176b8275d35d	2116	/**
<>	135:176b8275d35d	2117	* @brief Indicate the value of transfer direction (slave mode).
<>	135:176b8275d35d	2118	* @note RESET: Write transfer, Slave enters in receiver mode.
<>	135:176b8275d35d	2119	* SET: Read transfer, Slave enters in transmitter mode.
<>	135:176b8275d35d	2120	* @rmtoll ISR DIR LL_I2C_GetTransferDirection
<>	135:176b8275d35d	2121	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	2122	* @retval Returned value can be one of the following values:
<>	135:176b8275d35d	2123	* @arg @ref LL_I2C_DIRECTION_WRITE
<>	135:176b8275d35d	2124	* @arg @ref LL_I2C_DIRECTION_READ
<>	135:176b8275d35d	2125	*/
<>	135:176b8275d35d	2126	__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	2127	{
<>	135:176b8275d35d	2128	return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
<>	135:176b8275d35d	2129	}
<>	135:176b8275d35d	2130
<>	135:176b8275d35d	2131	/**
<>	135:176b8275d35d	2132	* @brief Return the slave matched address.
<>	135:176b8275d35d	2133	* @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
<>	135:176b8275d35d	2134	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	2135	* @retval Value between Min_Data=0x00 and Max_Data=0x3F
<>	135:176b8275d35d	2136	*/
<>	135:176b8275d35d	2137	__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	2138	{
<>	135:176b8275d35d	2139	return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
<>	135:176b8275d35d	2140	}
<>	135:176b8275d35d	2141
<>	135:176b8275d35d	2142	/**
<>	135:176b8275d35d	2143	* @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
<>	135:176b8275d35d	2144	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	2145	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	2146	* @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
<>	135:176b8275d35d	2147	* This bit has no effect when RELOAD bit is set.
<>	135:176b8275d35d	2148	* This bit has no effect in device mode when SBC bit is not set.
<>	135:176b8275d35d	2149	* @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
<>	135:176b8275d35d	2150	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	2151	* @retval None
<>	135:176b8275d35d	2152	*/
<>	135:176b8275d35d	2153	__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	2154	{
<>	135:176b8275d35d	2155	SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
<>	135:176b8275d35d	2156	}
<>	135:176b8275d35d	2157
<>	135:176b8275d35d	2158	/**
<>	135:176b8275d35d	2159	* @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
<>	135:176b8275d35d	2160	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	2161	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	2162	* @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
<>	135:176b8275d35d	2163	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	2164	* @retval State of bit (1 or 0).
<>	135:176b8275d35d	2165	*/
<>	135:176b8275d35d	2166	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	2167	{
<>	135:176b8275d35d	2168	return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE));
<>	135:176b8275d35d	2169	}
<>	135:176b8275d35d	2170
<>	135:176b8275d35d	2171	/**
<>	135:176b8275d35d	2172	* @brief Get the SMBus Packet Error byte calculated.
<>	135:176b8275d35d	2173	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	135:176b8275d35d	2174	* SMBus feature is supported by the I2Cx Instance.
<>	135:176b8275d35d	2175	* @rmtoll PECR PEC LL_I2C_GetSMBusPEC
<>	135:176b8275d35d	2176	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	2177	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	135:176b8275d35d	2178	*/
<>	135:176b8275d35d	2179	__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	2180	{
<>	135:176b8275d35d	2181	return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
<>	135:176b8275d35d	2182	}
<>	135:176b8275d35d	2183
<>	135:176b8275d35d	2184	/**
<>	135:176b8275d35d	2185	* @brief Read Receive Data register.
<>	135:176b8275d35d	2186	* @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
<>	135:176b8275d35d	2187	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	2188	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	135:176b8275d35d	2189	*/
<>	135:176b8275d35d	2190	__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
<>	135:176b8275d35d	2191	{
<>	135:176b8275d35d	2192	return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
<>	135:176b8275d35d	2193	}
<>	135:176b8275d35d	2194
<>	135:176b8275d35d	2195	/**
<>	135:176b8275d35d	2196	* @brief Write in Transmit Data Register .
<>	135:176b8275d35d	2197	* @rmtoll TXDR TXDATA LL_I2C_TransmitData8
<>	135:176b8275d35d	2198	* @param I2Cx I2C Instance.
<>	135:176b8275d35d	2199	* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
<>	135:176b8275d35d	2200	* @retval None
<>	135:176b8275d35d	2201	*/
<>	135:176b8275d35d	2202	__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
<>	135:176b8275d35d	2203	{
<>	135:176b8275d35d	2204	WRITE_REG(I2Cx->TXDR, Data);
<>	135:176b8275d35d	2205	}
<>	135:176b8275d35d	2206
<>	135:176b8275d35d	2207	/**
<>	135:176b8275d35d	2208	* @}
<>	135:176b8275d35d	2209	*/
<>	135:176b8275d35d	2210
<>	135:176b8275d35d	2211	#if defined(USE_FULL_LL_DRIVER)
<>	135:176b8275d35d	2212	/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
<>	135:176b8275d35d	2213	* @{
<>	135:176b8275d35d	2214	*/
<>	135:176b8275d35d	2215
<>	135:176b8275d35d	2216	uint32_t LL_I2C_Init(I2C_TypeDef I2Cx, LL_I2C_InitTypeDef I2C_InitStruct);
<>	135:176b8275d35d	2217	uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
<>	135:176b8275d35d	2218	void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
<>	135:176b8275d35d	2219
<>	135:176b8275d35d	2220
<>	135:176b8275d35d	2221	/**
<>	135:176b8275d35d	2222	* @}
<>	135:176b8275d35d	2223	*/
<>	135:176b8275d35d	2224	#endif /* USE_FULL_LL_DRIVER */
<>	135:176b8275d35d	2225
<>	135:176b8275d35d	2226	/**
<>	135:176b8275d35d	2227	* @}
<>	135:176b8275d35d	2228	*/
<>	135:176b8275d35d	2229
<>	135:176b8275d35d	2230	/**
<>	135:176b8275d35d	2231	* @}
<>	135:176b8275d35d	2232	*/
<>	135:176b8275d35d	2233
<>	135:176b8275d35d	2234	#endif /* I2C1 \|\| I2C2 \|\| I2C3 */
<>	135:176b8275d35d	2235
<>	135:176b8275d35d	2236	/**
<>	135:176b8275d35d	2237	* @}
<>	135:176b8275d35d	2238	*/
<>	135:176b8275d35d	2239
<>	135:176b8275d35d	2240	#ifdef __cplusplus
<>	135:176b8275d35d	2241	}
<>	135:176b8275d35d	2242	#endif
<>	135:176b8275d35d	2243
<>	135:176b8275d35d	2244	#endif /* __STM32F3xx_LL_I2C_H */
<>	135:176b8275d35d	2245
<>	135:176b8275d35d	2246	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/