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TARGET_NUCLEO_F334R8/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_cortex.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
135:176b8275d35d
Child:
168:b9e159c1930a
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 135:176b8275d35d 1 /**
<> 135:176b8275d35d 2 ******************************************************************************
<> 135:176b8275d35d 3 * @file stm32f3xx_ll_cortex.h
<> 135:176b8275d35d 4 * @author MCD Application Team
<> 135:176b8275d35d 5 * @version V1.4.0
<> 135:176b8275d35d 6 * @date 16-December-2016
<> 135:176b8275d35d 7 * @brief Header file of CORTEX LL module.
<> 135:176b8275d35d 8 @verbatim
<> 135:176b8275d35d 9 ==============================================================================
<> 135:176b8275d35d 10 ##### How to use this driver #####
<> 135:176b8275d35d 11 ==============================================================================
<> 135:176b8275d35d 12 [..]
<> 135:176b8275d35d 13 The LL CORTEX driver contains a set of generic APIs that can be
<> 135:176b8275d35d 14 used by user:
<> 135:176b8275d35d 15 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
<> 135:176b8275d35d 16 functions
<> 135:176b8275d35d 17 (+) Low power mode configuration (SCB register of Cortex-MCU)
<> 135:176b8275d35d 18 (+) MPU API to configure and enable regions
<> 135:176b8275d35d 19 (MPU services provided only on some devices)
<> 135:176b8275d35d 20 (+) API to access to MCU info (CPUID register)
<> 135:176b8275d35d 21 (+) API to enable fault handler (SHCSR accesses)
<> 135:176b8275d35d 22
<> 135:176b8275d35d 23 @endverbatim
<> 135:176b8275d35d 24 ******************************************************************************
<> 135:176b8275d35d 25 * @attention
<> 135:176b8275d35d 26 *
<> 135:176b8275d35d 27 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 135:176b8275d35d 28 *
<> 135:176b8275d35d 29 * Redistribution and use in source and binary forms, with or without modification,
<> 135:176b8275d35d 30 * are permitted provided that the following conditions are met:
<> 135:176b8275d35d 31 * 1. Redistributions of source code must retain the above copyright notice,
<> 135:176b8275d35d 32 * this list of conditions and the following disclaimer.
<> 135:176b8275d35d 33 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 135:176b8275d35d 34 * this list of conditions and the following disclaimer in the documentation
<> 135:176b8275d35d 35 * and/or other materials provided with the distribution.
<> 135:176b8275d35d 36 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 135:176b8275d35d 37 * may be used to endorse or promote products derived from this software
<> 135:176b8275d35d 38 * without specific prior written permission.
<> 135:176b8275d35d 39 *
<> 135:176b8275d35d 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 135:176b8275d35d 41 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 135:176b8275d35d 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 135:176b8275d35d 43 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 135:176b8275d35d 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 135:176b8275d35d 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 135:176b8275d35d 46 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 135:176b8275d35d 47 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 135:176b8275d35d 48 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 135:176b8275d35d 49 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 135:176b8275d35d 50 *
<> 135:176b8275d35d 51 ******************************************************************************
<> 135:176b8275d35d 52 */
<> 135:176b8275d35d 53
<> 135:176b8275d35d 54 /* Define to prevent recursive inclusion -------------------------------------*/
<> 135:176b8275d35d 55 #ifndef __STM32F3xx_LL_CORTEX_H
<> 135:176b8275d35d 56 #define __STM32F3xx_LL_CORTEX_H
<> 135:176b8275d35d 57
<> 135:176b8275d35d 58 #ifdef __cplusplus
<> 135:176b8275d35d 59 extern "C" {
<> 135:176b8275d35d 60 #endif
<> 135:176b8275d35d 61
<> 135:176b8275d35d 62 /* Includes ------------------------------------------------------------------*/
<> 135:176b8275d35d 63 #include "stm32f3xx.h"
<> 135:176b8275d35d 64
<> 135:176b8275d35d 65 /** @addtogroup STM32F3xx_LL_Driver
<> 135:176b8275d35d 66 * @{
<> 135:176b8275d35d 67 */
<> 135:176b8275d35d 68
<> 135:176b8275d35d 69 /** @defgroup CORTEX_LL CORTEX
<> 135:176b8275d35d 70 * @{
<> 135:176b8275d35d 71 */
<> 135:176b8275d35d 72
<> 135:176b8275d35d 73 /* Private types -------------------------------------------------------------*/
<> 135:176b8275d35d 74 /* Private variables ---------------------------------------------------------*/
<> 135:176b8275d35d 75
<> 135:176b8275d35d 76 /* Private constants ---------------------------------------------------------*/
<> 135:176b8275d35d 77
<> 135:176b8275d35d 78 /* Private macros ------------------------------------------------------------*/
<> 135:176b8275d35d 79
<> 135:176b8275d35d 80 /* Exported types ------------------------------------------------------------*/
<> 135:176b8275d35d 81 /* Exported constants --------------------------------------------------------*/
<> 135:176b8275d35d 82 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
<> 135:176b8275d35d 83 * @{
<> 135:176b8275d35d 84 */
<> 135:176b8275d35d 85
<> 135:176b8275d35d 86 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
<> 135:176b8275d35d 87 * @{
<> 135:176b8275d35d 88 */
<> 135:176b8275d35d 89 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) /*!< AHB clock divided by 8 selected as SysTick clock source.*/
<> 135:176b8275d35d 90 #define LL_SYSTICK_CLKSOURCE_HCLK ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock selected as SysTick clock source. */
<> 135:176b8275d35d 91 /**
<> 135:176b8275d35d 92 * @}
<> 135:176b8275d35d 93 */
<> 135:176b8275d35d 94
<> 135:176b8275d35d 95 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
<> 135:176b8275d35d 96 * @{
<> 135:176b8275d35d 97 */
<> 135:176b8275d35d 98 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
<> 135:176b8275d35d 99 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
<> 135:176b8275d35d 100 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
<> 135:176b8275d35d 101 /**
<> 135:176b8275d35d 102 * @}
<> 135:176b8275d35d 103 */
<> 135:176b8275d35d 104
<> 135:176b8275d35d 105 #if __MPU_PRESENT
<> 135:176b8275d35d 106
<> 135:176b8275d35d 107 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
<> 135:176b8275d35d 108 * @{
<> 135:176b8275d35d 109 */
<> 135:176b8275d35d 110 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) /*!< Disable NMI and privileged SW access */
<> 135:176b8275d35d 111 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
<> 135:176b8275d35d 112 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
<> 135:176b8275d35d 113 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
<> 135:176b8275d35d 114 /**
<> 135:176b8275d35d 115 * @}
<> 135:176b8275d35d 116 */
<> 135:176b8275d35d 117
<> 135:176b8275d35d 118 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
<> 135:176b8275d35d 119 * @{
<> 135:176b8275d35d 120 */
<> 135:176b8275d35d 121 #define LL_MPU_REGION_NUMBER0 ((uint32_t)0x00U) /*!< REGION Number 0 */
<> 135:176b8275d35d 122 #define LL_MPU_REGION_NUMBER1 ((uint32_t)0x01U) /*!< REGION Number 1 */
<> 135:176b8275d35d 123 #define LL_MPU_REGION_NUMBER2 ((uint32_t)0x02U) /*!< REGION Number 2 */
<> 135:176b8275d35d 124 #define LL_MPU_REGION_NUMBER3 ((uint32_t)0x03U) /*!< REGION Number 3 */
<> 135:176b8275d35d 125 #define LL_MPU_REGION_NUMBER4 ((uint32_t)0x04U) /*!< REGION Number 4 */
<> 135:176b8275d35d 126 #define LL_MPU_REGION_NUMBER5 ((uint32_t)0x05U) /*!< REGION Number 5 */
<> 135:176b8275d35d 127 #define LL_MPU_REGION_NUMBER6 ((uint32_t)0x06U) /*!< REGION Number 6 */
<> 135:176b8275d35d 128 #define LL_MPU_REGION_NUMBER7 ((uint32_t)0x07U) /*!< REGION Number 7 */
<> 135:176b8275d35d 129 /**
<> 135:176b8275d35d 130 * @}
<> 135:176b8275d35d 131 */
<> 135:176b8275d35d 132
<> 135:176b8275d35d 133 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
<> 135:176b8275d35d 134 * @{
<> 135:176b8275d35d 135 */
<> 135:176b8275d35d 136 #define LL_MPU_REGION_SIZE_32B ((uint32_t)(0x04U << MPU_RASR_SIZE_Pos)) /*!< 32B Size of the MPU protection region */
<> 135:176b8275d35d 137 #define LL_MPU_REGION_SIZE_64B ((uint32_t)(0x05U << MPU_RASR_SIZE_Pos)) /*!< 64B Size of the MPU protection region */
<> 135:176b8275d35d 138 #define LL_MPU_REGION_SIZE_128B ((uint32_t)(0x06U << MPU_RASR_SIZE_Pos)) /*!< 128B Size of the MPU protection region */
<> 135:176b8275d35d 139 #define LL_MPU_REGION_SIZE_256B ((uint32_t)(0x07U << MPU_RASR_SIZE_Pos)) /*!< 256B Size of the MPU protection region */
<> 135:176b8275d35d 140 #define LL_MPU_REGION_SIZE_512B ((uint32_t)(0x08U << MPU_RASR_SIZE_Pos)) /*!< 512B Size of the MPU protection region */
<> 135:176b8275d35d 141 #define LL_MPU_REGION_SIZE_1KB ((uint32_t)(0x09U << MPU_RASR_SIZE_Pos)) /*!< 1KB Size of the MPU protection region */
<> 135:176b8275d35d 142 #define LL_MPU_REGION_SIZE_2KB ((uint32_t)(0x0AU << MPU_RASR_SIZE_Pos)) /*!< 2KB Size of the MPU protection region */
<> 135:176b8275d35d 143 #define LL_MPU_REGION_SIZE_4KB ((uint32_t)(0x0BU << MPU_RASR_SIZE_Pos)) /*!< 4KB Size of the MPU protection region */
<> 135:176b8275d35d 144 #define LL_MPU_REGION_SIZE_8KB ((uint32_t)(0x0CU << MPU_RASR_SIZE_Pos)) /*!< 8KB Size of the MPU protection region */
<> 135:176b8275d35d 145 #define LL_MPU_REGION_SIZE_16KB ((uint32_t)(0x0DU << MPU_RASR_SIZE_Pos)) /*!< 16KB Size of the MPU protection region */
<> 135:176b8275d35d 146 #define LL_MPU_REGION_SIZE_32KB ((uint32_t)(0x0EU << MPU_RASR_SIZE_Pos)) /*!< 32KB Size of the MPU protection region */
<> 135:176b8275d35d 147 #define LL_MPU_REGION_SIZE_64KB ((uint32_t)(0x0FU << MPU_RASR_SIZE_Pos)) /*!< 64KB Size of the MPU protection region */
<> 135:176b8275d35d 148 #define LL_MPU_REGION_SIZE_128KB ((uint32_t)(0x10U << MPU_RASR_SIZE_Pos)) /*!< 128KB Size of the MPU protection region */
<> 135:176b8275d35d 149 #define LL_MPU_REGION_SIZE_256KB ((uint32_t)(0x11U << MPU_RASR_SIZE_Pos)) /*!< 256KB Size of the MPU protection region */
<> 135:176b8275d35d 150 #define LL_MPU_REGION_SIZE_512KB ((uint32_t)(0x12U << MPU_RASR_SIZE_Pos)) /*!< 512KB Size of the MPU protection region */
<> 135:176b8275d35d 151 #define LL_MPU_REGION_SIZE_1MB ((uint32_t)(0x13U << MPU_RASR_SIZE_Pos)) /*!< 1MB Size of the MPU protection region */
<> 135:176b8275d35d 152 #define LL_MPU_REGION_SIZE_2MB ((uint32_t)(0x14U << MPU_RASR_SIZE_Pos)) /*!< 2MB Size of the MPU protection region */
<> 135:176b8275d35d 153 #define LL_MPU_REGION_SIZE_4MB ((uint32_t)(0x15U << MPU_RASR_SIZE_Pos)) /*!< 4MB Size of the MPU protection region */
<> 135:176b8275d35d 154 #define LL_MPU_REGION_SIZE_8MB ((uint32_t)(0x16U << MPU_RASR_SIZE_Pos)) /*!< 8MB Size of the MPU protection region */
<> 135:176b8275d35d 155 #define LL_MPU_REGION_SIZE_16MB ((uint32_t)(0x17U << MPU_RASR_SIZE_Pos)) /*!< 16MB Size of the MPU protection region */
<> 135:176b8275d35d 156 #define LL_MPU_REGION_SIZE_32MB ((uint32_t)(0x18U << MPU_RASR_SIZE_Pos)) /*!< 32MB Size of the MPU protection region */
<> 135:176b8275d35d 157 #define LL_MPU_REGION_SIZE_64MB ((uint32_t)(0x19U << MPU_RASR_SIZE_Pos)) /*!< 64MB Size of the MPU protection region */
<> 135:176b8275d35d 158 #define LL_MPU_REGION_SIZE_128MB ((uint32_t)(0x1AU << MPU_RASR_SIZE_Pos)) /*!< 128MB Size of the MPU protection region */
<> 135:176b8275d35d 159 #define LL_MPU_REGION_SIZE_256MB ((uint32_t)(0x1BU << MPU_RASR_SIZE_Pos)) /*!< 256MB Size of the MPU protection region */
<> 135:176b8275d35d 160 #define LL_MPU_REGION_SIZE_512MB ((uint32_t)(0x1CU << MPU_RASR_SIZE_Pos)) /*!< 512MB Size of the MPU protection region */
<> 135:176b8275d35d 161 #define LL_MPU_REGION_SIZE_1GB ((uint32_t)(0x1DU << MPU_RASR_SIZE_Pos)) /*!< 1GB Size of the MPU protection region */
<> 135:176b8275d35d 162 #define LL_MPU_REGION_SIZE_2GB ((uint32_t)(0x1EU << MPU_RASR_SIZE_Pos)) /*!< 2GB Size of the MPU protection region */
<> 135:176b8275d35d 163 #define LL_MPU_REGION_SIZE_4GB ((uint32_t)(0x1FU << MPU_RASR_SIZE_Pos)) /*!< 4GB Size of the MPU protection region */
<> 135:176b8275d35d 164 /**
<> 135:176b8275d35d 165 * @}
<> 135:176b8275d35d 166 */
<> 135:176b8275d35d 167
<> 135:176b8275d35d 168 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
<> 135:176b8275d35d 169 * @{
<> 135:176b8275d35d 170 */
<> 135:176b8275d35d 171 #define LL_MPU_REGION_NO_ACCESS ((uint32_t)(0x00U << MPU_RASR_AP_Pos)) /*!< No access*/
<> 135:176b8275d35d 172 #define LL_MPU_REGION_PRIV_RW ((uint32_t)(0x01U << MPU_RASR_AP_Pos)) /*!< RW privileged (privileged access only)*/
<> 135:176b8275d35d 173 #define LL_MPU_REGION_PRIV_RW_URO ((uint32_t)(0x02U << MPU_RASR_AP_Pos)) /*!< RW privileged - RO user (Write in a user program generates a fault) */
<> 135:176b8275d35d 174 #define LL_MPU_REGION_FULL_ACCESS ((uint32_t)(0x03U << MPU_RASR_AP_Pos)) /*!< RW privileged & user (Full access) */
<> 135:176b8275d35d 175 #define LL_MPU_REGION_PRIV_RO ((uint32_t)(0x05U << MPU_RASR_AP_Pos)) /*!< RO privileged (privileged read only)*/
<> 135:176b8275d35d 176 #define LL_MPU_REGION_PRIV_RO_URO ((uint32_t)(0x06U << MPU_RASR_AP_Pos)) /*!< RO privileged & user (read only) */
<> 135:176b8275d35d 177 /**
<> 135:176b8275d35d 178 * @}
<> 135:176b8275d35d 179 */
<> 135:176b8275d35d 180
<> 135:176b8275d35d 181 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
<> 135:176b8275d35d 182 * @{
<> 135:176b8275d35d 183 */
<> 135:176b8275d35d 184 #define LL_MPU_TEX_LEVEL0 ((uint32_t)(0x00U << MPU_RASR_TEX_Pos)) /*!< b000 for TEX bits */
<> 135:176b8275d35d 185 #define LL_MPU_TEX_LEVEL1 ((uint32_t)(0x01U << MPU_RASR_TEX_Pos)) /*!< b001 for TEX bits */
<> 135:176b8275d35d 186 #define LL_MPU_TEX_LEVEL2 ((uint32_t)(0x02U << MPU_RASR_TEX_Pos)) /*!< b010 for TEX bits */
<> 135:176b8275d35d 187 #define LL_MPU_TEX_LEVEL4 ((uint32_t)(0x04U << MPU_RASR_TEX_Pos)) /*!< b100 for TEX bits */
<> 135:176b8275d35d 188 /**
<> 135:176b8275d35d 189 * @}
<> 135:176b8275d35d 190 */
<> 135:176b8275d35d 191
<> 135:176b8275d35d 192 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
<> 135:176b8275d35d 193 * @{
<> 135:176b8275d35d 194 */
<> 135:176b8275d35d 195 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE ((uint32_t)0x00U) /*!< Instruction fetches enabled */
<> 135:176b8275d35d 196 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
<> 135:176b8275d35d 197 /**
<> 135:176b8275d35d 198 * @}
<> 135:176b8275d35d 199 */
<> 135:176b8275d35d 200
<> 135:176b8275d35d 201 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
<> 135:176b8275d35d 202 * @{
<> 135:176b8275d35d 203 */
<> 135:176b8275d35d 204 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
<> 135:176b8275d35d 205 #define LL_MPU_ACCESS_NOT_SHAREABLE ((uint32_t)0x00U) /*!< Not Shareable memory attribute */
<> 135:176b8275d35d 206 /**
<> 135:176b8275d35d 207 * @}
<> 135:176b8275d35d 208 */
<> 135:176b8275d35d 209
<> 135:176b8275d35d 210 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
<> 135:176b8275d35d 211 * @{
<> 135:176b8275d35d 212 */
<> 135:176b8275d35d 213 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
<> 135:176b8275d35d 214 #define LL_MPU_ACCESS_NOT_CACHEABLE ((uint32_t)0x00U) /*!< Not Cacheable memory attribute */
<> 135:176b8275d35d 215 /**
<> 135:176b8275d35d 216 * @}
<> 135:176b8275d35d 217 */
<> 135:176b8275d35d 218
<> 135:176b8275d35d 219 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
<> 135:176b8275d35d 220 * @{
<> 135:176b8275d35d 221 */
<> 135:176b8275d35d 222 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
<> 135:176b8275d35d 223 #define LL_MPU_ACCESS_NOT_BUFFERABLE ((uint32_t)0x00U) /*!< Not Bufferable memory attribute */
<> 135:176b8275d35d 224 /**
<> 135:176b8275d35d 225 * @}
<> 135:176b8275d35d 226 */
<> 135:176b8275d35d 227 #endif /* __MPU_PRESENT */
<> 135:176b8275d35d 228 /**
<> 135:176b8275d35d 229 * @}
<> 135:176b8275d35d 230 */
<> 135:176b8275d35d 231
<> 135:176b8275d35d 232 /* Exported macro ------------------------------------------------------------*/
<> 135:176b8275d35d 233
<> 135:176b8275d35d 234 /* Exported functions --------------------------------------------------------*/
<> 135:176b8275d35d 235 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
<> 135:176b8275d35d 236 * @{
<> 135:176b8275d35d 237 */
<> 135:176b8275d35d 238
<> 135:176b8275d35d 239 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
<> 135:176b8275d35d 240 * @{
<> 135:176b8275d35d 241 */
<> 135:176b8275d35d 242
<> 135:176b8275d35d 243 /**
<> 135:176b8275d35d 244 * @brief This function checks if the Systick counter flag is active or not.
<> 135:176b8275d35d 245 * @note It can be used in timeout function on application side.
<> 135:176b8275d35d 246 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
<> 135:176b8275d35d 247 * @retval State of bit (1 or 0).
<> 135:176b8275d35d 248 */
<> 135:176b8275d35d 249 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
<> 135:176b8275d35d 250 {
<> 135:176b8275d35d 251 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
<> 135:176b8275d35d 252 }
<> 135:176b8275d35d 253
<> 135:176b8275d35d 254 /**
<> 135:176b8275d35d 255 * @brief Configures the SysTick clock source
<> 135:176b8275d35d 256 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
<> 135:176b8275d35d 257 * @param Source This parameter can be one of the following values:
<> 135:176b8275d35d 258 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
<> 135:176b8275d35d 259 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
<> 135:176b8275d35d 260 * @retval None
<> 135:176b8275d35d 261 */
<> 135:176b8275d35d 262 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
<> 135:176b8275d35d 263 {
<> 135:176b8275d35d 264 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
<> 135:176b8275d35d 265 {
<> 135:176b8275d35d 266 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
<> 135:176b8275d35d 267 }
<> 135:176b8275d35d 268 else
<> 135:176b8275d35d 269 {
<> 135:176b8275d35d 270 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
<> 135:176b8275d35d 271 }
<> 135:176b8275d35d 272 }
<> 135:176b8275d35d 273
<> 135:176b8275d35d 274 /**
<> 135:176b8275d35d 275 * @brief Get the SysTick clock source
<> 135:176b8275d35d 276 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
<> 135:176b8275d35d 277 * @retval Returned value can be one of the following values:
<> 135:176b8275d35d 278 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
<> 135:176b8275d35d 279 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
<> 135:176b8275d35d 280 */
<> 135:176b8275d35d 281 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
<> 135:176b8275d35d 282 {
<> 135:176b8275d35d 283 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
<> 135:176b8275d35d 284 }
<> 135:176b8275d35d 285
<> 135:176b8275d35d 286 /**
<> 135:176b8275d35d 287 * @brief Enable SysTick exception request
<> 135:176b8275d35d 288 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
<> 135:176b8275d35d 289 * @retval None
<> 135:176b8275d35d 290 */
<> 135:176b8275d35d 291 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
<> 135:176b8275d35d 292 {
<> 135:176b8275d35d 293 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
<> 135:176b8275d35d 294 }
<> 135:176b8275d35d 295
<> 135:176b8275d35d 296 /**
<> 135:176b8275d35d 297 * @brief Disable SysTick exception request
<> 135:176b8275d35d 298 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
<> 135:176b8275d35d 299 * @retval None
<> 135:176b8275d35d 300 */
<> 135:176b8275d35d 301 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
<> 135:176b8275d35d 302 {
<> 135:176b8275d35d 303 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
<> 135:176b8275d35d 304 }
<> 135:176b8275d35d 305
<> 135:176b8275d35d 306 /**
<> 135:176b8275d35d 307 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
<> 135:176b8275d35d 308 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
<> 135:176b8275d35d 309 * @retval State of bit (1 or 0).
<> 135:176b8275d35d 310 */
<> 135:176b8275d35d 311 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
<> 135:176b8275d35d 312 {
<> 135:176b8275d35d 313 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
<> 135:176b8275d35d 314 }
<> 135:176b8275d35d 315
<> 135:176b8275d35d 316 /**
<> 135:176b8275d35d 317 * @}
<> 135:176b8275d35d 318 */
<> 135:176b8275d35d 319
<> 135:176b8275d35d 320 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
<> 135:176b8275d35d 321 * @{
<> 135:176b8275d35d 322 */
<> 135:176b8275d35d 323
<> 135:176b8275d35d 324 /**
<> 135:176b8275d35d 325 * @brief Processor uses sleep as its low power mode
<> 135:176b8275d35d 326 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
<> 135:176b8275d35d 327 * @retval None
<> 135:176b8275d35d 328 */
<> 135:176b8275d35d 329 __STATIC_INLINE void LL_LPM_EnableSleep(void)
<> 135:176b8275d35d 330 {
<> 135:176b8275d35d 331 /* Clear SLEEPDEEP bit of Cortex System Control Register */
<> 135:176b8275d35d 332 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 135:176b8275d35d 333 }
<> 135:176b8275d35d 334
<> 135:176b8275d35d 335 /**
<> 135:176b8275d35d 336 * @brief Processor uses deep sleep as its low power mode
<> 135:176b8275d35d 337 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
<> 135:176b8275d35d 338 * @retval None
<> 135:176b8275d35d 339 */
<> 135:176b8275d35d 340 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
<> 135:176b8275d35d 341 {
<> 135:176b8275d35d 342 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 135:176b8275d35d 343 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 135:176b8275d35d 344 }
<> 135:176b8275d35d 345
<> 135:176b8275d35d 346 /**
<> 135:176b8275d35d 347 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
<> 135:176b8275d35d 348 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
<> 135:176b8275d35d 349 * empty main application.
<> 135:176b8275d35d 350 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
<> 135:176b8275d35d 351 * @retval None
<> 135:176b8275d35d 352 */
<> 135:176b8275d35d 353 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
<> 135:176b8275d35d 354 {
<> 135:176b8275d35d 355 /* Set SLEEPONEXIT bit of Cortex System Control Register */
<> 135:176b8275d35d 356 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
<> 135:176b8275d35d 357 }
<> 135:176b8275d35d 358
<> 135:176b8275d35d 359 /**
<> 135:176b8275d35d 360 * @brief Do not sleep when returning to Thread mode.
<> 135:176b8275d35d 361 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
<> 135:176b8275d35d 362 * @retval None
<> 135:176b8275d35d 363 */
<> 135:176b8275d35d 364 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
<> 135:176b8275d35d 365 {
<> 135:176b8275d35d 366 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
<> 135:176b8275d35d 367 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
<> 135:176b8275d35d 368 }
<> 135:176b8275d35d 369
<> 135:176b8275d35d 370 /**
<> 135:176b8275d35d 371 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
<> 135:176b8275d35d 372 * processor.
<> 135:176b8275d35d 373 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
<> 135:176b8275d35d 374 * @retval None
<> 135:176b8275d35d 375 */
<> 135:176b8275d35d 376 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
<> 135:176b8275d35d 377 {
<> 135:176b8275d35d 378 /* Set SEVEONPEND bit of Cortex System Control Register */
<> 135:176b8275d35d 379 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
<> 135:176b8275d35d 380 }
<> 135:176b8275d35d 381
<> 135:176b8275d35d 382 /**
<> 135:176b8275d35d 383 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
<> 135:176b8275d35d 384 * excluded
<> 135:176b8275d35d 385 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
<> 135:176b8275d35d 386 * @retval None
<> 135:176b8275d35d 387 */
<> 135:176b8275d35d 388 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
<> 135:176b8275d35d 389 {
<> 135:176b8275d35d 390 /* Clear SEVEONPEND bit of Cortex System Control Register */
<> 135:176b8275d35d 391 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
<> 135:176b8275d35d 392 }
<> 135:176b8275d35d 393
<> 135:176b8275d35d 394 /**
<> 135:176b8275d35d 395 * @}
<> 135:176b8275d35d 396 */
<> 135:176b8275d35d 397
<> 135:176b8275d35d 398 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
<> 135:176b8275d35d 399 * @{
<> 135:176b8275d35d 400 */
<> 135:176b8275d35d 401
<> 135:176b8275d35d 402 /**
<> 135:176b8275d35d 403 * @brief Enable a fault in System handler control register (SHCSR)
<> 135:176b8275d35d 404 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
<> 135:176b8275d35d 405 * @param Fault This parameter can be a combination of the following values:
<> 135:176b8275d35d 406 * @arg @ref LL_HANDLER_FAULT_USG
<> 135:176b8275d35d 407 * @arg @ref LL_HANDLER_FAULT_BUS
<> 135:176b8275d35d 408 * @arg @ref LL_HANDLER_FAULT_MEM
<> 135:176b8275d35d 409 * @retval None
<> 135:176b8275d35d 410 */
<> 135:176b8275d35d 411 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
<> 135:176b8275d35d 412 {
<> 135:176b8275d35d 413 /* Enable the system handler fault */
<> 135:176b8275d35d 414 SET_BIT(SCB->SHCSR, Fault);
<> 135:176b8275d35d 415 }
<> 135:176b8275d35d 416
<> 135:176b8275d35d 417 /**
<> 135:176b8275d35d 418 * @brief Disable a fault in System handler control register (SHCSR)
<> 135:176b8275d35d 419 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
<> 135:176b8275d35d 420 * @param Fault This parameter can be a combination of the following values:
<> 135:176b8275d35d 421 * @arg @ref LL_HANDLER_FAULT_USG
<> 135:176b8275d35d 422 * @arg @ref LL_HANDLER_FAULT_BUS
<> 135:176b8275d35d 423 * @arg @ref LL_HANDLER_FAULT_MEM
<> 135:176b8275d35d 424 * @retval None
<> 135:176b8275d35d 425 */
<> 135:176b8275d35d 426 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
<> 135:176b8275d35d 427 {
<> 135:176b8275d35d 428 /* Disable the system handler fault */
<> 135:176b8275d35d 429 CLEAR_BIT(SCB->SHCSR, Fault);
<> 135:176b8275d35d 430 }
<> 135:176b8275d35d 431
<> 135:176b8275d35d 432 /**
<> 135:176b8275d35d 433 * @}
<> 135:176b8275d35d 434 */
<> 135:176b8275d35d 435
<> 135:176b8275d35d 436 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
<> 135:176b8275d35d 437 * @{
<> 135:176b8275d35d 438 */
<> 135:176b8275d35d 439
<> 135:176b8275d35d 440 /**
<> 135:176b8275d35d 441 * @brief Get Implementer code
<> 135:176b8275d35d 442 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
<> 135:176b8275d35d 443 * @retval Value should be equal to 0x41 for ARM
<> 135:176b8275d35d 444 */
<> 135:176b8275d35d 445 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
<> 135:176b8275d35d 446 {
<> 135:176b8275d35d 447 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
<> 135:176b8275d35d 448 }
<> 135:176b8275d35d 449
<> 135:176b8275d35d 450 /**
<> 135:176b8275d35d 451 * @brief Get Variant number (The r value in the rnpn product revision identifier)
<> 135:176b8275d35d 452 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
<> 135:176b8275d35d 453 * @retval Value between 0 and 255 (0x0: revision 0)
<> 135:176b8275d35d 454 */
<> 135:176b8275d35d 455 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
<> 135:176b8275d35d 456 {
<> 135:176b8275d35d 457 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
<> 135:176b8275d35d 458 }
<> 135:176b8275d35d 459
<> 135:176b8275d35d 460 /**
<> 135:176b8275d35d 461 * @brief Get Constant number
<> 135:176b8275d35d 462 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
<> 135:176b8275d35d 463 * @retval Value should be equal to 0xF for Cortex-M4 devices
<> 135:176b8275d35d 464 */
<> 135:176b8275d35d 465 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
<> 135:176b8275d35d 466 {
<> 135:176b8275d35d 467 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
<> 135:176b8275d35d 468 }
<> 135:176b8275d35d 469
<> 135:176b8275d35d 470 /**
<> 135:176b8275d35d 471 * @brief Get Part number
<> 135:176b8275d35d 472 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
<> 135:176b8275d35d 473 * @retval Value should be equal to 0xC24 for Cortex-M4
<> 135:176b8275d35d 474 */
<> 135:176b8275d35d 475 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
<> 135:176b8275d35d 476 {
<> 135:176b8275d35d 477 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
<> 135:176b8275d35d 478 }
<> 135:176b8275d35d 479
<> 135:176b8275d35d 480 /**
<> 135:176b8275d35d 481 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
<> 135:176b8275d35d 482 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
<> 135:176b8275d35d 483 * @retval Value between 0 and 255 (0x1: patch 1)
<> 135:176b8275d35d 484 */
<> 135:176b8275d35d 485 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
<> 135:176b8275d35d 486 {
<> 135:176b8275d35d 487 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
<> 135:176b8275d35d 488 }
<> 135:176b8275d35d 489
<> 135:176b8275d35d 490 /**
<> 135:176b8275d35d 491 * @}
<> 135:176b8275d35d 492 */
<> 135:176b8275d35d 493
<> 135:176b8275d35d 494 #if __MPU_PRESENT
<> 135:176b8275d35d 495 /** @defgroup CORTEX_LL_EF_MPU MPU
<> 135:176b8275d35d 496 * @{
<> 135:176b8275d35d 497 */
<> 135:176b8275d35d 498
<> 135:176b8275d35d 499 /**
<> 135:176b8275d35d 500 * @brief Enable MPU with input options
<> 135:176b8275d35d 501 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
<> 135:176b8275d35d 502 * @param Options This parameter can be one of the following values:
<> 135:176b8275d35d 503 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
<> 135:176b8275d35d 504 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
<> 135:176b8275d35d 505 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
<> 135:176b8275d35d 506 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
<> 135:176b8275d35d 507 * @retval None
<> 135:176b8275d35d 508 */
<> 135:176b8275d35d 509 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
<> 135:176b8275d35d 510 {
<> 135:176b8275d35d 511 /* Enable the MPU*/
<> 135:176b8275d35d 512 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
<> 135:176b8275d35d 513 /* Ensure MPU settings take effects */
<> 135:176b8275d35d 514 __DSB();
<> 135:176b8275d35d 515 /* Sequence instruction fetches using update settings */
<> 135:176b8275d35d 516 __ISB();
<> 135:176b8275d35d 517 }
<> 135:176b8275d35d 518
<> 135:176b8275d35d 519 /**
<> 135:176b8275d35d 520 * @brief Disable MPU
<> 135:176b8275d35d 521 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
<> 135:176b8275d35d 522 * @retval None
<> 135:176b8275d35d 523 */
<> 135:176b8275d35d 524 __STATIC_INLINE void LL_MPU_Disable(void)
<> 135:176b8275d35d 525 {
<> 135:176b8275d35d 526 /* Make sure outstanding transfers are done */
<> 135:176b8275d35d 527 __DMB();
<> 135:176b8275d35d 528 /* Disable MPU*/
<> 135:176b8275d35d 529 WRITE_REG(MPU->CTRL, 0U);
<> 135:176b8275d35d 530 }
<> 135:176b8275d35d 531
<> 135:176b8275d35d 532 /**
<> 135:176b8275d35d 533 * @brief Check if MPU is enabled or not
<> 135:176b8275d35d 534 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
<> 135:176b8275d35d 535 * @retval State of bit (1 or 0).
<> 135:176b8275d35d 536 */
<> 135:176b8275d35d 537 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
<> 135:176b8275d35d 538 {
<> 135:176b8275d35d 539 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
<> 135:176b8275d35d 540 }
<> 135:176b8275d35d 541
<> 135:176b8275d35d 542 /**
<> 135:176b8275d35d 543 * @brief Enable a MPU region
<> 135:176b8275d35d 544 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
<> 135:176b8275d35d 545 * @param Region This parameter can be one of the following values:
<> 135:176b8275d35d 546 * @arg @ref LL_MPU_REGION_NUMBER0
<> 135:176b8275d35d 547 * @arg @ref LL_MPU_REGION_NUMBER1
<> 135:176b8275d35d 548 * @arg @ref LL_MPU_REGION_NUMBER2
<> 135:176b8275d35d 549 * @arg @ref LL_MPU_REGION_NUMBER3
<> 135:176b8275d35d 550 * @arg @ref LL_MPU_REGION_NUMBER4
<> 135:176b8275d35d 551 * @arg @ref LL_MPU_REGION_NUMBER5
<> 135:176b8275d35d 552 * @arg @ref LL_MPU_REGION_NUMBER6
<> 135:176b8275d35d 553 * @arg @ref LL_MPU_REGION_NUMBER7
<> 135:176b8275d35d 554 * @retval None
<> 135:176b8275d35d 555 */
<> 135:176b8275d35d 556 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
<> 135:176b8275d35d 557 {
<> 135:176b8275d35d 558 /* Set Region number */
<> 135:176b8275d35d 559 WRITE_REG(MPU->RNR, Region);
<> 135:176b8275d35d 560 /* Enable the MPU region */
<> 135:176b8275d35d 561 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
<> 135:176b8275d35d 562 }
<> 135:176b8275d35d 563
<> 135:176b8275d35d 564 /**
<> 135:176b8275d35d 565 * @brief Configure and enable a region
<> 135:176b8275d35d 566 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
<> 135:176b8275d35d 567 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
<> 135:176b8275d35d 568 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
<> 135:176b8275d35d 569 * MPU_RASR XN LL_MPU_ConfigRegion\n
<> 135:176b8275d35d 570 * MPU_RASR AP LL_MPU_ConfigRegion\n
<> 135:176b8275d35d 571 * MPU_RASR S LL_MPU_ConfigRegion\n
<> 135:176b8275d35d 572 * MPU_RASR C LL_MPU_ConfigRegion\n
<> 135:176b8275d35d 573 * MPU_RASR B LL_MPU_ConfigRegion\n
<> 135:176b8275d35d 574 * MPU_RASR SIZE LL_MPU_ConfigRegion
<> 135:176b8275d35d 575 * @param Region This parameter can be one of the following values:
<> 135:176b8275d35d 576 * @arg @ref LL_MPU_REGION_NUMBER0
<> 135:176b8275d35d 577 * @arg @ref LL_MPU_REGION_NUMBER1
<> 135:176b8275d35d 578 * @arg @ref LL_MPU_REGION_NUMBER2
<> 135:176b8275d35d 579 * @arg @ref LL_MPU_REGION_NUMBER3
<> 135:176b8275d35d 580 * @arg @ref LL_MPU_REGION_NUMBER4
<> 135:176b8275d35d 581 * @arg @ref LL_MPU_REGION_NUMBER5
<> 135:176b8275d35d 582 * @arg @ref LL_MPU_REGION_NUMBER6
<> 135:176b8275d35d 583 * @arg @ref LL_MPU_REGION_NUMBER7
<> 135:176b8275d35d 584 * @param Address Value of region base address
<> 135:176b8275d35d 585 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
<> 135:176b8275d35d 586 * @param Attributes This parameter can be a combination of the following values:
<> 135:176b8275d35d 587 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
<> 135:176b8275d35d 588 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
<> 135:176b8275d35d 589 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
<> 135:176b8275d35d 590 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
<> 135:176b8275d35d 591 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
<> 135:176b8275d35d 592 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
<> 135:176b8275d35d 593 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
<> 135:176b8275d35d 594 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
<> 135:176b8275d35d 595 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
<> 135:176b8275d35d 596 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
<> 135:176b8275d35d 597 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
<> 135:176b8275d35d 598 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
<> 135:176b8275d35d 599 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
<> 135:176b8275d35d 600 * @retval None
<> 135:176b8275d35d 601 */
<> 135:176b8275d35d 602 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
<> 135:176b8275d35d 603 {
<> 135:176b8275d35d 604 /* Set Region number */
<> 135:176b8275d35d 605 WRITE_REG(MPU->RNR, Region);
<> 135:176b8275d35d 606 /* Set base address */
<> 135:176b8275d35d 607 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
<> 135:176b8275d35d 608 /* Configure MPU */
<> 135:176b8275d35d 609 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
<> 135:176b8275d35d 610 }
<> 135:176b8275d35d 611
<> 135:176b8275d35d 612 /**
<> 135:176b8275d35d 613 * @brief Disable a region
<> 135:176b8275d35d 614 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
<> 135:176b8275d35d 615 * MPU_RASR ENABLE LL_MPU_DisableRegion
<> 135:176b8275d35d 616 * @param Region This parameter can be one of the following values:
<> 135:176b8275d35d 617 * @arg @ref LL_MPU_REGION_NUMBER0
<> 135:176b8275d35d 618 * @arg @ref LL_MPU_REGION_NUMBER1
<> 135:176b8275d35d 619 * @arg @ref LL_MPU_REGION_NUMBER2
<> 135:176b8275d35d 620 * @arg @ref LL_MPU_REGION_NUMBER3
<> 135:176b8275d35d 621 * @arg @ref LL_MPU_REGION_NUMBER4
<> 135:176b8275d35d 622 * @arg @ref LL_MPU_REGION_NUMBER5
<> 135:176b8275d35d 623 * @arg @ref LL_MPU_REGION_NUMBER6
<> 135:176b8275d35d 624 * @arg @ref LL_MPU_REGION_NUMBER7
<> 135:176b8275d35d 625 * @retval None
<> 135:176b8275d35d 626 */
<> 135:176b8275d35d 627 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
<> 135:176b8275d35d 628 {
<> 135:176b8275d35d 629 /* Set Region number */
<> 135:176b8275d35d 630 WRITE_REG(MPU->RNR, Region);
<> 135:176b8275d35d 631 /* Disable the MPU region */
<> 135:176b8275d35d 632 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
<> 135:176b8275d35d 633 }
<> 135:176b8275d35d 634
<> 135:176b8275d35d 635 /**
<> 135:176b8275d35d 636 * @}
<> 135:176b8275d35d 637 */
<> 135:176b8275d35d 638
<> 135:176b8275d35d 639 #endif /* __MPU_PRESENT */
<> 135:176b8275d35d 640 /**
<> 135:176b8275d35d 641 * @}
<> 135:176b8275d35d 642 */
<> 135:176b8275d35d 643
<> 135:176b8275d35d 644 /**
<> 135:176b8275d35d 645 * @}
<> 135:176b8275d35d 646 */
<> 135:176b8275d35d 647
<> 135:176b8275d35d 648 /**
<> 135:176b8275d35d 649 * @}
<> 135:176b8275d35d 650 */
<> 135:176b8275d35d 651
<> 135:176b8275d35d 652 #ifdef __cplusplus
<> 135:176b8275d35d 653 }
<> 135:176b8275d35d 654 #endif
<> 135:176b8275d35d 655
<> 135:176b8275d35d 656 #endif /* __STM32F3xx_LL_CORTEX_H */
<> 135:176b8275d35d 657
<> 135:176b8275d35d 658 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/