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TARGET_NUCLEO_F030R8/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_spi.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:30:20 2017 +0100
Revision:: 143:86740a56073b
Parent:: 134:ad3be0349dc5
Child:: 160:5571c4ff569f

Release 143 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	134:ad3be0349dc5	1	/**
<>	134:ad3be0349dc5	2	******************************************************************************
<>	134:ad3be0349dc5	3	* @file stm32f0xx_ll_spi.h
<>	134:ad3be0349dc5	4	* @author MCD Application Team
<>	134:ad3be0349dc5	5	* @version V1.4.0
<>	134:ad3be0349dc5	6	* @date 27-May-2016
<>	134:ad3be0349dc5	7	* @brief Header file of SPI LL module.
<>	134:ad3be0349dc5	8	******************************************************************************
<>	134:ad3be0349dc5	9	* @attention
<>	134:ad3be0349dc5	10	*
<>	134:ad3be0349dc5	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	134:ad3be0349dc5	12	*
<>	134:ad3be0349dc5	13	* Redistribution and use in source and binary forms, with or without modification,
<>	134:ad3be0349dc5	14	* are permitted provided that the following conditions are met:
<>	134:ad3be0349dc5	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	134:ad3be0349dc5	16	* this list of conditions and the following disclaimer.
<>	134:ad3be0349dc5	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	134:ad3be0349dc5	18	* this list of conditions and the following disclaimer in the documentation
<>	134:ad3be0349dc5	19	* and/or other materials provided with the distribution.
<>	134:ad3be0349dc5	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	134:ad3be0349dc5	21	* may be used to endorse or promote products derived from this software
<>	134:ad3be0349dc5	22	* without specific prior written permission.
<>	134:ad3be0349dc5	23	*
<>	134:ad3be0349dc5	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	134:ad3be0349dc5	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	134:ad3be0349dc5	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	134:ad3be0349dc5	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	134:ad3be0349dc5	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	134:ad3be0349dc5	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	134:ad3be0349dc5	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	134:ad3be0349dc5	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	134:ad3be0349dc5	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	134:ad3be0349dc5	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	134:ad3be0349dc5	34	*
<>	134:ad3be0349dc5	35	******************************************************************************
<>	134:ad3be0349dc5	36	*/
<>	134:ad3be0349dc5	37
<>	134:ad3be0349dc5	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	134:ad3be0349dc5	39	#ifndef __STM32F0xx_LL_SPI_H
<>	134:ad3be0349dc5	40	#define __STM32F0xx_LL_SPI_H
<>	134:ad3be0349dc5	41
<>	134:ad3be0349dc5	42	#ifdef __cplusplus
<>	134:ad3be0349dc5	43	extern "C" {
<>	134:ad3be0349dc5	44	#endif
<>	134:ad3be0349dc5	45
<>	134:ad3be0349dc5	46	/* Includes ------------------------------------------------------------------*/
<>	134:ad3be0349dc5	47	#include "stm32f0xx.h"
<>	134:ad3be0349dc5	48
<>	134:ad3be0349dc5	49	/** @addtogroup STM32F0xx_LL_Driver
<>	134:ad3be0349dc5	50	* @{
<>	134:ad3be0349dc5	51	*/
<>	134:ad3be0349dc5	52
<>	134:ad3be0349dc5	53	#if defined (SPI1) \|\| defined (SPI2)
<>	134:ad3be0349dc5	54
<>	134:ad3be0349dc5	55	/** @defgroup SPI_LL SPI
<>	134:ad3be0349dc5	56	* @{
<>	134:ad3be0349dc5	57	*/
<>	134:ad3be0349dc5	58
<>	134:ad3be0349dc5	59	/* Private types -------------------------------------------------------------*/
<>	134:ad3be0349dc5	60	/* Private variables ---------------------------------------------------------*/
<>	134:ad3be0349dc5	61	/* Private macros ------------------------------------------------------------*/
<>	134:ad3be0349dc5	62
<>	134:ad3be0349dc5	63	/* Exported types ------------------------------------------------------------*/
<>	134:ad3be0349dc5	64	#if defined(USE_FULL_LL_DRIVER)
<>	134:ad3be0349dc5	65	/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
<>	134:ad3be0349dc5	66	* @{
<>	134:ad3be0349dc5	67	*/
<>	134:ad3be0349dc5	68
<>	134:ad3be0349dc5	69	/**
<>	134:ad3be0349dc5	70	* @brief SPI Init structures definition
<>	134:ad3be0349dc5	71	*/
<>	134:ad3be0349dc5	72	typedef struct
<>	134:ad3be0349dc5	73	{
<>	134:ad3be0349dc5	74	uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
<>	134:ad3be0349dc5	75	This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
<>	134:ad3be0349dc5	76
<>	134:ad3be0349dc5	77	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
<>	134:ad3be0349dc5	78
<>	134:ad3be0349dc5	79	uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
<>	134:ad3be0349dc5	80	This parameter can be a value of @ref SPI_LL_EC_MODE.
<>	134:ad3be0349dc5	81
<>	134:ad3be0349dc5	82	This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
<>	134:ad3be0349dc5	83
<>	134:ad3be0349dc5	84	uint32_t DataWidth; /*!< Specifies the SPI data width.
<>	134:ad3be0349dc5	85	This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
<>	134:ad3be0349dc5	86
<>	134:ad3be0349dc5	87	This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
<>	134:ad3be0349dc5	88
<>	134:ad3be0349dc5	89	uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
<>	134:ad3be0349dc5	90	This parameter can be a value of @ref SPI_LL_EC_POLARITY.
<>	134:ad3be0349dc5	91
<>	134:ad3be0349dc5	92	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
<>	134:ad3be0349dc5	93
<>	134:ad3be0349dc5	94	uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
<>	134:ad3be0349dc5	95	This parameter can be a value of @ref SPI_LL_EC_PHASE.
<>	134:ad3be0349dc5	96
<>	134:ad3be0349dc5	97	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
<>	134:ad3be0349dc5	98
<>	134:ad3be0349dc5	99	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
<>	134:ad3be0349dc5	100	This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
<>	134:ad3be0349dc5	101
<>	134:ad3be0349dc5	102	This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
<>	134:ad3be0349dc5	103
<>	134:ad3be0349dc5	104	uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
<>	134:ad3be0349dc5	105	This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
<>	134:ad3be0349dc5	106	@note The communication clock is derived from the master clock. The slave clock does not need to be set.
<>	134:ad3be0349dc5	107
<>	134:ad3be0349dc5	108	This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
<>	134:ad3be0349dc5	109
<>	134:ad3be0349dc5	110	uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
<>	134:ad3be0349dc5	111	This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
<>	134:ad3be0349dc5	112
<>	134:ad3be0349dc5	113	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
<>	134:ad3be0349dc5	114
<>	134:ad3be0349dc5	115	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
<>	134:ad3be0349dc5	116	This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
<>	134:ad3be0349dc5	117
<>	134:ad3be0349dc5	118	This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
<>	134:ad3be0349dc5	119
<>	134:ad3be0349dc5	120	uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
<>	134:ad3be0349dc5	121	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
<>	134:ad3be0349dc5	122
<>	134:ad3be0349dc5	123	This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
<>	134:ad3be0349dc5	124
<>	134:ad3be0349dc5	125	} LL_SPI_InitTypeDef;
<>	134:ad3be0349dc5	126
<>	134:ad3be0349dc5	127	/**
<>	134:ad3be0349dc5	128	* @}
<>	134:ad3be0349dc5	129	*/
<>	134:ad3be0349dc5	130	#endif /* USE_FULL_LL_DRIVER */
<>	134:ad3be0349dc5	131
<>	134:ad3be0349dc5	132	/* Exported constants --------------------------------------------------------*/
<>	134:ad3be0349dc5	133	/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
<>	134:ad3be0349dc5	134	* @{
<>	134:ad3be0349dc5	135	*/
<>	134:ad3be0349dc5	136
<>	134:ad3be0349dc5	137	/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
<>	134:ad3be0349dc5	138	* @brief Flags defines which can be used with LL_SPI_ReadReg function
<>	134:ad3be0349dc5	139	* @{
<>	134:ad3be0349dc5	140	*/
<>	134:ad3be0349dc5	141	#define LL_SPI_SR_RXNE SPI_SR_RXNE /!< Rx buffer not empty flag /
<>	134:ad3be0349dc5	142	#define LL_SPI_SR_TXE SPI_SR_TXE /!< Tx buffer empty flag /
<>	134:ad3be0349dc5	143	#define LL_SPI_SR_BSY SPI_SR_BSY /!< Busy flag /
<>	134:ad3be0349dc5	144	#define LL_SPI_SR_UDR SPI_SR_UDR /!< Underrun flag /
<>	134:ad3be0349dc5	145	#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /!< CRC error flag /
<>	134:ad3be0349dc5	146	#define LL_SPI_SR_MODF SPI_SR_MODF /!< Mode fault flag /
<>	134:ad3be0349dc5	147	#define LL_SPI_SR_OVR SPI_SR_OVR /!< Overrun flag /
<>	134:ad3be0349dc5	148	#define LL_SPI_SR_FRE SPI_SR_FRE /!< TI mode frame format error flag /
<>	134:ad3be0349dc5	149	/**
<>	134:ad3be0349dc5	150	* @}
<>	134:ad3be0349dc5	151	*/
<>	134:ad3be0349dc5	152
<>	134:ad3be0349dc5	153	/** @defgroup SPI_LL_EC_IT IT Defines
<>	134:ad3be0349dc5	154	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
<>	134:ad3be0349dc5	155	* @{
<>	134:ad3be0349dc5	156	*/
<>	134:ad3be0349dc5	157	#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
<>	134:ad3be0349dc5	158	#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
<>	134:ad3be0349dc5	159	#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /!< Error interrupt enable /
<>	134:ad3be0349dc5	160	/**
<>	134:ad3be0349dc5	161	* @}
<>	134:ad3be0349dc5	162	*/
<>	134:ad3be0349dc5	163
<>	134:ad3be0349dc5	164	/** @defgroup SPI_LL_EC_MODE Operation Mode
<>	134:ad3be0349dc5	165	* @{
<>	134:ad3be0349dc5	166	*/
<>	134:ad3be0349dc5	167	#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI) /!< Master configuration /
<>	134:ad3be0349dc5	168	#define LL_SPI_MODE_SLAVE ((uint32_t)0x00000000U) /!< Slave configuration /
<>	134:ad3be0349dc5	169	/**
<>	134:ad3be0349dc5	170	* @}
<>	134:ad3be0349dc5	171	*/
<>	134:ad3be0349dc5	172
<>	134:ad3be0349dc5	173	/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
<>	134:ad3be0349dc5	174	* @{
<>	134:ad3be0349dc5	175	*/
<>	134:ad3be0349dc5	176	#define LL_SPI_PROTOCOL_MOTOROLA ((uint32_t)0x00000000U) /!< Motorola mode. Used as default value /
<>	134:ad3be0349dc5	177	#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /!< TI mode /
<>	134:ad3be0349dc5	178	/**
<>	134:ad3be0349dc5	179	* @}
<>	134:ad3be0349dc5	180	*/
<>	134:ad3be0349dc5	181
<>	134:ad3be0349dc5	182	/** @defgroup SPI_LL_EC_PHASE Clock Phase
<>	134:ad3be0349dc5	183	* @{
<>	134:ad3be0349dc5	184	*/
<>	134:ad3be0349dc5	185	#define LL_SPI_PHASE_1EDGE ((uint32_t)0x00000000U) /!< First clock transition is the first data capture edge /
<>	134:ad3be0349dc5	186	#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /!< Second clock transition is the first data capture edge /
<>	134:ad3be0349dc5	187	/**
<>	134:ad3be0349dc5	188	* @}
<>	134:ad3be0349dc5	189	*/
<>	134:ad3be0349dc5	190
<>	134:ad3be0349dc5	191	/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
<>	134:ad3be0349dc5	192	* @{
<>	134:ad3be0349dc5	193	*/
<>	134:ad3be0349dc5	194	#define LL_SPI_POLARITY_LOW ((uint32_t)0x00000000U) /!< Clock to 0 when idle /
<>	134:ad3be0349dc5	195	#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /!< Clock to 1 when idle /
<>	134:ad3be0349dc5	196	/**
<>	134:ad3be0349dc5	197	* @}
<>	134:ad3be0349dc5	198	*/
<>	134:ad3be0349dc5	199
<>	134:ad3be0349dc5	200	/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
<>	134:ad3be0349dc5	201	* @{
<>	134:ad3be0349dc5	202	*/
<>	134:ad3be0349dc5	203	#define LL_SPI_BAUDRATEPRESCALER_DIV2 ((uint32_t)0x00000000U) /!< BaudRate control equal to fPCLK/2 /
<>	134:ad3be0349dc5	204	#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/4 /
<>	134:ad3be0349dc5	205	#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/8 /
<>	134:ad3be0349dc5	206	#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/16 /
<>	134:ad3be0349dc5	207	#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /!< BaudRate control equal to fPCLK/32 /
<>	134:ad3be0349dc5	208	#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/64 /
<>	134:ad3be0349dc5	209	#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 \| SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/128 /
<>	134:ad3be0349dc5	210	#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 \| SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/256 /
<>	134:ad3be0349dc5	211	/**
<>	134:ad3be0349dc5	212	* @}
<>	134:ad3be0349dc5	213	*/
<>	134:ad3be0349dc5	214
<>	134:ad3be0349dc5	215	/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
<>	134:ad3be0349dc5	216	* @{
<>	134:ad3be0349dc5	217	*/
<>	134:ad3be0349dc5	218	#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /!< Data is transmitted/received with the LSB first /
<>	134:ad3be0349dc5	219	#define LL_SPI_MSB_FIRST ((uint32_t)0x00000000U) /!< Data is transmitted/received with the MSB first /
<>	134:ad3be0349dc5	220	/**
<>	134:ad3be0349dc5	221	* @}
<>	134:ad3be0349dc5	222	*/
<>	134:ad3be0349dc5	223
<>	134:ad3be0349dc5	224	/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
<>	134:ad3be0349dc5	225	* @{
<>	134:ad3be0349dc5	226	*/
<>	134:ad3be0349dc5	227	#define LL_SPI_FULL_DUPLEX ((uint32_t)0x00000000U) /!< Full-Duplex mode. Rx and Tx transfer on 2 lines /
<>	134:ad3be0349dc5	228	#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /!< Simplex Rx mode. Rx transfer only on 1 line /
<>	134:ad3be0349dc5	229	#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /!< Half-Duplex Rx mode. Rx transfer on 1 line /
<>	134:ad3be0349dc5	230	#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE) /!< Half-Duplex Tx mode. Tx transfer on 1 line /
<>	134:ad3be0349dc5	231	/**
<>	134:ad3be0349dc5	232	* @}
<>	134:ad3be0349dc5	233	*/
<>	134:ad3be0349dc5	234
<>	134:ad3be0349dc5	235	/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
<>	134:ad3be0349dc5	236	* @{
<>	134:ad3be0349dc5	237	*/
<>	134:ad3be0349dc5	238	#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /!< NSS managed internally. NSS pin not used and free /
<>	134:ad3be0349dc5	239	#define LL_SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U) /!< NSS pin used in Input. Only used in Master mode /
<>	134:ad3be0349dc5	240	#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /!< NSS pin used in Output. Only used in Slave mode as chip select /
<>	134:ad3be0349dc5	241	/**
<>	134:ad3be0349dc5	242	* @}
<>	134:ad3be0349dc5	243	*/
<>	134:ad3be0349dc5	244
<>	134:ad3be0349dc5	245	/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
<>	134:ad3be0349dc5	246	* @{
<>	134:ad3be0349dc5	247	*/
<>	134:ad3be0349dc5	248	#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 4 bits /
<>	134:ad3be0349dc5	249	#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /!< Data length for SPI transfer: 5 bits /
<>	134:ad3be0349dc5	250	#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 6 bits /
<>	134:ad3be0349dc5	251	#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 7 bits /
<>	134:ad3be0349dc5	252	#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 8 bits /
<>	134:ad3be0349dc5	253	#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /!< Data length for SPI transfer: 9 bits /
<>	134:ad3be0349dc5	254	#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 10 bits /
<>	134:ad3be0349dc5	255	#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 11 bits /
<>	134:ad3be0349dc5	256	#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 12 bits /
<>	134:ad3be0349dc5	257	#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2) /!< Data length for SPI transfer: 13 bits /
<>	134:ad3be0349dc5	258	#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 14 bits /
<>	134:ad3be0349dc5	259	#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 15 bits /
<>	134:ad3be0349dc5	260	#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 16 bits /
<>	134:ad3be0349dc5	261	/**
<>	134:ad3be0349dc5	262	* @}
<>	134:ad3be0349dc5	263	*/
<>	134:ad3be0349dc5	264	#if defined(USE_FULL_LL_DRIVER)
<>	134:ad3be0349dc5	265
<>	134:ad3be0349dc5	266	/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
<>	134:ad3be0349dc5	267	* @{
<>	134:ad3be0349dc5	268	*/
<>	134:ad3be0349dc5	269	#define LL_SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U) /!< CRC calculation disabled /
<>	134:ad3be0349dc5	270	#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /!< CRC calculation enabled /
<>	134:ad3be0349dc5	271	/**
<>	134:ad3be0349dc5	272	* @}
<>	134:ad3be0349dc5	273	*/
<>	134:ad3be0349dc5	274	#endif /* USE_FULL_LL_DRIVER */
<>	134:ad3be0349dc5	275
<>	134:ad3be0349dc5	276	/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
<>	134:ad3be0349dc5	277	* @{
<>	134:ad3be0349dc5	278	*/
<>	134:ad3be0349dc5	279	#define LL_SPI_CRC_8BIT ((uint32_t)0x00000000U) /!< 8-bit CRC length /
<>	134:ad3be0349dc5	280	#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /!< 16-bit CRC length /
<>	134:ad3be0349dc5	281	/**
<>	134:ad3be0349dc5	282	* @}
<>	134:ad3be0349dc5	283	*/
<>	134:ad3be0349dc5	284
<>	134:ad3be0349dc5	285	/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
<>	134:ad3be0349dc5	286	* @{
<>	134:ad3be0349dc5	287	*/
<>	134:ad3be0349dc5	288	#define LL_SPI_RX_FIFO_TH_HALF ((uint32_t)0x00000000U) /!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) /
<>	134:ad3be0349dc5	289	#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) /
<>	134:ad3be0349dc5	290	/**
<>	134:ad3be0349dc5	291	* @}
<>	134:ad3be0349dc5	292	*/
<>	134:ad3be0349dc5	293
<>	134:ad3be0349dc5	294	/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
<>	134:ad3be0349dc5	295	* @{
<>	134:ad3be0349dc5	296	*/
<>	134:ad3be0349dc5	297	#define LL_SPI_RX_FIFO_EMPTY ((uint32_t)0x00000000U) /!< FIFO reception empty /
<>	134:ad3be0349dc5	298	#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /!< FIFO reception 1/4 /
<>	134:ad3be0349dc5	299	#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /!< FIFO reception 1/2 /
<>	134:ad3be0349dc5	300	#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 \| SPI_SR_FRLVL_0) /!< FIFO reception full /
<>	134:ad3be0349dc5	301	/**
<>	134:ad3be0349dc5	302	* @}
<>	134:ad3be0349dc5	303	*/
<>	134:ad3be0349dc5	304
<>	134:ad3be0349dc5	305	/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
<>	134:ad3be0349dc5	306	* @{
<>	134:ad3be0349dc5	307	*/
<>	134:ad3be0349dc5	308	#define LL_SPI_TX_FIFO_EMPTY ((uint32_t)0x00000000U) /!< FIFO transmission empty /
<>	134:ad3be0349dc5	309	#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /!< FIFO transmission 1/4 /
<>	134:ad3be0349dc5	310	#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /!< FIFO transmission 1/2 /
<>	134:ad3be0349dc5	311	#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 \| SPI_SR_FTLVL_0) /!< FIFO transmission full /
<>	134:ad3be0349dc5	312	/**
<>	134:ad3be0349dc5	313	* @}
<>	134:ad3be0349dc5	314	*/
<>	134:ad3be0349dc5	315
<>	134:ad3be0349dc5	316	/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
<>	134:ad3be0349dc5	317	* @{
<>	134:ad3be0349dc5	318	*/
<>	134:ad3be0349dc5	319	#define LL_SPI_DMA_PARITY_EVEN ((uint32_t)0x00000000U) /!< Select DMA parity Even /
<>	134:ad3be0349dc5	320	#define LL_SPI_DMA_PARITY_ODD ((uint32_t)0x00000001U) /!< Select DMA parity Odd /
<>	134:ad3be0349dc5	321
<>	134:ad3be0349dc5	322	/**
<>	134:ad3be0349dc5	323	* @}
<>	134:ad3be0349dc5	324	*/
<>	134:ad3be0349dc5	325
<>	134:ad3be0349dc5	326	/**
<>	134:ad3be0349dc5	327	* @}
<>	134:ad3be0349dc5	328	*/
<>	134:ad3be0349dc5	329
<>	134:ad3be0349dc5	330	/* Exported macro ------------------------------------------------------------*/
<>	134:ad3be0349dc5	331	/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
<>	134:ad3be0349dc5	332	* @{
<>	134:ad3be0349dc5	333	*/
<>	134:ad3be0349dc5	334
<>	134:ad3be0349dc5	335	/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
<>	134:ad3be0349dc5	336	* @{
<>	134:ad3be0349dc5	337	*/
<>	134:ad3be0349dc5	338
<>	134:ad3be0349dc5	339	/**
<>	134:ad3be0349dc5	340	* @brief Write a value in SPI register
<>	134:ad3be0349dc5	341	* @param __INSTANCE__ SPI Instance
<>	134:ad3be0349dc5	342	* @param __REG__ Register to be written
<>	134:ad3be0349dc5	343	* @param __VALUE__ Value to be written in the register
<>	134:ad3be0349dc5	344	* @retval None
<>	134:ad3be0349dc5	345	*/
<>	134:ad3be0349dc5	346	#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	134:ad3be0349dc5	347
<>	134:ad3be0349dc5	348	/**
<>	134:ad3be0349dc5	349	* @brief Read a value in SPI register
<>	134:ad3be0349dc5	350	* @param __INSTANCE__ SPI Instance
<>	134:ad3be0349dc5	351	* @param __REG__ Register to be read
<>	134:ad3be0349dc5	352	* @retval Register value
<>	134:ad3be0349dc5	353	*/
<>	134:ad3be0349dc5	354	#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	134:ad3be0349dc5	355	/**
<>	134:ad3be0349dc5	356	* @}
<>	134:ad3be0349dc5	357	*/
<>	134:ad3be0349dc5	358
<>	134:ad3be0349dc5	359	/**
<>	134:ad3be0349dc5	360	* @}
<>	134:ad3be0349dc5	361	*/
<>	134:ad3be0349dc5	362
<>	134:ad3be0349dc5	363	/* Exported functions --------------------------------------------------------*/
<>	134:ad3be0349dc5	364	/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
<>	134:ad3be0349dc5	365	* @{
<>	134:ad3be0349dc5	366	*/
<>	134:ad3be0349dc5	367
<>	134:ad3be0349dc5	368	/** @defgroup SPI_LL_EF_Configuration Configuration
<>	134:ad3be0349dc5	369	* @{
<>	134:ad3be0349dc5	370	*/
<>	134:ad3be0349dc5	371
<>	134:ad3be0349dc5	372	/**
<>	134:ad3be0349dc5	373	* @brief Enable SPI peripheral
<>	134:ad3be0349dc5	374	* @rmtoll CR1 SPE LL_SPI_Enable
<>	134:ad3be0349dc5	375	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	376	* @retval None
<>	134:ad3be0349dc5	377	*/
<>	134:ad3be0349dc5	378	__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	379	{
<>	134:ad3be0349dc5	380	SET_BIT(SPIx->CR1, SPI_CR1_SPE);
<>	134:ad3be0349dc5	381	}
<>	134:ad3be0349dc5	382
<>	134:ad3be0349dc5	383	/**
<>	134:ad3be0349dc5	384	* @brief Disable SPI peripheral
<>	134:ad3be0349dc5	385	* @note When disabling the SPI, follow the procedure described in the Reference Manual.
<>	134:ad3be0349dc5	386	* @rmtoll CR1 SPE LL_SPI_Disable
<>	134:ad3be0349dc5	387	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	388	* @retval None
<>	134:ad3be0349dc5	389	*/
<>	134:ad3be0349dc5	390	__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	391	{
<>	134:ad3be0349dc5	392	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
<>	134:ad3be0349dc5	393	}
<>	134:ad3be0349dc5	394
<>	134:ad3be0349dc5	395	/**
<>	134:ad3be0349dc5	396	* @brief Check if SPI peripheral is enabled
<>	134:ad3be0349dc5	397	* @rmtoll CR1 SPE LL_SPI_IsEnabled
<>	134:ad3be0349dc5	398	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	399	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	400	*/
<>	134:ad3be0349dc5	401	__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	402	{
<>	134:ad3be0349dc5	403	return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
<>	134:ad3be0349dc5	404	}
<>	134:ad3be0349dc5	405
<>	134:ad3be0349dc5	406	/**
<>	134:ad3be0349dc5	407	* @brief Set SPI operation mode to Master or Slave
<>	134:ad3be0349dc5	408	* @note This bit should not be changed when communication is ongoing.
<>	134:ad3be0349dc5	409	* @rmtoll CR1 MSTR LL_SPI_SetMode\n
<>	134:ad3be0349dc5	410	* CR1 SSI LL_SPI_SetMode
<>	134:ad3be0349dc5	411	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	412	* @param Mode This parameter can be one of the following values:
<>	134:ad3be0349dc5	413	* @arg @ref LL_SPI_MODE_MASTER
<>	134:ad3be0349dc5	414	* @arg @ref LL_SPI_MODE_SLAVE
<>	134:ad3be0349dc5	415	* @retval None
<>	134:ad3be0349dc5	416	*/
<>	134:ad3be0349dc5	417	__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
<>	134:ad3be0349dc5	418	{
<>	134:ad3be0349dc5	419	MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI, Mode);
<>	134:ad3be0349dc5	420	}
<>	134:ad3be0349dc5	421
<>	134:ad3be0349dc5	422	/**
<>	134:ad3be0349dc5	423	* @brief Get SPI operation mode (Master or Slave)
<>	134:ad3be0349dc5	424	* @rmtoll CR1 MSTR LL_SPI_GetMode\n
<>	134:ad3be0349dc5	425	* CR1 SSI LL_SPI_GetMode
<>	134:ad3be0349dc5	426	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	427	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	428	* @arg @ref LL_SPI_MODE_MASTER
<>	134:ad3be0349dc5	429	* @arg @ref LL_SPI_MODE_SLAVE
<>	134:ad3be0349dc5	430	*/
<>	134:ad3be0349dc5	431	__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	432	{
<>	134:ad3be0349dc5	433	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI));
<>	134:ad3be0349dc5	434	}
<>	134:ad3be0349dc5	435
<>	134:ad3be0349dc5	436	/**
<>	134:ad3be0349dc5	437	* @brief Set serial protocol used
<>	134:ad3be0349dc5	438	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<>	134:ad3be0349dc5	439	* @rmtoll CR2 FRF LL_SPI_SetStandard
<>	134:ad3be0349dc5	440	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	441	* @param Standard This parameter can be one of the following values:
<>	134:ad3be0349dc5	442	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
<>	134:ad3be0349dc5	443	* @arg @ref LL_SPI_PROTOCOL_TI
<>	134:ad3be0349dc5	444	* @retval None
<>	134:ad3be0349dc5	445	*/
<>	134:ad3be0349dc5	446	__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
<>	134:ad3be0349dc5	447	{
<>	134:ad3be0349dc5	448	MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
<>	134:ad3be0349dc5	449	}
<>	134:ad3be0349dc5	450
<>	134:ad3be0349dc5	451	/**
<>	134:ad3be0349dc5	452	* @brief Get serial protocol used
<>	134:ad3be0349dc5	453	* @rmtoll CR2 FRF LL_SPI_GetStandard
<>	134:ad3be0349dc5	454	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	455	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	456	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
<>	134:ad3be0349dc5	457	* @arg @ref LL_SPI_PROTOCOL_TI
<>	134:ad3be0349dc5	458	*/
<>	134:ad3be0349dc5	459	__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	460	{
<>	134:ad3be0349dc5	461	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
<>	134:ad3be0349dc5	462	}
<>	134:ad3be0349dc5	463
<>	134:ad3be0349dc5	464	/**
<>	134:ad3be0349dc5	465	* @brief Set clock phase
<>	134:ad3be0349dc5	466	* @note This bit should not be changed when communication is ongoing.
<>	134:ad3be0349dc5	467	* This bit is not used in SPI TI mode.
<>	134:ad3be0349dc5	468	* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
<>	134:ad3be0349dc5	469	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	470	* @param ClockPhase This parameter can be one of the following values:
<>	134:ad3be0349dc5	471	* @arg @ref LL_SPI_PHASE_1EDGE
<>	134:ad3be0349dc5	472	* @arg @ref LL_SPI_PHASE_2EDGE
<>	134:ad3be0349dc5	473	* @retval None
<>	134:ad3be0349dc5	474	*/
<>	134:ad3be0349dc5	475	__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
<>	134:ad3be0349dc5	476	{
<>	134:ad3be0349dc5	477	MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
<>	134:ad3be0349dc5	478	}
<>	134:ad3be0349dc5	479
<>	134:ad3be0349dc5	480	/**
<>	134:ad3be0349dc5	481	* @brief Get clock phase
<>	134:ad3be0349dc5	482	* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
<>	134:ad3be0349dc5	483	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	484	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	485	* @arg @ref LL_SPI_PHASE_1EDGE
<>	134:ad3be0349dc5	486	* @arg @ref LL_SPI_PHASE_2EDGE
<>	134:ad3be0349dc5	487	*/
<>	134:ad3be0349dc5	488	__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	489	{
<>	134:ad3be0349dc5	490	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
<>	134:ad3be0349dc5	491	}
<>	134:ad3be0349dc5	492
<>	134:ad3be0349dc5	493	/**
<>	134:ad3be0349dc5	494	* @brief Set clock polarity
<>	134:ad3be0349dc5	495	* @note This bit should not be changed when communication is ongoing.
<>	134:ad3be0349dc5	496	* This bit is not used in SPI TI mode.
<>	134:ad3be0349dc5	497	* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
<>	134:ad3be0349dc5	498	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	499	* @param ClockPolarity This parameter can be one of the following values:
<>	134:ad3be0349dc5	500	* @arg @ref LL_SPI_POLARITY_LOW
<>	134:ad3be0349dc5	501	* @arg @ref LL_SPI_POLARITY_HIGH
<>	134:ad3be0349dc5	502	* @retval None
<>	134:ad3be0349dc5	503	*/
<>	134:ad3be0349dc5	504	__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
<>	134:ad3be0349dc5	505	{
<>	134:ad3be0349dc5	506	MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
<>	134:ad3be0349dc5	507	}
<>	134:ad3be0349dc5	508
<>	134:ad3be0349dc5	509	/**
<>	134:ad3be0349dc5	510	* @brief Get clock polarity
<>	134:ad3be0349dc5	511	* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
<>	134:ad3be0349dc5	512	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	513	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	514	* @arg @ref LL_SPI_POLARITY_LOW
<>	134:ad3be0349dc5	515	* @arg @ref LL_SPI_POLARITY_HIGH
<>	134:ad3be0349dc5	516	*/
<>	134:ad3be0349dc5	517	__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	518	{
<>	134:ad3be0349dc5	519	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
<>	134:ad3be0349dc5	520	}
<>	134:ad3be0349dc5	521
<>	134:ad3be0349dc5	522	/**
<>	134:ad3be0349dc5	523	* @brief Set baud rate prescaler
<>	134:ad3be0349dc5	524	* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
<>	134:ad3be0349dc5	525	* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
<>	134:ad3be0349dc5	526	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	527	* @param BaudRate This parameter can be one of the following values:
<>	134:ad3be0349dc5	528	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
<>	134:ad3be0349dc5	529	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
<>	134:ad3be0349dc5	530	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
<>	134:ad3be0349dc5	531	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
<>	134:ad3be0349dc5	532	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
<>	134:ad3be0349dc5	533	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
<>	134:ad3be0349dc5	534	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
<>	134:ad3be0349dc5	535	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
<>	134:ad3be0349dc5	536	* @retval None
<>	134:ad3be0349dc5	537	*/
<>	134:ad3be0349dc5	538	__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
<>	134:ad3be0349dc5	539	{
<>	134:ad3be0349dc5	540	MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
<>	134:ad3be0349dc5	541	}
<>	134:ad3be0349dc5	542
<>	134:ad3be0349dc5	543	/**
<>	134:ad3be0349dc5	544	* @brief Get baud rate prescaler
<>	134:ad3be0349dc5	545	* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
<>	134:ad3be0349dc5	546	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	547	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	548	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
<>	134:ad3be0349dc5	549	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
<>	134:ad3be0349dc5	550	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
<>	134:ad3be0349dc5	551	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
<>	134:ad3be0349dc5	552	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
<>	134:ad3be0349dc5	553	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
<>	134:ad3be0349dc5	554	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
<>	134:ad3be0349dc5	555	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
<>	134:ad3be0349dc5	556	*/
<>	134:ad3be0349dc5	557	__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	558	{
<>	134:ad3be0349dc5	559	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
<>	134:ad3be0349dc5	560	}
<>	134:ad3be0349dc5	561
<>	134:ad3be0349dc5	562	/**
<>	134:ad3be0349dc5	563	* @brief Set transfer bit order
<>	134:ad3be0349dc5	564	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
<>	134:ad3be0349dc5	565	* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
<>	134:ad3be0349dc5	566	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	567	* @param BitOrder This parameter can be one of the following values:
<>	134:ad3be0349dc5	568	* @arg @ref LL_SPI_LSB_FIRST
<>	134:ad3be0349dc5	569	* @arg @ref LL_SPI_MSB_FIRST
<>	134:ad3be0349dc5	570	* @retval None
<>	134:ad3be0349dc5	571	*/
<>	134:ad3be0349dc5	572	__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
<>	134:ad3be0349dc5	573	{
<>	134:ad3be0349dc5	574	MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
<>	134:ad3be0349dc5	575	}
<>	134:ad3be0349dc5	576
<>	134:ad3be0349dc5	577	/**
<>	134:ad3be0349dc5	578	* @brief Get transfer bit order
<>	134:ad3be0349dc5	579	* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
<>	134:ad3be0349dc5	580	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	581	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	582	* @arg @ref LL_SPI_LSB_FIRST
<>	134:ad3be0349dc5	583	* @arg @ref LL_SPI_MSB_FIRST
<>	134:ad3be0349dc5	584	*/
<>	134:ad3be0349dc5	585	__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	586	{
<>	134:ad3be0349dc5	587	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
<>	134:ad3be0349dc5	588	}
<>	134:ad3be0349dc5	589
<>	134:ad3be0349dc5	590	/**
<>	134:ad3be0349dc5	591	* @brief Set transfer direction mode
<>	134:ad3be0349dc5	592	* @note For Half-Duplex mode, Rx Direction is set by default.
<>	134:ad3be0349dc5	593	* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
<>	134:ad3be0349dc5	594	* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
<>	134:ad3be0349dc5	595	* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
<>	134:ad3be0349dc5	596	* CR1 BIDIOE LL_SPI_SetTransferDirection
<>	134:ad3be0349dc5	597	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	598	* @param TransferDirection This parameter can be one of the following values:
<>	134:ad3be0349dc5	599	* @arg @ref LL_SPI_FULL_DUPLEX
<>	134:ad3be0349dc5	600	* @arg @ref LL_SPI_SIMPLEX_RX
<>	134:ad3be0349dc5	601	* @arg @ref LL_SPI_HALF_DUPLEX_RX
<>	134:ad3be0349dc5	602	* @arg @ref LL_SPI_HALF_DUPLEX_TX
<>	134:ad3be0349dc5	603	* @retval None
<>	134:ad3be0349dc5	604	*/
<>	134:ad3be0349dc5	605	__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
<>	134:ad3be0349dc5	606	{
<>	134:ad3be0349dc5	607	MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE, TransferDirection);
<>	134:ad3be0349dc5	608	}
<>	134:ad3be0349dc5	609
<>	134:ad3be0349dc5	610	/**
<>	134:ad3be0349dc5	611	* @brief Get transfer direction mode
<>	134:ad3be0349dc5	612	* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
<>	134:ad3be0349dc5	613	* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
<>	134:ad3be0349dc5	614	* CR1 BIDIOE LL_SPI_GetTransferDirection
<>	134:ad3be0349dc5	615	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	616	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	617	* @arg @ref LL_SPI_FULL_DUPLEX
<>	134:ad3be0349dc5	618	* @arg @ref LL_SPI_SIMPLEX_RX
<>	134:ad3be0349dc5	619	* @arg @ref LL_SPI_HALF_DUPLEX_RX
<>	134:ad3be0349dc5	620	* @arg @ref LL_SPI_HALF_DUPLEX_TX
<>	134:ad3be0349dc5	621	*/
<>	134:ad3be0349dc5	622	__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	623	{
<>	134:ad3be0349dc5	624	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE));
<>	134:ad3be0349dc5	625	}
<>	134:ad3be0349dc5	626
<>	134:ad3be0349dc5	627	/**
<>	134:ad3be0349dc5	628	* @brief Set frame data width
<>	134:ad3be0349dc5	629	* @rmtoll CR2 DS LL_SPI_SetDataWidth
<>	134:ad3be0349dc5	630	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	631	* @param DataWidth This parameter can be one of the following values:
<>	134:ad3be0349dc5	632	* @arg @ref LL_SPI_DATAWIDTH_4BIT
<>	134:ad3be0349dc5	633	* @arg @ref LL_SPI_DATAWIDTH_5BIT
<>	134:ad3be0349dc5	634	* @arg @ref LL_SPI_DATAWIDTH_6BIT
<>	134:ad3be0349dc5	635	* @arg @ref LL_SPI_DATAWIDTH_7BIT
<>	134:ad3be0349dc5	636	* @arg @ref LL_SPI_DATAWIDTH_8BIT
<>	134:ad3be0349dc5	637	* @arg @ref LL_SPI_DATAWIDTH_9BIT
<>	134:ad3be0349dc5	638	* @arg @ref LL_SPI_DATAWIDTH_10BIT
<>	134:ad3be0349dc5	639	* @arg @ref LL_SPI_DATAWIDTH_11BIT
<>	134:ad3be0349dc5	640	* @arg @ref LL_SPI_DATAWIDTH_12BIT
<>	134:ad3be0349dc5	641	* @arg @ref LL_SPI_DATAWIDTH_13BIT
<>	134:ad3be0349dc5	642	* @arg @ref LL_SPI_DATAWIDTH_14BIT
<>	134:ad3be0349dc5	643	* @arg @ref LL_SPI_DATAWIDTH_15BIT
<>	134:ad3be0349dc5	644	* @arg @ref LL_SPI_DATAWIDTH_16BIT
<>	134:ad3be0349dc5	645	* @retval None
<>	134:ad3be0349dc5	646	*/
<>	134:ad3be0349dc5	647	__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
<>	134:ad3be0349dc5	648	{
<>	134:ad3be0349dc5	649	MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
<>	134:ad3be0349dc5	650	}
<>	134:ad3be0349dc5	651
<>	134:ad3be0349dc5	652	/**
<>	134:ad3be0349dc5	653	* @brief Get frame data width
<>	134:ad3be0349dc5	654	* @rmtoll CR2 DS LL_SPI_GetDataWidth
<>	134:ad3be0349dc5	655	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	656	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	657	* @arg @ref LL_SPI_DATAWIDTH_4BIT
<>	134:ad3be0349dc5	658	* @arg @ref LL_SPI_DATAWIDTH_5BIT
<>	134:ad3be0349dc5	659	* @arg @ref LL_SPI_DATAWIDTH_6BIT
<>	134:ad3be0349dc5	660	* @arg @ref LL_SPI_DATAWIDTH_7BIT
<>	134:ad3be0349dc5	661	* @arg @ref LL_SPI_DATAWIDTH_8BIT
<>	134:ad3be0349dc5	662	* @arg @ref LL_SPI_DATAWIDTH_9BIT
<>	134:ad3be0349dc5	663	* @arg @ref LL_SPI_DATAWIDTH_10BIT
<>	134:ad3be0349dc5	664	* @arg @ref LL_SPI_DATAWIDTH_11BIT
<>	134:ad3be0349dc5	665	* @arg @ref LL_SPI_DATAWIDTH_12BIT
<>	134:ad3be0349dc5	666	* @arg @ref LL_SPI_DATAWIDTH_13BIT
<>	134:ad3be0349dc5	667	* @arg @ref LL_SPI_DATAWIDTH_14BIT
<>	134:ad3be0349dc5	668	* @arg @ref LL_SPI_DATAWIDTH_15BIT
<>	134:ad3be0349dc5	669	* @arg @ref LL_SPI_DATAWIDTH_16BIT
<>	134:ad3be0349dc5	670	*/
<>	134:ad3be0349dc5	671	__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	672	{
<>	134:ad3be0349dc5	673	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
<>	134:ad3be0349dc5	674	}
<>	134:ad3be0349dc5	675
<>	134:ad3be0349dc5	676	/**
<>	134:ad3be0349dc5	677	* @brief Set threshold of RXFIFO that triggers an RXNE event
<>	134:ad3be0349dc5	678	* @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
<>	134:ad3be0349dc5	679	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	680	* @param Threshold This parameter can be one of the following values:
<>	134:ad3be0349dc5	681	* @arg @ref LL_SPI_RX_FIFO_TH_HALF
<>	134:ad3be0349dc5	682	* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
<>	134:ad3be0349dc5	683	* @retval None
<>	134:ad3be0349dc5	684	*/
<>	134:ad3be0349dc5	685	__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
<>	134:ad3be0349dc5	686	{
<>	134:ad3be0349dc5	687	MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
<>	134:ad3be0349dc5	688	}
<>	134:ad3be0349dc5	689
<>	134:ad3be0349dc5	690	/**
<>	134:ad3be0349dc5	691	* @brief Get threshold of RXFIFO that triggers an RXNE event
<>	134:ad3be0349dc5	692	* @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
<>	134:ad3be0349dc5	693	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	694	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	695	* @arg @ref LL_SPI_RX_FIFO_TH_HALF
<>	134:ad3be0349dc5	696	* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
<>	134:ad3be0349dc5	697	*/
<>	134:ad3be0349dc5	698	__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	699	{
<>	134:ad3be0349dc5	700	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
<>	134:ad3be0349dc5	701	}
<>	134:ad3be0349dc5	702
<>	134:ad3be0349dc5	703	/**
<>	134:ad3be0349dc5	704	* @}
<>	134:ad3be0349dc5	705	*/
<>	134:ad3be0349dc5	706
<>	134:ad3be0349dc5	707	/** @defgroup SPI_LL_EF_CRC_Management CRC Management
<>	134:ad3be0349dc5	708	* @{
<>	134:ad3be0349dc5	709	*/
<>	134:ad3be0349dc5	710
<>	134:ad3be0349dc5	711	/**
<>	134:ad3be0349dc5	712	* @brief Enable CRC
<>	134:ad3be0349dc5	713	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<>	134:ad3be0349dc5	714	* @rmtoll CR1 CRCEN LL_SPI_EnableCRC
<>	134:ad3be0349dc5	715	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	716	* @retval None
<>	134:ad3be0349dc5	717	*/
<>	134:ad3be0349dc5	718	__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	719	{
<>	134:ad3be0349dc5	720	SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
<>	134:ad3be0349dc5	721	}
<>	134:ad3be0349dc5	722
<>	134:ad3be0349dc5	723	/**
<>	134:ad3be0349dc5	724	* @brief Disable CRC
<>	134:ad3be0349dc5	725	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<>	134:ad3be0349dc5	726	* @rmtoll CR1 CRCEN LL_SPI_DisableCRC
<>	134:ad3be0349dc5	727	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	728	* @retval None
<>	134:ad3be0349dc5	729	*/
<>	134:ad3be0349dc5	730	__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	731	{
<>	134:ad3be0349dc5	732	CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
<>	134:ad3be0349dc5	733	}
<>	134:ad3be0349dc5	734
<>	134:ad3be0349dc5	735	/**
<>	134:ad3be0349dc5	736	* @brief Check if CRC is enabled
<>	134:ad3be0349dc5	737	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<>	134:ad3be0349dc5	738	* @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
<>	134:ad3be0349dc5	739	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	740	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	741	*/
<>	134:ad3be0349dc5	742	__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	743	{
<>	134:ad3be0349dc5	744	return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
<>	134:ad3be0349dc5	745	}
<>	134:ad3be0349dc5	746
<>	134:ad3be0349dc5	747	/**
<>	134:ad3be0349dc5	748	* @brief Set CRC Length
<>	134:ad3be0349dc5	749	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<>	134:ad3be0349dc5	750	* @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
<>	134:ad3be0349dc5	751	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	752	* @param CRCLength This parameter can be one of the following values:
<>	134:ad3be0349dc5	753	* @arg @ref LL_SPI_CRC_8BIT
<>	134:ad3be0349dc5	754	* @arg @ref LL_SPI_CRC_16BIT
<>	134:ad3be0349dc5	755	* @retval None
<>	134:ad3be0349dc5	756	*/
<>	134:ad3be0349dc5	757	__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
<>	134:ad3be0349dc5	758	{
<>	134:ad3be0349dc5	759	MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
<>	134:ad3be0349dc5	760	}
<>	134:ad3be0349dc5	761
<>	134:ad3be0349dc5	762	/**
<>	134:ad3be0349dc5	763	* @brief Get CRC Length
<>	134:ad3be0349dc5	764	* @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
<>	134:ad3be0349dc5	765	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	766	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	767	* @arg @ref LL_SPI_CRC_8BIT
<>	134:ad3be0349dc5	768	* @arg @ref LL_SPI_CRC_16BIT
<>	134:ad3be0349dc5	769	*/
<>	134:ad3be0349dc5	770	__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	771	{
<>	134:ad3be0349dc5	772	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
<>	134:ad3be0349dc5	773	}
<>	134:ad3be0349dc5	774
<>	134:ad3be0349dc5	775	/**
<>	134:ad3be0349dc5	776	* @brief Set CRCNext to transfer CRC on the line
<>	134:ad3be0349dc5	777	* @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
<>	134:ad3be0349dc5	778	* @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
<>	134:ad3be0349dc5	779	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	780	* @retval None
<>	134:ad3be0349dc5	781	*/
<>	134:ad3be0349dc5	782	__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	783	{
<>	134:ad3be0349dc5	784	SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
<>	134:ad3be0349dc5	785	}
<>	134:ad3be0349dc5	786
<>	134:ad3be0349dc5	787	/**
<>	134:ad3be0349dc5	788	* @brief Set polynomial for CRC calculation
<>	134:ad3be0349dc5	789	* @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
<>	134:ad3be0349dc5	790	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	791	* @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<>	134:ad3be0349dc5	792	* @retval None
<>	134:ad3be0349dc5	793	*/
<>	134:ad3be0349dc5	794	__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
<>	134:ad3be0349dc5	795	{
<>	134:ad3be0349dc5	796	WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
<>	134:ad3be0349dc5	797	}
<>	134:ad3be0349dc5	798
<>	134:ad3be0349dc5	799	/**
<>	134:ad3be0349dc5	800	* @brief Get polynomial for CRC calculation
<>	134:ad3be0349dc5	801	* @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
<>	134:ad3be0349dc5	802	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	803	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<>	134:ad3be0349dc5	804	*/
<>	134:ad3be0349dc5	805	__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	806	{
<>	134:ad3be0349dc5	807	return (uint32_t)(READ_REG(SPIx->CRCPR));
<>	134:ad3be0349dc5	808	}
<>	134:ad3be0349dc5	809
<>	134:ad3be0349dc5	810	/**
<>	134:ad3be0349dc5	811	* @brief Get Rx CRC
<>	134:ad3be0349dc5	812	* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
<>	134:ad3be0349dc5	813	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	814	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<>	134:ad3be0349dc5	815	*/
<>	134:ad3be0349dc5	816	__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	817	{
<>	134:ad3be0349dc5	818	return (uint32_t)(READ_REG(SPIx->RXCRCR));
<>	134:ad3be0349dc5	819	}
<>	134:ad3be0349dc5	820
<>	134:ad3be0349dc5	821	/**
<>	134:ad3be0349dc5	822	* @brief Get Tx CRC
<>	134:ad3be0349dc5	823	* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
<>	134:ad3be0349dc5	824	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	825	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<>	134:ad3be0349dc5	826	*/
<>	134:ad3be0349dc5	827	__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	828	{
<>	134:ad3be0349dc5	829	return (uint32_t)(READ_REG(SPIx->TXCRCR));
<>	134:ad3be0349dc5	830	}
<>	134:ad3be0349dc5	831
<>	134:ad3be0349dc5	832	/**
<>	134:ad3be0349dc5	833	* @}
<>	134:ad3be0349dc5	834	*/
<>	134:ad3be0349dc5	835
<>	134:ad3be0349dc5	836	/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
<>	134:ad3be0349dc5	837	* @{
<>	134:ad3be0349dc5	838	*/
<>	134:ad3be0349dc5	839
<>	134:ad3be0349dc5	840	/**
<>	134:ad3be0349dc5	841	* @brief Set NSS mode
<>	134:ad3be0349dc5	842	* @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
<>	134:ad3be0349dc5	843	* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
<>	134:ad3be0349dc5	844	* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
<>	134:ad3be0349dc5	845	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	846	* @param NSS This parameter can be one of the following values:
<>	134:ad3be0349dc5	847	* @arg @ref LL_SPI_NSS_SOFT
<>	134:ad3be0349dc5	848	* @arg @ref LL_SPI_NSS_HARD_INPUT
<>	134:ad3be0349dc5	849	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
<>	134:ad3be0349dc5	850	* @retval None
<>	134:ad3be0349dc5	851	*/
<>	134:ad3be0349dc5	852	__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
<>	134:ad3be0349dc5	853	{
<>	134:ad3be0349dc5	854	MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
<>	134:ad3be0349dc5	855	MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
<>	134:ad3be0349dc5	856	}
<>	134:ad3be0349dc5	857
<>	134:ad3be0349dc5	858	/**
<>	134:ad3be0349dc5	859	* @brief Get NSS mode
<>	134:ad3be0349dc5	860	* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
<>	134:ad3be0349dc5	861	* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
<>	134:ad3be0349dc5	862	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	863	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	864	* @arg @ref LL_SPI_NSS_SOFT
<>	134:ad3be0349dc5	865	* @arg @ref LL_SPI_NSS_HARD_INPUT
<>	134:ad3be0349dc5	866	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
<>	134:ad3be0349dc5	867	*/
<>	134:ad3be0349dc5	868	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	869	{
<>	134:ad3be0349dc5	870	register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
<>	134:ad3be0349dc5	871	register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
<>	134:ad3be0349dc5	872	return (Ssm \| Ssoe);
<>	134:ad3be0349dc5	873	}
<>	134:ad3be0349dc5	874
<>	134:ad3be0349dc5	875	/**
<>	134:ad3be0349dc5	876	* @brief Enable NSS pulse management
<>	134:ad3be0349dc5	877	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
<>	134:ad3be0349dc5	878	* @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
<>	134:ad3be0349dc5	879	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	880	* @retval None
<>	134:ad3be0349dc5	881	*/
<>	134:ad3be0349dc5	882	__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	883	{
<>	134:ad3be0349dc5	884	SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
<>	134:ad3be0349dc5	885	}
<>	134:ad3be0349dc5	886
<>	134:ad3be0349dc5	887	/**
<>	134:ad3be0349dc5	888	* @brief Disable NSS pulse management
<>	134:ad3be0349dc5	889	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
<>	134:ad3be0349dc5	890	* @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
<>	134:ad3be0349dc5	891	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	892	* @retval None
<>	134:ad3be0349dc5	893	*/
<>	134:ad3be0349dc5	894	__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	895	{
<>	134:ad3be0349dc5	896	CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
<>	134:ad3be0349dc5	897	}
<>	134:ad3be0349dc5	898
<>	134:ad3be0349dc5	899	/**
<>	134:ad3be0349dc5	900	* @brief Check if NSS pulse is enabled
<>	134:ad3be0349dc5	901	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
<>	134:ad3be0349dc5	902	* @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
<>	134:ad3be0349dc5	903	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	904	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	905	*/
<>	134:ad3be0349dc5	906	__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	907	{
<>	134:ad3be0349dc5	908	return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP));
<>	134:ad3be0349dc5	909	}
<>	134:ad3be0349dc5	910
<>	134:ad3be0349dc5	911	/**
<>	134:ad3be0349dc5	912	* @}
<>	134:ad3be0349dc5	913	*/
<>	134:ad3be0349dc5	914
<>	134:ad3be0349dc5	915	/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
<>	134:ad3be0349dc5	916	* @{
<>	134:ad3be0349dc5	917	*/
<>	134:ad3be0349dc5	918
<>	134:ad3be0349dc5	919	/**
<>	134:ad3be0349dc5	920	* @brief Check if Rx buffer is not empty
<>	134:ad3be0349dc5	921	* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
<>	134:ad3be0349dc5	922	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	923	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	924	*/
<>	134:ad3be0349dc5	925	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	926	{
<>	134:ad3be0349dc5	927	return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
<>	134:ad3be0349dc5	928	}
<>	134:ad3be0349dc5	929
<>	134:ad3be0349dc5	930	/**
<>	134:ad3be0349dc5	931	* @brief Check if Tx buffer is empty
<>	134:ad3be0349dc5	932	* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
<>	134:ad3be0349dc5	933	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	934	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	935	*/
<>	134:ad3be0349dc5	936	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	937	{
<>	134:ad3be0349dc5	938	return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
<>	134:ad3be0349dc5	939	}
<>	134:ad3be0349dc5	940
<>	134:ad3be0349dc5	941	/**
<>	134:ad3be0349dc5	942	* @brief Get CRC error flag
<>	134:ad3be0349dc5	943	* @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
<>	134:ad3be0349dc5	944	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	945	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	946	*/
<>	134:ad3be0349dc5	947	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	948	{
<>	134:ad3be0349dc5	949	return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
<>	134:ad3be0349dc5	950	}
<>	134:ad3be0349dc5	951
<>	134:ad3be0349dc5	952	/**
<>	134:ad3be0349dc5	953	* @brief Get mode fault error flag
<>	134:ad3be0349dc5	954	* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
<>	134:ad3be0349dc5	955	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	956	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	957	*/
<>	134:ad3be0349dc5	958	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	959	{
<>	134:ad3be0349dc5	960	return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
<>	134:ad3be0349dc5	961	}
<>	134:ad3be0349dc5	962
<>	134:ad3be0349dc5	963	/**
<>	134:ad3be0349dc5	964	* @brief Get overrun error flag
<>	134:ad3be0349dc5	965	* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
<>	134:ad3be0349dc5	966	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	967	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	968	*/
<>	134:ad3be0349dc5	969	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	970	{
<>	134:ad3be0349dc5	971	return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
<>	134:ad3be0349dc5	972	}
<>	134:ad3be0349dc5	973
<>	134:ad3be0349dc5	974	/**
<>	134:ad3be0349dc5	975	* @brief Get busy flag
<>	134:ad3be0349dc5	976	* @note The BSY flag is cleared under any one of the following conditions:
<>	134:ad3be0349dc5	977	* -When the SPI is correctly disabled
<>	134:ad3be0349dc5	978	* -When a fault is detected in Master mode (MODF bit set to 1)
<>	134:ad3be0349dc5	979	* -In Master mode, when it finishes a data transmission and no new data is ready to be
<>	134:ad3be0349dc5	980	* sent
<>	134:ad3be0349dc5	981	* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
<>	134:ad3be0349dc5	982	* each data transfer.
<>	134:ad3be0349dc5	983	* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
<>	134:ad3be0349dc5	984	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	985	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	986	*/
<>	134:ad3be0349dc5	987	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	988	{
<>	134:ad3be0349dc5	989	return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
<>	134:ad3be0349dc5	990	}
<>	134:ad3be0349dc5	991
<>	134:ad3be0349dc5	992	/**
<>	134:ad3be0349dc5	993	* @brief Get frame format error flag
<>	134:ad3be0349dc5	994	* @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
<>	134:ad3be0349dc5	995	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	996	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	997	*/
<>	134:ad3be0349dc5	998	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	999	{
<>	134:ad3be0349dc5	1000	return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
<>	134:ad3be0349dc5	1001	}
<>	134:ad3be0349dc5	1002
<>	134:ad3be0349dc5	1003	/**
<>	134:ad3be0349dc5	1004	* @brief Get FIFO reception Level
<>	134:ad3be0349dc5	1005	* @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
<>	134:ad3be0349dc5	1006	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1007	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	1008	* @arg @ref LL_SPI_RX_FIFO_EMPTY
<>	134:ad3be0349dc5	1009	* @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
<>	134:ad3be0349dc5	1010	* @arg @ref LL_SPI_RX_FIFO_HALF_FULL
<>	134:ad3be0349dc5	1011	* @arg @ref LL_SPI_RX_FIFO_FULL
<>	134:ad3be0349dc5	1012	*/
<>	134:ad3be0349dc5	1013	__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1014	{
<>	134:ad3be0349dc5	1015	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
<>	134:ad3be0349dc5	1016	}
<>	134:ad3be0349dc5	1017
<>	134:ad3be0349dc5	1018	/**
<>	134:ad3be0349dc5	1019	* @brief Get FIFO Transmission Level
<>	134:ad3be0349dc5	1020	* @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
<>	134:ad3be0349dc5	1021	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1022	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	1023	* @arg @ref LL_SPI_TX_FIFO_EMPTY
<>	134:ad3be0349dc5	1024	* @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
<>	134:ad3be0349dc5	1025	* @arg @ref LL_SPI_TX_FIFO_HALF_FULL
<>	134:ad3be0349dc5	1026	* @arg @ref LL_SPI_TX_FIFO_FULL
<>	134:ad3be0349dc5	1027	*/
<>	134:ad3be0349dc5	1028	__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1029	{
<>	134:ad3be0349dc5	1030	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
<>	134:ad3be0349dc5	1031	}
<>	134:ad3be0349dc5	1032
<>	134:ad3be0349dc5	1033	/**
<>	134:ad3be0349dc5	1034	* @brief Clear CRC error flag
<>	134:ad3be0349dc5	1035	* @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
<>	134:ad3be0349dc5	1036	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1037	* @retval None
<>	134:ad3be0349dc5	1038	*/
<>	134:ad3be0349dc5	1039	__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1040	{
<>	134:ad3be0349dc5	1041	CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
<>	134:ad3be0349dc5	1042	}
<>	134:ad3be0349dc5	1043
<>	134:ad3be0349dc5	1044	/**
<>	134:ad3be0349dc5	1045	* @brief Clear mode fault error flag
<>	134:ad3be0349dc5	1046	* @note Clearing this flag is done by a read access to the SPIx_SR
<>	134:ad3be0349dc5	1047	* register followed by a write access to the SPIx_CR1 register
<>	134:ad3be0349dc5	1048	* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
<>	134:ad3be0349dc5	1049	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1050	* @retval None
<>	134:ad3be0349dc5	1051	*/
<>	134:ad3be0349dc5	1052	__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1053	{
<>	134:ad3be0349dc5	1054	__IO uint32_t tmpreg;
<>	134:ad3be0349dc5	1055	tmpreg = SPIx->SR;
<>	134:ad3be0349dc5	1056	(void) tmpreg;
<>	134:ad3be0349dc5	1057	tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
<>	134:ad3be0349dc5	1058	(void) tmpreg;
<>	134:ad3be0349dc5	1059	}
<>	134:ad3be0349dc5	1060
<>	134:ad3be0349dc5	1061	/**
<>	134:ad3be0349dc5	1062	* @brief Clear overrun error flag
<>	134:ad3be0349dc5	1063	* @note Clearing this flag is done by a read access to the SPIx_DR
<>	134:ad3be0349dc5	1064	* register followed by a read access to the SPIx_SR register
<>	134:ad3be0349dc5	1065	* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
<>	134:ad3be0349dc5	1066	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1067	* @retval None
<>	134:ad3be0349dc5	1068	*/
<>	134:ad3be0349dc5	1069	__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1070	{
<>	134:ad3be0349dc5	1071	__IO uint32_t tmpreg;
<>	134:ad3be0349dc5	1072	tmpreg = SPIx->DR;
<>	134:ad3be0349dc5	1073	(void) tmpreg;
<>	134:ad3be0349dc5	1074	tmpreg = SPIx->SR;
<>	134:ad3be0349dc5	1075	(void) tmpreg;
<>	134:ad3be0349dc5	1076	}
<>	134:ad3be0349dc5	1077
<>	134:ad3be0349dc5	1078	/**
<>	134:ad3be0349dc5	1079	* @brief Clear frame format error flag
<>	134:ad3be0349dc5	1080	* @note Clearing this flag is done by reading SPIx_SR register
<>	134:ad3be0349dc5	1081	* @rmtoll SR FRE LL_SPI_ClearFlag_FRE
<>	134:ad3be0349dc5	1082	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1083	* @retval None
<>	134:ad3be0349dc5	1084	*/
<>	134:ad3be0349dc5	1085	__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1086	{
<>	134:ad3be0349dc5	1087	__IO uint32_t tmpreg;
<>	134:ad3be0349dc5	1088	tmpreg = SPIx->SR;
<>	134:ad3be0349dc5	1089	(void) tmpreg;
<>	134:ad3be0349dc5	1090	}
<>	134:ad3be0349dc5	1091
<>	134:ad3be0349dc5	1092	/**
<>	134:ad3be0349dc5	1093	* @}
<>	134:ad3be0349dc5	1094	*/
<>	134:ad3be0349dc5	1095
<>	134:ad3be0349dc5	1096	/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
<>	134:ad3be0349dc5	1097	* @{
<>	134:ad3be0349dc5	1098	*/
<>	134:ad3be0349dc5	1099
<>	134:ad3be0349dc5	1100	/**
<>	134:ad3be0349dc5	1101	* @brief Enable error interrupt
<>	134:ad3be0349dc5	1102	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
<>	134:ad3be0349dc5	1103	* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
<>	134:ad3be0349dc5	1104	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1105	* @retval None
<>	134:ad3be0349dc5	1106	*/
<>	134:ad3be0349dc5	1107	__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1108	{
<>	134:ad3be0349dc5	1109	SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
<>	134:ad3be0349dc5	1110	}
<>	134:ad3be0349dc5	1111
<>	134:ad3be0349dc5	1112	/**
<>	134:ad3be0349dc5	1113	* @brief Enable Rx buffer not empty interrupt
<>	134:ad3be0349dc5	1114	* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
<>	134:ad3be0349dc5	1115	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1116	* @retval None
<>	134:ad3be0349dc5	1117	*/
<>	134:ad3be0349dc5	1118	__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1119	{
<>	134:ad3be0349dc5	1120	SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
<>	134:ad3be0349dc5	1121	}
<>	134:ad3be0349dc5	1122
<>	134:ad3be0349dc5	1123	/**
<>	134:ad3be0349dc5	1124	* @brief Enable Tx buffer empty interrupt
<>	134:ad3be0349dc5	1125	* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
<>	134:ad3be0349dc5	1126	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1127	* @retval None
<>	134:ad3be0349dc5	1128	*/
<>	134:ad3be0349dc5	1129	__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1130	{
<>	134:ad3be0349dc5	1131	SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
<>	134:ad3be0349dc5	1132	}
<>	134:ad3be0349dc5	1133
<>	134:ad3be0349dc5	1134	/**
<>	134:ad3be0349dc5	1135	* @brief Disable error interrupt
<>	134:ad3be0349dc5	1136	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
<>	134:ad3be0349dc5	1137	* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
<>	134:ad3be0349dc5	1138	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1139	* @retval None
<>	134:ad3be0349dc5	1140	*/
<>	134:ad3be0349dc5	1141	__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1142	{
<>	134:ad3be0349dc5	1143	CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
<>	134:ad3be0349dc5	1144	}
<>	134:ad3be0349dc5	1145
<>	134:ad3be0349dc5	1146	/**
<>	134:ad3be0349dc5	1147	* @brief Disable Rx buffer not empty interrupt
<>	134:ad3be0349dc5	1148	* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
<>	134:ad3be0349dc5	1149	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1150	* @retval None
<>	134:ad3be0349dc5	1151	*/
<>	134:ad3be0349dc5	1152	__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1153	{
<>	134:ad3be0349dc5	1154	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
<>	134:ad3be0349dc5	1155	}
<>	134:ad3be0349dc5	1156
<>	134:ad3be0349dc5	1157	/**
<>	134:ad3be0349dc5	1158	* @brief Disable Tx buffer empty interrupt
<>	134:ad3be0349dc5	1159	* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
<>	134:ad3be0349dc5	1160	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1161	* @retval None
<>	134:ad3be0349dc5	1162	*/
<>	134:ad3be0349dc5	1163	__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1164	{
<>	134:ad3be0349dc5	1165	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
<>	134:ad3be0349dc5	1166	}
<>	134:ad3be0349dc5	1167
<>	134:ad3be0349dc5	1168	/**
<>	134:ad3be0349dc5	1169	* @brief Check if error interrupt is enabled
<>	134:ad3be0349dc5	1170	* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
<>	134:ad3be0349dc5	1171	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1172	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1173	*/
<>	134:ad3be0349dc5	1174	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1175	{
<>	134:ad3be0349dc5	1176	return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
<>	134:ad3be0349dc5	1177	}
<>	134:ad3be0349dc5	1178
<>	134:ad3be0349dc5	1179	/**
<>	134:ad3be0349dc5	1180	* @brief Check if Rx buffer not empty interrupt is enabled
<>	134:ad3be0349dc5	1181	* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
<>	134:ad3be0349dc5	1182	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1183	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1184	*/
<>	134:ad3be0349dc5	1185	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1186	{
<>	134:ad3be0349dc5	1187	return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
<>	134:ad3be0349dc5	1188	}
<>	134:ad3be0349dc5	1189
<>	134:ad3be0349dc5	1190	/**
<>	134:ad3be0349dc5	1191	* @brief Check if Tx buffer empty interrupt
<>	134:ad3be0349dc5	1192	* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
<>	134:ad3be0349dc5	1193	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1194	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1195	*/
<>	134:ad3be0349dc5	1196	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1197	{
<>	134:ad3be0349dc5	1198	return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
<>	134:ad3be0349dc5	1199	}
<>	134:ad3be0349dc5	1200
<>	134:ad3be0349dc5	1201	/**
<>	134:ad3be0349dc5	1202	* @}
<>	134:ad3be0349dc5	1203	*/
<>	134:ad3be0349dc5	1204
<>	134:ad3be0349dc5	1205	/** @defgroup SPI_LL_EF_DMA_Management DMA Management
<>	134:ad3be0349dc5	1206	* @{
<>	134:ad3be0349dc5	1207	*/
<>	134:ad3be0349dc5	1208
<>	134:ad3be0349dc5	1209	/**
<>	134:ad3be0349dc5	1210	* @brief Enable DMA Rx
<>	134:ad3be0349dc5	1211	* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
<>	134:ad3be0349dc5	1212	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1213	* @retval None
<>	134:ad3be0349dc5	1214	*/
<>	134:ad3be0349dc5	1215	__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1216	{
<>	134:ad3be0349dc5	1217	SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
<>	134:ad3be0349dc5	1218	}
<>	134:ad3be0349dc5	1219
<>	134:ad3be0349dc5	1220	/**
<>	134:ad3be0349dc5	1221	* @brief Disable DMA Rx
<>	134:ad3be0349dc5	1222	* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
<>	134:ad3be0349dc5	1223	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1224	* @retval None
<>	134:ad3be0349dc5	1225	*/
<>	134:ad3be0349dc5	1226	__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1227	{
<>	134:ad3be0349dc5	1228	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
<>	134:ad3be0349dc5	1229	}
<>	134:ad3be0349dc5	1230
<>	134:ad3be0349dc5	1231	/**
<>	134:ad3be0349dc5	1232	* @brief Check if DMA Rx is enabled
<>	134:ad3be0349dc5	1233	* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
<>	134:ad3be0349dc5	1234	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1235	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1236	*/
<>	134:ad3be0349dc5	1237	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1238	{
<>	134:ad3be0349dc5	1239	return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
<>	134:ad3be0349dc5	1240	}
<>	134:ad3be0349dc5	1241
<>	134:ad3be0349dc5	1242	/**
<>	134:ad3be0349dc5	1243	* @brief Enable DMA Tx
<>	134:ad3be0349dc5	1244	* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
<>	134:ad3be0349dc5	1245	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1246	* @retval None
<>	134:ad3be0349dc5	1247	*/
<>	134:ad3be0349dc5	1248	__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1249	{
<>	134:ad3be0349dc5	1250	SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
<>	134:ad3be0349dc5	1251	}
<>	134:ad3be0349dc5	1252
<>	134:ad3be0349dc5	1253	/**
<>	134:ad3be0349dc5	1254	* @brief Disable DMA Tx
<>	134:ad3be0349dc5	1255	* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
<>	134:ad3be0349dc5	1256	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1257	* @retval None
<>	134:ad3be0349dc5	1258	*/
<>	134:ad3be0349dc5	1259	__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1260	{
<>	134:ad3be0349dc5	1261	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
<>	134:ad3be0349dc5	1262	}
<>	134:ad3be0349dc5	1263
<>	134:ad3be0349dc5	1264	/**
<>	134:ad3be0349dc5	1265	* @brief Check if DMA Tx is enabled
<>	134:ad3be0349dc5	1266	* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
<>	134:ad3be0349dc5	1267	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1268	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1269	*/
<>	134:ad3be0349dc5	1270	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1271	{
<>	134:ad3be0349dc5	1272	return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
<>	134:ad3be0349dc5	1273	}
<>	134:ad3be0349dc5	1274
<>	134:ad3be0349dc5	1275	/**
<>	134:ad3be0349dc5	1276	* @brief Set parity of Last DMA reception
<>	134:ad3be0349dc5	1277	* @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
<>	134:ad3be0349dc5	1278	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1279	* @param Parity This parameter can be one of the following values:
<>	134:ad3be0349dc5	1280	* @arg @ref LL_SPI_DMA_PARITY_ODD
<>	134:ad3be0349dc5	1281	* @arg @ref LL_SPI_DMA_PARITY_EVEN
<>	134:ad3be0349dc5	1282	* @retval None
<>	134:ad3be0349dc5	1283	*/
<>	134:ad3be0349dc5	1284	__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
<>	134:ad3be0349dc5	1285	{
<>	134:ad3be0349dc5	1286	MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << 13U));
<>	134:ad3be0349dc5	1287	}
<>	134:ad3be0349dc5	1288
<>	134:ad3be0349dc5	1289	/**
<>	134:ad3be0349dc5	1290	* @brief Get parity configuration for Last DMA reception
<>	134:ad3be0349dc5	1291	* @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
<>	134:ad3be0349dc5	1292	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1293	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	1294	* @arg @ref LL_SPI_DMA_PARITY_ODD
<>	134:ad3be0349dc5	1295	* @arg @ref LL_SPI_DMA_PARITY_EVEN
<>	134:ad3be0349dc5	1296	*/
<>	134:ad3be0349dc5	1297	__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1298	{
<>	134:ad3be0349dc5	1299	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> 13U);
<>	134:ad3be0349dc5	1300	}
<>	134:ad3be0349dc5	1301
<>	134:ad3be0349dc5	1302	/**
<>	134:ad3be0349dc5	1303	* @brief Set parity of Last DMA transmission
<>	134:ad3be0349dc5	1304	* @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
<>	134:ad3be0349dc5	1305	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1306	* @param Parity This parameter can be one of the following values:
<>	134:ad3be0349dc5	1307	* @arg @ref LL_SPI_DMA_PARITY_ODD
<>	134:ad3be0349dc5	1308	* @arg @ref LL_SPI_DMA_PARITY_EVEN
<>	134:ad3be0349dc5	1309	* @retval None
<>	134:ad3be0349dc5	1310	*/
<>	134:ad3be0349dc5	1311	__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
<>	134:ad3be0349dc5	1312	{
<>	134:ad3be0349dc5	1313	MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << 14U));
<>	134:ad3be0349dc5	1314	}
<>	134:ad3be0349dc5	1315
<>	134:ad3be0349dc5	1316	/**
<>	134:ad3be0349dc5	1317	* @brief Get parity configuration for Last DMA transmission
<>	134:ad3be0349dc5	1318	* @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
<>	134:ad3be0349dc5	1319	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1320	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	1321	* @arg @ref LL_SPI_DMA_PARITY_ODD
<>	134:ad3be0349dc5	1322	* @arg @ref LL_SPI_DMA_PARITY_EVEN
<>	134:ad3be0349dc5	1323	*/
<>	134:ad3be0349dc5	1324	__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1325	{
<>	134:ad3be0349dc5	1326	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> 14U);
<>	134:ad3be0349dc5	1327	}
<>	134:ad3be0349dc5	1328
<>	134:ad3be0349dc5	1329	/**
<>	134:ad3be0349dc5	1330	* @brief Get the data register address used for DMA transfer
<>	134:ad3be0349dc5	1331	* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
<>	134:ad3be0349dc5	1332	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1333	* @retval Address of data register
<>	134:ad3be0349dc5	1334	*/
<>	134:ad3be0349dc5	1335	__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1336	{
<>	134:ad3be0349dc5	1337	return (uint32_t) & (SPIx->DR);
<>	134:ad3be0349dc5	1338	}
<>	134:ad3be0349dc5	1339
<>	134:ad3be0349dc5	1340	/**
<>	134:ad3be0349dc5	1341	* @}
<>	134:ad3be0349dc5	1342	*/
<>	134:ad3be0349dc5	1343
<>	134:ad3be0349dc5	1344	/** @defgroup SPI_LL_EF_DATA_Management DATA Management
<>	134:ad3be0349dc5	1345	* @{
<>	134:ad3be0349dc5	1346	*/
<>	134:ad3be0349dc5	1347
<>	134:ad3be0349dc5	1348	/**
<>	134:ad3be0349dc5	1349	* @brief Read 8-Bits in the data register
<>	134:ad3be0349dc5	1350	* @rmtoll DR DR LL_SPI_ReceiveData8
<>	134:ad3be0349dc5	1351	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1352	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
<>	134:ad3be0349dc5	1353	*/
<>	134:ad3be0349dc5	1354	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1355	{
<>	134:ad3be0349dc5	1356	return (uint8_t)(READ_REG(SPIx->DR));
<>	134:ad3be0349dc5	1357	}
<>	134:ad3be0349dc5	1358
<>	134:ad3be0349dc5	1359	/**
<>	134:ad3be0349dc5	1360	* @brief Read 16-Bits in the data register
<>	134:ad3be0349dc5	1361	* @rmtoll DR DR LL_SPI_ReceiveData16
<>	134:ad3be0349dc5	1362	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1363	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
<>	134:ad3be0349dc5	1364	*/
<>	134:ad3be0349dc5	1365	__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1366	{
<>	134:ad3be0349dc5	1367	return (uint16_t)(READ_REG(SPIx->DR));
<>	134:ad3be0349dc5	1368	}
<>	134:ad3be0349dc5	1369
<>	134:ad3be0349dc5	1370	/**
<>	134:ad3be0349dc5	1371	* @brief Write 8-Bits in the data register
<>	134:ad3be0349dc5	1372	* @rmtoll DR DR LL_SPI_TransmitData8
<>	134:ad3be0349dc5	1373	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1374	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
<>	134:ad3be0349dc5	1375	* @retval None
<>	134:ad3be0349dc5	1376	*/
<>	134:ad3be0349dc5	1377	__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
<>	134:ad3be0349dc5	1378	{
<>	134:ad3be0349dc5	1379	((__IO uint8_t )&SPIx->DR) = TxData;
<>	134:ad3be0349dc5	1380	}
<>	134:ad3be0349dc5	1381
<>	134:ad3be0349dc5	1382	/**
<>	134:ad3be0349dc5	1383	* @brief Write 16-Bits in the data register
<>	134:ad3be0349dc5	1384	* @rmtoll DR DR LL_SPI_TransmitData16
<>	134:ad3be0349dc5	1385	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1386	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
<>	134:ad3be0349dc5	1387	* @retval None
<>	134:ad3be0349dc5	1388	*/
<>	134:ad3be0349dc5	1389	__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
<>	134:ad3be0349dc5	1390	{
<>	134:ad3be0349dc5	1391	((__IO uint16_t )&SPIx->DR) = TxData;
<>	134:ad3be0349dc5	1392	}
<>	134:ad3be0349dc5	1393
<>	134:ad3be0349dc5	1394	/**
<>	134:ad3be0349dc5	1395	* @}
<>	134:ad3be0349dc5	1396	*/
<>	134:ad3be0349dc5	1397	#if defined(USE_FULL_LL_DRIVER)
<>	134:ad3be0349dc5	1398	/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
<>	134:ad3be0349dc5	1399	* @{
<>	134:ad3be0349dc5	1400	*/
<>	134:ad3be0349dc5	1401
<>	134:ad3be0349dc5	1402	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
<>	134:ad3be0349dc5	1403	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct);
<>	134:ad3be0349dc5	1404	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
<>	134:ad3be0349dc5	1405
<>	134:ad3be0349dc5	1406	/**
<>	134:ad3be0349dc5	1407	* @}
<>	134:ad3be0349dc5	1408	*/
<>	134:ad3be0349dc5	1409	#endif /* USE_FULL_LL_DRIVER */
<>	134:ad3be0349dc5	1410	/**
<>	134:ad3be0349dc5	1411	* @}
<>	134:ad3be0349dc5	1412	*/
<>	134:ad3be0349dc5	1413
<>	134:ad3be0349dc5	1414	/**
<>	134:ad3be0349dc5	1415	* @}
<>	134:ad3be0349dc5	1416	*/
<>	134:ad3be0349dc5	1417
<>	134:ad3be0349dc5	1418	#if defined(SPI_I2S_SUPPORT)
<>	134:ad3be0349dc5	1419	/** @defgroup I2S_LL I2S
<>	134:ad3be0349dc5	1420	* @{
<>	134:ad3be0349dc5	1421	*/
<>	134:ad3be0349dc5	1422
<>	134:ad3be0349dc5	1423	/* Private variables ---------------------------------------------------------*/
<>	134:ad3be0349dc5	1424	/* Private constants ---------------------------------------------------------*/
<>	134:ad3be0349dc5	1425	/* Private macros ------------------------------------------------------------*/
<>	134:ad3be0349dc5	1426
<>	134:ad3be0349dc5	1427	/* Exported types ------------------------------------------------------------*/
<>	134:ad3be0349dc5	1428	#if defined(USE_FULL_LL_DRIVER)
<>	134:ad3be0349dc5	1429	/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
<>	134:ad3be0349dc5	1430	* @{
<>	134:ad3be0349dc5	1431	*/
<>	134:ad3be0349dc5	1432
<>	134:ad3be0349dc5	1433	/**
<>	134:ad3be0349dc5	1434	* @brief I2S Init structure definition
<>	134:ad3be0349dc5	1435	*/
<>	134:ad3be0349dc5	1436
<>	134:ad3be0349dc5	1437	typedef struct
<>	134:ad3be0349dc5	1438	{
<>	134:ad3be0349dc5	1439	uint32_t Mode; /*!< Specifies the I2S operating mode.
<>	134:ad3be0349dc5	1440	This parameter can be a value of @ref I2S_LL_EC_MODE
<>	134:ad3be0349dc5	1441
<>	134:ad3be0349dc5	1442	This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
<>	134:ad3be0349dc5	1443
<>	134:ad3be0349dc5	1444	uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
<>	134:ad3be0349dc5	1445	This parameter can be a value of @ref I2S_LL_EC_STANDARD
<>	134:ad3be0349dc5	1446
<>	134:ad3be0349dc5	1447	This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
<>	134:ad3be0349dc5	1448
<>	134:ad3be0349dc5	1449
<>	134:ad3be0349dc5	1450	uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
<>	134:ad3be0349dc5	1451	This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
<>	134:ad3be0349dc5	1452
<>	134:ad3be0349dc5	1453	This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
<>	134:ad3be0349dc5	1454
<>	134:ad3be0349dc5	1455
<>	134:ad3be0349dc5	1456	uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
<>	134:ad3be0349dc5	1457	This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
<>	134:ad3be0349dc5	1458
<>	134:ad3be0349dc5	1459	This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
<>	134:ad3be0349dc5	1460
<>	134:ad3be0349dc5	1461
<>	134:ad3be0349dc5	1462	uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
<>	134:ad3be0349dc5	1463	This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
<>	134:ad3be0349dc5	1464
<>	134:ad3be0349dc5	1465	Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
<>	134:ad3be0349dc5	1466	and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
<>	134:ad3be0349dc5	1467
<>	134:ad3be0349dc5	1468
<>	134:ad3be0349dc5	1469	uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
<>	134:ad3be0349dc5	1470	This parameter can be a value of @ref I2S_LL_EC_POLARITY
<>	134:ad3be0349dc5	1471
<>	134:ad3be0349dc5	1472	This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
<>	134:ad3be0349dc5	1473
<>	134:ad3be0349dc5	1474	} LL_I2S_InitTypeDef;
<>	134:ad3be0349dc5	1475
<>	134:ad3be0349dc5	1476	/**
<>	134:ad3be0349dc5	1477	* @}
<>	134:ad3be0349dc5	1478	*/
<>	134:ad3be0349dc5	1479	#endif /USE_FULL_LL_DRIVER/
<>	134:ad3be0349dc5	1480
<>	134:ad3be0349dc5	1481	/* Exported constants --------------------------------------------------------*/
<>	134:ad3be0349dc5	1482	/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
<>	134:ad3be0349dc5	1483	* @{
<>	134:ad3be0349dc5	1484	*/
<>	134:ad3be0349dc5	1485
<>	134:ad3be0349dc5	1486	/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
<>	134:ad3be0349dc5	1487	* @brief Flags defines which can be used with LL_I2S_ReadReg function
<>	134:ad3be0349dc5	1488	* @{
<>	134:ad3be0349dc5	1489	*/
<>	134:ad3be0349dc5	1490	#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /!< Rx buffer not empty flag /
<>	134:ad3be0349dc5	1491	#define LL_I2S_SR_TXE LL_SPI_SR_TXE /!< Tx buffer empty flag /
<>	134:ad3be0349dc5	1492	#define LL_I2S_SR_BSY LL_SPI_SR_BSY /!< Busy flag /
<>	134:ad3be0349dc5	1493	#define LL_I2S_SR_UDR LL_SPI_SR_UDR /!< Underrun flag /
<>	134:ad3be0349dc5	1494	#define LL_I2S_SR_OVR LL_SPI_SR_OVR /!< Overrun flag /
<>	134:ad3be0349dc5	1495	#define LL_I2S_SR_FRE LL_SPI_SR_FRE /!< TI mode frame format error flag /
<>	134:ad3be0349dc5	1496	/**
<>	134:ad3be0349dc5	1497	* @}
<>	134:ad3be0349dc5	1498	*/
<>	134:ad3be0349dc5	1499
<>	134:ad3be0349dc5	1500	/** @defgroup SPI_LL_EC_IT IT Defines
<>	134:ad3be0349dc5	1501	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
<>	134:ad3be0349dc5	1502	* @{
<>	134:ad3be0349dc5	1503	*/
<>	134:ad3be0349dc5	1504	#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
<>	134:ad3be0349dc5	1505	#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
<>	134:ad3be0349dc5	1506	#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /!< Error interrupt enable /
<>	134:ad3be0349dc5	1507	/**
<>	134:ad3be0349dc5	1508	* @}
<>	134:ad3be0349dc5	1509	*/
<>	134:ad3be0349dc5	1510
<>	134:ad3be0349dc5	1511	/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
<>	134:ad3be0349dc5	1512	* @{
<>	134:ad3be0349dc5	1513	*/
<>	134:ad3be0349dc5	1514	#define LL_I2S_DATAFORMAT_16B ((uint32_t)0x00000000U) /!< Data length 16 bits, Channel lenght 16bit /
<>	134:ad3be0349dc5	1515	#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /!< Data length 16 bits, Channel lenght 32bit /
<>	134:ad3be0349dc5	1516	#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_0) /!< Data length 24 bits, Channel lenght 32bit /
<>	134:ad3be0349dc5	1517	#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_1) /!< Data length 16 bits, Channel lenght 32bit /
<>	134:ad3be0349dc5	1518	/**
<>	134:ad3be0349dc5	1519	* @}
<>	134:ad3be0349dc5	1520	*/
<>	134:ad3be0349dc5	1521
<>	134:ad3be0349dc5	1522	/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
<>	134:ad3be0349dc5	1523	* @{
<>	134:ad3be0349dc5	1524	*/
<>	134:ad3be0349dc5	1525	#define LL_I2S_POLARITY_LOW ((uint32_t)0x00000000U) /!< Clock steady state is low level /
<>	134:ad3be0349dc5	1526	#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /!< Clock steady state is high level /
<>	134:ad3be0349dc5	1527	/**
<>	134:ad3be0349dc5	1528	* @}
<>	134:ad3be0349dc5	1529	*/
<>	134:ad3be0349dc5	1530
<>	134:ad3be0349dc5	1531	/** @defgroup I2S_LL_EC_STANDARD I2s Standard
<>	134:ad3be0349dc5	1532	* @{
<>	134:ad3be0349dc5	1533	*/
<>	134:ad3be0349dc5	1534	#define LL_I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U) /!< I2S standard philips /
<>	134:ad3be0349dc5	1535	#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /!< MSB justified standard (left justified) /
<>	134:ad3be0349dc5	1536	#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /!< LSB justified standard (right justified) /
<>	134:ad3be0349dc5	1537	#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1) /!< PCM standard, short frame synchronization /
<>	134:ad3be0349dc5	1538	#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1 \| SPI_I2SCFGR_PCMSYNC) /!< PCM standard, long frame synchronization /
<>	134:ad3be0349dc5	1539	/**
<>	134:ad3be0349dc5	1540	* @}
<>	134:ad3be0349dc5	1541	*/
<>	134:ad3be0349dc5	1542
<>	134:ad3be0349dc5	1543	/** @defgroup I2S_LL_EC_MODE Operation Mode
<>	134:ad3be0349dc5	1544	* @{
<>	134:ad3be0349dc5	1545	*/
<>	134:ad3be0349dc5	1546	#define LL_I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U) /!< Slave Tx configuration /
<>	134:ad3be0349dc5	1547	#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /!< Slave Rx configuration /
<>	134:ad3be0349dc5	1548	#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /!< Master Tx configuration /
<>	134:ad3be0349dc5	1549	#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 \| SPI_I2SCFGR_I2SCFG_1) /!< Master Rx configuration /
<>	134:ad3be0349dc5	1550	/**
<>	134:ad3be0349dc5	1551	* @}
<>	134:ad3be0349dc5	1552	*/
<>	134:ad3be0349dc5	1553
<>	134:ad3be0349dc5	1554	/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
<>	134:ad3be0349dc5	1555	* @{
<>	134:ad3be0349dc5	1556	*/
<>	134:ad3be0349dc5	1557	#define LL_I2S_PRESCALER_PARITY_EVEN ((uint32_t)0x00000000U) /!< Odd factor: Real divider value is = I2SDIV 2 */
<>	134:ad3be0349dc5	1558	#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /!< Odd factor: Real divider value is = (I2SDIV 2)+1 */
<>	134:ad3be0349dc5	1559	/**
<>	134:ad3be0349dc5	1560	* @}
<>	134:ad3be0349dc5	1561	*/
<>	134:ad3be0349dc5	1562
<>	134:ad3be0349dc5	1563	#if defined(USE_FULL_LL_DRIVER)
<>	134:ad3be0349dc5	1564
<>	134:ad3be0349dc5	1565	/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
<>	134:ad3be0349dc5	1566	* @{
<>	134:ad3be0349dc5	1567	*/
<>	134:ad3be0349dc5	1568	#define LL_I2S_MCLK_OUTPUT_DISABLE ((uint32_t)0x00000000U) /!< Master clock output is disabled /
<>	134:ad3be0349dc5	1569	#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /!< Master clock output is enabled /
<>	134:ad3be0349dc5	1570	/**
<>	134:ad3be0349dc5	1571	* @}
<>	134:ad3be0349dc5	1572	*/
<>	134:ad3be0349dc5	1573
<>	134:ad3be0349dc5	1574	/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
<>	134:ad3be0349dc5	1575	* @{
<>	134:ad3be0349dc5	1576	*/
<>	134:ad3be0349dc5	1577
<>	134:ad3be0349dc5	1578	#define LL_I2S_AUDIOFREQ_192K ((uint32_t)192000) /!< Audio Frequency configuration 192000 Hz /
<>	134:ad3be0349dc5	1579	#define LL_I2S_AUDIOFREQ_96K ((uint32_t) 96000) /!< Audio Frequency configuration 96000 Hz /
<>	134:ad3be0349dc5	1580	#define LL_I2S_AUDIOFREQ_48K ((uint32_t) 48000) /!< Audio Frequency configuration 48000 Hz /
<>	134:ad3be0349dc5	1581	#define LL_I2S_AUDIOFREQ_44K ((uint32_t) 44100) /!< Audio Frequency configuration 44100 Hz /
<>	134:ad3be0349dc5	1582	#define LL_I2S_AUDIOFREQ_32K ((uint32_t) 32000) /!< Audio Frequency configuration 32000 Hz /
<>	134:ad3be0349dc5	1583	#define LL_I2S_AUDIOFREQ_22K ((uint32_t) 22050) /!< Audio Frequency configuration 22050 Hz /
<>	134:ad3be0349dc5	1584	#define LL_I2S_AUDIOFREQ_16K ((uint32_t) 16000) /!< Audio Frequency configuration 16000 Hz /
<>	134:ad3be0349dc5	1585	#define LL_I2S_AUDIOFREQ_11K ((uint32_t) 11025) /!< Audio Frequency configuration 11025 Hz /
<>	134:ad3be0349dc5	1586	#define LL_I2S_AUDIOFREQ_8K ((uint32_t) 8000) /!< Audio Frequency configuration 8000 Hz /
<>	134:ad3be0349dc5	1587	#define LL_I2S_AUDIOFREQ_DEFAULT ((uint32_t) 2) /!< Audio Freq not specified. Register I2SDIV = 2 /
<>	134:ad3be0349dc5	1588	/**
<>	134:ad3be0349dc5	1589	* @}
<>	134:ad3be0349dc5	1590	*/
<>	134:ad3be0349dc5	1591	#endif /* USE_FULL_LL_DRIVER */
<>	134:ad3be0349dc5	1592
<>	134:ad3be0349dc5	1593	/**
<>	134:ad3be0349dc5	1594	* @}
<>	134:ad3be0349dc5	1595	*/
<>	134:ad3be0349dc5	1596
<>	134:ad3be0349dc5	1597	/* Exported macro ------------------------------------------------------------*/
<>	134:ad3be0349dc5	1598	/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
<>	134:ad3be0349dc5	1599	* @{
<>	134:ad3be0349dc5	1600	*/
<>	134:ad3be0349dc5	1601
<>	134:ad3be0349dc5	1602	/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
<>	134:ad3be0349dc5	1603	* @{
<>	134:ad3be0349dc5	1604	*/
<>	134:ad3be0349dc5	1605
<>	134:ad3be0349dc5	1606	/**
<>	134:ad3be0349dc5	1607	* @brief Write a value in I2S register
<>	134:ad3be0349dc5	1608	* @param __INSTANCE__ I2S Instance
<>	134:ad3be0349dc5	1609	* @param __REG__ Register to be written
<>	134:ad3be0349dc5	1610	* @param __VALUE__ Value to be written in the register
<>	134:ad3be0349dc5	1611	* @retval None
<>	134:ad3be0349dc5	1612	*/
<>	134:ad3be0349dc5	1613	#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	134:ad3be0349dc5	1614
<>	134:ad3be0349dc5	1615	/**
<>	134:ad3be0349dc5	1616	* @brief Read a value in I2S register
<>	134:ad3be0349dc5	1617	* @param __INSTANCE__ I2S Instance
<>	134:ad3be0349dc5	1618	* @param __REG__ Register to be read
<>	134:ad3be0349dc5	1619	* @retval Register value
<>	134:ad3be0349dc5	1620	*/
<>	134:ad3be0349dc5	1621	#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	134:ad3be0349dc5	1622	/**
<>	134:ad3be0349dc5	1623	* @}
<>	134:ad3be0349dc5	1624	*/
<>	134:ad3be0349dc5	1625
<>	134:ad3be0349dc5	1626	/**
<>	134:ad3be0349dc5	1627	* @}
<>	134:ad3be0349dc5	1628	*/
<>	134:ad3be0349dc5	1629
<>	134:ad3be0349dc5	1630
<>	134:ad3be0349dc5	1631	/* Exported functions --------------------------------------------------------*/
<>	134:ad3be0349dc5	1632
<>	134:ad3be0349dc5	1633	/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
<>	134:ad3be0349dc5	1634	* @{
<>	134:ad3be0349dc5	1635	*/
<>	134:ad3be0349dc5	1636
<>	134:ad3be0349dc5	1637	/** @defgroup I2S_LL_EF_Configuration Configuration
<>	134:ad3be0349dc5	1638	* @{
<>	134:ad3be0349dc5	1639	*/
<>	134:ad3be0349dc5	1640
<>	134:ad3be0349dc5	1641	/**
<>	134:ad3be0349dc5	1642	* @brief Select I2S mode and Enable I2S peripheral
<>	134:ad3be0349dc5	1643	* @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
<>	134:ad3be0349dc5	1644	* I2SCFGR I2SE LL_I2S_Enable
<>	134:ad3be0349dc5	1645	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1646	* @retval None
<>	134:ad3be0349dc5	1647	*/
<>	134:ad3be0349dc5	1648	__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1649	{
<>	134:ad3be0349dc5	1650	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
<>	134:ad3be0349dc5	1651	}
<>	134:ad3be0349dc5	1652
<>	134:ad3be0349dc5	1653	/**
<>	134:ad3be0349dc5	1654	* @brief Disable I2S peripheral
<>	134:ad3be0349dc5	1655	* @rmtoll I2SCFGR I2SE LL_I2S_Disable
<>	134:ad3be0349dc5	1656	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1657	* @retval None
<>	134:ad3be0349dc5	1658	*/
<>	134:ad3be0349dc5	1659	__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1660	{
<>	134:ad3be0349dc5	1661	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
<>	134:ad3be0349dc5	1662	}
<>	134:ad3be0349dc5	1663
<>	134:ad3be0349dc5	1664	/**
<>	134:ad3be0349dc5	1665	* @brief Check if I2S peripheral is enabled
<>	134:ad3be0349dc5	1666	* @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
<>	134:ad3be0349dc5	1667	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1668	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1669	*/
<>	134:ad3be0349dc5	1670	__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1671	{
<>	134:ad3be0349dc5	1672	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
<>	134:ad3be0349dc5	1673	}
<>	134:ad3be0349dc5	1674
<>	134:ad3be0349dc5	1675	/**
<>	134:ad3be0349dc5	1676	* @brief Set I2S data frame length
<>	134:ad3be0349dc5	1677	* @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
<>	134:ad3be0349dc5	1678	* I2SCFGR CHLEN LL_I2S_SetDataFormat
<>	134:ad3be0349dc5	1679	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1680	* @param DataFormat This parameter can be one of the following values:
<>	134:ad3be0349dc5	1681	* @arg @ref LL_I2S_DATAFORMAT_16B
<>	134:ad3be0349dc5	1682	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
<>	134:ad3be0349dc5	1683	* @arg @ref LL_I2S_DATAFORMAT_24B
<>	134:ad3be0349dc5	1684	* @arg @ref LL_I2S_DATAFORMAT_32B
<>	134:ad3be0349dc5	1685	* @retval None
<>	134:ad3be0349dc5	1686	*/
<>	134:ad3be0349dc5	1687	__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
<>	134:ad3be0349dc5	1688	{
<>	134:ad3be0349dc5	1689	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN, DataFormat);
<>	134:ad3be0349dc5	1690	}
<>	134:ad3be0349dc5	1691
<>	134:ad3be0349dc5	1692	/**
<>	134:ad3be0349dc5	1693	* @brief Get I2S data frame length
<>	134:ad3be0349dc5	1694	* @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
<>	134:ad3be0349dc5	1695	* I2SCFGR CHLEN LL_I2S_GetDataFormat
<>	134:ad3be0349dc5	1696	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1697	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	1698	* @arg @ref LL_I2S_DATAFORMAT_16B
<>	134:ad3be0349dc5	1699	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
<>	134:ad3be0349dc5	1700	* @arg @ref LL_I2S_DATAFORMAT_24B
<>	134:ad3be0349dc5	1701	* @arg @ref LL_I2S_DATAFORMAT_32B
<>	134:ad3be0349dc5	1702	*/
<>	134:ad3be0349dc5	1703	__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1704	{
<>	134:ad3be0349dc5	1705	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN));
<>	134:ad3be0349dc5	1706	}
<>	134:ad3be0349dc5	1707
<>	134:ad3be0349dc5	1708	/**
<>	134:ad3be0349dc5	1709	* @brief Set I2S clock polarity
<>	134:ad3be0349dc5	1710	* @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
<>	134:ad3be0349dc5	1711	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1712	* @param ClockPolarity This parameter can be one of the following values:
<>	134:ad3be0349dc5	1713	* @arg @ref LL_I2S_POLARITY_LOW
<>	134:ad3be0349dc5	1714	* @arg @ref LL_I2S_POLARITY_HIGH
<>	134:ad3be0349dc5	1715	* @retval None
<>	134:ad3be0349dc5	1716	*/
<>	134:ad3be0349dc5	1717	__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
<>	134:ad3be0349dc5	1718	{
<>	134:ad3be0349dc5	1719	SET_BIT(SPIx->I2SCFGR, ClockPolarity);
<>	134:ad3be0349dc5	1720	}
<>	134:ad3be0349dc5	1721
<>	134:ad3be0349dc5	1722	/**
<>	134:ad3be0349dc5	1723	* @brief Get I2S clock polarity
<>	134:ad3be0349dc5	1724	* @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
<>	134:ad3be0349dc5	1725	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1726	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	1727	* @arg @ref LL_I2S_POLARITY_LOW
<>	134:ad3be0349dc5	1728	* @arg @ref LL_I2S_POLARITY_HIGH
<>	134:ad3be0349dc5	1729	*/
<>	134:ad3be0349dc5	1730	__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1731	{
<>	134:ad3be0349dc5	1732	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
<>	134:ad3be0349dc5	1733	}
<>	134:ad3be0349dc5	1734
<>	134:ad3be0349dc5	1735	/**
<>	134:ad3be0349dc5	1736	* @brief Set I2S standard protocol
<>	134:ad3be0349dc5	1737	* @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
<>	134:ad3be0349dc5	1738	* I2SCFGR PCMSYNC LL_I2S_SetStandard
<>	134:ad3be0349dc5	1739	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1740	* @param Standard This parameter can be one of the following values:
<>	134:ad3be0349dc5	1741	* @arg @ref LL_I2S_STANDARD_PHILIPS
<>	134:ad3be0349dc5	1742	* @arg @ref LL_I2S_STANDARD_MSB
<>	134:ad3be0349dc5	1743	* @arg @ref LL_I2S_STANDARD_LSB
<>	134:ad3be0349dc5	1744	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
<>	134:ad3be0349dc5	1745	* @arg @ref LL_I2S_STANDARD_PCM_LONG
<>	134:ad3be0349dc5	1746	* @retval None
<>	134:ad3be0349dc5	1747	*/
<>	134:ad3be0349dc5	1748	__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
<>	134:ad3be0349dc5	1749	{
<>	134:ad3be0349dc5	1750	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC, Standard);
<>	134:ad3be0349dc5	1751	}
<>	134:ad3be0349dc5	1752
<>	134:ad3be0349dc5	1753	/**
<>	134:ad3be0349dc5	1754	* @brief Get I2S standard protocol
<>	134:ad3be0349dc5	1755	* @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
<>	134:ad3be0349dc5	1756	* I2SCFGR PCMSYNC LL_I2S_GetStandard
<>	134:ad3be0349dc5	1757	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1758	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	1759	* @arg @ref LL_I2S_STANDARD_PHILIPS
<>	134:ad3be0349dc5	1760	* @arg @ref LL_I2S_STANDARD_MSB
<>	134:ad3be0349dc5	1761	* @arg @ref LL_I2S_STANDARD_LSB
<>	134:ad3be0349dc5	1762	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
<>	134:ad3be0349dc5	1763	* @arg @ref LL_I2S_STANDARD_PCM_LONG
<>	134:ad3be0349dc5	1764	*/
<>	134:ad3be0349dc5	1765	__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1766	{
<>	134:ad3be0349dc5	1767	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC));
<>	134:ad3be0349dc5	1768	}
<>	134:ad3be0349dc5	1769
<>	134:ad3be0349dc5	1770	/**
<>	134:ad3be0349dc5	1771	* @brief Set I2S transfer mode
<>	134:ad3be0349dc5	1772	* @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
<>	134:ad3be0349dc5	1773	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1774	* @param Mode This parameter can be one of the following values:
<>	134:ad3be0349dc5	1775	* @arg @ref LL_I2S_MODE_SLAVE_TX
<>	134:ad3be0349dc5	1776	* @arg @ref LL_I2S_MODE_SLAVE_RX
<>	134:ad3be0349dc5	1777	* @arg @ref LL_I2S_MODE_MASTER_TX
<>	134:ad3be0349dc5	1778	* @arg @ref LL_I2S_MODE_MASTER_RX
<>	134:ad3be0349dc5	1779	* @retval None
<>	134:ad3be0349dc5	1780	*/
<>	134:ad3be0349dc5	1781	__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
<>	134:ad3be0349dc5	1782	{
<>	134:ad3be0349dc5	1783	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
<>	134:ad3be0349dc5	1784	}
<>	134:ad3be0349dc5	1785
<>	134:ad3be0349dc5	1786	/**
<>	134:ad3be0349dc5	1787	* @brief Get I2S transfer mode
<>	134:ad3be0349dc5	1788	* @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
<>	134:ad3be0349dc5	1789	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1790	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	1791	* @arg @ref LL_I2S_MODE_SLAVE_TX
<>	134:ad3be0349dc5	1792	* @arg @ref LL_I2S_MODE_SLAVE_RX
<>	134:ad3be0349dc5	1793	* @arg @ref LL_I2S_MODE_MASTER_TX
<>	134:ad3be0349dc5	1794	* @arg @ref LL_I2S_MODE_MASTER_RX
<>	134:ad3be0349dc5	1795	*/
<>	134:ad3be0349dc5	1796	__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1797	{
<>	134:ad3be0349dc5	1798	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
<>	134:ad3be0349dc5	1799	}
<>	134:ad3be0349dc5	1800
<>	134:ad3be0349dc5	1801	/**
<>	134:ad3be0349dc5	1802	* @brief Set I2S linear prescaler
<>	134:ad3be0349dc5	1803	* @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
<>	134:ad3be0349dc5	1804	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1805	* @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
<>	134:ad3be0349dc5	1806	* @retval None
<>	134:ad3be0349dc5	1807	*/
<>	134:ad3be0349dc5	1808	__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
<>	134:ad3be0349dc5	1809	{
<>	134:ad3be0349dc5	1810	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
<>	134:ad3be0349dc5	1811	}
<>	134:ad3be0349dc5	1812
<>	134:ad3be0349dc5	1813	/**
<>	134:ad3be0349dc5	1814	* @brief Get I2S linear prescaler
<>	134:ad3be0349dc5	1815	* @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
<>	134:ad3be0349dc5	1816	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1817	* @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
<>	134:ad3be0349dc5	1818	*/
<>	134:ad3be0349dc5	1819	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1820	{
<>	134:ad3be0349dc5	1821	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
<>	134:ad3be0349dc5	1822	}
<>	134:ad3be0349dc5	1823
<>	134:ad3be0349dc5	1824	/**
<>	134:ad3be0349dc5	1825	* @brief Set I2S parity prescaler
<>	134:ad3be0349dc5	1826	* @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
<>	134:ad3be0349dc5	1827	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1828	* @param PrescalerParity This parameter can be one of the following values:
<>	134:ad3be0349dc5	1829	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
<>	134:ad3be0349dc5	1830	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
<>	134:ad3be0349dc5	1831	* @retval None
<>	134:ad3be0349dc5	1832	*/
<>	134:ad3be0349dc5	1833	__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
<>	134:ad3be0349dc5	1834	{
<>	134:ad3be0349dc5	1835	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
<>	134:ad3be0349dc5	1836	}
<>	134:ad3be0349dc5	1837
<>	134:ad3be0349dc5	1838	/**
<>	134:ad3be0349dc5	1839	* @brief Get I2S parity prescaler
<>	134:ad3be0349dc5	1840	* @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
<>	134:ad3be0349dc5	1841	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1842	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	1843	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
<>	134:ad3be0349dc5	1844	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
<>	134:ad3be0349dc5	1845	*/
<>	134:ad3be0349dc5	1846	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1847	{
<>	134:ad3be0349dc5	1848	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
<>	134:ad3be0349dc5	1849	}
<>	134:ad3be0349dc5	1850
<>	134:ad3be0349dc5	1851	/**
<>	134:ad3be0349dc5	1852	* @brief Enable the master clock ouput (Pin MCK)
<>	134:ad3be0349dc5	1853	* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
<>	134:ad3be0349dc5	1854	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1855	* @retval None
<>	134:ad3be0349dc5	1856	*/
<>	134:ad3be0349dc5	1857	__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1858	{
<>	134:ad3be0349dc5	1859	SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
<>	134:ad3be0349dc5	1860	}
<>	134:ad3be0349dc5	1861
<>	134:ad3be0349dc5	1862	/**
<>	134:ad3be0349dc5	1863	* @brief Disable the master clock ouput (Pin MCK)
<>	134:ad3be0349dc5	1864	* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
<>	134:ad3be0349dc5	1865	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1866	* @retval None
<>	134:ad3be0349dc5	1867	*/
<>	134:ad3be0349dc5	1868	__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1869	{
<>	134:ad3be0349dc5	1870	CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
<>	134:ad3be0349dc5	1871	}
<>	134:ad3be0349dc5	1872
<>	134:ad3be0349dc5	1873	/**
<>	134:ad3be0349dc5	1874	* @brief Check if the master clock ouput (Pin MCK) is enabled
<>	134:ad3be0349dc5	1875	* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
<>	134:ad3be0349dc5	1876	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1877	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1878	*/
<>	134:ad3be0349dc5	1879	__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1880	{
<>	134:ad3be0349dc5	1881	return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
<>	134:ad3be0349dc5	1882	}
<>	134:ad3be0349dc5	1883
<>	134:ad3be0349dc5	1884	#if defined(SPI_I2SCFGR_ASTRTEN)
<>	134:ad3be0349dc5	1885	/**
<>	134:ad3be0349dc5	1886	* @brief Enable asynchronous start
<>	134:ad3be0349dc5	1887	* @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
<>	134:ad3be0349dc5	1888	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1889	* @retval None
<>	134:ad3be0349dc5	1890	*/
<>	134:ad3be0349dc5	1891	__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1892	{
<>	134:ad3be0349dc5	1893	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
<>	134:ad3be0349dc5	1894	}
<>	134:ad3be0349dc5	1895
<>	134:ad3be0349dc5	1896	/**
<>	134:ad3be0349dc5	1897	* @brief Disable asynchronous start
<>	134:ad3be0349dc5	1898	* @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
<>	134:ad3be0349dc5	1899	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1900	* @retval None
<>	134:ad3be0349dc5	1901	*/
<>	134:ad3be0349dc5	1902	__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1903	{
<>	134:ad3be0349dc5	1904	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
<>	134:ad3be0349dc5	1905	}
<>	134:ad3be0349dc5	1906
<>	134:ad3be0349dc5	1907	/**
<>	134:ad3be0349dc5	1908	* @brief Check if asynchronous start is enabled
<>	134:ad3be0349dc5	1909	* @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
<>	134:ad3be0349dc5	1910	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1911	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1912	*/
<>	134:ad3be0349dc5	1913	__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1914	{
<>	134:ad3be0349dc5	1915	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN));
<>	134:ad3be0349dc5	1916	}
<>	134:ad3be0349dc5	1917	#endif /* SPI_I2SCFGR_ASTRTEN */
<>	134:ad3be0349dc5	1918
<>	134:ad3be0349dc5	1919	/**
<>	134:ad3be0349dc5	1920	* @}
<>	134:ad3be0349dc5	1921	*/
<>	134:ad3be0349dc5	1922
<>	134:ad3be0349dc5	1923	/** @defgroup I2S_LL_EF_FLAG FLAG Management
<>	134:ad3be0349dc5	1924	* @{
<>	134:ad3be0349dc5	1925	*/
<>	134:ad3be0349dc5	1926
<>	134:ad3be0349dc5	1927	/**
<>	134:ad3be0349dc5	1928	* @brief Check if Rx buffer is not empty
<>	134:ad3be0349dc5	1929	* @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
<>	134:ad3be0349dc5	1930	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1931	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1932	*/
<>	134:ad3be0349dc5	1933	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1934	{
<>	134:ad3be0349dc5	1935	return LL_SPI_IsActiveFlag_RXNE(SPIx);
<>	134:ad3be0349dc5	1936	}
<>	134:ad3be0349dc5	1937
<>	134:ad3be0349dc5	1938	/**
<>	134:ad3be0349dc5	1939	* @brief Check if Tx buffer is empty
<>	134:ad3be0349dc5	1940	* @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
<>	134:ad3be0349dc5	1941	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1942	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1943	*/
<>	134:ad3be0349dc5	1944	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1945	{
<>	134:ad3be0349dc5	1946	return LL_SPI_IsActiveFlag_TXE(SPIx);
<>	134:ad3be0349dc5	1947	}
<>	134:ad3be0349dc5	1948
<>	134:ad3be0349dc5	1949	/**
<>	134:ad3be0349dc5	1950	* @brief Get busy flag
<>	134:ad3be0349dc5	1951	* @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
<>	134:ad3be0349dc5	1952	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1953	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1954	*/
<>	134:ad3be0349dc5	1955	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1956	{
<>	134:ad3be0349dc5	1957	return LL_SPI_IsActiveFlag_BSY(SPIx);
<>	134:ad3be0349dc5	1958	}
<>	134:ad3be0349dc5	1959
<>	134:ad3be0349dc5	1960	/**
<>	134:ad3be0349dc5	1961	* @brief Get overrun error flag
<>	134:ad3be0349dc5	1962	* @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
<>	134:ad3be0349dc5	1963	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1964	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1965	*/
<>	134:ad3be0349dc5	1966	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1967	{
<>	134:ad3be0349dc5	1968	return LL_SPI_IsActiveFlag_OVR(SPIx);
<>	134:ad3be0349dc5	1969	}
<>	134:ad3be0349dc5	1970
<>	134:ad3be0349dc5	1971	/**
<>	134:ad3be0349dc5	1972	* @brief Get underrun error flag
<>	134:ad3be0349dc5	1973	* @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
<>	134:ad3be0349dc5	1974	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1975	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1976	*/
<>	134:ad3be0349dc5	1977	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1978	{
<>	134:ad3be0349dc5	1979	return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
<>	134:ad3be0349dc5	1980	}
<>	134:ad3be0349dc5	1981
<>	134:ad3be0349dc5	1982	/**
<>	134:ad3be0349dc5	1983	* @brief Get frame format error flag
<>	134:ad3be0349dc5	1984	* @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
<>	134:ad3be0349dc5	1985	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	1986	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1987	*/
<>	134:ad3be0349dc5	1988	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	1989	{
<>	134:ad3be0349dc5	1990	return LL_SPI_IsActiveFlag_FRE(SPIx);
<>	134:ad3be0349dc5	1991	}
<>	134:ad3be0349dc5	1992
<>	134:ad3be0349dc5	1993	/**
<>	134:ad3be0349dc5	1994	* @brief Get channel side flag.
<>	134:ad3be0349dc5	1995	* @note 0: Channel Left has to be transmitted or has been received\n
<>	134:ad3be0349dc5	1996	* 1: Channel Right has to be transmitted or has been received\n
<>	134:ad3be0349dc5	1997	* It has no significance in PCM mode.
<>	134:ad3be0349dc5	1998	* @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
<>	134:ad3be0349dc5	1999	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	2000	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	2001	*/
<>	134:ad3be0349dc5	2002	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	2003	{
<>	134:ad3be0349dc5	2004	return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
<>	134:ad3be0349dc5	2005	}
<>	134:ad3be0349dc5	2006
<>	134:ad3be0349dc5	2007	/**
<>	134:ad3be0349dc5	2008	* @brief Clear overrun error flag
<>	134:ad3be0349dc5	2009	* @rmtoll SR OVR LL_I2S_ClearFlag_OVR
<>	134:ad3be0349dc5	2010	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	2011	* @retval None
<>	134:ad3be0349dc5	2012	*/
<>	134:ad3be0349dc5	2013	__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	2014	{
<>	134:ad3be0349dc5	2015	LL_SPI_ClearFlag_OVR(SPIx);
<>	134:ad3be0349dc5	2016	}
<>	134:ad3be0349dc5	2017
<>	134:ad3be0349dc5	2018	/**
<>	134:ad3be0349dc5	2019	* @brief Clear underrun error flag
<>	134:ad3be0349dc5	2020	* @rmtoll SR UDR LL_I2S_ClearFlag_UDR
<>	134:ad3be0349dc5	2021	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	2022	* @retval None
<>	134:ad3be0349dc5	2023	*/
<>	134:ad3be0349dc5	2024	__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	2025	{
<>	134:ad3be0349dc5	2026	__IO uint32_t tmpreg;
<>	134:ad3be0349dc5	2027	tmpreg = SPIx->SR;
<>	134:ad3be0349dc5	2028	(void)tmpreg;
<>	134:ad3be0349dc5	2029	}
<>	134:ad3be0349dc5	2030
<>	134:ad3be0349dc5	2031	/**
<>	134:ad3be0349dc5	2032	* @brief Clear frame format error flag
<>	134:ad3be0349dc5	2033	* @rmtoll SR FRE LL_I2S_ClearFlag_FRE
<>	134:ad3be0349dc5	2034	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	2035	* @retval None
<>	134:ad3be0349dc5	2036	*/
<>	134:ad3be0349dc5	2037	__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	2038	{
<>	134:ad3be0349dc5	2039	LL_SPI_ClearFlag_FRE(SPIx);
<>	134:ad3be0349dc5	2040	}
<>	134:ad3be0349dc5	2041
<>	134:ad3be0349dc5	2042	/**
<>	134:ad3be0349dc5	2043	* @}
<>	134:ad3be0349dc5	2044	*/
<>	134:ad3be0349dc5	2045
<>	134:ad3be0349dc5	2046	/** @defgroup I2S_LL_EF_IT Interrupt Management
<>	134:ad3be0349dc5	2047	* @{
<>	134:ad3be0349dc5	2048	*/
<>	134:ad3be0349dc5	2049
<>	134:ad3be0349dc5	2050	/**
<>	134:ad3be0349dc5	2051	* @brief Enable error IT
<>	134:ad3be0349dc5	2052	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
<>	134:ad3be0349dc5	2053	* @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
<>	134:ad3be0349dc5	2054	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	2055	* @retval None
<>	134:ad3be0349dc5	2056	*/
<>	134:ad3be0349dc5	2057	__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	2058	{
<>	134:ad3be0349dc5	2059	LL_SPI_EnableIT_ERR(SPIx);
<>	134:ad3be0349dc5	2060	}
<>	134:ad3be0349dc5	2061
<>	134:ad3be0349dc5	2062	/**
<>	134:ad3be0349dc5	2063	* @brief Enable Rx buffer not empty IT
<>	134:ad3be0349dc5	2064	* @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
<>	134:ad3be0349dc5	2065	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	2066	* @retval None
<>	134:ad3be0349dc5	2067	*/
<>	134:ad3be0349dc5	2068	__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	2069	{
<>	134:ad3be0349dc5	2070	LL_SPI_EnableIT_RXNE(SPIx);
<>	134:ad3be0349dc5	2071	}
<>	134:ad3be0349dc5	2072
<>	134:ad3be0349dc5	2073	/**
<>	134:ad3be0349dc5	2074	* @brief Enable Tx buffer empty IT
<>	134:ad3be0349dc5	2075	* @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
<>	134:ad3be0349dc5	2076	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	2077	* @retval None
<>	134:ad3be0349dc5	2078	*/
<>	134:ad3be0349dc5	2079	__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	2080	{
<>	134:ad3be0349dc5	2081	LL_SPI_EnableIT_TXE(SPIx);
<>	134:ad3be0349dc5	2082	}
<>	134:ad3be0349dc5	2083
<>	134:ad3be0349dc5	2084	/**
<>	134:ad3be0349dc5	2085	* @brief Disable error IT
<>	134:ad3be0349dc5	2086	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
<>	134:ad3be0349dc5	2087	* @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
<>	134:ad3be0349dc5	2088	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	2089	* @retval None
<>	134:ad3be0349dc5	2090	*/
<>	134:ad3be0349dc5	2091	__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	2092	{
<>	134:ad3be0349dc5	2093	LL_SPI_DisableIT_ERR(SPIx);
<>	134:ad3be0349dc5	2094	}
<>	134:ad3be0349dc5	2095
<>	134:ad3be0349dc5	2096	/**
<>	134:ad3be0349dc5	2097	* @brief Disable Rx buffer not empty IT
<>	134:ad3be0349dc5	2098	* @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
<>	134:ad3be0349dc5	2099	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	2100	* @retval None
<>	134:ad3be0349dc5	2101	*/
<>	134:ad3be0349dc5	2102	__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	2103	{
<>	134:ad3be0349dc5	2104	LL_SPI_DisableIT_RXNE(SPIx);
<>	134:ad3be0349dc5	2105	}
<>	134:ad3be0349dc5	2106
<>	134:ad3be0349dc5	2107	/**
<>	134:ad3be0349dc5	2108	* @brief Disable Tx buffer empty IT
<>	134:ad3be0349dc5	2109	* @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
<>	134:ad3be0349dc5	2110	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	2111	* @retval None
<>	134:ad3be0349dc5	2112	*/
<>	134:ad3be0349dc5	2113	__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	2114	{
<>	134:ad3be0349dc5	2115	LL_SPI_DisableIT_TXE(SPIx);
<>	134:ad3be0349dc5	2116	}
<>	134:ad3be0349dc5	2117
<>	134:ad3be0349dc5	2118	/**
<>	134:ad3be0349dc5	2119	* @brief Check if ERR IT is enabled
<>	134:ad3be0349dc5	2120	* @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
<>	134:ad3be0349dc5	2121	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	2122	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	2123	*/
<>	134:ad3be0349dc5	2124	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	2125	{
<>	134:ad3be0349dc5	2126	return LL_SPI_IsEnabledIT_ERR(SPIx);
<>	134:ad3be0349dc5	2127	}
<>	134:ad3be0349dc5	2128
<>	134:ad3be0349dc5	2129	/**
<>	134:ad3be0349dc5	2130	* @brief Check if RXNE IT is enabled
<>	134:ad3be0349dc5	2131	* @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
<>	134:ad3be0349dc5	2132	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	2133	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	2134	*/
<>	134:ad3be0349dc5	2135	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	2136	{
<>	134:ad3be0349dc5	2137	return LL_SPI_IsEnabledIT_RXNE(SPIx);
<>	134:ad3be0349dc5	2138	}
<>	134:ad3be0349dc5	2139
<>	134:ad3be0349dc5	2140	/**
<>	134:ad3be0349dc5	2141	* @brief Check if TXE IT is enabled
<>	134:ad3be0349dc5	2142	* @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
<>	134:ad3be0349dc5	2143	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	2144	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	2145	*/
<>	134:ad3be0349dc5	2146	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	2147	{
<>	134:ad3be0349dc5	2148	return LL_SPI_IsEnabledIT_TXE(SPIx);
<>	134:ad3be0349dc5	2149	}
<>	134:ad3be0349dc5	2150
<>	134:ad3be0349dc5	2151	/**
<>	134:ad3be0349dc5	2152	* @}
<>	134:ad3be0349dc5	2153	*/
<>	134:ad3be0349dc5	2154
<>	134:ad3be0349dc5	2155	/** @defgroup I2S_LL_EF_DMA DMA Management
<>	134:ad3be0349dc5	2156	* @{
<>	134:ad3be0349dc5	2157	*/
<>	134:ad3be0349dc5	2158
<>	134:ad3be0349dc5	2159	/**
<>	134:ad3be0349dc5	2160	* @brief Enable DMA Rx
<>	134:ad3be0349dc5	2161	* @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
<>	134:ad3be0349dc5	2162	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	2163	* @retval None
<>	134:ad3be0349dc5	2164	*/
<>	134:ad3be0349dc5	2165	__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	2166	{
<>	134:ad3be0349dc5	2167	LL_SPI_EnableDMAReq_RX(SPIx);
<>	134:ad3be0349dc5	2168	}
<>	134:ad3be0349dc5	2169
<>	134:ad3be0349dc5	2170	/**
<>	134:ad3be0349dc5	2171	* @brief Disable DMA Rx
<>	134:ad3be0349dc5	2172	* @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
<>	134:ad3be0349dc5	2173	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	2174	* @retval None
<>	134:ad3be0349dc5	2175	*/
<>	134:ad3be0349dc5	2176	__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	2177	{
<>	134:ad3be0349dc5	2178	LL_SPI_DisableDMAReq_RX(SPIx);
<>	134:ad3be0349dc5	2179	}
<>	134:ad3be0349dc5	2180
<>	134:ad3be0349dc5	2181	/**
<>	134:ad3be0349dc5	2182	* @brief Check if DMA Rx is enabled
<>	134:ad3be0349dc5	2183	* @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
<>	134:ad3be0349dc5	2184	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	2185	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	2186	*/
<>	134:ad3be0349dc5	2187	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	2188	{
<>	134:ad3be0349dc5	2189	return LL_SPI_IsEnabledDMAReq_RX(SPIx);
<>	134:ad3be0349dc5	2190	}
<>	134:ad3be0349dc5	2191
<>	134:ad3be0349dc5	2192	/**
<>	134:ad3be0349dc5	2193	* @brief Enable DMA Tx
<>	134:ad3be0349dc5	2194	* @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
<>	134:ad3be0349dc5	2195	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	2196	* @retval None
<>	134:ad3be0349dc5	2197	*/
<>	134:ad3be0349dc5	2198	__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	2199	{
<>	134:ad3be0349dc5	2200	LL_SPI_EnableDMAReq_TX(SPIx);
<>	134:ad3be0349dc5	2201	}
<>	134:ad3be0349dc5	2202
<>	134:ad3be0349dc5	2203	/**
<>	134:ad3be0349dc5	2204	* @brief Disable DMA Tx
<>	134:ad3be0349dc5	2205	* @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
<>	134:ad3be0349dc5	2206	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	2207	* @retval None
<>	134:ad3be0349dc5	2208	*/
<>	134:ad3be0349dc5	2209	__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	2210	{
<>	134:ad3be0349dc5	2211	LL_SPI_DisableDMAReq_TX(SPIx);
<>	134:ad3be0349dc5	2212	}
<>	134:ad3be0349dc5	2213
<>	134:ad3be0349dc5	2214	/**
<>	134:ad3be0349dc5	2215	* @brief Check if DMA Tx is enabled
<>	134:ad3be0349dc5	2216	* @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
<>	134:ad3be0349dc5	2217	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	2218	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	2219	*/
<>	134:ad3be0349dc5	2220	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	2221	{
<>	134:ad3be0349dc5	2222	return LL_SPI_IsEnabledDMAReq_TX(SPIx);
<>	134:ad3be0349dc5	2223	}
<>	134:ad3be0349dc5	2224
<>	134:ad3be0349dc5	2225	/**
<>	134:ad3be0349dc5	2226	* @}
<>	134:ad3be0349dc5	2227	*/
<>	134:ad3be0349dc5	2228
<>	134:ad3be0349dc5	2229	/** @defgroup I2S_LL_EF_DATA DATA Management
<>	134:ad3be0349dc5	2230	* @{
<>	134:ad3be0349dc5	2231	*/
<>	134:ad3be0349dc5	2232
<>	134:ad3be0349dc5	2233	/**
<>	134:ad3be0349dc5	2234	* @brief Read 16-Bits in data register
<>	134:ad3be0349dc5	2235	* @rmtoll DR DR LL_I2S_ReceiveData16
<>	134:ad3be0349dc5	2236	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	2237	* @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
<>	134:ad3be0349dc5	2238	*/
<>	134:ad3be0349dc5	2239	__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
<>	134:ad3be0349dc5	2240	{
<>	134:ad3be0349dc5	2241	return LL_SPI_ReceiveData16(SPIx);
<>	134:ad3be0349dc5	2242	}
<>	134:ad3be0349dc5	2243
<>	134:ad3be0349dc5	2244	/**
<>	134:ad3be0349dc5	2245	* @brief Write 16-Bits in data register
<>	134:ad3be0349dc5	2246	* @rmtoll DR DR LL_I2S_TransmitData16
<>	134:ad3be0349dc5	2247	* @param SPIx SPI Instance
<>	134:ad3be0349dc5	2248	* @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
<>	134:ad3be0349dc5	2249	* @retval None
<>	134:ad3be0349dc5	2250	*/
<>	134:ad3be0349dc5	2251	__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
<>	134:ad3be0349dc5	2252	{
<>	134:ad3be0349dc5	2253	LL_SPI_TransmitData16(SPIx, TxData);
<>	134:ad3be0349dc5	2254	}
<>	134:ad3be0349dc5	2255
<>	134:ad3be0349dc5	2256	/**
<>	134:ad3be0349dc5	2257	* @}
<>	134:ad3be0349dc5	2258	*/
<>	134:ad3be0349dc5	2259
<>	134:ad3be0349dc5	2260	#if defined(USE_FULL_LL_DRIVER)
<>	134:ad3be0349dc5	2261	/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
<>	134:ad3be0349dc5	2262	* @{
<>	134:ad3be0349dc5	2263	*/
<>	134:ad3be0349dc5	2264
<>	134:ad3be0349dc5	2265	ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
<>	134:ad3be0349dc5	2266	ErrorStatus LL_I2S_Init(SPI_TypeDef SPIx, LL_I2S_InitTypeDef I2S_InitStruct);
<>	134:ad3be0349dc5	2267	void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
<>	134:ad3be0349dc5	2268	void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
<>	134:ad3be0349dc5	2269
<>	134:ad3be0349dc5	2270	/**
<>	134:ad3be0349dc5	2271	* @}
<>	134:ad3be0349dc5	2272	*/
<>	134:ad3be0349dc5	2273	#endif /* USE_FULL_LL_DRIVER */
<>	134:ad3be0349dc5	2274
<>	134:ad3be0349dc5	2275	/**
<>	134:ad3be0349dc5	2276	* @}
<>	134:ad3be0349dc5	2277	*/
<>	134:ad3be0349dc5	2278
<>	134:ad3be0349dc5	2279	/**
<>	134:ad3be0349dc5	2280	* @}
<>	134:ad3be0349dc5	2281	*/
<>	134:ad3be0349dc5	2282	#endif /* SPI_I2S_SUPPORT */
<>	134:ad3be0349dc5	2283
<>	134:ad3be0349dc5	2284	#endif /* defined (SPI1) \|\| defined (SPI2) */
<>	134:ad3be0349dc5	2285
<>	134:ad3be0349dc5	2286	/**
<>	134:ad3be0349dc5	2287	* @}
<>	134:ad3be0349dc5	2288	*/
<>	134:ad3be0349dc5	2289
<>	134:ad3be0349dc5	2290	#ifdef __cplusplus
<>	134:ad3be0349dc5	2291	}
<>	134:ad3be0349dc5	2292	#endif
<>	134:ad3be0349dc5	2293
<>	134:ad3be0349dc5	2294	#endif /* __STM32F0xx_LL_SPI_H */
<>	134:ad3be0349dc5	2295
<>	134:ad3be0349dc5	2296	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/