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TARGET_NUCLEO_F030R8/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_pwr.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
134:ad3be0349dc5
Child:
160:5571c4ff569f
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 134:ad3be0349dc5 1 /**
<> 134:ad3be0349dc5 2 ******************************************************************************
<> 134:ad3be0349dc5 3 * @file stm32f0xx_ll_pwr.h
<> 134:ad3be0349dc5 4 * @author MCD Application Team
<> 134:ad3be0349dc5 5 * @version V1.4.0
<> 134:ad3be0349dc5 6 * @date 27-May-2016
<> 134:ad3be0349dc5 7 * @brief Header file of PWR LL module.
<> 134:ad3be0349dc5 8 ******************************************************************************
<> 134:ad3be0349dc5 9 * @attention
<> 134:ad3be0349dc5 10 *
<> 134:ad3be0349dc5 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 134:ad3be0349dc5 12 *
<> 134:ad3be0349dc5 13 * Redistribution and use in source and binary forms, with or without modification,
<> 134:ad3be0349dc5 14 * are permitted provided that the following conditions are met:
<> 134:ad3be0349dc5 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 134:ad3be0349dc5 16 * this list of conditions and the following disclaimer.
<> 134:ad3be0349dc5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 134:ad3be0349dc5 18 * this list of conditions and the following disclaimer in the documentation
<> 134:ad3be0349dc5 19 * and/or other materials provided with the distribution.
<> 134:ad3be0349dc5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 134:ad3be0349dc5 21 * may be used to endorse or promote products derived from this software
<> 134:ad3be0349dc5 22 * without specific prior written permission.
<> 134:ad3be0349dc5 23 *
<> 134:ad3be0349dc5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 134:ad3be0349dc5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 134:ad3be0349dc5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 134:ad3be0349dc5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 134:ad3be0349dc5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 134:ad3be0349dc5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 134:ad3be0349dc5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 134:ad3be0349dc5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 134:ad3be0349dc5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 134:ad3be0349dc5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 134:ad3be0349dc5 34 *
<> 134:ad3be0349dc5 35 ******************************************************************************
<> 134:ad3be0349dc5 36 */
<> 134:ad3be0349dc5 37
<> 134:ad3be0349dc5 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 134:ad3be0349dc5 39 #ifndef __STM32F0xx_LL_PWR_H
<> 134:ad3be0349dc5 40 #define __STM32F0xx_LL_PWR_H
<> 134:ad3be0349dc5 41
<> 134:ad3be0349dc5 42 #ifdef __cplusplus
<> 134:ad3be0349dc5 43 extern "C" {
<> 134:ad3be0349dc5 44 #endif
<> 134:ad3be0349dc5 45
<> 134:ad3be0349dc5 46 /* Includes ------------------------------------------------------------------*/
<> 134:ad3be0349dc5 47 #include "stm32f0xx.h"
<> 134:ad3be0349dc5 48
<> 134:ad3be0349dc5 49 /** @addtogroup STM32F0xx_LL_Driver
<> 134:ad3be0349dc5 50 * @{
<> 134:ad3be0349dc5 51 */
<> 134:ad3be0349dc5 52
<> 134:ad3be0349dc5 53 #if defined(PWR)
<> 134:ad3be0349dc5 54
<> 134:ad3be0349dc5 55 /** @defgroup PWR_LL PWR
<> 134:ad3be0349dc5 56 * @{
<> 134:ad3be0349dc5 57 */
<> 134:ad3be0349dc5 58
<> 134:ad3be0349dc5 59 /* Private types -------------------------------------------------------------*/
<> 134:ad3be0349dc5 60 /* Private variables ---------------------------------------------------------*/
<> 134:ad3be0349dc5 61
<> 134:ad3be0349dc5 62 /* Private constants ---------------------------------------------------------*/
<> 134:ad3be0349dc5 63
<> 134:ad3be0349dc5 64 /* Private macros ------------------------------------------------------------*/
<> 134:ad3be0349dc5 65
<> 134:ad3be0349dc5 66 /* Exported types ------------------------------------------------------------*/
<> 134:ad3be0349dc5 67 /* Exported constants --------------------------------------------------------*/
<> 134:ad3be0349dc5 68 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
<> 134:ad3be0349dc5 69 * @{
<> 134:ad3be0349dc5 70 */
<> 134:ad3be0349dc5 71
<> 134:ad3be0349dc5 72 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
<> 134:ad3be0349dc5 73 * @brief Flags defines which can be used with LL_PWR_WriteReg function
<> 134:ad3be0349dc5 74 * @{
<> 134:ad3be0349dc5 75 */
<> 134:ad3be0349dc5 76 #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
<> 134:ad3be0349dc5 77 #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
<> 134:ad3be0349dc5 78 /**
<> 134:ad3be0349dc5 79 * @}
<> 134:ad3be0349dc5 80 */
<> 134:ad3be0349dc5 81
<> 134:ad3be0349dc5 82 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
<> 134:ad3be0349dc5 83 * @brief Flags defines which can be used with LL_PWR_ReadReg function
<> 134:ad3be0349dc5 84 * @{
<> 134:ad3be0349dc5 85 */
<> 134:ad3be0349dc5 86 #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
<> 134:ad3be0349dc5 87 #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
<> 134:ad3be0349dc5 88 #if defined (PWR_PVD_SUPPORT)
<> 134:ad3be0349dc5 89 #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
<> 134:ad3be0349dc5 90 #endif
<> 134:ad3be0349dc5 91 #if defined (PWR_CSR_VREFINTRDYF)
<> 134:ad3be0349dc5 92 #define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */
<> 134:ad3be0349dc5 93 #endif
<> 134:ad3be0349dc5 94 #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */
<> 134:ad3be0349dc5 95 #define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */
<> 134:ad3be0349dc5 96 #if defined (PWR_CSR_EWUP3)
<> 134:ad3be0349dc5 97 #define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */
<> 134:ad3be0349dc5 98 #endif /* PWR_CSR_EWUP3 */
<> 134:ad3be0349dc5 99 #if defined (PWR_CSR_EWUP4)
<> 134:ad3be0349dc5 100 #define LL_PWR_CSR_EWUP4 PWR_CSR_EWUP4 /*!< Enable WKUP pin 4 */
<> 134:ad3be0349dc5 101 #endif /* PWR_CSR_EWUP4 */
<> 134:ad3be0349dc5 102 #if defined (PWR_CSR_EWUP5)
<> 134:ad3be0349dc5 103 #define LL_PWR_CSR_EWUP5 PWR_CSR_EWUP5 /*!< Enable WKUP pin 5 */
<> 134:ad3be0349dc5 104 #endif /* PWR_CSR_EWUP5 */
<> 134:ad3be0349dc5 105 #if defined (PWR_CSR_EWUP6)
<> 134:ad3be0349dc5 106 #define LL_PWR_CSR_EWUP6 PWR_CSR_EWUP6 /*!< Enable WKUP pin 6 */
<> 134:ad3be0349dc5 107 #endif /* PWR_CSR_EWUP6 */
<> 134:ad3be0349dc5 108 #if defined (PWR_CSR_EWUP7)
<> 134:ad3be0349dc5 109 #define LL_PWR_CSR_EWUP7 PWR_CSR_EWUP7 /*!< Enable WKUP pin 7 */
<> 134:ad3be0349dc5 110 #endif /* PWR_CSR_EWUP7 */
<> 134:ad3be0349dc5 111 #if defined (PWR_CSR_EWUP8)
<> 134:ad3be0349dc5 112 #define LL_PWR_CSR_EWUP8 PWR_CSR_EWUP8 /*!< Enable WKUP pin 8 */
<> 134:ad3be0349dc5 113 #endif /* PWR_CSR_EWUP8 */
<> 134:ad3be0349dc5 114 /**
<> 134:ad3be0349dc5 115 * @}
<> 134:ad3be0349dc5 116 */
<> 134:ad3be0349dc5 117
<> 134:ad3be0349dc5 118
<> 134:ad3be0349dc5 119 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
<> 134:ad3be0349dc5 120 * @{
<> 134:ad3be0349dc5 121 */
<> 134:ad3be0349dc5 122 #define LL_PWR_MODE_STOP_MAINREGU ((uint32_t)0x00000000U) /*!< Enter Stop mode when the CPU enters deepsleep */
<> 134:ad3be0349dc5 123 #define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (ith low power regulator ON) when the CPU enters deepsleep */
<> 134:ad3be0349dc5 124 #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
<> 134:ad3be0349dc5 125 /**
<> 134:ad3be0349dc5 126 * @}
<> 134:ad3be0349dc5 127 */
<> 134:ad3be0349dc5 128
<> 134:ad3be0349dc5 129 #if defined(PWR_CR_LPDS)
<> 134:ad3be0349dc5 130 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
<> 134:ad3be0349dc5 131 * @{
<> 134:ad3be0349dc5 132 */
<> 134:ad3be0349dc5 133 #define LL_PWR_REGU_DSMODE_MAIN ((uint32_t)0x00000000U) /*!< Voltage regulator in main mode during deepsleep mode */
<> 134:ad3be0349dc5 134 #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage regulator in low-power mode during deepsleep mode */
<> 134:ad3be0349dc5 135 /**
<> 134:ad3be0349dc5 136 * @}
<> 134:ad3be0349dc5 137 */
<> 134:ad3be0349dc5 138 #endif /* PWR_CR_LPDS */
<> 134:ad3be0349dc5 139
<> 134:ad3be0349dc5 140 #if defined (PWR_PVD_SUPPORT)
<> 134:ad3be0349dc5 141 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
<> 134:ad3be0349dc5 142 * @{
<> 134:ad3be0349dc5 143 */
<> 134:ad3be0349dc5 144 #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold 0 */
<> 134:ad3be0349dc5 145 #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold 1 */
<> 134:ad3be0349dc5 146 #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold 2 */
<> 134:ad3be0349dc5 147 #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold 3 */
<> 134:ad3be0349dc5 148 #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold 4 */
<> 134:ad3be0349dc5 149 #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold 5 */
<> 134:ad3be0349dc5 150 #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold 6 */
<> 134:ad3be0349dc5 151 #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold 7 */
<> 134:ad3be0349dc5 152 /**
<> 134:ad3be0349dc5 153 * @}
<> 134:ad3be0349dc5 154 */
<> 134:ad3be0349dc5 155 #endif
<> 134:ad3be0349dc5 156
<> 134:ad3be0349dc5 157 /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
<> 134:ad3be0349dc5 158 * @{
<> 134:ad3be0349dc5 159 */
<> 134:ad3be0349dc5 160 #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */
<> 134:ad3be0349dc5 161 #define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */
<> 134:ad3be0349dc5 162 #if defined (PWR_CSR_EWUP3)
<> 134:ad3be0349dc5 163 #define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */
<> 134:ad3be0349dc5 164 #endif /* PWR_CSR_EWUP3 */
<> 134:ad3be0349dc5 165 #if defined (PWR_CSR_EWUP4)
<> 134:ad3be0349dc5 166 #define LL_PWR_WAKEUP_PIN4 (PWR_CSR_EWUP4) /*!< WKUP pin 4 : LLG TBD */
<> 134:ad3be0349dc5 167 #endif /* PWR_CSR_EWUP4 */
<> 134:ad3be0349dc5 168 #if defined (PWR_CSR_EWUP5)
<> 134:ad3be0349dc5 169 #define LL_PWR_WAKEUP_PIN5 (PWR_CSR_EWUP5) /*!< WKUP pin 5 : LLG TBD */
<> 134:ad3be0349dc5 170 #endif /* PWR_CSR_EWUP5 */
<> 134:ad3be0349dc5 171 #if defined (PWR_CSR_EWUP6)
<> 134:ad3be0349dc5 172 #define LL_PWR_WAKEUP_PIN6 (PWR_CSR_EWUP6) /*!< WKUP pin 6 : LLG TBD */
<> 134:ad3be0349dc5 173 #endif /* PWR_CSR_EWUP6 */
<> 134:ad3be0349dc5 174 #if defined (PWR_CSR_EWUP7)
<> 134:ad3be0349dc5 175 #define LL_PWR_WAKEUP_PIN7 (PWR_CSR_EWUP7) /*!< WKUP pin 7 : LLG TBD */
<> 134:ad3be0349dc5 176 #endif /* PWR_CSR_EWUP7 */
<> 134:ad3be0349dc5 177 #if defined (PWR_CSR_EWUP8)
<> 134:ad3be0349dc5 178 #define LL_PWR_WAKEUP_PIN8 (PWR_CSR_EWUP8) /*!< WKUP pin 8 : LLG TBD */
<> 134:ad3be0349dc5 179 #endif /* PWR_CSR_EWUP8 */
<> 134:ad3be0349dc5 180 /**
<> 134:ad3be0349dc5 181 * @}
<> 134:ad3be0349dc5 182 */
<> 134:ad3be0349dc5 183
<> 134:ad3be0349dc5 184 /**
<> 134:ad3be0349dc5 185 * @}
<> 134:ad3be0349dc5 186 */
<> 134:ad3be0349dc5 187
<> 134:ad3be0349dc5 188
<> 134:ad3be0349dc5 189 /* Exported macro ------------------------------------------------------------*/
<> 134:ad3be0349dc5 190 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
<> 134:ad3be0349dc5 191 * @{
<> 134:ad3be0349dc5 192 */
<> 134:ad3be0349dc5 193
<> 134:ad3be0349dc5 194 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
<> 134:ad3be0349dc5 195 * @{
<> 134:ad3be0349dc5 196 */
<> 134:ad3be0349dc5 197
<> 134:ad3be0349dc5 198 /**
<> 134:ad3be0349dc5 199 * @brief Write a value in PWR register
<> 134:ad3be0349dc5 200 * @param __REG__ Register to be written
<> 134:ad3be0349dc5 201 * @param __VALUE__ Value to be written in the register
<> 134:ad3be0349dc5 202 * @retval None
<> 134:ad3be0349dc5 203 */
<> 134:ad3be0349dc5 204 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
<> 134:ad3be0349dc5 205
<> 134:ad3be0349dc5 206 /**
<> 134:ad3be0349dc5 207 * @brief Read a value in PWR register
<> 134:ad3be0349dc5 208 * @param __REG__ Register to be read
<> 134:ad3be0349dc5 209 * @retval Register value
<> 134:ad3be0349dc5 210 */
<> 134:ad3be0349dc5 211 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
<> 134:ad3be0349dc5 212 /**
<> 134:ad3be0349dc5 213 * @}
<> 134:ad3be0349dc5 214 */
<> 134:ad3be0349dc5 215
<> 134:ad3be0349dc5 216 /**
<> 134:ad3be0349dc5 217 * @}
<> 134:ad3be0349dc5 218 */
<> 134:ad3be0349dc5 219
<> 134:ad3be0349dc5 220
<> 134:ad3be0349dc5 221 /* Exported functions --------------------------------------------------------*/
<> 134:ad3be0349dc5 222 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
<> 134:ad3be0349dc5 223 * @{
<> 134:ad3be0349dc5 224 */
<> 134:ad3be0349dc5 225
<> 134:ad3be0349dc5 226 /** @defgroup PWR_LL_EF_Configuration Configuration
<> 134:ad3be0349dc5 227 * @{
<> 134:ad3be0349dc5 228 */
<> 134:ad3be0349dc5 229
<> 134:ad3be0349dc5 230
<> 134:ad3be0349dc5 231 /**
<> 134:ad3be0349dc5 232 * @brief Enable access to the backup domain
<> 134:ad3be0349dc5 233 * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
<> 134:ad3be0349dc5 234 * @retval None
<> 134:ad3be0349dc5 235 */
<> 134:ad3be0349dc5 236 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
<> 134:ad3be0349dc5 237 {
<> 134:ad3be0349dc5 238 SET_BIT(PWR->CR, PWR_CR_DBP);
<> 134:ad3be0349dc5 239 }
<> 134:ad3be0349dc5 240
<> 134:ad3be0349dc5 241 /**
<> 134:ad3be0349dc5 242 * @brief Disable access to the backup domain
<> 134:ad3be0349dc5 243 * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
<> 134:ad3be0349dc5 244 * @retval None
<> 134:ad3be0349dc5 245 */
<> 134:ad3be0349dc5 246 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
<> 134:ad3be0349dc5 247 {
<> 134:ad3be0349dc5 248 CLEAR_BIT(PWR->CR, PWR_CR_DBP);
<> 134:ad3be0349dc5 249 }
<> 134:ad3be0349dc5 250
<> 134:ad3be0349dc5 251 /**
<> 134:ad3be0349dc5 252 * @brief Check if the backup domain is enabled
<> 134:ad3be0349dc5 253 * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
<> 134:ad3be0349dc5 254 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 255 */
<> 134:ad3be0349dc5 256 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
<> 134:ad3be0349dc5 257 {
<> 134:ad3be0349dc5 258 return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
<> 134:ad3be0349dc5 259 }
<> 134:ad3be0349dc5 260
<> 134:ad3be0349dc5 261 #if defined(PWR_CR_LPDS)
<> 134:ad3be0349dc5 262 /**
<> 134:ad3be0349dc5 263 * @brief Set voltage regulator mode during deep sleep mode
<> 134:ad3be0349dc5 264 * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
<> 134:ad3be0349dc5 265 * @param RegulMode This parameter can be one of the following values:
<> 134:ad3be0349dc5 266 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
<> 134:ad3be0349dc5 267 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
<> 134:ad3be0349dc5 268 * @retval None
<> 134:ad3be0349dc5 269 */
<> 134:ad3be0349dc5 270 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
<> 134:ad3be0349dc5 271 {
<> 134:ad3be0349dc5 272 MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
<> 134:ad3be0349dc5 273 }
<> 134:ad3be0349dc5 274
<> 134:ad3be0349dc5 275 /**
<> 134:ad3be0349dc5 276 * @brief Get voltage regulator mode during deep sleep mode
<> 134:ad3be0349dc5 277 * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
<> 134:ad3be0349dc5 278 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 279 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
<> 134:ad3be0349dc5 280 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
<> 134:ad3be0349dc5 281 */
<> 134:ad3be0349dc5 282 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
<> 134:ad3be0349dc5 283 {
<> 134:ad3be0349dc5 284 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
<> 134:ad3be0349dc5 285 }
<> 134:ad3be0349dc5 286 #endif /* PWR_CR_LPDS */
<> 134:ad3be0349dc5 287
<> 134:ad3be0349dc5 288 /**
<> 134:ad3be0349dc5 289 * @brief Set power down mode when CPU enters deepsleep
<> 134:ad3be0349dc5 290 * @rmtoll CR PDDS LL_PWR_SetPowerMode\n
<> 134:ad3be0349dc5 291 * CR LPDS LL_PWR_SetPowerMode
<> 134:ad3be0349dc5 292 * @param PDMode This parameter can be one of the following values:
<> 134:ad3be0349dc5 293 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
<> 134:ad3be0349dc5 294 * @arg @ref LL_PWR_MODE_STOP_LPREGU
<> 134:ad3be0349dc5 295 * @arg @ref LL_PWR_MODE_STANDBY
<> 134:ad3be0349dc5 296 * @retval None
<> 134:ad3be0349dc5 297 */
<> 134:ad3be0349dc5 298 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
<> 134:ad3be0349dc5 299 {
<> 134:ad3be0349dc5 300 MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
<> 134:ad3be0349dc5 301 }
<> 134:ad3be0349dc5 302
<> 134:ad3be0349dc5 303 /**
<> 134:ad3be0349dc5 304 * @brief Get power down mode when CPU enters deepsleep
<> 134:ad3be0349dc5 305 * @rmtoll CR PDDS LL_PWR_GetPowerMode
<> 134:ad3be0349dc5 306 * CR LPDS LL_PWR_SetPowerMode
<> 134:ad3be0349dc5 307 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 308 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
<> 134:ad3be0349dc5 309 * @arg @ref LL_PWR_MODE_STOP_LPREGU
<> 134:ad3be0349dc5 310 * @arg @ref LL_PWR_MODE_STANDBY
<> 134:ad3be0349dc5 311 */
<> 134:ad3be0349dc5 312 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
<> 134:ad3be0349dc5 313 {
<> 134:ad3be0349dc5 314 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
<> 134:ad3be0349dc5 315 }
<> 134:ad3be0349dc5 316
<> 134:ad3be0349dc5 317 #if defined (PWR_PVD_SUPPORT)
<> 134:ad3be0349dc5 318 /**
<> 134:ad3be0349dc5 319 * @brief Configure the voltage threshold detected by the Power Voltage Detector
<> 134:ad3be0349dc5 320 * @rmtoll CR PLS LL_PWR_SetPVDLevel
<> 134:ad3be0349dc5 321 * @param PVDLevel This parameter can be one of the following values:
<> 134:ad3be0349dc5 322 * @arg @ref LL_PWR_PVDLEVEL_0
<> 134:ad3be0349dc5 323 * @arg @ref LL_PWR_PVDLEVEL_1
<> 134:ad3be0349dc5 324 * @arg @ref LL_PWR_PVDLEVEL_2
<> 134:ad3be0349dc5 325 * @arg @ref LL_PWR_PVDLEVEL_3
<> 134:ad3be0349dc5 326 * @arg @ref LL_PWR_PVDLEVEL_4
<> 134:ad3be0349dc5 327 * @arg @ref LL_PWR_PVDLEVEL_5
<> 134:ad3be0349dc5 328 * @arg @ref LL_PWR_PVDLEVEL_6
<> 134:ad3be0349dc5 329 * @arg @ref LL_PWR_PVDLEVEL_7
<> 134:ad3be0349dc5 330 * @retval None
<> 134:ad3be0349dc5 331 */
<> 134:ad3be0349dc5 332 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
<> 134:ad3be0349dc5 333 {
<> 134:ad3be0349dc5 334 MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
<> 134:ad3be0349dc5 335 }
<> 134:ad3be0349dc5 336
<> 134:ad3be0349dc5 337 /**
<> 134:ad3be0349dc5 338 * @brief Get the voltage threshold detection
<> 134:ad3be0349dc5 339 * @rmtoll CR PLS LL_PWR_GetPVDLevel
<> 134:ad3be0349dc5 340 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 341 * @arg @ref LL_PWR_PVDLEVEL_0
<> 134:ad3be0349dc5 342 * @arg @ref LL_PWR_PVDLEVEL_1
<> 134:ad3be0349dc5 343 * @arg @ref LL_PWR_PVDLEVEL_2
<> 134:ad3be0349dc5 344 * @arg @ref LL_PWR_PVDLEVEL_3
<> 134:ad3be0349dc5 345 * @arg @ref LL_PWR_PVDLEVEL_4
<> 134:ad3be0349dc5 346 * @arg @ref LL_PWR_PVDLEVEL_5
<> 134:ad3be0349dc5 347 * @arg @ref LL_PWR_PVDLEVEL_6
<> 134:ad3be0349dc5 348 * @arg @ref LL_PWR_PVDLEVEL_7
<> 134:ad3be0349dc5 349 */
<> 134:ad3be0349dc5 350 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
<> 134:ad3be0349dc5 351 {
<> 134:ad3be0349dc5 352 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
<> 134:ad3be0349dc5 353 }
<> 134:ad3be0349dc5 354
<> 134:ad3be0349dc5 355 /**
<> 134:ad3be0349dc5 356 * @brief Enable Power Voltage Detector
<> 134:ad3be0349dc5 357 * @rmtoll CR PVDE LL_PWR_EnablePVD
<> 134:ad3be0349dc5 358 * @retval None
<> 134:ad3be0349dc5 359 */
<> 134:ad3be0349dc5 360 __STATIC_INLINE void LL_PWR_EnablePVD(void)
<> 134:ad3be0349dc5 361 {
<> 134:ad3be0349dc5 362 SET_BIT(PWR->CR, PWR_CR_PVDE);
<> 134:ad3be0349dc5 363 }
<> 134:ad3be0349dc5 364
<> 134:ad3be0349dc5 365 /**
<> 134:ad3be0349dc5 366 * @brief Disable Power Voltage Detector
<> 134:ad3be0349dc5 367 * @rmtoll CR PVDE LL_PWR_DisablePVD
<> 134:ad3be0349dc5 368 * @retval None
<> 134:ad3be0349dc5 369 */
<> 134:ad3be0349dc5 370 __STATIC_INLINE void LL_PWR_DisablePVD(void)
<> 134:ad3be0349dc5 371 {
<> 134:ad3be0349dc5 372 CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
<> 134:ad3be0349dc5 373 }
<> 134:ad3be0349dc5 374
<> 134:ad3be0349dc5 375 /**
<> 134:ad3be0349dc5 376 * @brief Check if Power Voltage Detector is enabled
<> 134:ad3be0349dc5 377 * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
<> 134:ad3be0349dc5 378 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 379 */
<> 134:ad3be0349dc5 380 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
<> 134:ad3be0349dc5 381 {
<> 134:ad3be0349dc5 382 return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
<> 134:ad3be0349dc5 383 }
<> 134:ad3be0349dc5 384 #endif
<> 134:ad3be0349dc5 385
<> 134:ad3be0349dc5 386 /**
<> 134:ad3be0349dc5 387 * @brief Enable the WakeUp PINx functionality
<> 134:ad3be0349dc5 388 * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n
<> 134:ad3be0349dc5 389 * CSR EWUP2 LL_PWR_EnableWakeUpPin\n
<> 134:ad3be0349dc5 390 * CSR EWUP3 LL_PWR_EnableWakeUpPin
<> 134:ad3be0349dc5 391 * @param WakeUpPin This parameter can be one of the following values:
<> 134:ad3be0349dc5 392 * @arg @ref LL_PWR_WAKEUP_PIN1
<> 134:ad3be0349dc5 393 * @arg @ref LL_PWR_WAKEUP_PIN2
<> 134:ad3be0349dc5 394 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
<> 134:ad3be0349dc5 395 * @arg @ref LL_PWR_WAKEUP_PIN4 (*)
<> 134:ad3be0349dc5 396 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
<> 134:ad3be0349dc5 397 * @arg @ref LL_PWR_WAKEUP_PIN6 (*)
<> 134:ad3be0349dc5 398 * @arg @ref LL_PWR_WAKEUP_PIN7 (*)
<> 134:ad3be0349dc5 399 * @arg @ref LL_PWR_WAKEUP_PIN8 (*)
<> 134:ad3be0349dc5 400 *
<> 134:ad3be0349dc5 401 * (*) not available on all devices
<> 134:ad3be0349dc5 402 * @retval None
<> 134:ad3be0349dc5 403 */
<> 134:ad3be0349dc5 404 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
<> 134:ad3be0349dc5 405 {
<> 134:ad3be0349dc5 406 SET_BIT(PWR->CSR, WakeUpPin);
<> 134:ad3be0349dc5 407 }
<> 134:ad3be0349dc5 408
<> 134:ad3be0349dc5 409 /**
<> 134:ad3be0349dc5 410 * @brief Disable the WakeUp PINx functionality
<> 134:ad3be0349dc5 411 * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n
<> 134:ad3be0349dc5 412 * CSR EWUP2 LL_PWR_DisableWakeUpPin\n
<> 134:ad3be0349dc5 413 * CSR EWUP3 LL_PWR_DisableWakeUpPin
<> 134:ad3be0349dc5 414 * @param WakeUpPin This parameter can be one of the following values:
<> 134:ad3be0349dc5 415 * @arg @ref LL_PWR_WAKEUP_PIN1
<> 134:ad3be0349dc5 416 * @arg @ref LL_PWR_WAKEUP_PIN2
<> 134:ad3be0349dc5 417 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
<> 134:ad3be0349dc5 418 * @arg @ref LL_PWR_WAKEUP_PIN4 (*)
<> 134:ad3be0349dc5 419 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
<> 134:ad3be0349dc5 420 * @arg @ref LL_PWR_WAKEUP_PIN6 (*)
<> 134:ad3be0349dc5 421 * @arg @ref LL_PWR_WAKEUP_PIN7 (*)
<> 134:ad3be0349dc5 422 * @arg @ref LL_PWR_WAKEUP_PIN8 (*)
<> 134:ad3be0349dc5 423 *
<> 134:ad3be0349dc5 424 * (*) not available on all devices
<> 134:ad3be0349dc5 425 * @retval None
<> 134:ad3be0349dc5 426 */
<> 134:ad3be0349dc5 427 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
<> 134:ad3be0349dc5 428 {
<> 134:ad3be0349dc5 429 CLEAR_BIT(PWR->CSR, WakeUpPin);
<> 134:ad3be0349dc5 430 }
<> 134:ad3be0349dc5 431
<> 134:ad3be0349dc5 432 /**
<> 134:ad3be0349dc5 433 * @brief Check if the WakeUp PINx functionality is enabled
<> 134:ad3be0349dc5 434 * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n
<> 134:ad3be0349dc5 435 * CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n
<> 134:ad3be0349dc5 436 * CSR EWUP3 LL_PWR_IsEnabledWakeUpPin
<> 134:ad3be0349dc5 437 * @param WakeUpPin This parameter can be one of the following values:
<> 134:ad3be0349dc5 438 * @arg @ref LL_PWR_WAKEUP_PIN1
<> 134:ad3be0349dc5 439 * @arg @ref LL_PWR_WAKEUP_PIN2
<> 134:ad3be0349dc5 440 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
<> 134:ad3be0349dc5 441 * @arg @ref LL_PWR_WAKEUP_PIN4 (*)
<> 134:ad3be0349dc5 442 * @arg @ref LL_PWR_WAKEUP_PIN5 (*)
<> 134:ad3be0349dc5 443 * @arg @ref LL_PWR_WAKEUP_PIN6 (*)
<> 134:ad3be0349dc5 444 * @arg @ref LL_PWR_WAKEUP_PIN7 (*)
<> 134:ad3be0349dc5 445 * @arg @ref LL_PWR_WAKEUP_PIN8 (*)
<> 134:ad3be0349dc5 446 *
<> 134:ad3be0349dc5 447 * (*) not available on all devices
<> 134:ad3be0349dc5 448 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 449 */
<> 134:ad3be0349dc5 450 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
<> 134:ad3be0349dc5 451 {
<> 134:ad3be0349dc5 452 return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
<> 134:ad3be0349dc5 453 }
<> 134:ad3be0349dc5 454
<> 134:ad3be0349dc5 455 /**
<> 134:ad3be0349dc5 456 * @}
<> 134:ad3be0349dc5 457 */
<> 134:ad3be0349dc5 458
<> 134:ad3be0349dc5 459 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
<> 134:ad3be0349dc5 460 * @{
<> 134:ad3be0349dc5 461 */
<> 134:ad3be0349dc5 462
<> 134:ad3be0349dc5 463 /**
<> 134:ad3be0349dc5 464 * @brief Get Wake-up Flag
<> 134:ad3be0349dc5 465 * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
<> 134:ad3be0349dc5 466 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 467 */
<> 134:ad3be0349dc5 468 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
<> 134:ad3be0349dc5 469 {
<> 134:ad3be0349dc5 470 return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
<> 134:ad3be0349dc5 471 }
<> 134:ad3be0349dc5 472
<> 134:ad3be0349dc5 473 /**
<> 134:ad3be0349dc5 474 * @brief Get Standby Flag
<> 134:ad3be0349dc5 475 * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
<> 134:ad3be0349dc5 476 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 477 */
<> 134:ad3be0349dc5 478 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
<> 134:ad3be0349dc5 479 {
<> 134:ad3be0349dc5 480 return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
<> 134:ad3be0349dc5 481 }
<> 134:ad3be0349dc5 482
<> 134:ad3be0349dc5 483 #if defined (PWR_PVD_SUPPORT)
<> 134:ad3be0349dc5 484 /**
<> 134:ad3be0349dc5 485 * @brief Indicate whether VDD voltage is below the selected PVD threshold
<> 134:ad3be0349dc5 486 * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
<> 134:ad3be0349dc5 487 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 488 */
<> 134:ad3be0349dc5 489 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
<> 134:ad3be0349dc5 490 {
<> 134:ad3be0349dc5 491 return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
<> 134:ad3be0349dc5 492 }
<> 134:ad3be0349dc5 493 #endif
<> 134:ad3be0349dc5 494
<> 134:ad3be0349dc5 495 #if defined (PWR_CSR_VREFINTRDYF)
<> 134:ad3be0349dc5 496 /**
<> 134:ad3be0349dc5 497 * @brief Get Internal Reference VrefInt Flag
<> 134:ad3be0349dc5 498 * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY
<> 134:ad3be0349dc5 499 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 500 */
<> 134:ad3be0349dc5 501 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void)
<> 134:ad3be0349dc5 502 {
<> 134:ad3be0349dc5 503 return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF));
<> 134:ad3be0349dc5 504 }
<> 134:ad3be0349dc5 505 #endif
<> 134:ad3be0349dc5 506
<> 134:ad3be0349dc5 507
<> 134:ad3be0349dc5 508
<> 134:ad3be0349dc5 509 /**
<> 134:ad3be0349dc5 510 * @brief Clear Standby Flag
<> 134:ad3be0349dc5 511 * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
<> 134:ad3be0349dc5 512 * @retval None
<> 134:ad3be0349dc5 513 */
<> 134:ad3be0349dc5 514 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
<> 134:ad3be0349dc5 515 {
<> 134:ad3be0349dc5 516 SET_BIT(PWR->CR, PWR_CR_CSBF);
<> 134:ad3be0349dc5 517 }
<> 134:ad3be0349dc5 518
<> 134:ad3be0349dc5 519 /**
<> 134:ad3be0349dc5 520 * @brief Clear Wake-up Flags
<> 134:ad3be0349dc5 521 * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
<> 134:ad3be0349dc5 522 * @retval None
<> 134:ad3be0349dc5 523 */
<> 134:ad3be0349dc5 524 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
<> 134:ad3be0349dc5 525 {
<> 134:ad3be0349dc5 526 SET_BIT(PWR->CR, PWR_CR_CWUF);
<> 134:ad3be0349dc5 527 }
<> 134:ad3be0349dc5 528
<> 134:ad3be0349dc5 529
<> 134:ad3be0349dc5 530 #if defined(USE_FULL_LL_DRIVER)
<> 134:ad3be0349dc5 531 /** @defgroup PWR_LL_EF_Init De-initialization function
<> 134:ad3be0349dc5 532 * @{
<> 134:ad3be0349dc5 533 */
<> 134:ad3be0349dc5 534 ErrorStatus LL_PWR_DeInit(void);
<> 134:ad3be0349dc5 535 /**
<> 134:ad3be0349dc5 536 * @}
<> 134:ad3be0349dc5 537 */
<> 134:ad3be0349dc5 538 #endif /* USE_FULL_LL_DRIVER */
<> 134:ad3be0349dc5 539
<> 134:ad3be0349dc5 540 /**
<> 134:ad3be0349dc5 541 * @}
<> 134:ad3be0349dc5 542 */
<> 134:ad3be0349dc5 543
<> 134:ad3be0349dc5 544 /**
<> 134:ad3be0349dc5 545 * @}
<> 134:ad3be0349dc5 546 */
<> 134:ad3be0349dc5 547
<> 134:ad3be0349dc5 548 /**
<> 134:ad3be0349dc5 549 * @}
<> 134:ad3be0349dc5 550 */
<> 134:ad3be0349dc5 551
<> 134:ad3be0349dc5 552 #endif /* defined(PWR) */
<> 134:ad3be0349dc5 553
<> 134:ad3be0349dc5 554 /**
<> 134:ad3be0349dc5 555 * @}
<> 134:ad3be0349dc5 556 */
<> 134:ad3be0349dc5 557
<> 134:ad3be0349dc5 558 #ifdef __cplusplus
<> 134:ad3be0349dc5 559 }
<> 134:ad3be0349dc5 560 #endif
<> 134:ad3be0349dc5 561
<> 134:ad3be0349dc5 562 #endif /* __STM32F0xx_LL_PWR_H */
<> 134:ad3be0349dc5 563
<> 134:ad3be0349dc5 564 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/