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TARGET_NUCLEO_F030R8/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
134:ad3be0349dc5
Child:
160:5571c4ff569f
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 134:ad3be0349dc5 1 /**
<> 134:ad3be0349dc5 2 ******************************************************************************
<> 134:ad3be0349dc5 3 * @file stm32f0xx_ll_adc.h
<> 134:ad3be0349dc5 4 * @author MCD Application Team
<> 134:ad3be0349dc5 5 * @version V1.4.0
<> 134:ad3be0349dc5 6 * @date 27-May-2016
<> 134:ad3be0349dc5 7 * @brief Header file of ADC LL module.
<> 134:ad3be0349dc5 8 ******************************************************************************
<> 134:ad3be0349dc5 9 * @attention
<> 134:ad3be0349dc5 10 *
<> 134:ad3be0349dc5 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 134:ad3be0349dc5 12 *
<> 134:ad3be0349dc5 13 * Redistribution and use in source and binary forms, with or without modification,
<> 134:ad3be0349dc5 14 * are permitted provided that the following conditions are met:
<> 134:ad3be0349dc5 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 134:ad3be0349dc5 16 * this list of conditions and the following disclaimer.
<> 134:ad3be0349dc5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 134:ad3be0349dc5 18 * this list of conditions and the following disclaimer in the documentation
<> 134:ad3be0349dc5 19 * and/or other materials provided with the distribution.
<> 134:ad3be0349dc5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 134:ad3be0349dc5 21 * may be used to endorse or promote products derived from this software
<> 134:ad3be0349dc5 22 * without specific prior written permission.
<> 134:ad3be0349dc5 23 *
<> 134:ad3be0349dc5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 134:ad3be0349dc5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 134:ad3be0349dc5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 134:ad3be0349dc5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 134:ad3be0349dc5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 134:ad3be0349dc5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 134:ad3be0349dc5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 134:ad3be0349dc5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 134:ad3be0349dc5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 134:ad3be0349dc5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 134:ad3be0349dc5 34 *
<> 134:ad3be0349dc5 35 ******************************************************************************
<> 134:ad3be0349dc5 36 */
<> 134:ad3be0349dc5 37
<> 134:ad3be0349dc5 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 134:ad3be0349dc5 39 #ifndef __STM32F0xx_LL_ADC_H
<> 134:ad3be0349dc5 40 #define __STM32F0xx_LL_ADC_H
<> 134:ad3be0349dc5 41
<> 134:ad3be0349dc5 42 #ifdef __cplusplus
<> 134:ad3be0349dc5 43 extern "C" {
<> 134:ad3be0349dc5 44 #endif
<> 134:ad3be0349dc5 45
<> 134:ad3be0349dc5 46 /* Includes ------------------------------------------------------------------*/
<> 134:ad3be0349dc5 47 #include "stm32f0xx.h"
<> 134:ad3be0349dc5 48
<> 134:ad3be0349dc5 49 /** @addtogroup STM32F0xx_LL_Driver
<> 134:ad3be0349dc5 50 * @{
<> 134:ad3be0349dc5 51 */
<> 134:ad3be0349dc5 52
<> 134:ad3be0349dc5 53 #if defined (ADC1)
<> 134:ad3be0349dc5 54
<> 134:ad3be0349dc5 55 /** @defgroup ADC_LL ADC
<> 134:ad3be0349dc5 56 * @{
<> 134:ad3be0349dc5 57 */
<> 134:ad3be0349dc5 58
<> 134:ad3be0349dc5 59 /* Private types -------------------------------------------------------------*/
<> 134:ad3be0349dc5 60 /* Private variables ---------------------------------------------------------*/
<> 134:ad3be0349dc5 61
<> 134:ad3be0349dc5 62 /* Private constants ---------------------------------------------------------*/
<> 134:ad3be0349dc5 63 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
<> 134:ad3be0349dc5 64 * @{
<> 134:ad3be0349dc5 65 */
<> 134:ad3be0349dc5 66
<> 134:ad3be0349dc5 67 /* Internal mask for ADC group regular trigger: */
<> 134:ad3be0349dc5 68 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
<> 134:ad3be0349dc5 69 /* - regular trigger source */
<> 134:ad3be0349dc5 70 /* - regular trigger edge */
<> 134:ad3be0349dc5 71 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
<> 134:ad3be0349dc5 72
<> 134:ad3be0349dc5 73 /* Mask containing trigger source masks for each of possible */
<> 134:ad3be0349dc5 74 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
<> 134:ad3be0349dc5 75 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
<> 134:ad3be0349dc5 76 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0U)) | \
<> 134:ad3be0349dc5 77 ((ADC_CFGR1_EXTSEL) << (4U * 1U)) | \
<> 134:ad3be0349dc5 78 ((ADC_CFGR1_EXTSEL) << (4U * 2U)) | \
<> 134:ad3be0349dc5 79 ((ADC_CFGR1_EXTSEL) << (4U * 3U)) )
<> 134:ad3be0349dc5 80
<> 134:ad3be0349dc5 81 /* Mask containing trigger edge masks for each of possible */
<> 134:ad3be0349dc5 82 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
<> 134:ad3be0349dc5 83 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
<> 134:ad3be0349dc5 84 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0U)) | \
<> 134:ad3be0349dc5 85 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \
<> 134:ad3be0349dc5 86 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \
<> 134:ad3be0349dc5 87 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) )
<> 134:ad3be0349dc5 88
<> 134:ad3be0349dc5 89 /* Definition of ADC group regular trigger bits information. */
<> 134:ad3be0349dc5 90 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTSEL) */
<> 134:ad3be0349dc5 91 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTEN) */
<> 134:ad3be0349dc5 92
<> 134:ad3be0349dc5 93
<> 134:ad3be0349dc5 94
<> 134:ad3be0349dc5 95 /* Internal mask for ADC channel: */
<> 134:ad3be0349dc5 96 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
<> 134:ad3be0349dc5 97 /* - channel identifier defined by number */
<> 134:ad3be0349dc5 98 /* - channel identifier defined by bitfield */
<> 134:ad3be0349dc5 99 /* - channel differentiation between external channels (connected to */
<> 134:ad3be0349dc5 100 /* GPIO pins) and internal channels (connected to internal paths) */
<> 134:ad3be0349dc5 101 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWDCH)
<> 134:ad3be0349dc5 102 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
<> 134:ad3be0349dc5 103 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t)26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
<> 134:ad3be0349dc5 104 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
<> 134:ad3be0349dc5 105 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
<> 134:ad3be0349dc5 106 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 ((uint32_t)0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
<> 134:ad3be0349dc5 107
<> 134:ad3be0349dc5 108 /* Channel differentiation between external and internal channels */
<> 134:ad3be0349dc5 109 #define ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */
<> 134:ad3be0349dc5 110 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
<> 134:ad3be0349dc5 111
<> 134:ad3be0349dc5 112 /* Definition of channels ID number information to be inserted into */
<> 134:ad3be0349dc5 113 /* channels literals definition. */
<> 134:ad3be0349dc5 114 #define ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U)
<> 134:ad3be0349dc5 115 #define ADC_CHANNEL_1_NUMBER ( ADC_CFGR1_AWDCH_0)
<> 134:ad3be0349dc5 116 #define ADC_CHANNEL_2_NUMBER ( ADC_CFGR1_AWDCH_1 )
<> 134:ad3be0349dc5 117 #define ADC_CHANNEL_3_NUMBER ( ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
<> 134:ad3be0349dc5 118 #define ADC_CHANNEL_4_NUMBER ( ADC_CFGR1_AWDCH_2 )
<> 134:ad3be0349dc5 119 #define ADC_CHANNEL_5_NUMBER ( ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_0)
<> 134:ad3be0349dc5 120 #define ADC_CHANNEL_6_NUMBER ( ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1 )
<> 134:ad3be0349dc5 121 #define ADC_CHANNEL_7_NUMBER ( ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
<> 134:ad3be0349dc5 122 #define ADC_CHANNEL_8_NUMBER ( ADC_CFGR1_AWDCH_3 )
<> 134:ad3be0349dc5 123 #define ADC_CHANNEL_9_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_0)
<> 134:ad3be0349dc5 124 #define ADC_CHANNEL_10_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_1 )
<> 134:ad3be0349dc5 125 #define ADC_CHANNEL_11_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
<> 134:ad3be0349dc5 126 #define ADC_CHANNEL_12_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2 )
<> 134:ad3be0349dc5 127 #define ADC_CHANNEL_13_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_0)
<> 134:ad3be0349dc5 128 #define ADC_CHANNEL_14_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1 )
<> 134:ad3be0349dc5 129 #define ADC_CHANNEL_15_NUMBER ( ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
<> 134:ad3be0349dc5 130 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWDCH_4 )
<> 134:ad3be0349dc5 131 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWDCH_4 | ADC_CFGR1_AWDCH_0)
<> 134:ad3be0349dc5 132 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWDCH_4 | ADC_CFGR1_AWDCH_1 )
<> 134:ad3be0349dc5 133
<> 134:ad3be0349dc5 134 /* Definition of channels ID bitfield information to be inserted into */
<> 134:ad3be0349dc5 135 /* channels literals definition. */
<> 134:ad3be0349dc5 136 #define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
<> 134:ad3be0349dc5 137 #define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
<> 134:ad3be0349dc5 138 #define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
<> 134:ad3be0349dc5 139 #define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)
<> 134:ad3be0349dc5 140 #define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)
<> 134:ad3be0349dc5 141 #define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)
<> 134:ad3be0349dc5 142 #define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)
<> 134:ad3be0349dc5 143 #define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)
<> 134:ad3be0349dc5 144 #define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)
<> 134:ad3be0349dc5 145 #define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)
<> 134:ad3be0349dc5 146 #define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)
<> 134:ad3be0349dc5 147 #define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)
<> 134:ad3be0349dc5 148 #define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)
<> 134:ad3be0349dc5 149 #define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)
<> 134:ad3be0349dc5 150 #define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)
<> 134:ad3be0349dc5 151 #define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)
<> 134:ad3be0349dc5 152 #define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)
<> 134:ad3be0349dc5 153 #define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)
<> 134:ad3be0349dc5 154 #define ADC_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18)
<> 134:ad3be0349dc5 155
<> 134:ad3be0349dc5 156 /* Internal mask for ADC analog watchdog: */
<> 134:ad3be0349dc5 157 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
<> 134:ad3be0349dc5 158 /* (concatenation of multiple bits used in different analog watchdogs, */
<> 134:ad3be0349dc5 159 /* (feature of several watchdogs not available on all STM32 families)). */
<> 134:ad3be0349dc5 160 /* - analog watchdog 1: monitored channel defined by number, */
<> 134:ad3be0349dc5 161 /* selection of ADC group (ADC group regular). */
<> 134:ad3be0349dc5 162
<> 134:ad3be0349dc5 163 /* Internal register offset for ADC analog watchdog channel configuration */
<> 134:ad3be0349dc5 164 #define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U)
<> 134:ad3be0349dc5 165
<> 134:ad3be0349dc5 166 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
<> 134:ad3be0349dc5 167
<> 134:ad3be0349dc5 168 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)
<> 134:ad3be0349dc5 169 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
<> 134:ad3be0349dc5 170
<> 134:ad3be0349dc5 171 /* Internal register offset for ADC analog watchdog threshold configuration */
<> 134:ad3be0349dc5 172 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
<> 134:ad3be0349dc5 173 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET)
<> 134:ad3be0349dc5 174
<> 134:ad3be0349dc5 175
<> 134:ad3be0349dc5 176 /* ADC registers bits positions */
<> 134:ad3be0349dc5 177 #define ADC_CFGR1_RES_BITOFFSET_POS ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_RES) */
<> 134:ad3be0349dc5 178 #define ADC_CFGR1_AWDSGL_BITOFFSET_POS ((uint32_t)22U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_AWDSGL) */
<> 134:ad3be0349dc5 179 #define ADC_TR_HT_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
<> 134:ad3be0349dc5 180 #define ADC_CHSELR_CHSEL0_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL0) */
<> 134:ad3be0349dc5 181 #define ADC_CHSELR_CHSEL1_BITOFFSET_POS ((uint32_t) 1U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL1) */
<> 134:ad3be0349dc5 182 #define ADC_CHSELR_CHSEL2_BITOFFSET_POS ((uint32_t) 2U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL2) */
<> 134:ad3be0349dc5 183 #define ADC_CHSELR_CHSEL3_BITOFFSET_POS ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL3) */
<> 134:ad3be0349dc5 184 #define ADC_CHSELR_CHSEL4_BITOFFSET_POS ((uint32_t) 4U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL4) */
<> 134:ad3be0349dc5 185 #define ADC_CHSELR_CHSEL5_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL5) */
<> 134:ad3be0349dc5 186 #define ADC_CHSELR_CHSEL6_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL6) */
<> 134:ad3be0349dc5 187 #define ADC_CHSELR_CHSEL7_BITOFFSET_POS ((uint32_t) 7U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL7) */
<> 134:ad3be0349dc5 188 #define ADC_CHSELR_CHSEL8_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL8) */
<> 134:ad3be0349dc5 189 #define ADC_CHSELR_CHSEL9_BITOFFSET_POS ((uint32_t) 9U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL9) */
<> 134:ad3be0349dc5 190 #define ADC_CHSELR_CHSEL10_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL10) */
<> 134:ad3be0349dc5 191 #define ADC_CHSELR_CHSEL11_BITOFFSET_POS ((uint32_t)11U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL11) */
<> 134:ad3be0349dc5 192 #define ADC_CHSELR_CHSEL12_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL12) */
<> 134:ad3be0349dc5 193 #define ADC_CHSELR_CHSEL13_BITOFFSET_POS ((uint32_t)13U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL13) */
<> 134:ad3be0349dc5 194 #define ADC_CHSELR_CHSEL14_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL14) */
<> 134:ad3be0349dc5 195 #define ADC_CHSELR_CHSEL15_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL15) */
<> 134:ad3be0349dc5 196 #define ADC_CHSELR_CHSEL16_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL16) */
<> 134:ad3be0349dc5 197 #define ADC_CHSELR_CHSEL17_BITOFFSET_POS ((uint32_t)17U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL17) */
<> 134:ad3be0349dc5 198 #define ADC_CHSELR_CHSEL18_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL18) */
<> 134:ad3be0349dc5 199
<> 134:ad3be0349dc5 200
<> 134:ad3be0349dc5 201 /* ADC registers bits groups */
<> 134:ad3be0349dc5 202 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
<> 134:ad3be0349dc5 203
<> 134:ad3be0349dc5 204
<> 134:ad3be0349dc5 205 /* ADC internal channels related definitions */
<> 134:ad3be0349dc5 206 /* Internal voltage reference VrefInt */
<> 134:ad3be0349dc5 207 #define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
<> 134:ad3be0349dc5 208 #define VREFINT_CAL_VREF ((uint32_t) 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
<> 134:ad3be0349dc5 209 /* Temperature sensor */
<> 134:ad3be0349dc5 210 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F0, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
<> 134:ad3be0349dc5 211 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F0, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
<> 134:ad3be0349dc5 212 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
<> 134:ad3be0349dc5 213 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
<> 134:ad3be0349dc5 214 #define TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
<> 134:ad3be0349dc5 215
<> 134:ad3be0349dc5 216
<> 134:ad3be0349dc5 217 /**
<> 134:ad3be0349dc5 218 * @}
<> 134:ad3be0349dc5 219 */
<> 134:ad3be0349dc5 220
<> 134:ad3be0349dc5 221
<> 134:ad3be0349dc5 222 #if defined(USE_FULL_LL_DRIVER)
<> 134:ad3be0349dc5 223 /* Private macros ------------------------------------------------------------*/
<> 134:ad3be0349dc5 224 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
<> 134:ad3be0349dc5 225 * @{
<> 134:ad3be0349dc5 226 */
<> 134:ad3be0349dc5 227
<> 134:ad3be0349dc5 228
<> 134:ad3be0349dc5 229 /**
<> 134:ad3be0349dc5 230 * @}
<> 134:ad3be0349dc5 231 */
<> 134:ad3be0349dc5 232
<> 134:ad3be0349dc5 233 #endif
<> 134:ad3be0349dc5 234
<> 134:ad3be0349dc5 235 /* Exported types ------------------------------------------------------------*/
<> 134:ad3be0349dc5 236 #if defined(USE_FULL_LL_DRIVER)
<> 134:ad3be0349dc5 237 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
<> 134:ad3be0349dc5 238 * @{
<> 134:ad3be0349dc5 239 */
<> 134:ad3be0349dc5 240
<> 134:ad3be0349dc5 241 /**
<> 134:ad3be0349dc5 242 * @brief Structure definition of some features of ADC instance.
<> 134:ad3be0349dc5 243 * @note These parameters have an impact on ADC scope: ADC instance.
<> 134:ad3be0349dc5 244 * Refer to corresponding unitary functions into
<> 134:ad3be0349dc5 245 * @ref ADC_LL_EF_Configuration_ADC_Instance .
<> 134:ad3be0349dc5 246 * @note The setting of these parameters by function @ref LL_ADC_Init()
<> 134:ad3be0349dc5 247 * is conditioned to ADC state:
<> 134:ad3be0349dc5 248 * ADC instance must be disabled.
<> 134:ad3be0349dc5 249 * This condition is applied to all ADC features, for efficiency
<> 134:ad3be0349dc5 250 * and compatibility over all STM32 families. However, the different
<> 134:ad3be0349dc5 251 * features can be set under different ADC state conditions
<> 134:ad3be0349dc5 252 * (setting possible with ADC enabled without conversion on going,
<> 134:ad3be0349dc5 253 * ADC enabled with conversion on going, ...)
<> 134:ad3be0349dc5 254 * Each feature can be updated afterwards with a unitary function
<> 134:ad3be0349dc5 255 * and potentially with ADC in a different state than disabled,
<> 134:ad3be0349dc5 256 * refer to description of each function for setting
<> 134:ad3be0349dc5 257 * conditioned to ADC state.
<> 134:ad3be0349dc5 258 */
<> 134:ad3be0349dc5 259 typedef struct
<> 134:ad3be0349dc5 260 {
<> 134:ad3be0349dc5 261 uint32_t Clock; /*!< Set ADC instance clock source and prescaler.
<> 134:ad3be0349dc5 262 This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE
<> 134:ad3be0349dc5 263 @note On this STM32 serie, this parameter has some clock ratio constraints:
<> 134:ad3be0349dc5 264 ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle
<> 134:ad3be0349dc5 265 (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle).
<> 134:ad3be0349dc5 266
<> 134:ad3be0349dc5 267
<> 134:ad3be0349dc5 268 This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock().
<> 134:ad3be0349dc5 269 For more details, refer to description of this function. */
<> 134:ad3be0349dc5 270
<> 134:ad3be0349dc5 271 uint32_t Resolution; /*!< Set ADC resolution.
<> 134:ad3be0349dc5 272 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
<> 134:ad3be0349dc5 273
<> 134:ad3be0349dc5 274 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
<> 134:ad3be0349dc5 275
<> 134:ad3be0349dc5 276 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
<> 134:ad3be0349dc5 277 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
<> 134:ad3be0349dc5 278
<> 134:ad3be0349dc5 279 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
<> 134:ad3be0349dc5 280
<> 134:ad3be0349dc5 281 uint32_t LowPowerMode; /*!< Set ADC low power mode.
<> 134:ad3be0349dc5 282 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
<> 134:ad3be0349dc5 283
<> 134:ad3be0349dc5 284 This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
<> 134:ad3be0349dc5 285
<> 134:ad3be0349dc5 286 } LL_ADC_InitTypeDef;
<> 134:ad3be0349dc5 287
<> 134:ad3be0349dc5 288 /**
<> 134:ad3be0349dc5 289 * @brief Structure definition of some features of ADC group regular.
<> 134:ad3be0349dc5 290 * @note These parameters have an impact on ADC scope: ADC group regular.
<> 134:ad3be0349dc5 291 * Refer to corresponding unitary functions into
<> 134:ad3be0349dc5 292 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
<> 134:ad3be0349dc5 293 * (functions with prefix "REG").
<> 134:ad3be0349dc5 294 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
<> 134:ad3be0349dc5 295 * is conditioned to ADC state:
<> 134:ad3be0349dc5 296 * ADC instance must be disabled.
<> 134:ad3be0349dc5 297 * This condition is applied to all ADC features, for efficiency
<> 134:ad3be0349dc5 298 * and compatibility over all STM32 families. However, the different
<> 134:ad3be0349dc5 299 * features can be set under different ADC state conditions
<> 134:ad3be0349dc5 300 * (setting possible with ADC enabled without conversion on going,
<> 134:ad3be0349dc5 301 * ADC enabled with conversion on going, ...)
<> 134:ad3be0349dc5 302 * Each feature can be updated afterwards with a unitary function
<> 134:ad3be0349dc5 303 * and potentially with ADC in a different state than disabled,
<> 134:ad3be0349dc5 304 * refer to description of each function for setting
<> 134:ad3be0349dc5 305 * conditioned to ADC state.
<> 134:ad3be0349dc5 306 */
<> 134:ad3be0349dc5 307 typedef struct
<> 134:ad3be0349dc5 308 {
<> 134:ad3be0349dc5 309 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
<> 134:ad3be0349dc5 310 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
<> 134:ad3be0349dc5 311 @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
<> 134:ad3be0349dc5 312 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
<> 134:ad3be0349dc5 313 In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
<> 134:ad3be0349dc5 314
<> 134:ad3be0349dc5 315 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
<> 134:ad3be0349dc5 316
<> 134:ad3be0349dc5 317 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
<> 134:ad3be0349dc5 318 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
<> 134:ad3be0349dc5 319 @note This parameter has an effect only if group regular sequencer is enabled
<> 134:ad3be0349dc5 320 (several ADC channels enabled in group regular sequencer).
<> 134:ad3be0349dc5 321
<> 134:ad3be0349dc5 322 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
<> 134:ad3be0349dc5 323
<> 134:ad3be0349dc5 324 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
<> 134:ad3be0349dc5 325 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
<> 134:ad3be0349dc5 326 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
<> 134:ad3be0349dc5 327
<> 134:ad3be0349dc5 328 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
<> 134:ad3be0349dc5 329
<> 134:ad3be0349dc5 330 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
<> 134:ad3be0349dc5 331 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
<> 134:ad3be0349dc5 332
<> 134:ad3be0349dc5 333 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
<> 134:ad3be0349dc5 334
<> 134:ad3be0349dc5 335 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
<> 134:ad3be0349dc5 336 data preserved or overwritten.
<> 134:ad3be0349dc5 337 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
<> 134:ad3be0349dc5 338
<> 134:ad3be0349dc5 339 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
<> 134:ad3be0349dc5 340
<> 134:ad3be0349dc5 341 } LL_ADC_REG_InitTypeDef;
<> 134:ad3be0349dc5 342
<> 134:ad3be0349dc5 343 /**
<> 134:ad3be0349dc5 344 * @}
<> 134:ad3be0349dc5 345 */
<> 134:ad3be0349dc5 346 #endif /* USE_FULL_LL_DRIVER */
<> 134:ad3be0349dc5 347
<> 134:ad3be0349dc5 348 /* Exported constants --------------------------------------------------------*/
<> 134:ad3be0349dc5 349 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
<> 134:ad3be0349dc5 350 * @{
<> 134:ad3be0349dc5 351 */
<> 134:ad3be0349dc5 352
<> 134:ad3be0349dc5 353 /** @defgroup ADC_LL_EC_FLAG ADC flags
<> 134:ad3be0349dc5 354 * @brief Flags defines which can be used with LL_ADC_ReadReg function
<> 134:ad3be0349dc5 355 * @{
<> 134:ad3be0349dc5 356 */
<> 134:ad3be0349dc5 357 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
<> 134:ad3be0349dc5 358 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
<> 134:ad3be0349dc5 359 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
<> 134:ad3be0349dc5 360 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
<> 134:ad3be0349dc5 361 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
<> 134:ad3be0349dc5 362 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD /*!< ADC flag ADC analog watchdog 1 */
<> 134:ad3be0349dc5 363 /**
<> 134:ad3be0349dc5 364 * @}
<> 134:ad3be0349dc5 365 */
<> 134:ad3be0349dc5 366
<> 134:ad3be0349dc5 367 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
<> 134:ad3be0349dc5 368 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
<> 134:ad3be0349dc5 369 * @{
<> 134:ad3be0349dc5 370 */
<> 134:ad3be0349dc5 371 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
<> 134:ad3be0349dc5 372 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
<> 134:ad3be0349dc5 373 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
<> 134:ad3be0349dc5 374 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
<> 134:ad3be0349dc5 375 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
<> 134:ad3be0349dc5 376 #define LL_ADC_IT_AWD1 ADC_IER_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
<> 134:ad3be0349dc5 377 /**
<> 134:ad3be0349dc5 378 * @}
<> 134:ad3be0349dc5 379 */
<> 134:ad3be0349dc5 380
<> 134:ad3be0349dc5 381 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
<> 134:ad3be0349dc5 382 * @{
<> 134:ad3be0349dc5 383 */
<> 134:ad3be0349dc5 384 /* List of ADC registers intended to be used (most commonly) with */
<> 134:ad3be0349dc5 385 /* DMA transfer. */
<> 134:ad3be0349dc5 386 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
<> 134:ad3be0349dc5 387 #define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
<> 134:ad3be0349dc5 388 /**
<> 134:ad3be0349dc5 389 * @}
<> 134:ad3be0349dc5 390 */
<> 134:ad3be0349dc5 391
<> 134:ad3be0349dc5 392 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
<> 134:ad3be0349dc5 393 * @{
<> 134:ad3be0349dc5 394 */
<> 134:ad3be0349dc5 395 /* Note: Other measurement paths to internal channels may be available */
<> 134:ad3be0349dc5 396 /* (connections to other peripherals). */
<> 134:ad3be0349dc5 397 /* If they are not listed below, they do not require any specific */
<> 134:ad3be0349dc5 398 /* path enable. In this case, Access to measurement path is done */
<> 134:ad3be0349dc5 399 /* only by selecting the corresponding ADC internal channel. */
<> 134:ad3be0349dc5 400 #define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/*!< ADC measurement pathes all disabled */
<> 134:ad3be0349dc5 401 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
<> 134:ad3be0349dc5 402 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
<> 134:ad3be0349dc5 403 #if defined(ADC_CCR_VBATEN)
<> 134:ad3be0349dc5 404 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
<> 134:ad3be0349dc5 405 #endif
<> 134:ad3be0349dc5 406 /**
<> 134:ad3be0349dc5 407 * @}
<> 134:ad3be0349dc5 408 */
<> 134:ad3be0349dc5 409
<> 134:ad3be0349dc5 410 /** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source
<> 134:ad3be0349dc5 411 * @{
<> 134:ad3be0349dc5 412 */
<> 134:ad3be0349dc5 413 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 4 */
<> 134:ad3be0349dc5 414 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by 2 */
<> 134:ad3be0349dc5 415 #define LL_ADC_CLOCK_ASYNC ((uint32_t)0x00000000U) /*!< ADC asynchronous clock. On this STM32 serie, asynchronous clock has no prescaler. */
<> 134:ad3be0349dc5 416 /**
<> 134:ad3be0349dc5 417 * @}
<> 134:ad3be0349dc5 418 */
<> 134:ad3be0349dc5 419
<> 134:ad3be0349dc5 420 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
<> 134:ad3be0349dc5 421 * @{
<> 134:ad3be0349dc5 422 */
<> 134:ad3be0349dc5 423 #define LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< ADC resolution 12 bits */
<> 134:ad3be0349dc5 424 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */
<> 134:ad3be0349dc5 425 #define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 8 bits */
<> 134:ad3be0349dc5 426 #define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 6 bits */
<> 134:ad3be0349dc5 427 /**
<> 134:ad3be0349dc5 428 * @}
<> 134:ad3be0349dc5 429 */
<> 134:ad3be0349dc5 430
<> 134:ad3be0349dc5 431 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
<> 134:ad3be0349dc5 432 * @{
<> 134:ad3be0349dc5 433 */
<> 134:ad3be0349dc5 434 #define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
<> 134:ad3be0349dc5 435 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
<> 134:ad3be0349dc5 436 /**
<> 134:ad3be0349dc5 437 * @}
<> 134:ad3be0349dc5 438 */
<> 134:ad3be0349dc5 439
<> 134:ad3be0349dc5 440 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
<> 134:ad3be0349dc5 441 * @{
<> 134:ad3be0349dc5 442 */
<> 134:ad3be0349dc5 443 #define LL_ADC_LP_MODE_NONE ((uint32_t)0x00000000U) /*!< No ADC low power mode activated */
<> 134:ad3be0349dc5 444 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
<> 134:ad3be0349dc5 445 #define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). Note: On STM32F0, if enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) during auto wait phase. */
<> 134:ad3be0349dc5 446 #define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */
<> 134:ad3be0349dc5 447 /**
<> 134:ad3be0349dc5 448 * @}
<> 134:ad3be0349dc5 449 */
<> 134:ad3be0349dc5 450
<> 134:ad3be0349dc5 451 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
<> 134:ad3be0349dc5 452 * @{
<> 134:ad3be0349dc5 453 */
<> 134:ad3be0349dc5 454 #define LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
<> 134:ad3be0349dc5 455 /**
<> 134:ad3be0349dc5 456 * @}
<> 134:ad3be0349dc5 457 */
<> 134:ad3be0349dc5 458
<> 134:ad3be0349dc5 459 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
<> 134:ad3be0349dc5 460 * @{
<> 134:ad3be0349dc5 461 */
<> 134:ad3be0349dc5 462 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
<> 134:ad3be0349dc5 463 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
<> 134:ad3be0349dc5 464 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
<> 134:ad3be0349dc5 465 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
<> 134:ad3be0349dc5 466 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
<> 134:ad3be0349dc5 467 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
<> 134:ad3be0349dc5 468 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
<> 134:ad3be0349dc5 469 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
<> 134:ad3be0349dc5 470 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
<> 134:ad3be0349dc5 471 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
<> 134:ad3be0349dc5 472 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
<> 134:ad3be0349dc5 473 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
<> 134:ad3be0349dc5 474 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
<> 134:ad3be0349dc5 475 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
<> 134:ad3be0349dc5 476 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
<> 134:ad3be0349dc5 477 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
<> 134:ad3be0349dc5 478 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
<> 134:ad3be0349dc5 479 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
<> 134:ad3be0349dc5 480 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
<> 134:ad3be0349dc5 481 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
<> 134:ad3be0349dc5 482 #if defined(ADC_CCR_VBATEN)
<> 134:ad3be0349dc5 483 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
<> 134:ad3be0349dc5 484 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/2: Vbat voltage through a divider ladder of factor 1/2 to have Vbat always below Vdda. */
<> 134:ad3be0349dc5 485 #endif
<> 134:ad3be0349dc5 486 /**
<> 134:ad3be0349dc5 487 * @}
<> 134:ad3be0349dc5 488 */
<> 134:ad3be0349dc5 489
<> 134:ad3be0349dc5 490 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
<> 134:ad3be0349dc5 491 * @{
<> 134:ad3be0349dc5 492 */
<> 134:ad3be0349dc5 493 #define LL_ADC_REG_TRIG_SOFTWARE ((uint32_t)0x00000000U) /*!< ADC group regular conversion trigger internal: SW start. */
<> 134:ad3be0349dc5 494 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
<> 134:ad3be0349dc5 495 #define LL_ADC_REG_TRIG_EXT_TIM1_CH4 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
<> 134:ad3be0349dc5 496 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
<> 134:ad3be0349dc5 497 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
<> 134:ad3be0349dc5 498 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
<> 134:ad3be0349dc5 499 /**
<> 134:ad3be0349dc5 500 * @}
<> 134:ad3be0349dc5 501 */
<> 134:ad3be0349dc5 502
<> 134:ad3be0349dc5 503 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
<> 134:ad3be0349dc5 504 * @{
<> 134:ad3be0349dc5 505 */
<> 134:ad3be0349dc5 506 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
<> 134:ad3be0349dc5 507 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
<> 134:ad3be0349dc5 508 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
<> 134:ad3be0349dc5 509 /**
<> 134:ad3be0349dc5 510 * @}
<> 134:ad3be0349dc5 511 */
<> 134:ad3be0349dc5 512
<> 134:ad3be0349dc5 513 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
<> 134:ad3be0349dc5 514 * @{
<> 134:ad3be0349dc5 515 */
<> 134:ad3be0349dc5 516 #define LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */
<> 134:ad3be0349dc5 517 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
<> 134:ad3be0349dc5 518 /**
<> 134:ad3be0349dc5 519 * @}
<> 134:ad3be0349dc5 520 */
<> 134:ad3be0349dc5 521
<> 134:ad3be0349dc5 522 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
<> 134:ad3be0349dc5 523 * @{
<> 134:ad3be0349dc5 524 */
<> 134:ad3be0349dc5 525 #define LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U) /*!< ADC conversions are not transferred by DMA */
<> 134:ad3be0349dc5 526 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
<> 134:ad3be0349dc5 527 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
<> 134:ad3be0349dc5 528 /**
<> 134:ad3be0349dc5 529 * @}
<> 134:ad3be0349dc5 530 */
<> 134:ad3be0349dc5 531
<> 134:ad3be0349dc5 532 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
<> 134:ad3be0349dc5 533 * @{
<> 134:ad3be0349dc5 534 */
<> 134:ad3be0349dc5 535 #define LL_ADC_REG_OVR_DATA_PRESERVED ((uint32_t)0x00000000U)/*!< ADC group regular behavior in case of overrun: data preserved */
<> 134:ad3be0349dc5 536 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
<> 134:ad3be0349dc5 537 /**
<> 134:ad3be0349dc5 538 * @}
<> 134:ad3be0349dc5 539 */
<> 134:ad3be0349dc5 540
<> 134:ad3be0349dc5 541 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction
<> 134:ad3be0349dc5 542 * @{
<> 134:ad3be0349dc5 543 */
<> 134:ad3be0349dc5 544 #define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD ((uint32_t)0x00000000U)/*!< ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */
<> 134:ad3be0349dc5 545 #define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */
<> 134:ad3be0349dc5 546 /**
<> 134:ad3be0349dc5 547 * @}
<> 134:ad3be0349dc5 548 */
<> 134:ad3be0349dc5 549
<> 134:ad3be0349dc5 550 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
<> 134:ad3be0349dc5 551 * @{
<> 134:ad3be0349dc5 552 */
<> 134:ad3be0349dc5 553 #define LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */
<> 134:ad3be0349dc5 554 #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
<> 134:ad3be0349dc5 555 /**
<> 134:ad3be0349dc5 556 * @}
<> 134:ad3be0349dc5 557 */
<> 134:ad3be0349dc5 558
<> 134:ad3be0349dc5 559 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
<> 134:ad3be0349dc5 560 * @{
<> 134:ad3be0349dc5 561 */
<> 134:ad3be0349dc5 562 #define LL_ADC_SAMPLINGTIME_1CYCLE_5 ((uint32_t)0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */
<> 134:ad3be0349dc5 563 #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP_0) /*!< Sampling time 7.5 ADC clock cycles */
<> 134:ad3be0349dc5 564 #define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR_SMP_1) /*!< Sampling time 13.5 ADC clock cycles */
<> 134:ad3be0349dc5 565 #define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0) /*!< Sampling time 28.5 ADC clock cycles */
<> 134:ad3be0349dc5 566 #define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR_SMP_2) /*!< Sampling time 41.5 ADC clock cycles */
<> 134:ad3be0349dc5 567 #define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0) /*!< Sampling time 55.5 ADC clock cycles */
<> 134:ad3be0349dc5 568 #define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1) /*!< Sampling time 71.5 ADC clock cycles */
<> 134:ad3be0349dc5 569 #define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0) /*!< Sampling time 239.5 ADC clock cycles */
<> 134:ad3be0349dc5 570 /**
<> 134:ad3be0349dc5 571 * @}
<> 134:ad3be0349dc5 572 */
<> 134:ad3be0349dc5 573
<> 134:ad3be0349dc5 574 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
<> 134:ad3be0349dc5 575 * @{
<> 134:ad3be0349dc5 576 */
<> 134:ad3be0349dc5 577 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
<> 134:ad3be0349dc5 578 /**
<> 134:ad3be0349dc5 579 * @}
<> 134:ad3be0349dc5 580 */
<> 134:ad3be0349dc5 581
<> 134:ad3be0349dc5 582 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
<> 134:ad3be0349dc5 583 * @{
<> 134:ad3be0349dc5 584 */
<> 134:ad3be0349dc5 585 #define LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U) /*!< ADC analog watchdog monitoring disabled */
<> 134:ad3be0349dc5 586 #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CFGR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
<> 134:ad3be0349dc5 587 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
<> 134:ad3be0349dc5 588 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
<> 134:ad3be0349dc5 589 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
<> 134:ad3be0349dc5 590 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
<> 134:ad3be0349dc5 591 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
<> 134:ad3be0349dc5 592 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
<> 134:ad3be0349dc5 593 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
<> 134:ad3be0349dc5 594 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
<> 134:ad3be0349dc5 595 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
<> 134:ad3be0349dc5 596 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
<> 134:ad3be0349dc5 597 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
<> 134:ad3be0349dc5 598 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
<> 134:ad3be0349dc5 599 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
<> 134:ad3be0349dc5 600 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
<> 134:ad3be0349dc5 601 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
<> 134:ad3be0349dc5 602 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
<> 134:ad3be0349dc5 603 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
<> 134:ad3be0349dc5 604 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
<> 134:ad3be0349dc5 605 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
<> 134:ad3be0349dc5 606 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
<> 134:ad3be0349dc5 607 #if defined(ADC_CCR_VBATEN)
<> 134:ad3be0349dc5 608 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
<> 134:ad3be0349dc5 609 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
<> 134:ad3be0349dc5 610 #endif
<> 134:ad3be0349dc5 611 /**
<> 134:ad3be0349dc5 612 * @}
<> 134:ad3be0349dc5 613 */
<> 134:ad3be0349dc5 614
<> 134:ad3be0349dc5 615 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
<> 134:ad3be0349dc5 616 * @{
<> 134:ad3be0349dc5 617 */
<> 134:ad3be0349dc5 618 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR_HT ) /*!< ADC analog watchdog threshold high */
<> 134:ad3be0349dc5 619 #define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR_LT) /*!< ADC analog watchdog threshold low */
<> 134:ad3be0349dc5 620 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR_HT | ADC_TR_LT) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
<> 134:ad3be0349dc5 621 /**
<> 134:ad3be0349dc5 622 * @}
<> 134:ad3be0349dc5 623 */
<> 134:ad3be0349dc5 624
<> 134:ad3be0349dc5 625
<> 134:ad3be0349dc5 626 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
<> 134:ad3be0349dc5 627 * @note Only ADC IP HW delays are defined in ADC LL driver driver,
<> 134:ad3be0349dc5 628 * not timeout values.
<> 134:ad3be0349dc5 629 * For details on delays values, refer to descriptions in source code
<> 134:ad3be0349dc5 630 * above each literal definition.
<> 134:ad3be0349dc5 631 * @{
<> 134:ad3be0349dc5 632 */
<> 134:ad3be0349dc5 633
<> 134:ad3be0349dc5 634 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
<> 134:ad3be0349dc5 635 /* not timeout values. */
<> 134:ad3be0349dc5 636 /* Timeout values for ADC operations are dependent to device clock */
<> 134:ad3be0349dc5 637 /* configuration (system clock versus ADC clock), */
<> 134:ad3be0349dc5 638 /* and therefore must be defined in user application. */
<> 134:ad3be0349dc5 639 /* Indications for estimation of ADC timeout delays, for this */
<> 134:ad3be0349dc5 640 /* STM32 serie: */
<> 134:ad3be0349dc5 641 /* - ADC calibration time: maximum delay is 83/fADC. */
<> 134:ad3be0349dc5 642 /* (refer to device datasheet, parameter "tCAL") */
<> 134:ad3be0349dc5 643 /* - ADC enable time: maximum delay is 1 conversion cycle. */
<> 134:ad3be0349dc5 644 /* (refer to device datasheet, parameter "tSTAB") */
<> 134:ad3be0349dc5 645 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
<> 134:ad3be0349dc5 646 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
<> 134:ad3be0349dc5 647 /* cycles */
<> 134:ad3be0349dc5 648 /* - ADC conversion time: duration depending on ADC clock and ADC */
<> 134:ad3be0349dc5 649 /* configuration. */
<> 134:ad3be0349dc5 650 /* (refer to device reference manual, section "Timing") */
<> 134:ad3be0349dc5 651
<> 134:ad3be0349dc5 652
<> 134:ad3be0349dc5 653 /* Delay for internal voltage reference stabilization time. */
<> 134:ad3be0349dc5 654 /* Delay set to maximum value (refer to device datasheet, */
<> 134:ad3be0349dc5 655 /* parameter "tSTART"). */
<> 134:ad3be0349dc5 656 /* Unit: us */
<> 134:ad3be0349dc5 657 #define LL_ADC_DELAY_VREFINT_STAB_US ((uint32_t) 10U) /*!< Delay for internal voltage reference stabilization time */
<> 134:ad3be0349dc5 658
<> 134:ad3be0349dc5 659 /* Delay for temperature sensor stabilization time. */
<> 134:ad3be0349dc5 660 /* Literal set to maximum value (refer to device datasheet, */
<> 134:ad3be0349dc5 661 /* parameter "tSTART"). */
<> 134:ad3be0349dc5 662 /* Unit: us */
<> 134:ad3be0349dc5 663 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 10U) /*!< Delay for temperature sensor stabilization time */
<> 134:ad3be0349dc5 664
<> 134:ad3be0349dc5 665 /* Delay required between ADC end of calibration and ADC enable. */
<> 134:ad3be0349dc5 666 /* Note: On this STM32 serie, a minimum number of ADC clock cycles */
<> 134:ad3be0349dc5 667 /* are required between ADC end of calibration and ADC enable. */
<> 134:ad3be0349dc5 668 /* Wait time can be computed in user application by waiting for the */
<> 134:ad3be0349dc5 669 /* equivalent number of CPU cycles, by taking into account */
<> 134:ad3be0349dc5 670 /* ratio of CPU clock versus ADC clock prescalers. */
<> 134:ad3be0349dc5 671 /* Unit: ADC clock cycles. */
<> 134:ad3be0349dc5 672 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ((uint32_t) 2U) /*!< Delay required between ADC end of calibration and ADC enable */
<> 134:ad3be0349dc5 673
<> 134:ad3be0349dc5 674 /**
<> 134:ad3be0349dc5 675 * @}
<> 134:ad3be0349dc5 676 */
<> 134:ad3be0349dc5 677
<> 134:ad3be0349dc5 678 /**
<> 134:ad3be0349dc5 679 * @}
<> 134:ad3be0349dc5 680 */
<> 134:ad3be0349dc5 681
<> 134:ad3be0349dc5 682
<> 134:ad3be0349dc5 683 /* Exported macro ------------------------------------------------------------*/
<> 134:ad3be0349dc5 684 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
<> 134:ad3be0349dc5 685 * @{
<> 134:ad3be0349dc5 686 */
<> 134:ad3be0349dc5 687
<> 134:ad3be0349dc5 688 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
<> 134:ad3be0349dc5 689 * @{
<> 134:ad3be0349dc5 690 */
<> 134:ad3be0349dc5 691
<> 134:ad3be0349dc5 692 /**
<> 134:ad3be0349dc5 693 * @brief Write a value in ADC register
<> 134:ad3be0349dc5 694 * @param __INSTANCE__ ADC Instance
<> 134:ad3be0349dc5 695 * @param __REG__ Register to be written
<> 134:ad3be0349dc5 696 * @param __VALUE__ Value to be written in the register
<> 134:ad3be0349dc5 697 * @retval None
<> 134:ad3be0349dc5 698 */
<> 134:ad3be0349dc5 699 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<> 134:ad3be0349dc5 700
<> 134:ad3be0349dc5 701 /**
<> 134:ad3be0349dc5 702 * @brief Read a value in ADC register
<> 134:ad3be0349dc5 703 * @param __INSTANCE__ ADC Instance
<> 134:ad3be0349dc5 704 * @param __REG__ Register to be read
<> 134:ad3be0349dc5 705 * @retval Register value
<> 134:ad3be0349dc5 706 */
<> 134:ad3be0349dc5 707 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<> 134:ad3be0349dc5 708 /**
<> 134:ad3be0349dc5 709 * @}
<> 134:ad3be0349dc5 710 */
<> 134:ad3be0349dc5 711
<> 134:ad3be0349dc5 712 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
<> 134:ad3be0349dc5 713 * @{
<> 134:ad3be0349dc5 714 */
<> 134:ad3be0349dc5 715
<> 134:ad3be0349dc5 716 /**
<> 134:ad3be0349dc5 717 * @brief Helper macro to get ADC channel number in decimal format
<> 134:ad3be0349dc5 718 * from literals LL_ADC_CHANNEL_x.
<> 134:ad3be0349dc5 719 * @note Example:
<> 134:ad3be0349dc5 720 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
<> 134:ad3be0349dc5 721 * will return decimal number "4".
<> 134:ad3be0349dc5 722 * @note The input can be a value from functions where a channel
<> 134:ad3be0349dc5 723 * number is returned, either defined with number
<> 134:ad3be0349dc5 724 * or with bitfield (only one bit must be set).
<> 134:ad3be0349dc5 725 * @param __CHANNEL__ This parameter can be one of the following values:
<> 134:ad3be0349dc5 726 * @arg @ref LL_ADC_CHANNEL_0
<> 134:ad3be0349dc5 727 * @arg @ref LL_ADC_CHANNEL_1
<> 134:ad3be0349dc5 728 * @arg @ref LL_ADC_CHANNEL_2
<> 134:ad3be0349dc5 729 * @arg @ref LL_ADC_CHANNEL_3
<> 134:ad3be0349dc5 730 * @arg @ref LL_ADC_CHANNEL_4
<> 134:ad3be0349dc5 731 * @arg @ref LL_ADC_CHANNEL_5
<> 134:ad3be0349dc5 732 * @arg @ref LL_ADC_CHANNEL_6
<> 134:ad3be0349dc5 733 * @arg @ref LL_ADC_CHANNEL_7
<> 134:ad3be0349dc5 734 * @arg @ref LL_ADC_CHANNEL_8
<> 134:ad3be0349dc5 735 * @arg @ref LL_ADC_CHANNEL_9
<> 134:ad3be0349dc5 736 * @arg @ref LL_ADC_CHANNEL_10
<> 134:ad3be0349dc5 737 * @arg @ref LL_ADC_CHANNEL_11
<> 134:ad3be0349dc5 738 * @arg @ref LL_ADC_CHANNEL_12
<> 134:ad3be0349dc5 739 * @arg @ref LL_ADC_CHANNEL_13
<> 134:ad3be0349dc5 740 * @arg @ref LL_ADC_CHANNEL_14
<> 134:ad3be0349dc5 741 * @arg @ref LL_ADC_CHANNEL_15
<> 134:ad3be0349dc5 742 * @arg @ref LL_ADC_CHANNEL_16
<> 134:ad3be0349dc5 743 * @arg @ref LL_ADC_CHANNEL_17
<> 134:ad3be0349dc5 744 * @arg @ref LL_ADC_CHANNEL_18 (1)
<> 134:ad3be0349dc5 745 * @arg @ref LL_ADC_CHANNEL_VREFINT
<> 134:ad3be0349dc5 746 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
<> 134:ad3be0349dc5 747 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
<> 134:ad3be0349dc5 748 *
<> 134:ad3be0349dc5 749 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<> 134:ad3be0349dc5 750 * @retval Value between Min_Data=0 and Max_Data=18
<> 134:ad3be0349dc5 751 */
<> 134:ad3be0349dc5 752 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
<> 134:ad3be0349dc5 753 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U) \
<> 134:ad3be0349dc5 754 ? ( \
<> 134:ad3be0349dc5 755 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
<> 134:ad3be0349dc5 756 ) \
<> 134:ad3be0349dc5 757 : \
<> 134:ad3be0349dc5 758 ( \
<> 134:ad3be0349dc5 759 (((__CHANNEL__) & ADC_CHSELR_CHSEL0) == ADC_CHSELR_CHSEL0) ? (0U) : \
<> 134:ad3be0349dc5 760 ( \
<> 134:ad3be0349dc5 761 (((__CHANNEL__) & ADC_CHSELR_CHSEL1) == ADC_CHSELR_CHSEL1) ? (1U) : \
<> 134:ad3be0349dc5 762 ( \
<> 134:ad3be0349dc5 763 (((__CHANNEL__) & ADC_CHSELR_CHSEL2) == ADC_CHSELR_CHSEL2) ? (2U) : \
<> 134:ad3be0349dc5 764 ( \
<> 134:ad3be0349dc5 765 (((__CHANNEL__) & ADC_CHSELR_CHSEL3) == ADC_CHSELR_CHSEL3) ? (3U) : \
<> 134:ad3be0349dc5 766 ( \
<> 134:ad3be0349dc5 767 (((__CHANNEL__) & ADC_CHSELR_CHSEL4) == ADC_CHSELR_CHSEL4) ? (4U) : \
<> 134:ad3be0349dc5 768 ( \
<> 134:ad3be0349dc5 769 (((__CHANNEL__) & ADC_CHSELR_CHSEL5) == ADC_CHSELR_CHSEL5) ? (5U) : \
<> 134:ad3be0349dc5 770 ( \
<> 134:ad3be0349dc5 771 (((__CHANNEL__) & ADC_CHSELR_CHSEL6) == ADC_CHSELR_CHSEL6) ? (6U) : \
<> 134:ad3be0349dc5 772 ( \
<> 134:ad3be0349dc5 773 (((__CHANNEL__) & ADC_CHSELR_CHSEL7) == ADC_CHSELR_CHSEL7) ? (7U) : \
<> 134:ad3be0349dc5 774 ( \
<> 134:ad3be0349dc5 775 (((__CHANNEL__) & ADC_CHSELR_CHSEL8) == ADC_CHSELR_CHSEL8) ? (8U) : \
<> 134:ad3be0349dc5 776 ( \
<> 134:ad3be0349dc5 777 (((__CHANNEL__) & ADC_CHSELR_CHSEL9) == ADC_CHSELR_CHSEL9) ? (9U) : \
<> 134:ad3be0349dc5 778 ( \
<> 134:ad3be0349dc5 779 (((__CHANNEL__) & ADC_CHSELR_CHSEL10) == ADC_CHSELR_CHSEL10) ? (10U) : \
<> 134:ad3be0349dc5 780 ( \
<> 134:ad3be0349dc5 781 (((__CHANNEL__) & ADC_CHSELR_CHSEL11) == ADC_CHSELR_CHSEL11) ? (11U) : \
<> 134:ad3be0349dc5 782 ( \
<> 134:ad3be0349dc5 783 (((__CHANNEL__) & ADC_CHSELR_CHSEL12) == ADC_CHSELR_CHSEL12) ? (12U) : \
<> 134:ad3be0349dc5 784 ( \
<> 134:ad3be0349dc5 785 (((__CHANNEL__) & ADC_CHSELR_CHSEL13) == ADC_CHSELR_CHSEL13) ? (13U) : \
<> 134:ad3be0349dc5 786 ( \
<> 134:ad3be0349dc5 787 (((__CHANNEL__) & ADC_CHSELR_CHSEL14) == ADC_CHSELR_CHSEL14) ? (14U) : \
<> 134:ad3be0349dc5 788 ( \
<> 134:ad3be0349dc5 789 (((__CHANNEL__) & ADC_CHSELR_CHSEL15) == ADC_CHSELR_CHSEL15) ? (15U) : \
<> 134:ad3be0349dc5 790 ( \
<> 134:ad3be0349dc5 791 (((__CHANNEL__) & ADC_CHSELR_CHSEL16) == ADC_CHSELR_CHSEL16) ? (16U) : \
<> 134:ad3be0349dc5 792 ( \
<> 134:ad3be0349dc5 793 (((__CHANNEL__) & ADC_CHSELR_CHSEL17) == ADC_CHSELR_CHSEL17) ? (17U) : \
<> 134:ad3be0349dc5 794 ( \
<> 134:ad3be0349dc5 795 (((__CHANNEL__) & ADC_CHSELR_CHSEL18) == ADC_CHSELR_CHSEL18) ? (18U) : \
<> 134:ad3be0349dc5 796 (0U) \
<> 134:ad3be0349dc5 797 ) \
<> 134:ad3be0349dc5 798 ) \
<> 134:ad3be0349dc5 799 ) \
<> 134:ad3be0349dc5 800 ) \
<> 134:ad3be0349dc5 801 ) \
<> 134:ad3be0349dc5 802 ) \
<> 134:ad3be0349dc5 803 ) \
<> 134:ad3be0349dc5 804 ) \
<> 134:ad3be0349dc5 805 ) \
<> 134:ad3be0349dc5 806 ) \
<> 134:ad3be0349dc5 807 ) \
<> 134:ad3be0349dc5 808 ) \
<> 134:ad3be0349dc5 809 ) \
<> 134:ad3be0349dc5 810 ) \
<> 134:ad3be0349dc5 811 ) \
<> 134:ad3be0349dc5 812 ) \
<> 134:ad3be0349dc5 813 ) \
<> 134:ad3be0349dc5 814 ) \
<> 134:ad3be0349dc5 815 ) \
<> 134:ad3be0349dc5 816 )
<> 134:ad3be0349dc5 817
<> 134:ad3be0349dc5 818 /**
<> 134:ad3be0349dc5 819 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
<> 134:ad3be0349dc5 820 * from number in decimal format.
<> 134:ad3be0349dc5 821 * @note Example:
<> 134:ad3be0349dc5 822 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
<> 134:ad3be0349dc5 823 * will return a data equivalent to "LL_ADC_CHANNEL_4".
<> 134:ad3be0349dc5 824 * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18
<> 134:ad3be0349dc5 825 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 826 * @arg @ref LL_ADC_CHANNEL_0
<> 134:ad3be0349dc5 827 * @arg @ref LL_ADC_CHANNEL_1
<> 134:ad3be0349dc5 828 * @arg @ref LL_ADC_CHANNEL_2
<> 134:ad3be0349dc5 829 * @arg @ref LL_ADC_CHANNEL_3
<> 134:ad3be0349dc5 830 * @arg @ref LL_ADC_CHANNEL_4
<> 134:ad3be0349dc5 831 * @arg @ref LL_ADC_CHANNEL_5
<> 134:ad3be0349dc5 832 * @arg @ref LL_ADC_CHANNEL_6
<> 134:ad3be0349dc5 833 * @arg @ref LL_ADC_CHANNEL_7
<> 134:ad3be0349dc5 834 * @arg @ref LL_ADC_CHANNEL_8
<> 134:ad3be0349dc5 835 * @arg @ref LL_ADC_CHANNEL_9
<> 134:ad3be0349dc5 836 * @arg @ref LL_ADC_CHANNEL_10
<> 134:ad3be0349dc5 837 * @arg @ref LL_ADC_CHANNEL_11
<> 134:ad3be0349dc5 838 * @arg @ref LL_ADC_CHANNEL_12
<> 134:ad3be0349dc5 839 * @arg @ref LL_ADC_CHANNEL_13
<> 134:ad3be0349dc5 840 * @arg @ref LL_ADC_CHANNEL_14
<> 134:ad3be0349dc5 841 * @arg @ref LL_ADC_CHANNEL_15
<> 134:ad3be0349dc5 842 * @arg @ref LL_ADC_CHANNEL_16
<> 134:ad3be0349dc5 843 * @arg @ref LL_ADC_CHANNEL_17
<> 134:ad3be0349dc5 844 * @arg @ref LL_ADC_CHANNEL_18 (1)
<> 134:ad3be0349dc5 845 * @arg @ref LL_ADC_CHANNEL_VREFINT (2)
<> 134:ad3be0349dc5 846 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2)
<> 134:ad3be0349dc5 847 * @arg @ref LL_ADC_CHANNEL_VBAT (1)(2)
<> 134:ad3be0349dc5 848 *
<> 134:ad3be0349dc5 849 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.\n
<> 134:ad3be0349dc5 850 * (2) For ADC channel read back from ADC register,
<> 134:ad3be0349dc5 851 * comparison with internal channel parameter to be done
<> 134:ad3be0349dc5 852 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
<> 134:ad3be0349dc5 853 */
<> 134:ad3be0349dc5 854 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
<> 134:ad3be0349dc5 855 ( \
<> 134:ad3be0349dc5 856 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
<> 134:ad3be0349dc5 857 (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)) \
<> 134:ad3be0349dc5 858 )
<> 134:ad3be0349dc5 859
<> 134:ad3be0349dc5 860 /**
<> 134:ad3be0349dc5 861 * @brief Helper macro to determine whether the selected channel
<> 134:ad3be0349dc5 862 * corresponds to literal definitions of driver.
<> 134:ad3be0349dc5 863 * @note The different literal definitions of ADC channels are:
<> 134:ad3be0349dc5 864 * - ADC internal channel:
<> 134:ad3be0349dc5 865 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
<> 134:ad3be0349dc5 866 * - ADC external channel (channel connected to a GPIO pin):
<> 134:ad3be0349dc5 867 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
<> 134:ad3be0349dc5 868 * @note The channel parameter must be a value defined from literal
<> 134:ad3be0349dc5 869 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
<> 134:ad3be0349dc5 870 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
<> 134:ad3be0349dc5 871 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
<> 134:ad3be0349dc5 872 * must not be a value from functions where a channel number is
<> 134:ad3be0349dc5 873 * returned from ADC registers,
<> 134:ad3be0349dc5 874 * because internal and external channels share the same channel
<> 134:ad3be0349dc5 875 * number in ADC registers. The differentiation is made only with
<> 134:ad3be0349dc5 876 * parameters definitions of driver.
<> 134:ad3be0349dc5 877 * @param __CHANNEL__ This parameter can be one of the following values:
<> 134:ad3be0349dc5 878 * @arg @ref LL_ADC_CHANNEL_0
<> 134:ad3be0349dc5 879 * @arg @ref LL_ADC_CHANNEL_1
<> 134:ad3be0349dc5 880 * @arg @ref LL_ADC_CHANNEL_2
<> 134:ad3be0349dc5 881 * @arg @ref LL_ADC_CHANNEL_3
<> 134:ad3be0349dc5 882 * @arg @ref LL_ADC_CHANNEL_4
<> 134:ad3be0349dc5 883 * @arg @ref LL_ADC_CHANNEL_5
<> 134:ad3be0349dc5 884 * @arg @ref LL_ADC_CHANNEL_6
<> 134:ad3be0349dc5 885 * @arg @ref LL_ADC_CHANNEL_7
<> 134:ad3be0349dc5 886 * @arg @ref LL_ADC_CHANNEL_8
<> 134:ad3be0349dc5 887 * @arg @ref LL_ADC_CHANNEL_9
<> 134:ad3be0349dc5 888 * @arg @ref LL_ADC_CHANNEL_10
<> 134:ad3be0349dc5 889 * @arg @ref LL_ADC_CHANNEL_11
<> 134:ad3be0349dc5 890 * @arg @ref LL_ADC_CHANNEL_12
<> 134:ad3be0349dc5 891 * @arg @ref LL_ADC_CHANNEL_13
<> 134:ad3be0349dc5 892 * @arg @ref LL_ADC_CHANNEL_14
<> 134:ad3be0349dc5 893 * @arg @ref LL_ADC_CHANNEL_15
<> 134:ad3be0349dc5 894 * @arg @ref LL_ADC_CHANNEL_16
<> 134:ad3be0349dc5 895 * @arg @ref LL_ADC_CHANNEL_17
<> 134:ad3be0349dc5 896 * @arg @ref LL_ADC_CHANNEL_18 (1)
<> 134:ad3be0349dc5 897 * @arg @ref LL_ADC_CHANNEL_VREFINT
<> 134:ad3be0349dc5 898 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
<> 134:ad3be0349dc5 899 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
<> 134:ad3be0349dc5 900 *
<> 134:ad3be0349dc5 901 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<> 134:ad3be0349dc5 902 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
<> 134:ad3be0349dc5 903 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
<> 134:ad3be0349dc5 904 */
<> 134:ad3be0349dc5 905 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
<> 134:ad3be0349dc5 906 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
<> 134:ad3be0349dc5 907
<> 134:ad3be0349dc5 908 /**
<> 134:ad3be0349dc5 909 * @brief Helper macro to convert a channel defined from parameter
<> 134:ad3be0349dc5 910 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
<> 134:ad3be0349dc5 911 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
<> 134:ad3be0349dc5 912 * to its equivalent parameter definition of a ADC external channel
<> 134:ad3be0349dc5 913 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
<> 134:ad3be0349dc5 914 * @note The channel parameter can be, additionally to a value
<> 134:ad3be0349dc5 915 * defined from parameter definition of a ADC internal channel
<> 134:ad3be0349dc5 916 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
<> 134:ad3be0349dc5 917 * a value defined from parameter definition of
<> 134:ad3be0349dc5 918 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
<> 134:ad3be0349dc5 919 * or a value from functions where a channel number is returned
<> 134:ad3be0349dc5 920 * from ADC registers.
<> 134:ad3be0349dc5 921 * @param __CHANNEL__ This parameter can be one of the following values:
<> 134:ad3be0349dc5 922 * @arg @ref LL_ADC_CHANNEL_0
<> 134:ad3be0349dc5 923 * @arg @ref LL_ADC_CHANNEL_1
<> 134:ad3be0349dc5 924 * @arg @ref LL_ADC_CHANNEL_2
<> 134:ad3be0349dc5 925 * @arg @ref LL_ADC_CHANNEL_3
<> 134:ad3be0349dc5 926 * @arg @ref LL_ADC_CHANNEL_4
<> 134:ad3be0349dc5 927 * @arg @ref LL_ADC_CHANNEL_5
<> 134:ad3be0349dc5 928 * @arg @ref LL_ADC_CHANNEL_6
<> 134:ad3be0349dc5 929 * @arg @ref LL_ADC_CHANNEL_7
<> 134:ad3be0349dc5 930 * @arg @ref LL_ADC_CHANNEL_8
<> 134:ad3be0349dc5 931 * @arg @ref LL_ADC_CHANNEL_9
<> 134:ad3be0349dc5 932 * @arg @ref LL_ADC_CHANNEL_10
<> 134:ad3be0349dc5 933 * @arg @ref LL_ADC_CHANNEL_11
<> 134:ad3be0349dc5 934 * @arg @ref LL_ADC_CHANNEL_12
<> 134:ad3be0349dc5 935 * @arg @ref LL_ADC_CHANNEL_13
<> 134:ad3be0349dc5 936 * @arg @ref LL_ADC_CHANNEL_14
<> 134:ad3be0349dc5 937 * @arg @ref LL_ADC_CHANNEL_15
<> 134:ad3be0349dc5 938 * @arg @ref LL_ADC_CHANNEL_16
<> 134:ad3be0349dc5 939 * @arg @ref LL_ADC_CHANNEL_17
<> 134:ad3be0349dc5 940 * @arg @ref LL_ADC_CHANNEL_18 (1)
<> 134:ad3be0349dc5 941 * @arg @ref LL_ADC_CHANNEL_VREFINT
<> 134:ad3be0349dc5 942 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
<> 134:ad3be0349dc5 943 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
<> 134:ad3be0349dc5 944 *
<> 134:ad3be0349dc5 945 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<> 134:ad3be0349dc5 946 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 947 * @arg @ref LL_ADC_CHANNEL_0
<> 134:ad3be0349dc5 948 * @arg @ref LL_ADC_CHANNEL_1
<> 134:ad3be0349dc5 949 * @arg @ref LL_ADC_CHANNEL_2
<> 134:ad3be0349dc5 950 * @arg @ref LL_ADC_CHANNEL_3
<> 134:ad3be0349dc5 951 * @arg @ref LL_ADC_CHANNEL_4
<> 134:ad3be0349dc5 952 * @arg @ref LL_ADC_CHANNEL_5
<> 134:ad3be0349dc5 953 * @arg @ref LL_ADC_CHANNEL_6
<> 134:ad3be0349dc5 954 * @arg @ref LL_ADC_CHANNEL_7
<> 134:ad3be0349dc5 955 * @arg @ref LL_ADC_CHANNEL_8
<> 134:ad3be0349dc5 956 * @arg @ref LL_ADC_CHANNEL_9
<> 134:ad3be0349dc5 957 * @arg @ref LL_ADC_CHANNEL_10
<> 134:ad3be0349dc5 958 * @arg @ref LL_ADC_CHANNEL_11
<> 134:ad3be0349dc5 959 * @arg @ref LL_ADC_CHANNEL_12
<> 134:ad3be0349dc5 960 * @arg @ref LL_ADC_CHANNEL_13
<> 134:ad3be0349dc5 961 * @arg @ref LL_ADC_CHANNEL_14
<> 134:ad3be0349dc5 962 * @arg @ref LL_ADC_CHANNEL_15
<> 134:ad3be0349dc5 963 * @arg @ref LL_ADC_CHANNEL_16
<> 134:ad3be0349dc5 964 * @arg @ref LL_ADC_CHANNEL_17
<> 134:ad3be0349dc5 965 * @arg @ref LL_ADC_CHANNEL_18
<> 134:ad3be0349dc5 966 */
<> 134:ad3be0349dc5 967 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
<> 134:ad3be0349dc5 968 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
<> 134:ad3be0349dc5 969
<> 134:ad3be0349dc5 970 /**
<> 134:ad3be0349dc5 971 * @brief Helper macro to determine whether the internal channel
<> 134:ad3be0349dc5 972 * selected is available on the ADC instance selected.
<> 134:ad3be0349dc5 973 * @note The channel parameter must be a value defined from parameter
<> 134:ad3be0349dc5 974 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
<> 134:ad3be0349dc5 975 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
<> 134:ad3be0349dc5 976 * must not be a value defined from parameter definition of
<> 134:ad3be0349dc5 977 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
<> 134:ad3be0349dc5 978 * or a value from functions where a channel number is
<> 134:ad3be0349dc5 979 * returned from ADC registers,
<> 134:ad3be0349dc5 980 * because internal and external channels share the same channel
<> 134:ad3be0349dc5 981 * number in ADC registers. The differentiation is made only with
<> 134:ad3be0349dc5 982 * parameters definitions of driver.
<> 134:ad3be0349dc5 983 * @param __ADC_INSTANCE__ ADC instance
<> 134:ad3be0349dc5 984 * @param __CHANNEL__ This parameter can be one of the following values:
<> 134:ad3be0349dc5 985 * @arg @ref LL_ADC_CHANNEL_VREFINT
<> 134:ad3be0349dc5 986 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
<> 134:ad3be0349dc5 987 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
<> 134:ad3be0349dc5 988 *
<> 134:ad3be0349dc5 989 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<> 134:ad3be0349dc5 990 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
<> 134:ad3be0349dc5 991 * Value "1" if the internal channel selected is available on the ADC instance selected.
<> 134:ad3be0349dc5 992 */
<> 134:ad3be0349dc5 993 #if defined(ADC_CCR_VBATEN)
<> 134:ad3be0349dc5 994 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
<> 134:ad3be0349dc5 995 ( \
<> 134:ad3be0349dc5 996 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
<> 134:ad3be0349dc5 997 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
<> 134:ad3be0349dc5 998 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
<> 134:ad3be0349dc5 999 )
<> 134:ad3be0349dc5 1000 #else
<> 134:ad3be0349dc5 1001 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
<> 134:ad3be0349dc5 1002 ( \
<> 134:ad3be0349dc5 1003 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
<> 134:ad3be0349dc5 1004 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \
<> 134:ad3be0349dc5 1005 )
<> 134:ad3be0349dc5 1006 #endif
<> 134:ad3be0349dc5 1007
<> 134:ad3be0349dc5 1008 /**
<> 134:ad3be0349dc5 1009 * @brief Helper macro to define ADC analog watchdog parameter:
<> 134:ad3be0349dc5 1010 * define a single channel to monitor with analog watchdog
<> 134:ad3be0349dc5 1011 * from sequencer channel and groups definition.
<> 134:ad3be0349dc5 1012 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
<> 134:ad3be0349dc5 1013 * Example:
<> 134:ad3be0349dc5 1014 * LL_ADC_SetAnalogWDMonitChannels(
<> 134:ad3be0349dc5 1015 * ADC1, LL_ADC_AWD1,
<> 134:ad3be0349dc5 1016 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
<> 134:ad3be0349dc5 1017 * @param __CHANNEL__ This parameter can be one of the following values:
<> 134:ad3be0349dc5 1018 * @arg @ref LL_ADC_CHANNEL_0
<> 134:ad3be0349dc5 1019 * @arg @ref LL_ADC_CHANNEL_1
<> 134:ad3be0349dc5 1020 * @arg @ref LL_ADC_CHANNEL_2
<> 134:ad3be0349dc5 1021 * @arg @ref LL_ADC_CHANNEL_3
<> 134:ad3be0349dc5 1022 * @arg @ref LL_ADC_CHANNEL_4
<> 134:ad3be0349dc5 1023 * @arg @ref LL_ADC_CHANNEL_5
<> 134:ad3be0349dc5 1024 * @arg @ref LL_ADC_CHANNEL_6
<> 134:ad3be0349dc5 1025 * @arg @ref LL_ADC_CHANNEL_7
<> 134:ad3be0349dc5 1026 * @arg @ref LL_ADC_CHANNEL_8
<> 134:ad3be0349dc5 1027 * @arg @ref LL_ADC_CHANNEL_9
<> 134:ad3be0349dc5 1028 * @arg @ref LL_ADC_CHANNEL_10
<> 134:ad3be0349dc5 1029 * @arg @ref LL_ADC_CHANNEL_11
<> 134:ad3be0349dc5 1030 * @arg @ref LL_ADC_CHANNEL_12
<> 134:ad3be0349dc5 1031 * @arg @ref LL_ADC_CHANNEL_13
<> 134:ad3be0349dc5 1032 * @arg @ref LL_ADC_CHANNEL_14
<> 134:ad3be0349dc5 1033 * @arg @ref LL_ADC_CHANNEL_15
<> 134:ad3be0349dc5 1034 * @arg @ref LL_ADC_CHANNEL_16
<> 134:ad3be0349dc5 1035 * @arg @ref LL_ADC_CHANNEL_17
<> 134:ad3be0349dc5 1036 * @arg @ref LL_ADC_CHANNEL_18 (1)
<> 134:ad3be0349dc5 1037 * @arg @ref LL_ADC_CHANNEL_VREFINT (2)
<> 134:ad3be0349dc5 1038 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2)
<> 134:ad3be0349dc5 1039 * @arg @ref LL_ADC_CHANNEL_VBAT (1)(2)
<> 134:ad3be0349dc5 1040 *
<> 134:ad3be0349dc5 1041 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.\n
<> 134:ad3be0349dc5 1042 * (2) For ADC channel read back from ADC register,
<> 134:ad3be0349dc5 1043 * comparison with internal channel parameter to be done
<> 134:ad3be0349dc5 1044 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
<> 134:ad3be0349dc5 1045 * @param __GROUP__ This parameter can be one of the following values:
<> 134:ad3be0349dc5 1046 * @arg @ref LL_ADC_GROUP_REGULAR
<> 134:ad3be0349dc5 1047 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1048 * @arg @ref LL_ADC_AWD_DISABLE
<> 134:ad3be0349dc5 1049 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
<> 134:ad3be0349dc5 1050 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
<> 134:ad3be0349dc5 1051 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
<> 134:ad3be0349dc5 1052 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
<> 134:ad3be0349dc5 1053 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
<> 134:ad3be0349dc5 1054 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
<> 134:ad3be0349dc5 1055 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
<> 134:ad3be0349dc5 1056 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
<> 134:ad3be0349dc5 1057 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
<> 134:ad3be0349dc5 1058 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
<> 134:ad3be0349dc5 1059 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
<> 134:ad3be0349dc5 1060 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
<> 134:ad3be0349dc5 1061 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
<> 134:ad3be0349dc5 1062 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
<> 134:ad3be0349dc5 1063 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
<> 134:ad3be0349dc5 1064 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
<> 134:ad3be0349dc5 1065 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
<> 134:ad3be0349dc5 1066 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
<> 134:ad3be0349dc5 1067 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
<> 134:ad3be0349dc5 1068 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1)
<> 134:ad3be0349dc5 1069 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
<> 134:ad3be0349dc5 1070 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
<> 134:ad3be0349dc5 1071 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
<> 134:ad3be0349dc5 1072 *
<> 134:ad3be0349dc5 1073 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<> 134:ad3be0349dc5 1074 */
<> 134:ad3be0349dc5 1075 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
<> 134:ad3be0349dc5 1076 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL)
<> 134:ad3be0349dc5 1077
<> 134:ad3be0349dc5 1078 /**
<> 134:ad3be0349dc5 1079 * @brief Helper macro to set the value of ADC analog watchdog threshold high
<> 134:ad3be0349dc5 1080 * or low in function of ADC resolution, when ADC resolution is
<> 134:ad3be0349dc5 1081 * different of 12 bits.
<> 134:ad3be0349dc5 1082 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
<> 134:ad3be0349dc5 1083 * or @ref LL_ADC_SetAnalogWDThresholds().
<> 134:ad3be0349dc5 1084 * Example, with a ADC resolution of 8 bits, to set the value of
<> 134:ad3be0349dc5 1085 * analog watchdog threshold high (on 8 bits):
<> 134:ad3be0349dc5 1086 * LL_ADC_SetAnalogWDThresholds
<> 134:ad3be0349dc5 1087 * (< ADCx param >,
<> 134:ad3be0349dc5 1088 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
<> 134:ad3be0349dc5 1089 * );
<> 134:ad3be0349dc5 1090 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<> 134:ad3be0349dc5 1091 * @arg @ref LL_ADC_RESOLUTION_12B
<> 134:ad3be0349dc5 1092 * @arg @ref LL_ADC_RESOLUTION_10B
<> 134:ad3be0349dc5 1093 * @arg @ref LL_ADC_RESOLUTION_8B
<> 134:ad3be0349dc5 1094 * @arg @ref LL_ADC_RESOLUTION_6B
<> 134:ad3be0349dc5 1095 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
<> 134:ad3be0349dc5 1096 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<> 134:ad3be0349dc5 1097 */
<> 134:ad3be0349dc5 1098 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
<> 134:ad3be0349dc5 1099 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
<> 134:ad3be0349dc5 1100
<> 134:ad3be0349dc5 1101 /**
<> 134:ad3be0349dc5 1102 * @brief Helper macro to get the value of ADC analog watchdog threshold high
<> 134:ad3be0349dc5 1103 * or low in function of ADC resolution, when ADC resolution is
<> 134:ad3be0349dc5 1104 * different of 12 bits.
<> 134:ad3be0349dc5 1105 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
<> 134:ad3be0349dc5 1106 * Example, with a ADC resolution of 8 bits, to get the value of
<> 134:ad3be0349dc5 1107 * analog watchdog threshold high (on 8 bits):
<> 134:ad3be0349dc5 1108 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
<> 134:ad3be0349dc5 1109 * (LL_ADC_RESOLUTION_8B,
<> 134:ad3be0349dc5 1110 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
<> 134:ad3be0349dc5 1111 * );
<> 134:ad3be0349dc5 1112 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<> 134:ad3be0349dc5 1113 * @arg @ref LL_ADC_RESOLUTION_12B
<> 134:ad3be0349dc5 1114 * @arg @ref LL_ADC_RESOLUTION_10B
<> 134:ad3be0349dc5 1115 * @arg @ref LL_ADC_RESOLUTION_8B
<> 134:ad3be0349dc5 1116 * @arg @ref LL_ADC_RESOLUTION_6B
<> 134:ad3be0349dc5 1117 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
<> 134:ad3be0349dc5 1118 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<> 134:ad3be0349dc5 1119 */
<> 134:ad3be0349dc5 1120 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
<> 134:ad3be0349dc5 1121 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
<> 134:ad3be0349dc5 1122
<> 134:ad3be0349dc5 1123 /**
<> 134:ad3be0349dc5 1124 * @brief Helper macro to get the ADC analog watchdog threshold high
<> 134:ad3be0349dc5 1125 * or low from raw value containing both thresholds concatenated.
<> 134:ad3be0349dc5 1126 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
<> 134:ad3be0349dc5 1127 * Example, to get analog watchdog threshold high from the register raw value:
<> 134:ad3be0349dc5 1128 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
<> 134:ad3be0349dc5 1129 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
<> 134:ad3be0349dc5 1130 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
<> 134:ad3be0349dc5 1131 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
<> 134:ad3be0349dc5 1132 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
<> 134:ad3be0349dc5 1133 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<> 134:ad3be0349dc5 1134 */
<> 134:ad3be0349dc5 1135 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
<> 134:ad3be0349dc5 1136 (((__AWD_THRESHOLD_TYPE__) == LL_ADC_AWD_THRESHOLD_LOW) \
<> 134:ad3be0349dc5 1137 ? ( \
<> 134:ad3be0349dc5 1138 (__AWD_THRESHOLDS__) & LL_ADC_AWD_THRESHOLD_LOW \
<> 134:ad3be0349dc5 1139 ) \
<> 134:ad3be0349dc5 1140 : \
<> 134:ad3be0349dc5 1141 ( \
<> 134:ad3be0349dc5 1142 ((__AWD_THRESHOLDS__) >> ADC_TR_HT_BITOFFSET_POS) & LL_ADC_AWD_THRESHOLD_LOW \
<> 134:ad3be0349dc5 1143 ) \
<> 134:ad3be0349dc5 1144 )
<> 134:ad3be0349dc5 1145
<> 134:ad3be0349dc5 1146 /**
<> 134:ad3be0349dc5 1147 * @brief Helper macro to select the ADC common instance
<> 134:ad3be0349dc5 1148 * to which is belonging the selected ADC instance.
<> 134:ad3be0349dc5 1149 * @note ADC common register instance can be used for:
<> 134:ad3be0349dc5 1150 * - Set parameters common to several ADC instances
<> 134:ad3be0349dc5 1151 * - Multimode (for devices with several ADC instances)
<> 134:ad3be0349dc5 1152 * Refer to functions having argument "ADCxy_COMMON" as parameter.
<> 134:ad3be0349dc5 1153 * @param __ADCx__ ADC instance
<> 134:ad3be0349dc5 1154 * @retval ADC common register instance
<> 134:ad3be0349dc5 1155 */
<> 134:ad3be0349dc5 1156 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
<> 134:ad3be0349dc5 1157 (ADC1_COMMON)
<> 134:ad3be0349dc5 1158
<> 134:ad3be0349dc5 1159 /**
<> 134:ad3be0349dc5 1160 * @brief Helper macro to check if all ADC instances sharing the same
<> 134:ad3be0349dc5 1161 * ADC common instance are disabled.
<> 134:ad3be0349dc5 1162 * @note This check is required by functions with setting conditioned to
<> 134:ad3be0349dc5 1163 * ADC state:
<> 134:ad3be0349dc5 1164 * All ADC instances of the ADC common group must be disabled.
<> 134:ad3be0349dc5 1165 * Refer to functions having argument "ADCxy_COMMON" as parameter.
<> 134:ad3be0349dc5 1166 * @note On devices with only 1 ADC common instance, parameter of this macro
<> 134:ad3be0349dc5 1167 * is useless and can be ignored (parameter kept for compatibility
<> 134:ad3be0349dc5 1168 * with devices featuring several ADC common instances).
<> 134:ad3be0349dc5 1169 * @param __ADCXY_COMMON__ ADC common instance
<> 134:ad3be0349dc5 1170 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<> 134:ad3be0349dc5 1171 * @retval Value "0" if all ADC instances sharing the same ADC common instance
<> 134:ad3be0349dc5 1172 * are disabled.
<> 134:ad3be0349dc5 1173 * Value "1" if at least one ADC instance sharing the same ADC common instance
<> 134:ad3be0349dc5 1174 * is enabled.
<> 134:ad3be0349dc5 1175 */
<> 134:ad3be0349dc5 1176 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
<> 134:ad3be0349dc5 1177 LL_ADC_IsEnabled(ADC1)
<> 134:ad3be0349dc5 1178
<> 134:ad3be0349dc5 1179 /**
<> 134:ad3be0349dc5 1180 * @brief Helper macro to define the ADC conversion data full-scale digital
<> 134:ad3be0349dc5 1181 * value corresponding to the selected ADC resolution.
<> 134:ad3be0349dc5 1182 * @note ADC conversion data full-scale corresponds to voltage range
<> 134:ad3be0349dc5 1183 * determined by analog voltage references Vref+ and Vref-
<> 134:ad3be0349dc5 1184 * (refer to reference manual).
<> 134:ad3be0349dc5 1185 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<> 134:ad3be0349dc5 1186 * @arg @ref LL_ADC_RESOLUTION_12B
<> 134:ad3be0349dc5 1187 * @arg @ref LL_ADC_RESOLUTION_10B
<> 134:ad3be0349dc5 1188 * @arg @ref LL_ADC_RESOLUTION_8B
<> 134:ad3be0349dc5 1189 * @arg @ref LL_ADC_RESOLUTION_6B
<> 134:ad3be0349dc5 1190 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
<> 134:ad3be0349dc5 1191 */
<> 134:ad3be0349dc5 1192 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
<> 134:ad3be0349dc5 1193 (((uint32_t)0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U)))
<> 134:ad3be0349dc5 1194
<> 134:ad3be0349dc5 1195 /**
<> 134:ad3be0349dc5 1196 * @brief Helper macro to convert the ADC conversion data from
<> 134:ad3be0349dc5 1197 * a resolution to another resolution.
<> 134:ad3be0349dc5 1198 * @param __DATA__ ADC conversion data to be converted
<> 134:ad3be0349dc5 1199 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
<> 134:ad3be0349dc5 1200 * This parameter can be one of the following values:
<> 134:ad3be0349dc5 1201 * @arg @ref LL_ADC_RESOLUTION_12B
<> 134:ad3be0349dc5 1202 * @arg @ref LL_ADC_RESOLUTION_10B
<> 134:ad3be0349dc5 1203 * @arg @ref LL_ADC_RESOLUTION_8B
<> 134:ad3be0349dc5 1204 * @arg @ref LL_ADC_RESOLUTION_6B
<> 134:ad3be0349dc5 1205 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
<> 134:ad3be0349dc5 1206 * This parameter can be one of the following values:
<> 134:ad3be0349dc5 1207 * @arg @ref LL_ADC_RESOLUTION_12B
<> 134:ad3be0349dc5 1208 * @arg @ref LL_ADC_RESOLUTION_10B
<> 134:ad3be0349dc5 1209 * @arg @ref LL_ADC_RESOLUTION_8B
<> 134:ad3be0349dc5 1210 * @arg @ref LL_ADC_RESOLUTION_6B
<> 134:ad3be0349dc5 1211 * @retval ADC conversion data to the requested resolution
<> 134:ad3be0349dc5 1212 */
<> 134:ad3be0349dc5 1213 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
<> 134:ad3be0349dc5 1214 (((__DATA__) \
<> 134:ad3be0349dc5 1215 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U))) \
<> 134:ad3be0349dc5 1216 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U)) \
<> 134:ad3be0349dc5 1217 )
<> 134:ad3be0349dc5 1218
<> 134:ad3be0349dc5 1219 /**
<> 134:ad3be0349dc5 1220 * @brief Helper macro to calculate the voltage (unit: mVolt)
<> 134:ad3be0349dc5 1221 * corresponding to a ADC conversion data (unit: digital value).
<> 134:ad3be0349dc5 1222 * @note Analog reference voltage (Vref+) must be either known from
<> 134:ad3be0349dc5 1223 * user board environment or can be calculated using ADC measurement
<> 134:ad3be0349dc5 1224 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<> 134:ad3be0349dc5 1225 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
<> 134:ad3be0349dc5 1226 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
<> 134:ad3be0349dc5 1227 * (unit: digital value).
<> 134:ad3be0349dc5 1228 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<> 134:ad3be0349dc5 1229 * @arg @ref LL_ADC_RESOLUTION_12B
<> 134:ad3be0349dc5 1230 * @arg @ref LL_ADC_RESOLUTION_10B
<> 134:ad3be0349dc5 1231 * @arg @ref LL_ADC_RESOLUTION_8B
<> 134:ad3be0349dc5 1232 * @arg @ref LL_ADC_RESOLUTION_6B
<> 134:ad3be0349dc5 1233 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
<> 134:ad3be0349dc5 1234 */
<> 134:ad3be0349dc5 1235 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
<> 134:ad3be0349dc5 1236 __ADC_DATA__,\
<> 134:ad3be0349dc5 1237 __ADC_RESOLUTION__) \
<> 134:ad3be0349dc5 1238 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
<> 134:ad3be0349dc5 1239 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
<> 134:ad3be0349dc5 1240 )
<> 134:ad3be0349dc5 1241
<> 134:ad3be0349dc5 1242 /**
<> 134:ad3be0349dc5 1243 * @brief Helper macro to calculate analog reference voltage (Vref+)
<> 134:ad3be0349dc5 1244 * (unit: mVolt) from ADC conversion data of internal voltage
<> 134:ad3be0349dc5 1245 * reference VrefInt.
<> 134:ad3be0349dc5 1246 * @note Computation is using VrefInt calibration value
<> 134:ad3be0349dc5 1247 * stored in system memory for each device during production.
<> 134:ad3be0349dc5 1248 * @note This voltage depends on user board environment: voltage level
<> 134:ad3be0349dc5 1249 * connected to pin Vref+.
<> 134:ad3be0349dc5 1250 * On devices with small package, the pin Vref+ is not present
<> 134:ad3be0349dc5 1251 * and internally bonded to pin Vdda.
<> 134:ad3be0349dc5 1252 * @note On this STM32 serie, calibration data of internal voltage reference
<> 134:ad3be0349dc5 1253 * VrefInt corresponds to a resolution of 12 bits,
<> 134:ad3be0349dc5 1254 * this is the recommended ADC resolution to convert voltage of
<> 134:ad3be0349dc5 1255 * internal voltage reference VrefInt.
<> 134:ad3be0349dc5 1256 * Otherwise, this macro performs the processing to scale
<> 134:ad3be0349dc5 1257 * ADC conversion data to 12 bits.
<> 134:ad3be0349dc5 1258 * @param __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits)
<> 134:ad3be0349dc5 1259 * of internal voltage reference VrefInt (unit: digital value).
<> 134:ad3be0349dc5 1260 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<> 134:ad3be0349dc5 1261 * @arg @ref LL_ADC_RESOLUTION_12B
<> 134:ad3be0349dc5 1262 * @arg @ref LL_ADC_RESOLUTION_10B
<> 134:ad3be0349dc5 1263 * @arg @ref LL_ADC_RESOLUTION_8B
<> 134:ad3be0349dc5 1264 * @arg @ref LL_ADC_RESOLUTION_6B
<> 134:ad3be0349dc5 1265 * @retval Analog reference voltage (unit: mV)
<> 134:ad3be0349dc5 1266 */
<> 134:ad3be0349dc5 1267 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
<> 134:ad3be0349dc5 1268 __ADC_RESOLUTION__) \
<> 134:ad3be0349dc5 1269 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
<> 134:ad3be0349dc5 1270 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
<> 134:ad3be0349dc5 1271 (__ADC_RESOLUTION__), \
<> 134:ad3be0349dc5 1272 LL_ADC_RESOLUTION_12B) \
<> 134:ad3be0349dc5 1273 )
<> 134:ad3be0349dc5 1274
<> 134:ad3be0349dc5 1275 /**
<> 134:ad3be0349dc5 1276 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
<> 134:ad3be0349dc5 1277 * from ADC conversion data of internal temperature sensor.
<> 134:ad3be0349dc5 1278 * @note Computation is using temperature sensor calibration values
<> 134:ad3be0349dc5 1279 * stored in system memory for each device during production.
<> 134:ad3be0349dc5 1280 * @note Calculation formula:
<> 134:ad3be0349dc5 1281 * Temperature = ((TS_ADC_DATA - TS_CAL1)
<> 134:ad3be0349dc5 1282 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
<> 134:ad3be0349dc5 1283 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
<> 134:ad3be0349dc5 1284 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
<> 134:ad3be0349dc5 1285 * Avg_Slope = (TS_CAL2 - TS_CAL1)
<> 134:ad3be0349dc5 1286 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
<> 134:ad3be0349dc5 1287 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
<> 134:ad3be0349dc5 1288 * TEMP_DEGC_CAL1 (calibrated in factory)
<> 134:ad3be0349dc5 1289 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
<> 134:ad3be0349dc5 1290 * TEMP_DEGC_CAL2 (calibrated in factory)
<> 134:ad3be0349dc5 1291 * Caution: Calculation relevancy under reserve that calibration
<> 134:ad3be0349dc5 1292 * parameters are correct (address and data).
<> 134:ad3be0349dc5 1293 * To calculate temperature using temperature sensor
<> 134:ad3be0349dc5 1294 * datasheet typical values (generic values less, therefore
<> 134:ad3be0349dc5 1295 * less accurate than calibrated values),
<> 134:ad3be0349dc5 1296 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
<> 134:ad3be0349dc5 1297 * @note As calculation input, the analog reference voltage (Vref+) must be
<> 134:ad3be0349dc5 1298 * defined as it impacts the ADC LSB equivalent voltage.
<> 134:ad3be0349dc5 1299 * @note Analog reference voltage (Vref+) must be either known from
<> 134:ad3be0349dc5 1300 * user board environment or can be calculated using ADC measurement
<> 134:ad3be0349dc5 1301 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<> 134:ad3be0349dc5 1302 * @note On this STM32 serie, calibration data of temperature sensor
<> 134:ad3be0349dc5 1303 * corresponds to a resolution of 12 bits,
<> 134:ad3be0349dc5 1304 * this is the recommended ADC resolution to convert voltage of
<> 134:ad3be0349dc5 1305 * temperature sensor.
<> 134:ad3be0349dc5 1306 * Otherwise, this macro performs the processing to scale
<> 134:ad3be0349dc5 1307 * ADC conversion data to 12 bits.
<> 134:ad3be0349dc5 1308 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
<> 134:ad3be0349dc5 1309 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
<> 134:ad3be0349dc5 1310 * temperature sensor (unit: digital value).
<> 134:ad3be0349dc5 1311 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
<> 134:ad3be0349dc5 1312 * sensor voltage has been measured.
<> 134:ad3be0349dc5 1313 * This parameter can be one of the following values:
<> 134:ad3be0349dc5 1314 * @arg @ref LL_ADC_RESOLUTION_12B
<> 134:ad3be0349dc5 1315 * @arg @ref LL_ADC_RESOLUTION_10B
<> 134:ad3be0349dc5 1316 * @arg @ref LL_ADC_RESOLUTION_8B
<> 134:ad3be0349dc5 1317 * @arg @ref LL_ADC_RESOLUTION_6B
<> 134:ad3be0349dc5 1318 * @retval Temperature (unit: degree Celsius)
<> 134:ad3be0349dc5 1319 */
<> 134:ad3be0349dc5 1320 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
<> 134:ad3be0349dc5 1321 __TEMPSENSOR_ADC_DATA__,\
<> 134:ad3be0349dc5 1322 __ADC_RESOLUTION__) \
<> 134:ad3be0349dc5 1323 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
<> 134:ad3be0349dc5 1324 (__ADC_RESOLUTION__), \
<> 134:ad3be0349dc5 1325 LL_ADC_RESOLUTION_12B) \
<> 134:ad3be0349dc5 1326 * (__VREFANALOG_VOLTAGE__)) \
<> 134:ad3be0349dc5 1327 / TEMPSENSOR_CAL_VREFANALOG) \
<> 134:ad3be0349dc5 1328 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
<> 134:ad3be0349dc5 1329 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
<> 134:ad3be0349dc5 1330 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
<> 134:ad3be0349dc5 1331 ) + TEMPSENSOR_CAL1_TEMP \
<> 134:ad3be0349dc5 1332 )
<> 134:ad3be0349dc5 1333
<> 134:ad3be0349dc5 1334 /**
<> 134:ad3be0349dc5 1335 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
<> 134:ad3be0349dc5 1336 * from ADC conversion data of internal temperature sensor.
<> 134:ad3be0349dc5 1337 * @note Computation is using temperature sensor typical values
<> 134:ad3be0349dc5 1338 * (refer to device datasheet).
<> 134:ad3be0349dc5 1339 * @note Calculation formula:
<> 134:ad3be0349dc5 1340 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
<> 134:ad3be0349dc5 1341 * / Avg_Slope + CALx_TEMP
<> 134:ad3be0349dc5 1342 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
<> 134:ad3be0349dc5 1343 * (unit: digital value)
<> 134:ad3be0349dc5 1344 * Avg_Slope = temperature sensor slope
<> 134:ad3be0349dc5 1345 * (unit: uV/Degree Celsius)
<> 134:ad3be0349dc5 1346 * TS_TYP_CALx_VOLT = temperature sensor digital value at
<> 134:ad3be0349dc5 1347 * temperature CALx_TEMP (unit: mV)
<> 134:ad3be0349dc5 1348 * Caution: Calculation relevancy under reserve the temperature sensor
<> 134:ad3be0349dc5 1349 * of the current device has characteristics in line with
<> 134:ad3be0349dc5 1350 * datasheet typical values.
<> 134:ad3be0349dc5 1351 * If temperature sensor calibration values are available on
<> 134:ad3be0349dc5 1352 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
<> 134:ad3be0349dc5 1353 * temperature calculation will be more accurate using
<> 134:ad3be0349dc5 1354 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
<> 134:ad3be0349dc5 1355 * @note As calculation input, the analog reference voltage (Vref+) must be
<> 134:ad3be0349dc5 1356 * defined as it impacts the ADC LSB equivalent voltage.
<> 134:ad3be0349dc5 1357 * @note Analog reference voltage (Vref+) must be either known from
<> 134:ad3be0349dc5 1358 * user board environment or can be calculated using ADC measurement
<> 134:ad3be0349dc5 1359 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<> 134:ad3be0349dc5 1360 * @note ADC measurement data must correspond to a resolution of 12bits
<> 134:ad3be0349dc5 1361 * (full scale digital value 4095). If not the case, the data must be
<> 134:ad3be0349dc5 1362 * preliminarily rescaled to an equivalent resolution of 12 bits.
<> 134:ad3be0349dc5 1363 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
<> 134:ad3be0349dc5 1364 * On STM32F0, refer to device datasheet parameter "Avg_Slope".
<> 134:ad3be0349dc5 1365 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
<> 134:ad3be0349dc5 1366 * On STM32F0, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
<> 134:ad3be0349dc5 1367 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
<> 134:ad3be0349dc5 1368 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
<> 134:ad3be0349dc5 1369 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
<> 134:ad3be0349dc5 1370 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
<> 134:ad3be0349dc5 1371 * This parameter can be one of the following values:
<> 134:ad3be0349dc5 1372 * @arg @ref LL_ADC_RESOLUTION_12B
<> 134:ad3be0349dc5 1373 * @arg @ref LL_ADC_RESOLUTION_10B
<> 134:ad3be0349dc5 1374 * @arg @ref LL_ADC_RESOLUTION_8B
<> 134:ad3be0349dc5 1375 * @arg @ref LL_ADC_RESOLUTION_6B
<> 134:ad3be0349dc5 1376 * @retval Temperature (unit: degree Celsius)
<> 134:ad3be0349dc5 1377 */
<> 134:ad3be0349dc5 1378 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
<> 134:ad3be0349dc5 1379 __TEMPSENSOR_TYP_CALX_V__,\
<> 134:ad3be0349dc5 1380 __TEMPSENSOR_CALX_TEMP__,\
<> 134:ad3be0349dc5 1381 __VREFANALOG_VOLTAGE__,\
<> 134:ad3be0349dc5 1382 __TEMPSENSOR_ADC_DATA__,\
<> 134:ad3be0349dc5 1383 __ADC_RESOLUTION__) \
<> 134:ad3be0349dc5 1384 ((( ( \
<> 134:ad3be0349dc5 1385 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
<> 134:ad3be0349dc5 1386 * 1000) \
<> 134:ad3be0349dc5 1387 - \
<> 134:ad3be0349dc5 1388 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
<> 134:ad3be0349dc5 1389 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
<> 134:ad3be0349dc5 1390 * 1000) \
<> 134:ad3be0349dc5 1391 ) \
<> 134:ad3be0349dc5 1392 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
<> 134:ad3be0349dc5 1393 ) + (__TEMPSENSOR_CALX_TEMP__) \
<> 134:ad3be0349dc5 1394 )
<> 134:ad3be0349dc5 1395
<> 134:ad3be0349dc5 1396 /**
<> 134:ad3be0349dc5 1397 * @}
<> 134:ad3be0349dc5 1398 */
<> 134:ad3be0349dc5 1399
<> 134:ad3be0349dc5 1400 /**
<> 134:ad3be0349dc5 1401 * @}
<> 134:ad3be0349dc5 1402 */
<> 134:ad3be0349dc5 1403
<> 134:ad3be0349dc5 1404
<> 134:ad3be0349dc5 1405 /* Exported functions --------------------------------------------------------*/
<> 134:ad3be0349dc5 1406 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
<> 134:ad3be0349dc5 1407 * @{
<> 134:ad3be0349dc5 1408 */
<> 134:ad3be0349dc5 1409
<> 134:ad3be0349dc5 1410 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
<> 134:ad3be0349dc5 1411 * @{
<> 134:ad3be0349dc5 1412 */
<> 134:ad3be0349dc5 1413 /* Note: LL ADC functions to set DMA transfer are located into sections of */
<> 134:ad3be0349dc5 1414 /* configuration of ADC instance, groups and multimode (if available): */
<> 134:ad3be0349dc5 1415 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
<> 134:ad3be0349dc5 1416
<> 134:ad3be0349dc5 1417 /**
<> 134:ad3be0349dc5 1418 * @brief Function to help to configure DMA transfer from ADC: retrieve the
<> 134:ad3be0349dc5 1419 * ADC register address from ADC instance and a list of ADC registers
<> 134:ad3be0349dc5 1420 * intended to be used (most commonly) with DMA transfer.
<> 134:ad3be0349dc5 1421 * @note These ADC registers are data registers:
<> 134:ad3be0349dc5 1422 * when ADC conversion data is available in ADC data registers,
<> 134:ad3be0349dc5 1423 * ADC generates a DMA transfer request.
<> 134:ad3be0349dc5 1424 * @note This macro is intended to be used with LL DMA driver, refer to
<> 134:ad3be0349dc5 1425 * function "LL_DMA_ConfigAddresses()".
<> 134:ad3be0349dc5 1426 * Example:
<> 134:ad3be0349dc5 1427 * LL_DMA_ConfigAddresses(DMA1,
<> 134:ad3be0349dc5 1428 * LL_DMA_CHANNEL_1,
<> 134:ad3be0349dc5 1429 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
<> 134:ad3be0349dc5 1430 * (uint32_t)&< array or variable >,
<> 134:ad3be0349dc5 1431 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
<> 134:ad3be0349dc5 1432 * @note For devices with several ADC: in multimode, some devices
<> 134:ad3be0349dc5 1433 * use a different data register outside of ADC instance scope
<> 134:ad3be0349dc5 1434 * (common data register). This macro manages this register difference,
<> 134:ad3be0349dc5 1435 * only ADC instance has to be set as parameter.
<> 134:ad3be0349dc5 1436 * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
<> 134:ad3be0349dc5 1437 * @param ADCx ADC instance
<> 134:ad3be0349dc5 1438 * @param Register This parameter can be one of the following values:
<> 134:ad3be0349dc5 1439 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
<> 134:ad3be0349dc5 1440 * @retval ADC register address
<> 134:ad3be0349dc5 1441 */
<> 134:ad3be0349dc5 1442 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
<> 134:ad3be0349dc5 1443 {
<> 134:ad3be0349dc5 1444 /* Retrieve address of register DR */
<> 134:ad3be0349dc5 1445 return (uint32_t)&(ADCx->DR);
<> 134:ad3be0349dc5 1446 }
<> 134:ad3be0349dc5 1447
<> 134:ad3be0349dc5 1448 /**
<> 134:ad3be0349dc5 1449 * @}
<> 134:ad3be0349dc5 1450 */
<> 134:ad3be0349dc5 1451
<> 134:ad3be0349dc5 1452 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
<> 134:ad3be0349dc5 1453 * @{
<> 134:ad3be0349dc5 1454 */
<> 134:ad3be0349dc5 1455
<> 134:ad3be0349dc5 1456 /**
<> 134:ad3be0349dc5 1457 * @brief Set parameter common to several ADC: measurement path to internal
<> 134:ad3be0349dc5 1458 * channels (VrefInt, temperature sensor, ...).
<> 134:ad3be0349dc5 1459 * @note One or several values can be selected.
<> 134:ad3be0349dc5 1460 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
<> 134:ad3be0349dc5 1461 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
<> 134:ad3be0349dc5 1462 * @note Stabilization time of measurement path to internal channel:
<> 134:ad3be0349dc5 1463 * After enabling internal paths, before starting ADC conversion,
<> 134:ad3be0349dc5 1464 * a delay is required for internal voltage reference and
<> 134:ad3be0349dc5 1465 * temperature sensor stabilization time.
<> 134:ad3be0349dc5 1466 * Refer to device datasheet.
<> 134:ad3be0349dc5 1467 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
<> 134:ad3be0349dc5 1468 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
<> 134:ad3be0349dc5 1469 * @note ADC internal channel sampling time constraint:
<> 134:ad3be0349dc5 1470 * For ADC conversion of internal channels,
<> 134:ad3be0349dc5 1471 * a sampling time minimum value is required.
<> 134:ad3be0349dc5 1472 * Refer to device datasheet.
<> 134:ad3be0349dc5 1473 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 1474 * ADC state:
<> 134:ad3be0349dc5 1475 * All ADC instances of the ADC common group must be disabled.
<> 134:ad3be0349dc5 1476 * This check can be done with function @ref LL_ADC_IsEnabled() for each
<> 134:ad3be0349dc5 1477 * ADC instance or by using helper macro helper macro
<> 134:ad3be0349dc5 1478 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
<> 134:ad3be0349dc5 1479 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
<> 134:ad3be0349dc5 1480 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
<> 134:ad3be0349dc5 1481 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
<> 134:ad3be0349dc5 1482 * @param ADCxy_COMMON ADC common instance
<> 134:ad3be0349dc5 1483 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<> 134:ad3be0349dc5 1484 * @param PathInternal This parameter can be a combination of the following values:
<> 134:ad3be0349dc5 1485 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
<> 134:ad3be0349dc5 1486 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
<> 134:ad3be0349dc5 1487 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
<> 134:ad3be0349dc5 1488 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT (1)
<> 134:ad3be0349dc5 1489 *
<> 134:ad3be0349dc5 1490 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<> 134:ad3be0349dc5 1491 * @retval None
<> 134:ad3be0349dc5 1492 */
<> 134:ad3be0349dc5 1493 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
<> 134:ad3be0349dc5 1494 {
<> 134:ad3be0349dc5 1495 #if defined(ADC_CCR_VBATEN)
<> 134:ad3be0349dc5 1496 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
<> 134:ad3be0349dc5 1497 #else
<> 134:ad3be0349dc5 1498 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
<> 134:ad3be0349dc5 1499 #endif
<> 134:ad3be0349dc5 1500 }
<> 134:ad3be0349dc5 1501
<> 134:ad3be0349dc5 1502 /**
<> 134:ad3be0349dc5 1503 * @brief Get parameter common to several ADC: measurement path to internal
<> 134:ad3be0349dc5 1504 * channels (VrefInt, temperature sensor, ...).
<> 134:ad3be0349dc5 1505 * @note One or several values can be selected.
<> 134:ad3be0349dc5 1506 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
<> 134:ad3be0349dc5 1507 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
<> 134:ad3be0349dc5 1508 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
<> 134:ad3be0349dc5 1509 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
<> 134:ad3be0349dc5 1510 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
<> 134:ad3be0349dc5 1511 * @param ADCxy_COMMON ADC common instance
<> 134:ad3be0349dc5 1512 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<> 134:ad3be0349dc5 1513 * @retval Returned value can be a combination of the following values:
<> 134:ad3be0349dc5 1514 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
<> 134:ad3be0349dc5 1515 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
<> 134:ad3be0349dc5 1516 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
<> 134:ad3be0349dc5 1517 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT (1)
<> 134:ad3be0349dc5 1518 *
<> 134:ad3be0349dc5 1519 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<> 134:ad3be0349dc5 1520 */
<> 134:ad3be0349dc5 1521 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
<> 134:ad3be0349dc5 1522 {
<> 134:ad3be0349dc5 1523 #if defined(ADC_CCR_VBATEN)
<> 134:ad3be0349dc5 1524 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
<> 134:ad3be0349dc5 1525 #else
<> 134:ad3be0349dc5 1526 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN));
<> 134:ad3be0349dc5 1527 #endif
<> 134:ad3be0349dc5 1528 }
<> 134:ad3be0349dc5 1529
<> 134:ad3be0349dc5 1530 /**
<> 134:ad3be0349dc5 1531 * @}
<> 134:ad3be0349dc5 1532 */
<> 134:ad3be0349dc5 1533
<> 134:ad3be0349dc5 1534 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
<> 134:ad3be0349dc5 1535 * @{
<> 134:ad3be0349dc5 1536 */
<> 134:ad3be0349dc5 1537
<> 134:ad3be0349dc5 1538 /**
<> 134:ad3be0349dc5 1539 * @brief Set ADC instance clock source and prescaler.
<> 134:ad3be0349dc5 1540 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 1541 * ADC state:
<> 134:ad3be0349dc5 1542 * ADC must be disabled.
<> 134:ad3be0349dc5 1543 * @rmtoll CFGR2 CKMODE LL_ADC_SetClock
<> 134:ad3be0349dc5 1544 * @param ADCx ADC instance
<> 134:ad3be0349dc5 1545 * @param ClockSource This parameter can be one of the following values:
<> 134:ad3be0349dc5 1546 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
<> 134:ad3be0349dc5 1547 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
<> 134:ad3be0349dc5 1548 * @arg @ref LL_ADC_CLOCK_ASYNC (1)
<> 134:ad3be0349dc5 1549 *
<> 134:ad3be0349dc5 1550 * (1) On this STM32 serie, synchronous clock has no prescaler.
<> 134:ad3be0349dc5 1551 * @retval None
<> 134:ad3be0349dc5 1552 */
<> 134:ad3be0349dc5 1553 __STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource)
<> 134:ad3be0349dc5 1554 {
<> 134:ad3be0349dc5 1555 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource);
<> 134:ad3be0349dc5 1556 }
<> 134:ad3be0349dc5 1557
<> 134:ad3be0349dc5 1558 /**
<> 134:ad3be0349dc5 1559 * @brief Get ADC instance clock source and prescaler.
<> 134:ad3be0349dc5 1560 * @rmtoll CFGR2 CKMODE LL_ADC_GetClock
<> 134:ad3be0349dc5 1561 * @param ADCx ADC instance
<> 134:ad3be0349dc5 1562 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1563 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
<> 134:ad3be0349dc5 1564 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
<> 134:ad3be0349dc5 1565 * @arg @ref LL_ADC_CLOCK_ASYNC (1)
<> 134:ad3be0349dc5 1566 *
<> 134:ad3be0349dc5 1567 * (1) On this STM32 serie, synchronous clock has no prescaler.
<> 134:ad3be0349dc5 1568 */
<> 134:ad3be0349dc5 1569 __STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 1570 {
<> 134:ad3be0349dc5 1571 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE));
<> 134:ad3be0349dc5 1572 }
<> 134:ad3be0349dc5 1573
<> 134:ad3be0349dc5 1574 /**
<> 134:ad3be0349dc5 1575 * @brief Set ADC resolution.
<> 134:ad3be0349dc5 1576 * Refer to reference manual for alignments formats
<> 134:ad3be0349dc5 1577 * dependencies to ADC resolutions.
<> 134:ad3be0349dc5 1578 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 1579 * ADC state:
<> 134:ad3be0349dc5 1580 * ADC must be disabled or enabled without conversion on going
<> 134:ad3be0349dc5 1581 * on group regular.
<> 134:ad3be0349dc5 1582 * @rmtoll CFGR1 RES LL_ADC_SetResolution
<> 134:ad3be0349dc5 1583 * @param ADCx ADC instance
<> 134:ad3be0349dc5 1584 * @param Resolution This parameter can be one of the following values:
<> 134:ad3be0349dc5 1585 * @arg @ref LL_ADC_RESOLUTION_12B
<> 134:ad3be0349dc5 1586 * @arg @ref LL_ADC_RESOLUTION_10B
<> 134:ad3be0349dc5 1587 * @arg @ref LL_ADC_RESOLUTION_8B
<> 134:ad3be0349dc5 1588 * @arg @ref LL_ADC_RESOLUTION_6B
<> 134:ad3be0349dc5 1589 * @retval None
<> 134:ad3be0349dc5 1590 */
<> 134:ad3be0349dc5 1591 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
<> 134:ad3be0349dc5 1592 {
<> 134:ad3be0349dc5 1593 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
<> 134:ad3be0349dc5 1594 }
<> 134:ad3be0349dc5 1595
<> 134:ad3be0349dc5 1596 /**
<> 134:ad3be0349dc5 1597 * @brief Get ADC resolution.
<> 134:ad3be0349dc5 1598 * Refer to reference manual for alignments formats
<> 134:ad3be0349dc5 1599 * dependencies to ADC resolutions.
<> 134:ad3be0349dc5 1600 * @rmtoll CFGR1 RES LL_ADC_GetResolution
<> 134:ad3be0349dc5 1601 * @param ADCx ADC instance
<> 134:ad3be0349dc5 1602 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1603 * @arg @ref LL_ADC_RESOLUTION_12B
<> 134:ad3be0349dc5 1604 * @arg @ref LL_ADC_RESOLUTION_10B
<> 134:ad3be0349dc5 1605 * @arg @ref LL_ADC_RESOLUTION_8B
<> 134:ad3be0349dc5 1606 * @arg @ref LL_ADC_RESOLUTION_6B
<> 134:ad3be0349dc5 1607 */
<> 134:ad3be0349dc5 1608 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 1609 {
<> 134:ad3be0349dc5 1610 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
<> 134:ad3be0349dc5 1611 }
<> 134:ad3be0349dc5 1612
<> 134:ad3be0349dc5 1613 /**
<> 134:ad3be0349dc5 1614 * @brief Set ADC conversion data alignment.
<> 134:ad3be0349dc5 1615 * @note Refer to reference manual for alignments formats
<> 134:ad3be0349dc5 1616 * dependencies to ADC resolutions.
<> 134:ad3be0349dc5 1617 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 1618 * ADC state:
<> 134:ad3be0349dc5 1619 * ADC must be disabled or enabled without conversion on going
<> 134:ad3be0349dc5 1620 * on group regular.
<> 134:ad3be0349dc5 1621 * @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment
<> 134:ad3be0349dc5 1622 * @param ADCx ADC instance
<> 134:ad3be0349dc5 1623 * @param DataAlignment This parameter can be one of the following values:
<> 134:ad3be0349dc5 1624 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
<> 134:ad3be0349dc5 1625 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
<> 134:ad3be0349dc5 1626 * @retval None
<> 134:ad3be0349dc5 1627 */
<> 134:ad3be0349dc5 1628 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
<> 134:ad3be0349dc5 1629 {
<> 134:ad3be0349dc5 1630 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);
<> 134:ad3be0349dc5 1631 }
<> 134:ad3be0349dc5 1632
<> 134:ad3be0349dc5 1633 /**
<> 134:ad3be0349dc5 1634 * @brief Get ADC conversion data alignment.
<> 134:ad3be0349dc5 1635 * @note Refer to reference manual for alignments formats
<> 134:ad3be0349dc5 1636 * dependencies to ADC resolutions.
<> 134:ad3be0349dc5 1637 * @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment
<> 134:ad3be0349dc5 1638 * @param ADCx ADC instance
<> 134:ad3be0349dc5 1639 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1640 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
<> 134:ad3be0349dc5 1641 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
<> 134:ad3be0349dc5 1642 */
<> 134:ad3be0349dc5 1643 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 1644 {
<> 134:ad3be0349dc5 1645 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));
<> 134:ad3be0349dc5 1646 }
<> 134:ad3be0349dc5 1647
<> 134:ad3be0349dc5 1648 /**
<> 134:ad3be0349dc5 1649 * @brief Set ADC low power mode.
<> 134:ad3be0349dc5 1650 * @note Description of ADC low power modes:
<> 134:ad3be0349dc5 1651 * - ADC low power mode "auto wait": Dynamic low power mode,
<> 134:ad3be0349dc5 1652 * ADC conversions occurrences are limited to the minimum necessary
<> 134:ad3be0349dc5 1653 * in order to reduce power consumption.
<> 134:ad3be0349dc5 1654 * New ADC conversion starts only when the previous
<> 134:ad3be0349dc5 1655 * unitary conversion data (for ADC group regular)
<> 134:ad3be0349dc5 1656 * has been retrieved by user software.
<> 134:ad3be0349dc5 1657 * In the meantime, ADC remains idle: does not performs any
<> 134:ad3be0349dc5 1658 * other conversion.
<> 134:ad3be0349dc5 1659 * This mode allows to automatically adapt the ADC conversions
<> 134:ad3be0349dc5 1660 * triggers to the speed of the software that reads the data.
<> 134:ad3be0349dc5 1661 * Moreover, this avoids risk of overrun for low frequency
<> 134:ad3be0349dc5 1662 * applications.
<> 134:ad3be0349dc5 1663 * How to use this low power mode:
<> 134:ad3be0349dc5 1664 * - Do not use with interruption or DMA since these modes
<> 134:ad3be0349dc5 1665 * have to clear immediately the EOC flag to free the
<> 134:ad3be0349dc5 1666 * IRQ vector sequencer.
<> 134:ad3be0349dc5 1667 * - Do use with polling: 1. Start conversion,
<> 134:ad3be0349dc5 1668 * 2. Later on, when conversion data is needed: poll for end of
<> 134:ad3be0349dc5 1669 * conversion to ensure that conversion is completed and
<> 134:ad3be0349dc5 1670 * retrieve ADC conversion data. This will trig another
<> 134:ad3be0349dc5 1671 * ADC conversion start.
<> 134:ad3be0349dc5 1672 * - ADC low power mode "auto power-off" (feature available on
<> 134:ad3be0349dc5 1673 * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
<> 134:ad3be0349dc5 1674 * the ADC automatically powers-off after a conversion and
<> 134:ad3be0349dc5 1675 * automatically wakes up when a new conversion is triggered
<> 134:ad3be0349dc5 1676 * (with startup time between trigger and start of sampling).
<> 134:ad3be0349dc5 1677 * This feature can be combined with low power mode "auto wait".
<> 134:ad3be0349dc5 1678 * @note With ADC low power mode "auto wait", the ADC conversion data read
<> 134:ad3be0349dc5 1679 * is corresponding to previous ADC conversion start, independently
<> 134:ad3be0349dc5 1680 * of delay during which ADC was idle.
<> 134:ad3be0349dc5 1681 * Therefore, the ADC conversion data may be outdated: does not
<> 134:ad3be0349dc5 1682 * correspond to the current voltage level on the selected
<> 134:ad3be0349dc5 1683 * ADC channel.
<> 134:ad3be0349dc5 1684 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 1685 * ADC state:
<> 134:ad3be0349dc5 1686 * ADC must be disabled or enabled without conversion on going
<> 134:ad3be0349dc5 1687 * on group regular.
<> 134:ad3be0349dc5 1688 * @rmtoll CFGR1 WAIT LL_ADC_SetLowPowerMode\n
<> 134:ad3be0349dc5 1689 * CFGR1 AUTOFF LL_ADC_SetLowPowerMode
<> 134:ad3be0349dc5 1690 * @param ADCx ADC instance
<> 134:ad3be0349dc5 1691 * @param LowPowerMode This parameter can be one of the following values:
<> 134:ad3be0349dc5 1692 * @arg @ref LL_ADC_LP_MODE_NONE
<> 134:ad3be0349dc5 1693 * @arg @ref LL_ADC_LP_AUTOWAIT
<> 134:ad3be0349dc5 1694 * @arg @ref LL_ADC_LP_AUTOPOWEROFF
<> 134:ad3be0349dc5 1695 * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
<> 134:ad3be0349dc5 1696 * @retval None
<> 134:ad3be0349dc5 1697 */
<> 134:ad3be0349dc5 1698 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
<> 134:ad3be0349dc5 1699 {
<> 134:ad3be0349dc5 1700 MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode);
<> 134:ad3be0349dc5 1701 }
<> 134:ad3be0349dc5 1702
<> 134:ad3be0349dc5 1703 /**
<> 134:ad3be0349dc5 1704 * @brief Get ADC low power mode:
<> 134:ad3be0349dc5 1705 * @note Description of ADC low power modes:
<> 134:ad3be0349dc5 1706 * - ADC low power mode "auto wait": Dynamic low power mode,
<> 134:ad3be0349dc5 1707 * ADC conversions occurrences are limited to the minimum necessary
<> 134:ad3be0349dc5 1708 * in order to reduce power consumption.
<> 134:ad3be0349dc5 1709 * New ADC conversion starts only when the previous
<> 134:ad3be0349dc5 1710 * unitary conversion data (for ADC group regular)
<> 134:ad3be0349dc5 1711 * has been retrieved by user software.
<> 134:ad3be0349dc5 1712 * In the meantime, ADC remains idle: does not performs any
<> 134:ad3be0349dc5 1713 * other conversion.
<> 134:ad3be0349dc5 1714 * This mode allows to automatically adapt the ADC conversions
<> 134:ad3be0349dc5 1715 * triggers to the speed of the software that reads the data.
<> 134:ad3be0349dc5 1716 * Moreover, this avoids risk of overrun for low frequency
<> 134:ad3be0349dc5 1717 * applications.
<> 134:ad3be0349dc5 1718 * How to use this low power mode:
<> 134:ad3be0349dc5 1719 * - Do not use with interruption or DMA since these modes
<> 134:ad3be0349dc5 1720 * have to clear immediately the EOC flag to free the
<> 134:ad3be0349dc5 1721 * IRQ vector sequencer.
<> 134:ad3be0349dc5 1722 * - Do use with polling: 1. Start conversion,
<> 134:ad3be0349dc5 1723 * 2. Later on, when conversion data is needed: poll for end of
<> 134:ad3be0349dc5 1724 * conversion to ensure that conversion is completed and
<> 134:ad3be0349dc5 1725 * retrieve ADC conversion data. This will trig another
<> 134:ad3be0349dc5 1726 * ADC conversion start.
<> 134:ad3be0349dc5 1727 * - ADC low power mode "auto power-off" (feature available on
<> 134:ad3be0349dc5 1728 * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
<> 134:ad3be0349dc5 1729 * the ADC automatically powers-off after a conversion and
<> 134:ad3be0349dc5 1730 * automatically wakes up when a new conversion is triggered
<> 134:ad3be0349dc5 1731 * (with startup time between trigger and start of sampling).
<> 134:ad3be0349dc5 1732 * This feature can be combined with low power mode "auto wait".
<> 134:ad3be0349dc5 1733 * @note With ADC low power mode "auto wait", the ADC conversion data read
<> 134:ad3be0349dc5 1734 * is corresponding to previous ADC conversion start, independently
<> 134:ad3be0349dc5 1735 * of delay during which ADC was idle.
<> 134:ad3be0349dc5 1736 * Therefore, the ADC conversion data may be outdated: does not
<> 134:ad3be0349dc5 1737 * correspond to the current voltage level on the selected
<> 134:ad3be0349dc5 1738 * ADC channel.
<> 134:ad3be0349dc5 1739 * @rmtoll CFGR1 WAIT LL_ADC_GetLowPowerMode\n
<> 134:ad3be0349dc5 1740 * CFGR1 AUTOFF LL_ADC_GetLowPowerMode
<> 134:ad3be0349dc5 1741 * @param ADCx ADC instance
<> 134:ad3be0349dc5 1742 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1743 * @arg @ref LL_ADC_LP_MODE_NONE
<> 134:ad3be0349dc5 1744 * @arg @ref LL_ADC_LP_AUTOWAIT
<> 134:ad3be0349dc5 1745 * @arg @ref LL_ADC_LP_AUTOPOWEROFF
<> 134:ad3be0349dc5 1746 * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
<> 134:ad3be0349dc5 1747 */
<> 134:ad3be0349dc5 1748 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 1749 {
<> 134:ad3be0349dc5 1750 return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF)));
<> 134:ad3be0349dc5 1751 }
<> 134:ad3be0349dc5 1752
<> 134:ad3be0349dc5 1753 /**
<> 134:ad3be0349dc5 1754 * @brief Set sampling time common to a group of channels.
<> 134:ad3be0349dc5 1755 * @note Unit: ADC clock cycles.
<> 134:ad3be0349dc5 1756 * @note On this STM32 serie, sampling time scope is on ADC instance:
<> 134:ad3be0349dc5 1757 * Sampling time common to all channels.
<> 134:ad3be0349dc5 1758 * (on some other STM32 families, sampling time is channel wise)
<> 134:ad3be0349dc5 1759 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
<> 134:ad3be0349dc5 1760 * converted:
<> 134:ad3be0349dc5 1761 * sampling time constraints must be respected (sampling time can be
<> 134:ad3be0349dc5 1762 * adjusted in function of ADC clock frequency and sampling time
<> 134:ad3be0349dc5 1763 * setting).
<> 134:ad3be0349dc5 1764 * Refer to device datasheet for timings values (parameters TS_vrefint,
<> 134:ad3be0349dc5 1765 * TS_temp, ...).
<> 134:ad3be0349dc5 1766 * @note Conversion time is the addition of sampling time and processing time.
<> 134:ad3be0349dc5 1767 * On this STM32 serie, ADC processing time is:
<> 134:ad3be0349dc5 1768 * - 12.5 ADC clock cycles at ADC resolution 12 bits
<> 134:ad3be0349dc5 1769 * - 10.5 ADC clock cycles at ADC resolution 10 bits
<> 134:ad3be0349dc5 1770 * - 8.5 ADC clock cycles at ADC resolution 8 bits
<> 134:ad3be0349dc5 1771 * - 6.5 ADC clock cycles at ADC resolution 6 bits
<> 134:ad3be0349dc5 1772 * @note In case of ADC conversion of internal channel (VrefInt,
<> 134:ad3be0349dc5 1773 * temperature sensor, ...), a sampling time minimum value
<> 134:ad3be0349dc5 1774 * is required.
<> 134:ad3be0349dc5 1775 * Refer to device datasheet.
<> 134:ad3be0349dc5 1776 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 1777 * ADC state:
<> 134:ad3be0349dc5 1778 * ADC must be disabled or enabled without conversion on going
<> 134:ad3be0349dc5 1779 * on group regular.
<> 134:ad3be0349dc5 1780 * @rmtoll SMPR SMP LL_ADC_SetSamplingTimeCommonChannels
<> 134:ad3be0349dc5 1781 * @param ADCx ADC instance
<> 134:ad3be0349dc5 1782 * @param SamplingTime This parameter can be one of the following values:
<> 134:ad3be0349dc5 1783 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
<> 134:ad3be0349dc5 1784 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
<> 134:ad3be0349dc5 1785 * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
<> 134:ad3be0349dc5 1786 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
<> 134:ad3be0349dc5 1787 * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
<> 134:ad3be0349dc5 1788 * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
<> 134:ad3be0349dc5 1789 * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
<> 134:ad3be0349dc5 1790 * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
<> 134:ad3be0349dc5 1791 * @retval None
<> 134:ad3be0349dc5 1792 */
<> 134:ad3be0349dc5 1793 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTime)
<> 134:ad3be0349dc5 1794 {
<> 134:ad3be0349dc5 1795 MODIFY_REG(ADCx->SMPR, ADC_SMPR_SMP, SamplingTime);
<> 134:ad3be0349dc5 1796 }
<> 134:ad3be0349dc5 1797
<> 134:ad3be0349dc5 1798 /**
<> 134:ad3be0349dc5 1799 * @brief Get sampling time common to a group of channels.
<> 134:ad3be0349dc5 1800 * @note Unit: ADC clock cycles.
<> 134:ad3be0349dc5 1801 * @note On this STM32 serie, sampling time scope is on ADC instance:
<> 134:ad3be0349dc5 1802 * Sampling time common to all channels.
<> 134:ad3be0349dc5 1803 * (on some other STM32 families, sampling time is channel wise)
<> 134:ad3be0349dc5 1804 * @note Conversion time is the addition of sampling time and processing time.
<> 134:ad3be0349dc5 1805 * Refer to reference manual for ADC processing time of
<> 134:ad3be0349dc5 1806 * this STM32 serie.
<> 134:ad3be0349dc5 1807 * @rmtoll SMPR SMP LL_ADC_GetSamplingTimeCommonChannels
<> 134:ad3be0349dc5 1808 * @param ADCx ADC instance
<> 134:ad3be0349dc5 1809 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1810 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
<> 134:ad3be0349dc5 1811 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
<> 134:ad3be0349dc5 1812 * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
<> 134:ad3be0349dc5 1813 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
<> 134:ad3be0349dc5 1814 * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
<> 134:ad3be0349dc5 1815 * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
<> 134:ad3be0349dc5 1816 * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
<> 134:ad3be0349dc5 1817 * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
<> 134:ad3be0349dc5 1818 */
<> 134:ad3be0349dc5 1819 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 1820 {
<> 134:ad3be0349dc5 1821 return (uint32_t)(READ_BIT(ADCx->SMPR, ADC_SMPR_SMP));
<> 134:ad3be0349dc5 1822 }
<> 134:ad3be0349dc5 1823
<> 134:ad3be0349dc5 1824 /**
<> 134:ad3be0349dc5 1825 * @}
<> 134:ad3be0349dc5 1826 */
<> 134:ad3be0349dc5 1827
<> 134:ad3be0349dc5 1828 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
<> 134:ad3be0349dc5 1829 * @{
<> 134:ad3be0349dc5 1830 */
<> 134:ad3be0349dc5 1831
<> 134:ad3be0349dc5 1832 /**
<> 134:ad3be0349dc5 1833 * @brief Set ADC group regular conversion trigger source:
<> 134:ad3be0349dc5 1834 * internal (SW start) or from external IP (timer event,
<> 134:ad3be0349dc5 1835 * external interrupt line).
<> 134:ad3be0349dc5 1836 * @note On this STM32 serie, setting trigger source to external trigger
<> 134:ad3be0349dc5 1837 * also set trigger polarity to rising edge
<> 134:ad3be0349dc5 1838 * (default setting for compatibility with some ADC on other
<> 134:ad3be0349dc5 1839 * STM32 families having this setting set by HW default value).
<> 134:ad3be0349dc5 1840 * In case of need to modify trigger edge, use
<> 134:ad3be0349dc5 1841 * function @ref LL_ADC_REG_SetTriggerEdge().
<> 134:ad3be0349dc5 1842 * @note Availability of parameters of trigger sources from timer
<> 134:ad3be0349dc5 1843 * depends on timers availability on the selected device.
<> 134:ad3be0349dc5 1844 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 1845 * ADC state:
<> 134:ad3be0349dc5 1846 * ADC must be disabled or enabled without conversion on going
<> 134:ad3be0349dc5 1847 * on group regular.
<> 134:ad3be0349dc5 1848 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n
<> 134:ad3be0349dc5 1849 * CFGR1 EXTEN LL_ADC_REG_SetTriggerSource
<> 134:ad3be0349dc5 1850 * @param ADCx ADC instance
<> 134:ad3be0349dc5 1851 * @param TriggerSource This parameter can be one of the following values:
<> 134:ad3be0349dc5 1852 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
<> 134:ad3be0349dc5 1853 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
<> 134:ad3be0349dc5 1854 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
<> 134:ad3be0349dc5 1855 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1)
<> 134:ad3be0349dc5 1856 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
<> 134:ad3be0349dc5 1857 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (1)
<> 134:ad3be0349dc5 1858 *
<> 134:ad3be0349dc5 1859 * (1) On STM32F0, parameter not available on all devices
<> 134:ad3be0349dc5 1860 * @retval None
<> 134:ad3be0349dc5 1861 */
<> 134:ad3be0349dc5 1862 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
<> 134:ad3be0349dc5 1863 {
<> 134:ad3be0349dc5 1864 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
<> 134:ad3be0349dc5 1865 }
<> 134:ad3be0349dc5 1866
<> 134:ad3be0349dc5 1867 /**
<> 134:ad3be0349dc5 1868 * @brief Get ADC group regular conversion trigger source:
<> 134:ad3be0349dc5 1869 * internal (SW start) or from external IP (timer event,
<> 134:ad3be0349dc5 1870 * external interrupt line).
<> 134:ad3be0349dc5 1871 * @note To determine whether group regular trigger source is
<> 134:ad3be0349dc5 1872 * internal (SW start) or external, without detail
<> 134:ad3be0349dc5 1873 * of which peripheral is selected as external trigger,
<> 134:ad3be0349dc5 1874 * (equivalent to
<> 134:ad3be0349dc5 1875 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
<> 134:ad3be0349dc5 1876 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
<> 134:ad3be0349dc5 1877 * @note Availability of parameters of trigger sources from timer
<> 134:ad3be0349dc5 1878 * depends on timers availability on the selected device.
<> 134:ad3be0349dc5 1879 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource\n
<> 134:ad3be0349dc5 1880 * CFGR1 EXTEN LL_ADC_REG_GetTriggerSource
<> 134:ad3be0349dc5 1881 * @param ADCx ADC instance
<> 134:ad3be0349dc5 1882 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1883 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
<> 134:ad3be0349dc5 1884 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
<> 134:ad3be0349dc5 1885 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
<> 134:ad3be0349dc5 1886 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1)
<> 134:ad3be0349dc5 1887 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
<> 134:ad3be0349dc5 1888 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (1)
<> 134:ad3be0349dc5 1889 *
<> 134:ad3be0349dc5 1890 * (1) On STM32F0, parameter not available on all devices
<> 134:ad3be0349dc5 1891 */
<> 134:ad3be0349dc5 1892 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 1893 {
<> 134:ad3be0349dc5 1894 register uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
<> 134:ad3be0349dc5 1895
<> 134:ad3be0349dc5 1896 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
<> 134:ad3be0349dc5 1897 /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */
<> 134:ad3be0349dc5 1898 register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
<> 134:ad3be0349dc5 1899
<> 134:ad3be0349dc5 1900 /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */
<> 134:ad3be0349dc5 1901 /* to match with triggers literals definition. */
<> 134:ad3be0349dc5 1902 return ((TriggerSource
<> 134:ad3be0349dc5 1903 & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL)
<> 134:ad3be0349dc5 1904 | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN)
<> 134:ad3be0349dc5 1905 );
<> 134:ad3be0349dc5 1906 }
<> 134:ad3be0349dc5 1907
<> 134:ad3be0349dc5 1908 /**
<> 134:ad3be0349dc5 1909 * @brief Get ADC group regular conversion trigger source internal (SW start)
<> 134:ad3be0349dc5 1910 or external.
<> 134:ad3be0349dc5 1911 * @note In case of group regular trigger source set to external trigger,
<> 134:ad3be0349dc5 1912 * to determine which peripheral is selected as external trigger,
<> 134:ad3be0349dc5 1913 * use function @ref LL_ADC_REG_GetTriggerSource().
<> 134:ad3be0349dc5 1914 * @rmtoll CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
<> 134:ad3be0349dc5 1915 * @param ADCx ADC instance
<> 134:ad3be0349dc5 1916 * @retval Value "0" if trigger source external trigger
<> 134:ad3be0349dc5 1917 * Value "1" if trigger source SW start.
<> 134:ad3be0349dc5 1918 */
<> 134:ad3be0349dc5 1919 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 1920 {
<> 134:ad3be0349dc5 1921 return (READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN));
<> 134:ad3be0349dc5 1922 }
<> 134:ad3be0349dc5 1923
<> 134:ad3be0349dc5 1924 /**
<> 134:ad3be0349dc5 1925 * @brief Set ADC group regular conversion trigger polarity.
<> 134:ad3be0349dc5 1926 * @note Applicable only for trigger source set to external trigger.
<> 134:ad3be0349dc5 1927 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 1928 * ADC state:
<> 134:ad3be0349dc5 1929 * ADC must be disabled or enabled without conversion on going
<> 134:ad3be0349dc5 1930 * on group regular.
<> 134:ad3be0349dc5 1931 * @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge
<> 134:ad3be0349dc5 1932 * @param ADCx ADC instance
<> 134:ad3be0349dc5 1933 * @param ExternalTriggerEdge This parameter can be one of the following values:
<> 134:ad3be0349dc5 1934 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
<> 134:ad3be0349dc5 1935 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
<> 134:ad3be0349dc5 1936 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
<> 134:ad3be0349dc5 1937 * @retval None
<> 134:ad3be0349dc5 1938 */
<> 134:ad3be0349dc5 1939 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
<> 134:ad3be0349dc5 1940 {
<> 134:ad3be0349dc5 1941 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
<> 134:ad3be0349dc5 1942 }
<> 134:ad3be0349dc5 1943
<> 134:ad3be0349dc5 1944 /**
<> 134:ad3be0349dc5 1945 * @brief Get ADC group regular conversion trigger polarity.
<> 134:ad3be0349dc5 1946 * @note Applicable only for trigger source set to external trigger.
<> 134:ad3be0349dc5 1947 * @rmtoll CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge
<> 134:ad3be0349dc5 1948 * @param ADCx ADC instance
<> 134:ad3be0349dc5 1949 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1950 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
<> 134:ad3be0349dc5 1951 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
<> 134:ad3be0349dc5 1952 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
<> 134:ad3be0349dc5 1953 */
<> 134:ad3be0349dc5 1954 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 1955 {
<> 134:ad3be0349dc5 1956 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
<> 134:ad3be0349dc5 1957 }
<> 134:ad3be0349dc5 1958
<> 134:ad3be0349dc5 1959
<> 134:ad3be0349dc5 1960 /**
<> 134:ad3be0349dc5 1961 * @brief Set ADC group regular sequencer scan direction.
<> 134:ad3be0349dc5 1962 * @note On some other STM32 families, this setting is not available and
<> 134:ad3be0349dc5 1963 * the default scan direction is forward.
<> 134:ad3be0349dc5 1964 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 1965 * ADC state:
<> 134:ad3be0349dc5 1966 * ADC must be disabled or enabled without conversion on going
<> 134:ad3be0349dc5 1967 * on group regular.
<> 134:ad3be0349dc5 1968 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection
<> 134:ad3be0349dc5 1969 * @param ADCx ADC instance
<> 134:ad3be0349dc5 1970 * @param ScanDirection This parameter can be one of the following values:
<> 134:ad3be0349dc5 1971 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
<> 134:ad3be0349dc5 1972 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
<> 134:ad3be0349dc5 1973 * @retval None
<> 134:ad3be0349dc5 1974 */
<> 134:ad3be0349dc5 1975 __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
<> 134:ad3be0349dc5 1976 {
<> 134:ad3be0349dc5 1977 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection);
<> 134:ad3be0349dc5 1978 }
<> 134:ad3be0349dc5 1979
<> 134:ad3be0349dc5 1980 /**
<> 134:ad3be0349dc5 1981 * @brief Get ADC group regular sequencer scan direction.
<> 134:ad3be0349dc5 1982 * @note On some other STM32 families, this setting is not available and
<> 134:ad3be0349dc5 1983 * the default scan direction is forward.
<> 134:ad3be0349dc5 1984 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection
<> 134:ad3be0349dc5 1985 * @param ADCx ADC instance
<> 134:ad3be0349dc5 1986 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 1987 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
<> 134:ad3be0349dc5 1988 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
<> 134:ad3be0349dc5 1989 */
<> 134:ad3be0349dc5 1990 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 1991 {
<> 134:ad3be0349dc5 1992 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));
<> 134:ad3be0349dc5 1993 }
<> 134:ad3be0349dc5 1994
<> 134:ad3be0349dc5 1995 /**
<> 134:ad3be0349dc5 1996 * @brief Set ADC group regular sequencer discontinuous mode:
<> 134:ad3be0349dc5 1997 * sequence subdivided and scan conversions interrupted every selected
<> 134:ad3be0349dc5 1998 * number of ranks.
<> 134:ad3be0349dc5 1999 * @note It is not possible to enable both ADC group regular
<> 134:ad3be0349dc5 2000 * continuous mode and sequencer discontinuous mode.
<> 134:ad3be0349dc5 2001 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 2002 * ADC state:
<> 134:ad3be0349dc5 2003 * ADC must be disabled or enabled without conversion on going
<> 134:ad3be0349dc5 2004 * on group regular.
<> 134:ad3be0349dc5 2005 * @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
<> 134:ad3be0349dc5 2006 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2007 * @param SeqDiscont This parameter can be one of the following values:
<> 134:ad3be0349dc5 2008 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
<> 134:ad3be0349dc5 2009 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
<> 134:ad3be0349dc5 2010 * @retval None
<> 134:ad3be0349dc5 2011 */
<> 134:ad3be0349dc5 2012 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
<> 134:ad3be0349dc5 2013 {
<> 134:ad3be0349dc5 2014 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);
<> 134:ad3be0349dc5 2015 }
<> 134:ad3be0349dc5 2016
<> 134:ad3be0349dc5 2017 /**
<> 134:ad3be0349dc5 2018 * @brief Get ADC group regular sequencer discontinuous mode:
<> 134:ad3be0349dc5 2019 * sequence subdivided and scan conversions interrupted every selected
<> 134:ad3be0349dc5 2020 * number of ranks.
<> 134:ad3be0349dc5 2021 * @rmtoll CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
<> 134:ad3be0349dc5 2022 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2023 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 2024 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
<> 134:ad3be0349dc5 2025 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
<> 134:ad3be0349dc5 2026 */
<> 134:ad3be0349dc5 2027 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 2028 {
<> 134:ad3be0349dc5 2029 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));
<> 134:ad3be0349dc5 2030 }
<> 134:ad3be0349dc5 2031
<> 134:ad3be0349dc5 2032 /**
<> 134:ad3be0349dc5 2033 * @brief Set ADC group regular sequence: channel on rank corresponding to
<> 134:ad3be0349dc5 2034 * channel number.
<> 134:ad3be0349dc5 2035 * @note This function performs:
<> 134:ad3be0349dc5 2036 * - Channels ordering into each rank of scan sequence:
<> 134:ad3be0349dc5 2037 * rank of each channel is fixed by channel HW number
<> 134:ad3be0349dc5 2038 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
<> 134:ad3be0349dc5 2039 * - Set channels selected by overwriting the current sequencer
<> 134:ad3be0349dc5 2040 * configuration.
<> 134:ad3be0349dc5 2041 * @note On this STM32 serie, ADC group regular sequencer is
<> 134:ad3be0349dc5 2042 * not fully configurable: sequencer length and each rank
<> 134:ad3be0349dc5 2043 * affectation to a channel are fixed by channel HW number.
<> 134:ad3be0349dc5 2044 * @note Depending on devices and packages, some channels may not be available.
<> 134:ad3be0349dc5 2045 * Refer to device datasheet for channels availability.
<> 134:ad3be0349dc5 2046 * @note On this STM32 serie, to measure internal channels (VrefInt,
<> 134:ad3be0349dc5 2047 * TempSensor, ...), measurement paths to internal channels must be
<> 134:ad3be0349dc5 2048 * enabled separately.
<> 134:ad3be0349dc5 2049 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
<> 134:ad3be0349dc5 2050 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 2051 * ADC state:
<> 134:ad3be0349dc5 2052 * ADC must be disabled or enabled without conversion on going
<> 134:ad3be0349dc5 2053 * on group regular.
<> 134:ad3be0349dc5 2054 * @note One or several values can be selected.
<> 134:ad3be0349dc5 2055 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
<> 134:ad3be0349dc5 2056 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n
<> 134:ad3be0349dc5 2057 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n
<> 134:ad3be0349dc5 2058 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n
<> 134:ad3be0349dc5 2059 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n
<> 134:ad3be0349dc5 2060 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n
<> 134:ad3be0349dc5 2061 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n
<> 134:ad3be0349dc5 2062 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n
<> 134:ad3be0349dc5 2063 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n
<> 134:ad3be0349dc5 2064 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n
<> 134:ad3be0349dc5 2065 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n
<> 134:ad3be0349dc5 2066 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n
<> 134:ad3be0349dc5 2067 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n
<> 134:ad3be0349dc5 2068 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n
<> 134:ad3be0349dc5 2069 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n
<> 134:ad3be0349dc5 2070 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n
<> 134:ad3be0349dc5 2071 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n
<> 134:ad3be0349dc5 2072 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n
<> 134:ad3be0349dc5 2073 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n
<> 134:ad3be0349dc5 2074 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels
<> 134:ad3be0349dc5 2075 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2076 * @param Channel This parameter can be a combination of the following values:
<> 134:ad3be0349dc5 2077 * @arg @ref LL_ADC_CHANNEL_0
<> 134:ad3be0349dc5 2078 * @arg @ref LL_ADC_CHANNEL_1
<> 134:ad3be0349dc5 2079 * @arg @ref LL_ADC_CHANNEL_2
<> 134:ad3be0349dc5 2080 * @arg @ref LL_ADC_CHANNEL_3
<> 134:ad3be0349dc5 2081 * @arg @ref LL_ADC_CHANNEL_4
<> 134:ad3be0349dc5 2082 * @arg @ref LL_ADC_CHANNEL_5
<> 134:ad3be0349dc5 2083 * @arg @ref LL_ADC_CHANNEL_6
<> 134:ad3be0349dc5 2084 * @arg @ref LL_ADC_CHANNEL_7
<> 134:ad3be0349dc5 2085 * @arg @ref LL_ADC_CHANNEL_8
<> 134:ad3be0349dc5 2086 * @arg @ref LL_ADC_CHANNEL_9
<> 134:ad3be0349dc5 2087 * @arg @ref LL_ADC_CHANNEL_10
<> 134:ad3be0349dc5 2088 * @arg @ref LL_ADC_CHANNEL_11
<> 134:ad3be0349dc5 2089 * @arg @ref LL_ADC_CHANNEL_12
<> 134:ad3be0349dc5 2090 * @arg @ref LL_ADC_CHANNEL_13
<> 134:ad3be0349dc5 2091 * @arg @ref LL_ADC_CHANNEL_14
<> 134:ad3be0349dc5 2092 * @arg @ref LL_ADC_CHANNEL_15
<> 134:ad3be0349dc5 2093 * @arg @ref LL_ADC_CHANNEL_16
<> 134:ad3be0349dc5 2094 * @arg @ref LL_ADC_CHANNEL_17
<> 134:ad3be0349dc5 2095 * @arg @ref LL_ADC_CHANNEL_18 (1)
<> 134:ad3be0349dc5 2096 * @arg @ref LL_ADC_CHANNEL_VREFINT
<> 134:ad3be0349dc5 2097 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
<> 134:ad3be0349dc5 2098 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
<> 134:ad3be0349dc5 2099 *
<> 134:ad3be0349dc5 2100 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<> 134:ad3be0349dc5 2101 * @retval None
<> 134:ad3be0349dc5 2102 */
<> 134:ad3be0349dc5 2103 __STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
<> 134:ad3be0349dc5 2104 {
<> 134:ad3be0349dc5 2105 /* Parameter "Channel" is used with masks because containing */
<> 134:ad3be0349dc5 2106 /* other bits reserved for other purpose. */
<> 134:ad3be0349dc5 2107 WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
<> 134:ad3be0349dc5 2108 }
<> 134:ad3be0349dc5 2109
<> 134:ad3be0349dc5 2110 /**
<> 134:ad3be0349dc5 2111 * @brief Add channel to ADC group regular sequence: channel on rank corresponding to
<> 134:ad3be0349dc5 2112 * channel number.
<> 134:ad3be0349dc5 2113 * @note This function performs:
<> 134:ad3be0349dc5 2114 * - Channels ordering into each rank of scan sequence:
<> 134:ad3be0349dc5 2115 * rank of each channel is fixed by channel HW number
<> 134:ad3be0349dc5 2116 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
<> 134:ad3be0349dc5 2117 * - Set channels selected by adding them to the current sequencer
<> 134:ad3be0349dc5 2118 * configuration.
<> 134:ad3be0349dc5 2119 * @note On this STM32 serie, ADC group regular sequencer is
<> 134:ad3be0349dc5 2120 * not fully configurable: sequencer length and each rank
<> 134:ad3be0349dc5 2121 * affectation to a channel are fixed by channel HW number.
<> 134:ad3be0349dc5 2122 * @note Depending on devices and packages, some channels may not be available.
<> 134:ad3be0349dc5 2123 * Refer to device datasheet for channels availability.
<> 134:ad3be0349dc5 2124 * @note On this STM32 serie, to measure internal channels (VrefInt,
<> 134:ad3be0349dc5 2125 * TempSensor, ...), measurement paths to internal channels must be
<> 134:ad3be0349dc5 2126 * enabled separately.
<> 134:ad3be0349dc5 2127 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
<> 134:ad3be0349dc5 2128 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 2129 * ADC state:
<> 134:ad3be0349dc5 2130 * ADC must be disabled or enabled without conversion on going
<> 134:ad3be0349dc5 2131 * on group regular.
<> 134:ad3be0349dc5 2132 * @note One or several values can be selected.
<> 134:ad3be0349dc5 2133 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
<> 134:ad3be0349dc5 2134 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n
<> 134:ad3be0349dc5 2135 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n
<> 134:ad3be0349dc5 2136 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n
<> 134:ad3be0349dc5 2137 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n
<> 134:ad3be0349dc5 2138 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n
<> 134:ad3be0349dc5 2139 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n
<> 134:ad3be0349dc5 2140 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n
<> 134:ad3be0349dc5 2141 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n
<> 134:ad3be0349dc5 2142 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n
<> 134:ad3be0349dc5 2143 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n
<> 134:ad3be0349dc5 2144 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n
<> 134:ad3be0349dc5 2145 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n
<> 134:ad3be0349dc5 2146 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n
<> 134:ad3be0349dc5 2147 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n
<> 134:ad3be0349dc5 2148 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n
<> 134:ad3be0349dc5 2149 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n
<> 134:ad3be0349dc5 2150 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n
<> 134:ad3be0349dc5 2151 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n
<> 134:ad3be0349dc5 2152 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd
<> 134:ad3be0349dc5 2153 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2154 * @param Channel This parameter can be a combination of the following values:
<> 134:ad3be0349dc5 2155 * @arg @ref LL_ADC_CHANNEL_0
<> 134:ad3be0349dc5 2156 * @arg @ref LL_ADC_CHANNEL_1
<> 134:ad3be0349dc5 2157 * @arg @ref LL_ADC_CHANNEL_2
<> 134:ad3be0349dc5 2158 * @arg @ref LL_ADC_CHANNEL_3
<> 134:ad3be0349dc5 2159 * @arg @ref LL_ADC_CHANNEL_4
<> 134:ad3be0349dc5 2160 * @arg @ref LL_ADC_CHANNEL_5
<> 134:ad3be0349dc5 2161 * @arg @ref LL_ADC_CHANNEL_6
<> 134:ad3be0349dc5 2162 * @arg @ref LL_ADC_CHANNEL_7
<> 134:ad3be0349dc5 2163 * @arg @ref LL_ADC_CHANNEL_8
<> 134:ad3be0349dc5 2164 * @arg @ref LL_ADC_CHANNEL_9
<> 134:ad3be0349dc5 2165 * @arg @ref LL_ADC_CHANNEL_10
<> 134:ad3be0349dc5 2166 * @arg @ref LL_ADC_CHANNEL_11
<> 134:ad3be0349dc5 2167 * @arg @ref LL_ADC_CHANNEL_12
<> 134:ad3be0349dc5 2168 * @arg @ref LL_ADC_CHANNEL_13
<> 134:ad3be0349dc5 2169 * @arg @ref LL_ADC_CHANNEL_14
<> 134:ad3be0349dc5 2170 * @arg @ref LL_ADC_CHANNEL_15
<> 134:ad3be0349dc5 2171 * @arg @ref LL_ADC_CHANNEL_16
<> 134:ad3be0349dc5 2172 * @arg @ref LL_ADC_CHANNEL_17
<> 134:ad3be0349dc5 2173 * @arg @ref LL_ADC_CHANNEL_18 (1)
<> 134:ad3be0349dc5 2174 * @arg @ref LL_ADC_CHANNEL_VREFINT
<> 134:ad3be0349dc5 2175 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
<> 134:ad3be0349dc5 2176 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
<> 134:ad3be0349dc5 2177 *
<> 134:ad3be0349dc5 2178 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<> 134:ad3be0349dc5 2179 * @retval None
<> 134:ad3be0349dc5 2180 */
<> 134:ad3be0349dc5 2181 __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
<> 134:ad3be0349dc5 2182 {
<> 134:ad3be0349dc5 2183 /* Parameter "Channel" is used with masks because containing */
<> 134:ad3be0349dc5 2184 /* other bits reserved for other purpose. */
<> 134:ad3be0349dc5 2185 SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
<> 134:ad3be0349dc5 2186 }
<> 134:ad3be0349dc5 2187
<> 134:ad3be0349dc5 2188 /**
<> 134:ad3be0349dc5 2189 * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to
<> 134:ad3be0349dc5 2190 * channel number.
<> 134:ad3be0349dc5 2191 * @note This function performs:
<> 134:ad3be0349dc5 2192 * - Channels ordering into each rank of scan sequence:
<> 134:ad3be0349dc5 2193 * rank of each channel is fixed by channel HW number
<> 134:ad3be0349dc5 2194 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
<> 134:ad3be0349dc5 2195 * - Set channels selected by removing them to the current sequencer
<> 134:ad3be0349dc5 2196 * configuration.
<> 134:ad3be0349dc5 2197 * @note On this STM32 serie, ADC group regular sequencer is
<> 134:ad3be0349dc5 2198 * not fully configurable: sequencer length and each rank
<> 134:ad3be0349dc5 2199 * affectation to a channel are fixed by channel HW number.
<> 134:ad3be0349dc5 2200 * @note Depending on devices and packages, some channels may not be available.
<> 134:ad3be0349dc5 2201 * Refer to device datasheet for channels availability.
<> 134:ad3be0349dc5 2202 * @note On this STM32 serie, to measure internal channels (VrefInt,
<> 134:ad3be0349dc5 2203 * TempSensor, ...), measurement paths to internal channels must be
<> 134:ad3be0349dc5 2204 * enabled separately.
<> 134:ad3be0349dc5 2205 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
<> 134:ad3be0349dc5 2206 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 2207 * ADC state:
<> 134:ad3be0349dc5 2208 * ADC must be disabled or enabled without conversion on going
<> 134:ad3be0349dc5 2209 * on group regular.
<> 134:ad3be0349dc5 2210 * @note One or several values can be selected.
<> 134:ad3be0349dc5 2211 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
<> 134:ad3be0349dc5 2212 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n
<> 134:ad3be0349dc5 2213 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n
<> 134:ad3be0349dc5 2214 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n
<> 134:ad3be0349dc5 2215 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n
<> 134:ad3be0349dc5 2216 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n
<> 134:ad3be0349dc5 2217 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n
<> 134:ad3be0349dc5 2218 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n
<> 134:ad3be0349dc5 2219 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n
<> 134:ad3be0349dc5 2220 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n
<> 134:ad3be0349dc5 2221 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n
<> 134:ad3be0349dc5 2222 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n
<> 134:ad3be0349dc5 2223 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n
<> 134:ad3be0349dc5 2224 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n
<> 134:ad3be0349dc5 2225 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n
<> 134:ad3be0349dc5 2226 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n
<> 134:ad3be0349dc5 2227 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n
<> 134:ad3be0349dc5 2228 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n
<> 134:ad3be0349dc5 2229 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n
<> 134:ad3be0349dc5 2230 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem
<> 134:ad3be0349dc5 2231 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2232 * @param Channel This parameter can be a combination of the following values:
<> 134:ad3be0349dc5 2233 * @arg @ref LL_ADC_CHANNEL_0
<> 134:ad3be0349dc5 2234 * @arg @ref LL_ADC_CHANNEL_1
<> 134:ad3be0349dc5 2235 * @arg @ref LL_ADC_CHANNEL_2
<> 134:ad3be0349dc5 2236 * @arg @ref LL_ADC_CHANNEL_3
<> 134:ad3be0349dc5 2237 * @arg @ref LL_ADC_CHANNEL_4
<> 134:ad3be0349dc5 2238 * @arg @ref LL_ADC_CHANNEL_5
<> 134:ad3be0349dc5 2239 * @arg @ref LL_ADC_CHANNEL_6
<> 134:ad3be0349dc5 2240 * @arg @ref LL_ADC_CHANNEL_7
<> 134:ad3be0349dc5 2241 * @arg @ref LL_ADC_CHANNEL_8
<> 134:ad3be0349dc5 2242 * @arg @ref LL_ADC_CHANNEL_9
<> 134:ad3be0349dc5 2243 * @arg @ref LL_ADC_CHANNEL_10
<> 134:ad3be0349dc5 2244 * @arg @ref LL_ADC_CHANNEL_11
<> 134:ad3be0349dc5 2245 * @arg @ref LL_ADC_CHANNEL_12
<> 134:ad3be0349dc5 2246 * @arg @ref LL_ADC_CHANNEL_13
<> 134:ad3be0349dc5 2247 * @arg @ref LL_ADC_CHANNEL_14
<> 134:ad3be0349dc5 2248 * @arg @ref LL_ADC_CHANNEL_15
<> 134:ad3be0349dc5 2249 * @arg @ref LL_ADC_CHANNEL_16
<> 134:ad3be0349dc5 2250 * @arg @ref LL_ADC_CHANNEL_17
<> 134:ad3be0349dc5 2251 * @arg @ref LL_ADC_CHANNEL_18 (1)
<> 134:ad3be0349dc5 2252 * @arg @ref LL_ADC_CHANNEL_VREFINT
<> 134:ad3be0349dc5 2253 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
<> 134:ad3be0349dc5 2254 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
<> 134:ad3be0349dc5 2255 *
<> 134:ad3be0349dc5 2256 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<> 134:ad3be0349dc5 2257 * @retval None
<> 134:ad3be0349dc5 2258 */
<> 134:ad3be0349dc5 2259 __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
<> 134:ad3be0349dc5 2260 {
<> 134:ad3be0349dc5 2261 /* Parameter "Channel" is used with masks because containing */
<> 134:ad3be0349dc5 2262 /* other bits reserved for other purpose. */
<> 134:ad3be0349dc5 2263 CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
<> 134:ad3be0349dc5 2264 }
<> 134:ad3be0349dc5 2265
<> 134:ad3be0349dc5 2266 /**
<> 134:ad3be0349dc5 2267 * @brief Get ADC group regular sequence: channel on rank corresponding to
<> 134:ad3be0349dc5 2268 * channel number.
<> 134:ad3be0349dc5 2269 * @note This function performs:
<> 134:ad3be0349dc5 2270 * - Channels order reading into each rank of scan sequence:
<> 134:ad3be0349dc5 2271 * rank of each channel is fixed by channel HW number
<> 134:ad3be0349dc5 2272 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
<> 134:ad3be0349dc5 2273 * @note On this STM32 serie, ADC group regular sequencer is
<> 134:ad3be0349dc5 2274 * not fully configurable: sequencer length and each rank
<> 134:ad3be0349dc5 2275 * affectation to a channel are fixed by channel HW number.
<> 134:ad3be0349dc5 2276 * @note Depending on devices and packages, some channels may not be available.
<> 134:ad3be0349dc5 2277 * Refer to device datasheet for channels availability.
<> 134:ad3be0349dc5 2278 * @note On this STM32 serie, to measure internal channels (VrefInt,
<> 134:ad3be0349dc5 2279 * TempSensor, ...), measurement paths to internal channels must be
<> 134:ad3be0349dc5 2280 * enabled separately.
<> 134:ad3be0349dc5 2281 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
<> 134:ad3be0349dc5 2282 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 2283 * ADC state:
<> 134:ad3be0349dc5 2284 * ADC must be disabled or enabled without conversion on going
<> 134:ad3be0349dc5 2285 * on group regular.
<> 134:ad3be0349dc5 2286 * @note One or several values can be retrieved.
<> 134:ad3be0349dc5 2287 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
<> 134:ad3be0349dc5 2288 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n
<> 134:ad3be0349dc5 2289 * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n
<> 134:ad3be0349dc5 2290 * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n
<> 134:ad3be0349dc5 2291 * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n
<> 134:ad3be0349dc5 2292 * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n
<> 134:ad3be0349dc5 2293 * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n
<> 134:ad3be0349dc5 2294 * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n
<> 134:ad3be0349dc5 2295 * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n
<> 134:ad3be0349dc5 2296 * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n
<> 134:ad3be0349dc5 2297 * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n
<> 134:ad3be0349dc5 2298 * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n
<> 134:ad3be0349dc5 2299 * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n
<> 134:ad3be0349dc5 2300 * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n
<> 134:ad3be0349dc5 2301 * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n
<> 134:ad3be0349dc5 2302 * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n
<> 134:ad3be0349dc5 2303 * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n
<> 134:ad3be0349dc5 2304 * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n
<> 134:ad3be0349dc5 2305 * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n
<> 134:ad3be0349dc5 2306 * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels
<> 134:ad3be0349dc5 2307 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2308 * @retval Returned value can be a combination of the following values:
<> 134:ad3be0349dc5 2309 * @arg @ref LL_ADC_CHANNEL_0
<> 134:ad3be0349dc5 2310 * @arg @ref LL_ADC_CHANNEL_1
<> 134:ad3be0349dc5 2311 * @arg @ref LL_ADC_CHANNEL_2
<> 134:ad3be0349dc5 2312 * @arg @ref LL_ADC_CHANNEL_3
<> 134:ad3be0349dc5 2313 * @arg @ref LL_ADC_CHANNEL_4
<> 134:ad3be0349dc5 2314 * @arg @ref LL_ADC_CHANNEL_5
<> 134:ad3be0349dc5 2315 * @arg @ref LL_ADC_CHANNEL_6
<> 134:ad3be0349dc5 2316 * @arg @ref LL_ADC_CHANNEL_7
<> 134:ad3be0349dc5 2317 * @arg @ref LL_ADC_CHANNEL_8
<> 134:ad3be0349dc5 2318 * @arg @ref LL_ADC_CHANNEL_9
<> 134:ad3be0349dc5 2319 * @arg @ref LL_ADC_CHANNEL_10
<> 134:ad3be0349dc5 2320 * @arg @ref LL_ADC_CHANNEL_11
<> 134:ad3be0349dc5 2321 * @arg @ref LL_ADC_CHANNEL_12
<> 134:ad3be0349dc5 2322 * @arg @ref LL_ADC_CHANNEL_13
<> 134:ad3be0349dc5 2323 * @arg @ref LL_ADC_CHANNEL_14
<> 134:ad3be0349dc5 2324 * @arg @ref LL_ADC_CHANNEL_15
<> 134:ad3be0349dc5 2325 * @arg @ref LL_ADC_CHANNEL_16
<> 134:ad3be0349dc5 2326 * @arg @ref LL_ADC_CHANNEL_17
<> 134:ad3be0349dc5 2327 * @arg @ref LL_ADC_CHANNEL_18 (1)
<> 134:ad3be0349dc5 2328 * @arg @ref LL_ADC_CHANNEL_VREFINT
<> 134:ad3be0349dc5 2329 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
<> 134:ad3be0349dc5 2330 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
<> 134:ad3be0349dc5 2331 *
<> 134:ad3be0349dc5 2332 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<> 134:ad3be0349dc5 2333 */
<> 134:ad3be0349dc5 2334 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 2335 {
<> 134:ad3be0349dc5 2336 register uint32_t ChannelsBitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
<> 134:ad3be0349dc5 2337
<> 134:ad3be0349dc5 2338 return ( (((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
<> 134:ad3be0349dc5 2339 | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
<> 134:ad3be0349dc5 2340 | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
<> 134:ad3be0349dc5 2341 | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
<> 134:ad3be0349dc5 2342 | (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
<> 134:ad3be0349dc5 2343 | (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
<> 134:ad3be0349dc5 2344 | (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
<> 134:ad3be0349dc5 2345 | (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
<> 134:ad3be0349dc5 2346 | (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)
<> 134:ad3be0349dc5 2347 | (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)
<> 134:ad3be0349dc5 2348 | (((ChannelsBitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
<> 134:ad3be0349dc5 2349 | (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
<> 134:ad3be0349dc5 2350 | (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
<> 134:ad3be0349dc5 2351 | (((ChannelsBitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
<> 134:ad3be0349dc5 2352 | (((ChannelsBitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)
<> 134:ad3be0349dc5 2353 | (((ChannelsBitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)
<> 134:ad3be0349dc5 2354 | (((ChannelsBitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)
<> 134:ad3be0349dc5 2355 | (((ChannelsBitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)
<> 134:ad3be0349dc5 2356 #if defined(ADC_CCR_VBATEN)
<> 134:ad3be0349dc5 2357 | (((ChannelsBitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)
<> 134:ad3be0349dc5 2358 #endif
<> 134:ad3be0349dc5 2359 );
<> 134:ad3be0349dc5 2360 }
<> 134:ad3be0349dc5 2361 /**
<> 134:ad3be0349dc5 2362 * @brief Set ADC continuous conversion mode on ADC group regular.
<> 134:ad3be0349dc5 2363 * @note Description of ADC continuous conversion mode:
<> 134:ad3be0349dc5 2364 * - single mode: one conversion per trigger
<> 134:ad3be0349dc5 2365 * - continuous mode: after the first trigger, following
<> 134:ad3be0349dc5 2366 * conversions launched successively automatically.
<> 134:ad3be0349dc5 2367 * @note It is not possible to enable both ADC group regular
<> 134:ad3be0349dc5 2368 * continuous mode and sequencer discontinuous mode.
<> 134:ad3be0349dc5 2369 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 2370 * ADC state:
<> 134:ad3be0349dc5 2371 * ADC must be disabled or enabled without conversion on going
<> 134:ad3be0349dc5 2372 * on group regular.
<> 134:ad3be0349dc5 2373 * @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode
<> 134:ad3be0349dc5 2374 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2375 * @param Continuous This parameter can be one of the following values:
<> 134:ad3be0349dc5 2376 * @arg @ref LL_ADC_REG_CONV_SINGLE
<> 134:ad3be0349dc5 2377 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
<> 134:ad3be0349dc5 2378 * @retval None
<> 134:ad3be0349dc5 2379 */
<> 134:ad3be0349dc5 2380 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
<> 134:ad3be0349dc5 2381 {
<> 134:ad3be0349dc5 2382 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
<> 134:ad3be0349dc5 2383 }
<> 134:ad3be0349dc5 2384
<> 134:ad3be0349dc5 2385 /**
<> 134:ad3be0349dc5 2386 * @brief Get ADC continuous conversion mode on ADC group regular.
<> 134:ad3be0349dc5 2387 * @note Description of ADC continuous conversion mode:
<> 134:ad3be0349dc5 2388 * - single mode: one conversion per trigger
<> 134:ad3be0349dc5 2389 * - continuous mode: after the first trigger, following
<> 134:ad3be0349dc5 2390 * conversions launched successively automatically.
<> 134:ad3be0349dc5 2391 * @rmtoll CFGR1 CONT LL_ADC_REG_GetContinuousMode
<> 134:ad3be0349dc5 2392 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2393 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 2394 * @arg @ref LL_ADC_REG_CONV_SINGLE
<> 134:ad3be0349dc5 2395 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
<> 134:ad3be0349dc5 2396 */
<> 134:ad3be0349dc5 2397 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 2398 {
<> 134:ad3be0349dc5 2399 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
<> 134:ad3be0349dc5 2400 }
<> 134:ad3be0349dc5 2401
<> 134:ad3be0349dc5 2402 /**
<> 134:ad3be0349dc5 2403 * @brief Set ADC group regular conversion data transfer: no transfer or
<> 134:ad3be0349dc5 2404 * transfer by DMA, and DMA requests mode.
<> 134:ad3be0349dc5 2405 * @note If transfer by DMA selected, specifies the DMA requests
<> 134:ad3be0349dc5 2406 * mode:
<> 134:ad3be0349dc5 2407 * - Limited mode (One shot mode): DMA transfer requests are stopped
<> 134:ad3be0349dc5 2408 * when number of DMA data transfers (number of
<> 134:ad3be0349dc5 2409 * ADC conversions) is reached.
<> 134:ad3be0349dc5 2410 * This ADC mode is intended to be used with DMA mode non-circular.
<> 134:ad3be0349dc5 2411 * - Unlimited mode: DMA transfer requests are unlimited,
<> 134:ad3be0349dc5 2412 * whatever number of DMA data transfers (number of
<> 134:ad3be0349dc5 2413 * ADC conversions).
<> 134:ad3be0349dc5 2414 * This ADC mode is intended to be used with DMA mode circular.
<> 134:ad3be0349dc5 2415 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
<> 134:ad3be0349dc5 2416 * mode non-circular:
<> 134:ad3be0349dc5 2417 * when DMA transfers size will be reached, DMA will stop transfers of
<> 134:ad3be0349dc5 2418 * ADC conversions data ADC will raise an overrun error
<> 134:ad3be0349dc5 2419 * (overrun flag and interruption if enabled).
<> 134:ad3be0349dc5 2420 * @note To configure DMA source address (peripheral address),
<> 134:ad3be0349dc5 2421 * use function @ref LL_ADC_DMA_GetRegAddr().
<> 134:ad3be0349dc5 2422 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 2423 * ADC state:
<> 134:ad3be0349dc5 2424 * ADC must be disabled or enabled without conversion on going
<> 134:ad3be0349dc5 2425 * on group regular.
<> 134:ad3be0349dc5 2426 * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n
<> 134:ad3be0349dc5 2427 * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer
<> 134:ad3be0349dc5 2428 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2429 * @param DMATransfer This parameter can be one of the following values:
<> 134:ad3be0349dc5 2430 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
<> 134:ad3be0349dc5 2431 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
<> 134:ad3be0349dc5 2432 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
<> 134:ad3be0349dc5 2433 * @retval None
<> 134:ad3be0349dc5 2434 */
<> 134:ad3be0349dc5 2435 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
<> 134:ad3be0349dc5 2436 {
<> 134:ad3be0349dc5 2437 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer);
<> 134:ad3be0349dc5 2438 }
<> 134:ad3be0349dc5 2439
<> 134:ad3be0349dc5 2440 /**
<> 134:ad3be0349dc5 2441 * @brief Get ADC group regular conversion data transfer: no transfer or
<> 134:ad3be0349dc5 2442 * transfer by DMA, and DMA requests mode.
<> 134:ad3be0349dc5 2443 * @note If transfer by DMA selected, specifies the DMA requests
<> 134:ad3be0349dc5 2444 * mode:
<> 134:ad3be0349dc5 2445 * - Limited mode (One shot mode): DMA transfer requests are stopped
<> 134:ad3be0349dc5 2446 * when number of DMA data transfers (number of
<> 134:ad3be0349dc5 2447 * ADC conversions) is reached.
<> 134:ad3be0349dc5 2448 * This ADC mode is intended to be used with DMA mode non-circular.
<> 134:ad3be0349dc5 2449 * - Unlimited mode: DMA transfer requests are unlimited,
<> 134:ad3be0349dc5 2450 * whatever number of DMA data transfers (number of
<> 134:ad3be0349dc5 2451 * ADC conversions).
<> 134:ad3be0349dc5 2452 * This ADC mode is intended to be used with DMA mode circular.
<> 134:ad3be0349dc5 2453 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
<> 134:ad3be0349dc5 2454 * mode non-circular:
<> 134:ad3be0349dc5 2455 * when DMA transfers size will be reached, DMA will stop transfers of
<> 134:ad3be0349dc5 2456 * ADC conversions data ADC will raise an overrun error
<> 134:ad3be0349dc5 2457 * (overrun flag and interruption if enabled).
<> 134:ad3be0349dc5 2458 * @note To configure DMA source address (peripheral address),
<> 134:ad3be0349dc5 2459 * use function @ref LL_ADC_DMA_GetRegAddr().
<> 134:ad3be0349dc5 2460 * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n
<> 134:ad3be0349dc5 2461 * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer
<> 134:ad3be0349dc5 2462 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2463 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 2464 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
<> 134:ad3be0349dc5 2465 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
<> 134:ad3be0349dc5 2466 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
<> 134:ad3be0349dc5 2467 */
<> 134:ad3be0349dc5 2468 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 2469 {
<> 134:ad3be0349dc5 2470 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));
<> 134:ad3be0349dc5 2471 }
<> 134:ad3be0349dc5 2472
<> 134:ad3be0349dc5 2473 /**
<> 134:ad3be0349dc5 2474 * @brief Set ADC group regular behavior in case of overrun:
<> 134:ad3be0349dc5 2475 * data preserved or overwritten.
<> 134:ad3be0349dc5 2476 * @note Compatibility with devices without feature overrun:
<> 134:ad3be0349dc5 2477 * other devices without this feature have a behavior
<> 134:ad3be0349dc5 2478 * equivalent to data overwritten.
<> 134:ad3be0349dc5 2479 * The default setting of overrun is data preserved.
<> 134:ad3be0349dc5 2480 * Therefore, for compatibility with all devices, parameter
<> 134:ad3be0349dc5 2481 * overrun should be set to data overwritten.
<> 134:ad3be0349dc5 2482 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 2483 * ADC state:
<> 134:ad3be0349dc5 2484 * ADC must be disabled or enabled without conversion on going
<> 134:ad3be0349dc5 2485 * on group regular.
<> 134:ad3be0349dc5 2486 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun
<> 134:ad3be0349dc5 2487 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2488 * @param Overrun This parameter can be one of the following values:
<> 134:ad3be0349dc5 2489 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
<> 134:ad3be0349dc5 2490 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
<> 134:ad3be0349dc5 2491 * @retval None
<> 134:ad3be0349dc5 2492 */
<> 134:ad3be0349dc5 2493 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
<> 134:ad3be0349dc5 2494 {
<> 134:ad3be0349dc5 2495 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
<> 134:ad3be0349dc5 2496 }
<> 134:ad3be0349dc5 2497
<> 134:ad3be0349dc5 2498 /**
<> 134:ad3be0349dc5 2499 * @brief Get ADC group regular behavior in case of overrun:
<> 134:ad3be0349dc5 2500 * data preserved or overwritten.
<> 134:ad3be0349dc5 2501 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_GetOverrun
<> 134:ad3be0349dc5 2502 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2503 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 2504 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
<> 134:ad3be0349dc5 2505 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
<> 134:ad3be0349dc5 2506 */
<> 134:ad3be0349dc5 2507 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 2508 {
<> 134:ad3be0349dc5 2509 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
<> 134:ad3be0349dc5 2510 }
<> 134:ad3be0349dc5 2511
<> 134:ad3be0349dc5 2512 /**
<> 134:ad3be0349dc5 2513 * @}
<> 134:ad3be0349dc5 2514 */
<> 134:ad3be0349dc5 2515
<> 134:ad3be0349dc5 2516
<> 134:ad3be0349dc5 2517 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
<> 134:ad3be0349dc5 2518 * @{
<> 134:ad3be0349dc5 2519 */
<> 134:ad3be0349dc5 2520
<> 134:ad3be0349dc5 2521 /**
<> 134:ad3be0349dc5 2522 * @brief Set ADC analog watchdog monitored channels:
<> 134:ad3be0349dc5 2523 * a single channel or all channels,
<> 134:ad3be0349dc5 2524 * on ADC group regular.
<> 134:ad3be0349dc5 2525 * @note Once monitored channels are selected, analog watchdog
<> 134:ad3be0349dc5 2526 * is enabled.
<> 134:ad3be0349dc5 2527 * @note In case of need to define a single channel to monitor
<> 134:ad3be0349dc5 2528 * with analog watchdog from sequencer channel definition,
<> 134:ad3be0349dc5 2529 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
<> 134:ad3be0349dc5 2530 * @note On this STM32 serie, there is only 1 kind of analog watchdog
<> 134:ad3be0349dc5 2531 * instance:
<> 134:ad3be0349dc5 2532 * - AWD standard (instance AWD1):
<> 134:ad3be0349dc5 2533 * - channels monitored: can monitor 1 channel or all channels.
<> 134:ad3be0349dc5 2534 * - groups monitored: ADC group regular.
<> 134:ad3be0349dc5 2535 * - resolution: resolution is not limited (corresponds to
<> 134:ad3be0349dc5 2536 * ADC resolution configured).
<> 134:ad3be0349dc5 2537 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 2538 * ADC state:
<> 134:ad3be0349dc5 2539 * ADC must be disabled or enabled without conversion on going
<> 134:ad3be0349dc5 2540 * on group regular.
<> 134:ad3be0349dc5 2541 * @rmtoll CFGR1 AWDCH LL_ADC_SetAnalogWDMonitChannels\n
<> 134:ad3be0349dc5 2542 * CFGR1 AWDSGL LL_ADC_SetAnalogWDMonitChannels\n
<> 134:ad3be0349dc5 2543 * CFGR1 AWDEN LL_ADC_SetAnalogWDMonitChannels
<> 134:ad3be0349dc5 2544 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2545 * @param AWDChannelGroup This parameter can be one of the following values:
<> 134:ad3be0349dc5 2546 * @arg @ref LL_ADC_AWD_DISABLE
<> 134:ad3be0349dc5 2547 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
<> 134:ad3be0349dc5 2548 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
<> 134:ad3be0349dc5 2549 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
<> 134:ad3be0349dc5 2550 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
<> 134:ad3be0349dc5 2551 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
<> 134:ad3be0349dc5 2552 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
<> 134:ad3be0349dc5 2553 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
<> 134:ad3be0349dc5 2554 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
<> 134:ad3be0349dc5 2555 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
<> 134:ad3be0349dc5 2556 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
<> 134:ad3be0349dc5 2557 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
<> 134:ad3be0349dc5 2558 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
<> 134:ad3be0349dc5 2559 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
<> 134:ad3be0349dc5 2560 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
<> 134:ad3be0349dc5 2561 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
<> 134:ad3be0349dc5 2562 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
<> 134:ad3be0349dc5 2563 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
<> 134:ad3be0349dc5 2564 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
<> 134:ad3be0349dc5 2565 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
<> 134:ad3be0349dc5 2566 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1)
<> 134:ad3be0349dc5 2567 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
<> 134:ad3be0349dc5 2568 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
<> 134:ad3be0349dc5 2569 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
<> 134:ad3be0349dc5 2570 *
<> 134:ad3be0349dc5 2571 * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<> 134:ad3be0349dc5 2572 * @retval None
<> 134:ad3be0349dc5 2573 */
<> 134:ad3be0349dc5 2574 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
<> 134:ad3be0349dc5 2575 {
<> 134:ad3be0349dc5 2576 MODIFY_REG(ADCx->CFGR1,
<> 134:ad3be0349dc5 2577 (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN),
<> 134:ad3be0349dc5 2578 (AWDChannelGroup & ADC_AWD_CR_ALL_CHANNEL_MASK));
<> 134:ad3be0349dc5 2579 }
<> 134:ad3be0349dc5 2580
<> 134:ad3be0349dc5 2581 /**
<> 134:ad3be0349dc5 2582 * @brief Get ADC analog watchdog monitored channel.
<> 134:ad3be0349dc5 2583 * @note Usage of the returned channel number:
<> 134:ad3be0349dc5 2584 * - To reinject this channel into another function LL_ADC_xxx:
<> 134:ad3be0349dc5 2585 * the returned channel number is only partly formatted on definition
<> 134:ad3be0349dc5 2586 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
<> 134:ad3be0349dc5 2587 * with parts of literals LL_ADC_CHANNEL_x or using
<> 134:ad3be0349dc5 2588 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<> 134:ad3be0349dc5 2589 * Then the selected literal LL_ADC_CHANNEL_x can be used
<> 134:ad3be0349dc5 2590 * as parameter for another function.
<> 134:ad3be0349dc5 2591 * - To get the channel number in decimal format:
<> 134:ad3be0349dc5 2592 * process the returned value with the helper macro
<> 134:ad3be0349dc5 2593 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<> 134:ad3be0349dc5 2594 * Applicable only when the analog watchdog is set to monitor
<> 134:ad3be0349dc5 2595 * one channel.
<> 134:ad3be0349dc5 2596 * @note On this STM32 serie, there is only 1 kind of analog watchdog
<> 134:ad3be0349dc5 2597 * instance:
<> 134:ad3be0349dc5 2598 * - AWD standard (instance AWD1):
<> 134:ad3be0349dc5 2599 * - channels monitored: can monitor 1 channel or all channels.
<> 134:ad3be0349dc5 2600 * - groups monitored: ADC group regular.
<> 134:ad3be0349dc5 2601 * - resolution: resolution is not limited (corresponds to
<> 134:ad3be0349dc5 2602 * ADC resolution configured).
<> 134:ad3be0349dc5 2603 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 2604 * ADC state:
<> 134:ad3be0349dc5 2605 * ADC must be disabled or enabled without conversion on going
<> 134:ad3be0349dc5 2606 * on group regular.
<> 134:ad3be0349dc5 2607 * @rmtoll CFGR1 AWDCH LL_ADC_GetAnalogWDMonitChannels\n
<> 134:ad3be0349dc5 2608 * CFGR1 AWDSGL LL_ADC_GetAnalogWDMonitChannels\n
<> 134:ad3be0349dc5 2609 * CFGR1 AWDEN LL_ADC_GetAnalogWDMonitChannels
<> 134:ad3be0349dc5 2610 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2611 * @retval Returned value can be one of the following values:
<> 134:ad3be0349dc5 2612 * @arg @ref LL_ADC_AWD_DISABLE
<> 134:ad3be0349dc5 2613 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
<> 134:ad3be0349dc5 2614 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
<> 134:ad3be0349dc5 2615 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
<> 134:ad3be0349dc5 2616 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
<> 134:ad3be0349dc5 2617 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
<> 134:ad3be0349dc5 2618 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
<> 134:ad3be0349dc5 2619 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
<> 134:ad3be0349dc5 2620 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
<> 134:ad3be0349dc5 2621 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
<> 134:ad3be0349dc5 2622 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
<> 134:ad3be0349dc5 2623 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
<> 134:ad3be0349dc5 2624 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
<> 134:ad3be0349dc5 2625 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
<> 134:ad3be0349dc5 2626 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
<> 134:ad3be0349dc5 2627 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
<> 134:ad3be0349dc5 2628 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
<> 134:ad3be0349dc5 2629 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
<> 134:ad3be0349dc5 2630 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
<> 134:ad3be0349dc5 2631 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
<> 134:ad3be0349dc5 2632 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
<> 134:ad3be0349dc5 2633 */
<> 134:ad3be0349dc5 2634 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 2635 {
<> 134:ad3be0349dc5 2636 register uint32_t AWDChannelGroup = READ_BIT(ADCx->CFGR1, (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN));
<> 134:ad3be0349dc5 2637
<> 134:ad3be0349dc5 2638 /* Note: Set variable according to channel definition including channel ID */
<> 134:ad3be0349dc5 2639 /* with bitfield. */
<> 134:ad3be0349dc5 2640 register uint32_t AWDChannelSingle = ((AWDChannelGroup & ADC_CFGR1_AWDSGL) >> ADC_CFGR1_AWDSGL_BITOFFSET_POS);
<> 134:ad3be0349dc5 2641 register uint32_t AWDChannelBitField = (ADC_CHANNEL_0_BITFIELD << ((AWDChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS));
<> 134:ad3be0349dc5 2642
<> 134:ad3be0349dc5 2643 return (AWDChannelGroup | (AWDChannelBitField * AWDChannelSingle));
<> 134:ad3be0349dc5 2644 }
<> 134:ad3be0349dc5 2645
<> 134:ad3be0349dc5 2646 /**
<> 134:ad3be0349dc5 2647 * @brief Set ADC analog watchdog thresholds value of both thresholds
<> 134:ad3be0349dc5 2648 * high and low.
<> 134:ad3be0349dc5 2649 * @note If value of only one threshold high or low must be set,
<> 134:ad3be0349dc5 2650 * use function @ref LL_ADC_SetAnalogWDThresholds().
<> 134:ad3be0349dc5 2651 * @note In case of ADC resolution different of 12 bits,
<> 134:ad3be0349dc5 2652 * analog watchdog thresholds data require a specific shift.
<> 134:ad3be0349dc5 2653 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
<> 134:ad3be0349dc5 2654 * @note On this STM32 serie, there is only 1 kind of analog watchdog
<> 134:ad3be0349dc5 2655 * instance:
<> 134:ad3be0349dc5 2656 * - AWD standard (instance AWD1):
<> 134:ad3be0349dc5 2657 * - channels monitored: can monitor 1 channel or all channels.
<> 134:ad3be0349dc5 2658 * - groups monitored: ADC group regular.
<> 134:ad3be0349dc5 2659 * - resolution: resolution is not limited (corresponds to
<> 134:ad3be0349dc5 2660 * ADC resolution configured).
<> 134:ad3be0349dc5 2661 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 2662 * ADC state:
<> 134:ad3be0349dc5 2663 * ADC must be disabled or enabled without conversion on going
<> 134:ad3be0349dc5 2664 * on group regular.
<> 134:ad3be0349dc5 2665 * @rmtoll TR HT LL_ADC_ConfigAnalogWDThresholds\n
<> 134:ad3be0349dc5 2666 * TR LT LL_ADC_ConfigAnalogWDThresholds
<> 134:ad3be0349dc5 2667 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2668 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
<> 134:ad3be0349dc5 2669 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
<> 134:ad3be0349dc5 2670 * @retval None
<> 134:ad3be0349dc5 2671 */
<> 134:ad3be0349dc5 2672 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
<> 134:ad3be0349dc5 2673 {
<> 134:ad3be0349dc5 2674 MODIFY_REG(ADCx->TR,
<> 134:ad3be0349dc5 2675 ADC_TR_HT | ADC_TR_LT,
<> 134:ad3be0349dc5 2676 (AWDThresholdHighValue << ADC_TR_HT_BITOFFSET_POS) | AWDThresholdLowValue);
<> 134:ad3be0349dc5 2677 }
<> 134:ad3be0349dc5 2678
<> 134:ad3be0349dc5 2679 /**
<> 134:ad3be0349dc5 2680 * @brief Set ADC analog watchdog threshold value of threshold
<> 134:ad3be0349dc5 2681 * high or low.
<> 134:ad3be0349dc5 2682 * @note If values of both thresholds high or low must be set,
<> 134:ad3be0349dc5 2683 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
<> 134:ad3be0349dc5 2684 * @note In case of ADC resolution different of 12 bits,
<> 134:ad3be0349dc5 2685 * analog watchdog thresholds data require a specific shift.
<> 134:ad3be0349dc5 2686 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
<> 134:ad3be0349dc5 2687 * @note On this STM32 serie, there is only 1 kind of analog watchdog
<> 134:ad3be0349dc5 2688 * instance:
<> 134:ad3be0349dc5 2689 * - AWD standard (instance AWD1):
<> 134:ad3be0349dc5 2690 * - channels monitored: can monitor 1 channel or all channels.
<> 134:ad3be0349dc5 2691 * - groups monitored: ADC group regular.
<> 134:ad3be0349dc5 2692 * - resolution: resolution is not limited (corresponds to
<> 134:ad3be0349dc5 2693 * ADC resolution configured).
<> 134:ad3be0349dc5 2694 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 2695 * ADC state:
<> 134:ad3be0349dc5 2696 * ADC must be disabled or enabled without conversion on going
<> 134:ad3be0349dc5 2697 * on group regular.
<> 134:ad3be0349dc5 2698 * @rmtoll TR HT LL_ADC_SetAnalogWDThresholds\n
<> 134:ad3be0349dc5 2699 * TR LT LL_ADC_SetAnalogWDThresholds
<> 134:ad3be0349dc5 2700 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2701 * @param AWDThresholdsHighLow This parameter can be one of the following values:
<> 134:ad3be0349dc5 2702 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
<> 134:ad3be0349dc5 2703 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
<> 134:ad3be0349dc5 2704 * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF
<> 134:ad3be0349dc5 2705 * @retval None
<> 134:ad3be0349dc5 2706 */
<> 134:ad3be0349dc5 2707 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
<> 134:ad3be0349dc5 2708 {
<> 134:ad3be0349dc5 2709 /* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010" */
<> 134:ad3be0349dc5 2710 /* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold */
<> 134:ad3be0349dc5 2711 /* high is selected, then data is shifted to LSB. Else(threshold low), */
<> 134:ad3be0349dc5 2712 /* data is not shifted. */
<> 134:ad3be0349dc5 2713 MODIFY_REG(ADCx->TR,
<> 134:ad3be0349dc5 2714 AWDThresholdsHighLow,
<> 134:ad3be0349dc5 2715 AWDThresholdValue << ((AWDThresholdsHighLow >> ADC_TR_HT_BITOFFSET_POS) & ((uint32_t)0x00000010U)));
<> 134:ad3be0349dc5 2716 }
<> 134:ad3be0349dc5 2717
<> 134:ad3be0349dc5 2718 /**
<> 134:ad3be0349dc5 2719 * @brief Get ADC analog watchdog threshold value of threshold high,
<> 134:ad3be0349dc5 2720 * threshold low or raw data with ADC thresholds high and low
<> 134:ad3be0349dc5 2721 * concatenated.
<> 134:ad3be0349dc5 2722 * @note If raw data with ADC thresholds high and low is retrieved,
<> 134:ad3be0349dc5 2723 * the data of each threshold high or low can be isolated
<> 134:ad3be0349dc5 2724 * using helper macro:
<> 134:ad3be0349dc5 2725 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
<> 134:ad3be0349dc5 2726 * @note In case of ADC resolution different of 12 bits,
<> 134:ad3be0349dc5 2727 * analog watchdog thresholds data require a specific shift.
<> 134:ad3be0349dc5 2728 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
<> 134:ad3be0349dc5 2729 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
<> 134:ad3be0349dc5 2730 * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
<> 134:ad3be0349dc5 2731 * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
<> 134:ad3be0349dc5 2732 * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
<> 134:ad3be0349dc5 2733 * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
<> 134:ad3be0349dc5 2734 * TR3 LT3 LL_ADC_GetAnalogWDThresholds
<> 134:ad3be0349dc5 2735 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2736 * @param AWDThresholdsHighLow This parameter can be one of the following values:
<> 134:ad3be0349dc5 2737 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
<> 134:ad3be0349dc5 2738 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
<> 134:ad3be0349dc5 2739 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
<> 134:ad3be0349dc5 2740 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<> 134:ad3be0349dc5 2741 */
<> 134:ad3be0349dc5 2742 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
<> 134:ad3be0349dc5 2743 {
<> 134:ad3be0349dc5 2744 /* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010" */
<> 134:ad3be0349dc5 2745 /* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold */
<> 134:ad3be0349dc5 2746 /* high is selected, then data is shifted to LSB. Else(threshold low or */
<> 134:ad3be0349dc5 2747 /* both thresholds), data is not shifted. */
<> 134:ad3be0349dc5 2748 return (uint32_t)(READ_BIT(ADCx->TR,
<> 134:ad3be0349dc5 2749 (AWDThresholdsHighLow | ADC_TR_LT))
<> 134:ad3be0349dc5 2750 >> ((~AWDThresholdsHighLow) & ((uint32_t)0x00000010U))
<> 134:ad3be0349dc5 2751 );
<> 134:ad3be0349dc5 2752 }
<> 134:ad3be0349dc5 2753
<> 134:ad3be0349dc5 2754 /**
<> 134:ad3be0349dc5 2755 * @}
<> 134:ad3be0349dc5 2756 */
<> 134:ad3be0349dc5 2757
<> 134:ad3be0349dc5 2758 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
<> 134:ad3be0349dc5 2759 * @{
<> 134:ad3be0349dc5 2760 */
<> 134:ad3be0349dc5 2761
<> 134:ad3be0349dc5 2762 /**
<> 134:ad3be0349dc5 2763 * @brief Enable the selected ADC instance.
<> 134:ad3be0349dc5 2764 * @note On this STM32 serie, after ADC enable, a delay for
<> 134:ad3be0349dc5 2765 * ADC internal analog stabilization is required before performing a
<> 134:ad3be0349dc5 2766 * ADC conversion start.
<> 134:ad3be0349dc5 2767 * Refer to device datasheet, parameter tSTAB.
<> 134:ad3be0349dc5 2768 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
<> 134:ad3be0349dc5 2769 * is enabled and when conversion clock is active.
<> 134:ad3be0349dc5 2770 * (not only core clock: this ADC has a dual clock domain)
<> 134:ad3be0349dc5 2771 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 2772 * ADC state:
<> 134:ad3be0349dc5 2773 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
<> 134:ad3be0349dc5 2774 * @rmtoll CR ADEN LL_ADC_Enable
<> 134:ad3be0349dc5 2775 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2776 * @retval None
<> 134:ad3be0349dc5 2777 */
<> 134:ad3be0349dc5 2778 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 2779 {
<> 134:ad3be0349dc5 2780 /* Note: Write register with some additional bits forced to state reset */
<> 134:ad3be0349dc5 2781 /* instead of modifying only the selected bit for this function, */
<> 134:ad3be0349dc5 2782 /* to not interfere with bits with HW property "rs". */
<> 134:ad3be0349dc5 2783 MODIFY_REG(ADCx->CR,
<> 134:ad3be0349dc5 2784 ADC_CR_BITS_PROPERTY_RS,
<> 134:ad3be0349dc5 2785 ADC_CR_ADEN);
<> 134:ad3be0349dc5 2786 }
<> 134:ad3be0349dc5 2787
<> 134:ad3be0349dc5 2788 /**
<> 134:ad3be0349dc5 2789 * @brief Disable the selected ADC instance.
<> 134:ad3be0349dc5 2790 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 2791 * ADC state:
<> 134:ad3be0349dc5 2792 * ADC must be not disabled. Must be enabled without conversion on going
<> 134:ad3be0349dc5 2793 * on group regular.
<> 134:ad3be0349dc5 2794 * @rmtoll CR ADDIS LL_ADC_Disable
<> 134:ad3be0349dc5 2795 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2796 * @retval None
<> 134:ad3be0349dc5 2797 */
<> 134:ad3be0349dc5 2798 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 2799 {
<> 134:ad3be0349dc5 2800 /* Note: Write register with some additional bits forced to state reset */
<> 134:ad3be0349dc5 2801 /* instead of modifying only the selected bit for this function, */
<> 134:ad3be0349dc5 2802 /* to not interfere with bits with HW property "rs". */
<> 134:ad3be0349dc5 2803 MODIFY_REG(ADCx->CR,
<> 134:ad3be0349dc5 2804 ADC_CR_BITS_PROPERTY_RS,
<> 134:ad3be0349dc5 2805 ADC_CR_ADDIS);
<> 134:ad3be0349dc5 2806 }
<> 134:ad3be0349dc5 2807
<> 134:ad3be0349dc5 2808 /**
<> 134:ad3be0349dc5 2809 * @brief Get the selected ADC instance enable state.
<> 134:ad3be0349dc5 2810 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
<> 134:ad3be0349dc5 2811 * is enabled and when conversion clock is active.
<> 134:ad3be0349dc5 2812 * (not only core clock: this ADC has a dual clock domain)
<> 134:ad3be0349dc5 2813 * @rmtoll CR ADEN LL_ADC_IsEnabled
<> 134:ad3be0349dc5 2814 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2815 * @retval 0: ADC is disabled, 1: ADC is enabled.
<> 134:ad3be0349dc5 2816 */
<> 134:ad3be0349dc5 2817 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 2818 {
<> 134:ad3be0349dc5 2819 return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN));
<> 134:ad3be0349dc5 2820 }
<> 134:ad3be0349dc5 2821
<> 134:ad3be0349dc5 2822 /**
<> 134:ad3be0349dc5 2823 * @brief Get the selected ADC instance disable state.
<> 134:ad3be0349dc5 2824 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
<> 134:ad3be0349dc5 2825 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2826 * @retval 0: no ADC disable command on going.
<> 134:ad3be0349dc5 2827 */
<> 134:ad3be0349dc5 2828 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 2829 {
<> 134:ad3be0349dc5 2830 return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS));
<> 134:ad3be0349dc5 2831 }
<> 134:ad3be0349dc5 2832
<> 134:ad3be0349dc5 2833 /**
<> 134:ad3be0349dc5 2834 * @brief Start ADC calibration in the mode single-ended
<> 134:ad3be0349dc5 2835 * or differential (for devices with differential mode available).
<> 134:ad3be0349dc5 2836 * @note On this STM32 serie, a minimum number of ADC clock cycles
<> 134:ad3be0349dc5 2837 * are required between ADC end of calibration and ADC enable.
<> 134:ad3be0349dc5 2838 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
<> 134:ad3be0349dc5 2839 * @note In case of usage of ADC with DMA transfer:
<> 134:ad3be0349dc5 2840 * On this STM32 serie, ADC DMA transfer request should be disabled
<> 134:ad3be0349dc5 2841 * during calibration:
<> 134:ad3be0349dc5 2842 * Calibration factor is available in data register
<> 134:ad3be0349dc5 2843 * and also transfered by DMA.
<> 134:ad3be0349dc5 2844 * To not insert ADC calibration factor among ADC conversion data
<> 134:ad3be0349dc5 2845 * in array variable, DMA transfer must be disabled during
<> 134:ad3be0349dc5 2846 * calibration.
<> 134:ad3be0349dc5 2847 * (DMA transfer setting backup and disable before calibration,
<> 134:ad3be0349dc5 2848 * DMA transfer setting restore after calibration.
<> 134:ad3be0349dc5 2849 * Refer to functions @ref LL_ADC_REG_GetDMATransfer(),
<> 134:ad3be0349dc5 2850 * @ref LL_ADC_REG_SetDMATransfer() ).
<> 134:ad3be0349dc5 2851 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 2852 * ADC state:
<> 134:ad3be0349dc5 2853 * ADC must be ADC disabled.
<> 134:ad3be0349dc5 2854 * @rmtoll CR ADCAL LL_ADC_StartCalibration
<> 134:ad3be0349dc5 2855 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2856 * @retval None
<> 134:ad3be0349dc5 2857 */
<> 134:ad3be0349dc5 2858 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 2859 {
<> 134:ad3be0349dc5 2860 /* Note: Write register with some additional bits forced to state reset */
<> 134:ad3be0349dc5 2861 /* instead of modifying only the selected bit for this function, */
<> 134:ad3be0349dc5 2862 /* to not interfere with bits with HW property "rs". */
<> 134:ad3be0349dc5 2863 MODIFY_REG(ADCx->CR,
<> 134:ad3be0349dc5 2864 ADC_CR_BITS_PROPERTY_RS,
<> 134:ad3be0349dc5 2865 ADC_CR_ADCAL);
<> 134:ad3be0349dc5 2866 }
<> 134:ad3be0349dc5 2867
<> 134:ad3be0349dc5 2868 /**
<> 134:ad3be0349dc5 2869 * @brief Get ADC calibration state.
<> 134:ad3be0349dc5 2870 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
<> 134:ad3be0349dc5 2871 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2872 * @retval 0: calibration complete, 1: calibration in progress.
<> 134:ad3be0349dc5 2873 */
<> 134:ad3be0349dc5 2874 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 2875 {
<> 134:ad3be0349dc5 2876 return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL));
<> 134:ad3be0349dc5 2877 }
<> 134:ad3be0349dc5 2878
<> 134:ad3be0349dc5 2879 /**
<> 134:ad3be0349dc5 2880 * @}
<> 134:ad3be0349dc5 2881 */
<> 134:ad3be0349dc5 2882
<> 134:ad3be0349dc5 2883 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
<> 134:ad3be0349dc5 2884 * @{
<> 134:ad3be0349dc5 2885 */
<> 134:ad3be0349dc5 2886
<> 134:ad3be0349dc5 2887 /**
<> 134:ad3be0349dc5 2888 * @brief Start ADC group regular conversion.
<> 134:ad3be0349dc5 2889 * @note On this STM32 serie, this function is relevant for both
<> 134:ad3be0349dc5 2890 * internal trigger (SW start) and external trigger:
<> 134:ad3be0349dc5 2891 * - If ADC trigger has been set to software start, ADC conversion
<> 134:ad3be0349dc5 2892 * starts immediately.
<> 134:ad3be0349dc5 2893 * - If ADC trigger has been set to external trigger, ADC conversion
<> 134:ad3be0349dc5 2894 * will start at next trigger event (on the selected trigger edge)
<> 134:ad3be0349dc5 2895 * following the ADC start conversion command.
<> 134:ad3be0349dc5 2896 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 2897 * ADC state:
<> 134:ad3be0349dc5 2898 * ADC must be enabled without conversion on going on group regular,
<> 134:ad3be0349dc5 2899 * without conversion stop command on going on group regular.
<> 134:ad3be0349dc5 2900 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
<> 134:ad3be0349dc5 2901 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2902 * @retval None
<> 134:ad3be0349dc5 2903 */
<> 134:ad3be0349dc5 2904 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 2905 {
<> 134:ad3be0349dc5 2906 /* Note: Write register with some additional bits forced to state reset */
<> 134:ad3be0349dc5 2907 /* instead of modifying only the selected bit for this function, */
<> 134:ad3be0349dc5 2908 /* to not interfere with bits with HW property "rs". */
<> 134:ad3be0349dc5 2909 MODIFY_REG(ADCx->CR,
<> 134:ad3be0349dc5 2910 ADC_CR_BITS_PROPERTY_RS,
<> 134:ad3be0349dc5 2911 ADC_CR_ADSTART);
<> 134:ad3be0349dc5 2912 }
<> 134:ad3be0349dc5 2913
<> 134:ad3be0349dc5 2914 /**
<> 134:ad3be0349dc5 2915 * @brief Stop ADC group regular conversion.
<> 134:ad3be0349dc5 2916 * @note On this STM32 serie, setting of this feature is conditioned to
<> 134:ad3be0349dc5 2917 * ADC state:
<> 134:ad3be0349dc5 2918 * ADC must be enabled with conversion on going on group regular,
<> 134:ad3be0349dc5 2919 * without ADC disable command on going.
<> 134:ad3be0349dc5 2920 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
<> 134:ad3be0349dc5 2921 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2922 * @retval None
<> 134:ad3be0349dc5 2923 */
<> 134:ad3be0349dc5 2924 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 2925 {
<> 134:ad3be0349dc5 2926 /* Note: Write register with some additional bits forced to state reset */
<> 134:ad3be0349dc5 2927 /* instead of modifying only the selected bit for this function, */
<> 134:ad3be0349dc5 2928 /* to not interfere with bits with HW property "rs". */
<> 134:ad3be0349dc5 2929 MODIFY_REG(ADCx->CR,
<> 134:ad3be0349dc5 2930 ADC_CR_BITS_PROPERTY_RS,
<> 134:ad3be0349dc5 2931 ADC_CR_ADSTP);
<> 134:ad3be0349dc5 2932 }
<> 134:ad3be0349dc5 2933
<> 134:ad3be0349dc5 2934 /**
<> 134:ad3be0349dc5 2935 * @brief Get ADC group regular conversion state.
<> 134:ad3be0349dc5 2936 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
<> 134:ad3be0349dc5 2937 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2938 * @retval 0: no conversion is on going on ADC group regular.
<> 134:ad3be0349dc5 2939 */
<> 134:ad3be0349dc5 2940 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 2941 {
<> 134:ad3be0349dc5 2942 return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART));
<> 134:ad3be0349dc5 2943 }
<> 134:ad3be0349dc5 2944
<> 134:ad3be0349dc5 2945 /**
<> 134:ad3be0349dc5 2946 * @brief Get ADC group regular command of conversion stop state
<> 134:ad3be0349dc5 2947 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
<> 134:ad3be0349dc5 2948 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2949 * @retval 0: no command of conversion stop is on going on ADC group regular.
<> 134:ad3be0349dc5 2950 */
<> 134:ad3be0349dc5 2951 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 2952 {
<> 134:ad3be0349dc5 2953 return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP));
<> 134:ad3be0349dc5 2954 }
<> 134:ad3be0349dc5 2955
<> 134:ad3be0349dc5 2956 /**
<> 134:ad3be0349dc5 2957 * @brief Get ADC group regular conversion data, range fit for
<> 134:ad3be0349dc5 2958 * all ADC configurations: all ADC resolutions and
<> 134:ad3be0349dc5 2959 * all oversampling increased data width (for devices
<> 134:ad3be0349dc5 2960 * with feature oversampling).
<> 134:ad3be0349dc5 2961 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData32
<> 134:ad3be0349dc5 2962 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2963 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
<> 134:ad3be0349dc5 2964 */
<> 134:ad3be0349dc5 2965 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 2966 {
<> 134:ad3be0349dc5 2967 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<> 134:ad3be0349dc5 2968 }
<> 134:ad3be0349dc5 2969
<> 134:ad3be0349dc5 2970 /**
<> 134:ad3be0349dc5 2971 * @brief Get ADC group regular conversion data, range fit for
<> 134:ad3be0349dc5 2972 * ADC resolution 12 bits.
<> 134:ad3be0349dc5 2973 * @note For devices with feature oversampling: Oversampling
<> 134:ad3be0349dc5 2974 * can increase data width, function for extended range
<> 134:ad3be0349dc5 2975 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
<> 134:ad3be0349dc5 2976 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData12
<> 134:ad3be0349dc5 2977 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2978 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<> 134:ad3be0349dc5 2979 */
<> 134:ad3be0349dc5 2980 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 2981 {
<> 134:ad3be0349dc5 2982 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<> 134:ad3be0349dc5 2983 }
<> 134:ad3be0349dc5 2984
<> 134:ad3be0349dc5 2985 /**
<> 134:ad3be0349dc5 2986 * @brief Get ADC group regular conversion data, range fit for
<> 134:ad3be0349dc5 2987 * ADC resolution 10 bits.
<> 134:ad3be0349dc5 2988 * @note For devices with feature oversampling: Oversampling
<> 134:ad3be0349dc5 2989 * can increase data width, function for extended range
<> 134:ad3be0349dc5 2990 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
<> 134:ad3be0349dc5 2991 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData10
<> 134:ad3be0349dc5 2992 * @param ADCx ADC instance
<> 134:ad3be0349dc5 2993 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
<> 134:ad3be0349dc5 2994 */
<> 134:ad3be0349dc5 2995 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 2996 {
<> 134:ad3be0349dc5 2997 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<> 134:ad3be0349dc5 2998 }
<> 134:ad3be0349dc5 2999
<> 134:ad3be0349dc5 3000 /**
<> 134:ad3be0349dc5 3001 * @brief Get ADC group regular conversion data, range fit for
<> 134:ad3be0349dc5 3002 * ADC resolution 8 bits.
<> 134:ad3be0349dc5 3003 * @note For devices with feature oversampling: Oversampling
<> 134:ad3be0349dc5 3004 * can increase data width, function for extended range
<> 134:ad3be0349dc5 3005 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
<> 134:ad3be0349dc5 3006 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData8
<> 134:ad3be0349dc5 3007 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3008 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
<> 134:ad3be0349dc5 3009 */
<> 134:ad3be0349dc5 3010 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3011 {
<> 134:ad3be0349dc5 3012 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<> 134:ad3be0349dc5 3013 }
<> 134:ad3be0349dc5 3014
<> 134:ad3be0349dc5 3015 /**
<> 134:ad3be0349dc5 3016 * @brief Get ADC group regular conversion data, range fit for
<> 134:ad3be0349dc5 3017 * ADC resolution 6 bits.
<> 134:ad3be0349dc5 3018 * @note For devices with feature oversampling: Oversampling
<> 134:ad3be0349dc5 3019 * can increase data width, function for extended range
<> 134:ad3be0349dc5 3020 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
<> 134:ad3be0349dc5 3021 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData6
<> 134:ad3be0349dc5 3022 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3023 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
<> 134:ad3be0349dc5 3024 */
<> 134:ad3be0349dc5 3025 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3026 {
<> 134:ad3be0349dc5 3027 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<> 134:ad3be0349dc5 3028 }
<> 134:ad3be0349dc5 3029
<> 134:ad3be0349dc5 3030 /**
<> 134:ad3be0349dc5 3031 * @}
<> 134:ad3be0349dc5 3032 */
<> 134:ad3be0349dc5 3033
<> 134:ad3be0349dc5 3034 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
<> 134:ad3be0349dc5 3035 * @{
<> 134:ad3be0349dc5 3036 */
<> 134:ad3be0349dc5 3037
<> 134:ad3be0349dc5 3038 /**
<> 134:ad3be0349dc5 3039 * @brief Get flag ADC ready.
<> 134:ad3be0349dc5 3040 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
<> 134:ad3be0349dc5 3041 * is enabled and when conversion clock is active.
<> 134:ad3be0349dc5 3042 * (not only core clock: this ADC has a dual clock domain)
<> 134:ad3be0349dc5 3043 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
<> 134:ad3be0349dc5 3044 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3045 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 3046 */
<> 134:ad3be0349dc5 3047 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3048 {
<> 134:ad3be0349dc5 3049 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY));
<> 134:ad3be0349dc5 3050 }
<> 134:ad3be0349dc5 3051
<> 134:ad3be0349dc5 3052 /**
<> 134:ad3be0349dc5 3053 * @brief Get flag ADC group regular end of unitary conversion.
<> 134:ad3be0349dc5 3054 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
<> 134:ad3be0349dc5 3055 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3056 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 3057 */
<> 134:ad3be0349dc5 3058 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3059 {
<> 134:ad3be0349dc5 3060 return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC));
<> 134:ad3be0349dc5 3061 }
<> 134:ad3be0349dc5 3062
<> 134:ad3be0349dc5 3063 /**
<> 134:ad3be0349dc5 3064 * @brief Get flag ADC group regular end of sequence conversions.
<> 134:ad3be0349dc5 3065 * @rmtoll ISR EOSEQ LL_ADC_IsActiveFlag_EOS
<> 134:ad3be0349dc5 3066 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3067 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 3068 */
<> 134:ad3be0349dc5 3069 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3070 {
<> 134:ad3be0349dc5 3071 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
<> 134:ad3be0349dc5 3072 }
<> 134:ad3be0349dc5 3073
<> 134:ad3be0349dc5 3074 /**
<> 134:ad3be0349dc5 3075 * @brief Get flag ADC group regular overrun.
<> 134:ad3be0349dc5 3076 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
<> 134:ad3be0349dc5 3077 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3078 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 3079 */
<> 134:ad3be0349dc5 3080 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3081 {
<> 134:ad3be0349dc5 3082 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
<> 134:ad3be0349dc5 3083 }
<> 134:ad3be0349dc5 3084
<> 134:ad3be0349dc5 3085 /**
<> 134:ad3be0349dc5 3086 * @brief Get flag ADC group regular end of sampling phase.
<> 134:ad3be0349dc5 3087 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
<> 134:ad3be0349dc5 3088 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3089 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 3090 */
<> 134:ad3be0349dc5 3091 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3092 {
<> 134:ad3be0349dc5 3093 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP));
<> 134:ad3be0349dc5 3094 }
<> 134:ad3be0349dc5 3095
<> 134:ad3be0349dc5 3096 /**
<> 134:ad3be0349dc5 3097 * @brief Get flag ADC analog watchdog 1 flag
<> 134:ad3be0349dc5 3098 * @rmtoll ISR AWD LL_ADC_IsActiveFlag_AWD1
<> 134:ad3be0349dc5 3099 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3100 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 3101 */
<> 134:ad3be0349dc5 3102 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3103 {
<> 134:ad3be0349dc5 3104 return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
<> 134:ad3be0349dc5 3105 }
<> 134:ad3be0349dc5 3106
<> 134:ad3be0349dc5 3107 /**
<> 134:ad3be0349dc5 3108 * @brief Clear flag ADC ready.
<> 134:ad3be0349dc5 3109 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
<> 134:ad3be0349dc5 3110 * is enabled and when conversion clock is active.
<> 134:ad3be0349dc5 3111 * (not only core clock: this ADC has a dual clock domain)
<> 134:ad3be0349dc5 3112 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
<> 134:ad3be0349dc5 3113 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3114 * @retval None
<> 134:ad3be0349dc5 3115 */
<> 134:ad3be0349dc5 3116 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3117 {
<> 134:ad3be0349dc5 3118 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
<> 134:ad3be0349dc5 3119 }
<> 134:ad3be0349dc5 3120
<> 134:ad3be0349dc5 3121 /**
<> 134:ad3be0349dc5 3122 * @brief Clear flag ADC group regular end of unitary conversion.
<> 134:ad3be0349dc5 3123 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
<> 134:ad3be0349dc5 3124 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3125 * @retval None
<> 134:ad3be0349dc5 3126 */
<> 134:ad3be0349dc5 3127 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3128 {
<> 134:ad3be0349dc5 3129 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
<> 134:ad3be0349dc5 3130 }
<> 134:ad3be0349dc5 3131
<> 134:ad3be0349dc5 3132 /**
<> 134:ad3be0349dc5 3133 * @brief Clear flag ADC group regular end of sequence conversions.
<> 134:ad3be0349dc5 3134 * @rmtoll ISR EOSEQ LL_ADC_ClearFlag_EOS
<> 134:ad3be0349dc5 3135 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3136 * @retval None
<> 134:ad3be0349dc5 3137 */
<> 134:ad3be0349dc5 3138 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3139 {
<> 134:ad3be0349dc5 3140 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
<> 134:ad3be0349dc5 3141 }
<> 134:ad3be0349dc5 3142
<> 134:ad3be0349dc5 3143 /**
<> 134:ad3be0349dc5 3144 * @brief Clear flag ADC group regular overrun.
<> 134:ad3be0349dc5 3145 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
<> 134:ad3be0349dc5 3146 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3147 * @retval None
<> 134:ad3be0349dc5 3148 */
<> 134:ad3be0349dc5 3149 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3150 {
<> 134:ad3be0349dc5 3151 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
<> 134:ad3be0349dc5 3152 }
<> 134:ad3be0349dc5 3153
<> 134:ad3be0349dc5 3154 /**
<> 134:ad3be0349dc5 3155 * @brief Clear flag ADC group regular end of sampling phase.
<> 134:ad3be0349dc5 3156 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
<> 134:ad3be0349dc5 3157 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3158 * @retval None
<> 134:ad3be0349dc5 3159 */
<> 134:ad3be0349dc5 3160 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3161 {
<> 134:ad3be0349dc5 3162 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
<> 134:ad3be0349dc5 3163 }
<> 134:ad3be0349dc5 3164
<> 134:ad3be0349dc5 3165 /**
<> 134:ad3be0349dc5 3166 * @brief Clear flag ADC analog watchdog 1.
<> 134:ad3be0349dc5 3167 * @rmtoll ISR AWD LL_ADC_ClearFlag_AWD1
<> 134:ad3be0349dc5 3168 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3169 * @retval None
<> 134:ad3be0349dc5 3170 */
<> 134:ad3be0349dc5 3171 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3172 {
<> 134:ad3be0349dc5 3173 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
<> 134:ad3be0349dc5 3174 }
<> 134:ad3be0349dc5 3175
<> 134:ad3be0349dc5 3176 /**
<> 134:ad3be0349dc5 3177 * @}
<> 134:ad3be0349dc5 3178 */
<> 134:ad3be0349dc5 3179
<> 134:ad3be0349dc5 3180 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
<> 134:ad3be0349dc5 3181 * @{
<> 134:ad3be0349dc5 3182 */
<> 134:ad3be0349dc5 3183
<> 134:ad3be0349dc5 3184 /**
<> 134:ad3be0349dc5 3185 * @brief Enable ADC ready.
<> 134:ad3be0349dc5 3186 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
<> 134:ad3be0349dc5 3187 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3188 * @retval None
<> 134:ad3be0349dc5 3189 */
<> 134:ad3be0349dc5 3190 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3191 {
<> 134:ad3be0349dc5 3192 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
<> 134:ad3be0349dc5 3193 }
<> 134:ad3be0349dc5 3194
<> 134:ad3be0349dc5 3195 /**
<> 134:ad3be0349dc5 3196 * @brief Enable interruption ADC group regular end of unitary conversion.
<> 134:ad3be0349dc5 3197 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
<> 134:ad3be0349dc5 3198 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3199 * @retval None
<> 134:ad3be0349dc5 3200 */
<> 134:ad3be0349dc5 3201 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3202 {
<> 134:ad3be0349dc5 3203 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
<> 134:ad3be0349dc5 3204 }
<> 134:ad3be0349dc5 3205
<> 134:ad3be0349dc5 3206 /**
<> 134:ad3be0349dc5 3207 * @brief Enable interruption ADC group regular end of sequence conversions.
<> 134:ad3be0349dc5 3208 * @rmtoll IER EOSEQIE LL_ADC_EnableIT_EOS
<> 134:ad3be0349dc5 3209 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3210 * @retval None
<> 134:ad3be0349dc5 3211 */
<> 134:ad3be0349dc5 3212 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3213 {
<> 134:ad3be0349dc5 3214 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
<> 134:ad3be0349dc5 3215 }
<> 134:ad3be0349dc5 3216
<> 134:ad3be0349dc5 3217 /**
<> 134:ad3be0349dc5 3218 * @brief Enable ADC group regular interruption overrun.
<> 134:ad3be0349dc5 3219 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
<> 134:ad3be0349dc5 3220 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3221 * @retval None
<> 134:ad3be0349dc5 3222 */
<> 134:ad3be0349dc5 3223 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3224 {
<> 134:ad3be0349dc5 3225 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
<> 134:ad3be0349dc5 3226 }
<> 134:ad3be0349dc5 3227
<> 134:ad3be0349dc5 3228 /**
<> 134:ad3be0349dc5 3229 * @brief Enable interruption ADC group regular end of sampling.
<> 134:ad3be0349dc5 3230 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
<> 134:ad3be0349dc5 3231 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3232 * @retval None
<> 134:ad3be0349dc5 3233 */
<> 134:ad3be0349dc5 3234 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3235 {
<> 134:ad3be0349dc5 3236 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
<> 134:ad3be0349dc5 3237 }
<> 134:ad3be0349dc5 3238
<> 134:ad3be0349dc5 3239 /**
<> 134:ad3be0349dc5 3240 * @brief Enable interruption ADC analog watchdog 1.
<> 134:ad3be0349dc5 3241 * @rmtoll IER AWDIE LL_ADC_EnableIT_AWD1
<> 134:ad3be0349dc5 3242 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3243 * @retval None
<> 134:ad3be0349dc5 3244 */
<> 134:ad3be0349dc5 3245 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3246 {
<> 134:ad3be0349dc5 3247 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
<> 134:ad3be0349dc5 3248 }
<> 134:ad3be0349dc5 3249
<> 134:ad3be0349dc5 3250 /**
<> 134:ad3be0349dc5 3251 * @brief Disable interruption ADC ready.
<> 134:ad3be0349dc5 3252 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
<> 134:ad3be0349dc5 3253 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3254 * @retval None
<> 134:ad3be0349dc5 3255 */
<> 134:ad3be0349dc5 3256 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3257 {
<> 134:ad3be0349dc5 3258 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
<> 134:ad3be0349dc5 3259 }
<> 134:ad3be0349dc5 3260
<> 134:ad3be0349dc5 3261 /**
<> 134:ad3be0349dc5 3262 * @brief Disable interruption ADC group regular end of unitary conversion.
<> 134:ad3be0349dc5 3263 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
<> 134:ad3be0349dc5 3264 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3265 * @retval None
<> 134:ad3be0349dc5 3266 */
<> 134:ad3be0349dc5 3267 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3268 {
<> 134:ad3be0349dc5 3269 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
<> 134:ad3be0349dc5 3270 }
<> 134:ad3be0349dc5 3271
<> 134:ad3be0349dc5 3272 /**
<> 134:ad3be0349dc5 3273 * @brief Disable interruption ADC group regular end of sequence conversions.
<> 134:ad3be0349dc5 3274 * @rmtoll IER EOSEQIE LL_ADC_DisableIT_EOS
<> 134:ad3be0349dc5 3275 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3276 * @retval None
<> 134:ad3be0349dc5 3277 */
<> 134:ad3be0349dc5 3278 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3279 {
<> 134:ad3be0349dc5 3280 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
<> 134:ad3be0349dc5 3281 }
<> 134:ad3be0349dc5 3282
<> 134:ad3be0349dc5 3283 /**
<> 134:ad3be0349dc5 3284 * @brief Disable interruption ADC group regular overrun.
<> 134:ad3be0349dc5 3285 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
<> 134:ad3be0349dc5 3286 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3287 * @retval None
<> 134:ad3be0349dc5 3288 */
<> 134:ad3be0349dc5 3289 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3290 {
<> 134:ad3be0349dc5 3291 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
<> 134:ad3be0349dc5 3292 }
<> 134:ad3be0349dc5 3293
<> 134:ad3be0349dc5 3294 /**
<> 134:ad3be0349dc5 3295 * @brief Disable interruption ADC group regular end of sampling.
<> 134:ad3be0349dc5 3296 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
<> 134:ad3be0349dc5 3297 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3298 * @retval None
<> 134:ad3be0349dc5 3299 */
<> 134:ad3be0349dc5 3300 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3301 {
<> 134:ad3be0349dc5 3302 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
<> 134:ad3be0349dc5 3303 }
<> 134:ad3be0349dc5 3304
<> 134:ad3be0349dc5 3305 /**
<> 134:ad3be0349dc5 3306 * @brief Disable interruption ADC analog watchdog 1.
<> 134:ad3be0349dc5 3307 * @rmtoll IER AWDIE LL_ADC_DisableIT_AWD1
<> 134:ad3be0349dc5 3308 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3309 * @retval None
<> 134:ad3be0349dc5 3310 */
<> 134:ad3be0349dc5 3311 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3312 {
<> 134:ad3be0349dc5 3313 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
<> 134:ad3be0349dc5 3314 }
<> 134:ad3be0349dc5 3315
<> 134:ad3be0349dc5 3316 /**
<> 134:ad3be0349dc5 3317 * @brief Get state of interruption ADC ready
<> 134:ad3be0349dc5 3318 * (0: interrupt disabled, 1: interrupt enabled).
<> 134:ad3be0349dc5 3319 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
<> 134:ad3be0349dc5 3320 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3321 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 3322 */
<> 134:ad3be0349dc5 3323 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3324 {
<> 134:ad3be0349dc5 3325 return (READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY));
<> 134:ad3be0349dc5 3326 }
<> 134:ad3be0349dc5 3327
<> 134:ad3be0349dc5 3328 /**
<> 134:ad3be0349dc5 3329 * @brief Get state of interruption ADC group regular end of unitary conversion
<> 134:ad3be0349dc5 3330 * (0: interrupt disabled, 1: interrupt enabled).
<> 134:ad3be0349dc5 3331 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
<> 134:ad3be0349dc5 3332 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3333 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 3334 */
<> 134:ad3be0349dc5 3335 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3336 {
<> 134:ad3be0349dc5 3337 return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC));
<> 134:ad3be0349dc5 3338 }
<> 134:ad3be0349dc5 3339
<> 134:ad3be0349dc5 3340 /**
<> 134:ad3be0349dc5 3341 * @brief Get state of interruption ADC group regular end of sequence conversions
<> 134:ad3be0349dc5 3342 * (0: interrupt disabled, 1: interrupt enabled).
<> 134:ad3be0349dc5 3343 * @rmtoll IER EOSEQIE LL_ADC_IsEnabledIT_EOS
<> 134:ad3be0349dc5 3344 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3345 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 3346 */
<> 134:ad3be0349dc5 3347 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3348 {
<> 134:ad3be0349dc5 3349 return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
<> 134:ad3be0349dc5 3350 }
<> 134:ad3be0349dc5 3351
<> 134:ad3be0349dc5 3352 /**
<> 134:ad3be0349dc5 3353 * @brief Get state of interruption ADC group regular overrun
<> 134:ad3be0349dc5 3354 * (0: interrupt disabled, 1: interrupt enabled).
<> 134:ad3be0349dc5 3355 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
<> 134:ad3be0349dc5 3356 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3357 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 3358 */
<> 134:ad3be0349dc5 3359 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3360 {
<> 134:ad3be0349dc5 3361 return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
<> 134:ad3be0349dc5 3362 }
<> 134:ad3be0349dc5 3363
<> 134:ad3be0349dc5 3364 /**
<> 134:ad3be0349dc5 3365 * @brief Get state of interruption ADC group regular end of sampling
<> 134:ad3be0349dc5 3366 * (0: interrupt disabled, 1: interrupt enabled).
<> 134:ad3be0349dc5 3367 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
<> 134:ad3be0349dc5 3368 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3369 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 3370 */
<> 134:ad3be0349dc5 3371 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3372 {
<> 134:ad3be0349dc5 3373 return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP));
<> 134:ad3be0349dc5 3374 }
<> 134:ad3be0349dc5 3375
<> 134:ad3be0349dc5 3376 /**
<> 134:ad3be0349dc5 3377 * @brief Get state of interruption ADC analog watchdog 1
<> 134:ad3be0349dc5 3378 * (0: interrupt disabled, 1: interrupt enabled).
<> 134:ad3be0349dc5 3379 * @rmtoll IER AWDIE LL_ADC_IsEnabledIT_AWD1
<> 134:ad3be0349dc5 3380 * @param ADCx ADC instance
<> 134:ad3be0349dc5 3381 * @retval State of bit (1 or 0).
<> 134:ad3be0349dc5 3382 */
<> 134:ad3be0349dc5 3383 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
<> 134:ad3be0349dc5 3384 {
<> 134:ad3be0349dc5 3385 return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
<> 134:ad3be0349dc5 3386 }
<> 134:ad3be0349dc5 3387
<> 134:ad3be0349dc5 3388 /**
<> 134:ad3be0349dc5 3389 * @}
<> 134:ad3be0349dc5 3390 */
<> 134:ad3be0349dc5 3391
<> 134:ad3be0349dc5 3392 #if defined(USE_FULL_LL_DRIVER)
<> 134:ad3be0349dc5 3393 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
<> 134:ad3be0349dc5 3394 * @{
<> 134:ad3be0349dc5 3395 */
<> 134:ad3be0349dc5 3396
<> 134:ad3be0349dc5 3397 /* Initialization of some features of ADC common parameters and multimode */
<> 134:ad3be0349dc5 3398 /* Note: On this STM32 serie, there is no ADC common initialization */
<> 134:ad3be0349dc5 3399 /* function. */
<> 134:ad3be0349dc5 3400 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
<> 134:ad3be0349dc5 3401
<> 134:ad3be0349dc5 3402 /* De-initialization of ADC instance */
<> 134:ad3be0349dc5 3403 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
<> 134:ad3be0349dc5 3404
<> 134:ad3be0349dc5 3405 /* Initialization of some features of ADC instance */
<> 134:ad3be0349dc5 3406 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
<> 134:ad3be0349dc5 3407 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
<> 134:ad3be0349dc5 3408
<> 134:ad3be0349dc5 3409 /* Initialization of some features of ADC instance and ADC group regular */
<> 134:ad3be0349dc5 3410 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
<> 134:ad3be0349dc5 3411 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
<> 134:ad3be0349dc5 3412
<> 134:ad3be0349dc5 3413 /**
<> 134:ad3be0349dc5 3414 * @}
<> 134:ad3be0349dc5 3415 */
<> 134:ad3be0349dc5 3416 #endif /* USE_FULL_LL_DRIVER */
<> 134:ad3be0349dc5 3417
<> 134:ad3be0349dc5 3418 /**
<> 134:ad3be0349dc5 3419 * @}
<> 134:ad3be0349dc5 3420 */
<> 134:ad3be0349dc5 3421
<> 134:ad3be0349dc5 3422 /**
<> 134:ad3be0349dc5 3423 * @}
<> 134:ad3be0349dc5 3424 */
<> 134:ad3be0349dc5 3425
<> 134:ad3be0349dc5 3426 #endif /* ADC1 */
<> 134:ad3be0349dc5 3427
<> 134:ad3be0349dc5 3428 /**
<> 134:ad3be0349dc5 3429 * @}
<> 134:ad3be0349dc5 3430 */
<> 134:ad3be0349dc5 3431
<> 134:ad3be0349dc5 3432 #ifdef __cplusplus
<> 134:ad3be0349dc5 3433 }
<> 134:ad3be0349dc5 3434 #endif
<> 134:ad3be0349dc5 3435
<> 134:ad3be0349dc5 3436 #endif /* __STM32F0xx_LL_ADC_H */
<> 134:ad3be0349dc5 3437
<> 134:ad3be0349dc5 3438 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/