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mbed 2

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TARGET_NUCLEO_F030R8/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
134:ad3be0349dc5 
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 85:024bf7f99721 1 /**
bogdanm 85:024bf7f99721 2 ******************************************************************************
bogdanm 85:024bf7f99721 3 * @file stm32f0xx_hal_rcc.h
bogdanm 85:024bf7f99721 4 * @author MCD Application Team
<> 134:ad3be0349dc5 5 * @version V1.5.0
<> 134:ad3be0349dc5 6 * @date 04-November-2016
bogdanm 85:024bf7f99721 7 * @brief Header file of RCC HAL module.
bogdanm 85:024bf7f99721 8 ******************************************************************************
bogdanm 85:024bf7f99721 9 * @attention
bogdanm 85:024bf7f99721 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 85:024bf7f99721 12 *
bogdanm 85:024bf7f99721 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 85:024bf7f99721 14 * are permitted provided that the following conditions are met:
bogdanm 85:024bf7f99721 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 85:024bf7f99721 16 * this list of conditions and the following disclaimer.
bogdanm 85:024bf7f99721 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 85:024bf7f99721 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 85:024bf7f99721 19 * and/or other materials provided with the distribution.
bogdanm 85:024bf7f99721 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 85:024bf7f99721 21 * may be used to endorse or promote products derived from this software
bogdanm 85:024bf7f99721 22 * without specific prior written permission.
bogdanm 85:024bf7f99721 23 *
bogdanm 85:024bf7f99721 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 85:024bf7f99721 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 85:024bf7f99721 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 85:024bf7f99721 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 85:024bf7f99721 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 85:024bf7f99721 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 85:024bf7f99721 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 85:024bf7f99721 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 85:024bf7f99721 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 85:024bf7f99721 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 85:024bf7f99721 34 *
bogdanm 85:024bf7f99721 35 ******************************************************************************
Kojto 122:f9eeca106725 36 */
bogdanm 85:024bf7f99721 37
bogdanm 85:024bf7f99721 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 85:024bf7f99721 39 #ifndef __STM32F0xx_HAL_RCC_H
bogdanm 85:024bf7f99721 40 #define __STM32F0xx_HAL_RCC_H
bogdanm 85:024bf7f99721 41
bogdanm 85:024bf7f99721 42 #ifdef __cplusplus
bogdanm 85:024bf7f99721 43 extern "C" {
bogdanm 85:024bf7f99721 44 #endif
bogdanm 85:024bf7f99721 45
bogdanm 85:024bf7f99721 46 /* Includes ------------------------------------------------------------------*/
bogdanm 85:024bf7f99721 47 #include "stm32f0xx_hal_def.h"
bogdanm 85:024bf7f99721 48
bogdanm 85:024bf7f99721 49 /** @addtogroup STM32F0xx_HAL_Driver
bogdanm 85:024bf7f99721 50 * @{
bogdanm 85:024bf7f99721 51 */
bogdanm 85:024bf7f99721 52
bogdanm 85:024bf7f99721 53 /** @addtogroup RCC
bogdanm 85:024bf7f99721 54 * @{
Kojto 122:f9eeca106725 55 */
Kojto 108:34e6b704fe68 56
Kojto 108:34e6b704fe68 57 /** @addtogroup RCC_Private_Constants
Kojto 108:34e6b704fe68 58 * @{
Kojto 108:34e6b704fe68 59 */
Kojto 108:34e6b704fe68 60
Kojto 108:34e6b704fe68 61 /** @defgroup RCC_Timeout RCC Timeout
Kojto 108:34e6b704fe68 62 * @{
Kojto 122:f9eeca106725 63 */
Kojto 108:34e6b704fe68 64
Kojto 108:34e6b704fe68 65 /* Disable Backup domain write protection state change timeout */
<> 134:ad3be0349dc5 66 #define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */
Kojto 108:34e6b704fe68 67 /* LSE state change timeout */
Kojto 108:34e6b704fe68 68 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
<> 134:ad3be0349dc5 69 #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
Kojto 122:f9eeca106725 70 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
<> 134:ad3be0349dc5 71 #define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
<> 134:ad3be0349dc5 72 #define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
<> 134:ad3be0349dc5 73 #define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
<> 134:ad3be0349dc5 74 #define HSI14_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
Kojto 122:f9eeca106725 75 #if defined(RCC_HSI48_SUPPORT)
<> 134:ad3be0349dc5 76 #define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
Kojto 122:f9eeca106725 77 #endif /* RCC_HSI48_SUPPORT */
Kojto 108:34e6b704fe68 78 /**
Kojto 108:34e6b704fe68 79 * @}
Kojto 108:34e6b704fe68 80 */
Kojto 108:34e6b704fe68 81
Kojto 108:34e6b704fe68 82 /** @defgroup RCC_Register_Offset Register offsets
Kojto 108:34e6b704fe68 83 * @{
Kojto 108:34e6b704fe68 84 */
Kojto 108:34e6b704fe68 85 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
<> 134:ad3be0349dc5 86 #define RCC_CR_OFFSET 0x00U
<> 134:ad3be0349dc5 87 #define RCC_CFGR_OFFSET 0x04U
<> 134:ad3be0349dc5 88 #define RCC_CIR_OFFSET 0x08U
<> 134:ad3be0349dc5 89 #define RCC_BDCR_OFFSET 0x20U
<> 134:ad3be0349dc5 90 #define RCC_CSR_OFFSET 0x24U
Kojto 108:34e6b704fe68 91
Kojto 108:34e6b704fe68 92 /**
Kojto 108:34e6b704fe68 93 * @}
bogdanm 85:024bf7f99721 94 */
bogdanm 85:024bf7f99721 95
Kojto 108:34e6b704fe68 96
Kojto 108:34e6b704fe68 97 /* CR register byte 2 (Bits[23:16]) base address */
<> 134:ad3be0349dc5 98 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
Kojto 108:34e6b704fe68 99
Kojto 108:34e6b704fe68 100 /* CIR register byte 1 (Bits[15:8]) base address */
<> 134:ad3be0349dc5 101 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
Kojto 108:34e6b704fe68 102
Kojto 108:34e6b704fe68 103 /* CIR register byte 2 (Bits[23:16]) base address */
<> 134:ad3be0349dc5 104 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
Kojto 108:34e6b704fe68 105
Kojto 108:34e6b704fe68 106 /* Defines used for Flags */
<> 134:ad3be0349dc5 107 #define CR_REG_INDEX ((uint8_t)1U)
<> 134:ad3be0349dc5 108 #define CR2_REG_INDEX ((uint8_t)2U)
<> 134:ad3be0349dc5 109 #define BDCR_REG_INDEX ((uint8_t)3U)
<> 134:ad3be0349dc5 110 #define CSR_REG_INDEX ((uint8_t)4U)
Kojto 108:34e6b704fe68 111
Kojto 122:f9eeca106725 112 /* Bits position in in the CFGR register */
Kojto 122:f9eeca106725 113 #define RCC_CFGR_PLLMUL_BITNUMBER 18U
Kojto 122:f9eeca106725 114 #define RCC_CFGR_HPRE_BITNUMBER 4U
Kojto 122:f9eeca106725 115 #define RCC_CFGR_PPRE_BITNUMBER 8U
Kojto 108:34e6b704fe68 116 /* Flags in the CFGR2 register */
<> 134:ad3be0349dc5 117 #define RCC_CFGR2_PREDIV_BITNUMBER 0U
Kojto 108:34e6b704fe68 118 /* Flags in the CR register */
<> 134:ad3be0349dc5 119 #define RCC_CR_HSIRDY_BitNumber 1U
<> 134:ad3be0349dc5 120 #define RCC_CR_HSERDY_BitNumber 17U
<> 134:ad3be0349dc5 121 #define RCC_CR_PLLRDY_BitNumber 25U
Kojto 108:34e6b704fe68 122 /* Flags in the CR2 register */
<> 134:ad3be0349dc5 123 #define RCC_CR2_HSI14RDY_BitNumber 1U
<> 134:ad3be0349dc5 124 #define RCC_CR2_HSI48RDY_BitNumber 16U
Kojto 108:34e6b704fe68 125 /* Flags in the BDCR register */
<> 134:ad3be0349dc5 126 #define RCC_BDCR_LSERDY_BitNumber 1U
Kojto 108:34e6b704fe68 127 /* Flags in the CSR register */
<> 134:ad3be0349dc5 128 #define RCC_CSR_LSIRDY_BitNumber 1U
<> 134:ad3be0349dc5 129 #define RCC_CSR_V18PWRRSTF_BitNumber 23U
<> 134:ad3be0349dc5 130 #define RCC_CSR_RMVF_BitNumber 24U
<> 134:ad3be0349dc5 131 #define RCC_CSR_OBLRSTF_BitNumber 25U
<> 134:ad3be0349dc5 132 #define RCC_CSR_PINRSTF_BitNumber 26U
<> 134:ad3be0349dc5 133 #define RCC_CSR_PORRSTF_BitNumber 27U
<> 134:ad3be0349dc5 134 #define RCC_CSR_SFTRSTF_BitNumber 28U
<> 134:ad3be0349dc5 135 #define RCC_CSR_IWDGRSTF_BitNumber 29U
<> 134:ad3be0349dc5 136 #define RCC_CSR_WWDGRSTF_BitNumber 30U
<> 134:ad3be0349dc5 137 #define RCC_CSR_LPWRRSTF_BitNumber 31U
Kojto 108:34e6b704fe68 138 /* Flags in the HSITRIM register */
<> 134:ad3be0349dc5 139 #define RCC_CR_HSITRIM_BitNumber 3U
<> 134:ad3be0349dc5 140 #define RCC_HSI14TRIM_BIT_NUMBER 3U
<> 134:ad3be0349dc5 141 #define RCC_FLAG_MASK ((uint8_t)0x1FU)
Kojto 108:34e6b704fe68 142
Kojto 108:34e6b704fe68 143 /**
Kojto 108:34e6b704fe68 144 * @}
Kojto 108:34e6b704fe68 145 */
Kojto 108:34e6b704fe68 146
Kojto 108:34e6b704fe68 147 /** @addtogroup RCC_Private_Macros
Kojto 108:34e6b704fe68 148 * @{
Kojto 108:34e6b704fe68 149 */
Kojto 108:34e6b704fe68 150 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
Kojto 108:34e6b704fe68 151 ((__HSE__) == RCC_HSE_BYPASS))
Kojto 108:34e6b704fe68 152 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
Kojto 108:34e6b704fe68 153 ((__LSE__) == RCC_LSE_BYPASS))
Kojto 108:34e6b704fe68 154 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
Kojto 108:34e6b704fe68 155 #define IS_RCC_HSI14(__HSI14__) (((__HSI14__) == RCC_HSI14_OFF) || ((__HSI14__) == RCC_HSI14_ON) || ((__HSI14__) == RCC_HSI14_ADC_CONTROL))
<> 134:ad3be0349dc5 156 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
Kojto 108:34e6b704fe68 157 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
Kojto 108:34e6b704fe68 158 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
Kojto 108:34e6b704fe68 159 ((__PLL__) == RCC_PLL_ON))
Kojto 108:34e6b704fe68 160 #define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \
Kojto 108:34e6b704fe68 161 ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \
Kojto 108:34e6b704fe68 162 ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \
Kojto 108:34e6b704fe68 163 ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \
Kojto 108:34e6b704fe68 164 ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \
Kojto 108:34e6b704fe68 165 ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \
Kojto 108:34e6b704fe68 166 ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \
Kojto 108:34e6b704fe68 167 ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16))
Kojto 122:f9eeca106725 168
Kojto 108:34e6b704fe68 169 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
Kojto 108:34e6b704fe68 170 ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
Kojto 108:34e6b704fe68 171 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
Kojto 108:34e6b704fe68 172 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
Kojto 108:34e6b704fe68 173 ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
Kojto 108:34e6b704fe68 174 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
Kojto 108:34e6b704fe68 175 ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
Kojto 108:34e6b704fe68 176 ((__MUL__) == RCC_PLL_MUL16))
Kojto 108:34e6b704fe68 177 #define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
Kojto 108:34e6b704fe68 178 (((__CLK__) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
Kojto 108:34e6b704fe68 179 (((__CLK__) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1))
Kojto 108:34e6b704fe68 180 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
Kojto 108:34e6b704fe68 181 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
Kojto 108:34e6b704fe68 182 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
Kojto 108:34e6b704fe68 183 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
Kojto 108:34e6b704fe68 184 ((__HCLK__) == RCC_SYSCLK_DIV512))
Kojto 108:34e6b704fe68 185 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
Kojto 108:34e6b704fe68 186 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
Kojto 108:34e6b704fe68 187 ((__PCLK__) == RCC_HCLK_DIV16))
Kojto 122:f9eeca106725 188 #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
Kojto 108:34e6b704fe68 189 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
Kojto 108:34e6b704fe68 190 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
Kojto 108:34e6b704fe68 191 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
Kojto 108:34e6b704fe68 192 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
Kojto 108:34e6b704fe68 193 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \
Kojto 108:34e6b704fe68 194 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
Kojto 108:34e6b704fe68 195 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
Kojto 108:34e6b704fe68 196 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
Kojto 108:34e6b704fe68 197 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \
Kojto 108:34e6b704fe68 198 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK))
Kojto 108:34e6b704fe68 199
Kojto 108:34e6b704fe68 200 /**
Kojto 108:34e6b704fe68 201 * @}
Kojto 108:34e6b704fe68 202 */
Kojto 108:34e6b704fe68 203
Kojto 122:f9eeca106725 204 /* Exported types ------------------------------------------------------------*/
bogdanm 85:024bf7f99721 205
bogdanm 92:4fc01daae5a5 206 /** @defgroup RCC_Exported_Types RCC Exported Types
bogdanm 92:4fc01daae5a5 207 * @{
bogdanm 92:4fc01daae5a5 208 */
bogdanm 92:4fc01daae5a5 209
Kojto 108:34e6b704fe68 210 /**
Kojto 108:34e6b704fe68 211 * @brief RCC PLL configuration structure definition
bogdanm 85:024bf7f99721 212 */
bogdanm 85:024bf7f99721 213 typedef struct
bogdanm 85:024bf7f99721 214 {
Kojto 122:f9eeca106725 215 uint32_t PLLState; /*!< PLLState: The new state of the PLL.
Kojto 108:34e6b704fe68 216 This parameter can be a value of @ref RCC_PLL_Config */
bogdanm 85:024bf7f99721 217
Kojto 122:f9eeca106725 218 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
Kojto 122:f9eeca106725 219 This parameter must be a value of @ref RCC_PLL_Clock_Source */
bogdanm 85:024bf7f99721 220
Kojto 122:f9eeca106725 221 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
Kojto 122:f9eeca106725 222 This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
Kojto 122:f9eeca106725 223
Kojto 122:f9eeca106725 224 uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
Kojto 108:34e6b704fe68 225 This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
bogdanm 85:024bf7f99721 226
Kojto 108:34e6b704fe68 227 } RCC_PLLInitTypeDef;
Kojto 108:34e6b704fe68 228
Kojto 122:f9eeca106725 229 /**
Kojto 108:34e6b704fe68 230 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
bogdanm 85:024bf7f99721 231 */
bogdanm 85:024bf7f99721 232 typedef struct
bogdanm 85:024bf7f99721 233 {
Kojto 108:34e6b704fe68 234 uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto 108:34e6b704fe68 235 This parameter can be a value of @ref RCC_Oscillator_Type */
bogdanm 85:024bf7f99721 236
Kojto 108:34e6b704fe68 237 uint32_t HSEState; /*!< The new state of the HSE.
Kojto 108:34e6b704fe68 238 This parameter can be a value of @ref RCC_HSE_Config */
Kojto 122:f9eeca106725 239
Kojto 108:34e6b704fe68 240 uint32_t LSEState; /*!< The new state of the LSE.
Kojto 108:34e6b704fe68 241 This parameter can be a value of @ref RCC_LSE_Config */
Kojto 122:f9eeca106725 242
Kojto 108:34e6b704fe68 243 uint32_t HSIState; /*!< The new state of the HSI.
Kojto 108:34e6b704fe68 244 This parameter can be a value of @ref RCC_HSI_Config */
bogdanm 85:024bf7f99721 245
Kojto 108:34e6b704fe68 246 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
Kojto 108:34e6b704fe68 247 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto 122:f9eeca106725 248
bogdanm 85:024bf7f99721 249 uint32_t HSI14State; /*!< The new state of the HSI14.
bogdanm 85:024bf7f99721 250 This parameter can be a value of @ref RCC_HSI14_Config */
bogdanm 85:024bf7f99721 251
bogdanm 85:024bf7f99721 252 uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT).
bogdanm 85:024bf7f99721 253 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
bogdanm 85:024bf7f99721 254
Kojto 108:34e6b704fe68 255 uint32_t LSIState; /*!< The new state of the LSI.
Kojto 108:34e6b704fe68 256 This parameter can be a value of @ref RCC_LSI_Config */
bogdanm 85:024bf7f99721 257
Kojto 122:f9eeca106725 258 uint32_t HSI48State; /*!< The new state of the HSI48.
Kojto 122:f9eeca106725 259 This parameter can be a value of @ref RCC_HSI48_Config */
Kojto 122:f9eeca106725 260
Kojto 122:f9eeca106725 261 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
bogdanm 85:024bf7f99721 262
Kojto 108:34e6b704fe68 263 } RCC_OscInitTypeDef;
Kojto 108:34e6b704fe68 264
Kojto 122:f9eeca106725 265 /**
Kojto 108:34e6b704fe68 266 * @brief RCC System, AHB and APB busses clock configuration structure definition
bogdanm 85:024bf7f99721 267 */
bogdanm 85:024bf7f99721 268 typedef struct
bogdanm 85:024bf7f99721 269 {
Kojto 108:34e6b704fe68 270 uint32_t ClockType; /*!< The clock to be configured.
Kojto 108:34e6b704fe68 271 This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto 122:f9eeca106725 272
Kojto 108:34e6b704fe68 273 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Kojto 108:34e6b704fe68 274 This parameter can be a value of @ref RCC_System_Clock_Source */
bogdanm 85:024bf7f99721 275
Kojto 108:34e6b704fe68 276 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto 108:34e6b704fe68 277 This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto 122:f9eeca106725 278
Kojto 108:34e6b704fe68 279 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto 108:34e6b704fe68 280 This parameter can be a value of @ref RCC_APB1_Clock_Source */
Kojto 122:f9eeca106725 281
Kojto 108:34e6b704fe68 282 } RCC_ClkInitTypeDef;
bogdanm 85:024bf7f99721 283
bogdanm 92:4fc01daae5a5 284 /**
bogdanm 92:4fc01daae5a5 285 * @}
bogdanm 92:4fc01daae5a5 286 */
Kojto 108:34e6b704fe68 287
bogdanm 85:024bf7f99721 288 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 289 /** @defgroup RCC_Exported_Constants RCC Exported Constants
bogdanm 85:024bf7f99721 290 * @{
bogdanm 85:024bf7f99721 291 */
bogdanm 85:024bf7f99721 292
Kojto 108:34e6b704fe68 293 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
bogdanm 92:4fc01daae5a5 294 * @{
bogdanm 92:4fc01daae5a5 295 */
bogdanm 85:024bf7f99721 296
Kojto 108:34e6b704fe68 297 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */
bogdanm 92:4fc01daae5a5 298
bogdanm 92:4fc01daae5a5 299 /**
bogdanm 92:4fc01daae5a5 300 * @}
Kojto 122:f9eeca106725 301 */
bogdanm 85:024bf7f99721 302
Kojto 108:34e6b704fe68 303 /** @defgroup RCC_Oscillator_Type Oscillator Type
bogdanm 85:024bf7f99721 304 * @{
bogdanm 85:024bf7f99721 305 */
<> 134:ad3be0349dc5 306 #define RCC_OSCILLATORTYPE_NONE (0x00000000U)
<> 134:ad3be0349dc5 307 #define RCC_OSCILLATORTYPE_HSE (0x00000001U)
<> 134:ad3be0349dc5 308 #define RCC_OSCILLATORTYPE_HSI (0x00000002U)
<> 134:ad3be0349dc5 309 #define RCC_OSCILLATORTYPE_LSE (0x00000004U)
<> 134:ad3be0349dc5 310 #define RCC_OSCILLATORTYPE_LSI (0x00000008U)
<> 134:ad3be0349dc5 311 #define RCC_OSCILLATORTYPE_HSI14 (0x00000010U)
Kojto 122:f9eeca106725 312 #if defined(RCC_HSI48_SUPPORT)
<> 134:ad3be0349dc5 313 #define RCC_OSCILLATORTYPE_HSI48 (0x00000020U)
Kojto 122:f9eeca106725 314 #endif /* RCC_HSI48_SUPPORT */
bogdanm 85:024bf7f99721 315 /**
bogdanm 85:024bf7f99721 316 * @}
bogdanm 85:024bf7f99721 317 */
bogdanm 85:024bf7f99721 318
Kojto 108:34e6b704fe68 319 /** @defgroup RCC_HSE_Config HSE Config
bogdanm 85:024bf7f99721 320 * @{
bogdanm 85:024bf7f99721 321 */
<> 134:ad3be0349dc5 322 #define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */
<> 134:ad3be0349dc5 323 #define RCC_HSE_ON (0x00000001U) /*!< HSE clock activation */
<> 134:ad3be0349dc5 324 #define RCC_HSE_BYPASS (0x00000005U) /*!< External clock source for HSE clock */
bogdanm 85:024bf7f99721 325 /**
bogdanm 85:024bf7f99721 326 * @}
bogdanm 85:024bf7f99721 327 */
bogdanm 85:024bf7f99721 328
Kojto 108:34e6b704fe68 329 /** @defgroup RCC_LSE_Config LSE Config
bogdanm 85:024bf7f99721 330 * @{
bogdanm 85:024bf7f99721 331 */
<> 134:ad3be0349dc5 332 #define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */
<> 134:ad3be0349dc5 333 #define RCC_LSE_ON (0x00000001U) /*!< LSE clock activation */
<> 134:ad3be0349dc5 334 #define RCC_LSE_BYPASS (0x00000005U) /*!< External clock source for LSE clock */
bogdanm 85:024bf7f99721 335
bogdanm 85:024bf7f99721 336 /**
bogdanm 85:024bf7f99721 337 * @}
bogdanm 85:024bf7f99721 338 */
bogdanm 85:024bf7f99721 339
Kojto 108:34e6b704fe68 340 /** @defgroup RCC_HSI_Config HSI Config
bogdanm 85:024bf7f99721 341 * @{
bogdanm 85:024bf7f99721 342 */
<> 134:ad3be0349dc5 343 #define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */
Kojto 122:f9eeca106725 344 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
bogdanm 85:024bf7f99721 345
<> 134:ad3be0349dc5 346 #define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */
bogdanm 85:024bf7f99721 347
bogdanm 85:024bf7f99721 348 /**
bogdanm 85:024bf7f99721 349 * @}
bogdanm 85:024bf7f99721 350 */
Kojto 122:f9eeca106725 351
bogdanm 92:4fc01daae5a5 352 /** @defgroup RCC_HSI14_Config RCC HSI14 Config
bogdanm 85:024bf7f99721 353 * @{
bogdanm 85:024bf7f99721 354 */
<> 134:ad3be0349dc5 355 #define RCC_HSI14_OFF ((uint32_t)0x00000000U)
bogdanm 85:024bf7f99721 356 #define RCC_HSI14_ON RCC_CR2_HSI14ON
bogdanm 85:024bf7f99721 357 #define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS)
bogdanm 85:024bf7f99721 358
<> 134:ad3be0349dc5 359 #define RCC_HSI14CALIBRATION_DEFAULT (0x10U) /* Default HSI14 calibration trimming value */
Kojto 108:34e6b704fe68 360 /**
Kojto 108:34e6b704fe68 361 * @}
Kojto 108:34e6b704fe68 362 */
Kojto 108:34e6b704fe68 363
Kojto 108:34e6b704fe68 364 /** @defgroup RCC_LSI_Config LSI Config
Kojto 108:34e6b704fe68 365 * @{
Kojto 108:34e6b704fe68 366 */
<> 134:ad3be0349dc5 367 #define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */
Kojto 108:34e6b704fe68 368 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
Kojto 108:34e6b704fe68 369
Kojto 108:34e6b704fe68 370 /**
Kojto 108:34e6b704fe68 371 * @}
Kojto 108:34e6b704fe68 372 */
bogdanm 85:024bf7f99721 373
Kojto 122:f9eeca106725 374 #if defined(RCC_HSI48_SUPPORT)
Kojto 122:f9eeca106725 375 /** @defgroup RCC_HSI48_Config HSI48 Config
Kojto 122:f9eeca106725 376 * @{
Kojto 122:f9eeca106725 377 */
<> 134:ad3be0349dc5 378 #define RCC_HSI48_OFF ((uint8_t)0x00U)
<> 134:ad3be0349dc5 379 #define RCC_HSI48_ON ((uint8_t)0x01U)
Kojto 122:f9eeca106725 380
Kojto 122:f9eeca106725 381 /**
Kojto 122:f9eeca106725 382 * @}
Kojto 122:f9eeca106725 383 */
Kojto 122:f9eeca106725 384 #endif /* RCC_HSI48_SUPPORT */
Kojto 122:f9eeca106725 385
Kojto 108:34e6b704fe68 386 /** @defgroup RCC_PLL_Config PLL Config
Kojto 108:34e6b704fe68 387 * @{
Kojto 108:34e6b704fe68 388 */
<> 134:ad3be0349dc5 389 #define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */
<> 134:ad3be0349dc5 390 #define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */
<> 134:ad3be0349dc5 391 #define RCC_PLL_ON (0x00000002U) /*!< PLL activation */
Kojto 108:34e6b704fe68 392
Kojto 108:34e6b704fe68 393 /**
Kojto 108:34e6b704fe68 394 * @}
Kojto 108:34e6b704fe68 395 */
Kojto 108:34e6b704fe68 396
Kojto 108:34e6b704fe68 397 /** @defgroup RCC_System_Clock_Type System Clock Type
Kojto 108:34e6b704fe68 398 * @{
Kojto 108:34e6b704fe68 399 */
<> 134:ad3be0349dc5 400 #define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */
<> 134:ad3be0349dc5 401 #define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */
<> 134:ad3be0349dc5 402 #define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */
Kojto 108:34e6b704fe68 403
bogdanm 85:024bf7f99721 404 /**
bogdanm 85:024bf7f99721 405 * @}
bogdanm 85:024bf7f99721 406 */
bogdanm 85:024bf7f99721 407
Kojto 108:34e6b704fe68 408 /** @defgroup RCC_System_Clock_Source System Clock Source
bogdanm 85:024bf7f99721 409 * @{
bogdanm 85:024bf7f99721 410 */
Kojto 122:f9eeca106725 411 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
Kojto 122:f9eeca106725 412 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
Kojto 122:f9eeca106725 413 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
Kojto 108:34e6b704fe68 414
Kojto 108:34e6b704fe68 415 /**
Kojto 108:34e6b704fe68 416 * @}
Kojto 122:f9eeca106725 417 */
bogdanm 85:024bf7f99721 418
Kojto 108:34e6b704fe68 419 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Kojto 108:34e6b704fe68 420 * @{
Kojto 108:34e6b704fe68 421 */
Kojto 108:34e6b704fe68 422 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
Kojto 108:34e6b704fe68 423 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
Kojto 108:34e6b704fe68 424 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
Kojto 108:34e6b704fe68 425
bogdanm 85:024bf7f99721 426 /**
bogdanm 85:024bf7f99721 427 * @}
bogdanm 85:024bf7f99721 428 */
Kojto 122:f9eeca106725 429
Kojto 108:34e6b704fe68 430 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
Kojto 108:34e6b704fe68 431 * @{
Kojto 108:34e6b704fe68 432 */
Kojto 122:f9eeca106725 433 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
Kojto 122:f9eeca106725 434 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
Kojto 122:f9eeca106725 435 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
Kojto 122:f9eeca106725 436 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
Kojto 122:f9eeca106725 437 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
Kojto 122:f9eeca106725 438 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
Kojto 122:f9eeca106725 439 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
Kojto 122:f9eeca106725 440 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
Kojto 122:f9eeca106725 441 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
bogdanm 85:024bf7f99721 442
bogdanm 85:024bf7f99721 443 /**
bogdanm 85:024bf7f99721 444 * @}
bogdanm 85:024bf7f99721 445 */
Kojto 108:34e6b704fe68 446
Kojto 122:f9eeca106725 447 /** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
Kojto 122:f9eeca106725 448 * @{
Kojto 122:f9eeca106725 449 */
Kojto 122:f9eeca106725 450 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1 /*!< HCLK not divided */
Kojto 122:f9eeca106725 451 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2 /*!< HCLK divided by 2 */
Kojto 122:f9eeca106725 452 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4 /*!< HCLK divided by 4 */
Kojto 122:f9eeca106725 453 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8 /*!< HCLK divided by 8 */
Kojto 122:f9eeca106725 454 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16 /*!< HCLK divided by 16 */
Kojto 122:f9eeca106725 455
Kojto 122:f9eeca106725 456 /**
Kojto 122:f9eeca106725 457 * @}
Kojto 122:f9eeca106725 458 */
Kojto 122:f9eeca106725 459
Kojto 122:f9eeca106725 460 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
Kojto 122:f9eeca106725 461 * @{
Kojto 122:f9eeca106725 462 */
<> 134:ad3be0349dc5 463 #define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /*!< No clock */
Kojto 122:f9eeca106725 464 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
Kojto 122:f9eeca106725 465 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
Kojto 122:f9eeca106725 466 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 32 used as RTC clock */
Kojto 122:f9eeca106725 467 /**
Kojto 122:f9eeca106725 468 * @}
Kojto 122:f9eeca106725 469 */
Kojto 122:f9eeca106725 470
bogdanm 92:4fc01daae5a5 471 /** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
bogdanm 85:024bf7f99721 472 * @{
bogdanm 85:024bf7f99721 473 */
bogdanm 85:024bf7f99721 474 #define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
bogdanm 85:024bf7f99721 475 #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
bogdanm 85:024bf7f99721 476 #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
bogdanm 85:024bf7f99721 477 #define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
bogdanm 85:024bf7f99721 478 #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
bogdanm 85:024bf7f99721 479 #define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
bogdanm 85:024bf7f99721 480 #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
bogdanm 85:024bf7f99721 481 #define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
bogdanm 85:024bf7f99721 482 #define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
bogdanm 85:024bf7f99721 483 #define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
bogdanm 85:024bf7f99721 484 #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
bogdanm 85:024bf7f99721 485 #define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
bogdanm 85:024bf7f99721 486 #define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
bogdanm 85:024bf7f99721 487 #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
bogdanm 85:024bf7f99721 488 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
bogdanm 85:024bf7f99721 489
bogdanm 85:024bf7f99721 490 /**
bogdanm 85:024bf7f99721 491 * @}
bogdanm 85:024bf7f99721 492 */
bogdanm 85:024bf7f99721 493
Kojto 122:f9eeca106725 494 /** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
Kojto 122:f9eeca106725 495 * @{
Kojto 122:f9eeca106725 496 */
Kojto 122:f9eeca106725 497
Kojto 122:f9eeca106725 498 #define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
Kojto 122:f9eeca106725 499 #define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
Kojto 122:f9eeca106725 500 #define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
Kojto 122:f9eeca106725 501 #define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
Kojto 122:f9eeca106725 502 #define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
Kojto 122:f9eeca106725 503 #define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
Kojto 122:f9eeca106725 504 #define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
Kojto 122:f9eeca106725 505 #define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
Kojto 122:f9eeca106725 506 #define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
Kojto 122:f9eeca106725 507 #define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
Kojto 122:f9eeca106725 508 #define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
Kojto 122:f9eeca106725 509 #define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
Kojto 122:f9eeca106725 510 #define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
Kojto 122:f9eeca106725 511 #define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
Kojto 122:f9eeca106725 512 #define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
Kojto 122:f9eeca106725 513 #define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
Kojto 122:f9eeca106725 514
Kojto 122:f9eeca106725 515 /**
Kojto 122:f9eeca106725 516 * @}
Kojto 122:f9eeca106725 517 */
Kojto 122:f9eeca106725 518
Kojto 122:f9eeca106725 519
bogdanm 92:4fc01daae5a5 520 /** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source
bogdanm 85:024bf7f99721 521 * @{
bogdanm 85:024bf7f99721 522 */
bogdanm 85:024bf7f99721 523 #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
bogdanm 85:024bf7f99721 524 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
bogdanm 85:024bf7f99721 525 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
bogdanm 85:024bf7f99721 526 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
bogdanm 85:024bf7f99721 527
bogdanm 85:024bf7f99721 528 /**
bogdanm 85:024bf7f99721 529 * @}
bogdanm 85:024bf7f99721 530 */
bogdanm 85:024bf7f99721 531
bogdanm 92:4fc01daae5a5 532 /** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
bogdanm 85:024bf7f99721 533 * @{
bogdanm 85:024bf7f99721 534 */
bogdanm 85:024bf7f99721 535 #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
bogdanm 85:024bf7f99721 536 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
bogdanm 85:024bf7f99721 537
bogdanm 85:024bf7f99721 538 /**
bogdanm 85:024bf7f99721 539 * @}
bogdanm 85:024bf7f99721 540 */
Kojto 108:34e6b704fe68 541 /** @defgroup RCC_MCO_Index MCO Index
bogdanm 85:024bf7f99721 542 * @{
bogdanm 85:024bf7f99721 543 */
<> 134:ad3be0349dc5 544 #define RCC_MCO1 (0x00000000U)
Kojto 108:34e6b704fe68 545 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
bogdanm 85:024bf7f99721 546
bogdanm 85:024bf7f99721 547 /**
bogdanm 85:024bf7f99721 548 * @}
bogdanm 85:024bf7f99721 549 */
bogdanm 85:024bf7f99721 550
bogdanm 92:4fc01daae5a5 551 /** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source
bogdanm 85:024bf7f99721 552 * @{
bogdanm 85:024bf7f99721 553 */
Kojto 122:f9eeca106725 554 #define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
Kojto 122:f9eeca106725 555 #define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
Kojto 122:f9eeca106725 556 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
Kojto 122:f9eeca106725 557 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
Kojto 122:f9eeca106725 558 #define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
Kojto 122:f9eeca106725 559 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
Kojto 122:f9eeca106725 560 #define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
Kojto 122:f9eeca106725 561 #define RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCO_HSI14
Kojto 108:34e6b704fe68 562
bogdanm 85:024bf7f99721 563 /**
bogdanm 85:024bf7f99721 564 * @}
bogdanm 85:024bf7f99721 565 */
Kojto 108:34e6b704fe68 566
Kojto 108:34e6b704fe68 567 /** @defgroup RCC_Interrupt Interrupts
bogdanm 85:024bf7f99721 568 * @{
bogdanm 85:024bf7f99721 569 */
Kojto 122:f9eeca106725 570 #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
Kojto 122:f9eeca106725 571 #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
Kojto 122:f9eeca106725 572 #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
Kojto 122:f9eeca106725 573 #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
Kojto 122:f9eeca106725 574 #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
Kojto 122:f9eeca106725 575 #define RCC_IT_HSI14RDY ((uint8_t)RCC_CIR_HSI14RDYF) /*!< HSI14 Ready Interrupt flag */
Kojto 122:f9eeca106725 576 #if defined(RCC_CIR_HSI48RDYF)
Kojto 122:f9eeca106725 577 #define RCC_IT_HSI48RDY ((uint8_t)RCC_CIR_HSI48RDYF) /*!< HSI48 Ready Interrupt flag */
Kojto 122:f9eeca106725 578 #endif
Kojto 122:f9eeca106725 579 #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
bogdanm 85:024bf7f99721 580 /**
bogdanm 85:024bf7f99721 581 * @}
Kojto 122:f9eeca106725 582 */
bogdanm 85:024bf7f99721 583
Kojto 108:34e6b704fe68 584 /** @defgroup RCC_Flag Flags
Kojto 108:34e6b704fe68 585 * Elements values convention: XXXYYYYYb
bogdanm 85:024bf7f99721 586 * - YYYYY : Flag position in the register
Kojto 108:34e6b704fe68 587 * - XXX : Register index
Kojto 108:34e6b704fe68 588 * - 001: CR register
Kojto 108:34e6b704fe68 589 * - 010: CR2 register
Kojto 108:34e6b704fe68 590 * - 011: BDCR register
Kojto 108:34e6b704fe68 591 * - 0100: CSR register
bogdanm 85:024bf7f99721 592 * @{
bogdanm 85:024bf7f99721 593 */
bogdanm 85:024bf7f99721 594 /* Flags in the CR register */
<> 134:ad3be0349dc5 595 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_BitNumber))
<> 134:ad3be0349dc5 596 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_BitNumber))
<> 134:ad3be0349dc5 597 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_BitNumber))
bogdanm 85:024bf7f99721 598 /* Flags in the CR2 register */
<> 134:ad3be0349dc5 599 #define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5U) | RCC_CR2_HSI14RDY_BitNumber))
bogdanm 85:024bf7f99721 600
bogdanm 85:024bf7f99721 601 /* Flags in the CSR register */
<> 134:ad3be0349dc5 602 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_BitNumber))
Kojto 122:f9eeca106725 603 #if defined(RCC_CSR_V18PWRRSTF)
<> 134:ad3be0349dc5 604 #define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_V18PWRRSTF_BitNumber))
Kojto 122:f9eeca106725 605 #endif
<> 134:ad3be0349dc5 606 #define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_BitNumber))
<> 134:ad3be0349dc5 607 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_BitNumber)) /*!< PIN reset flag */
<> 134:ad3be0349dc5 608 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_BitNumber)) /*!< POR/PDR reset flag */
<> 134:ad3be0349dc5 609 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_BitNumber)) /*!< Software Reset flag */
<> 134:ad3be0349dc5 610 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_BitNumber)) /*!< Independent Watchdog reset flag */
<> 134:ad3be0349dc5 611 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_BitNumber)) /*!< Window watchdog reset flag */
<> 134:ad3be0349dc5 612 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_BitNumber)) /*!< Low-Power reset flag */
bogdanm 85:024bf7f99721 613
Kojto 108:34e6b704fe68 614 /* Flags in the BDCR register */
<> 134:ad3be0349dc5 615 #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_BitNumber)) /*!< External Low Speed oscillator Ready */
bogdanm 85:024bf7f99721 616
bogdanm 92:4fc01daae5a5 617 /**
bogdanm 92:4fc01daae5a5 618 * @}
Kojto 122:f9eeca106725 619 */
bogdanm 85:024bf7f99721 620
bogdanm 85:024bf7f99721 621 /**
bogdanm 85:024bf7f99721 622 * @}
Kojto 122:f9eeca106725 623 */
Kojto 122:f9eeca106725 624
bogdanm 85:024bf7f99721 625 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 626
bogdanm 92:4fc01daae5a5 627 /** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto 108:34e6b704fe68 628 * @{
Kojto 108:34e6b704fe68 629 */
bogdanm 85:024bf7f99721 630
bogdanm 92:4fc01daae5a5 631 /** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
bogdanm 92:4fc01daae5a5 632 * @brief Enable or disable the AHB peripheral clock.
bogdanm 85:024bf7f99721 633 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 85:024bf7f99721 634 * is disabled and the application software has to enable this clock before
bogdanm 85:024bf7f99721 635 * using it.
bogdanm 92:4fc01daae5a5 636 * @{
bogdanm 85:024bf7f99721 637 */
Kojto 108:34e6b704fe68 638 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto 108:34e6b704fe68 639 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 640 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
Kojto 122:f9eeca106725 641 /* Delay after an RCC peripheral clock enabling */\
Kojto 108:34e6b704fe68 642 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
Kojto 108:34e6b704fe68 643 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 644 } while(0)
Kojto 108:34e6b704fe68 645 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto 108:34e6b704fe68 646 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 647 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
Kojto 122:f9eeca106725 648 /* Delay after an RCC peripheral clock enabling */\
Kojto 108:34e6b704fe68 649 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
Kojto 108:34e6b704fe68 650 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 651 } while(0)
Kojto 108:34e6b704fe68 652 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto 108:34e6b704fe68 653 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 654 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
Kojto 122:f9eeca106725 655 /* Delay after an RCC peripheral clock enabling */\
Kojto 108:34e6b704fe68 656 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
Kojto 108:34e6b704fe68 657 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 658 } while(0)
Kojto 108:34e6b704fe68 659 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto 108:34e6b704fe68 660 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 661 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
Kojto 122:f9eeca106725 662 /* Delay after an RCC peripheral clock enabling */\
Kojto 108:34e6b704fe68 663 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
Kojto 108:34e6b704fe68 664 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 665 } while(0)
Kojto 108:34e6b704fe68 666 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto 108:34e6b704fe68 667 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 668 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
Kojto 122:f9eeca106725 669 /* Delay after an RCC peripheral clock enabling */\
Kojto 108:34e6b704fe68 670 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
Kojto 108:34e6b704fe68 671 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 672 } while(0)
Kojto 108:34e6b704fe68 673 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto 108:34e6b704fe68 674 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 675 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
Kojto 122:f9eeca106725 676 /* Delay after an RCC peripheral clock enabling */\
Kojto 108:34e6b704fe68 677 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
Kojto 108:34e6b704fe68 678 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 679 } while(0)
Kojto 108:34e6b704fe68 680 #define __HAL_RCC_SRAM_CLK_ENABLE() do { \
Kojto 108:34e6b704fe68 681 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 682 SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
Kojto 122:f9eeca106725 683 /* Delay after an RCC peripheral clock enabling */\
Kojto 108:34e6b704fe68 684 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
Kojto 108:34e6b704fe68 685 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 686 } while(0)
Kojto 108:34e6b704fe68 687 #define __HAL_RCC_FLITF_CLK_ENABLE() do { \
Kojto 108:34e6b704fe68 688 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 689 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
Kojto 122:f9eeca106725 690 /* Delay after an RCC peripheral clock enabling */\
Kojto 108:34e6b704fe68 691 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
Kojto 108:34e6b704fe68 692 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 693 } while(0)
bogdanm 85:024bf7f99721 694
Kojto 108:34e6b704fe68 695 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
Kojto 108:34e6b704fe68 696 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
Kojto 108:34e6b704fe68 697 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
Kojto 108:34e6b704fe68 698 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
Kojto 108:34e6b704fe68 699 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
Kojto 108:34e6b704fe68 700 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
Kojto 108:34e6b704fe68 701 #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
Kojto 108:34e6b704fe68 702 #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
bogdanm 92:4fc01daae5a5 703 /**
bogdanm 92:4fc01daae5a5 704 * @}
bogdanm 92:4fc01daae5a5 705 */
bogdanm 85:024bf7f99721 706
Kojto 108:34e6b704fe68 707 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
Kojto 108:34e6b704fe68 708 * @brief Get the enable or disable status of the AHB peripheral clock.
Kojto 108:34e6b704fe68 709 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 108:34e6b704fe68 710 * is disabled and the application software has to enable this clock before
Kojto 108:34e6b704fe68 711 * using it.
Kojto 108:34e6b704fe68 712 * @{
Kojto 108:34e6b704fe68 713 */
Kojto 108:34e6b704fe68 714 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
Kojto 108:34e6b704fe68 715 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
Kojto 108:34e6b704fe68 716 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
Kojto 108:34e6b704fe68 717 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
Kojto 108:34e6b704fe68 718 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
Kojto 108:34e6b704fe68 719 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
Kojto 108:34e6b704fe68 720 #define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
Kojto 108:34e6b704fe68 721 #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
Kojto 108:34e6b704fe68 722 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
Kojto 108:34e6b704fe68 723 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
Kojto 108:34e6b704fe68 724 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
Kojto 108:34e6b704fe68 725 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
Kojto 108:34e6b704fe68 726 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
Kojto 108:34e6b704fe68 727 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
Kojto 108:34e6b704fe68 728 #define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
Kojto 108:34e6b704fe68 729 #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
Kojto 108:34e6b704fe68 730 /**
Kojto 108:34e6b704fe68 731 * @}
Kojto 108:34e6b704fe68 732 */
Kojto 108:34e6b704fe68 733
bogdanm 92:4fc01daae5a5 734 /** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
bogdanm 92:4fc01daae5a5 735 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm 85:024bf7f99721 736 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 85:024bf7f99721 737 * is disabled and the application software has to enable this clock before
bogdanm 85:024bf7f99721 738 * using it.
bogdanm 92:4fc01daae5a5 739 * @{
bogdanm 85:024bf7f99721 740 */
Kojto 108:34e6b704fe68 741 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto 108:34e6b704fe68 742 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 743 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto 122:f9eeca106725 744 /* Delay after an RCC peripheral clock enabling */\
Kojto 108:34e6b704fe68 745 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto 108:34e6b704fe68 746 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 747 } while(0)
Kojto 108:34e6b704fe68 748 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto 108:34e6b704fe68 749 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 750 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 122:f9eeca106725 751 /* Delay after an RCC peripheral clock enabling */\
Kojto 108:34e6b704fe68 752 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 108:34e6b704fe68 753 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 754 } while(0)
Kojto 108:34e6b704fe68 755 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
Kojto 108:34e6b704fe68 756 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 757 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto 122:f9eeca106725 758 /* Delay after an RCC peripheral clock enabling */\
Kojto 108:34e6b704fe68 759 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto 108:34e6b704fe68 760 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 761 } while(0)
Kojto 108:34e6b704fe68 762 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
Kojto 108:34e6b704fe68 763 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 764 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 122:f9eeca106725 765 /* Delay after an RCC peripheral clock enabling */\
Kojto 108:34e6b704fe68 766 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 108:34e6b704fe68 767 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 768 } while(0)
Kojto 108:34e6b704fe68 769 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
Kojto 108:34e6b704fe68 770 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 771 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto 122:f9eeca106725 772 /* Delay after an RCC peripheral clock enabling */\
Kojto 108:34e6b704fe68 773 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto 108:34e6b704fe68 774 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 775 } while(0)
bogdanm 85:024bf7f99721 776
Kojto 108:34e6b704fe68 777 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto 108:34e6b704fe68 778 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto 108:34e6b704fe68 779 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto 108:34e6b704fe68 780 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto 108:34e6b704fe68 781 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
bogdanm 92:4fc01daae5a5 782 /**
bogdanm 92:4fc01daae5a5 783 * @}
bogdanm 92:4fc01daae5a5 784 */
Kojto 108:34e6b704fe68 785
Kojto 108:34e6b704fe68 786 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto 108:34e6b704fe68 787 * @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto 108:34e6b704fe68 788 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 108:34e6b704fe68 789 * is disabled and the application software has to enable this clock before
Kojto 108:34e6b704fe68 790 * using it.
Kojto 108:34e6b704fe68 791 * @{
Kojto 108:34e6b704fe68 792 */
Kojto 108:34e6b704fe68 793 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto 108:34e6b704fe68 794 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
Kojto 108:34e6b704fe68 795 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
Kojto 108:34e6b704fe68 796 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
Kojto 108:34e6b704fe68 797 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
Kojto 108:34e6b704fe68 798 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto 108:34e6b704fe68 799 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
Kojto 108:34e6b704fe68 800 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
Kojto 108:34e6b704fe68 801 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
Kojto 108:34e6b704fe68 802 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
Kojto 108:34e6b704fe68 803 /**
Kojto 108:34e6b704fe68 804 * @}
Kojto 108:34e6b704fe68 805 */
Kojto 108:34e6b704fe68 806
bogdanm 92:4fc01daae5a5 807
bogdanm 92:4fc01daae5a5 808 /** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
bogdanm 92:4fc01daae5a5 809 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm 85:024bf7f99721 810 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 85:024bf7f99721 811 * is disabled and the application software has to enable this clock before
bogdanm 85:024bf7f99721 812 * using it.
bogdanm 92:4fc01daae5a5 813 * @{
bogdanm 85:024bf7f99721 814 */
Kojto 108:34e6b704fe68 815 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
Kojto 108:34e6b704fe68 816 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 817 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto 122:f9eeca106725 818 /* Delay after an RCC peripheral clock enabling */\
Kojto 108:34e6b704fe68 819 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto 108:34e6b704fe68 820 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 821 } while(0)
Kojto 108:34e6b704fe68 822 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
Kojto 108:34e6b704fe68 823 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 824 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 122:f9eeca106725 825 /* Delay after an RCC peripheral clock enabling */\
Kojto 108:34e6b704fe68 826 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 108:34e6b704fe68 827 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 828 } while(0)
Kojto 108:34e6b704fe68 829 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
Kojto 108:34e6b704fe68 830 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 831 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 122:f9eeca106725 832 /* Delay after an RCC peripheral clock enabling */\
Kojto 108:34e6b704fe68 833 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 108:34e6b704fe68 834 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 835 } while(0)
Kojto 108:34e6b704fe68 836 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto 108:34e6b704fe68 837 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 838 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 122:f9eeca106725 839 /* Delay after an RCC peripheral clock enabling */\
Kojto 108:34e6b704fe68 840 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 108:34e6b704fe68 841 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 842 } while(0)
Kojto 108:34e6b704fe68 843 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \
Kojto 108:34e6b704fe68 844 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 845 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
Kojto 122:f9eeca106725 846 /* Delay after an RCC peripheral clock enabling */\
Kojto 108:34e6b704fe68 847 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
Kojto 108:34e6b704fe68 848 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 849 } while(0)
Kojto 108:34e6b704fe68 850 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \
Kojto 108:34e6b704fe68 851 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 852 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
Kojto 122:f9eeca106725 853 /* Delay after an RCC peripheral clock enabling */\
Kojto 108:34e6b704fe68 854 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
Kojto 108:34e6b704fe68 855 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 856 } while(0)
Kojto 108:34e6b704fe68 857 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
Kojto 108:34e6b704fe68 858 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 859 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 122:f9eeca106725 860 /* Delay after an RCC peripheral clock enabling */\
Kojto 108:34e6b704fe68 861 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 108:34e6b704fe68 862 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 863 } while(0)
Kojto 108:34e6b704fe68 864 #define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \
Kojto 108:34e6b704fe68 865 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 866 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
Kojto 122:f9eeca106725 867 /* Delay after an RCC peripheral clock enabling */\
Kojto 108:34e6b704fe68 868 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
Kojto 108:34e6b704fe68 869 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 870 } while(0)
bogdanm 85:024bf7f99721 871
Kojto 108:34e6b704fe68 872 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto 108:34e6b704fe68 873 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto 108:34e6b704fe68 874 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto 108:34e6b704fe68 875 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto 108:34e6b704fe68 876 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
Kojto 108:34e6b704fe68 877 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
Kojto 108:34e6b704fe68 878 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto 108:34e6b704fe68 879 #define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN))
bogdanm 92:4fc01daae5a5 880 /**
bogdanm 92:4fc01daae5a5 881 * @}
bogdanm 92:4fc01daae5a5 882 */
bogdanm 85:024bf7f99721 883
Kojto 108:34e6b704fe68 884 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto 108:34e6b704fe68 885 * @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto 108:34e6b704fe68 886 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 108:34e6b704fe68 887 * is disabled and the application software has to enable this clock before
Kojto 108:34e6b704fe68 888 * using it.
Kojto 108:34e6b704fe68 889 * @{
Kojto 108:34e6b704fe68 890 */
Kojto 108:34e6b704fe68 891 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
Kojto 108:34e6b704fe68 892 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
Kojto 108:34e6b704fe68 893 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
Kojto 108:34e6b704fe68 894 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
Kojto 108:34e6b704fe68 895 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
Kojto 108:34e6b704fe68 896 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
Kojto 108:34e6b704fe68 897 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
Kojto 108:34e6b704fe68 898 #define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) != RESET)
Kojto 108:34e6b704fe68 899 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
Kojto 108:34e6b704fe68 900 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
Kojto 108:34e6b704fe68 901 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
Kojto 108:34e6b704fe68 902 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
Kojto 108:34e6b704fe68 903 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
Kojto 108:34e6b704fe68 904 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
Kojto 108:34e6b704fe68 905 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
Kojto 108:34e6b704fe68 906 #define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) == RESET)
Kojto 108:34e6b704fe68 907 /**
Kojto 108:34e6b704fe68 908 * @}
Kojto 108:34e6b704fe68 909 */
Kojto 108:34e6b704fe68 910
bogdanm 92:4fc01daae5a5 911 /** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
bogdanm 92:4fc01daae5a5 912 * @brief Force or release AHB peripheral reset.
bogdanm 92:4fc01daae5a5 913 * @{
Kojto 122:f9eeca106725 914 */
Kojto 122:f9eeca106725 915 #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
Kojto 108:34e6b704fe68 916 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
Kojto 108:34e6b704fe68 917 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
Kojto 108:34e6b704fe68 918 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
Kojto 108:34e6b704fe68 919 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
bogdanm 85:024bf7f99721 920
<> 134:ad3be0349dc5 921 #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)
Kojto 108:34e6b704fe68 922 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
Kojto 108:34e6b704fe68 923 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
Kojto 108:34e6b704fe68 924 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
Kojto 108:34e6b704fe68 925 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
bogdanm 92:4fc01daae5a5 926 /**
bogdanm 92:4fc01daae5a5 927 * @}
bogdanm 92:4fc01daae5a5 928 */
bogdanm 85:024bf7f99721 929
bogdanm 92:4fc01daae5a5 930 /** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
bogdanm 92:4fc01daae5a5 931 * @brief Force or release APB1 peripheral reset.
bogdanm 92:4fc01daae5a5 932 * @{
Kojto 122:f9eeca106725 933 */
Kojto 122:f9eeca106725 934 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
Kojto 108:34e6b704fe68 935 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
Kojto 108:34e6b704fe68 936 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
Kojto 108:34e6b704fe68 937 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
Kojto 108:34e6b704fe68 938 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
Kojto 108:34e6b704fe68 939 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
bogdanm 85:024bf7f99721 940
<> 134:ad3be0349dc5 941 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)
Kojto 108:34e6b704fe68 942 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto 108:34e6b704fe68 943 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto 108:34e6b704fe68 944 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto 108:34e6b704fe68 945 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto 108:34e6b704fe68 946 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
bogdanm 92:4fc01daae5a5 947 /**
bogdanm 92:4fc01daae5a5 948 * @}
bogdanm 92:4fc01daae5a5 949 */
bogdanm 85:024bf7f99721 950
bogdanm 92:4fc01daae5a5 951 /** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
bogdanm 92:4fc01daae5a5 952 * @brief Force or release APB2 peripheral reset.
bogdanm 92:4fc01daae5a5 953 * @{
Kojto 122:f9eeca106725 954 */
Kojto 122:f9eeca106725 955 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
Kojto 108:34e6b704fe68 956 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
Kojto 108:34e6b704fe68 957 #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
Kojto 108:34e6b704fe68 958 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
Kojto 108:34e6b704fe68 959 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
Kojto 108:34e6b704fe68 960 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
Kojto 108:34e6b704fe68 961 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
Kojto 108:34e6b704fe68 962 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
Kojto 108:34e6b704fe68 963 #define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST))
bogdanm 85:024bf7f99721 964
<> 134:ad3be0349dc5 965 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)
Kojto 108:34e6b704fe68 966 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto 108:34e6b704fe68 967 #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
Kojto 108:34e6b704fe68 968 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto 108:34e6b704fe68 969 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto 108:34e6b704fe68 970 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto 108:34e6b704fe68 971 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
Kojto 108:34e6b704fe68 972 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
Kojto 108:34e6b704fe68 973 #define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST))
Kojto 108:34e6b704fe68 974 /**
Kojto 108:34e6b704fe68 975 * @}
Kojto 108:34e6b704fe68 976 */
Kojto 108:34e6b704fe68 977 /** @defgroup RCC_HSI_Configuration HSI Configuration
Kojto 108:34e6b704fe68 978 * @{
Kojto 122:f9eeca106725 979 */
Kojto 108:34e6b704fe68 980
Kojto 108:34e6b704fe68 981 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto 108:34e6b704fe68 982 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto 108:34e6b704fe68 983 * @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto 108:34e6b704fe68 984 * you have to select another source of the system clock then stop the HSI.
Kojto 108:34e6b704fe68 985 * @note After enabling the HSI, the application software should wait on HSIRDY
Kojto 108:34e6b704fe68 986 * flag to be set indicating that HSI clock is stable and can be used as
Kojto 108:34e6b704fe68 987 * system clock source.
Kojto 108:34e6b704fe68 988 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto 108:34e6b704fe68 989 * clock cycles.
Kojto 108:34e6b704fe68 990 */
Kojto 108:34e6b704fe68 991 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
Kojto 108:34e6b704fe68 992 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
Kojto 108:34e6b704fe68 993
Kojto 122:f9eeca106725 994 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto 108:34e6b704fe68 995 * @note The calibration is used to compensate for the variations in voltage
Kojto 108:34e6b704fe68 996 * and temperature that influence the frequency of the internal HSI RC.
Kojto 122:f9eeca106725 997 * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
Kojto 108:34e6b704fe68 998 * (default is RCC_HSICALIBRATION_DEFAULT).
Kojto 108:34e6b704fe68 999 * This parameter must be a number between 0 and 0x1F.
Kojto 122:f9eeca106725 1000 */
Kojto 108:34e6b704fe68 1001 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
Kojto 108:34e6b704fe68 1002 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_BitNumber)
Kojto 108:34e6b704fe68 1003
bogdanm 92:4fc01daae5a5 1004 /**
bogdanm 92:4fc01daae5a5 1005 * @}
bogdanm 92:4fc01daae5a5 1006 */
bogdanm 85:024bf7f99721 1007
Kojto 108:34e6b704fe68 1008 /** @defgroup RCC_LSI_Configuration LSI Configuration
bogdanm 92:4fc01daae5a5 1009 * @{
Kojto 122:f9eeca106725 1010 */
bogdanm 85:024bf7f99721 1011
Kojto 122:f9eeca106725 1012 /** @brief Macro to enable the Internal Low Speed oscillator (LSI).
Kojto 108:34e6b704fe68 1013 * @note After enabling the LSI, the application software should wait on
Kojto 108:34e6b704fe68 1014 * LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto 108:34e6b704fe68 1015 * be used to clock the IWDG and/or the RTC.
Kojto 122:f9eeca106725 1016 */
Kojto 122:f9eeca106725 1017 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
Kojto 122:f9eeca106725 1018
Kojto 122:f9eeca106725 1019 /** @brief Macro to disable the Internal Low Speed oscillator (LSI).
Kojto 108:34e6b704fe68 1020 * @note LSI can not be disabled if the IWDG is running.
Kojto 108:34e6b704fe68 1021 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto 108:34e6b704fe68 1022 * clock cycles.
Kojto 108:34e6b704fe68 1023 */
Kojto 108:34e6b704fe68 1024 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
Kojto 122:f9eeca106725 1025
bogdanm 92:4fc01daae5a5 1026 /**
bogdanm 92:4fc01daae5a5 1027 * @}
bogdanm 92:4fc01daae5a5 1028 */
bogdanm 85:024bf7f99721 1029
Kojto 108:34e6b704fe68 1030 /** @defgroup RCC_HSE_Configuration HSE Configuration
bogdanm 92:4fc01daae5a5 1031 * @{
Kojto 122:f9eeca106725 1032 */
bogdanm 85:024bf7f99721 1033
bogdanm 85:024bf7f99721 1034 /**
bogdanm 85:024bf7f99721 1035 * @brief Macro to configure the External High Speed oscillator (HSE).
Kojto 108:34e6b704fe68 1036 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
Kojto 108:34e6b704fe68 1037 * supported by this macro. User should request a transition to HSE Off
Kojto 108:34e6b704fe68 1038 * first and then HSE On or HSE Bypass.
bogdanm 85:024bf7f99721 1039 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm 85:024bf7f99721 1040 * software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm 85:024bf7f99721 1041 * is stable and can be used to clock the PLL and/or system clock.
bogdanm 85:024bf7f99721 1042 * @note HSE state can not be changed if it is used directly or through the
bogdanm 85:024bf7f99721 1043 * PLL as system clock. In this case, you have to select another source
bogdanm 85:024bf7f99721 1044 * of the system clock then change the HSE state (ex. disable it).
bogdanm 85:024bf7f99721 1045 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Kojto 122:f9eeca106725 1046 * @note This function reset the CSSON bit, so if the clock security system(CSS)
bogdanm 85:024bf7f99721 1047 * was previously enabled you have to enable it again after calling this
bogdanm 85:024bf7f99721 1048 * function.
Kojto 122:f9eeca106725 1049 * @param __STATE__ specifies the new state of the HSE.
bogdanm 85:024bf7f99721 1050 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1051 * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm 85:024bf7f99721 1052 * 6 HSE oscillator clock cycles.
Kojto 122:f9eeca106725 1053 * @arg @ref RCC_HSE_ON turn ON the HSE oscillator
Kojto 122:f9eeca106725 1054 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
bogdanm 85:024bf7f99721 1055 */
Kojto 108:34e6b704fe68 1056 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
Kojto 108:34e6b704fe68 1057 do{ \
Kojto 108:34e6b704fe68 1058 if ((__STATE__) == RCC_HSE_ON) \
Kojto 108:34e6b704fe68 1059 { \
Kojto 108:34e6b704fe68 1060 SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 108:34e6b704fe68 1061 } \
Kojto 108:34e6b704fe68 1062 else if ((__STATE__) == RCC_HSE_OFF) \
Kojto 108:34e6b704fe68 1063 { \
Kojto 108:34e6b704fe68 1064 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 108:34e6b704fe68 1065 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto 108:34e6b704fe68 1066 } \
Kojto 108:34e6b704fe68 1067 else if ((__STATE__) == RCC_HSE_BYPASS) \
Kojto 108:34e6b704fe68 1068 { \
Kojto 108:34e6b704fe68 1069 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto 108:34e6b704fe68 1070 SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 108:34e6b704fe68 1071 } \
Kojto 108:34e6b704fe68 1072 else \
Kojto 108:34e6b704fe68 1073 { \
Kojto 108:34e6b704fe68 1074 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 108:34e6b704fe68 1075 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto 108:34e6b704fe68 1076 } \
Kojto 108:34e6b704fe68 1077 }while(0)
bogdanm 85:024bf7f99721 1078
bogdanm 85:024bf7f99721 1079 /**
bogdanm 85:024bf7f99721 1080 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
bogdanm 85:024bf7f99721 1081 * @note Predivision factor can not be changed if PLL is used as system clock
bogdanm 85:024bf7f99721 1082 * In this case, you have to select another source of the system clock, disable the PLL and
bogdanm 85:024bf7f99721 1083 * then change the HSE predivision factor.
Kojto 122:f9eeca106725 1084 * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
bogdanm 85:024bf7f99721 1085 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
bogdanm 85:024bf7f99721 1086 */
Kojto 108:34e6b704fe68 1087 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
Kojto 108:34e6b704fe68 1088 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))
Kojto 108:34e6b704fe68 1089
bogdanm 92:4fc01daae5a5 1090 /**
bogdanm 92:4fc01daae5a5 1091 * @}
bogdanm 92:4fc01daae5a5 1092 */
bogdanm 85:024bf7f99721 1093
Kojto 108:34e6b704fe68 1094 /** @defgroup RCC_LSE_Configuration LSE Configuration
bogdanm 92:4fc01daae5a5 1095 * @{
Kojto 122:f9eeca106725 1096 */
Kojto 108:34e6b704fe68 1097
bogdanm 85:024bf7f99721 1098 /**
bogdanm 85:024bf7f99721 1099 * @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto 108:34e6b704fe68 1100 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
bogdanm 85:024bf7f99721 1101 * @note As the LSE is in the Backup domain and write access is denied to
Kojto 108:34e6b704fe68 1102 * this domain after reset, you have to enable write access using
Kojto 122:f9eeca106725 1103 * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto 108:34e6b704fe68 1104 * (to be done once after reset).
bogdanm 85:024bf7f99721 1105 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
bogdanm 85:024bf7f99721 1106 * software should wait on LSERDY flag to be set indicating that LSE clock
bogdanm 85:024bf7f99721 1107 * is stable and can be used to clock the RTC.
Kojto 122:f9eeca106725 1108 * @param __STATE__ specifies the new state of the LSE.
bogdanm 85:024bf7f99721 1109 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1110 * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
bogdanm 85:024bf7f99721 1111 * 6 LSE oscillator clock cycles.
Kojto 122:f9eeca106725 1112 * @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
Kojto 122:f9eeca106725 1113 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
bogdanm 85:024bf7f99721 1114 */
Kojto 108:34e6b704fe68 1115 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
Kojto 108:34e6b704fe68 1116 do{ \
Kojto 108:34e6b704fe68 1117 if ((__STATE__) == RCC_LSE_ON) \
Kojto 108:34e6b704fe68 1118 { \
Kojto 108:34e6b704fe68 1119 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto 108:34e6b704fe68 1120 } \
Kojto 108:34e6b704fe68 1121 else if ((__STATE__) == RCC_LSE_OFF) \
Kojto 108:34e6b704fe68 1122 { \
Kojto 108:34e6b704fe68 1123 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto 108:34e6b704fe68 1124 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto 108:34e6b704fe68 1125 } \
Kojto 108:34e6b704fe68 1126 else if ((__STATE__) == RCC_LSE_BYPASS) \
Kojto 108:34e6b704fe68 1127 { \
Kojto 108:34e6b704fe68 1128 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto 108:34e6b704fe68 1129 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto 108:34e6b704fe68 1130 } \
Kojto 108:34e6b704fe68 1131 else \
Kojto 108:34e6b704fe68 1132 { \
Kojto 108:34e6b704fe68 1133 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto 108:34e6b704fe68 1134 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto 108:34e6b704fe68 1135 } \
Kojto 108:34e6b704fe68 1136 }while(0)
Kojto 108:34e6b704fe68 1137
bogdanm 92:4fc01daae5a5 1138 /**
bogdanm 92:4fc01daae5a5 1139 * @}
bogdanm 92:4fc01daae5a5 1140 */
bogdanm 85:024bf7f99721 1141
bogdanm 92:4fc01daae5a5 1142 /** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration
bogdanm 92:4fc01daae5a5 1143 * @{
Kojto 122:f9eeca106725 1144 */
bogdanm 92:4fc01daae5a5 1145
Kojto 122:f9eeca106725 1146 /** @brief Macro to enable the Internal 14Mhz High Speed oscillator (HSI14).
Kojto 122:f9eeca106725 1147 * @note After enabling the HSI14 with @ref __HAL_RCC_HSI14_ENABLE(), the application software
Kojto 122:f9eeca106725 1148 * should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be
Kojto 122:f9eeca106725 1149 * used as system clock source. This is not necessary if @ref HAL_RCC_OscConfig() is used.
Kojto 122:f9eeca106725 1150 * clock cycles.
Kojto 122:f9eeca106725 1151 */
Kojto 122:f9eeca106725 1152 #define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON)
Kojto 122:f9eeca106725 1153
Kojto 122:f9eeca106725 1154 /** @brief Macro to disable the Internal 14Mhz High Speed oscillator (HSI14).
bogdanm 85:024bf7f99721 1155 * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 85:024bf7f99721 1156 * @note HSI14 can not be stopped if it is used as system clock source. In this case,
bogdanm 85:024bf7f99721 1157 * you have to select another source of the system clock then stop the HSI14.
bogdanm 85:024bf7f99721 1158 * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
bogdanm 85:024bf7f99721 1159 * clock cycles.
bogdanm 85:024bf7f99721 1160 */
bogdanm 85:024bf7f99721 1161 #define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON)
bogdanm 85:024bf7f99721 1162
Kojto 122:f9eeca106725 1163 /** @brief Macro to enable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC.
bogdanm 85:024bf7f99721 1164 */
bogdanm 85:024bf7f99721 1165 #define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
Kojto 122:f9eeca106725 1166
Kojto 122:f9eeca106725 1167 /** @brief Macro to disable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC.
Kojto 122:f9eeca106725 1168 */
bogdanm 85:024bf7f99721 1169 #define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
bogdanm 92:4fc01daae5a5 1170
bogdanm 85:024bf7f99721 1171 /** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value.
bogdanm 85:024bf7f99721 1172 * @note The calibration is used to compensate for the variations in voltage
bogdanm 85:024bf7f99721 1173 * and temperature that influence the frequency of the internal HSI14 RC.
Kojto 122:f9eeca106725 1174 * @param __HSI14CALIBRATIONVALUE__ specifies the calibration trimming value
bogdanm 85:024bf7f99721 1175 * (default is RCC_HSI14CALIBRATION_DEFAULT).
bogdanm 85:024bf7f99721 1176 * This parameter must be a number between 0 and 0x1F.
bogdanm 85:024bf7f99721 1177 */
Kojto 122:f9eeca106725 1178 #define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CALIBRATIONVALUE__) \
Kojto 122:f9eeca106725 1179 MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CALIBRATIONVALUE__) << RCC_HSI14TRIM_BIT_NUMBER)
bogdanm 92:4fc01daae5a5 1180 /**
bogdanm 92:4fc01daae5a5 1181 * @}
bogdanm 92:4fc01daae5a5 1182 */
bogdanm 85:024bf7f99721 1183
bogdanm 92:4fc01daae5a5 1184 /** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
bogdanm 92:4fc01daae5a5 1185 * @{
Kojto 122:f9eeca106725 1186 */
bogdanm 92:4fc01daae5a5 1187
bogdanm 85:024bf7f99721 1188 /** @brief Macro to configure the USART1 clock (USART1CLK).
Kojto 122:f9eeca106725 1189 * @param __USART1CLKSOURCE__ specifies the USART1 clock source.
bogdanm 85:024bf7f99721 1190 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1191 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
Kojto 122:f9eeca106725 1192 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
Kojto 122:f9eeca106725 1193 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
Kojto 122:f9eeca106725 1194 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
bogdanm 85:024bf7f99721 1195 */
Kojto 122:f9eeca106725 1196 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \
Kojto 122:f9eeca106725 1197 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__))
bogdanm 85:024bf7f99721 1198
bogdanm 85:024bf7f99721 1199 /** @brief Macro to get the USART1 clock source.
bogdanm 85:024bf7f99721 1200 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1201 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
Kojto 122:f9eeca106725 1202 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
Kojto 122:f9eeca106725 1203 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
Kojto 122:f9eeca106725 1204 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
bogdanm 85:024bf7f99721 1205 */
bogdanm 85:024bf7f99721 1206 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
Kojto 122:f9eeca106725 1207
bogdanm 92:4fc01daae5a5 1208 /**
bogdanm 92:4fc01daae5a5 1209 * @}
bogdanm 92:4fc01daae5a5 1210 */
bogdanm 85:024bf7f99721 1211
bogdanm 92:4fc01daae5a5 1212 /** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
bogdanm 92:4fc01daae5a5 1213 * @{
Kojto 122:f9eeca106725 1214 */
Kojto 122:f9eeca106725 1215
bogdanm 85:024bf7f99721 1216 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
Kojto 122:f9eeca106725 1217 * @param __I2C1CLKSOURCE__ specifies the I2C1 clock source.
bogdanm 85:024bf7f99721 1218 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1219 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
Kojto 122:f9eeca106725 1220 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
bogdanm 85:024bf7f99721 1221 */
Kojto 122:f9eeca106725 1222 #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \
Kojto 122:f9eeca106725 1223 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__))
bogdanm 85:024bf7f99721 1224
bogdanm 85:024bf7f99721 1225 /** @brief Macro to get the I2C1 clock source.
bogdanm 85:024bf7f99721 1226 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1227 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
Kojto 122:f9eeca106725 1228 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
bogdanm 85:024bf7f99721 1229 */
bogdanm 85:024bf7f99721 1230 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
bogdanm 92:4fc01daae5a5 1231 /**
bogdanm 92:4fc01daae5a5 1232 * @}
bogdanm 92:4fc01daae5a5 1233 */
bogdanm 85:024bf7f99721 1234
Kojto 108:34e6b704fe68 1235 /** @defgroup RCC_PLL_Configuration PLL Configuration
Kojto 108:34e6b704fe68 1236 * @{
Kojto 122:f9eeca106725 1237 */
Kojto 108:34e6b704fe68 1238
Kojto 122:f9eeca106725 1239 /** @brief Macro to enable the main PLL.
Kojto 108:34e6b704fe68 1240 * @note After enabling the main PLL, the application software should wait on
Kojto 108:34e6b704fe68 1241 * PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto 108:34e6b704fe68 1242 * be used as system clock source.
Kojto 108:34e6b704fe68 1243 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto 108:34e6b704fe68 1244 */
Kojto 108:34e6b704fe68 1245 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
Kojto 108:34e6b704fe68 1246
Kojto 122:f9eeca106725 1247 /** @brief Macro to disable the main PLL.
Kojto 108:34e6b704fe68 1248 * @note The main PLL can not be disabled if it is used as system clock source
Kojto 108:34e6b704fe68 1249 */
Kojto 108:34e6b704fe68 1250 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
Kojto 108:34e6b704fe68 1251
Kojto 108:34e6b704fe68 1252 /** @brief Macro to configure the PLL clock source, multiplication and division factors.
Kojto 108:34e6b704fe68 1253 * @note This function must be used only when the main PLL is disabled.
Kojto 108:34e6b704fe68 1254 *
Kojto 122:f9eeca106725 1255 * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source.
Kojto 108:34e6b704fe68 1256 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1257 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 1258 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 1259 * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
Kojto 108:34e6b704fe68 1260 * This parameter can be one of the following values:
Kojto 108:34e6b704fe68 1261 * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
Kojto 122:f9eeca106725 1262 * @param __PREDIV__ specifies the predivider factor for PLL VCO input clock
Kojto 108:34e6b704fe68 1263 * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
Kojto 108:34e6b704fe68 1264 *
Kojto 108:34e6b704fe68 1265 */
Kojto 108:34e6b704fe68 1266 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PREDIV__, __PLLMUL__) \
Kojto 108:34e6b704fe68 1267 do { \
Kojto 108:34e6b704fe68 1268 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
Kojto 108:34e6b704fe68 1269 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSOURCE__))); \
Kojto 108:34e6b704fe68 1270 } while(0)
Kojto 108:34e6b704fe68 1271
Kojto 122:f9eeca106725 1272
Kojto 108:34e6b704fe68 1273 /** @brief Get oscillator clock selected as PLL input clock
Kojto 108:34e6b704fe68 1274 * @retval The clock source used for PLL entry. The returned value can be one
Kojto 108:34e6b704fe68 1275 * of the following:
Kojto 122:f9eeca106725 1276 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
Kojto 108:34e6b704fe68 1277 */
Kojto 122:f9eeca106725 1278 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
Kojto 108:34e6b704fe68 1279
Kojto 108:34e6b704fe68 1280 /**
Kojto 108:34e6b704fe68 1281 * @}
Kojto 108:34e6b704fe68 1282 */
Kojto 108:34e6b704fe68 1283
Kojto 108:34e6b704fe68 1284 /** @defgroup RCC_Get_Clock_source Get Clock source
Kojto 108:34e6b704fe68 1285 * @{
Kojto 122:f9eeca106725 1286 */
Kojto 108:34e6b704fe68 1287
Kojto 108:34e6b704fe68 1288 /**
Kojto 108:34e6b704fe68 1289 * @brief Macro to configure the system clock source.
Kojto 122:f9eeca106725 1290 * @param __SYSCLKSOURCE__ specifies the system clock source.
Kojto 108:34e6b704fe68 1291 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1292 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
Kojto 122:f9eeca106725 1293 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
Kojto 122:f9eeca106725 1294 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
Kojto 108:34e6b704fe68 1295 */
Kojto 122:f9eeca106725 1296 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
Kojto 122:f9eeca106725 1297 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
Kojto 108:34e6b704fe68 1298
Kojto 108:34e6b704fe68 1299 /** @brief Macro to get the clock source used as system clock.
Kojto 108:34e6b704fe68 1300 * @retval The clock source used as system clock. The returned value can be one
Kojto 108:34e6b704fe68 1301 * of the following:
Kojto 122:f9eeca106725 1302 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
Kojto 122:f9eeca106725 1303 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
Kojto 122:f9eeca106725 1304 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
Kojto 122:f9eeca106725 1305 */
Kojto 108:34e6b704fe68 1306 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
Kojto 122:f9eeca106725 1307
Kojto 108:34e6b704fe68 1308 /**
Kojto 108:34e6b704fe68 1309 * @}
Kojto 108:34e6b704fe68 1310 */
Kojto 108:34e6b704fe68 1311
Kojto 122:f9eeca106725 1312 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
bogdanm 92:4fc01daae5a5 1313 * @{
bogdanm 92:4fc01daae5a5 1314 */
bogdanm 85:024bf7f99721 1315
Kojto 122:f9eeca106725 1316 #if defined(RCC_CFGR_MCOPRE)
Kojto 122:f9eeca106725 1317 /** @brief Macro to configure the MCO clock.
Kojto 122:f9eeca106725 1318 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto 122:f9eeca106725 1319 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1320 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
Kojto 122:f9eeca106725 1321 * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
Kojto 122:f9eeca106725 1322 * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock
Kojto 122:f9eeca106725 1323 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
Kojto 122:f9eeca106725 1324 * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
Kojto 122:f9eeca106725 1325 * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
Kojto 122:f9eeca106725 1326 * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock
Kojto 122:f9eeca106725 1327 @if STM32F042x6
Kojto 122:f9eeca106725 1328 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
Kojto 122:f9eeca106725 1329 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
Kojto 122:f9eeca106725 1330 @elseif STM32F048xx
Kojto 122:f9eeca106725 1331 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
Kojto 122:f9eeca106725 1332 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
Kojto 122:f9eeca106725 1333 @elseif STM32F071xB
Kojto 122:f9eeca106725 1334 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
Kojto 122:f9eeca106725 1335 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
Kojto 122:f9eeca106725 1336 @elseif STM32F072xB
Kojto 122:f9eeca106725 1337 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
Kojto 122:f9eeca106725 1338 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
Kojto 122:f9eeca106725 1339 @elseif STM32F078xx
Kojto 122:f9eeca106725 1340 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
Kojto 122:f9eeca106725 1341 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
Kojto 122:f9eeca106725 1342 @elseif STM32F091xC
Kojto 122:f9eeca106725 1343 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
Kojto 122:f9eeca106725 1344 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
Kojto 122:f9eeca106725 1345 @elseif STM32F098xx
Kojto 122:f9eeca106725 1346 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
Kojto 122:f9eeca106725 1347 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
Kojto 122:f9eeca106725 1348 @elseif STM32F030x6
Kojto 122:f9eeca106725 1349 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
Kojto 122:f9eeca106725 1350 @elseif STM32F030xC
Kojto 122:f9eeca106725 1351 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
Kojto 122:f9eeca106725 1352 @elseif STM32F031x6
Kojto 122:f9eeca106725 1353 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
Kojto 122:f9eeca106725 1354 @elseif STM32F038xx
Kojto 122:f9eeca106725 1355 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
Kojto 122:f9eeca106725 1356 @elseif STM32F070x6
Kojto 122:f9eeca106725 1357 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
Kojto 122:f9eeca106725 1358 @elseif STM32F070xB
Kojto 122:f9eeca106725 1359 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
Kojto 122:f9eeca106725 1360 @endif
Kojto 122:f9eeca106725 1361 * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
Kojto 122:f9eeca106725 1362 * @param __MCODIV__ specifies the MCO clock prescaler.
Kojto 122:f9eeca106725 1363 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1364 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
Kojto 122:f9eeca106725 1365 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
Kojto 122:f9eeca106725 1366 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
Kojto 122:f9eeca106725 1367 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
Kojto 122:f9eeca106725 1368 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
Kojto 122:f9eeca106725 1369 * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32
Kojto 122:f9eeca106725 1370 * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64
Kojto 122:f9eeca106725 1371 * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128
Kojto 122:f9eeca106725 1372 */
Kojto 122:f9eeca106725 1373 #else
Kojto 122:f9eeca106725 1374 /** @brief Macro to configure the MCO clock.
Kojto 122:f9eeca106725 1375 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto 122:f9eeca106725 1376 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1377 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
Kojto 122:f9eeca106725 1378 * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
Kojto 122:f9eeca106725 1379 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
Kojto 122:f9eeca106725 1380 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
Kojto 122:f9eeca106725 1381 * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
Kojto 122:f9eeca106725 1382 * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
Kojto 122:f9eeca106725 1383 * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock
Kojto 122:f9eeca106725 1384 * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
Kojto 122:f9eeca106725 1385 * @param __MCODIV__ specifies the MCO clock prescaler.
Kojto 122:f9eeca106725 1386 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1387 * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
Kojto 122:f9eeca106725 1388 */
Kojto 122:f9eeca106725 1389 #endif
Kojto 122:f9eeca106725 1390 #if defined(RCC_CFGR_MCOPRE)
Kojto 122:f9eeca106725 1391 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto 122:f9eeca106725 1392 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Kojto 122:f9eeca106725 1393 #else
Kojto 122:f9eeca106725 1394
Kojto 122:f9eeca106725 1395 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto 122:f9eeca106725 1396 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
Kojto 122:f9eeca106725 1397
Kojto 122:f9eeca106725 1398 #endif
Kojto 122:f9eeca106725 1399
Kojto 122:f9eeca106725 1400 /**
Kojto 122:f9eeca106725 1401 * @}
Kojto 122:f9eeca106725 1402 */
Kojto 122:f9eeca106725 1403
Kojto 122:f9eeca106725 1404 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
Kojto 122:f9eeca106725 1405 * @{
Kojto 122:f9eeca106725 1406 */
Kojto 122:f9eeca106725 1407
Kojto 122:f9eeca106725 1408 /** @brief Macro to configure the RTC clock (RTCCLK).
bogdanm 85:024bf7f99721 1409 * @note As the RTC clock configuration bits are in the Backup domain and write
bogdanm 85:024bf7f99721 1410 * access is denied to this domain after reset, you have to enable write
bogdanm 85:024bf7f99721 1411 * access using the Power Backup Access macro before to configure
Kojto 108:34e6b704fe68 1412 * the RTC clock source (to be done once after reset).
<> 134:ad3be0349dc5 1413 * @note Once the RTC clock is configured it cannot be changed unless the
Kojto 122:f9eeca106725 1414 * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
bogdanm 85:024bf7f99721 1415 * a Power On Reset (POR).
bogdanm 85:024bf7f99721 1416 *
Kojto 122:f9eeca106725 1417 * @param __RTC_CLKSOURCE__ specifies the RTC clock source.
Kojto 108:34e6b704fe68 1418 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1419 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
Kojto 122:f9eeca106725 1420 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
Kojto 122:f9eeca106725 1421 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
Kojto 122:f9eeca106725 1422 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
Kojto 108:34e6b704fe68 1423 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
bogdanm 85:024bf7f99721 1424 * work in STOP and STANDBY modes, and can be used as wakeup source.
bogdanm 85:024bf7f99721 1425 * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
bogdanm 85:024bf7f99721 1426 * the RTC cannot be used in STOP and STANDBY modes.
bogdanm 85:024bf7f99721 1427 * @note The system must always be configured so as to get a PCLK frequency greater than or
bogdanm 85:024bf7f99721 1428 * equal to the RTCCLK frequency for a proper operation of the RTC.
bogdanm 85:024bf7f99721 1429 */
Kojto 108:34e6b704fe68 1430 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
Kojto 108:34e6b704fe68 1431
Kojto 122:f9eeca106725 1432 /** @brief Macro to get the RTC clock source.
bogdanm 85:024bf7f99721 1433 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 1434 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
Kojto 122:f9eeca106725 1435 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
Kojto 122:f9eeca106725 1436 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
Kojto 122:f9eeca106725 1437 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
bogdanm 85:024bf7f99721 1438 */
Kojto 108:34e6b704fe68 1439 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
Kojto 108:34e6b704fe68 1440
Kojto 122:f9eeca106725 1441 /** @brief Macro to enable the the RTC clock.
Kojto 108:34e6b704fe68 1442 * @note These macros must be used only after the RTC clock source was selected.
bogdanm 92:4fc01daae5a5 1443 */
Kojto 108:34e6b704fe68 1444 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
bogdanm 85:024bf7f99721 1445
Kojto 122:f9eeca106725 1446 /** @brief Macro to disable the the RTC clock.
Kojto 108:34e6b704fe68 1447 * @note These macros must be used only after the RTC clock source was selected.
bogdanm 85:024bf7f99721 1448 */
Kojto 108:34e6b704fe68 1449 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Kojto 108:34e6b704fe68 1450
Kojto 122:f9eeca106725 1451 /** @brief Macro to force the Backup domain reset.
Kojto 108:34e6b704fe68 1452 * @note This function resets the RTC peripheral (including the backup registers)
Kojto 108:34e6b704fe68 1453 * and the RTC clock source selection in RCC_BDCR register.
Kojto 108:34e6b704fe68 1454 */
Kojto 108:34e6b704fe68 1455 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Kojto 108:34e6b704fe68 1456
Kojto 108:34e6b704fe68 1457 /** @brief Macros to release the Backup domain reset.
Kojto 108:34e6b704fe68 1458 */
Kojto 108:34e6b704fe68 1459 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Kojto 108:34e6b704fe68 1460
bogdanm 92:4fc01daae5a5 1461 /**
bogdanm 92:4fc01daae5a5 1462 * @}
bogdanm 92:4fc01daae5a5 1463 */
bogdanm 85:024bf7f99721 1464
Kojto 108:34e6b704fe68 1465 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
bogdanm 85:024bf7f99721 1466 * @brief macros to manage the specified RCC Flags and interrupts.
bogdanm 85:024bf7f99721 1467 * @{
bogdanm 85:024bf7f99721 1468 */
bogdanm 85:024bf7f99721 1469
Kojto 108:34e6b704fe68 1470 /** @brief Enable RCC interrupt.
Kojto 122:f9eeca106725 1471 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
Kojto 108:34e6b704fe68 1472 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 1473 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
Kojto 122:f9eeca106725 1474 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
Kojto 122:f9eeca106725 1475 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
Kojto 122:f9eeca106725 1476 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
Kojto 122:f9eeca106725 1477 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
Kojto 122:f9eeca106725 1478 * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt
Kojto 122:f9eeca106725 1479 @if STM32F042x6
Kojto 122:f9eeca106725 1480 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1481 @elseif STM32F048xx
Kojto 122:f9eeca106725 1482 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1483 @elseif STM32F071xB
Kojto 122:f9eeca106725 1484 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1485 @elseif STM32F072xB
Kojto 122:f9eeca106725 1486 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1487 @elseif STM32F078xx
Kojto 122:f9eeca106725 1488 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1489 @elseif STM32F091xC
Kojto 122:f9eeca106725 1490 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1491 @elseif STM32F098xx
Kojto 122:f9eeca106725 1492 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1493 @endif
bogdanm 85:024bf7f99721 1494 */
Kojto 108:34e6b704fe68 1495 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
bogdanm 85:024bf7f99721 1496
Kojto 108:34e6b704fe68 1497 /** @brief Disable RCC interrupt.
Kojto 122:f9eeca106725 1498 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
Kojto 108:34e6b704fe68 1499 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 1500 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
Kojto 122:f9eeca106725 1501 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
Kojto 122:f9eeca106725 1502 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
Kojto 122:f9eeca106725 1503 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
Kojto 122:f9eeca106725 1504 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
Kojto 122:f9eeca106725 1505 * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt
Kojto 122:f9eeca106725 1506 @if STM32F042x6
Kojto 122:f9eeca106725 1507 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1508 @elseif STM32F048xx
Kojto 122:f9eeca106725 1509 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1510 @elseif STM32F071xB
Kojto 122:f9eeca106725 1511 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1512 @elseif STM32F072xB
Kojto 122:f9eeca106725 1513 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1514 @elseif STM32F078xx
Kojto 122:f9eeca106725 1515 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1516 @elseif STM32F091xC
Kojto 122:f9eeca106725 1517 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1518 @elseif STM32F098xx
Kojto 122:f9eeca106725 1519 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1520 @endif
Kojto 108:34e6b704fe68 1521 */
Kojto 122:f9eeca106725 1522 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
Kojto 108:34e6b704fe68 1523
Kojto 108:34e6b704fe68 1524 /** @brief Clear the RCC's interrupt pending bits.
Kojto 122:f9eeca106725 1525 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
Kojto 108:34e6b704fe68 1526 * This parameter can be any combination of the following values:
Kojto 122:f9eeca106725 1527 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
Kojto 122:f9eeca106725 1528 * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
Kojto 122:f9eeca106725 1529 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
Kojto 122:f9eeca106725 1530 * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
Kojto 122:f9eeca106725 1531 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
Kojto 122:f9eeca106725 1532 * @arg @ref RCC_IT_CSS Clock Security System interrupt
Kojto 122:f9eeca106725 1533 * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt
Kojto 122:f9eeca106725 1534 @if STM32F042x6
Kojto 122:f9eeca106725 1535 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1536 @elseif STM32F048xx
Kojto 122:f9eeca106725 1537 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1538 @elseif STM32F071xB
Kojto 122:f9eeca106725 1539 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1540 @elseif STM32F072xB
Kojto 122:f9eeca106725 1541 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1542 @elseif STM32F078xx
Kojto 122:f9eeca106725 1543 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1544 @elseif STM32F091xC
Kojto 122:f9eeca106725 1545 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1546 @elseif STM32F098xx
Kojto 122:f9eeca106725 1547 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1548 @endif
bogdanm 85:024bf7f99721 1549 */
Kojto 108:34e6b704fe68 1550 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
bogdanm 85:024bf7f99721 1551
Kojto 108:34e6b704fe68 1552 /** @brief Check the RCC's interrupt has occurred or not.
Kojto 122:f9eeca106725 1553 * @param __INTERRUPT__ specifies the RCC interrupt source to check.
Kojto 108:34e6b704fe68 1554 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1555 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
Kojto 122:f9eeca106725 1556 * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
Kojto 122:f9eeca106725 1557 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
Kojto 122:f9eeca106725 1558 * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
Kojto 122:f9eeca106725 1559 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
Kojto 122:f9eeca106725 1560 * @arg @ref RCC_IT_CSS Clock Security System interrupt
Kojto 122:f9eeca106725 1561 * @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt enable
Kojto 122:f9eeca106725 1562 @if STM32F042x6
Kojto 122:f9eeca106725 1563 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1564 @elseif STM32F048xx
Kojto 122:f9eeca106725 1565 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1566 @elseif STM32F071xB
Kojto 122:f9eeca106725 1567 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1568 @elseif STM32F072xB
Kojto 122:f9eeca106725 1569 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1570 @elseif STM32F078xx
Kojto 122:f9eeca106725 1571 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1572 @elseif STM32F091xC
Kojto 122:f9eeca106725 1573 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1574 @elseif STM32F098xx
Kojto 122:f9eeca106725 1575 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
Kojto 122:f9eeca106725 1576 @endif
Kojto 108:34e6b704fe68 1577 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm 85:024bf7f99721 1578 */
Kojto 108:34e6b704fe68 1579 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
bogdanm 85:024bf7f99721 1580
Kojto 108:34e6b704fe68 1581 /** @brief Set RMVF bit to clear the reset flags.
Kojto 122:f9eeca106725 1582 * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
Kojto 122:f9eeca106725 1583 * RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
bogdanm 85:024bf7f99721 1584 */
Kojto 108:34e6b704fe68 1585 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
bogdanm 85:024bf7f99721 1586
bogdanm 85:024bf7f99721 1587 /** @brief Check RCC flag is set or not.
Kojto 122:f9eeca106725 1588 * @param __FLAG__ specifies the flag to check.
Kojto 108:34e6b704fe68 1589 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1590 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
Kojto 122:f9eeca106725 1591 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
Kojto 122:f9eeca106725 1592 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
Kojto 122:f9eeca106725 1593 * @arg @ref RCC_FLAG_HSI14RDY HSI14 oscillator clock ready
Kojto 122:f9eeca106725 1594 @if STM32F038xx
Kojto 122:f9eeca106725 1595 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
Kojto 122:f9eeca106725 1596 @elseif STM32F042x6
Kojto 122:f9eeca106725 1597 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
Kojto 122:f9eeca106725 1598 @elseif STM32F048xx
Kojto 122:f9eeca106725 1599 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
Kojto 122:f9eeca106725 1600 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
Kojto 122:f9eeca106725 1601 @elseif STM32F058xx
Kojto 122:f9eeca106725 1602 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
Kojto 122:f9eeca106725 1603 @elseif STM32F071xB
Kojto 122:f9eeca106725 1604 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
Kojto 122:f9eeca106725 1605 @elseif STM32F072xB
Kojto 122:f9eeca106725 1606 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
Kojto 122:f9eeca106725 1607 @elseif STM32F078xx
Kojto 122:f9eeca106725 1608 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
Kojto 122:f9eeca106725 1609 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
Kojto 122:f9eeca106725 1610 @elseif STM32F091xC
Kojto 122:f9eeca106725 1611 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
Kojto 122:f9eeca106725 1612 @elseif STM32F098xx
Kojto 122:f9eeca106725 1613 * @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
Kojto 122:f9eeca106725 1614 * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
Kojto 122:f9eeca106725 1615 @endif
Kojto 122:f9eeca106725 1616 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
Kojto 122:f9eeca106725 1617 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
Kojto 122:f9eeca106725 1618 * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset
Kojto 122:f9eeca106725 1619 * @arg @ref RCC_FLAG_PINRST Pin reset.
Kojto 122:f9eeca106725 1620 * @arg @ref RCC_FLAG_PORRST POR/PDR reset.
Kojto 122:f9eeca106725 1621 * @arg @ref RCC_FLAG_SFTRST Software reset.
Kojto 122:f9eeca106725 1622 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
Kojto 122:f9eeca106725 1623 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
Kojto 122:f9eeca106725 1624 * @arg @ref RCC_FLAG_LPWRRST Low Power reset.
bogdanm 85:024bf7f99721 1625 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 85:024bf7f99721 1626 */
<> 134:ad3be0349dc5 1627 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \
<> 134:ad3be0349dc5 1628 (((__FLAG__) >> 5U) == CR2_REG_INDEX)? RCC->CR2 : \
<> 134:ad3be0349dc5 1629 (((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \
<> 134:ad3be0349dc5 1630 RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
bogdanm 85:024bf7f99721 1631
Kojto 108:34e6b704fe68 1632 /**
Kojto 108:34e6b704fe68 1633 * @}
Kojto 122:f9eeca106725 1634 */
bogdanm 85:024bf7f99721 1635
bogdanm 85:024bf7f99721 1636 /**
bogdanm 85:024bf7f99721 1637 * @}
Kojto 122:f9eeca106725 1638 */
bogdanm 92:4fc01daae5a5 1639
bogdanm 85:024bf7f99721 1640 /* Include RCC HAL Extension module */
bogdanm 85:024bf7f99721 1641 #include "stm32f0xx_hal_rcc_ex.h"
bogdanm 85:024bf7f99721 1642
bogdanm 85:024bf7f99721 1643 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 1644 /** @addtogroup RCC_Exported_Functions
bogdanm 92:4fc01daae5a5 1645 * @{
bogdanm 92:4fc01daae5a5 1646 */
bogdanm 92:4fc01daae5a5 1647
bogdanm 92:4fc01daae5a5 1648 /** @addtogroup RCC_Exported_Functions_Group1
bogdanm 92:4fc01daae5a5 1649 * @{
bogdanm 92:4fc01daae5a5 1650 */
bogdanm 92:4fc01daae5a5 1651
Kojto 108:34e6b704fe68 1652 /* Initialization and de-initialization functions ******************************/
Kojto 108:34e6b704fe68 1653 void HAL_RCC_DeInit(void);
Kojto 108:34e6b704fe68 1654 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 108:34e6b704fe68 1655 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
bogdanm 85:024bf7f99721 1656
bogdanm 92:4fc01daae5a5 1657 /**
bogdanm 92:4fc01daae5a5 1658 * @}
bogdanm 92:4fc01daae5a5 1659 */
bogdanm 92:4fc01daae5a5 1660
bogdanm 92:4fc01daae5a5 1661 /** @addtogroup RCC_Exported_Functions_Group2
bogdanm 92:4fc01daae5a5 1662 * @{
bogdanm 92:4fc01daae5a5 1663 */
Kojto 108:34e6b704fe68 1664
Kojto 108:34e6b704fe68 1665 /* Peripheral Control functions ************************************************/
Kojto 108:34e6b704fe68 1666 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto 108:34e6b704fe68 1667 void HAL_RCC_EnableCSS(void);
<> 134:ad3be0349dc5 1668 /* CSS NMI IRQ handler */
<> 134:ad3be0349dc5 1669 void HAL_RCC_NMI_IRQHandler(void);
<> 134:ad3be0349dc5 1670 /* User Callbacks in non blocking mode (IT mode) */
<> 134:ad3be0349dc5 1671 void HAL_RCC_CSSCallback(void);
Kojto 108:34e6b704fe68 1672 void HAL_RCC_DisableCSS(void);
Kojto 108:34e6b704fe68 1673 uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto 108:34e6b704fe68 1674 uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto 108:34e6b704fe68 1675 uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto 108:34e6b704fe68 1676 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 108:34e6b704fe68 1677 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
bogdanm 85:024bf7f99721 1678
bogdanm 85:024bf7f99721 1679 /**
bogdanm 85:024bf7f99721 1680 * @}
bogdanm 85:024bf7f99721 1681 */
bogdanm 85:024bf7f99721 1682
bogdanm 85:024bf7f99721 1683 /**
bogdanm 85:024bf7f99721 1684 * @}
Kojto 122:f9eeca106725 1685 */
Kojto 108:34e6b704fe68 1686
Kojto 108:34e6b704fe68 1687 /**
Kojto 108:34e6b704fe68 1688 * @}
Kojto 122:f9eeca106725 1689 */
bogdanm 85:024bf7f99721 1690
bogdanm 92:4fc01daae5a5 1691 /**
bogdanm 92:4fc01daae5a5 1692 * @}
bogdanm 92:4fc01daae5a5 1693 */
Kojto 108:34e6b704fe68 1694
bogdanm 85:024bf7f99721 1695 #ifdef __cplusplus
bogdanm 85:024bf7f99721 1696 }
bogdanm 85:024bf7f99721 1697 #endif
bogdanm 85:024bf7f99721 1698
bogdanm 85:024bf7f99721 1699 #endif /* __STM32F0xx_HAL_RCC_H */
bogdanm 85:024bf7f99721 1700
bogdanm 85:024bf7f99721 1701 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bogdanm 92:4fc01daae5a5 1702