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TARGET_NUCLEO_F030R8/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_adc.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
134:ad3be0349dc5 
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 85:024bf7f99721 1 /**
bogdanm 85:024bf7f99721 2 ******************************************************************************
bogdanm 85:024bf7f99721 3 * @file stm32f0xx_hal_adc.h
bogdanm 85:024bf7f99721 4 * @author MCD Application Team
<> 134:ad3be0349dc5 5 * @version V1.5.0
<> 134:ad3be0349dc5 6 * @date 04-November-2016
bogdanm 85:024bf7f99721 7 * @brief Header file containing functions prototypes of ADC HAL library.
bogdanm 85:024bf7f99721 8 ******************************************************************************
bogdanm 85:024bf7f99721 9 * @attention
bogdanm 85:024bf7f99721 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 85:024bf7f99721 12 *
bogdanm 85:024bf7f99721 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 85:024bf7f99721 14 * are permitted provided that the following conditions are met:
bogdanm 85:024bf7f99721 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 85:024bf7f99721 16 * this list of conditions and the following disclaimer.
bogdanm 85:024bf7f99721 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 85:024bf7f99721 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 85:024bf7f99721 19 * and/or other materials provided with the distribution.
bogdanm 85:024bf7f99721 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 85:024bf7f99721 21 * may be used to endorse or promote products derived from this software
bogdanm 85:024bf7f99721 22 * without specific prior written permission.
bogdanm 85:024bf7f99721 23 *
bogdanm 85:024bf7f99721 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 85:024bf7f99721 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 85:024bf7f99721 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 85:024bf7f99721 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 85:024bf7f99721 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 85:024bf7f99721 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 85:024bf7f99721 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 85:024bf7f99721 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 85:024bf7f99721 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 85:024bf7f99721 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 85:024bf7f99721 34 *
bogdanm 85:024bf7f99721 35 ******************************************************************************
bogdanm 85:024bf7f99721 36 */
bogdanm 85:024bf7f99721 37
bogdanm 85:024bf7f99721 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 85:024bf7f99721 39 #ifndef __STM32F0xx_HAL_ADC_H
bogdanm 85:024bf7f99721 40 #define __STM32F0xx_HAL_ADC_H
bogdanm 85:024bf7f99721 41
bogdanm 85:024bf7f99721 42 #ifdef __cplusplus
bogdanm 85:024bf7f99721 43 extern "C" {
bogdanm 85:024bf7f99721 44 #endif
bogdanm 85:024bf7f99721 45
bogdanm 85:024bf7f99721 46 /* Includes ------------------------------------------------------------------*/
bogdanm 85:024bf7f99721 47 #include "stm32f0xx_hal_def.h"
bogdanm 85:024bf7f99721 48
bogdanm 85:024bf7f99721 49 /** @addtogroup STM32F0xx_HAL_Driver
bogdanm 85:024bf7f99721 50 * @{
bogdanm 85:024bf7f99721 51 */
bogdanm 85:024bf7f99721 52
bogdanm 85:024bf7f99721 53 /** @addtogroup ADC
bogdanm 85:024bf7f99721 54 * @{
bogdanm 85:024bf7f99721 55 */
bogdanm 85:024bf7f99721 56
bogdanm 85:024bf7f99721 57 /* Exported types ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 58 /** @defgroup ADC_Exported_Types ADC Exported Types
bogdanm 92:4fc01daae5a5 59 * @{
bogdanm 92:4fc01daae5a5 60 */
bogdanm 85:024bf7f99721 61
bogdanm 85:024bf7f99721 62 /**
bogdanm 85:024bf7f99721 63 * @brief Structure definition of ADC initialization and regular group
bogdanm 85:024bf7f99721 64 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
bogdanm 85:024bf7f99721 65 * ADC state can be either:
bogdanm 85:024bf7f99721 66 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ClockPrescaler')
Kojto 108:34e6b704fe68 67 * - For all parameters except 'ClockPrescaler' and 'resolution': ADC enabled without conversion on going on regular group.
bogdanm 85:024bf7f99721 68 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
Kojto 93:e188a91d3eaa 69 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
bogdanm 85:024bf7f99721 70 */
bogdanm 85:024bf7f99721 71 typedef struct
bogdanm 85:024bf7f99721 72 {
bogdanm 92:4fc01daae5a5 73 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator 14MHz) and clock prescaler.
bogdanm 85:024bf7f99721 74 This parameter can be a value of @ref ADC_ClockPrescaler
bogdanm 85:024bf7f99721 75 Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level.
bogdanm 85:024bf7f99721 76 Note: This parameter can be modified only if the ADC is disabled */
bogdanm 85:024bf7f99721 77 uint32_t Resolution; /*!< Configures the ADC resolution.
bogdanm 85:024bf7f99721 78 This parameter can be a value of @ref ADC_Resolution */
bogdanm 85:024bf7f99721 79 uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
bogdanm 92:4fc01daae5a5 80 This parameter can be a value of @ref ADC_Data_align */
bogdanm 85:024bf7f99721 81 uint32_t ScanConvMode; /*!< Configures the sequencer of regular group.
bogdanm 85:024bf7f99721 82 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
bogdanm 85:024bf7f99721 83 Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices):
bogdanm 85:024bf7f99721 84 If only 1 channel is set: Conversion is performed in single mode.
bogdanm 85:024bf7f99721 85 If several channels are set: Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
bogdanm 85:024bf7f99721 86 Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0).
bogdanm 85:024bf7f99721 87 This parameter can be a value of @ref ADC_Scan_mode */
bogdanm 85:024bf7f99721 88 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
bogdanm 85:024bf7f99721 89 This parameter can be a value of @ref ADC_EOCSelection. */
bogdanm 85:024bf7f99721 90 uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous
Kojto 108:34e6b704fe68 91 conversion (for regular group) has been treated by user software, using function HAL_ADC_GetValue().
Kojto 108:34e6b704fe68 92 This feature automatically adapts the ADC conversions trigs to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
bogdanm 92:4fc01daae5a5 93 This parameter can be set to ENABLE or DISABLE.
bogdanm 92:4fc01daae5a5 94 Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
bogdanm 92:4fc01daae5a5 95 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
bogdanm 92:4fc01daae5a5 96 and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion. */
bogdanm 85:024bf7f99721 97 uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
bogdanm 85:024bf7f99721 98 This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
bogdanm 85:024bf7f99721 99 This parameter can be set to ENABLE or DISABLE.
bogdanm 85:024bf7f99721 100 Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */
bogdanm 85:024bf7f99721 101 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
bogdanm 85:024bf7f99721 102 after the selected trigger occurred (software start or external trigger).
bogdanm 85:024bf7f99721 103 This parameter can be set to ENABLE or DISABLE. */
bogdanm 85:024bf7f99721 104 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
bogdanm 85:024bf7f99721 105 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
bogdanm 85:024bf7f99721 106 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
bogdanm 85:024bf7f99721 107 This parameter can be set to ENABLE or DISABLE
bogdanm 85:024bf7f99721 108 Note: Number of discontinuous ranks increment is fixed to one-by-one. */
bogdanm 85:024bf7f99721 109 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
bogdanm 85:024bf7f99721 110 If set to ADC_SOFTWARE_START, external triggers are disabled.
bogdanm 85:024bf7f99721 111 This parameter can be a value of @ref ADC_External_trigger_source_Regular */
bogdanm 85:024bf7f99721 112 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
bogdanm 85:024bf7f99721 113 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
bogdanm 85:024bf7f99721 114 This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
bogdanm 85:024bf7f99721 115 uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
bogdanm 85:024bf7f99721 116 or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
bogdanm 85:024bf7f99721 117 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
bogdanm 85:024bf7f99721 118 This parameter can be set to ENABLE or DISABLE. */
bogdanm 85:024bf7f99721 119 uint32_t Overrun; /*!< Select the behaviour in case of overrun: data preserved or overwritten
bogdanm 85:024bf7f99721 120 This parameter has an effect on regular group only, including in DMA mode.
bogdanm 85:024bf7f99721 121 This parameter can be a value of @ref ADC_Overrun */
Kojto 108:34e6b704fe68 122 uint32_t SamplingTimeCommon; /*!< Sampling time value to be set for the selected channel.
Kojto 108:34e6b704fe68 123 Unit: ADC clock cycles
Kojto 108:34e6b704fe68 124 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
Kojto 108:34e6b704fe68 125 Note: On STM32F0 devices, the sampling time setting is common to all channels. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure.
Kojto 108:34e6b704fe68 126 This parameter can be a value of @ref ADC_sampling_times
Kojto 108:34e6b704fe68 127 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
Kojto 108:34e6b704fe68 128 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
Kojto 108:34e6b704fe68 129 Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */
bogdanm 85:024bf7f99721 130 }ADC_InitTypeDef;
bogdanm 85:024bf7f99721 131
bogdanm 85:024bf7f99721 132 /**
bogdanm 85:024bf7f99721 133 * @brief Structure definition of ADC channel for regular group
bogdanm 85:024bf7f99721 134 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
bogdanm 85:024bf7f99721 135 * ADC state can be either:
bogdanm 85:024bf7f99721 136 * - For all parameters: ADC disabled or enabled without conversion on going on regular group.
bogdanm 85:024bf7f99721 137 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
bogdanm 85:024bf7f99721 138 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
bogdanm 85:024bf7f99721 139 */
bogdanm 85:024bf7f99721 140 typedef struct
bogdanm 85:024bf7f99721 141 {
bogdanm 85:024bf7f99721 142 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
bogdanm 85:024bf7f99721 143 This parameter can be a value of @ref ADC_channels
bogdanm 85:024bf7f99721 144 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
bogdanm 85:024bf7f99721 145 uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer.
Kojto 108:34e6b704fe68 146 On STM32F0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...)..
bogdanm 85:024bf7f99721 147 Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
bogdanm 85:024bf7f99721 148 This parameter can be a value of @ref ADC_rank */
bogdanm 92:4fc01daae5a5 149 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
bogdanm 85:024bf7f99721 150 Unit: ADC clock cycles
bogdanm 85:024bf7f99721 151 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
bogdanm 85:024bf7f99721 152 This parameter can be a value of @ref ADC_sampling_times
bogdanm 92:4fc01daae5a5 153 Caution: this setting impacts the entire regular group. Therefore, call of HAL_ADC_ConfigChannel() to configure a channel can impact the configuration of other channels previously set.
Kojto 108:34e6b704fe68 154 Caution: Obsolete parameter. Use parameter "SamplingTimeCommon" in ADC initialization structure.
Kojto 108:34e6b704fe68 155 If parameter "SamplingTimeCommon" is set to a valid sampling time, parameter "SamplingTime" is discarded.
bogdanm 85:024bf7f99721 156 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
bogdanm 85:024bf7f99721 157 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
bogdanm 85:024bf7f99721 158 Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */
bogdanm 85:024bf7f99721 159 }ADC_ChannelConfTypeDef;
bogdanm 85:024bf7f99721 160
bogdanm 85:024bf7f99721 161 /**
bogdanm 85:024bf7f99721 162 * @brief Structure definition of ADC analog watchdog
bogdanm 85:024bf7f99721 163 * @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
bogdanm 85:024bf7f99721 164 * ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular group.
bogdanm 85:024bf7f99721 165 */
bogdanm 85:024bf7f99721 166 typedef struct
bogdanm 85:024bf7f99721 167 {
bogdanm 85:024bf7f99721 168 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all/none channels.
bogdanm 85:024bf7f99721 169 This parameter can be a value of @ref ADC_analog_watchdog_mode. */
bogdanm 85:024bf7f99721 170 uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
bogdanm 85:024bf7f99721 171 This parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored.
bogdanm 85:024bf7f99721 172 This parameter can be a value of @ref ADC_channels. */
bogdanm 85:024bf7f99721 173 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
bogdanm 85:024bf7f99721 174 This parameter can be set to ENABLE or DISABLE */
bogdanm 85:024bf7f99721 175 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
bogdanm 85:024bf7f99721 176 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
bogdanm 85:024bf7f99721 177 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
bogdanm 85:024bf7f99721 178 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
bogdanm 85:024bf7f99721 179 }ADC_AnalogWDGConfTypeDef;
bogdanm 85:024bf7f99721 180
bogdanm 85:024bf7f99721 181 /**
Kojto 108:34e6b704fe68 182 * @brief HAL ADC state machine: ADC states definition (bitfields)
Kojto 122:f9eeca106725 183 * @note ADC state machine is managed by bitfields, state must be compared
Kojto 122:f9eeca106725 184 * with bit by bit.
Kojto 122:f9eeca106725 185 * For example:
Kojto 122:f9eeca106725 186 * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
Kojto 122:f9eeca106725 187 * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
Kojto 122:f9eeca106725 188 */
Kojto 108:34e6b704fe68 189 /* States of ADC global scope */
<> 134:ad3be0349dc5 190 #define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */
<> 134:ad3be0349dc5 191 #define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */
<> 134:ad3be0349dc5 192 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
<> 134:ad3be0349dc5 193 #define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */
Kojto 108:34e6b704fe68 194
Kojto 108:34e6b704fe68 195 /* States of ADC errors */
<> 134:ad3be0349dc5 196 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */
<> 134:ad3be0349dc5 197 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */
<> 134:ad3be0349dc5 198 #define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */
Kojto 108:34e6b704fe68 199
Kojto 108:34e6b704fe68 200 /* States of ADC group regular */
<> 134:ad3be0349dc5 201 #define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
Kojto 108:34e6b704fe68 202 external trigger, low power auto power-on, multimode ADC master control) */
<> 134:ad3be0349dc5 203 #define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */
<> 134:ad3be0349dc5 204 #define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */
<> 134:ad3be0349dc5 205 #define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< Not available on STM32F0 device: End Of Sampling flag raised */
Kojto 108:34e6b704fe68 206
Kojto 108:34e6b704fe68 207 /* States of ADC group injected */
<> 134:ad3be0349dc5 208 #define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
Kojto 108:34e6b704fe68 209 external trigger, low power auto power-on, multimode ADC master control) */
<> 134:ad3be0349dc5 210 #define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Not available on STM32F0 device: Conversion data available on group injected */
<> 134:ad3be0349dc5 211 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence */
Kojto 108:34e6b704fe68 212
Kojto 108:34e6b704fe68 213 /* States of ADC analog watchdogs */
<> 134:ad3be0349dc5 214 #define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
<> 134:ad3be0349dc5 215 #define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 */
<> 134:ad3be0349dc5 216 #define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 */
Kojto 108:34e6b704fe68 217
Kojto 108:34e6b704fe68 218 /* States of ADC multi-mode */
<> 134:ad3be0349dc5 219 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( */
Kojto 108:34e6b704fe68 220
bogdanm 85:024bf7f99721 221
bogdanm 85:024bf7f99721 222 /**
bogdanm 85:024bf7f99721 223 * @brief ADC handle Structure definition
bogdanm 85:024bf7f99721 224 */
bogdanm 85:024bf7f99721 225 typedef struct
bogdanm 85:024bf7f99721 226 {
bogdanm 85:024bf7f99721 227 ADC_TypeDef *Instance; /*!< Register base address */
bogdanm 85:024bf7f99721 228
bogdanm 85:024bf7f99721 229 ADC_InitTypeDef Init; /*!< ADC required parameters */
bogdanm 85:024bf7f99721 230
bogdanm 85:024bf7f99721 231 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
bogdanm 85:024bf7f99721 232
bogdanm 85:024bf7f99721 233 HAL_LockTypeDef Lock; /*!< ADC locking object */
bogdanm 85:024bf7f99721 234
Kojto 108:34e6b704fe68 235 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
bogdanm 85:024bf7f99721 236
bogdanm 85:024bf7f99721 237 __IO uint32_t ErrorCode; /*!< ADC Error code */
bogdanm 85:024bf7f99721 238 }ADC_HandleTypeDef;
bogdanm 92:4fc01daae5a5 239 /**
bogdanm 92:4fc01daae5a5 240 * @}
bogdanm 92:4fc01daae5a5 241 */
bogdanm 92:4fc01daae5a5 242
bogdanm 92:4fc01daae5a5 243
bogdanm 85:024bf7f99721 244
bogdanm 85:024bf7f99721 245 /* Exported constants --------------------------------------------------------*/
bogdanm 85:024bf7f99721 246
bogdanm 92:4fc01daae5a5 247 /** @defgroup ADC_Exported_Constants ADC Exported Constants
bogdanm 85:024bf7f99721 248 * @{
bogdanm 85:024bf7f99721 249 */
bogdanm 85:024bf7f99721 250
bogdanm 92:4fc01daae5a5 251 /** @defgroup ADC_Error_Code ADC Error Code
bogdanm 85:024bf7f99721 252 * @{
bogdanm 85:024bf7f99721 253 */
<> 134:ad3be0349dc5 254 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
<> 134:ad3be0349dc5 255 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error: if problem of clocking,
bogdanm 85:024bf7f99721 256 enable/disable, erroneous state */
<> 134:ad3be0349dc5 257 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
<> 134:ad3be0349dc5 258 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
bogdanm 85:024bf7f99721 259
bogdanm 85:024bf7f99721 260 /**
bogdanm 85:024bf7f99721 261 * @}
bogdanm 85:024bf7f99721 262 */
bogdanm 85:024bf7f99721 263
bogdanm 92:4fc01daae5a5 264 /** @defgroup ADC_ClockPrescaler ADC ClockPrescaler
bogdanm 85:024bf7f99721 265 * @{
bogdanm 85:024bf7f99721 266 */
<> 134:ad3be0349dc5 267 #define ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock derived from ADC dedicated HSI */
bogdanm 85:024bf7f99721 268
bogdanm 85:024bf7f99721 269 #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */
bogdanm 85:024bf7f99721 270 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */
bogdanm 85:024bf7f99721 271
bogdanm 85:024bf7f99721 272 /**
bogdanm 85:024bf7f99721 273 * @}
bogdanm 85:024bf7f99721 274 */
bogdanm 85:024bf7f99721 275
bogdanm 92:4fc01daae5a5 276 /** @defgroup ADC_Resolution ADC Resolution
bogdanm 85:024bf7f99721 277 * @{
bogdanm 85:024bf7f99721 278 */
<> 134:ad3be0349dc5 279 #define ADC_RESOLUTION_12B (0x00000000U) /*!< ADC 12-bit resolution */
Kojto 108:34e6b704fe68 280 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */
Kojto 108:34e6b704fe68 281 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */
Kojto 108:34e6b704fe68 282 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */
bogdanm 85:024bf7f99721 283 /**
bogdanm 85:024bf7f99721 284 * @}
bogdanm 85:024bf7f99721 285 */
bogdanm 85:024bf7f99721 286
bogdanm 92:4fc01daae5a5 287 /** @defgroup ADC_Data_align ADC Data_align
bogdanm 85:024bf7f99721 288 * @{
bogdanm 85:024bf7f99721 289 */
<> 134:ad3be0349dc5 290 #define ADC_DATAALIGN_RIGHT (0x00000000U)
bogdanm 85:024bf7f99721 291 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN)
bogdanm 85:024bf7f99721 292 /**
bogdanm 85:024bf7f99721 293 * @}
bogdanm 85:024bf7f99721 294 */
bogdanm 85:024bf7f99721 295
bogdanm 92:4fc01daae5a5 296 /** @defgroup ADC_Scan_mode ADC Scan mode
bogdanm 85:024bf7f99721 297 * @{
bogdanm 85:024bf7f99721 298 */
bogdanm 85:024bf7f99721 299 /* Note: Scan mode values must be compatible with other STM32 devices having */
bogdanm 85:024bf7f99721 300 /* a configurable sequencer. */
bogdanm 85:024bf7f99721 301 /* Scan direction setting values are defined by taking in account */
bogdanm 85:024bf7f99721 302 /* already defined values for other STM32 devices: */
<> 134:ad3be0349dc5 303 /* ADC_SCAN_DISABLE (0x00000000U) */
<> 134:ad3be0349dc5 304 /* ADC_SCAN_ENABLE (0x00000001U) */
bogdanm 85:024bf7f99721 305 /* Scan direction forward is considered as default setting equivalent */
bogdanm 85:024bf7f99721 306 /* to scan enable. */
bogdanm 85:024bf7f99721 307 /* Scan direction backward is considered as additional setting. */
bogdanm 85:024bf7f99721 308 /* In case of migration from another STM32 device, the user will be */
bogdanm 85:024bf7f99721 309 /* warned of change of setting choices with assert check. */
<> 134:ad3be0349dc5 310 #define ADC_SCAN_DIRECTION_FORWARD (0x00000001U) /*!< Scan direction forward: from channel 0 to channel 18 */
<> 134:ad3be0349dc5 311 #define ADC_SCAN_DIRECTION_BACKWARD (0x00000002U) /*!< Scan direction backward: from channel 18 to channel 0 */
bogdanm 85:024bf7f99721 312
bogdanm 85:024bf7f99721 313 #define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */
bogdanm 85:024bf7f99721 314
bogdanm 85:024bf7f99721 315 /**
bogdanm 85:024bf7f99721 316 * @}
bogdanm 85:024bf7f99721 317 */
bogdanm 85:024bf7f99721 318
bogdanm 92:4fc01daae5a5 319 /** @defgroup ADC_External_trigger_edge_Regular ADC External trigger edge Regular
bogdanm 85:024bf7f99721 320 * @{
bogdanm 85:024bf7f99721 321 */
<> 134:ad3be0349dc5 322 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U)
bogdanm 85:024bf7f99721 323 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0)
bogdanm 85:024bf7f99721 324 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1)
bogdanm 85:024bf7f99721 325 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN)
bogdanm 85:024bf7f99721 326 /**
bogdanm 85:024bf7f99721 327 * @}
bogdanm 85:024bf7f99721 328 */
bogdanm 85:024bf7f99721 329
bogdanm 92:4fc01daae5a5 330 /** @defgroup ADC_EOCSelection ADC EOCSelection
bogdanm 85:024bf7f99721 331 * @{
bogdanm 85:024bf7f99721 332 */
Kojto 108:34e6b704fe68 333 #define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
Kojto 108:34e6b704fe68 334 #define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
Kojto 108:34e6b704fe68 335 #define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */
bogdanm 85:024bf7f99721 336 /**
bogdanm 85:024bf7f99721 337 * @}
bogdanm 85:024bf7f99721 338 */
bogdanm 85:024bf7f99721 339
bogdanm 92:4fc01daae5a5 340 /** @defgroup ADC_Overrun ADC Overrun
bogdanm 85:024bf7f99721 341 * @{
bogdanm 85:024bf7f99721 342 */
<> 134:ad3be0349dc5 343 #define ADC_OVR_DATA_OVERWRITTEN (0x00000000U)
<> 134:ad3be0349dc5 344 #define ADC_OVR_DATA_PRESERVED (0x00000001U)
bogdanm 85:024bf7f99721 345 /**
bogdanm 85:024bf7f99721 346 * @}
bogdanm 85:024bf7f99721 347 */
bogdanm 85:024bf7f99721 348
bogdanm 92:4fc01daae5a5 349 /** @defgroup ADC_rank ADC rank
bogdanm 85:024bf7f99721 350 * @{
bogdanm 85:024bf7f99721 351 */
<> 134:ad3be0349dc5 352 #define ADC_RANK_CHANNEL_NUMBER (0x00001000U) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
<> 134:ad3be0349dc5 353 #define ADC_RANK_NONE (0x00001001U) /*!< Disable the selected rank (selected channel) from sequencer */
bogdanm 85:024bf7f99721 354 /**
bogdanm 85:024bf7f99721 355 * @}
bogdanm 85:024bf7f99721 356 */
bogdanm 85:024bf7f99721 357
bogdanm 92:4fc01daae5a5 358 /** @defgroup ADC_sampling_times ADC sampling times
bogdanm 85:024bf7f99721 359 * @{
Kojto 108:34e6b704fe68 360 */
Kojto 108:34e6b704fe68 361 /* Note: Parameter "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit */
Kojto 108:34e6b704fe68 362 /* to distinguish this parameter versus reset value 0x00000000, */
Kojto 108:34e6b704fe68 363 /* in the context of management of parameters "SamplingTimeCommon" */
Kojto 108:34e6b704fe68 364 /* and "SamplingTime" (obsolete)). */
<> 134:ad3be0349dc5 365 #define ADC_SAMPLETIME_1CYCLE_5 (0x10000000U) /*!< Sampling time 1.5 ADC clock cycle */
bogdanm 85:024bf7f99721 366 #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR_SMP_0) /*!< Sampling time 7.5 ADC clock cycles */
bogdanm 85:024bf7f99721 367 #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR_SMP_1) /*!< Sampling time 13.5 ADC clock cycles */
bogdanm 85:024bf7f99721 368 #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0)) /*!< Sampling time 28.5 ADC clock cycles */
bogdanm 85:024bf7f99721 369 #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t) ADC_SMPR_SMP_2) /*!< Sampling time 41.5 ADC clock cycles */
bogdanm 85:024bf7f99721 370 #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0)) /*!< Sampling time 55.5 ADC clock cycles */
bogdanm 85:024bf7f99721 371 #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1)) /*!< Sampling time 71.5 ADC clock cycles */
bogdanm 85:024bf7f99721 372 #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR_SMP) /*!< Sampling time 239.5 ADC clock cycles */
bogdanm 85:024bf7f99721 373 /**
bogdanm 85:024bf7f99721 374 * @}
bogdanm 85:024bf7f99721 375 */
bogdanm 85:024bf7f99721 376
bogdanm 92:4fc01daae5a5 377 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
bogdanm 85:024bf7f99721 378 * @{
bogdanm 85:024bf7f99721 379 */
<> 134:ad3be0349dc5 380 #define ADC_ANALOGWATCHDOG_NONE ( 0x00000000U)
bogdanm 85:024bf7f99721 381 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN))
bogdanm 85:024bf7f99721 382 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN)
bogdanm 85:024bf7f99721 383 /**
bogdanm 85:024bf7f99721 384 * @}
bogdanm 85:024bf7f99721 385 */
bogdanm 85:024bf7f99721 386
bogdanm 92:4fc01daae5a5 387 /** @defgroup ADC_Event_type ADC Event type
bogdanm 85:024bf7f99721 388 * @{
bogdanm 85:024bf7f99721 389 */
Kojto 108:34e6b704fe68 390 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog 1 event */
Kojto 108:34e6b704fe68 391 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */
bogdanm 85:024bf7f99721 392 /**
bogdanm 85:024bf7f99721 393 * @}
bogdanm 85:024bf7f99721 394 */
bogdanm 85:024bf7f99721 395
bogdanm 92:4fc01daae5a5 396 /** @defgroup ADC_interrupts_definition ADC interrupts definition
bogdanm 85:024bf7f99721 397 * @{
bogdanm 85:024bf7f99721 398 */
bogdanm 85:024bf7f99721 399 #define ADC_IT_AWD ADC_IER_AWDIE /*!< ADC Analog watchdog interrupt source */
bogdanm 85:024bf7f99721 400 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
bogdanm 85:024bf7f99721 401 #define ADC_IT_EOS ADC_IER_EOSEQIE /*!< ADC End of Regular sequence of Conversions interrupt source */
bogdanm 85:024bf7f99721 402 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of Regular Conversion interrupt source */
bogdanm 85:024bf7f99721 403 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of Sampling interrupt source */
bogdanm 85:024bf7f99721 404 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */
bogdanm 85:024bf7f99721 405 /**
bogdanm 85:024bf7f99721 406 * @}
bogdanm 85:024bf7f99721 407 */
bogdanm 85:024bf7f99721 408
bogdanm 92:4fc01daae5a5 409 /** @defgroup ADC_flags_definition ADC flags definition
bogdanm 85:024bf7f99721 410 * @{
bogdanm 85:024bf7f99721 411 */
bogdanm 85:024bf7f99721 412 #define ADC_FLAG_AWD ADC_ISR_AWD /*!< ADC Analog watchdog flag */
bogdanm 85:024bf7f99721 413 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
bogdanm 85:024bf7f99721 414 #define ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC End of Regular sequence of Conversions flag */
bogdanm 85:024bf7f99721 415 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
bogdanm 85:024bf7f99721 416 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
bogdanm 85:024bf7f99721 417 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */
bogdanm 85:024bf7f99721 418 /**
bogdanm 85:024bf7f99721 419 * @}
bogdanm 85:024bf7f99721 420 */
bogdanm 85:024bf7f99721 421
Kojto 108:34e6b704fe68 422 /**
Kojto 108:34e6b704fe68 423 * @}
bogdanm 85:024bf7f99721 424 */
Kojto 108:34e6b704fe68 425
Kojto 108:34e6b704fe68 426
Kojto 108:34e6b704fe68 427 /* Private constants ---------------------------------------------------------*/
Kojto 108:34e6b704fe68 428
Kojto 108:34e6b704fe68 429 /** @addtogroup ADC_Private_Constants ADC Private Constants
Kojto 108:34e6b704fe68 430 * @{
Kojto 108:34e6b704fe68 431 */
Kojto 108:34e6b704fe68 432
Kojto 108:34e6b704fe68 433 /** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular
Kojto 108:34e6b704fe68 434 * @{
Kojto 108:34e6b704fe68 435 */
Kojto 108:34e6b704fe68 436
Kojto 108:34e6b704fe68 437 /* List of external triggers of regular group for ADC1: */
Kojto 108:34e6b704fe68 438 /* (used internally by HAL driver. To not use into HAL structure parameters) */
<> 134:ad3be0349dc5 439 #define ADC1_2_EXTERNALTRIG_T1_TRGO (0x00000000U)
Kojto 108:34e6b704fe68 440 #define ADC1_2_EXTERNALTRIG_T1_CC4 ((uint32_t)ADC_CFGR1_EXTSEL_0)
Kojto 108:34e6b704fe68 441 #define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_1)
Kojto 108:34e6b704fe68 442 #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0))
Kojto 108:34e6b704fe68 443 #define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_2)
bogdanm 85:024bf7f99721 444 /**
bogdanm 85:024bf7f99721 445 * @}
bogdanm 85:024bf7f99721 446 */
bogdanm 85:024bf7f99721 447
Kojto 108:34e6b704fe68 448 /* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */
Kojto 108:34e6b704fe68 449 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC)
bogdanm 85:024bf7f99721 450
bogdanm 85:024bf7f99721 451 /**
bogdanm 85:024bf7f99721 452 * @}
Kojto 108:34e6b704fe68 453 */
Kojto 108:34e6b704fe68 454
Kojto 108:34e6b704fe68 455
Kojto 108:34e6b704fe68 456 /* Exported macro ------------------------------------------------------------*/
bogdanm 85:024bf7f99721 457
bogdanm 92:4fc01daae5a5 458 /** @defgroup ADC_Exported_Macros ADC Exported Macros
bogdanm 85:024bf7f99721 459 * @{
bogdanm 85:024bf7f99721 460 */
Kojto 108:34e6b704fe68 461 /* Macro for internal HAL driver usage, and possibly can be used into code of */
Kojto 108:34e6b704fe68 462 /* final user. */
Kojto 108:34e6b704fe68 463
Kojto 108:34e6b704fe68 464 /**
Kojto 108:34e6b704fe68 465 * @brief Enable the ADC peripheral
Kojto 108:34e6b704fe68 466 * @param __HANDLE__: ADC handle
Kojto 108:34e6b704fe68 467 * @retval None
Kojto 108:34e6b704fe68 468 */
Kojto 108:34e6b704fe68 469 #define __HAL_ADC_ENABLE(__HANDLE__) \
Kojto 108:34e6b704fe68 470 ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
Kojto 108:34e6b704fe68 471
Kojto 108:34e6b704fe68 472 /**
Kojto 108:34e6b704fe68 473 * @brief Disable the ADC peripheral
Kojto 108:34e6b704fe68 474 * @param __HANDLE__: ADC handle
Kojto 108:34e6b704fe68 475 * @retval None
Kojto 108:34e6b704fe68 476 */
Kojto 108:34e6b704fe68 477 #define __HAL_ADC_DISABLE(__HANDLE__) \
Kojto 108:34e6b704fe68 478 do{ \
Kojto 108:34e6b704fe68 479 (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \
Kojto 108:34e6b704fe68 480 __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
Kojto 108:34e6b704fe68 481 } while(0)
Kojto 108:34e6b704fe68 482
Kojto 108:34e6b704fe68 483 /**
Kojto 108:34e6b704fe68 484 * @brief Enable the ADC end of conversion interrupt.
Kojto 108:34e6b704fe68 485 * @param __HANDLE__: ADC handle
Kojto 108:34e6b704fe68 486 * @param __INTERRUPT__: ADC Interrupt
Kojto 108:34e6b704fe68 487 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 488 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
Kojto 108:34e6b704fe68 489 * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
Kojto 108:34e6b704fe68 490 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
Kojto 108:34e6b704fe68 491 * @arg ADC_IT_OVR: ADC overrun interrupt source
Kojto 108:34e6b704fe68 492 * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
Kojto 108:34e6b704fe68 493 * @arg ADC_IT_RDY: ADC Ready interrupt source
Kojto 108:34e6b704fe68 494 * @retval None
Kojto 108:34e6b704fe68 495 */
Kojto 108:34e6b704fe68 496 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
Kojto 108:34e6b704fe68 497 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Kojto 108:34e6b704fe68 498
Kojto 108:34e6b704fe68 499 /**
Kojto 108:34e6b704fe68 500 * @brief Disable the ADC end of conversion interrupt.
Kojto 108:34e6b704fe68 501 * @param __HANDLE__: ADC handle
Kojto 108:34e6b704fe68 502 * @param __INTERRUPT__: ADC Interrupt
Kojto 108:34e6b704fe68 503 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 504 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
Kojto 108:34e6b704fe68 505 * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
Kojto 108:34e6b704fe68 506 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
Kojto 108:34e6b704fe68 507 * @arg ADC_IT_OVR: ADC overrun interrupt source
Kojto 108:34e6b704fe68 508 * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
Kojto 108:34e6b704fe68 509 * @arg ADC_IT_RDY: ADC Ready interrupt source
Kojto 108:34e6b704fe68 510 * @retval None
Kojto 108:34e6b704fe68 511 */
Kojto 108:34e6b704fe68 512 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
Kojto 108:34e6b704fe68 513 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Kojto 108:34e6b704fe68 514
Kojto 108:34e6b704fe68 515 /** @brief Checks if the specified ADC interrupt source is enabled or disabled.
Kojto 108:34e6b704fe68 516 * @param __HANDLE__: ADC handle
Kojto 108:34e6b704fe68 517 * @param __INTERRUPT__: ADC interrupt source to check
Kojto 108:34e6b704fe68 518 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 519 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
Kojto 108:34e6b704fe68 520 * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
Kojto 108:34e6b704fe68 521 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
Kojto 108:34e6b704fe68 522 * @arg ADC_IT_OVR: ADC overrun interrupt source
Kojto 108:34e6b704fe68 523 * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
Kojto 108:34e6b704fe68 524 * @arg ADC_IT_RDY: ADC Ready interrupt source
Kojto 108:34e6b704fe68 525 * @retval State ofinterruption (SET or RESET)
Kojto 108:34e6b704fe68 526 */
Kojto 108:34e6b704fe68 527 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
Kojto 108:34e6b704fe68 528 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
Kojto 108:34e6b704fe68 529
Kojto 108:34e6b704fe68 530 /**
Kojto 108:34e6b704fe68 531 * @brief Get the selected ADC's flag status.
Kojto 108:34e6b704fe68 532 * @param __HANDLE__: ADC handle
Kojto 108:34e6b704fe68 533 * @param __FLAG__: ADC flag
Kojto 108:34e6b704fe68 534 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 535 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
Kojto 108:34e6b704fe68 536 * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
Kojto 108:34e6b704fe68 537 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
Kojto 108:34e6b704fe68 538 * @arg ADC_FLAG_OVR: ADC overrun flag
Kojto 108:34e6b704fe68 539 * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
Kojto 108:34e6b704fe68 540 * @arg ADC_FLAG_RDY: ADC Ready flag
Kojto 108:34e6b704fe68 541 * @retval None
Kojto 108:34e6b704fe68 542 */
Kojto 108:34e6b704fe68 543 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
Kojto 108:34e6b704fe68 544 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
Kojto 108:34e6b704fe68 545
Kojto 108:34e6b704fe68 546 /**
Kojto 108:34e6b704fe68 547 * @brief Clear the ADC's pending flags
Kojto 108:34e6b704fe68 548 * @param __HANDLE__: ADC handle
Kojto 108:34e6b704fe68 549 * @param __FLAG__: ADC flag
Kojto 108:34e6b704fe68 550 * This parameter can be any combination of the following values:
Kojto 108:34e6b704fe68 551 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
Kojto 108:34e6b704fe68 552 * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
Kojto 108:34e6b704fe68 553 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
Kojto 108:34e6b704fe68 554 * @arg ADC_FLAG_OVR: ADC overrun flag
Kojto 108:34e6b704fe68 555 * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
Kojto 108:34e6b704fe68 556 * @arg ADC_FLAG_RDY: ADC Ready flag
Kojto 108:34e6b704fe68 557 * @retval None
Kojto 108:34e6b704fe68 558 */
Kojto 108:34e6b704fe68 559 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
Kojto 108:34e6b704fe68 560 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
Kojto 108:34e6b704fe68 561 (((__HANDLE__)->Instance->ISR) = (__FLAG__))
Kojto 108:34e6b704fe68 562
bogdanm 85:024bf7f99721 563 /** @brief Reset ADC handle state
bogdanm 85:024bf7f99721 564 * @param __HANDLE__: ADC handle
bogdanm 85:024bf7f99721 565 * @retval None
bogdanm 85:024bf7f99721 566 */
Kojto 108:34e6b704fe68 567 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
Kojto 108:34e6b704fe68 568 ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
Kojto 108:34e6b704fe68 569
Kojto 108:34e6b704fe68 570 /**
Kojto 108:34e6b704fe68 571 * @}
Kojto 108:34e6b704fe68 572 */
Kojto 108:34e6b704fe68 573
Kojto 108:34e6b704fe68 574
Kojto 108:34e6b704fe68 575 /* Private macro -------------------------------------------------------------*/
Kojto 108:34e6b704fe68 576
Kojto 108:34e6b704fe68 577 /** @defgroup ADC_Private_Macros ADC Private Macros
Kojto 108:34e6b704fe68 578 * @{
Kojto 108:34e6b704fe68 579 */
Kojto 108:34e6b704fe68 580 /* Macro reserved for internal HAL driver usage, not intended to be used in */
Kojto 108:34e6b704fe68 581 /* code of final user. */
Kojto 108:34e6b704fe68 582
bogdanm 85:024bf7f99721 583
Kojto 108:34e6b704fe68 584 /**
Kojto 108:34e6b704fe68 585 * @brief Verification of hardware constraints before ADC can be enabled
Kojto 108:34e6b704fe68 586 * @param __HANDLE__: ADC handle
Kojto 108:34e6b704fe68 587 * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
Kojto 108:34e6b704fe68 588 */
Kojto 108:34e6b704fe68 589 #define ADC_ENABLING_CONDITIONS(__HANDLE__) \
Kojto 108:34e6b704fe68 590 (( ( ((__HANDLE__)->Instance->CR) & \
Kojto 108:34e6b704fe68 591 (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) \
Kojto 108:34e6b704fe68 592 ) == RESET \
Kojto 108:34e6b704fe68 593 ) ? SET : RESET)
Kojto 108:34e6b704fe68 594
Kojto 108:34e6b704fe68 595 /**
Kojto 108:34e6b704fe68 596 * @brief Verification of hardware constraints before ADC can be disabled
Kojto 108:34e6b704fe68 597 * @param __HANDLE__: ADC handle
Kojto 108:34e6b704fe68 598 * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
Kojto 108:34e6b704fe68 599 */
Kojto 108:34e6b704fe68 600 #define ADC_DISABLING_CONDITIONS(__HANDLE__) \
Kojto 108:34e6b704fe68 601 (( ( ((__HANDLE__)->Instance->CR) & \
Kojto 108:34e6b704fe68 602 (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \
Kojto 108:34e6b704fe68 603 ) ? SET : RESET)
bogdanm 85:024bf7f99721 604
bogdanm 85:024bf7f99721 605 /**
bogdanm 85:024bf7f99721 606 * @brief Verification of ADC state: enabled or disabled
bogdanm 85:024bf7f99721 607 * @param __HANDLE__: ADC handle
bogdanm 85:024bf7f99721 608 * @retval SET (ADC enabled) or RESET (ADC disabled)
bogdanm 85:024bf7f99721 609 */
bogdanm 85:024bf7f99721 610 /* Note: If low power mode AutoPowerOff is enabled, power-on/off phases are */
bogdanm 85:024bf7f99721 611 /* performed automatically by hardware and flag ADC_FLAG_RDY is not */
bogdanm 85:024bf7f99721 612 /* set. */
Kojto 108:34e6b704fe68 613 #define ADC_IS_ENABLE(__HANDLE__) \
Kojto 108:34e6b704fe68 614 (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
Kojto 108:34e6b704fe68 615 (((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) || \
Kojto 108:34e6b704fe68 616 ((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_AUTOFF) == ADC_CFGR1_AUTOFF) ) \
Kojto 108:34e6b704fe68 617 ) ? SET : RESET)
bogdanm 85:024bf7f99721 618
bogdanm 85:024bf7f99721 619 /**
bogdanm 85:024bf7f99721 620 * @brief Test if conversion trigger of regular group is software start
bogdanm 85:024bf7f99721 621 * or external trigger.
bogdanm 85:024bf7f99721 622 * @param __HANDLE__: ADC handle
bogdanm 85:024bf7f99721 623 * @retval SET (software start) or RESET (external trigger)
bogdanm 85:024bf7f99721 624 */
Kojto 108:34e6b704fe68 625 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
Kojto 108:34e6b704fe68 626 (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET)
bogdanm 85:024bf7f99721 627
bogdanm 85:024bf7f99721 628 /**
bogdanm 85:024bf7f99721 629 * @brief Check if no conversion on going on regular group
bogdanm 85:024bf7f99721 630 * @param __HANDLE__: ADC handle
bogdanm 85:024bf7f99721 631 * @retval SET (conversion is on going) or RESET (no conversion is on going)
bogdanm 85:024bf7f99721 632 */
Kojto 108:34e6b704fe68 633 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
Kojto 108:34e6b704fe68 634 (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
Kojto 108:34e6b704fe68 635 ) ? RESET : SET)
bogdanm 85:024bf7f99721 636
bogdanm 85:024bf7f99721 637 /**
bogdanm 85:024bf7f99721 638 * @brief Returns resolution bits in CFGR1 register: RES[1:0].
bogdanm 85:024bf7f99721 639 * Returned value is among parameters to @ref ADC_Resolution.
bogdanm 85:024bf7f99721 640 * @param __HANDLE__: ADC handle
bogdanm 85:024bf7f99721 641 * @retval None
bogdanm 85:024bf7f99721 642 */
Kojto 108:34e6b704fe68 643 #define ADC_GET_RESOLUTION(__HANDLE__) \
Kojto 108:34e6b704fe68 644 (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)
bogdanm 85:024bf7f99721 645
bogdanm 85:024bf7f99721 646 /**
bogdanm 85:024bf7f99721 647 * @brief Returns ADC sample time bits in SMPR register: SMP[2:0].
bogdanm 85:024bf7f99721 648 * Returned value is among parameters to @ref ADC_Resolution.
bogdanm 85:024bf7f99721 649 * @param __HANDLE__: ADC handle
bogdanm 85:024bf7f99721 650 * @retval None
bogdanm 85:024bf7f99721 651 */
Kojto 108:34e6b704fe68 652 #define ADC_GET_SAMPLINGTIME(__HANDLE__) \
Kojto 108:34e6b704fe68 653 (((__HANDLE__)->Instance->SMPR) & ADC_SMPR_SMP)
bogdanm 85:024bf7f99721 654
bogdanm 85:024bf7f99721 655 /**
Kojto 108:34e6b704fe68 656 * @brief Simultaneously clears and sets specific bits of the handle State
Kojto 108:34e6b704fe68 657 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
Kojto 108:34e6b704fe68 658 * the first parameter is the ADC handle State, the second parameter is the
Kojto 108:34e6b704fe68 659 * bit field to clear, the third and last parameter is the bit field to set.
bogdanm 85:024bf7f99721 660 * @retval None
bogdanm 85:024bf7f99721 661 */
Kojto 108:34e6b704fe68 662 #define ADC_STATE_CLR_SET MODIFY_REG
bogdanm 85:024bf7f99721 663
bogdanm 85:024bf7f99721 664 /**
bogdanm 85:024bf7f99721 665 * @brief Clear ADC error code (set it to error code: "no error")
bogdanm 85:024bf7f99721 666 * @param __HANDLE__: ADC handle
bogdanm 85:024bf7f99721 667 * @retval None
bogdanm 85:024bf7f99721 668 */
Kojto 108:34e6b704fe68 669 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \
Kojto 108:34e6b704fe68 670 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
bogdanm 85:024bf7f99721 671
bogdanm 85:024bf7f99721 672
bogdanm 85:024bf7f99721 673 /**
bogdanm 85:024bf7f99721 674 * @brief Configure the channel number into channel selection register
bogdanm 85:024bf7f99721 675 * @param _CHANNEL_: ADC Channel
bogdanm 85:024bf7f99721 676 * @retval None
bogdanm 85:024bf7f99721 677 */
bogdanm 85:024bf7f99721 678 /* This function converts ADC channels from numbers (see defgroup ADC_channels)
bogdanm 85:024bf7f99721 679 to bitfields, to get the equivalence of CMSIS channels:
bogdanm 85:024bf7f99721 680 ADC_CHANNEL_0 ((uint32_t) ADC_CHSELR_CHSEL0)
bogdanm 85:024bf7f99721 681 ADC_CHANNEL_1 ((uint32_t) ADC_CHSELR_CHSEL1)
bogdanm 85:024bf7f99721 682 ADC_CHANNEL_2 ((uint32_t) ADC_CHSELR_CHSEL2)
bogdanm 85:024bf7f99721 683 ADC_CHANNEL_3 ((uint32_t) ADC_CHSELR_CHSEL3)
bogdanm 85:024bf7f99721 684 ADC_CHANNEL_4 ((uint32_t) ADC_CHSELR_CHSEL4)
bogdanm 85:024bf7f99721 685 ADC_CHANNEL_5 ((uint32_t) ADC_CHSELR_CHSEL5)
bogdanm 85:024bf7f99721 686 ADC_CHANNEL_6 ((uint32_t) ADC_CHSELR_CHSEL6)
bogdanm 85:024bf7f99721 687 ADC_CHANNEL_7 ((uint32_t) ADC_CHSELR_CHSEL7)
bogdanm 85:024bf7f99721 688 ADC_CHANNEL_8 ((uint32_t) ADC_CHSELR_CHSEL8)
bogdanm 85:024bf7f99721 689 ADC_CHANNEL_9 ((uint32_t) ADC_CHSELR_CHSEL9)
bogdanm 85:024bf7f99721 690 ADC_CHANNEL_10 ((uint32_t) ADC_CHSELR_CHSEL10)
bogdanm 85:024bf7f99721 691 ADC_CHANNEL_11 ((uint32_t) ADC_CHSELR_CHSEL11)
bogdanm 85:024bf7f99721 692 ADC_CHANNEL_12 ((uint32_t) ADC_CHSELR_CHSEL12)
bogdanm 85:024bf7f99721 693 ADC_CHANNEL_13 ((uint32_t) ADC_CHSELR_CHSEL13)
bogdanm 85:024bf7f99721 694 ADC_CHANNEL_14 ((uint32_t) ADC_CHSELR_CHSEL14)
bogdanm 85:024bf7f99721 695 ADC_CHANNEL_15 ((uint32_t) ADC_CHSELR_CHSEL15)
bogdanm 85:024bf7f99721 696 ADC_CHANNEL_16 ((uint32_t) ADC_CHSELR_CHSEL16)
bogdanm 85:024bf7f99721 697 ADC_CHANNEL_17 ((uint32_t) ADC_CHSELR_CHSEL17)
bogdanm 85:024bf7f99721 698 ADC_CHANNEL_18 ((uint32_t) ADC_CHSELR_CHSEL18)
bogdanm 85:024bf7f99721 699 */
Kojto 108:34e6b704fe68 700 #define ADC_CHSELR_CHANNEL(_CHANNEL_) \
Kojto 108:34e6b704fe68 701 ( 1U << (_CHANNEL_))
bogdanm 85:024bf7f99721 702
Kojto 108:34e6b704fe68 703 /**
Kojto 108:34e6b704fe68 704 * @brief Set the ADC's sample time
Kojto 108:34e6b704fe68 705 * @param _SAMPLETIME_: Sample time parameter.
Kojto 108:34e6b704fe68 706 * @retval None
bogdanm 85:024bf7f99721 707 */
Kojto 108:34e6b704fe68 708 /* Note: ADC sampling time set using mask ADC_SMPR_SMP due to parameter */
Kojto 108:34e6b704fe68 709 /* "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit (bit used to */
Kojto 108:34e6b704fe68 710 /* distinguish this parameter versus reset value 0x00000000, */
Kojto 108:34e6b704fe68 711 /* in the context of management of parameters "SamplingTimeCommon" */
Kojto 108:34e6b704fe68 712 /* and "SamplingTime" (obsolete)). */
Kojto 108:34e6b704fe68 713 #define ADC_SMPR_SET(_SAMPLETIME_) \
Kojto 108:34e6b704fe68 714 ((_SAMPLETIME_) & (ADC_SMPR_SMP))
bogdanm 85:024bf7f99721 715
bogdanm 85:024bf7f99721 716 /**
bogdanm 85:024bf7f99721 717 * @brief Set the Analog Watchdog 1 channel.
bogdanm 85:024bf7f99721 718 * @param _CHANNEL_: channel to be monitored by Analog Watchdog 1.
bogdanm 85:024bf7f99721 719 * @retval None
bogdanm 85:024bf7f99721 720 */
Kojto 108:34e6b704fe68 721 #define ADC_CFGR_AWDCH(_CHANNEL_) \
<> 134:ad3be0349dc5 722 ((_CHANNEL_) << 26U)
bogdanm 85:024bf7f99721 723
bogdanm 85:024bf7f99721 724 /**
bogdanm 85:024bf7f99721 725 * @brief Enable ADC discontinuous conversion mode for regular group
Kojto 93:e188a91d3eaa 726 * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode.
bogdanm 85:024bf7f99721 727 * @retval None
bogdanm 85:024bf7f99721 728 */
Kojto 108:34e6b704fe68 729 #define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \
<> 134:ad3be0349dc5 730 ((_REG_DISCONTINUOUS_MODE_) << 16U)
bogdanm 85:024bf7f99721 731
bogdanm 85:024bf7f99721 732 /**
bogdanm 85:024bf7f99721 733 * @brief Enable the ADC auto off mode.
bogdanm 85:024bf7f99721 734 * @param _AUTOOFF_: Auto off bit enable or disable.
bogdanm 85:024bf7f99721 735 * @retval None
bogdanm 85:024bf7f99721 736 */
Kojto 108:34e6b704fe68 737 #define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \
<> 134:ad3be0349dc5 738 ((_AUTOOFF_) << 15U)
bogdanm 85:024bf7f99721 739
bogdanm 85:024bf7f99721 740 /**
bogdanm 85:024bf7f99721 741 * @brief Enable the ADC auto delay mode.
bogdanm 85:024bf7f99721 742 * @param _AUTOWAIT_: Auto delay bit enable or disable.
bogdanm 85:024bf7f99721 743 * @retval None
bogdanm 85:024bf7f99721 744 */
Kojto 108:34e6b704fe68 745 #define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \
<> 134:ad3be0349dc5 746 ((_AUTOWAIT_) << 14U)
bogdanm 85:024bf7f99721 747
bogdanm 85:024bf7f99721 748 /**
bogdanm 85:024bf7f99721 749 * @brief Enable ADC continuous conversion mode.
bogdanm 85:024bf7f99721 750 * @param _CONTINUOUS_MODE_: Continuous mode.
bogdanm 85:024bf7f99721 751 * @retval None
bogdanm 85:024bf7f99721 752 */
Kojto 108:34e6b704fe68 753 #define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \
<> 134:ad3be0349dc5 754 ((_CONTINUOUS_MODE_) << 13U)
bogdanm 85:024bf7f99721 755
bogdanm 85:024bf7f99721 756 /**
bogdanm 85:024bf7f99721 757 * @brief Enable ADC overrun mode.
bogdanm 85:024bf7f99721 758 * @param _OVERRUN_MODE_: Overrun mode.
bogdanm 85:024bf7f99721 759 * @retval Overun bit setting to be programmed into CFGR register
bogdanm 85:024bf7f99721 760 */
bogdanm 85:024bf7f99721 761 /* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */
Kojto 108:34e6b704fe68 762 /* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */
Kojto 108:34e6b704fe68 763 /* as the default case to be compliant with other STM32 devices. */
Kojto 108:34e6b704fe68 764 #define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \
Kojto 108:34e6b704fe68 765 ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \
bogdanm 85:024bf7f99721 766 )? (ADC_CFGR1_OVRMOD) : (0x00000000) \
bogdanm 85:024bf7f99721 767 )
bogdanm 85:024bf7f99721 768
bogdanm 85:024bf7f99721 769 /**
bogdanm 85:024bf7f99721 770 * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
bogdanm 85:024bf7f99721 771 * @param _SCAN_MODE_: Scan conversion mode.
bogdanm 85:024bf7f99721 772 * @retval None
bogdanm 85:024bf7f99721 773 */
Kojto 108:34e6b704fe68 774 /* Note: Scan mode set using this macro (instead of parameter direct set) */
Kojto 108:34e6b704fe68 775 /* due to different modes on other STM32 devices: to avoid any */
Kojto 108:34e6b704fe68 776 /* unwanted setting, the exact parameter corresponding to the device */
Kojto 108:34e6b704fe68 777 /* must be passed to this macro. */
Kojto 108:34e6b704fe68 778 #define ADC_SCANDIR(_SCAN_MODE_) \
bogdanm 85:024bf7f99721 779 ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \
bogdanm 85:024bf7f99721 780 )? (ADC_CFGR1_SCANDIR) : (0x00000000) \
bogdanm 85:024bf7f99721 781 )
Kojto 108:34e6b704fe68 782
bogdanm 85:024bf7f99721 783 /**
bogdanm 85:024bf7f99721 784 * @brief Enable the ADC DMA continuous request.
bogdanm 85:024bf7f99721 785 * @param _DMACONTREQ_MODE_: DMA continuous request mode.
bogdanm 85:024bf7f99721 786 * @retval None
bogdanm 85:024bf7f99721 787 */
Kojto 108:34e6b704fe68 788 #define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \
<> 134:ad3be0349dc5 789 ((_DMACONTREQ_MODE_) << 1U)
Kojto 93:e188a91d3eaa 790
bogdanm 85:024bf7f99721 791 /**
bogdanm 85:024bf7f99721 792 * @brief Configure the analog watchdog high threshold into register TR.
bogdanm 85:024bf7f99721 793 * @param _Threshold_: Threshold value
bogdanm 85:024bf7f99721 794 * @retval None
bogdanm 85:024bf7f99721 795 */
Kojto 108:34e6b704fe68 796 #define ADC_TRX_HIGHTHRESHOLD(_Threshold_) \
<> 134:ad3be0349dc5 797 ((_Threshold_) << 16U)
Kojto 108:34e6b704fe68 798
bogdanm 85:024bf7f99721 799 /**
bogdanm 85:024bf7f99721 800 * @brief Shift the AWD threshold in function of the selected ADC resolution.
bogdanm 85:024bf7f99721 801 * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
bogdanm 85:024bf7f99721 802 * If resolution 12 bits, no shift.
bogdanm 85:024bf7f99721 803 * If resolution 10 bits, shift of 2 ranks on the left.
bogdanm 85:024bf7f99721 804 * If resolution 8 bits, shift of 4 ranks on the left.
bogdanm 85:024bf7f99721 805 * If resolution 6 bits, shift of 6 ranks on the left.
bogdanm 85:024bf7f99721 806 * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
bogdanm 85:024bf7f99721 807 * @param __HANDLE__: ADC handle
bogdanm 85:024bf7f99721 808 * @param _Threshold_: Value to be shifted
bogdanm 85:024bf7f99721 809 * @retval None
bogdanm 85:024bf7f99721 810 */
Kojto 108:34e6b704fe68 811 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
<> 134:ad3be0349dc5 812 ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2))
Kojto 108:34e6b704fe68 813
Kojto 108:34e6b704fe68 814
Kojto 108:34e6b704fe68 815 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \
Kojto 108:34e6b704fe68 816 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
Kojto 108:34e6b704fe68 817 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) )
Kojto 108:34e6b704fe68 818
Kojto 108:34e6b704fe68 819 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
Kojto 108:34e6b704fe68 820 ((RESOLUTION) == ADC_RESOLUTION_10B) || \
Kojto 108:34e6b704fe68 821 ((RESOLUTION) == ADC_RESOLUTION_8B) || \
Kojto 108:34e6b704fe68 822 ((RESOLUTION) == ADC_RESOLUTION_6B) )
Kojto 108:34e6b704fe68 823
Kojto 108:34e6b704fe68 824 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
Kojto 108:34e6b704fe68 825 ((ALIGN) == ADC_DATAALIGN_LEFT) )
Kojto 108:34e6b704fe68 826
Kojto 108:34e6b704fe68 827 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \
Kojto 108:34e6b704fe68 828 ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD) )
Kojto 108:34e6b704fe68 829
Kojto 108:34e6b704fe68 830 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
Kojto 108:34e6b704fe68 831 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
Kojto 108:34e6b704fe68 832 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
Kojto 108:34e6b704fe68 833 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
Kojto 108:34e6b704fe68 834
Kojto 108:34e6b704fe68 835 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \
Kojto 108:34e6b704fe68 836 ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) || \
Kojto 108:34e6b704fe68 837 ((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV) )
Kojto 108:34e6b704fe68 838
Kojto 108:34e6b704fe68 839 #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \
Kojto 108:34e6b704fe68 840 ((OVR) == ADC_OVR_DATA_OVERWRITTEN) )
Kojto 108:34e6b704fe68 841
Kojto 108:34e6b704fe68 842 #define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \
Kojto 108:34e6b704fe68 843 ((WATCHDOG) == ADC_RANK_NONE) )
Kojto 108:34e6b704fe68 844
Kojto 108:34e6b704fe68 845 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
Kojto 108:34e6b704fe68 846 ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \
Kojto 108:34e6b704fe68 847 ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \
Kojto 108:34e6b704fe68 848 ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \
Kojto 108:34e6b704fe68 849 ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \
Kojto 108:34e6b704fe68 850 ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \
Kojto 108:34e6b704fe68 851 ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \
Kojto 108:34e6b704fe68 852 ((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
Kojto 108:34e6b704fe68 853
Kojto 108:34e6b704fe68 854 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
Kojto 108:34e6b704fe68 855 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
Kojto 108:34e6b704fe68 856 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) )
Kojto 108:34e6b704fe68 857
Kojto 108:34e6b704fe68 858 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
Kojto 108:34e6b704fe68 859 ((EVENT) == ADC_OVR_EVENT) )
Kojto 108:34e6b704fe68 860
Kojto 108:34e6b704fe68 861 /** @defgroup ADC_range_verification ADC range verification
Kojto 108:34e6b704fe68 862 * in function of ADC resolution selected (12, 10, 8 or 6 bits)
Kojto 108:34e6b704fe68 863 * @{
Kojto 108:34e6b704fe68 864 */
Kojto 108:34e6b704fe68 865 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
<> 134:ad3be0349dc5 866 ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= (0x0FFFU))) || \
<> 134:ad3be0349dc5 867 (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= (0x03FFU))) || \
<> 134:ad3be0349dc5 868 (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= (0x00FFU))) || \
<> 134:ad3be0349dc5 869 (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= (0x003FU))) )
Kojto 108:34e6b704fe68 870 /**
Kojto 108:34e6b704fe68 871 * @}
Kojto 108:34e6b704fe68 872 */
Kojto 108:34e6b704fe68 873
Kojto 108:34e6b704fe68 874 /** @defgroup ADC_regular_rank_verification ADC regular rank verification
Kojto 108:34e6b704fe68 875 * @{
Kojto 108:34e6b704fe68 876 */
<> 134:ad3be0349dc5 877 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= (1U)) && ((RANK) <= (16U)))
Kojto 108:34e6b704fe68 878 /**
Kojto 108:34e6b704fe68 879 * @}
Kojto 108:34e6b704fe68 880 */
bogdanm 85:024bf7f99721 881
bogdanm 85:024bf7f99721 882 /**
bogdanm 85:024bf7f99721 883 * @}
bogdanm 85:024bf7f99721 884 */
bogdanm 85:024bf7f99721 885
bogdanm 85:024bf7f99721 886 /* Include ADC HAL Extension module */
bogdanm 85:024bf7f99721 887 #include "stm32f0xx_hal_adc_ex.h"
bogdanm 85:024bf7f99721 888
bogdanm 85:024bf7f99721 889 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 890 /** @addtogroup ADC_Exported_Functions
bogdanm 92:4fc01daae5a5 891 * @{
bogdanm 92:4fc01daae5a5 892 */
bogdanm 92:4fc01daae5a5 893
bogdanm 92:4fc01daae5a5 894 /** @addtogroup ADC_Exported_Functions_Group1
bogdanm 92:4fc01daae5a5 895 * @{
bogdanm 92:4fc01daae5a5 896 */
bogdanm 92:4fc01daae5a5 897
bogdanm 92:4fc01daae5a5 898
bogdanm 85:024bf7f99721 899 /* Initialization and de-initialization functions **********************************/
bogdanm 85:024bf7f99721 900 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
bogdanm 85:024bf7f99721 901 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
bogdanm 85:024bf7f99721 902 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
bogdanm 85:024bf7f99721 903 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
bogdanm 92:4fc01daae5a5 904 /**
bogdanm 92:4fc01daae5a5 905 * @}
bogdanm 92:4fc01daae5a5 906 */
bogdanm 85:024bf7f99721 907
bogdanm 85:024bf7f99721 908 /* IO operation functions *****************************************************/
bogdanm 92:4fc01daae5a5 909
bogdanm 92:4fc01daae5a5 910 /** @addtogroup ADC_Exported_Functions_Group2
bogdanm 92:4fc01daae5a5 911 * @{
bogdanm 92:4fc01daae5a5 912 */
bogdanm 92:4fc01daae5a5 913
bogdanm 92:4fc01daae5a5 914
bogdanm 85:024bf7f99721 915 /* Blocking mode: Polling */
bogdanm 85:024bf7f99721 916 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
bogdanm 85:024bf7f99721 917 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
bogdanm 85:024bf7f99721 918 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
bogdanm 85:024bf7f99721 919 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
bogdanm 85:024bf7f99721 920
bogdanm 85:024bf7f99721 921 /* Non-blocking mode: Interruption */
bogdanm 85:024bf7f99721 922 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
bogdanm 85:024bf7f99721 923 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
bogdanm 85:024bf7f99721 924
bogdanm 85:024bf7f99721 925 /* Non-blocking mode: DMA */
bogdanm 85:024bf7f99721 926 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
bogdanm 85:024bf7f99721 927 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
bogdanm 85:024bf7f99721 928
bogdanm 85:024bf7f99721 929 /* ADC retrieve conversion value intended to be used with polling or interruption */
bogdanm 85:024bf7f99721 930 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
bogdanm 85:024bf7f99721 931
bogdanm 85:024bf7f99721 932 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
bogdanm 85:024bf7f99721 933 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
bogdanm 85:024bf7f99721 934 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
bogdanm 85:024bf7f99721 935 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
bogdanm 85:024bf7f99721 936 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
bogdanm 85:024bf7f99721 937 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
bogdanm 92:4fc01daae5a5 938 /**
bogdanm 92:4fc01daae5a5 939 * @}
bogdanm 92:4fc01daae5a5 940 */
bogdanm 92:4fc01daae5a5 941
bogdanm 85:024bf7f99721 942
bogdanm 85:024bf7f99721 943 /* Peripheral Control functions ***********************************************/
bogdanm 92:4fc01daae5a5 944 /** @addtogroup ADC_Exported_Functions_Group3
bogdanm 92:4fc01daae5a5 945 * @{
bogdanm 92:4fc01daae5a5 946 */
bogdanm 85:024bf7f99721 947 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
bogdanm 85:024bf7f99721 948 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
bogdanm 92:4fc01daae5a5 949 /**
bogdanm 92:4fc01daae5a5 950 * @}
bogdanm 92:4fc01daae5a5 951 */
bogdanm 92:4fc01daae5a5 952
bogdanm 85:024bf7f99721 953
bogdanm 85:024bf7f99721 954 /* Peripheral State functions *************************************************/
bogdanm 92:4fc01daae5a5 955 /** @addtogroup ADC_Exported_Functions_Group4
bogdanm 92:4fc01daae5a5 956 * @{
bogdanm 92:4fc01daae5a5 957 */
Kojto 108:34e6b704fe68 958 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
bogdanm 85:024bf7f99721 959 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
bogdanm 92:4fc01daae5a5 960 /**
bogdanm 92:4fc01daae5a5 961 * @}
bogdanm 92:4fc01daae5a5 962 */
bogdanm 92:4fc01daae5a5 963
bogdanm 92:4fc01daae5a5 964
bogdanm 92:4fc01daae5a5 965 /**
bogdanm 92:4fc01daae5a5 966 * @}
bogdanm 92:4fc01daae5a5 967 */
bogdanm 92:4fc01daae5a5 968
bogdanm 85:024bf7f99721 969
bogdanm 85:024bf7f99721 970 /**
bogdanm 85:024bf7f99721 971 * @}
bogdanm 85:024bf7f99721 972 */
bogdanm 85:024bf7f99721 973
bogdanm 85:024bf7f99721 974 /**
bogdanm 85:024bf7f99721 975 * @}
bogdanm 85:024bf7f99721 976 */
bogdanm 85:024bf7f99721 977
bogdanm 85:024bf7f99721 978 #ifdef __cplusplus
bogdanm 85:024bf7f99721 979 }
bogdanm 85:024bf7f99721 980 #endif
bogdanm 85:024bf7f99721 981
bogdanm 85:024bf7f99721 982
bogdanm 85:024bf7f99721 983 #endif /* __STM32F0xx_HAL_ADC_H */
bogdanm 85:024bf7f99721 984
bogdanm 85:024bf7f99721 985 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bogdanm 92:4fc01daae5a5 986