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TARGET_NUCLEO_F030R8/TARGET_STM/TARGET_STM32F0/device/stm32_hal_legacy.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:30:20 2017 +0100
Revision:
143:86740a56073b
Parent:
134:ad3be0349dc5 
Release 143 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32_hal_legacy.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 134:ad3be0349dc5 5 * @version V1.5.0
<> 134:ad3be0349dc5 6 * @date 04-November-2016
<> 128:9bcdf88f62b0 7 * @brief This file contains aliases definition for the STM32Cube HAL constants
<> 128:9bcdf88f62b0 8 * macros and functions maintained for legacy purpose.
<> 128:9bcdf88f62b0 9 ******************************************************************************
<> 128:9bcdf88f62b0 10 * @attention
<> 128:9bcdf88f62b0 11 *
<> 128:9bcdf88f62b0 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 13 *
<> 128:9bcdf88f62b0 14 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 15 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 16 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 17 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 19 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 20 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 22 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 23 * without specific prior written permission.
<> 128:9bcdf88f62b0 24 *
<> 128:9bcdf88f62b0 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 35 *
<> 128:9bcdf88f62b0 36 ******************************************************************************
<> 128:9bcdf88f62b0 37 */
<> 128:9bcdf88f62b0 38
<> 128:9bcdf88f62b0 39 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 40 #ifndef __STM32_HAL_LEGACY
<> 128:9bcdf88f62b0 41 #define __STM32_HAL_LEGACY
<> 128:9bcdf88f62b0 42
<> 128:9bcdf88f62b0 43 #ifdef __cplusplus
<> 128:9bcdf88f62b0 44 extern "C" {
<> 128:9bcdf88f62b0 45 #endif
<> 128:9bcdf88f62b0 46
<> 128:9bcdf88f62b0 47 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 48 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 49 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 50
<> 128:9bcdf88f62b0 51 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 52 * @{
<> 128:9bcdf88f62b0 53 */
<> 128:9bcdf88f62b0 54 #define AES_FLAG_RDERR CRYP_FLAG_RDERR
<> 128:9bcdf88f62b0 55 #define AES_FLAG_WRERR CRYP_FLAG_WRERR
<> 128:9bcdf88f62b0 56 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
<> 128:9bcdf88f62b0 57 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
<> 128:9bcdf88f62b0 58 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
<> 128:9bcdf88f62b0 59
<> 128:9bcdf88f62b0 60 /**
<> 128:9bcdf88f62b0 61 * @}
<> 128:9bcdf88f62b0 62 */
<> 128:9bcdf88f62b0 63
<> 128:9bcdf88f62b0 64 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 65 * @{
<> 128:9bcdf88f62b0 66 */
<> 128:9bcdf88f62b0 67 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B
<> 128:9bcdf88f62b0 68 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B
<> 128:9bcdf88f62b0 69 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B
<> 128:9bcdf88f62b0 70 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B
<> 128:9bcdf88f62b0 71 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
<> 128:9bcdf88f62b0 72 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
<> 128:9bcdf88f62b0 73 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
<> 128:9bcdf88f62b0 74 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
<> 128:9bcdf88f62b0 75 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
<> 128:9bcdf88f62b0 76 #define REGULAR_GROUP ADC_REGULAR_GROUP
<> 128:9bcdf88f62b0 77 #define INJECTED_GROUP ADC_INJECTED_GROUP
<> 128:9bcdf88f62b0 78 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
<> 128:9bcdf88f62b0 79 #define AWD_EVENT ADC_AWD_EVENT
<> 128:9bcdf88f62b0 80 #define AWD1_EVENT ADC_AWD1_EVENT
<> 128:9bcdf88f62b0 81 #define AWD2_EVENT ADC_AWD2_EVENT
<> 128:9bcdf88f62b0 82 #define AWD3_EVENT ADC_AWD3_EVENT
<> 128:9bcdf88f62b0 83 #define OVR_EVENT ADC_OVR_EVENT
<> 128:9bcdf88f62b0 84 #define JQOVF_EVENT ADC_JQOVF_EVENT
<> 128:9bcdf88f62b0 85 #define ALL_CHANNELS ADC_ALL_CHANNELS
<> 128:9bcdf88f62b0 86 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
<> 128:9bcdf88f62b0 87 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
<> 128:9bcdf88f62b0 88 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
<> 128:9bcdf88f62b0 89 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
<> 128:9bcdf88f62b0 90 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
<> 128:9bcdf88f62b0 91 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
<> 128:9bcdf88f62b0 92 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
<> 128:9bcdf88f62b0 93 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
<> 128:9bcdf88f62b0 94 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
<> 128:9bcdf88f62b0 95 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
<> 128:9bcdf88f62b0 96 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
<> 128:9bcdf88f62b0 97 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
<> 128:9bcdf88f62b0 98 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
<> 128:9bcdf88f62b0 99 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
<> 128:9bcdf88f62b0 100 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
<> 128:9bcdf88f62b0 101 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
<> 128:9bcdf88f62b0 102 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
<> 128:9bcdf88f62b0 103 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
<> 128:9bcdf88f62b0 104 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
<> 128:9bcdf88f62b0 105 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
<> 128:9bcdf88f62b0 106 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
<> 128:9bcdf88f62b0 107
<> 128:9bcdf88f62b0 108 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
<> 128:9bcdf88f62b0 109 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
<> 128:9bcdf88f62b0 110 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
<> 128:9bcdf88f62b0 111 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
<> 128:9bcdf88f62b0 112 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
<> 128:9bcdf88f62b0 113 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
<> 128:9bcdf88f62b0 114 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
<> 128:9bcdf88f62b0 115 /**
<> 128:9bcdf88f62b0 116 * @}
<> 128:9bcdf88f62b0 117 */
<> 128:9bcdf88f62b0 118
<> 128:9bcdf88f62b0 119 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 120 * @{
<> 128:9bcdf88f62b0 121 */
<> 128:9bcdf88f62b0 122
<> 128:9bcdf88f62b0 123 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
<> 128:9bcdf88f62b0 124
<> 128:9bcdf88f62b0 125 /**
<> 128:9bcdf88f62b0 126 * @}
<> 128:9bcdf88f62b0 127 */
<> 128:9bcdf88f62b0 128
<> 128:9bcdf88f62b0 129 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 130 * @{
<> 128:9bcdf88f62b0 131 */
<> 128:9bcdf88f62b0 132 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
<> 128:9bcdf88f62b0 133 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
<> 128:9bcdf88f62b0 134 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
<> 128:9bcdf88f62b0 135 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
<> 128:9bcdf88f62b0 136 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
<> 128:9bcdf88f62b0 137 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
<> 128:9bcdf88f62b0 138 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
<> 128:9bcdf88f62b0 139 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
<> 128:9bcdf88f62b0 140 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
<> 134:ad3be0349dc5 141 #define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */
<> 128:9bcdf88f62b0 142 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
<> 128:9bcdf88f62b0 143 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 128:9bcdf88f62b0 144 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
<> 128:9bcdf88f62b0 145 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
<> 128:9bcdf88f62b0 146 #endif /* STM32F373xC || STM32F378xx */
<> 128:9bcdf88f62b0 147
<> 128:9bcdf88f62b0 148 #if defined(STM32L0) || defined(STM32L4)
<> 128:9bcdf88f62b0 149 #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
<> 128:9bcdf88f62b0 150
<> 128:9bcdf88f62b0 151 #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
<> 128:9bcdf88f62b0 152 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
<> 128:9bcdf88f62b0 153 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
<> 128:9bcdf88f62b0 154 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
<> 128:9bcdf88f62b0 155 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
<> 128:9bcdf88f62b0 156 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
<> 128:9bcdf88f62b0 157
<> 128:9bcdf88f62b0 158 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
<> 128:9bcdf88f62b0 159 #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
<> 128:9bcdf88f62b0 160 #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
<> 128:9bcdf88f62b0 161 #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
<> 128:9bcdf88f62b0 162 #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
<> 128:9bcdf88f62b0 163 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
<> 128:9bcdf88f62b0 164 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
<> 128:9bcdf88f62b0 165 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
<> 128:9bcdf88f62b0 166 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
<> 128:9bcdf88f62b0 167 #if defined(STM32L0)
<> 128:9bcdf88f62b0 168 /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
<> 128:9bcdf88f62b0 169 /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
<> 128:9bcdf88f62b0 170 /* to the second dedicated IO (only for COMP2). */
<> 128:9bcdf88f62b0 171 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
<> 128:9bcdf88f62b0 172 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
<> 128:9bcdf88f62b0 173 #else
<> 128:9bcdf88f62b0 174 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
<> 128:9bcdf88f62b0 175 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
<> 128:9bcdf88f62b0 176 #endif
<> 128:9bcdf88f62b0 177 #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
<> 128:9bcdf88f62b0 178 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
<> 128:9bcdf88f62b0 179
<> 128:9bcdf88f62b0 180 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
<> 128:9bcdf88f62b0 181 #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
<> 128:9bcdf88f62b0 182
<> 128:9bcdf88f62b0 183 /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
<> 128:9bcdf88f62b0 184 /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
<> 128:9bcdf88f62b0 185 #if defined(COMP_CSR_LOCK)
<> 128:9bcdf88f62b0 186 #define COMP_FLAG_LOCK COMP_CSR_LOCK
<> 128:9bcdf88f62b0 187 #elif defined(COMP_CSR_COMP1LOCK)
<> 128:9bcdf88f62b0 188 #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
<> 128:9bcdf88f62b0 189 #elif defined(COMP_CSR_COMPxLOCK)
<> 128:9bcdf88f62b0 190 #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
<> 128:9bcdf88f62b0 191 #endif
<> 128:9bcdf88f62b0 192
<> 128:9bcdf88f62b0 193 #if defined(STM32L4)
<> 128:9bcdf88f62b0 194 #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
<> 128:9bcdf88f62b0 195 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
<> 128:9bcdf88f62b0 196 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
<> 128:9bcdf88f62b0 197 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
<> 128:9bcdf88f62b0 198 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
<> 128:9bcdf88f62b0 199 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
<> 128:9bcdf88f62b0 200 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
<> 128:9bcdf88f62b0 201 #endif
<> 128:9bcdf88f62b0 202
<> 128:9bcdf88f62b0 203 #if defined(STM32L0)
<> 128:9bcdf88f62b0 204 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
<> 128:9bcdf88f62b0 205 #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
<> 128:9bcdf88f62b0 206 #else
<> 128:9bcdf88f62b0 207 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
<> 128:9bcdf88f62b0 208 #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
<> 128:9bcdf88f62b0 209 #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
<> 128:9bcdf88f62b0 210 #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
<> 128:9bcdf88f62b0 211 #endif
<> 128:9bcdf88f62b0 212
<> 128:9bcdf88f62b0 213 #endif
<> 128:9bcdf88f62b0 214 /**
<> 128:9bcdf88f62b0 215 * @}
<> 128:9bcdf88f62b0 216 */
<> 128:9bcdf88f62b0 217
<> 128:9bcdf88f62b0 218 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 219 * @{
<> 128:9bcdf88f62b0 220 */
<> 128:9bcdf88f62b0 221 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
<> 128:9bcdf88f62b0 222 /**
<> 128:9bcdf88f62b0 223 * @}
<> 128:9bcdf88f62b0 224 */
<> 128:9bcdf88f62b0 225
<> 128:9bcdf88f62b0 226 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 227 * @{
<> 128:9bcdf88f62b0 228 */
<> 128:9bcdf88f62b0 229
<> 128:9bcdf88f62b0 230 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
<> 128:9bcdf88f62b0 231 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
<> 128:9bcdf88f62b0 232
<> 128:9bcdf88f62b0 233 /**
<> 128:9bcdf88f62b0 234 * @}
<> 128:9bcdf88f62b0 235 */
<> 128:9bcdf88f62b0 236
<> 128:9bcdf88f62b0 237 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 238 * @{
<> 128:9bcdf88f62b0 239 */
<> 128:9bcdf88f62b0 240
<> 128:9bcdf88f62b0 241 #define DAC1_CHANNEL_1 DAC_CHANNEL_1
<> 128:9bcdf88f62b0 242 #define DAC1_CHANNEL_2 DAC_CHANNEL_2
<> 128:9bcdf88f62b0 243 #define DAC2_CHANNEL_1 DAC_CHANNEL_1
<> 128:9bcdf88f62b0 244 #define DAC_WAVE_NONE ((uint32_t)0x00000000U)
<> 128:9bcdf88f62b0 245 #define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
<> 128:9bcdf88f62b0 246 #define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
<> 128:9bcdf88f62b0 247 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
<> 128:9bcdf88f62b0 248 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
<> 128:9bcdf88f62b0 249 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
<> 128:9bcdf88f62b0 250
<> 128:9bcdf88f62b0 251 /**
<> 128:9bcdf88f62b0 252 * @}
<> 128:9bcdf88f62b0 253 */
<> 128:9bcdf88f62b0 254
<> 128:9bcdf88f62b0 255 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 256 * @{
<> 128:9bcdf88f62b0 257 */
<> 128:9bcdf88f62b0 258 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
<> 128:9bcdf88f62b0 259 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
<> 128:9bcdf88f62b0 260 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
<> 128:9bcdf88f62b0 261 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
<> 128:9bcdf88f62b0 262 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
<> 128:9bcdf88f62b0 263 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
<> 128:9bcdf88f62b0 264 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
<> 128:9bcdf88f62b0 265 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
<> 128:9bcdf88f62b0 266 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
<> 128:9bcdf88f62b0 267 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
<> 128:9bcdf88f62b0 268 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
<> 128:9bcdf88f62b0 269 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
<> 128:9bcdf88f62b0 270 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
<> 128:9bcdf88f62b0 271 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
<> 128:9bcdf88f62b0 272 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
<> 128:9bcdf88f62b0 273
<> 128:9bcdf88f62b0 274 #define IS_HAL_REMAPDMA IS_DMA_REMAP
<> 128:9bcdf88f62b0 275 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
<> 128:9bcdf88f62b0 276 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
<> 128:9bcdf88f62b0 277
<> 128:9bcdf88f62b0 278
<> 128:9bcdf88f62b0 279
<> 128:9bcdf88f62b0 280 /**
<> 128:9bcdf88f62b0 281 * @}
<> 128:9bcdf88f62b0 282 */
<> 128:9bcdf88f62b0 283
<> 128:9bcdf88f62b0 284 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 285 * @{
<> 128:9bcdf88f62b0 286 */
<> 128:9bcdf88f62b0 287
<> 128:9bcdf88f62b0 288 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
<> 128:9bcdf88f62b0 289 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
<> 128:9bcdf88f62b0 290 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
<> 128:9bcdf88f62b0 291 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
<> 128:9bcdf88f62b0 292 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
<> 128:9bcdf88f62b0 293 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
<> 128:9bcdf88f62b0 294 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
<> 128:9bcdf88f62b0 295 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
<> 128:9bcdf88f62b0 296 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
<> 128:9bcdf88f62b0 297 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
<> 128:9bcdf88f62b0 298 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
<> 128:9bcdf88f62b0 299 #define OBEX_PCROP OPTIONBYTE_PCROP
<> 128:9bcdf88f62b0 300 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
<> 128:9bcdf88f62b0 301 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
<> 128:9bcdf88f62b0 302 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
<> 128:9bcdf88f62b0 303 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
<> 128:9bcdf88f62b0 304 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
<> 128:9bcdf88f62b0 305 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
<> 128:9bcdf88f62b0 306 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
<> 128:9bcdf88f62b0 307 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
<> 128:9bcdf88f62b0 308 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
<> 128:9bcdf88f62b0 309 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
<> 128:9bcdf88f62b0 310 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
<> 128:9bcdf88f62b0 311 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
<> 128:9bcdf88f62b0 312 #define PAGESIZE FLASH_PAGE_SIZE
<> 128:9bcdf88f62b0 313 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
<> 128:9bcdf88f62b0 314 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
<> 128:9bcdf88f62b0 315 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
<> 128:9bcdf88f62b0 316 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
<> 128:9bcdf88f62b0 317 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
<> 128:9bcdf88f62b0 318 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
<> 128:9bcdf88f62b0 319 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
<> 128:9bcdf88f62b0 320 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
<> 128:9bcdf88f62b0 321 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
<> 128:9bcdf88f62b0 322 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
<> 128:9bcdf88f62b0 323 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
<> 128:9bcdf88f62b0 324 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
<> 128:9bcdf88f62b0 325 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
<> 128:9bcdf88f62b0 326 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
<> 128:9bcdf88f62b0 327 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
<> 128:9bcdf88f62b0 328 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
<> 128:9bcdf88f62b0 329 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
<> 128:9bcdf88f62b0 330 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
<> 128:9bcdf88f62b0 331 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
<> 128:9bcdf88f62b0 332 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
<> 128:9bcdf88f62b0 333 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
<> 128:9bcdf88f62b0 334 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
<> 128:9bcdf88f62b0 335 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
<> 128:9bcdf88f62b0 336 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
<> 128:9bcdf88f62b0 337 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
<> 128:9bcdf88f62b0 338 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
<> 128:9bcdf88f62b0 339 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
<> 128:9bcdf88f62b0 340 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
<> 128:9bcdf88f62b0 341 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
<> 128:9bcdf88f62b0 342 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
<> 128:9bcdf88f62b0 343 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
<> 128:9bcdf88f62b0 344 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
<> 128:9bcdf88f62b0 345 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
<> 128:9bcdf88f62b0 346 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
<> 128:9bcdf88f62b0 347 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
<> 128:9bcdf88f62b0 348 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
<> 128:9bcdf88f62b0 349 #define OB_WDG_SW OB_IWDG_SW
<> 128:9bcdf88f62b0 350 #define OB_WDG_HW OB_IWDG_HW
<> 128:9bcdf88f62b0 351 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
<> 128:9bcdf88f62b0 352 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
<> 128:9bcdf88f62b0 353 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
<> 128:9bcdf88f62b0 354 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
<> 128:9bcdf88f62b0 355 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
<> 128:9bcdf88f62b0 356 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
<> 128:9bcdf88f62b0 357 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
<> 128:9bcdf88f62b0 358 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
<> 134:ad3be0349dc5 359
<> 128:9bcdf88f62b0 360 /**
<> 128:9bcdf88f62b0 361 * @}
<> 128:9bcdf88f62b0 362 */
<> 128:9bcdf88f62b0 363
<> 128:9bcdf88f62b0 364 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 365 * @{
<> 128:9bcdf88f62b0 366 */
<> 128:9bcdf88f62b0 367
<> 128:9bcdf88f62b0 368 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
<> 128:9bcdf88f62b0 369 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
<> 128:9bcdf88f62b0 370 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
<> 128:9bcdf88f62b0 371 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
<> 128:9bcdf88f62b0 372 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
<> 128:9bcdf88f62b0 373 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
<> 128:9bcdf88f62b0 374 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
<> 128:9bcdf88f62b0 375 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
<> 128:9bcdf88f62b0 376 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
<> 128:9bcdf88f62b0 377 /**
<> 128:9bcdf88f62b0 378 * @}
<> 128:9bcdf88f62b0 379 */
<> 128:9bcdf88f62b0 380
<> 128:9bcdf88f62b0 381
<> 128:9bcdf88f62b0 382 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
<> 128:9bcdf88f62b0 383 * @{
<> 128:9bcdf88f62b0 384 */
<> 128:9bcdf88f62b0 385 #if defined(STM32L4) || defined(STM32F7)
<> 128:9bcdf88f62b0 386 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
<> 128:9bcdf88f62b0 387 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
<> 128:9bcdf88f62b0 388 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
<> 128:9bcdf88f62b0 389 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
<> 128:9bcdf88f62b0 390 #else
<> 128:9bcdf88f62b0 391 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
<> 128:9bcdf88f62b0 392 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
<> 128:9bcdf88f62b0 393 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
<> 128:9bcdf88f62b0 394 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
<> 128:9bcdf88f62b0 395 #endif
<> 128:9bcdf88f62b0 396 /**
<> 128:9bcdf88f62b0 397 * @}
<> 128:9bcdf88f62b0 398 */
<> 128:9bcdf88f62b0 399
<> 128:9bcdf88f62b0 400 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 401 * @{
<> 128:9bcdf88f62b0 402 */
<> 128:9bcdf88f62b0 403
<> 128:9bcdf88f62b0 404 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
<> 128:9bcdf88f62b0 405 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
<> 128:9bcdf88f62b0 406 /**
<> 128:9bcdf88f62b0 407 * @}
<> 128:9bcdf88f62b0 408 */
<> 128:9bcdf88f62b0 409
<> 128:9bcdf88f62b0 410 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 411 * @{
<> 128:9bcdf88f62b0 412 */
<> 128:9bcdf88f62b0 413 #define GET_GPIO_SOURCE GPIO_GET_INDEX
<> 128:9bcdf88f62b0 414 #define GET_GPIO_INDEX GPIO_GET_INDEX
<> 128:9bcdf88f62b0 415
<> 128:9bcdf88f62b0 416 #if defined(STM32F4)
<> 128:9bcdf88f62b0 417 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO
<> 128:9bcdf88f62b0 418 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
<> 128:9bcdf88f62b0 419 #endif
<> 128:9bcdf88f62b0 420
<> 128:9bcdf88f62b0 421 #if defined(STM32F7)
<> 128:9bcdf88f62b0 422 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
<> 128:9bcdf88f62b0 423 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
<> 128:9bcdf88f62b0 424 #endif
<> 128:9bcdf88f62b0 425
<> 128:9bcdf88f62b0 426 #if defined(STM32L4)
<> 128:9bcdf88f62b0 427 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
<> 128:9bcdf88f62b0 428 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
<> 128:9bcdf88f62b0 429 #endif
<> 128:9bcdf88f62b0 430
<> 128:9bcdf88f62b0 431 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
<> 128:9bcdf88f62b0 432 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
<> 128:9bcdf88f62b0 433 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
<> 128:9bcdf88f62b0 434
<> 128:9bcdf88f62b0 435 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
<> 128:9bcdf88f62b0 436 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
<> 128:9bcdf88f62b0 437 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
<> 128:9bcdf88f62b0 438 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
<> 128:9bcdf88f62b0 439 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
<> 128:9bcdf88f62b0 440 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
<> 128:9bcdf88f62b0 441
<> 128:9bcdf88f62b0 442 #if defined(STM32L1)
<> 128:9bcdf88f62b0 443 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
<> 128:9bcdf88f62b0 444 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
<> 128:9bcdf88f62b0 445 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
<> 128:9bcdf88f62b0 446 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
<> 128:9bcdf88f62b0 447 #endif /* STM32L1 */
<> 128:9bcdf88f62b0 448
<> 128:9bcdf88f62b0 449 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
<> 128:9bcdf88f62b0 450 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
<> 128:9bcdf88f62b0 451 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
<> 128:9bcdf88f62b0 452 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
<> 128:9bcdf88f62b0 453 #endif /* STM32F0 || STM32F3 || STM32F1 */
<> 128:9bcdf88f62b0 454
<> 128:9bcdf88f62b0 455 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
<> 128:9bcdf88f62b0 456 /**
<> 128:9bcdf88f62b0 457 * @}
<> 128:9bcdf88f62b0 458 */
<> 128:9bcdf88f62b0 459
<> 128:9bcdf88f62b0 460 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 461 * @{
<> 128:9bcdf88f62b0 462 */
<> 128:9bcdf88f62b0 463 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
<> 128:9bcdf88f62b0 464 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
<> 128:9bcdf88f62b0 465 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
<> 128:9bcdf88f62b0 466 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
<> 128:9bcdf88f62b0 467 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
<> 128:9bcdf88f62b0 468 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
<> 128:9bcdf88f62b0 469 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
<> 128:9bcdf88f62b0 470 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
<> 128:9bcdf88f62b0 471 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
<> 128:9bcdf88f62b0 472
<> 128:9bcdf88f62b0 473 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
<> 128:9bcdf88f62b0 474 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
<> 128:9bcdf88f62b0 475 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
<> 128:9bcdf88f62b0 476 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
<> 128:9bcdf88f62b0 477 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
<> 128:9bcdf88f62b0 478 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
<> 128:9bcdf88f62b0 479 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
<> 128:9bcdf88f62b0 480 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
<> 128:9bcdf88f62b0 481 /**
<> 128:9bcdf88f62b0 482 * @}
<> 128:9bcdf88f62b0 483 */
<> 128:9bcdf88f62b0 484
<> 128:9bcdf88f62b0 485 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 486 * @{
<> 128:9bcdf88f62b0 487 */
<> 128:9bcdf88f62b0 488 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
<> 128:9bcdf88f62b0 489 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
<> 128:9bcdf88f62b0 490 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
<> 128:9bcdf88f62b0 491 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
<> 128:9bcdf88f62b0 492 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
<> 128:9bcdf88f62b0 493 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
<> 128:9bcdf88f62b0 494 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
<> 128:9bcdf88f62b0 495 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
<> 128:9bcdf88f62b0 496 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
<> 128:9bcdf88f62b0 497 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
<> 128:9bcdf88f62b0 498 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
<> 128:9bcdf88f62b0 499 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
<> 128:9bcdf88f62b0 500 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
<> 128:9bcdf88f62b0 501 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
<> 128:9bcdf88f62b0 502 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
<> 128:9bcdf88f62b0 503 #endif
<> 128:9bcdf88f62b0 504 /**
<> 128:9bcdf88f62b0 505 * @}
<> 128:9bcdf88f62b0 506 */
<> 128:9bcdf88f62b0 507
<> 128:9bcdf88f62b0 508 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 509 * @{
<> 128:9bcdf88f62b0 510 */
<> 128:9bcdf88f62b0 511 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
<> 128:9bcdf88f62b0 512 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
<> 128:9bcdf88f62b0 513
<> 128:9bcdf88f62b0 514 /**
<> 128:9bcdf88f62b0 515 * @}
<> 128:9bcdf88f62b0 516 */
<> 128:9bcdf88f62b0 517
<> 128:9bcdf88f62b0 518 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 519 * @{
<> 128:9bcdf88f62b0 520 */
<> 128:9bcdf88f62b0 521 #define KR_KEY_RELOAD IWDG_KEY_RELOAD
<> 128:9bcdf88f62b0 522 #define KR_KEY_ENABLE IWDG_KEY_ENABLE
<> 128:9bcdf88f62b0 523 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
<> 128:9bcdf88f62b0 524 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
<> 128:9bcdf88f62b0 525 /**
<> 128:9bcdf88f62b0 526 * @}
<> 128:9bcdf88f62b0 527 */
<> 128:9bcdf88f62b0 528
<> 128:9bcdf88f62b0 529 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 530 * @{
<> 128:9bcdf88f62b0 531 */
<> 128:9bcdf88f62b0 532
<> 128:9bcdf88f62b0 533 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
<> 128:9bcdf88f62b0 534 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
<> 128:9bcdf88f62b0 535 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
<> 128:9bcdf88f62b0 536 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
<> 128:9bcdf88f62b0 537
<> 128:9bcdf88f62b0 538 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
<> 128:9bcdf88f62b0 539 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
<> 128:9bcdf88f62b0 540 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
<> 128:9bcdf88f62b0 541
<> 128:9bcdf88f62b0 542 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
<> 128:9bcdf88f62b0 543 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
<> 128:9bcdf88f62b0 544 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
<> 128:9bcdf88f62b0 545 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
<> 128:9bcdf88f62b0 546
<> 128:9bcdf88f62b0 547 /* The following 3 definition have also been present in a temporary version of lptim.h */
<> 128:9bcdf88f62b0 548 /* They need to be renamed also to the right name, just in case */
<> 128:9bcdf88f62b0 549 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
<> 128:9bcdf88f62b0 550 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
<> 128:9bcdf88f62b0 551 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
<> 128:9bcdf88f62b0 552
<> 128:9bcdf88f62b0 553 /**
<> 128:9bcdf88f62b0 554 * @}
<> 128:9bcdf88f62b0 555 */
<> 128:9bcdf88f62b0 556
<> 128:9bcdf88f62b0 557 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 558 * @{
<> 128:9bcdf88f62b0 559 */
<> 128:9bcdf88f62b0 560 #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
<> 128:9bcdf88f62b0 561 #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
<> 128:9bcdf88f62b0 562 #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
<> 128:9bcdf88f62b0 563 #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
<> 128:9bcdf88f62b0 564
<> 128:9bcdf88f62b0 565 #define NAND_AddressTypedef NAND_AddressTypeDef
<> 128:9bcdf88f62b0 566
<> 128:9bcdf88f62b0 567 #define __ARRAY_ADDRESS ARRAY_ADDRESS
<> 128:9bcdf88f62b0 568 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
<> 128:9bcdf88f62b0 569 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
<> 128:9bcdf88f62b0 570 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
<> 128:9bcdf88f62b0 571 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
<> 128:9bcdf88f62b0 572 /**
<> 128:9bcdf88f62b0 573 * @}
<> 128:9bcdf88f62b0 574 */
<> 128:9bcdf88f62b0 575
<> 128:9bcdf88f62b0 576 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 577 * @{
<> 128:9bcdf88f62b0 578 */
<> 128:9bcdf88f62b0 579 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef
<> 128:9bcdf88f62b0 580 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
<> 128:9bcdf88f62b0 581 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING
<> 128:9bcdf88f62b0 582 #define NOR_ERROR HAL_NOR_STATUS_ERROR
<> 128:9bcdf88f62b0 583 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
<> 128:9bcdf88f62b0 584
<> 128:9bcdf88f62b0 585 #define __NOR_WRITE NOR_WRITE
<> 128:9bcdf88f62b0 586 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
<> 128:9bcdf88f62b0 587 /**
<> 128:9bcdf88f62b0 588 * @}
<> 128:9bcdf88f62b0 589 */
<> 128:9bcdf88f62b0 590
<> 128:9bcdf88f62b0 591 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 592 * @{
<> 128:9bcdf88f62b0 593 */
<> 128:9bcdf88f62b0 594
<> 128:9bcdf88f62b0 595 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
<> 128:9bcdf88f62b0 596 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
<> 128:9bcdf88f62b0 597 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
<> 128:9bcdf88f62b0 598 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
<> 128:9bcdf88f62b0 599
<> 128:9bcdf88f62b0 600 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
<> 128:9bcdf88f62b0 601 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
<> 128:9bcdf88f62b0 602 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
<> 128:9bcdf88f62b0 603 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
<> 128:9bcdf88f62b0 604
<> 128:9bcdf88f62b0 605 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
<> 128:9bcdf88f62b0 606 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
<> 128:9bcdf88f62b0 607
<> 128:9bcdf88f62b0 608 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
<> 128:9bcdf88f62b0 609 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
<> 128:9bcdf88f62b0 610
<> 128:9bcdf88f62b0 611 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
<> 128:9bcdf88f62b0 612 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
<> 128:9bcdf88f62b0 613
<> 128:9bcdf88f62b0 614 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
<> 128:9bcdf88f62b0 615
<> 128:9bcdf88f62b0 616 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
<> 128:9bcdf88f62b0 617 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
<> 128:9bcdf88f62b0 618 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
<> 128:9bcdf88f62b0 619
<> 128:9bcdf88f62b0 620 /**
<> 128:9bcdf88f62b0 621 * @}
<> 128:9bcdf88f62b0 622 */
<> 128:9bcdf88f62b0 623
<> 128:9bcdf88f62b0 624 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 625 * @{
<> 128:9bcdf88f62b0 626 */
<> 128:9bcdf88f62b0 627 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
<> 128:9bcdf88f62b0 628 #if defined(STM32F7)
<> 128:9bcdf88f62b0 629 #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
<> 128:9bcdf88f62b0 630 #endif
<> 128:9bcdf88f62b0 631 /**
<> 128:9bcdf88f62b0 632 * @}
<> 128:9bcdf88f62b0 633 */
<> 128:9bcdf88f62b0 634
<> 128:9bcdf88f62b0 635 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 636 * @{
<> 128:9bcdf88f62b0 637 */
<> 128:9bcdf88f62b0 638
<> 128:9bcdf88f62b0 639 /* Compact Flash-ATA registers description */
<> 128:9bcdf88f62b0 640 #define CF_DATA ATA_DATA
<> 128:9bcdf88f62b0 641 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT
<> 128:9bcdf88f62b0 642 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
<> 128:9bcdf88f62b0 643 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW
<> 128:9bcdf88f62b0 644 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
<> 128:9bcdf88f62b0 645 #define CF_CARD_HEAD ATA_CARD_HEAD
<> 128:9bcdf88f62b0 646 #define CF_STATUS_CMD ATA_STATUS_CMD
<> 128:9bcdf88f62b0 647 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
<> 128:9bcdf88f62b0 648 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
<> 128:9bcdf88f62b0 649
<> 128:9bcdf88f62b0 650 /* Compact Flash-ATA commands */
<> 128:9bcdf88f62b0 651 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
<> 128:9bcdf88f62b0 652 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
<> 128:9bcdf88f62b0 653 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
<> 128:9bcdf88f62b0 654 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
<> 128:9bcdf88f62b0 655
<> 128:9bcdf88f62b0 656 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
<> 128:9bcdf88f62b0 657 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
<> 128:9bcdf88f62b0 658 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
<> 128:9bcdf88f62b0 659 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
<> 128:9bcdf88f62b0 660 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
<> 128:9bcdf88f62b0 661 /**
<> 128:9bcdf88f62b0 662 * @}
<> 128:9bcdf88f62b0 663 */
<> 128:9bcdf88f62b0 664
<> 128:9bcdf88f62b0 665 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 666 * @{
<> 128:9bcdf88f62b0 667 */
<> 128:9bcdf88f62b0 668
<> 128:9bcdf88f62b0 669 #define FORMAT_BIN RTC_FORMAT_BIN
<> 128:9bcdf88f62b0 670 #define FORMAT_BCD RTC_FORMAT_BCD
<> 128:9bcdf88f62b0 671
<> 128:9bcdf88f62b0 672 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
<> 128:9bcdf88f62b0 673 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
<> 128:9bcdf88f62b0 674 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
<> 128:9bcdf88f62b0 675 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
<> 128:9bcdf88f62b0 676 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
<> 128:9bcdf88f62b0 677
<> 128:9bcdf88f62b0 678 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
<> 128:9bcdf88f62b0 679 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
<> 128:9bcdf88f62b0 680 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
<> 128:9bcdf88f62b0 681 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
<> 128:9bcdf88f62b0 682 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
<> 128:9bcdf88f62b0 683 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
<> 128:9bcdf88f62b0 684 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
<> 128:9bcdf88f62b0 685 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
<> 128:9bcdf88f62b0 686
<> 128:9bcdf88f62b0 687 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
<> 128:9bcdf88f62b0 688 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
<> 128:9bcdf88f62b0 689 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
<> 128:9bcdf88f62b0 690 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
<> 128:9bcdf88f62b0 691
<> 128:9bcdf88f62b0 692 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
<> 128:9bcdf88f62b0 693 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
<> 128:9bcdf88f62b0 694 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
<> 128:9bcdf88f62b0 695
<> 128:9bcdf88f62b0 696 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
<> 128:9bcdf88f62b0 697 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
<> 128:9bcdf88f62b0 698 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
<> 128:9bcdf88f62b0 699
<> 128:9bcdf88f62b0 700 /**
<> 128:9bcdf88f62b0 701 * @}
<> 128:9bcdf88f62b0 702 */
<> 128:9bcdf88f62b0 703
<> 128:9bcdf88f62b0 704
<> 128:9bcdf88f62b0 705 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 706 * @{
<> 128:9bcdf88f62b0 707 */
<> 128:9bcdf88f62b0 708 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
<> 128:9bcdf88f62b0 709 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
<> 128:9bcdf88f62b0 710
<> 128:9bcdf88f62b0 711 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
<> 128:9bcdf88f62b0 712 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
<> 128:9bcdf88f62b0 713 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
<> 128:9bcdf88f62b0 714 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
<> 128:9bcdf88f62b0 715
<> 128:9bcdf88f62b0 716 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
<> 128:9bcdf88f62b0 717 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
<> 128:9bcdf88f62b0 718
<> 128:9bcdf88f62b0 719 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
<> 128:9bcdf88f62b0 720 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
<> 128:9bcdf88f62b0 721 /**
<> 128:9bcdf88f62b0 722 * @}
<> 128:9bcdf88f62b0 723 */
<> 128:9bcdf88f62b0 724
<> 128:9bcdf88f62b0 725
<> 128:9bcdf88f62b0 726 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 727 * @{
<> 128:9bcdf88f62b0 728 */
<> 128:9bcdf88f62b0 729 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
<> 128:9bcdf88f62b0 730 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
<> 128:9bcdf88f62b0 731 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
<> 128:9bcdf88f62b0 732 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
<> 128:9bcdf88f62b0 733 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
<> 128:9bcdf88f62b0 734 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
<> 128:9bcdf88f62b0 735 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
<> 128:9bcdf88f62b0 736 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
<> 128:9bcdf88f62b0 737 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
<> 128:9bcdf88f62b0 738 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
<> 128:9bcdf88f62b0 739 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
<> 128:9bcdf88f62b0 740 /**
<> 128:9bcdf88f62b0 741 * @}
<> 128:9bcdf88f62b0 742 */
<> 128:9bcdf88f62b0 743
<> 128:9bcdf88f62b0 744 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 745 * @{
<> 128:9bcdf88f62b0 746 */
<> 128:9bcdf88f62b0 747 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
<> 128:9bcdf88f62b0 748 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
<> 128:9bcdf88f62b0 749
<> 128:9bcdf88f62b0 750 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
<> 128:9bcdf88f62b0 751 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
<> 128:9bcdf88f62b0 752
<> 128:9bcdf88f62b0 753 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
<> 128:9bcdf88f62b0 754 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
<> 128:9bcdf88f62b0 755
<> 128:9bcdf88f62b0 756 /**
<> 128:9bcdf88f62b0 757 * @}
<> 128:9bcdf88f62b0 758 */
<> 128:9bcdf88f62b0 759
<> 128:9bcdf88f62b0 760 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 761 * @{
<> 128:9bcdf88f62b0 762 */
<> 128:9bcdf88f62b0 763 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
<> 128:9bcdf88f62b0 764 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
<> 128:9bcdf88f62b0 765
<> 128:9bcdf88f62b0 766 #define TIM_DMABase_CR1 TIM_DMABASE_CR1
<> 128:9bcdf88f62b0 767 #define TIM_DMABase_CR2 TIM_DMABASE_CR2
<> 128:9bcdf88f62b0 768 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR
<> 128:9bcdf88f62b0 769 #define TIM_DMABase_DIER TIM_DMABASE_DIER
<> 128:9bcdf88f62b0 770 #define TIM_DMABase_SR TIM_DMABASE_SR
<> 128:9bcdf88f62b0 771 #define TIM_DMABase_EGR TIM_DMABASE_EGR
<> 128:9bcdf88f62b0 772 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
<> 128:9bcdf88f62b0 773 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
<> 128:9bcdf88f62b0 774 #define TIM_DMABase_CCER TIM_DMABASE_CCER
<> 128:9bcdf88f62b0 775 #define TIM_DMABase_CNT TIM_DMABASE_CNT
<> 128:9bcdf88f62b0 776 #define TIM_DMABase_PSC TIM_DMABASE_PSC
<> 128:9bcdf88f62b0 777 #define TIM_DMABase_ARR TIM_DMABASE_ARR
<> 128:9bcdf88f62b0 778 #define TIM_DMABase_RCR TIM_DMABASE_RCR
<> 128:9bcdf88f62b0 779 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
<> 128:9bcdf88f62b0 780 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
<> 128:9bcdf88f62b0 781 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
<> 128:9bcdf88f62b0 782 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
<> 128:9bcdf88f62b0 783 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR
<> 128:9bcdf88f62b0 784 #define TIM_DMABase_DCR TIM_DMABASE_DCR
<> 128:9bcdf88f62b0 785 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR
<> 128:9bcdf88f62b0 786 #define TIM_DMABase_OR1 TIM_DMABASE_OR1
<> 128:9bcdf88f62b0 787 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
<> 128:9bcdf88f62b0 788 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
<> 128:9bcdf88f62b0 789 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
<> 128:9bcdf88f62b0 790 #define TIM_DMABase_OR2 TIM_DMABASE_OR2
<> 128:9bcdf88f62b0 791 #define TIM_DMABase_OR3 TIM_DMABASE_OR3
<> 128:9bcdf88f62b0 792 #define TIM_DMABase_OR TIM_DMABASE_OR
<> 128:9bcdf88f62b0 793
<> 128:9bcdf88f62b0 794 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
<> 128:9bcdf88f62b0 795 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
<> 128:9bcdf88f62b0 796 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
<> 128:9bcdf88f62b0 797 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
<> 128:9bcdf88f62b0 798 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
<> 128:9bcdf88f62b0 799 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM
<> 128:9bcdf88f62b0 800 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
<> 128:9bcdf88f62b0 801 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
<> 128:9bcdf88f62b0 802 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
<> 128:9bcdf88f62b0 803
<> 128:9bcdf88f62b0 804 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
<> 128:9bcdf88f62b0 805 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
<> 128:9bcdf88f62b0 806 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
<> 128:9bcdf88f62b0 807 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
<> 128:9bcdf88f62b0 808 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
<> 128:9bcdf88f62b0 809 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
<> 128:9bcdf88f62b0 810 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
<> 128:9bcdf88f62b0 811 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
<> 128:9bcdf88f62b0 812 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
<> 128:9bcdf88f62b0 813 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
<> 128:9bcdf88f62b0 814 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
<> 128:9bcdf88f62b0 815 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
<> 128:9bcdf88f62b0 816 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
<> 128:9bcdf88f62b0 817 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
<> 128:9bcdf88f62b0 818 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
<> 128:9bcdf88f62b0 819 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
<> 128:9bcdf88f62b0 820 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
<> 128:9bcdf88f62b0 821 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
<> 128:9bcdf88f62b0 822
<> 128:9bcdf88f62b0 823 /**
<> 128:9bcdf88f62b0 824 * @}
<> 128:9bcdf88f62b0 825 */
<> 128:9bcdf88f62b0 826
<> 128:9bcdf88f62b0 827 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 828 * @{
<> 128:9bcdf88f62b0 829 */
<> 128:9bcdf88f62b0 830 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
<> 128:9bcdf88f62b0 831 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
<> 128:9bcdf88f62b0 832 /**
<> 128:9bcdf88f62b0 833 * @}
<> 128:9bcdf88f62b0 834 */
<> 128:9bcdf88f62b0 835
<> 128:9bcdf88f62b0 836 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 837 * @{
<> 128:9bcdf88f62b0 838 */
<> 128:9bcdf88f62b0 839 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
<> 128:9bcdf88f62b0 840 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
<> 128:9bcdf88f62b0 841 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
<> 128:9bcdf88f62b0 842 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
<> 128:9bcdf88f62b0 843
<> 128:9bcdf88f62b0 844 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
<> 128:9bcdf88f62b0 845 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
<> 128:9bcdf88f62b0 846
<> 128:9bcdf88f62b0 847 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16
<> 128:9bcdf88f62b0 848 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
<> 128:9bcdf88f62b0 849 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
<> 128:9bcdf88f62b0 850 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
<> 128:9bcdf88f62b0 851
<> 128:9bcdf88f62b0 852 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8
<> 128:9bcdf88f62b0 853 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
<> 128:9bcdf88f62b0 854 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
<> 128:9bcdf88f62b0 855 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
<> 128:9bcdf88f62b0 856
<> 134:ad3be0349dc5 857 #define __DIV_LPUART UART_DIV_LPUART
<> 134:ad3be0349dc5 858
<> 128:9bcdf88f62b0 859 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
<> 128:9bcdf88f62b0 860 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
<> 128:9bcdf88f62b0 861
<> 128:9bcdf88f62b0 862 /**
<> 128:9bcdf88f62b0 863 * @}
<> 128:9bcdf88f62b0 864 */
<> 128:9bcdf88f62b0 865
<> 128:9bcdf88f62b0 866
<> 128:9bcdf88f62b0 867 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 868 * @{
<> 128:9bcdf88f62b0 869 */
<> 128:9bcdf88f62b0 870
<> 128:9bcdf88f62b0 871 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
<> 128:9bcdf88f62b0 872 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
<> 128:9bcdf88f62b0 873
<> 128:9bcdf88f62b0 874 #define USARTNACK_ENABLED USART_NACK_ENABLE
<> 128:9bcdf88f62b0 875 #define USARTNACK_DISABLED USART_NACK_DISABLE
<> 128:9bcdf88f62b0 876 /**
<> 128:9bcdf88f62b0 877 * @}
<> 128:9bcdf88f62b0 878 */
<> 128:9bcdf88f62b0 879
<> 128:9bcdf88f62b0 880 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 881 * @{
<> 128:9bcdf88f62b0 882 */
<> 128:9bcdf88f62b0 883 #define CFR_BASE WWDG_CFR_BASE
<> 128:9bcdf88f62b0 884
<> 128:9bcdf88f62b0 885 /**
<> 128:9bcdf88f62b0 886 * @}
<> 128:9bcdf88f62b0 887 */
<> 128:9bcdf88f62b0 888
<> 128:9bcdf88f62b0 889 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 890 * @{
<> 128:9bcdf88f62b0 891 */
<> 128:9bcdf88f62b0 892 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0
<> 128:9bcdf88f62b0 893 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1
<> 128:9bcdf88f62b0 894 #define CAN_IT_RQCP0 CAN_IT_TME
<> 128:9bcdf88f62b0 895 #define CAN_IT_RQCP1 CAN_IT_TME
<> 128:9bcdf88f62b0 896 #define CAN_IT_RQCP2 CAN_IT_TME
<> 128:9bcdf88f62b0 897 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE
<> 128:9bcdf88f62b0 898 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
<> 128:9bcdf88f62b0 899 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
<> 128:9bcdf88f62b0 900 #define CAN_TXSTATUS_OK ((uint8_t)0x01U)
<> 128:9bcdf88f62b0 901 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
<> 128:9bcdf88f62b0 902
<> 128:9bcdf88f62b0 903 /**
<> 128:9bcdf88f62b0 904 * @}
<> 128:9bcdf88f62b0 905 */
<> 128:9bcdf88f62b0 906
<> 128:9bcdf88f62b0 907 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 908 * @{
<> 128:9bcdf88f62b0 909 */
<> 128:9bcdf88f62b0 910
<> 128:9bcdf88f62b0 911 #define VLAN_TAG ETH_VLAN_TAG
<> 128:9bcdf88f62b0 912 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
<> 128:9bcdf88f62b0 913 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
<> 128:9bcdf88f62b0 914 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
<> 128:9bcdf88f62b0 915 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
<> 128:9bcdf88f62b0 916 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
<> 128:9bcdf88f62b0 917 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
<> 128:9bcdf88f62b0 918 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
<> 128:9bcdf88f62b0 919
<> 128:9bcdf88f62b0 920 #define ETH_MMCCR ((uint32_t)0x00000100U)
<> 128:9bcdf88f62b0 921 #define ETH_MMCRIR ((uint32_t)0x00000104U)
<> 128:9bcdf88f62b0 922 #define ETH_MMCTIR ((uint32_t)0x00000108U)
<> 128:9bcdf88f62b0 923 #define ETH_MMCRIMR ((uint32_t)0x0000010CU)
<> 128:9bcdf88f62b0 924 #define ETH_MMCTIMR ((uint32_t)0x00000110U)
<> 128:9bcdf88f62b0 925 #define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
<> 128:9bcdf88f62b0 926 #define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
<> 128:9bcdf88f62b0 927 #define ETH_MMCTGFCR ((uint32_t)0x00000168U)
<> 128:9bcdf88f62b0 928 #define ETH_MMCRFCECR ((uint32_t)0x00000194U)
<> 128:9bcdf88f62b0 929 #define ETH_MMCRFAECR ((uint32_t)0x00000198U)
<> 128:9bcdf88f62b0 930 #define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
<> 128:9bcdf88f62b0 931
<> 128:9bcdf88f62b0 932 #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
<> 128:9bcdf88f62b0 933 #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
<> 128:9bcdf88f62b0 934 #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
<> 128:9bcdf88f62b0 935 #define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
<> 128:9bcdf88f62b0 936 #define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
<> 128:9bcdf88f62b0 937 #define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
<> 128:9bcdf88f62b0 938 #define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
<> 128:9bcdf88f62b0 939 #define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
<> 128:9bcdf88f62b0 940 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
<> 128:9bcdf88f62b0 941 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
<> 128:9bcdf88f62b0 942 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
<> 128:9bcdf88f62b0 943 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
<> 128:9bcdf88f62b0 944 #define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
<> 128:9bcdf88f62b0 945 #define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
<> 128:9bcdf88f62b0 946 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
<> 128:9bcdf88f62b0 947 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
<> 128:9bcdf88f62b0 948 #define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
<> 128:9bcdf88f62b0 949 #if defined(STM32F1)
<> 128:9bcdf88f62b0 950 #else
<> 128:9bcdf88f62b0 951 #define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
<> 128:9bcdf88f62b0 952 #define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
<> 128:9bcdf88f62b0 953 #define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
<> 128:9bcdf88f62b0 954 #endif
<> 128:9bcdf88f62b0 955 #define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
<> 128:9bcdf88f62b0 956 #define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
<> 128:9bcdf88f62b0 957 #define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
<> 128:9bcdf88f62b0 958 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
<> 128:9bcdf88f62b0 959 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
<> 128:9bcdf88f62b0 960 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
<> 128:9bcdf88f62b0 961 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
<> 128:9bcdf88f62b0 962
<> 128:9bcdf88f62b0 963 /**
<> 128:9bcdf88f62b0 964 * @}
<> 128:9bcdf88f62b0 965 */
<> 128:9bcdf88f62b0 966
<> 128:9bcdf88f62b0 967 /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 968 * @{
<> 128:9bcdf88f62b0 969 */
<> 128:9bcdf88f62b0 970 #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
<> 128:9bcdf88f62b0 971 #define DCMI_IT_OVF DCMI_IT_OVR
<> 128:9bcdf88f62b0 972 #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
<> 128:9bcdf88f62b0 973 #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
<> 128:9bcdf88f62b0 974
<> 128:9bcdf88f62b0 975 #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
<> 128:9bcdf88f62b0 976 #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
<> 128:9bcdf88f62b0 977 #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
<> 128:9bcdf88f62b0 978
<> 128:9bcdf88f62b0 979 /**
<> 128:9bcdf88f62b0 980 * @}
<> 128:9bcdf88f62b0 981 */
<> 128:9bcdf88f62b0 982
<> 128:9bcdf88f62b0 983 #if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
<> 128:9bcdf88f62b0 984 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
<> 128:9bcdf88f62b0 985 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 986 * @{
<> 128:9bcdf88f62b0 987 */
<> 128:9bcdf88f62b0 988 #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
<> 128:9bcdf88f62b0 989 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
<> 128:9bcdf88f62b0 990 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
<> 128:9bcdf88f62b0 991 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
<> 128:9bcdf88f62b0 992 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
<> 128:9bcdf88f62b0 993
<> 128:9bcdf88f62b0 994 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888
<> 128:9bcdf88f62b0 995 #define CM_RGB888 DMA2D_INPUT_RGB888
<> 128:9bcdf88f62b0 996 #define CM_RGB565 DMA2D_INPUT_RGB565
<> 128:9bcdf88f62b0 997 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555
<> 128:9bcdf88f62b0 998 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444
<> 128:9bcdf88f62b0 999 #define CM_L8 DMA2D_INPUT_L8
<> 128:9bcdf88f62b0 1000 #define CM_AL44 DMA2D_INPUT_AL44
<> 128:9bcdf88f62b0 1001 #define CM_AL88 DMA2D_INPUT_AL88
<> 128:9bcdf88f62b0 1002 #define CM_L4 DMA2D_INPUT_L4
<> 128:9bcdf88f62b0 1003 #define CM_A8 DMA2D_INPUT_A8
<> 128:9bcdf88f62b0 1004 #define CM_A4 DMA2D_INPUT_A4
<> 128:9bcdf88f62b0 1005 /**
<> 128:9bcdf88f62b0 1006 * @}
<> 128:9bcdf88f62b0 1007 */
<> 128:9bcdf88f62b0 1008 #endif /* STM32L4xx || STM32F7*/
<> 128:9bcdf88f62b0 1009
<> 128:9bcdf88f62b0 1010 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
<> 128:9bcdf88f62b0 1011 * @{
<> 128:9bcdf88f62b0 1012 */
<> 128:9bcdf88f62b0 1013
<> 128:9bcdf88f62b0 1014 /**
<> 128:9bcdf88f62b0 1015 * @}
<> 128:9bcdf88f62b0 1016 */
<> 128:9bcdf88f62b0 1017
<> 128:9bcdf88f62b0 1018 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 1019
<> 128:9bcdf88f62b0 1020 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
<> 128:9bcdf88f62b0 1021 * @{
<> 128:9bcdf88f62b0 1022 */
<> 128:9bcdf88f62b0 1023 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
<> 128:9bcdf88f62b0 1024 /**
<> 128:9bcdf88f62b0 1025 * @}
<> 128:9bcdf88f62b0 1026 */
<> 128:9bcdf88f62b0 1027
<> 128:9bcdf88f62b0 1028 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
<> 128:9bcdf88f62b0 1029 * @{
<> 128:9bcdf88f62b0 1030 */
<> 128:9bcdf88f62b0 1031 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
<> 128:9bcdf88f62b0 1032 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
<> 128:9bcdf88f62b0 1033 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
<> 128:9bcdf88f62b0 1034 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
<> 128:9bcdf88f62b0 1035 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
<> 128:9bcdf88f62b0 1036 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
<> 128:9bcdf88f62b0 1037
<> 128:9bcdf88f62b0 1038 /*HASH Algorithm Selection*/
<> 128:9bcdf88f62b0 1039
<> 128:9bcdf88f62b0 1040 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
<> 128:9bcdf88f62b0 1041 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
<> 128:9bcdf88f62b0 1042 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
<> 128:9bcdf88f62b0 1043 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
<> 128:9bcdf88f62b0 1044
<> 128:9bcdf88f62b0 1045 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
<> 128:9bcdf88f62b0 1046 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
<> 128:9bcdf88f62b0 1047
<> 128:9bcdf88f62b0 1048 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
<> 128:9bcdf88f62b0 1049 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
<> 128:9bcdf88f62b0 1050 /**
<> 128:9bcdf88f62b0 1051 * @}
<> 128:9bcdf88f62b0 1052 */
<> 128:9bcdf88f62b0 1053
<> 128:9bcdf88f62b0 1054 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
<> 128:9bcdf88f62b0 1055 * @{
<> 128:9bcdf88f62b0 1056 */
<> 128:9bcdf88f62b0 1057 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
<> 128:9bcdf88f62b0 1058 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
<> 128:9bcdf88f62b0 1059 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
<> 128:9bcdf88f62b0 1060 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
<> 128:9bcdf88f62b0 1061 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
<> 128:9bcdf88f62b0 1062 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
<> 128:9bcdf88f62b0 1063 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
<> 128:9bcdf88f62b0 1064 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
<> 128:9bcdf88f62b0 1065 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
<> 128:9bcdf88f62b0 1066 #if defined(STM32L0)
<> 128:9bcdf88f62b0 1067 #else
<> 128:9bcdf88f62b0 1068 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
<> 128:9bcdf88f62b0 1069 #endif
<> 128:9bcdf88f62b0 1070 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
<> 128:9bcdf88f62b0 1071 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
<> 128:9bcdf88f62b0 1072 /**
<> 128:9bcdf88f62b0 1073 * @}
<> 128:9bcdf88f62b0 1074 */
<> 128:9bcdf88f62b0 1075
<> 128:9bcdf88f62b0 1076 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
<> 128:9bcdf88f62b0 1077 * @{
<> 128:9bcdf88f62b0 1078 */
<> 128:9bcdf88f62b0 1079 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
<> 128:9bcdf88f62b0 1080 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
<> 128:9bcdf88f62b0 1081 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
<> 128:9bcdf88f62b0 1082 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
<> 128:9bcdf88f62b0 1083 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
<> 128:9bcdf88f62b0 1084 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
<> 128:9bcdf88f62b0 1085 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
<> 128:9bcdf88f62b0 1086
<> 128:9bcdf88f62b0 1087 /**
<> 128:9bcdf88f62b0 1088 * @}
<> 128:9bcdf88f62b0 1089 */
<> 128:9bcdf88f62b0 1090
<> 128:9bcdf88f62b0 1091 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
<> 128:9bcdf88f62b0 1092 * @{
<> 128:9bcdf88f62b0 1093 */
<> 128:9bcdf88f62b0 1094 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
<> 128:9bcdf88f62b0 1095 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
<> 128:9bcdf88f62b0 1096 #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
<> 128:9bcdf88f62b0 1097 #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
<> 128:9bcdf88f62b0 1098
<> 128:9bcdf88f62b0 1099 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
<> 128:9bcdf88f62b0 1100 /**
<> 128:9bcdf88f62b0 1101 * @}
<> 128:9bcdf88f62b0 1102 */
<> 128:9bcdf88f62b0 1103
<> 128:9bcdf88f62b0 1104 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
<> 128:9bcdf88f62b0 1105 * @{
<> 128:9bcdf88f62b0 1106 */
<> 128:9bcdf88f62b0 1107 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
<> 128:9bcdf88f62b0 1108 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
<> 128:9bcdf88f62b0 1109 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
<> 128:9bcdf88f62b0 1110 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
<> 128:9bcdf88f62b0 1111 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
<> 128:9bcdf88f62b0 1112 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
<> 128:9bcdf88f62b0 1113 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
<> 128:9bcdf88f62b0 1114 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
<> 128:9bcdf88f62b0 1115 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
<> 128:9bcdf88f62b0 1116 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
<> 128:9bcdf88f62b0 1117 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
<> 128:9bcdf88f62b0 1118 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
<> 128:9bcdf88f62b0 1119 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
<> 128:9bcdf88f62b0 1120 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
<> 128:9bcdf88f62b0 1121 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
<> 128:9bcdf88f62b0 1122 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
<> 128:9bcdf88f62b0 1123
<> 128:9bcdf88f62b0 1124 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
<> 128:9bcdf88f62b0 1125 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
<> 128:9bcdf88f62b0 1126 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
<> 128:9bcdf88f62b0 1127 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
<> 128:9bcdf88f62b0 1128 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
<> 128:9bcdf88f62b0 1129 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
<> 128:9bcdf88f62b0 1130 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
<> 128:9bcdf88f62b0 1131
<> 128:9bcdf88f62b0 1132 #define CR_OFFSET_BB PWR_CR_OFFSET_BB
<> 128:9bcdf88f62b0 1133 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
<> 128:9bcdf88f62b0 1134
<> 128:9bcdf88f62b0 1135 #define DBP_BitNumber DBP_BIT_NUMBER
<> 128:9bcdf88f62b0 1136 #define PVDE_BitNumber PVDE_BIT_NUMBER
<> 128:9bcdf88f62b0 1137 #define PMODE_BitNumber PMODE_BIT_NUMBER
<> 128:9bcdf88f62b0 1138 #define EWUP_BitNumber EWUP_BIT_NUMBER
<> 128:9bcdf88f62b0 1139 #define FPDS_BitNumber FPDS_BIT_NUMBER
<> 128:9bcdf88f62b0 1140 #define ODEN_BitNumber ODEN_BIT_NUMBER
<> 128:9bcdf88f62b0 1141 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
<> 128:9bcdf88f62b0 1142 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
<> 128:9bcdf88f62b0 1143 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
<> 128:9bcdf88f62b0 1144 #define BRE_BitNumber BRE_BIT_NUMBER
<> 128:9bcdf88f62b0 1145
<> 128:9bcdf88f62b0 1146 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
<> 128:9bcdf88f62b0 1147
<> 128:9bcdf88f62b0 1148 /**
<> 128:9bcdf88f62b0 1149 * @}
<> 128:9bcdf88f62b0 1150 */
<> 128:9bcdf88f62b0 1151
<> 128:9bcdf88f62b0 1152 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
<> 128:9bcdf88f62b0 1153 * @{
<> 128:9bcdf88f62b0 1154 */
<> 128:9bcdf88f62b0 1155 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
<> 128:9bcdf88f62b0 1156 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
<> 128:9bcdf88f62b0 1157 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
<> 128:9bcdf88f62b0 1158 /**
<> 128:9bcdf88f62b0 1159 * @}
<> 128:9bcdf88f62b0 1160 */
<> 128:9bcdf88f62b0 1161
<> 128:9bcdf88f62b0 1162 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
<> 128:9bcdf88f62b0 1163 * @{
<> 128:9bcdf88f62b0 1164 */
<> 128:9bcdf88f62b0 1165 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
<> 128:9bcdf88f62b0 1166 /**
<> 128:9bcdf88f62b0 1167 * @}
<> 128:9bcdf88f62b0 1168 */
<> 128:9bcdf88f62b0 1169
<> 128:9bcdf88f62b0 1170 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
<> 128:9bcdf88f62b0 1171 * @{
<> 128:9bcdf88f62b0 1172 */
<> 128:9bcdf88f62b0 1173 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
<> 128:9bcdf88f62b0 1174 #define HAL_TIM_DMAError TIM_DMAError
<> 128:9bcdf88f62b0 1175 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
<> 128:9bcdf88f62b0 1176 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
<> 128:9bcdf88f62b0 1177 /**
<> 128:9bcdf88f62b0 1178 * @}
<> 128:9bcdf88f62b0 1179 */
<> 128:9bcdf88f62b0 1180
<> 128:9bcdf88f62b0 1181 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
<> 128:9bcdf88f62b0 1182 * @{
<> 128:9bcdf88f62b0 1183 */
<> 128:9bcdf88f62b0 1184 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
<> 128:9bcdf88f62b0 1185 /**
<> 128:9bcdf88f62b0 1186 * @}
<> 128:9bcdf88f62b0 1187 */
<> 128:9bcdf88f62b0 1188
<> 128:9bcdf88f62b0 1189 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
<> 128:9bcdf88f62b0 1190 * @{
<> 128:9bcdf88f62b0 1191 */
<> 128:9bcdf88f62b0 1192 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
<> 128:9bcdf88f62b0 1193 /**
<> 128:9bcdf88f62b0 1194 * @}
<> 128:9bcdf88f62b0 1195 */
<> 128:9bcdf88f62b0 1196
<> 128:9bcdf88f62b0 1197
<> 128:9bcdf88f62b0 1198 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
<> 128:9bcdf88f62b0 1199 * @{
<> 128:9bcdf88f62b0 1200 */
<> 128:9bcdf88f62b0 1201
<> 128:9bcdf88f62b0 1202 /**
<> 128:9bcdf88f62b0 1203 * @}
<> 128:9bcdf88f62b0 1204 */
<> 128:9bcdf88f62b0 1205
<> 128:9bcdf88f62b0 1206 /* Exported macros ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 1207
<> 128:9bcdf88f62b0 1208 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 1209 * @{
<> 128:9bcdf88f62b0 1210 */
<> 128:9bcdf88f62b0 1211 #define AES_IT_CC CRYP_IT_CC
<> 128:9bcdf88f62b0 1212 #define AES_IT_ERR CRYP_IT_ERR
<> 128:9bcdf88f62b0 1213 #define AES_FLAG_CCF CRYP_FLAG_CCF
<> 128:9bcdf88f62b0 1214 /**
<> 128:9bcdf88f62b0 1215 * @}
<> 128:9bcdf88f62b0 1216 */
<> 128:9bcdf88f62b0 1217
<> 128:9bcdf88f62b0 1218 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 1219 * @{
<> 128:9bcdf88f62b0 1220 */
<> 128:9bcdf88f62b0 1221 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
<> 128:9bcdf88f62b0 1222 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
<> 128:9bcdf88f62b0 1223 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
<> 128:9bcdf88f62b0 1224 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
<> 128:9bcdf88f62b0 1225 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
<> 128:9bcdf88f62b0 1226 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
<> 128:9bcdf88f62b0 1227 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
<> 128:9bcdf88f62b0 1228 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
<> 128:9bcdf88f62b0 1229 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
<> 128:9bcdf88f62b0 1230 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
<> 128:9bcdf88f62b0 1231 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
<> 128:9bcdf88f62b0 1232 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
<> 128:9bcdf88f62b0 1233 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
<> 128:9bcdf88f62b0 1234
<> 128:9bcdf88f62b0 1235 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
<> 128:9bcdf88f62b0 1236 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
<> 128:9bcdf88f62b0 1237 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
<> 128:9bcdf88f62b0 1238 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
<> 128:9bcdf88f62b0 1239 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
<> 128:9bcdf88f62b0 1240
<> 128:9bcdf88f62b0 1241 /**
<> 128:9bcdf88f62b0 1242 * @}
<> 128:9bcdf88f62b0 1243 */
<> 128:9bcdf88f62b0 1244
<> 128:9bcdf88f62b0 1245
<> 128:9bcdf88f62b0 1246 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 1247 * @{
<> 128:9bcdf88f62b0 1248 */
<> 128:9bcdf88f62b0 1249 #define __ADC_ENABLE __HAL_ADC_ENABLE
<> 128:9bcdf88f62b0 1250 #define __ADC_DISABLE __HAL_ADC_DISABLE
<> 128:9bcdf88f62b0 1251 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
<> 128:9bcdf88f62b0 1252 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
<> 128:9bcdf88f62b0 1253 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
<> 128:9bcdf88f62b0 1254 #define __ADC_IS_ENABLED ADC_IS_ENABLE
<> 128:9bcdf88f62b0 1255 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
<> 128:9bcdf88f62b0 1256 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
<> 128:9bcdf88f62b0 1257 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
<> 128:9bcdf88f62b0 1258 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
<> 128:9bcdf88f62b0 1259 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
<> 128:9bcdf88f62b0 1260 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
<> 128:9bcdf88f62b0 1261 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
<> 128:9bcdf88f62b0 1262
<> 128:9bcdf88f62b0 1263 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
<> 128:9bcdf88f62b0 1264 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK
<> 128:9bcdf88f62b0 1265 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
<> 128:9bcdf88f62b0 1266 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
<> 128:9bcdf88f62b0 1267 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
<> 128:9bcdf88f62b0 1268 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
<> 128:9bcdf88f62b0 1269 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
<> 128:9bcdf88f62b0 1270 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
<> 128:9bcdf88f62b0 1271 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
<> 128:9bcdf88f62b0 1272 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
<> 128:9bcdf88f62b0 1273 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
<> 128:9bcdf88f62b0 1274 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
<> 128:9bcdf88f62b0 1275 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
<> 128:9bcdf88f62b0 1276 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
<> 128:9bcdf88f62b0 1277 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
<> 128:9bcdf88f62b0 1278 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
<> 128:9bcdf88f62b0 1279 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
<> 128:9bcdf88f62b0 1280 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
<> 128:9bcdf88f62b0 1281 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
<> 128:9bcdf88f62b0 1282 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
<> 128:9bcdf88f62b0 1283
<> 128:9bcdf88f62b0 1284 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
<> 128:9bcdf88f62b0 1285 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
<> 128:9bcdf88f62b0 1286 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
<> 128:9bcdf88f62b0 1287 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
<> 128:9bcdf88f62b0 1288 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
<> 128:9bcdf88f62b0 1289 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
<> 128:9bcdf88f62b0 1290 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
<> 128:9bcdf88f62b0 1291 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
<> 128:9bcdf88f62b0 1292 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
<> 128:9bcdf88f62b0 1293 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
<> 128:9bcdf88f62b0 1294
<> 128:9bcdf88f62b0 1295 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
<> 128:9bcdf88f62b0 1296 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
<> 128:9bcdf88f62b0 1297 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
<> 128:9bcdf88f62b0 1298 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
<> 128:9bcdf88f62b0 1299 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
<> 128:9bcdf88f62b0 1300 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
<> 128:9bcdf88f62b0 1301 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
<> 128:9bcdf88f62b0 1302 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
<> 128:9bcdf88f62b0 1303
<> 128:9bcdf88f62b0 1304 #define __HAL_ADC_SQR1 ADC_SQR1
<> 128:9bcdf88f62b0 1305 #define __HAL_ADC_SMPR1 ADC_SMPR1
<> 128:9bcdf88f62b0 1306 #define __HAL_ADC_SMPR2 ADC_SMPR2
<> 128:9bcdf88f62b0 1307 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK
<> 128:9bcdf88f62b0 1308 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK
<> 128:9bcdf88f62b0 1309 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK
<> 128:9bcdf88f62b0 1310 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
<> 128:9bcdf88f62b0 1311 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
<> 128:9bcdf88f62b0 1312 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
<> 128:9bcdf88f62b0 1313 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
<> 128:9bcdf88f62b0 1314 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
<> 128:9bcdf88f62b0 1315 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
<> 128:9bcdf88f62b0 1316 #define __HAL_ADC_JSQR ADC_JSQR
<> 128:9bcdf88f62b0 1317
<> 128:9bcdf88f62b0 1318 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
<> 128:9bcdf88f62b0 1319 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
<> 128:9bcdf88f62b0 1320 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
<> 128:9bcdf88f62b0 1321 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
<> 128:9bcdf88f62b0 1322 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
<> 128:9bcdf88f62b0 1323 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
<> 128:9bcdf88f62b0 1324 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
<> 128:9bcdf88f62b0 1325 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
<> 128:9bcdf88f62b0 1326
<> 128:9bcdf88f62b0 1327 /**
<> 128:9bcdf88f62b0 1328 * @}
<> 128:9bcdf88f62b0 1329 */
<> 128:9bcdf88f62b0 1330
<> 128:9bcdf88f62b0 1331 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 1332 * @{
<> 128:9bcdf88f62b0 1333 */
<> 128:9bcdf88f62b0 1334 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
<> 128:9bcdf88f62b0 1335 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
<> 128:9bcdf88f62b0 1336 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
<> 128:9bcdf88f62b0 1337 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
<> 128:9bcdf88f62b0 1338
<> 128:9bcdf88f62b0 1339 /**
<> 128:9bcdf88f62b0 1340 * @}
<> 128:9bcdf88f62b0 1341 */
<> 128:9bcdf88f62b0 1342
<> 128:9bcdf88f62b0 1343 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 1344 * @{
<> 128:9bcdf88f62b0 1345 */
<> 128:9bcdf88f62b0 1346 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
<> 128:9bcdf88f62b0 1347 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
<> 128:9bcdf88f62b0 1348 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
<> 128:9bcdf88f62b0 1349 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
<> 128:9bcdf88f62b0 1350 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
<> 128:9bcdf88f62b0 1351 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
<> 128:9bcdf88f62b0 1352 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
<> 128:9bcdf88f62b0 1353 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
<> 128:9bcdf88f62b0 1354 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
<> 128:9bcdf88f62b0 1355 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
<> 128:9bcdf88f62b0 1356 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
<> 128:9bcdf88f62b0 1357 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
<> 128:9bcdf88f62b0 1358 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
<> 128:9bcdf88f62b0 1359 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
<> 128:9bcdf88f62b0 1360 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
<> 128:9bcdf88f62b0 1361 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
<> 128:9bcdf88f62b0 1362
<> 128:9bcdf88f62b0 1363 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
<> 128:9bcdf88f62b0 1364 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
<> 128:9bcdf88f62b0 1365 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
<> 128:9bcdf88f62b0 1366 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
<> 128:9bcdf88f62b0 1367 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
<> 128:9bcdf88f62b0 1368 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
<> 128:9bcdf88f62b0 1369 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
<> 128:9bcdf88f62b0 1370 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
<> 128:9bcdf88f62b0 1371 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
<> 128:9bcdf88f62b0 1372 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
<> 128:9bcdf88f62b0 1373 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
<> 128:9bcdf88f62b0 1374 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
<> 128:9bcdf88f62b0 1375 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
<> 128:9bcdf88f62b0 1376 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
<> 128:9bcdf88f62b0 1377
<> 128:9bcdf88f62b0 1378
<> 128:9bcdf88f62b0 1379 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
<> 128:9bcdf88f62b0 1380 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
<> 128:9bcdf88f62b0 1381 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
<> 128:9bcdf88f62b0 1382 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
<> 128:9bcdf88f62b0 1383 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
<> 128:9bcdf88f62b0 1384 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
<> 128:9bcdf88f62b0 1385 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
<> 128:9bcdf88f62b0 1386 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
<> 128:9bcdf88f62b0 1387 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
<> 128:9bcdf88f62b0 1388 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
<> 128:9bcdf88f62b0 1389 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
<> 128:9bcdf88f62b0 1390 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
<> 128:9bcdf88f62b0 1391 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
<> 128:9bcdf88f62b0 1392 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
<> 128:9bcdf88f62b0 1393 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
<> 128:9bcdf88f62b0 1394 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
<> 128:9bcdf88f62b0 1395 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
<> 128:9bcdf88f62b0 1396 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
<> 128:9bcdf88f62b0 1397 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
<> 128:9bcdf88f62b0 1398 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
<> 128:9bcdf88f62b0 1399 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
<> 128:9bcdf88f62b0 1400 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
<> 128:9bcdf88f62b0 1401 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
<> 128:9bcdf88f62b0 1402 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
<> 128:9bcdf88f62b0 1403
<> 128:9bcdf88f62b0 1404 /**
<> 128:9bcdf88f62b0 1405 * @}
<> 128:9bcdf88f62b0 1406 */
<> 128:9bcdf88f62b0 1407
<> 128:9bcdf88f62b0 1408 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 1409 * @{
<> 128:9bcdf88f62b0 1410 */
<> 128:9bcdf88f62b0 1411 #if defined(STM32F3)
<> 128:9bcdf88f62b0 1412 #define COMP_START __HAL_COMP_ENABLE
<> 128:9bcdf88f62b0 1413 #define COMP_STOP __HAL_COMP_DISABLE
<> 128:9bcdf88f62b0 1414 #define COMP_LOCK __HAL_COMP_LOCK
<> 128:9bcdf88f62b0 1415
<> 128:9bcdf88f62b0 1416 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
<> 128:9bcdf88f62b0 1417 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1418 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1419 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
<> 128:9bcdf88f62b0 1420 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1421 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1422 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
<> 128:9bcdf88f62b0 1423 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1424 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1425 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
<> 128:9bcdf88f62b0 1426 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1427 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1428 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
<> 128:9bcdf88f62b0 1429 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
<> 128:9bcdf88f62b0 1430 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
<> 128:9bcdf88f62b0 1431 __HAL_COMP_COMP6_EXTI_ENABLE_IT())
<> 128:9bcdf88f62b0 1432 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
<> 128:9bcdf88f62b0 1433 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
<> 128:9bcdf88f62b0 1434 __HAL_COMP_COMP6_EXTI_DISABLE_IT())
<> 128:9bcdf88f62b0 1435 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
<> 128:9bcdf88f62b0 1436 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
<> 128:9bcdf88f62b0 1437 __HAL_COMP_COMP6_EXTI_GET_FLAG())
<> 128:9bcdf88f62b0 1438 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
<> 128:9bcdf88f62b0 1439 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
<> 128:9bcdf88f62b0 1440 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
<> 128:9bcdf88f62b0 1441 # endif
<> 128:9bcdf88f62b0 1442 # if defined(STM32F302xE) || defined(STM32F302xC)
<> 128:9bcdf88f62b0 1443 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1444 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1445 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1446 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
<> 128:9bcdf88f62b0 1447 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1448 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1449 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1450 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
<> 128:9bcdf88f62b0 1451 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1452 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1453 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1454 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
<> 128:9bcdf88f62b0 1455 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1456 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1457 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1458 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
<> 128:9bcdf88f62b0 1459 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
<> 128:9bcdf88f62b0 1460 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
<> 128:9bcdf88f62b0 1461 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
<> 128:9bcdf88f62b0 1462 __HAL_COMP_COMP6_EXTI_ENABLE_IT())
<> 128:9bcdf88f62b0 1463 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
<> 128:9bcdf88f62b0 1464 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
<> 128:9bcdf88f62b0 1465 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
<> 128:9bcdf88f62b0 1466 __HAL_COMP_COMP6_EXTI_DISABLE_IT())
<> 128:9bcdf88f62b0 1467 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
<> 128:9bcdf88f62b0 1468 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
<> 128:9bcdf88f62b0 1469 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
<> 128:9bcdf88f62b0 1470 __HAL_COMP_COMP6_EXTI_GET_FLAG())
<> 128:9bcdf88f62b0 1471 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
<> 128:9bcdf88f62b0 1472 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
<> 128:9bcdf88f62b0 1473 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
<> 128:9bcdf88f62b0 1474 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
<> 128:9bcdf88f62b0 1475 # endif
<> 128:9bcdf88f62b0 1476 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
<> 128:9bcdf88f62b0 1477 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1478 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1479 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1480 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1481 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1482 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1483 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
<> 128:9bcdf88f62b0 1484 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1485 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1486 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1487 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1488 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1489 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1490 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
<> 128:9bcdf88f62b0 1491 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1492 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1493 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1494 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1495 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1496 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1497 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
<> 128:9bcdf88f62b0 1498 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1499 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1500 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1501 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1502 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1503 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1504 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
<> 128:9bcdf88f62b0 1505 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
<> 128:9bcdf88f62b0 1506 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
<> 128:9bcdf88f62b0 1507 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
<> 128:9bcdf88f62b0 1508 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
<> 128:9bcdf88f62b0 1509 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
<> 128:9bcdf88f62b0 1510 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
<> 128:9bcdf88f62b0 1511 __HAL_COMP_COMP7_EXTI_ENABLE_IT())
<> 128:9bcdf88f62b0 1512 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
<> 128:9bcdf88f62b0 1513 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
<> 128:9bcdf88f62b0 1514 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
<> 128:9bcdf88f62b0 1515 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
<> 128:9bcdf88f62b0 1516 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
<> 128:9bcdf88f62b0 1517 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
<> 128:9bcdf88f62b0 1518 __HAL_COMP_COMP7_EXTI_DISABLE_IT())
<> 128:9bcdf88f62b0 1519 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
<> 128:9bcdf88f62b0 1520 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
<> 128:9bcdf88f62b0 1521 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
<> 128:9bcdf88f62b0 1522 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
<> 128:9bcdf88f62b0 1523 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
<> 128:9bcdf88f62b0 1524 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
<> 128:9bcdf88f62b0 1525 __HAL_COMP_COMP7_EXTI_GET_FLAG())
<> 128:9bcdf88f62b0 1526 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
<> 128:9bcdf88f62b0 1527 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
<> 128:9bcdf88f62b0 1528 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
<> 128:9bcdf88f62b0 1529 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
<> 128:9bcdf88f62b0 1530 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
<> 128:9bcdf88f62b0 1531 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
<> 128:9bcdf88f62b0 1532 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
<> 128:9bcdf88f62b0 1533 # endif
<> 128:9bcdf88f62b0 1534 # if defined(STM32F373xC) ||defined(STM32F378xx)
<> 128:9bcdf88f62b0 1535 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1536 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
<> 128:9bcdf88f62b0 1537 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1538 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
<> 128:9bcdf88f62b0 1539 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1540 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
<> 128:9bcdf88f62b0 1541 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1542 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
<> 128:9bcdf88f62b0 1543 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
<> 128:9bcdf88f62b0 1544 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
<> 128:9bcdf88f62b0 1545 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
<> 128:9bcdf88f62b0 1546 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
<> 128:9bcdf88f62b0 1547 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
<> 128:9bcdf88f62b0 1548 __HAL_COMP_COMP2_EXTI_GET_FLAG())
<> 128:9bcdf88f62b0 1549 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
<> 128:9bcdf88f62b0 1550 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
<> 128:9bcdf88f62b0 1551 # endif
<> 128:9bcdf88f62b0 1552 #else
<> 128:9bcdf88f62b0 1553 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1554 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
<> 128:9bcdf88f62b0 1555 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
<> 128:9bcdf88f62b0 1556 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
<> 128:9bcdf88f62b0 1557 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1558 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
<> 128:9bcdf88f62b0 1559 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
<> 128:9bcdf88f62b0 1560 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
<> 128:9bcdf88f62b0 1561 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
<> 128:9bcdf88f62b0 1562 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
<> 128:9bcdf88f62b0 1563 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
<> 128:9bcdf88f62b0 1564 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
<> 128:9bcdf88f62b0 1565 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
<> 128:9bcdf88f62b0 1566 __HAL_COMP_COMP2_EXTI_GET_FLAG())
<> 128:9bcdf88f62b0 1567 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
<> 128:9bcdf88f62b0 1568 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
<> 128:9bcdf88f62b0 1569 #endif
<> 128:9bcdf88f62b0 1570
<> 128:9bcdf88f62b0 1571 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
<> 128:9bcdf88f62b0 1572
<> 128:9bcdf88f62b0 1573 #if defined(STM32L0) || defined(STM32L4)
<> 128:9bcdf88f62b0 1574 /* Note: On these STM32 families, the only argument of this macro */
<> 128:9bcdf88f62b0 1575 /* is COMP_FLAG_LOCK. */
<> 128:9bcdf88f62b0 1576 /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
<> 128:9bcdf88f62b0 1577 /* argument. */
<> 128:9bcdf88f62b0 1578 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
<> 128:9bcdf88f62b0 1579 #endif
<> 128:9bcdf88f62b0 1580 /**
<> 128:9bcdf88f62b0 1581 * @}
<> 128:9bcdf88f62b0 1582 */
<> 128:9bcdf88f62b0 1583
<> 128:9bcdf88f62b0 1584 #if defined(STM32L0) || defined(STM32L4)
<> 128:9bcdf88f62b0 1585 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
<> 128:9bcdf88f62b0 1586 * @{
<> 128:9bcdf88f62b0 1587 */
<> 128:9bcdf88f62b0 1588 #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
<> 128:9bcdf88f62b0 1589 #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
<> 128:9bcdf88f62b0 1590 /**
<> 128:9bcdf88f62b0 1591 * @}
<> 128:9bcdf88f62b0 1592 */
<> 128:9bcdf88f62b0 1593 #endif
<> 128:9bcdf88f62b0 1594
<> 128:9bcdf88f62b0 1595 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 1596 * @{
<> 128:9bcdf88f62b0 1597 */
<> 128:9bcdf88f62b0 1598
<> 128:9bcdf88f62b0 1599 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
<> 128:9bcdf88f62b0 1600 ((WAVE) == DAC_WAVE_NOISE)|| \
<> 128:9bcdf88f62b0 1601 ((WAVE) == DAC_WAVE_TRIANGLE))
<> 128:9bcdf88f62b0 1602
<> 128:9bcdf88f62b0 1603 /**
<> 128:9bcdf88f62b0 1604 * @}
<> 128:9bcdf88f62b0 1605 */
<> 128:9bcdf88f62b0 1606
<> 128:9bcdf88f62b0 1607 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 1608 * @{
<> 128:9bcdf88f62b0 1609 */
<> 128:9bcdf88f62b0 1610
<> 128:9bcdf88f62b0 1611 #define IS_WRPAREA IS_OB_WRPAREA
<> 128:9bcdf88f62b0 1612 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
<> 128:9bcdf88f62b0 1613 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
<> 128:9bcdf88f62b0 1614 #define IS_TYPEERASE IS_FLASH_TYPEERASE
<> 128:9bcdf88f62b0 1615 #define IS_NBSECTORS IS_FLASH_NBSECTORS
<> 128:9bcdf88f62b0 1616 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
<> 128:9bcdf88f62b0 1617
<> 128:9bcdf88f62b0 1618 /**
<> 128:9bcdf88f62b0 1619 * @}
<> 128:9bcdf88f62b0 1620 */
<> 128:9bcdf88f62b0 1621
<> 128:9bcdf88f62b0 1622 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 1623 * @{
<> 128:9bcdf88f62b0 1624 */
<> 128:9bcdf88f62b0 1625
<> 128:9bcdf88f62b0 1626 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
<> 128:9bcdf88f62b0 1627 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START
<> 128:9bcdf88f62b0 1628 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
<> 128:9bcdf88f62b0 1629 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME
<> 128:9bcdf88f62b0 1630 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
<> 128:9bcdf88f62b0 1631 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
<> 128:9bcdf88f62b0 1632 #define __HAL_I2C_SPEED I2C_SPEED
<> 128:9bcdf88f62b0 1633 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
<> 128:9bcdf88f62b0 1634 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
<> 128:9bcdf88f62b0 1635 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
<> 128:9bcdf88f62b0 1636 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
<> 128:9bcdf88f62b0 1637 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
<> 128:9bcdf88f62b0 1638 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
<> 128:9bcdf88f62b0 1639 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
<> 128:9bcdf88f62b0 1640 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE
<> 128:9bcdf88f62b0 1641 /**
<> 128:9bcdf88f62b0 1642 * @}
<> 128:9bcdf88f62b0 1643 */
<> 128:9bcdf88f62b0 1644
<> 128:9bcdf88f62b0 1645 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 1646 * @{
<> 128:9bcdf88f62b0 1647 */
<> 128:9bcdf88f62b0 1648
<> 128:9bcdf88f62b0 1649 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
<> 128:9bcdf88f62b0 1650 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
<> 128:9bcdf88f62b0 1651
<> 128:9bcdf88f62b0 1652 /**
<> 128:9bcdf88f62b0 1653 * @}
<> 128:9bcdf88f62b0 1654 */
<> 128:9bcdf88f62b0 1655
<> 128:9bcdf88f62b0 1656 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 1657 * @{
<> 128:9bcdf88f62b0 1658 */
<> 128:9bcdf88f62b0 1659
<> 128:9bcdf88f62b0 1660 #define __IRDA_DISABLE __HAL_IRDA_DISABLE
<> 128:9bcdf88f62b0 1661 #define __IRDA_ENABLE __HAL_IRDA_ENABLE
<> 128:9bcdf88f62b0 1662
<> 128:9bcdf88f62b0 1663 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
<> 128:9bcdf88f62b0 1664 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
<> 128:9bcdf88f62b0 1665 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
<> 128:9bcdf88f62b0 1666 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
<> 128:9bcdf88f62b0 1667
<> 128:9bcdf88f62b0 1668 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
<> 128:9bcdf88f62b0 1669
<> 128:9bcdf88f62b0 1670
<> 128:9bcdf88f62b0 1671 /**
<> 128:9bcdf88f62b0 1672 * @}
<> 128:9bcdf88f62b0 1673 */
<> 128:9bcdf88f62b0 1674
<> 128:9bcdf88f62b0 1675
<> 128:9bcdf88f62b0 1676 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 1677 * @{
<> 128:9bcdf88f62b0 1678 */
<> 128:9bcdf88f62b0 1679 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
<> 128:9bcdf88f62b0 1680 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
<> 128:9bcdf88f62b0 1681 /**
<> 128:9bcdf88f62b0 1682 * @}
<> 128:9bcdf88f62b0 1683 */
<> 128:9bcdf88f62b0 1684
<> 128:9bcdf88f62b0 1685
<> 128:9bcdf88f62b0 1686 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 1687 * @{
<> 128:9bcdf88f62b0 1688 */
<> 128:9bcdf88f62b0 1689
<> 128:9bcdf88f62b0 1690 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
<> 128:9bcdf88f62b0 1691 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
<> 128:9bcdf88f62b0 1692 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
<> 128:9bcdf88f62b0 1693
<> 128:9bcdf88f62b0 1694 /**
<> 128:9bcdf88f62b0 1695 * @}
<> 128:9bcdf88f62b0 1696 */
<> 128:9bcdf88f62b0 1697
<> 128:9bcdf88f62b0 1698
<> 128:9bcdf88f62b0 1699 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 1700 * @{
<> 128:9bcdf88f62b0 1701 */
<> 128:9bcdf88f62b0 1702 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
<> 128:9bcdf88f62b0 1703 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
<> 128:9bcdf88f62b0 1704 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
<> 128:9bcdf88f62b0 1705 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
<> 128:9bcdf88f62b0 1706 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
<> 128:9bcdf88f62b0 1707 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
<> 128:9bcdf88f62b0 1708 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
<> 128:9bcdf88f62b0 1709 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
<> 128:9bcdf88f62b0 1710 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
<> 128:9bcdf88f62b0 1711 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
<> 128:9bcdf88f62b0 1712 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
<> 128:9bcdf88f62b0 1713 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
<> 128:9bcdf88f62b0 1714 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
<> 128:9bcdf88f62b0 1715
<> 128:9bcdf88f62b0 1716 /**
<> 128:9bcdf88f62b0 1717 * @}
<> 128:9bcdf88f62b0 1718 */
<> 128:9bcdf88f62b0 1719
<> 128:9bcdf88f62b0 1720
<> 128:9bcdf88f62b0 1721 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 1722 * @{
<> 128:9bcdf88f62b0 1723 */
<> 128:9bcdf88f62b0 1724 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
<> 128:9bcdf88f62b0 1725 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
<> 128:9bcdf88f62b0 1726 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
<> 128:9bcdf88f62b0 1727 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
<> 128:9bcdf88f62b0 1728 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
<> 128:9bcdf88f62b0 1729 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
<> 128:9bcdf88f62b0 1730 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
<> 128:9bcdf88f62b0 1731 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
<> 128:9bcdf88f62b0 1732 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
<> 128:9bcdf88f62b0 1733 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
<> 128:9bcdf88f62b0 1734 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
<> 128:9bcdf88f62b0 1735 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
<> 128:9bcdf88f62b0 1736 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
<> 128:9bcdf88f62b0 1737 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
<> 128:9bcdf88f62b0 1738 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
<> 128:9bcdf88f62b0 1739 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
<> 128:9bcdf88f62b0 1740 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
<> 128:9bcdf88f62b0 1741 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
<> 128:9bcdf88f62b0 1742 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
<> 128:9bcdf88f62b0 1743 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
<> 128:9bcdf88f62b0 1744 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
<> 128:9bcdf88f62b0 1745 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
<> 128:9bcdf88f62b0 1746 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
<> 128:9bcdf88f62b0 1747 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
<> 128:9bcdf88f62b0 1748 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
<> 128:9bcdf88f62b0 1749 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
<> 128:9bcdf88f62b0 1750 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
<> 128:9bcdf88f62b0 1751 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
<> 128:9bcdf88f62b0 1752 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
<> 128:9bcdf88f62b0 1753 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
<> 128:9bcdf88f62b0 1754 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
<> 128:9bcdf88f62b0 1755 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
<> 128:9bcdf88f62b0 1756 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
<> 128:9bcdf88f62b0 1757 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
<> 128:9bcdf88f62b0 1758 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
<> 128:9bcdf88f62b0 1759
<> 128:9bcdf88f62b0 1760 #if defined (STM32F4)
<> 128:9bcdf88f62b0 1761 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
<> 128:9bcdf88f62b0 1762 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
<> 128:9bcdf88f62b0 1763 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
<> 128:9bcdf88f62b0 1764 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
<> 128:9bcdf88f62b0 1765 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
<> 128:9bcdf88f62b0 1766 #else
<> 128:9bcdf88f62b0 1767 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
<> 128:9bcdf88f62b0 1768 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
<> 128:9bcdf88f62b0 1769 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
<> 128:9bcdf88f62b0 1770 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
<> 128:9bcdf88f62b0 1771 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
<> 128:9bcdf88f62b0 1772 #endif /* STM32F4 */
<> 128:9bcdf88f62b0 1773 /**
<> 128:9bcdf88f62b0 1774 * @}
<> 128:9bcdf88f62b0 1775 */
<> 128:9bcdf88f62b0 1776
<> 128:9bcdf88f62b0 1777
<> 128:9bcdf88f62b0 1778 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
<> 128:9bcdf88f62b0 1779 * @{
<> 128:9bcdf88f62b0 1780 */
<> 128:9bcdf88f62b0 1781
<> 128:9bcdf88f62b0 1782 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
<> 128:9bcdf88f62b0 1783 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
<> 128:9bcdf88f62b0 1784
<> 128:9bcdf88f62b0 1785 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
<> 128:9bcdf88f62b0 1786 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
<> 128:9bcdf88f62b0 1787
<> 128:9bcdf88f62b0 1788 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
<> 128:9bcdf88f62b0 1789 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
<> 128:9bcdf88f62b0 1790 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1791 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1792 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
<> 128:9bcdf88f62b0 1793 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
<> 128:9bcdf88f62b0 1794 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
<> 128:9bcdf88f62b0 1795 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
<> 128:9bcdf88f62b0 1796 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
<> 128:9bcdf88f62b0 1797 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
<> 128:9bcdf88f62b0 1798 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1799 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1800 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
<> 128:9bcdf88f62b0 1801 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
<> 128:9bcdf88f62b0 1802 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
<> 128:9bcdf88f62b0 1803 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
<> 128:9bcdf88f62b0 1804 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
<> 128:9bcdf88f62b0 1805 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
<> 128:9bcdf88f62b0 1806 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
<> 128:9bcdf88f62b0 1807 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
<> 128:9bcdf88f62b0 1808 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
<> 128:9bcdf88f62b0 1809 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
<> 128:9bcdf88f62b0 1810 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1811 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1812 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
<> 128:9bcdf88f62b0 1813 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
<> 128:9bcdf88f62b0 1814 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1815 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1816 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
<> 128:9bcdf88f62b0 1817 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
<> 128:9bcdf88f62b0 1818 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
<> 128:9bcdf88f62b0 1819 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
<> 128:9bcdf88f62b0 1820 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
<> 128:9bcdf88f62b0 1821 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
<> 128:9bcdf88f62b0 1822 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
<> 128:9bcdf88f62b0 1823 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
<> 128:9bcdf88f62b0 1824 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
<> 128:9bcdf88f62b0 1825 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
<> 128:9bcdf88f62b0 1826 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
<> 128:9bcdf88f62b0 1827 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
<> 128:9bcdf88f62b0 1828 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
<> 128:9bcdf88f62b0 1829 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
<> 128:9bcdf88f62b0 1830 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
<> 128:9bcdf88f62b0 1831 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
<> 128:9bcdf88f62b0 1832 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
<> 128:9bcdf88f62b0 1833 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
<> 128:9bcdf88f62b0 1834 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
<> 128:9bcdf88f62b0 1835 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
<> 128:9bcdf88f62b0 1836 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
<> 128:9bcdf88f62b0 1837 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
<> 128:9bcdf88f62b0 1838 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
<> 128:9bcdf88f62b0 1839 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
<> 128:9bcdf88f62b0 1840 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
<> 128:9bcdf88f62b0 1841 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
<> 128:9bcdf88f62b0 1842 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1843 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1844 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
<> 128:9bcdf88f62b0 1845 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
<> 128:9bcdf88f62b0 1846 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
<> 128:9bcdf88f62b0 1847 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
<> 128:9bcdf88f62b0 1848 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
<> 128:9bcdf88f62b0 1849 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
<> 128:9bcdf88f62b0 1850 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
<> 128:9bcdf88f62b0 1851 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
<> 128:9bcdf88f62b0 1852 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
<> 128:9bcdf88f62b0 1853 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
<> 128:9bcdf88f62b0 1854 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
<> 128:9bcdf88f62b0 1855 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
<> 128:9bcdf88f62b0 1856 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
<> 128:9bcdf88f62b0 1857 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
<> 128:9bcdf88f62b0 1858 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
<> 128:9bcdf88f62b0 1859 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
<> 128:9bcdf88f62b0 1860 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1861 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1862 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
<> 128:9bcdf88f62b0 1863 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
<> 128:9bcdf88f62b0 1864 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
<> 128:9bcdf88f62b0 1865 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
<> 128:9bcdf88f62b0 1866 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1867 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1868 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
<> 128:9bcdf88f62b0 1869 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
<> 128:9bcdf88f62b0 1870 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
<> 128:9bcdf88f62b0 1871 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
<> 128:9bcdf88f62b0 1872 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
<> 128:9bcdf88f62b0 1873 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
<> 128:9bcdf88f62b0 1874 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
<> 128:9bcdf88f62b0 1875 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
<> 128:9bcdf88f62b0 1876 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1877 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1878 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
<> 128:9bcdf88f62b0 1879 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
<> 128:9bcdf88f62b0 1880 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
<> 128:9bcdf88f62b0 1881 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
<> 128:9bcdf88f62b0 1882 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
<> 128:9bcdf88f62b0 1883 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
<> 128:9bcdf88f62b0 1884 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
<> 128:9bcdf88f62b0 1885 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
<> 128:9bcdf88f62b0 1886 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1887 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1888 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
<> 128:9bcdf88f62b0 1889 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
<> 128:9bcdf88f62b0 1890 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
<> 128:9bcdf88f62b0 1891 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
<> 128:9bcdf88f62b0 1892 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1893 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1894 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
<> 128:9bcdf88f62b0 1895 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
<> 128:9bcdf88f62b0 1896 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
<> 128:9bcdf88f62b0 1897 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
<> 128:9bcdf88f62b0 1898 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1899 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1900 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
<> 128:9bcdf88f62b0 1901 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
<> 128:9bcdf88f62b0 1902 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
<> 128:9bcdf88f62b0 1903 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
<> 128:9bcdf88f62b0 1904 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
<> 128:9bcdf88f62b0 1905 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
<> 128:9bcdf88f62b0 1906 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
<> 128:9bcdf88f62b0 1907 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
<> 128:9bcdf88f62b0 1908 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
<> 128:9bcdf88f62b0 1909 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
<> 128:9bcdf88f62b0 1910 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
<> 128:9bcdf88f62b0 1911 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
<> 128:9bcdf88f62b0 1912 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
<> 128:9bcdf88f62b0 1913 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
<> 128:9bcdf88f62b0 1914 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1915 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1916 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
<> 128:9bcdf88f62b0 1917 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
<> 128:9bcdf88f62b0 1918 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
<> 128:9bcdf88f62b0 1919 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
<> 128:9bcdf88f62b0 1920 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
<> 128:9bcdf88f62b0 1921 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
<> 128:9bcdf88f62b0 1922 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1923 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1924 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
<> 128:9bcdf88f62b0 1925 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
<> 128:9bcdf88f62b0 1926 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1927 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1928 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
<> 128:9bcdf88f62b0 1929 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
<> 128:9bcdf88f62b0 1930 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
<> 128:9bcdf88f62b0 1931 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
<> 128:9bcdf88f62b0 1932 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
<> 128:9bcdf88f62b0 1933 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
<> 128:9bcdf88f62b0 1934 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1935 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1936 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
<> 128:9bcdf88f62b0 1937 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
<> 128:9bcdf88f62b0 1938 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
<> 128:9bcdf88f62b0 1939 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
<> 128:9bcdf88f62b0 1940 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1941 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1942 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
<> 128:9bcdf88f62b0 1943 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
<> 128:9bcdf88f62b0 1944 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
<> 128:9bcdf88f62b0 1945 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
<> 128:9bcdf88f62b0 1946 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1947 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1948 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
<> 128:9bcdf88f62b0 1949 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
<> 128:9bcdf88f62b0 1950 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
<> 128:9bcdf88f62b0 1951 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
<> 128:9bcdf88f62b0 1952 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1953 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1954 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
<> 128:9bcdf88f62b0 1955 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
<> 128:9bcdf88f62b0 1956 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
<> 128:9bcdf88f62b0 1957 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
<> 128:9bcdf88f62b0 1958 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1959 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1960 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
<> 128:9bcdf88f62b0 1961 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
<> 128:9bcdf88f62b0 1962 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
<> 128:9bcdf88f62b0 1963 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
<> 128:9bcdf88f62b0 1964 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1965 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1966 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
<> 128:9bcdf88f62b0 1967 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
<> 128:9bcdf88f62b0 1968 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
<> 128:9bcdf88f62b0 1969 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
<> 128:9bcdf88f62b0 1970 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1971 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1972 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
<> 128:9bcdf88f62b0 1973 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
<> 128:9bcdf88f62b0 1974 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
<> 128:9bcdf88f62b0 1975 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
<> 128:9bcdf88f62b0 1976 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1977 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1978 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
<> 128:9bcdf88f62b0 1979 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
<> 128:9bcdf88f62b0 1980 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
<> 128:9bcdf88f62b0 1981 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
<> 128:9bcdf88f62b0 1982 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1983 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1984 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
<> 128:9bcdf88f62b0 1985 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
<> 128:9bcdf88f62b0 1986 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
<> 128:9bcdf88f62b0 1987 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
<> 128:9bcdf88f62b0 1988 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1989 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1990 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
<> 128:9bcdf88f62b0 1991 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
<> 128:9bcdf88f62b0 1992 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
<> 128:9bcdf88f62b0 1993 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
<> 128:9bcdf88f62b0 1994 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 1995 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 1996 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
<> 128:9bcdf88f62b0 1997 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
<> 128:9bcdf88f62b0 1998 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
<> 128:9bcdf88f62b0 1999 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
<> 128:9bcdf88f62b0 2000 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2001 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2002 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
<> 128:9bcdf88f62b0 2003 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
<> 128:9bcdf88f62b0 2004 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
<> 128:9bcdf88f62b0 2005 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
<> 128:9bcdf88f62b0 2006 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2007 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2008 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
<> 128:9bcdf88f62b0 2009 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
<> 128:9bcdf88f62b0 2010 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
<> 128:9bcdf88f62b0 2011 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
<> 128:9bcdf88f62b0 2012 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2013 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2014 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
<> 128:9bcdf88f62b0 2015 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
<> 128:9bcdf88f62b0 2016 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
<> 128:9bcdf88f62b0 2017 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
<> 128:9bcdf88f62b0 2018 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2019 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2020 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
<> 128:9bcdf88f62b0 2021 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
<> 128:9bcdf88f62b0 2022 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
<> 128:9bcdf88f62b0 2023 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
<> 128:9bcdf88f62b0 2024 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2025 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2026 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
<> 128:9bcdf88f62b0 2027 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
<> 128:9bcdf88f62b0 2028 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
<> 128:9bcdf88f62b0 2029 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
<> 128:9bcdf88f62b0 2030 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2031 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2032 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
<> 128:9bcdf88f62b0 2033 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
<> 128:9bcdf88f62b0 2034 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
<> 128:9bcdf88f62b0 2035 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
<> 128:9bcdf88f62b0 2036 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2037 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2038 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
<> 128:9bcdf88f62b0 2039 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
<> 128:9bcdf88f62b0 2040 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
<> 128:9bcdf88f62b0 2041 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
<> 128:9bcdf88f62b0 2042 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2043 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2044 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
<> 128:9bcdf88f62b0 2045 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
<> 128:9bcdf88f62b0 2046 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
<> 128:9bcdf88f62b0 2047 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
<> 128:9bcdf88f62b0 2048 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2049 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2050 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
<> 128:9bcdf88f62b0 2051 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
<> 128:9bcdf88f62b0 2052 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
<> 128:9bcdf88f62b0 2053 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
<> 128:9bcdf88f62b0 2054 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2055 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2056 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
<> 128:9bcdf88f62b0 2057 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
<> 128:9bcdf88f62b0 2058 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
<> 128:9bcdf88f62b0 2059 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
<> 128:9bcdf88f62b0 2060 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2061 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2062 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
<> 128:9bcdf88f62b0 2063 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
<> 128:9bcdf88f62b0 2064 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
<> 128:9bcdf88f62b0 2065 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
<> 128:9bcdf88f62b0 2066 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
<> 128:9bcdf88f62b0 2067 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
<> 128:9bcdf88f62b0 2068 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2069 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2070 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
<> 128:9bcdf88f62b0 2071 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
<> 128:9bcdf88f62b0 2072 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
<> 128:9bcdf88f62b0 2073 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
<> 128:9bcdf88f62b0 2074 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2075 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2076 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
<> 128:9bcdf88f62b0 2077 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
<> 128:9bcdf88f62b0 2078 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
<> 128:9bcdf88f62b0 2079 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
<> 128:9bcdf88f62b0 2080 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2081 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2082 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
<> 128:9bcdf88f62b0 2083 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
<> 128:9bcdf88f62b0 2084 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
<> 128:9bcdf88f62b0 2085 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
<> 128:9bcdf88f62b0 2086 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2087 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2088 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
<> 128:9bcdf88f62b0 2089 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
<> 128:9bcdf88f62b0 2090 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
<> 128:9bcdf88f62b0 2091 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
<> 128:9bcdf88f62b0 2092 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2093 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2094 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2095 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2096 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
<> 128:9bcdf88f62b0 2097 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
<> 128:9bcdf88f62b0 2098 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2099 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2100 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
<> 128:9bcdf88f62b0 2101 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
<> 128:9bcdf88f62b0 2102 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
<> 128:9bcdf88f62b0 2103 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
<> 128:9bcdf88f62b0 2104 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2105 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2106 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
<> 128:9bcdf88f62b0 2107 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
<> 128:9bcdf88f62b0 2108 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
<> 128:9bcdf88f62b0 2109 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
<> 128:9bcdf88f62b0 2110 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2111 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2112 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
<> 128:9bcdf88f62b0 2113 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
<> 128:9bcdf88f62b0 2114 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
<> 128:9bcdf88f62b0 2115 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
<> 128:9bcdf88f62b0 2116 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
<> 128:9bcdf88f62b0 2117 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
<> 128:9bcdf88f62b0 2118 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
<> 128:9bcdf88f62b0 2119 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
<> 128:9bcdf88f62b0 2120 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
<> 128:9bcdf88f62b0 2121 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
<> 128:9bcdf88f62b0 2122 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
<> 128:9bcdf88f62b0 2123 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
<> 128:9bcdf88f62b0 2124 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
<> 128:9bcdf88f62b0 2125 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
<> 128:9bcdf88f62b0 2126 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
<> 128:9bcdf88f62b0 2127 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
<> 128:9bcdf88f62b0 2128 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
<> 128:9bcdf88f62b0 2129 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
<> 128:9bcdf88f62b0 2130 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
<> 128:9bcdf88f62b0 2131 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
<> 128:9bcdf88f62b0 2132 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
<> 128:9bcdf88f62b0 2133 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
<> 128:9bcdf88f62b0 2134 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
<> 128:9bcdf88f62b0 2135 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
<> 128:9bcdf88f62b0 2136 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2137 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2138 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
<> 128:9bcdf88f62b0 2139 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
<> 128:9bcdf88f62b0 2140 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
<> 128:9bcdf88f62b0 2141 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
<> 128:9bcdf88f62b0 2142 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2143 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2144 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
<> 128:9bcdf88f62b0 2145 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
<> 128:9bcdf88f62b0 2146 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
<> 128:9bcdf88f62b0 2147 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
<> 128:9bcdf88f62b0 2148 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2149 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2150 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
<> 128:9bcdf88f62b0 2151 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
<> 128:9bcdf88f62b0 2152 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
<> 128:9bcdf88f62b0 2153 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
<> 128:9bcdf88f62b0 2154 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2155 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2156 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
<> 128:9bcdf88f62b0 2157 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
<> 128:9bcdf88f62b0 2158 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
<> 128:9bcdf88f62b0 2159 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
<> 128:9bcdf88f62b0 2160 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2161 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2162 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
<> 128:9bcdf88f62b0 2163 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
<> 128:9bcdf88f62b0 2164 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
<> 128:9bcdf88f62b0 2165 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
<> 128:9bcdf88f62b0 2166 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2167 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2168 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
<> 128:9bcdf88f62b0 2169 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
<> 128:9bcdf88f62b0 2170 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
<> 128:9bcdf88f62b0 2171 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
<> 128:9bcdf88f62b0 2172 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2173 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2174 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
<> 128:9bcdf88f62b0 2175 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
<> 128:9bcdf88f62b0 2176 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
<> 128:9bcdf88f62b0 2177 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
<> 128:9bcdf88f62b0 2178 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2179 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2180 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
<> 128:9bcdf88f62b0 2181 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
<> 128:9bcdf88f62b0 2182 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
<> 128:9bcdf88f62b0 2183 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
<> 128:9bcdf88f62b0 2184 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2185 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2186 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
<> 128:9bcdf88f62b0 2187 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
<> 128:9bcdf88f62b0 2188 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
<> 128:9bcdf88f62b0 2189 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
<> 128:9bcdf88f62b0 2190 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2191 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2192 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
<> 128:9bcdf88f62b0 2193 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
<> 128:9bcdf88f62b0 2194 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
<> 128:9bcdf88f62b0 2195 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
<> 128:9bcdf88f62b0 2196 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
<> 128:9bcdf88f62b0 2197 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
<> 128:9bcdf88f62b0 2198 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
<> 128:9bcdf88f62b0 2199 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
<> 128:9bcdf88f62b0 2200 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2201 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2202 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
<> 128:9bcdf88f62b0 2203 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
<> 128:9bcdf88f62b0 2204 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
<> 128:9bcdf88f62b0 2205 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
<> 128:9bcdf88f62b0 2206 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2207 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2208 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
<> 128:9bcdf88f62b0 2209 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
<> 128:9bcdf88f62b0 2210 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
<> 128:9bcdf88f62b0 2211 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
<> 128:9bcdf88f62b0 2212 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2213 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2214 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
<> 128:9bcdf88f62b0 2215 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
<> 128:9bcdf88f62b0 2216 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
<> 128:9bcdf88f62b0 2217 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
<> 128:9bcdf88f62b0 2218 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2219 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2220 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
<> 128:9bcdf88f62b0 2221 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
<> 128:9bcdf88f62b0 2222 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
<> 128:9bcdf88f62b0 2223 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
<> 128:9bcdf88f62b0 2224 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2225 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2226 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
<> 128:9bcdf88f62b0 2227 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
<> 128:9bcdf88f62b0 2228 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
<> 128:9bcdf88f62b0 2229 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
<> 128:9bcdf88f62b0 2230 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2231 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2232 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
<> 128:9bcdf88f62b0 2233 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
<> 134:ad3be0349dc5 2234 #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
<> 134:ad3be0349dc5 2235 #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
<> 134:ad3be0349dc5 2236 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
<> 134:ad3be0349dc5 2237 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
<> 134:ad3be0349dc5 2238 #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
<> 134:ad3be0349dc5 2239 #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
<> 134:ad3be0349dc5 2240 #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
<> 134:ad3be0349dc5 2241 #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
<> 134:ad3be0349dc5 2242 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
<> 134:ad3be0349dc5 2243 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
<> 134:ad3be0349dc5 2244 #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
<> 134:ad3be0349dc5 2245 #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
<> 134:ad3be0349dc5 2246 #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
<> 134:ad3be0349dc5 2247 #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
<> 134:ad3be0349dc5 2248 #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
<> 134:ad3be0349dc5 2249 #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
<> 134:ad3be0349dc5 2250 #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
<> 134:ad3be0349dc5 2251 #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
<> 134:ad3be0349dc5 2252 #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
<> 134:ad3be0349dc5 2253 #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
<> 128:9bcdf88f62b0 2254 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
<> 128:9bcdf88f62b0 2255 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
<> 128:9bcdf88f62b0 2256 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
<> 128:9bcdf88f62b0 2257 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2258 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2259 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
<> 128:9bcdf88f62b0 2260 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
<> 128:9bcdf88f62b0 2261 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
<> 128:9bcdf88f62b0 2262 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
<> 128:9bcdf88f62b0 2263 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
<> 128:9bcdf88f62b0 2264 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2265 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2266 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
<> 128:9bcdf88f62b0 2267 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
<> 128:9bcdf88f62b0 2268 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
<> 128:9bcdf88f62b0 2269 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
<> 128:9bcdf88f62b0 2270 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
<> 128:9bcdf88f62b0 2271 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
<> 128:9bcdf88f62b0 2272 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2273 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2274 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
<> 128:9bcdf88f62b0 2275 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
<> 128:9bcdf88f62b0 2276 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
<> 128:9bcdf88f62b0 2277 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
<> 128:9bcdf88f62b0 2278 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2279 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2280 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
<> 128:9bcdf88f62b0 2281 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
<> 128:9bcdf88f62b0 2282 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2283 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2284 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
<> 128:9bcdf88f62b0 2285 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
<> 128:9bcdf88f62b0 2286 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
<> 128:9bcdf88f62b0 2287 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
<> 128:9bcdf88f62b0 2288
<> 128:9bcdf88f62b0 2289 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
<> 128:9bcdf88f62b0 2290 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
<> 128:9bcdf88f62b0 2291 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2292 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2293 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
<> 128:9bcdf88f62b0 2294 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
<> 128:9bcdf88f62b0 2295 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
<> 128:9bcdf88f62b0 2296 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
<> 128:9bcdf88f62b0 2297 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2298 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2299 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2300 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2301 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2302 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2303 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2304 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2305 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
<> 128:9bcdf88f62b0 2306 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
<> 128:9bcdf88f62b0 2307 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
<> 128:9bcdf88f62b0 2308 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
<> 128:9bcdf88f62b0 2309 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
<> 128:9bcdf88f62b0 2310 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2311 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2312 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
<> 128:9bcdf88f62b0 2313 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
<> 128:9bcdf88f62b0 2314 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
<> 128:9bcdf88f62b0 2315 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
<> 128:9bcdf88f62b0 2316 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
<> 128:9bcdf88f62b0 2317 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2318 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2319 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
<> 128:9bcdf88f62b0 2320 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
<> 128:9bcdf88f62b0 2321 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
<> 128:9bcdf88f62b0 2322 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
<> 128:9bcdf88f62b0 2323 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2324 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2325 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
<> 128:9bcdf88f62b0 2326 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
<> 128:9bcdf88f62b0 2327 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
<> 128:9bcdf88f62b0 2328 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
<> 128:9bcdf88f62b0 2329 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2330 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2331 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2332 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2333 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2334 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2335 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2336 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2337 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2338 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2339 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2340 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2341 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2342 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
<> 128:9bcdf88f62b0 2343 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
<> 128:9bcdf88f62b0 2344 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2345 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2346 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
<> 128:9bcdf88f62b0 2347 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
<> 128:9bcdf88f62b0 2348 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
<> 128:9bcdf88f62b0 2349 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
<> 128:9bcdf88f62b0 2350 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
<> 128:9bcdf88f62b0 2351 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
<> 128:9bcdf88f62b0 2352 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2353 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2354 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
<> 128:9bcdf88f62b0 2355 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
<> 128:9bcdf88f62b0 2356 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
<> 128:9bcdf88f62b0 2357 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
<> 128:9bcdf88f62b0 2358 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2359 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2360 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
<> 128:9bcdf88f62b0 2361 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
<> 128:9bcdf88f62b0 2362 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
<> 128:9bcdf88f62b0 2363 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
<> 128:9bcdf88f62b0 2364 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2365 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2366 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
<> 128:9bcdf88f62b0 2367 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
<> 128:9bcdf88f62b0 2368 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
<> 128:9bcdf88f62b0 2369 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
<> 128:9bcdf88f62b0 2370 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2371 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2372 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
<> 128:9bcdf88f62b0 2373 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
<> 128:9bcdf88f62b0 2374 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
<> 128:9bcdf88f62b0 2375 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2376 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2377 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
<> 128:9bcdf88f62b0 2378 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
<> 128:9bcdf88f62b0 2379 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
<> 128:9bcdf88f62b0 2380 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
<> 128:9bcdf88f62b0 2381 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
<> 128:9bcdf88f62b0 2382 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
<> 128:9bcdf88f62b0 2383 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2384 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2385 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
<> 128:9bcdf88f62b0 2386 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
<> 128:9bcdf88f62b0 2387 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
<> 128:9bcdf88f62b0 2388 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
<> 128:9bcdf88f62b0 2389 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2390 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2391 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
<> 128:9bcdf88f62b0 2392 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
<> 128:9bcdf88f62b0 2393 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
<> 128:9bcdf88f62b0 2394 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
<> 128:9bcdf88f62b0 2395 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2396 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2397 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2398 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2399 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
<> 128:9bcdf88f62b0 2400 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
<> 128:9bcdf88f62b0 2401 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2402 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2403 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2404 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2405 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
<> 128:9bcdf88f62b0 2406 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
<> 128:9bcdf88f62b0 2407 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
<> 128:9bcdf88f62b0 2408 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
<> 128:9bcdf88f62b0 2409 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2410 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2411 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
<> 128:9bcdf88f62b0 2412 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
<> 128:9bcdf88f62b0 2413 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
<> 128:9bcdf88f62b0 2414 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2415 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2416 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2417 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2418 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2419 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2420 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2421 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2422 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2423 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
<> 128:9bcdf88f62b0 2424 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
<> 128:9bcdf88f62b0 2425 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2426 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2427 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
<> 128:9bcdf88f62b0 2428 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
<> 128:9bcdf88f62b0 2429 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2430 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2431 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
<> 128:9bcdf88f62b0 2432 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
<> 128:9bcdf88f62b0 2433 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
<> 128:9bcdf88f62b0 2434 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
<> 128:9bcdf88f62b0 2435 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2436 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2437
<> 128:9bcdf88f62b0 2438 /* alias define maintained for legacy */
<> 128:9bcdf88f62b0 2439 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
<> 128:9bcdf88f62b0 2440 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
<> 128:9bcdf88f62b0 2441
<> 128:9bcdf88f62b0 2442 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
<> 128:9bcdf88f62b0 2443 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
<> 128:9bcdf88f62b0 2444 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
<> 128:9bcdf88f62b0 2445 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
<> 128:9bcdf88f62b0 2446 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
<> 128:9bcdf88f62b0 2447 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
<> 128:9bcdf88f62b0 2448 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
<> 128:9bcdf88f62b0 2449 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
<> 128:9bcdf88f62b0 2450 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
<> 128:9bcdf88f62b0 2451 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
<> 128:9bcdf88f62b0 2452 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
<> 128:9bcdf88f62b0 2453 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
<> 128:9bcdf88f62b0 2454 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
<> 128:9bcdf88f62b0 2455 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
<> 128:9bcdf88f62b0 2456 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
<> 128:9bcdf88f62b0 2457 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
<> 128:9bcdf88f62b0 2458 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
<> 128:9bcdf88f62b0 2459 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
<> 128:9bcdf88f62b0 2460 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
<> 128:9bcdf88f62b0 2461 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
<> 128:9bcdf88f62b0 2462 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
<> 128:9bcdf88f62b0 2463 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
<> 128:9bcdf88f62b0 2464
<> 128:9bcdf88f62b0 2465 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
<> 128:9bcdf88f62b0 2466 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
<> 128:9bcdf88f62b0 2467 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
<> 128:9bcdf88f62b0 2468 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
<> 128:9bcdf88f62b0 2469 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
<> 128:9bcdf88f62b0 2470 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
<> 128:9bcdf88f62b0 2471 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
<> 128:9bcdf88f62b0 2472 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
<> 128:9bcdf88f62b0 2473 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
<> 128:9bcdf88f62b0 2474 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
<> 128:9bcdf88f62b0 2475 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
<> 128:9bcdf88f62b0 2476 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
<> 128:9bcdf88f62b0 2477 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
<> 128:9bcdf88f62b0 2478 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
<> 128:9bcdf88f62b0 2479 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
<> 128:9bcdf88f62b0 2480 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
<> 128:9bcdf88f62b0 2481 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
<> 128:9bcdf88f62b0 2482 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
<> 128:9bcdf88f62b0 2483 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
<> 128:9bcdf88f62b0 2484 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
<> 128:9bcdf88f62b0 2485 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
<> 128:9bcdf88f62b0 2486 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
<> 128:9bcdf88f62b0 2487
<> 128:9bcdf88f62b0 2488 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2489 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2490 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2491 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2492 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2493 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2494 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2495 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2496 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2497 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2498 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2499 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2500 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2501 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2502 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2503 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2504 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2505 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2506 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2507 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2508 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2509 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2510 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2511 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2512 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2513 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2514 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2515 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2516 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2517 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2518 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2519 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2520 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2521 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2522 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2523 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2524 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2525 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2526 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2527 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2528 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2529 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2530 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2531 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2532 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2533 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2534 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2535 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2536 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2537 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2538 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2539 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2540 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2541 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2542 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2543 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2544 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2545 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2546 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2547 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2548 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2549 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2550 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2551 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2552 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2553 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2554 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2555 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2556 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2557 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2558 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2559 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2560 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2561 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2562 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2563 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2564 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2565 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2566 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2567 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2568 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2569 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2570 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2571 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2572 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2573 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2574 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2575 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2576 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2577 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2578 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2579 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2580 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2581 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2582 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2583 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2584 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2585 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2586 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2587 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2588 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2589 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2590 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2591 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2592 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2593 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2594 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2595 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2596 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2597 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2598 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2599 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2600 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2601 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2602 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2603 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2604
<> 128:9bcdf88f62b0 2605 #if defined(STM32F4)
<> 128:9bcdf88f62b0 2606 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
<> 128:9bcdf88f62b0 2607 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
<> 128:9bcdf88f62b0 2608 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2609 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2610 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
<> 128:9bcdf88f62b0 2611 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
<> 128:9bcdf88f62b0 2612 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2613 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2614 #define Sdmmc1ClockSelection SdioClockSelection
<> 128:9bcdf88f62b0 2615 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
<> 128:9bcdf88f62b0 2616 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
<> 128:9bcdf88f62b0 2617 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
<> 128:9bcdf88f62b0 2618 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
<> 128:9bcdf88f62b0 2619 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
<> 128:9bcdf88f62b0 2620 #endif
<> 128:9bcdf88f62b0 2621
<> 128:9bcdf88f62b0 2622 #if defined(STM32F7) || defined(STM32L4)
<> 128:9bcdf88f62b0 2623 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
<> 128:9bcdf88f62b0 2624 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
<> 128:9bcdf88f62b0 2625 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2626 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2627 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
<> 128:9bcdf88f62b0 2628 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
<> 128:9bcdf88f62b0 2629 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2630 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2631 #define SdioClockSelection Sdmmc1ClockSelection
<> 128:9bcdf88f62b0 2632 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
<> 128:9bcdf88f62b0 2633 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
<> 128:9bcdf88f62b0 2634 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
<> 128:9bcdf88f62b0 2635 #endif
<> 128:9bcdf88f62b0 2636
<> 128:9bcdf88f62b0 2637 #if defined(STM32F7)
<> 128:9bcdf88f62b0 2638 #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
<> 128:9bcdf88f62b0 2639 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
<> 128:9bcdf88f62b0 2640 #endif
<> 128:9bcdf88f62b0 2641
<> 128:9bcdf88f62b0 2642 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
<> 128:9bcdf88f62b0 2643 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
<> 128:9bcdf88f62b0 2644
<> 128:9bcdf88f62b0 2645 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
<> 128:9bcdf88f62b0 2646
<> 128:9bcdf88f62b0 2647 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
<> 128:9bcdf88f62b0 2648 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
<> 128:9bcdf88f62b0 2649 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
<> 128:9bcdf88f62b0 2650 #define IS_RCC_HCLK_DIV IS_RCC_PCLK
<> 128:9bcdf88f62b0 2651 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
<> 128:9bcdf88f62b0 2652
<> 128:9bcdf88f62b0 2653 #define RCC_IT_HSI14 RCC_IT_HSI14RDY
<> 128:9bcdf88f62b0 2654
<> 134:ad3be0349dc5 2655 #define RCC_IT_CSSLSE RCC_IT_LSECSS
<> 134:ad3be0349dc5 2656 #define RCC_IT_CSSHSE RCC_IT_CSS
<> 134:ad3be0349dc5 2657
<> 134:ad3be0349dc5 2658 #define RCC_PLLMUL_3 RCC_PLL_MUL3
<> 134:ad3be0349dc5 2659 #define RCC_PLLMUL_4 RCC_PLL_MUL4
<> 134:ad3be0349dc5 2660 #define RCC_PLLMUL_6 RCC_PLL_MUL6
<> 134:ad3be0349dc5 2661 #define RCC_PLLMUL_8 RCC_PLL_MUL8
<> 134:ad3be0349dc5 2662 #define RCC_PLLMUL_12 RCC_PLL_MUL12
<> 134:ad3be0349dc5 2663 #define RCC_PLLMUL_16 RCC_PLL_MUL16
<> 134:ad3be0349dc5 2664 #define RCC_PLLMUL_24 RCC_PLL_MUL24
<> 134:ad3be0349dc5 2665 #define RCC_PLLMUL_32 RCC_PLL_MUL32
<> 134:ad3be0349dc5 2666 #define RCC_PLLMUL_48 RCC_PLL_MUL48
<> 134:ad3be0349dc5 2667
<> 134:ad3be0349dc5 2668 #define RCC_PLLDIV_2 RCC_PLL_DIV2
<> 134:ad3be0349dc5 2669 #define RCC_PLLDIV_3 RCC_PLL_DIV3
<> 134:ad3be0349dc5 2670 #define RCC_PLLDIV_4 RCC_PLL_DIV4
<> 128:9bcdf88f62b0 2671
<> 128:9bcdf88f62b0 2672 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
<> 128:9bcdf88f62b0 2673 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
<> 128:9bcdf88f62b0 2674 #define RCC_MCO_NODIV RCC_MCODIV_1
<> 128:9bcdf88f62b0 2675 #define RCC_MCO_DIV1 RCC_MCODIV_1
<> 128:9bcdf88f62b0 2676 #define RCC_MCO_DIV2 RCC_MCODIV_2
<> 128:9bcdf88f62b0 2677 #define RCC_MCO_DIV4 RCC_MCODIV_4
<> 128:9bcdf88f62b0 2678 #define RCC_MCO_DIV8 RCC_MCODIV_8
<> 128:9bcdf88f62b0 2679 #define RCC_MCO_DIV16 RCC_MCODIV_16
<> 128:9bcdf88f62b0 2680 #define RCC_MCO_DIV32 RCC_MCODIV_32
<> 128:9bcdf88f62b0 2681 #define RCC_MCO_DIV64 RCC_MCODIV_64
<> 128:9bcdf88f62b0 2682 #define RCC_MCO_DIV128 RCC_MCODIV_128
<> 128:9bcdf88f62b0 2683 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
<> 128:9bcdf88f62b0 2684 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
<> 128:9bcdf88f62b0 2685 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
<> 128:9bcdf88f62b0 2686 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
<> 128:9bcdf88f62b0 2687 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
<> 128:9bcdf88f62b0 2688 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
<> 128:9bcdf88f62b0 2689 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
<> 128:9bcdf88f62b0 2690 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
<> 128:9bcdf88f62b0 2691 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
<> 128:9bcdf88f62b0 2692 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
<> 128:9bcdf88f62b0 2693 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
<> 128:9bcdf88f62b0 2694
<> 128:9bcdf88f62b0 2695 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
<> 128:9bcdf88f62b0 2696
<> 128:9bcdf88f62b0 2697 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
<> 128:9bcdf88f62b0 2698 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
<> 128:9bcdf88f62b0 2699 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
<> 128:9bcdf88f62b0 2700 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
<> 128:9bcdf88f62b0 2701 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
<> 128:9bcdf88f62b0 2702 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
<> 128:9bcdf88f62b0 2703 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
<> 128:9bcdf88f62b0 2704 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
<> 128:9bcdf88f62b0 2705
<> 128:9bcdf88f62b0 2706 #define HSION_BitNumber RCC_HSION_BIT_NUMBER
<> 128:9bcdf88f62b0 2707 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
<> 128:9bcdf88f62b0 2708 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
<> 128:9bcdf88f62b0 2709 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
<> 128:9bcdf88f62b0 2710 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
<> 128:9bcdf88f62b0 2711 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
<> 128:9bcdf88f62b0 2712 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
<> 128:9bcdf88f62b0 2713 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
<> 128:9bcdf88f62b0 2714 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
<> 128:9bcdf88f62b0 2715 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
<> 128:9bcdf88f62b0 2716 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
<> 128:9bcdf88f62b0 2717 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
<> 128:9bcdf88f62b0 2718 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
<> 128:9bcdf88f62b0 2719 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
<> 128:9bcdf88f62b0 2720 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
<> 128:9bcdf88f62b0 2721 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
<> 128:9bcdf88f62b0 2722 #define LSION_BitNumber RCC_LSION_BIT_NUMBER
<> 128:9bcdf88f62b0 2723 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
<> 128:9bcdf88f62b0 2724 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
<> 128:9bcdf88f62b0 2725 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
<> 128:9bcdf88f62b0 2726 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
<> 128:9bcdf88f62b0 2727 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
<> 128:9bcdf88f62b0 2728 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
<> 128:9bcdf88f62b0 2729 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
<> 128:9bcdf88f62b0 2730 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
<> 128:9bcdf88f62b0 2731 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
<> 128:9bcdf88f62b0 2732 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
<> 128:9bcdf88f62b0 2733 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
<> 128:9bcdf88f62b0 2734 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
<> 128:9bcdf88f62b0 2735 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
<> 128:9bcdf88f62b0 2736 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
<> 128:9bcdf88f62b0 2737 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
<> 128:9bcdf88f62b0 2738
<> 128:9bcdf88f62b0 2739 #define CR_HSION_BB RCC_CR_HSION_BB
<> 128:9bcdf88f62b0 2740 #define CR_CSSON_BB RCC_CR_CSSON_BB
<> 128:9bcdf88f62b0 2741 #define CR_PLLON_BB RCC_CR_PLLON_BB
<> 128:9bcdf88f62b0 2742 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
<> 128:9bcdf88f62b0 2743 #define CR_MSION_BB RCC_CR_MSION_BB
<> 128:9bcdf88f62b0 2744 #define CSR_LSION_BB RCC_CSR_LSION_BB
<> 128:9bcdf88f62b0 2745 #define CSR_LSEON_BB RCC_CSR_LSEON_BB
<> 128:9bcdf88f62b0 2746 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
<> 128:9bcdf88f62b0 2747 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
<> 128:9bcdf88f62b0 2748 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
<> 128:9bcdf88f62b0 2749 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
<> 128:9bcdf88f62b0 2750 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
<> 128:9bcdf88f62b0 2751 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
<> 128:9bcdf88f62b0 2752 #define CR_HSEON_BB RCC_CR_HSEON_BB
<> 128:9bcdf88f62b0 2753 #define CSR_RMVF_BB RCC_CSR_RMVF_BB
<> 128:9bcdf88f62b0 2754 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
<> 128:9bcdf88f62b0 2755 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
<> 128:9bcdf88f62b0 2756
<> 128:9bcdf88f62b0 2757 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
<> 128:9bcdf88f62b0 2758 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
<> 128:9bcdf88f62b0 2759 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
<> 128:9bcdf88f62b0 2760 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
<> 128:9bcdf88f62b0 2761 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
<> 128:9bcdf88f62b0 2762
<> 128:9bcdf88f62b0 2763 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
<> 128:9bcdf88f62b0 2764
<> 128:9bcdf88f62b0 2765 #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
<> 128:9bcdf88f62b0 2766 #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
<> 128:9bcdf88f62b0 2767
<> 128:9bcdf88f62b0 2768 #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
<> 128:9bcdf88f62b0 2769 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
<> 128:9bcdf88f62b0 2770 #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
<> 128:9bcdf88f62b0 2771 #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
<> 128:9bcdf88f62b0 2772 #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
<> 128:9bcdf88f62b0 2773 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
<> 128:9bcdf88f62b0 2774
<> 128:9bcdf88f62b0 2775 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
<> 128:9bcdf88f62b0 2776 #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
<> 128:9bcdf88f62b0 2777 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
<> 128:9bcdf88f62b0 2778 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
<> 128:9bcdf88f62b0 2779 #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
<> 128:9bcdf88f62b0 2780 #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
<> 128:9bcdf88f62b0 2781 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
<> 128:9bcdf88f62b0 2782 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
<> 128:9bcdf88f62b0 2783 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
<> 128:9bcdf88f62b0 2784 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
<> 128:9bcdf88f62b0 2785 #define DfsdmClockSelection Dfsdm1ClockSelection
<> 128:9bcdf88f62b0 2786 #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
<> 128:9bcdf88f62b0 2787 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
<> 128:9bcdf88f62b0 2788 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
<> 128:9bcdf88f62b0 2789 #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
<> 128:9bcdf88f62b0 2790 #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
<> 128:9bcdf88f62b0 2791
<> 128:9bcdf88f62b0 2792 /**
<> 128:9bcdf88f62b0 2793 * @}
<> 128:9bcdf88f62b0 2794 */
<> 128:9bcdf88f62b0 2795
<> 128:9bcdf88f62b0 2796 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 2797 * @{
<> 128:9bcdf88f62b0 2798 */
<> 128:9bcdf88f62b0 2799 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
<> 128:9bcdf88f62b0 2800
<> 128:9bcdf88f62b0 2801 /**
<> 128:9bcdf88f62b0 2802 * @}
<> 128:9bcdf88f62b0 2803 */
<> 128:9bcdf88f62b0 2804
<> 128:9bcdf88f62b0 2805 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 2806 * @{
<> 128:9bcdf88f62b0 2807 */
<> 128:9bcdf88f62b0 2808
<> 128:9bcdf88f62b0 2809 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
<> 128:9bcdf88f62b0 2810 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
<> 128:9bcdf88f62b0 2811 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
<> 128:9bcdf88f62b0 2812
<> 128:9bcdf88f62b0 2813 #if defined (STM32F1)
<> 128:9bcdf88f62b0 2814 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
<> 128:9bcdf88f62b0 2815
<> 128:9bcdf88f62b0 2816 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
<> 128:9bcdf88f62b0 2817
<> 128:9bcdf88f62b0 2818 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
<> 128:9bcdf88f62b0 2819
<> 128:9bcdf88f62b0 2820 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
<> 128:9bcdf88f62b0 2821
<> 128:9bcdf88f62b0 2822 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
<> 128:9bcdf88f62b0 2823 #else
<> 128:9bcdf88f62b0 2824 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
<> 128:9bcdf88f62b0 2825 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
<> 128:9bcdf88f62b0 2826 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
<> 128:9bcdf88f62b0 2827 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
<> 128:9bcdf88f62b0 2828 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
<> 128:9bcdf88f62b0 2829 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
<> 128:9bcdf88f62b0 2830 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
<> 128:9bcdf88f62b0 2831 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
<> 128:9bcdf88f62b0 2832 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
<> 128:9bcdf88f62b0 2833 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
<> 128:9bcdf88f62b0 2834 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
<> 128:9bcdf88f62b0 2835 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
<> 128:9bcdf88f62b0 2836 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
<> 128:9bcdf88f62b0 2837 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
<> 128:9bcdf88f62b0 2838 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
<> 128:9bcdf88f62b0 2839 #endif /* STM32F1 */
<> 128:9bcdf88f62b0 2840
<> 128:9bcdf88f62b0 2841 #define IS_ALARM IS_RTC_ALARM
<> 128:9bcdf88f62b0 2842 #define IS_ALARM_MASK IS_RTC_ALARM_MASK
<> 128:9bcdf88f62b0 2843 #define IS_TAMPER IS_RTC_TAMPER
<> 128:9bcdf88f62b0 2844 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
<> 128:9bcdf88f62b0 2845 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
<> 128:9bcdf88f62b0 2846 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
<> 128:9bcdf88f62b0 2847 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
<> 128:9bcdf88f62b0 2848 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
<> 128:9bcdf88f62b0 2849 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
<> 128:9bcdf88f62b0 2850 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
<> 128:9bcdf88f62b0 2851 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
<> 128:9bcdf88f62b0 2852 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
<> 128:9bcdf88f62b0 2853 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
<> 128:9bcdf88f62b0 2854 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
<> 128:9bcdf88f62b0 2855
<> 128:9bcdf88f62b0 2856 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
<> 128:9bcdf88f62b0 2857 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
<> 128:9bcdf88f62b0 2858
<> 128:9bcdf88f62b0 2859 /**
<> 128:9bcdf88f62b0 2860 * @}
<> 128:9bcdf88f62b0 2861 */
<> 128:9bcdf88f62b0 2862
<> 128:9bcdf88f62b0 2863 /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 2864 * @{
<> 128:9bcdf88f62b0 2865 */
<> 128:9bcdf88f62b0 2866
<> 128:9bcdf88f62b0 2867 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
<> 128:9bcdf88f62b0 2868 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
<> 128:9bcdf88f62b0 2869
<> 128:9bcdf88f62b0 2870 #if defined(STM32F4)
<> 128:9bcdf88f62b0 2871 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED
<> 128:9bcdf88f62b0 2872 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
<> 128:9bcdf88f62b0 2873 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
<> 128:9bcdf88f62b0 2874 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
<> 128:9bcdf88f62b0 2875 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
<> 128:9bcdf88f62b0 2876 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
<> 128:9bcdf88f62b0 2877 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
<> 128:9bcdf88f62b0 2878 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
<> 128:9bcdf88f62b0 2879 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
<> 128:9bcdf88f62b0 2880 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
<> 128:9bcdf88f62b0 2881 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
<> 128:9bcdf88f62b0 2882 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
<> 128:9bcdf88f62b0 2883 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
<> 128:9bcdf88f62b0 2884 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
<> 128:9bcdf88f62b0 2885 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
<> 128:9bcdf88f62b0 2886 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
<> 128:9bcdf88f62b0 2887 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
<> 128:9bcdf88f62b0 2888 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
<> 128:9bcdf88f62b0 2889 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
<> 128:9bcdf88f62b0 2890 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
<> 128:9bcdf88f62b0 2891 /* alias CMSIS */
<> 128:9bcdf88f62b0 2892 #define SDMMC1_IRQn SDIO_IRQn
<> 128:9bcdf88f62b0 2893 #define SDMMC1_IRQHandler SDIO_IRQHandler
<> 128:9bcdf88f62b0 2894 #endif
<> 128:9bcdf88f62b0 2895
<> 128:9bcdf88f62b0 2896 #if defined(STM32F7) || defined(STM32L4)
<> 128:9bcdf88f62b0 2897 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED
<> 128:9bcdf88f62b0 2898 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
<> 128:9bcdf88f62b0 2899 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
<> 128:9bcdf88f62b0 2900 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
<> 128:9bcdf88f62b0 2901 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
<> 128:9bcdf88f62b0 2902 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
<> 128:9bcdf88f62b0 2903 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
<> 128:9bcdf88f62b0 2904 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
<> 128:9bcdf88f62b0 2905 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
<> 128:9bcdf88f62b0 2906 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
<> 128:9bcdf88f62b0 2907 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
<> 128:9bcdf88f62b0 2908 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
<> 128:9bcdf88f62b0 2909 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
<> 128:9bcdf88f62b0 2910 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
<> 128:9bcdf88f62b0 2911 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
<> 128:9bcdf88f62b0 2912 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
<> 128:9bcdf88f62b0 2913 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
<> 128:9bcdf88f62b0 2914 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
<> 128:9bcdf88f62b0 2915 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
<> 128:9bcdf88f62b0 2916 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
<> 128:9bcdf88f62b0 2917 /* alias CMSIS for compatibilities */
<> 128:9bcdf88f62b0 2918 #define SDIO_IRQn SDMMC1_IRQn
<> 128:9bcdf88f62b0 2919 #define SDIO_IRQHandler SDMMC1_IRQHandler
<> 128:9bcdf88f62b0 2920 #endif
<> 128:9bcdf88f62b0 2921 /**
<> 128:9bcdf88f62b0 2922 * @}
<> 128:9bcdf88f62b0 2923 */
<> 128:9bcdf88f62b0 2924
<> 128:9bcdf88f62b0 2925 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 2926 * @{
<> 128:9bcdf88f62b0 2927 */
<> 128:9bcdf88f62b0 2928
<> 128:9bcdf88f62b0 2929 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
<> 128:9bcdf88f62b0 2930 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
<> 128:9bcdf88f62b0 2931 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
<> 128:9bcdf88f62b0 2932 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
<> 128:9bcdf88f62b0 2933 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
<> 128:9bcdf88f62b0 2934 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
<> 128:9bcdf88f62b0 2935
<> 128:9bcdf88f62b0 2936 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
<> 128:9bcdf88f62b0 2937 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
<> 128:9bcdf88f62b0 2938
<> 128:9bcdf88f62b0 2939 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
<> 128:9bcdf88f62b0 2940
<> 128:9bcdf88f62b0 2941 /**
<> 128:9bcdf88f62b0 2942 * @}
<> 128:9bcdf88f62b0 2943 */
<> 128:9bcdf88f62b0 2944
<> 128:9bcdf88f62b0 2945 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 2946 * @{
<> 128:9bcdf88f62b0 2947 */
<> 128:9bcdf88f62b0 2948 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
<> 128:9bcdf88f62b0 2949 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
<> 128:9bcdf88f62b0 2950 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
<> 128:9bcdf88f62b0 2951 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
<> 128:9bcdf88f62b0 2952 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
<> 128:9bcdf88f62b0 2953 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
<> 128:9bcdf88f62b0 2954 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
<> 128:9bcdf88f62b0 2955 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
<> 128:9bcdf88f62b0 2956 /**
<> 128:9bcdf88f62b0 2957 * @}
<> 128:9bcdf88f62b0 2958 */
<> 128:9bcdf88f62b0 2959
<> 128:9bcdf88f62b0 2960 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 2961 * @{
<> 128:9bcdf88f62b0 2962 */
<> 128:9bcdf88f62b0 2963
<> 128:9bcdf88f62b0 2964 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX
<> 128:9bcdf88f62b0 2965 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX
<> 128:9bcdf88f62b0 2966 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC
<> 128:9bcdf88f62b0 2967
<> 128:9bcdf88f62b0 2968 /**
<> 128:9bcdf88f62b0 2969 * @}
<> 128:9bcdf88f62b0 2970 */
<> 128:9bcdf88f62b0 2971
<> 128:9bcdf88f62b0 2972 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 2973 * @{
<> 128:9bcdf88f62b0 2974 */
<> 128:9bcdf88f62b0 2975
<> 128:9bcdf88f62b0 2976 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
<> 128:9bcdf88f62b0 2977 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
<> 128:9bcdf88f62b0 2978 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
<> 128:9bcdf88f62b0 2979 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
<> 128:9bcdf88f62b0 2980
<> 128:9bcdf88f62b0 2981 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
<> 128:9bcdf88f62b0 2982
<> 128:9bcdf88f62b0 2983 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
<> 128:9bcdf88f62b0 2984 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
<> 128:9bcdf88f62b0 2985
<> 128:9bcdf88f62b0 2986 /**
<> 128:9bcdf88f62b0 2987 * @}
<> 128:9bcdf88f62b0 2988 */
<> 128:9bcdf88f62b0 2989
<> 128:9bcdf88f62b0 2990
<> 128:9bcdf88f62b0 2991 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 2992 * @{
<> 128:9bcdf88f62b0 2993 */
<> 128:9bcdf88f62b0 2994
<> 128:9bcdf88f62b0 2995 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
<> 128:9bcdf88f62b0 2996 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
<> 128:9bcdf88f62b0 2997 #define __USART_ENABLE __HAL_USART_ENABLE
<> 128:9bcdf88f62b0 2998 #define __USART_DISABLE __HAL_USART_DISABLE
<> 128:9bcdf88f62b0 2999
<> 128:9bcdf88f62b0 3000 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
<> 128:9bcdf88f62b0 3001 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
<> 128:9bcdf88f62b0 3002
<> 128:9bcdf88f62b0 3003 /**
<> 128:9bcdf88f62b0 3004 * @}
<> 128:9bcdf88f62b0 3005 */
<> 128:9bcdf88f62b0 3006
<> 128:9bcdf88f62b0 3007 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 3008 * @{
<> 128:9bcdf88f62b0 3009 */
<> 128:9bcdf88f62b0 3010 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
<> 128:9bcdf88f62b0 3011
<> 128:9bcdf88f62b0 3012 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
<> 128:9bcdf88f62b0 3013 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
<> 128:9bcdf88f62b0 3014 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
<> 128:9bcdf88f62b0 3015 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
<> 128:9bcdf88f62b0 3016
<> 128:9bcdf88f62b0 3017 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
<> 128:9bcdf88f62b0 3018 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
<> 128:9bcdf88f62b0 3019 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
<> 128:9bcdf88f62b0 3020 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
<> 128:9bcdf88f62b0 3021
<> 128:9bcdf88f62b0 3022 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
<> 128:9bcdf88f62b0 3023 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
<> 128:9bcdf88f62b0 3024 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
<> 128:9bcdf88f62b0 3025 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
<> 128:9bcdf88f62b0 3026 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
<> 128:9bcdf88f62b0 3027 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
<> 128:9bcdf88f62b0 3028 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
<> 128:9bcdf88f62b0 3029
<> 128:9bcdf88f62b0 3030 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
<> 128:9bcdf88f62b0 3031 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
<> 128:9bcdf88f62b0 3032 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
<> 128:9bcdf88f62b0 3033 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
<> 128:9bcdf88f62b0 3034 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
<> 128:9bcdf88f62b0 3035 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
<> 128:9bcdf88f62b0 3036 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
<> 128:9bcdf88f62b0 3037 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
<> 128:9bcdf88f62b0 3038
<> 128:9bcdf88f62b0 3039 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
<> 128:9bcdf88f62b0 3040 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
<> 128:9bcdf88f62b0 3041 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
<> 128:9bcdf88f62b0 3042 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
<> 128:9bcdf88f62b0 3043 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
<> 128:9bcdf88f62b0 3044 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
<> 128:9bcdf88f62b0 3045 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
<> 128:9bcdf88f62b0 3046 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
<> 128:9bcdf88f62b0 3047
<> 128:9bcdf88f62b0 3048 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
<> 128:9bcdf88f62b0 3049 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
<> 128:9bcdf88f62b0 3050
<> 128:9bcdf88f62b0 3051 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
<> 128:9bcdf88f62b0 3052 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
<> 128:9bcdf88f62b0 3053 /**
<> 128:9bcdf88f62b0 3054 * @}
<> 128:9bcdf88f62b0 3055 */
<> 128:9bcdf88f62b0 3056
<> 128:9bcdf88f62b0 3057 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 3058 * @{
<> 128:9bcdf88f62b0 3059 */
<> 128:9bcdf88f62b0 3060 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
<> 128:9bcdf88f62b0 3061 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
<> 128:9bcdf88f62b0 3062
<> 128:9bcdf88f62b0 3063 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
<> 128:9bcdf88f62b0 3064 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
<> 128:9bcdf88f62b0 3065
<> 128:9bcdf88f62b0 3066 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
<> 128:9bcdf88f62b0 3067
<> 128:9bcdf88f62b0 3068 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
<> 128:9bcdf88f62b0 3069 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
<> 128:9bcdf88f62b0 3070 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
<> 128:9bcdf88f62b0 3071 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
<> 128:9bcdf88f62b0 3072 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
<> 128:9bcdf88f62b0 3073 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
<> 128:9bcdf88f62b0 3074 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
<> 128:9bcdf88f62b0 3075 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
<> 128:9bcdf88f62b0 3076 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
<> 128:9bcdf88f62b0 3077 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
<> 128:9bcdf88f62b0 3078 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
<> 128:9bcdf88f62b0 3079 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
<> 128:9bcdf88f62b0 3080
<> 128:9bcdf88f62b0 3081 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
<> 128:9bcdf88f62b0 3082 /**
<> 128:9bcdf88f62b0 3083 * @}
<> 128:9bcdf88f62b0 3084 */
<> 128:9bcdf88f62b0 3085
<> 128:9bcdf88f62b0 3086 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 3087 * @{
<> 128:9bcdf88f62b0 3088 */
<> 128:9bcdf88f62b0 3089
<> 128:9bcdf88f62b0 3090 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
<> 128:9bcdf88f62b0 3091 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
<> 128:9bcdf88f62b0 3092 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
<> 128:9bcdf88f62b0 3093 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
<> 128:9bcdf88f62b0 3094 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
<> 128:9bcdf88f62b0 3095 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
<> 128:9bcdf88f62b0 3096 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
<> 128:9bcdf88f62b0 3097
<> 128:9bcdf88f62b0 3098 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
<> 128:9bcdf88f62b0 3099 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
<> 128:9bcdf88f62b0 3100 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
<> 128:9bcdf88f62b0 3101 /**
<> 128:9bcdf88f62b0 3102 * @}
<> 128:9bcdf88f62b0 3103 */
<> 128:9bcdf88f62b0 3104
<> 128:9bcdf88f62b0 3105 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 3106 * @{
<> 128:9bcdf88f62b0 3107 */
<> 128:9bcdf88f62b0 3108 #define __HAL_LTDC_LAYER LTDC_LAYER
<> 128:9bcdf88f62b0 3109 /**
<> 128:9bcdf88f62b0 3110 * @}
<> 128:9bcdf88f62b0 3111 */
<> 128:9bcdf88f62b0 3112
<> 128:9bcdf88f62b0 3113 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 3114 * @{
<> 128:9bcdf88f62b0 3115 */
<> 128:9bcdf88f62b0 3116 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
<> 128:9bcdf88f62b0 3117 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
<> 128:9bcdf88f62b0 3118 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
<> 128:9bcdf88f62b0 3119 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
<> 128:9bcdf88f62b0 3120 #define SAI_STREOMODE SAI_STEREOMODE
<> 128:9bcdf88f62b0 3121 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
<> 128:9bcdf88f62b0 3122 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
<> 128:9bcdf88f62b0 3123 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
<> 128:9bcdf88f62b0 3124 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
<> 128:9bcdf88f62b0 3125 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
<> 128:9bcdf88f62b0 3126 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
<> 128:9bcdf88f62b0 3127 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
<> 128:9bcdf88f62b0 3128 #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
<> 128:9bcdf88f62b0 3129 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
<> 128:9bcdf88f62b0 3130 /**
<> 128:9bcdf88f62b0 3131 * @}
<> 128:9bcdf88f62b0 3132 */
<> 128:9bcdf88f62b0 3133
<> 128:9bcdf88f62b0 3134
<> 128:9bcdf88f62b0 3135 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
<> 128:9bcdf88f62b0 3136 * @{
<> 128:9bcdf88f62b0 3137 */
<> 128:9bcdf88f62b0 3138
<> 128:9bcdf88f62b0 3139 /**
<> 128:9bcdf88f62b0 3140 * @}
<> 128:9bcdf88f62b0 3141 */
<> 128:9bcdf88f62b0 3142
<> 128:9bcdf88f62b0 3143 #ifdef __cplusplus
<> 128:9bcdf88f62b0 3144 }
<> 128:9bcdf88f62b0 3145 #endif
<> 128:9bcdf88f62b0 3146
<> 128:9bcdf88f62b0 3147 #endif /* ___STM32_HAL_LEGACY */
<> 128:9bcdf88f62b0 3148
<> 128:9bcdf88f62b0 3149 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 128:9bcdf88f62b0 3150