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TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_tim.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:30:20 2017 +0100
Revision:: 143:86740a56073b
Child:: 167:84c0a372a020

Release 143 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	143:86740a56073b	1	/**
AnnaBridge	143:86740a56073b	2	******************************************************************************
AnnaBridge	143:86740a56073b	3	* @file stm32l0xx_ll_tim.h
AnnaBridge	143:86740a56073b	4	* @author MCD Application Team
AnnaBridge	143:86740a56073b	5	* @version V1.7.0
AnnaBridge	143:86740a56073b	6	* @date 31-May-2016
AnnaBridge	143:86740a56073b	7	* @brief Header file of TIM LL module.
AnnaBridge	143:86740a56073b	8	******************************************************************************
AnnaBridge	143:86740a56073b	9	* @attention
AnnaBridge	143:86740a56073b	10	*
AnnaBridge	143:86740a56073b	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	143:86740a56073b	12	*
AnnaBridge	143:86740a56073b	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	143:86740a56073b	14	* are permitted provided that the following conditions are met:
AnnaBridge	143:86740a56073b	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	143:86740a56073b	16	* this list of conditions and the following disclaimer.
AnnaBridge	143:86740a56073b	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	143:86740a56073b	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	143:86740a56073b	19	* and/or other materials provided with the distribution.
AnnaBridge	143:86740a56073b	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	143:86740a56073b	21	* may be used to endorse or promote products derived from this software
AnnaBridge	143:86740a56073b	22	* without specific prior written permission.
AnnaBridge	143:86740a56073b	23	*
AnnaBridge	143:86740a56073b	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	143:86740a56073b	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	143:86740a56073b	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	143:86740a56073b	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	143:86740a56073b	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	143:86740a56073b	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	143:86740a56073b	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	143:86740a56073b	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	143:86740a56073b	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	143:86740a56073b	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	143:86740a56073b	34	*
AnnaBridge	143:86740a56073b	35	******************************************************************************
AnnaBridge	143:86740a56073b	36	*/
AnnaBridge	143:86740a56073b	37
AnnaBridge	143:86740a56073b	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	143:86740a56073b	39	#ifndef __STM32L0xx_LL_TIM_H
AnnaBridge	143:86740a56073b	40	#define __STM32L0xx_LL_TIM_H
AnnaBridge	143:86740a56073b	41
AnnaBridge	143:86740a56073b	42	#ifdef __cplusplus
AnnaBridge	143:86740a56073b	43	extern "C" {
AnnaBridge	143:86740a56073b	44	#endif
AnnaBridge	143:86740a56073b	45
AnnaBridge	143:86740a56073b	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	47	#include "stm32l0xx.h"
AnnaBridge	143:86740a56073b	48
AnnaBridge	143:86740a56073b	49	/** @addtogroup STM32L0xx_LL_Driver
AnnaBridge	143:86740a56073b	50	* @{
AnnaBridge	143:86740a56073b	51	*/
AnnaBridge	143:86740a56073b	52
AnnaBridge	143:86740a56073b	53	#if defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM21) \|\| defined (TIM22) \|\| defined (TIM6) \|\| defined (TIM7)
AnnaBridge	143:86740a56073b	54
AnnaBridge	143:86740a56073b	55	/** @defgroup TIM_LL TIM
AnnaBridge	143:86740a56073b	56	* @{
AnnaBridge	143:86740a56073b	57	*/
AnnaBridge	143:86740a56073b	58
AnnaBridge	143:86740a56073b	59	/* Private types -------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	60	/* Private variables ---------------------------------------------------------*/
AnnaBridge	143:86740a56073b	61	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
AnnaBridge	143:86740a56073b	62	* @{
AnnaBridge	143:86740a56073b	63	*/
AnnaBridge	143:86740a56073b	64	static const uint8_t OFFSET_TAB_CCMRx[] =
AnnaBridge	143:86740a56073b	65	{
AnnaBridge	143:86740a56073b	66	0x00U, /* 0: TIMx_CH1 */
AnnaBridge	143:86740a56073b	67	0x00U, /* 1: NA */
AnnaBridge	143:86740a56073b	68	0x00U, /* 2: TIMx_CH2 */
AnnaBridge	143:86740a56073b	69	0x00U, /* 3: NA */
AnnaBridge	143:86740a56073b	70	0x04U, /* 4: TIMx_CH3 */
AnnaBridge	143:86740a56073b	71	0x00U, /* 5: NA */
AnnaBridge	143:86740a56073b	72	0x04U /* 6: TIMx_CH4 */
AnnaBridge	143:86740a56073b	73	};
AnnaBridge	143:86740a56073b	74
AnnaBridge	143:86740a56073b	75	static const uint8_t SHIFT_TAB_OCxx[] =
AnnaBridge	143:86740a56073b	76	{
AnnaBridge	143:86740a56073b	77	0U, /* 0: OC1M, OC1FE, OC1PE */
AnnaBridge	143:86740a56073b	78	0U, /* 1: - NA */
AnnaBridge	143:86740a56073b	79	8U, /* 2: OC2M, OC2FE, OC2PE */
AnnaBridge	143:86740a56073b	80	0U, /* 3: - NA */
AnnaBridge	143:86740a56073b	81	0U, /* 4: OC3M, OC3FE, OC3PE */
AnnaBridge	143:86740a56073b	82	0U, /* 5: - NA */
AnnaBridge	143:86740a56073b	83	8U /* 6: OC4M, OC4FE, OC4PE */
AnnaBridge	143:86740a56073b	84	};
AnnaBridge	143:86740a56073b	85
AnnaBridge	143:86740a56073b	86	static const uint8_t SHIFT_TAB_ICxx[] =
AnnaBridge	143:86740a56073b	87	{
AnnaBridge	143:86740a56073b	88	0U, /* 0: CC1S, IC1PSC, IC1F */
AnnaBridge	143:86740a56073b	89	0U, /* 1: - NA */
AnnaBridge	143:86740a56073b	90	8U, /* 2: CC2S, IC2PSC, IC2F */
AnnaBridge	143:86740a56073b	91	0U, /* 3: - NA */
AnnaBridge	143:86740a56073b	92	0U, /* 4: CC3S, IC3PSC, IC3F */
AnnaBridge	143:86740a56073b	93	0U, /* 5: - NA */
AnnaBridge	143:86740a56073b	94	8U /* 6: CC4S, IC4PSC, IC4F */
AnnaBridge	143:86740a56073b	95	};
AnnaBridge	143:86740a56073b	96
AnnaBridge	143:86740a56073b	97	static const uint8_t SHIFT_TAB_CCxP[] =
AnnaBridge	143:86740a56073b	98	{
AnnaBridge	143:86740a56073b	99	0U, /* 0: CC1P */
AnnaBridge	143:86740a56073b	100	0U, /* 1: NA */
AnnaBridge	143:86740a56073b	101	4U, /* 2: CC2P */
AnnaBridge	143:86740a56073b	102	0U, /* 3: NA */
AnnaBridge	143:86740a56073b	103	8U, /* 4: CC3P */
AnnaBridge	143:86740a56073b	104	0U, /* 5: NA */
AnnaBridge	143:86740a56073b	105	12U /* 6: CC4P */
AnnaBridge	143:86740a56073b	106	};
AnnaBridge	143:86740a56073b	107
AnnaBridge	143:86740a56073b	108	/**
AnnaBridge	143:86740a56073b	109	* @}
AnnaBridge	143:86740a56073b	110	*/
AnnaBridge	143:86740a56073b	111
AnnaBridge	143:86740a56073b	112
AnnaBridge	143:86740a56073b	113	/* Private constants ---------------------------------------------------------*/
AnnaBridge	143:86740a56073b	114	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
AnnaBridge	143:86740a56073b	115	* @{
AnnaBridge	143:86740a56073b	116	*/
AnnaBridge	143:86740a56073b	117	/** @defgroup TIM_LL_POSITION_VAL Bit Position Value
AnnaBridge	143:86740a56073b	118	* @brief Position of the bit in the register.
AnnaBridge	143:86740a56073b	119	* @{
AnnaBridge	143:86740a56073b	120	*/
AnnaBridge	143:86740a56073b	121	/* Defines used for the bit position in the register and perform offsets*/
AnnaBridge	143:86740a56073b	122	#define TIM_POSITION_ICPSC (uint32_t)2U /!< field position in half register TIMx_CCMRx (8 bits)/
AnnaBridge	143:86740a56073b	123	/**
AnnaBridge	143:86740a56073b	124	* @}
AnnaBridge	143:86740a56073b	125	*/
AnnaBridge	143:86740a56073b	126
AnnaBridge	143:86740a56073b	127
AnnaBridge	143:86740a56073b	128	/* Remap mask definitions */
AnnaBridge	143:86740a56073b	129	#define TIMx_OR_RMP_SHIFT ((uint32_t)16U)
AnnaBridge	143:86740a56073b	130	#define TIMx_OR_RMP_MASK ((uint32_t)0x0000FFFFU)
AnnaBridge	143:86740a56073b	131	#define TIM2_OR_RMP_MASK ((uint32_t)((TIM2_OR_ETR_RMP \| TIM2_OR_TI4_RMP ) << TIMx_OR_RMP_SHIFT))
AnnaBridge	143:86740a56073b	132	#define TIM21_OR_RMP_MASK ((uint32_t)((TIM21_OR_ETR_RMP \| TIM21_OR_TI1_RMP \| TIM21_OR_TI2_RMP) << TIMx_OR_RMP_SHIFT))
AnnaBridge	143:86740a56073b	133	#define TIM22_OR_RMP_MASK ((uint32_t)((TIM22_OR_ETR_RMP \| TIM22_OR_TI1_RMP) << TIMx_OR_RMP_SHIFT))
AnnaBridge	143:86740a56073b	134	#if defined(TIM3)
AnnaBridge	143:86740a56073b	135	#define TIM3_OR_RMP_MASK ((uint32_t)((TIM3_OR_ETR_RMP \| TIM3_OR_TI1_RMP \| TIM3_OR_TI2_RMP \| TIM3_OR_TI4_RMP) << TIMx_OR_RMP_SHIFT))
AnnaBridge	143:86740a56073b	136	#endif /* TIM3 */
AnnaBridge	143:86740a56073b	137
AnnaBridge	143:86740a56073b	138
AnnaBridge	143:86740a56073b	139
AnnaBridge	143:86740a56073b	140	/**
AnnaBridge	143:86740a56073b	141	* @}
AnnaBridge	143:86740a56073b	142	*/
AnnaBridge	143:86740a56073b	143
AnnaBridge	143:86740a56073b	144
AnnaBridge	143:86740a56073b	145	/* Private macros ------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	146	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
AnnaBridge	143:86740a56073b	147	* @{
AnnaBridge	143:86740a56073b	148	*/
AnnaBridge	143:86740a56073b	149	/** @brief Convert channel id into channel index.
AnnaBridge	143:86740a56073b	150	* @param __CHANNEL__ This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	151	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	152	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	153	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	154	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	155	* @retval none
AnnaBridge	143:86740a56073b	156	*/
AnnaBridge	143:86740a56073b	157	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
AnnaBridge	143:86740a56073b	158	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
AnnaBridge	143:86740a56073b	159	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
AnnaBridge	143:86740a56073b	160	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U : 6U)
AnnaBridge	143:86740a56073b	161
AnnaBridge	143:86740a56073b	162	/**
AnnaBridge	143:86740a56073b	163	* @}
AnnaBridge	143:86740a56073b	164	*/
AnnaBridge	143:86740a56073b	165
AnnaBridge	143:86740a56073b	166
AnnaBridge	143:86740a56073b	167	/* Exported types ------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	168	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	143:86740a56073b	169	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
AnnaBridge	143:86740a56073b	170	* @{
AnnaBridge	143:86740a56073b	171	*/
AnnaBridge	143:86740a56073b	172
AnnaBridge	143:86740a56073b	173	/**
AnnaBridge	143:86740a56073b	174	* @brief TIM Time Base configuration structure definition.
AnnaBridge	143:86740a56073b	175	*/
AnnaBridge	143:86740a56073b	176	typedef struct
AnnaBridge	143:86740a56073b	177	{
AnnaBridge	143:86740a56073b	178	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
AnnaBridge	143:86740a56073b	179	This parameter can be a number between 0x0000 and 0xFFFF.
AnnaBridge	143:86740a56073b	180
AnnaBridge	143:86740a56073b	181	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
AnnaBridge	143:86740a56073b	182
AnnaBridge	143:86740a56073b	183	uint32_t CounterMode; /*!< Specifies the counter mode.
AnnaBridge	143:86740a56073b	184	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
AnnaBridge	143:86740a56073b	185
AnnaBridge	143:86740a56073b	186	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
AnnaBridge	143:86740a56073b	187
AnnaBridge	143:86740a56073b	188	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
AnnaBridge	143:86740a56073b	189	Auto-Reload Register at the next update event.
AnnaBridge	143:86740a56073b	190	This parameter must be a number between 0x0000 and 0xFFFF.
AnnaBridge	143:86740a56073b	191	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
AnnaBridge	143:86740a56073b	192
AnnaBridge	143:86740a56073b	193	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
AnnaBridge	143:86740a56073b	194
AnnaBridge	143:86740a56073b	195	uint32_t ClockDivision; /*!< Specifies the clock division.
AnnaBridge	143:86740a56073b	196	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
AnnaBridge	143:86740a56073b	197
AnnaBridge	143:86740a56073b	198	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
AnnaBridge	143:86740a56073b	199	} LL_TIM_InitTypeDef;
AnnaBridge	143:86740a56073b	200
AnnaBridge	143:86740a56073b	201	/**
AnnaBridge	143:86740a56073b	202	* @brief TIM Output Compare configuration structure definition.
AnnaBridge	143:86740a56073b	203	*/
AnnaBridge	143:86740a56073b	204	typedef struct
AnnaBridge	143:86740a56073b	205	{
AnnaBridge	143:86740a56073b	206	uint32_t OCMode; /*!< Specifies the output mode.
AnnaBridge	143:86740a56073b	207	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
AnnaBridge	143:86740a56073b	208
AnnaBridge	143:86740a56073b	209	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
AnnaBridge	143:86740a56073b	210
AnnaBridge	143:86740a56073b	211	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
AnnaBridge	143:86740a56073b	212	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
AnnaBridge	143:86740a56073b	213
AnnaBridge	143:86740a56073b	214	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
AnnaBridge	143:86740a56073b	215
AnnaBridge	143:86740a56073b	216	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
AnnaBridge	143:86740a56073b	217	This parameter can be a number between 0x0000 and 0xFFFF.
AnnaBridge	143:86740a56073b	218
AnnaBridge	143:86740a56073b	219	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
AnnaBridge	143:86740a56073b	220
AnnaBridge	143:86740a56073b	221	uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge	143:86740a56073b	222	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
AnnaBridge	143:86740a56073b	223
AnnaBridge	143:86740a56073b	224	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
AnnaBridge	143:86740a56073b	225
AnnaBridge	143:86740a56073b	226	} LL_TIM_OC_InitTypeDef;
AnnaBridge	143:86740a56073b	227
AnnaBridge	143:86740a56073b	228	/**
AnnaBridge	143:86740a56073b	229	* @brief TIM Input Capture configuration structure definition.
AnnaBridge	143:86740a56073b	230	*/
AnnaBridge	143:86740a56073b	231
AnnaBridge	143:86740a56073b	232	typedef struct
AnnaBridge	143:86740a56073b	233	{
AnnaBridge	143:86740a56073b	234
AnnaBridge	143:86740a56073b	235	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	143:86740a56073b	236	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	143:86740a56073b	237
AnnaBridge	143:86740a56073b	238	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	143:86740a56073b	239
AnnaBridge	143:86740a56073b	240	uint32_t ICActiveInput; /*!< Specifies the input.
AnnaBridge	143:86740a56073b	241	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	143:86740a56073b	242
AnnaBridge	143:86740a56073b	243	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	143:86740a56073b	244
AnnaBridge	143:86740a56073b	245	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge	143:86740a56073b	246	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	143:86740a56073b	247
AnnaBridge	143:86740a56073b	248	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	143:86740a56073b	249
AnnaBridge	143:86740a56073b	250	uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge	143:86740a56073b	251	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	143:86740a56073b	252
AnnaBridge	143:86740a56073b	253	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	143:86740a56073b	254	} LL_TIM_IC_InitTypeDef;
AnnaBridge	143:86740a56073b	255
AnnaBridge	143:86740a56073b	256
AnnaBridge	143:86740a56073b	257	/**
AnnaBridge	143:86740a56073b	258	* @brief TIM Encoder interface configuration structure definition.
AnnaBridge	143:86740a56073b	259	*/
AnnaBridge	143:86740a56073b	260	typedef struct
AnnaBridge	143:86740a56073b	261	{
AnnaBridge	143:86740a56073b	262	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
AnnaBridge	143:86740a56073b	263	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
AnnaBridge	143:86740a56073b	264
AnnaBridge	143:86740a56073b	265	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
AnnaBridge	143:86740a56073b	266
AnnaBridge	143:86740a56073b	267	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
AnnaBridge	143:86740a56073b	268	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	143:86740a56073b	269
AnnaBridge	143:86740a56073b	270	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	143:86740a56073b	271
AnnaBridge	143:86740a56073b	272	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
AnnaBridge	143:86740a56073b	273	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	143:86740a56073b	274
AnnaBridge	143:86740a56073b	275	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	143:86740a56073b	276
AnnaBridge	143:86740a56073b	277	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
AnnaBridge	143:86740a56073b	278	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	143:86740a56073b	279
AnnaBridge	143:86740a56073b	280	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	143:86740a56073b	281
AnnaBridge	143:86740a56073b	282	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
AnnaBridge	143:86740a56073b	283	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	143:86740a56073b	284
AnnaBridge	143:86740a56073b	285	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	143:86740a56073b	286
AnnaBridge	143:86740a56073b	287	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
AnnaBridge	143:86740a56073b	288	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	143:86740a56073b	289
AnnaBridge	143:86740a56073b	290	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	143:86740a56073b	291
AnnaBridge	143:86740a56073b	292	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
AnnaBridge	143:86740a56073b	293	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	143:86740a56073b	294
AnnaBridge	143:86740a56073b	295	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	143:86740a56073b	296
AnnaBridge	143:86740a56073b	297	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
AnnaBridge	143:86740a56073b	298	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	143:86740a56073b	299
AnnaBridge	143:86740a56073b	300	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	143:86740a56073b	301
AnnaBridge	143:86740a56073b	302	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
AnnaBridge	143:86740a56073b	303	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	143:86740a56073b	304
AnnaBridge	143:86740a56073b	305	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	143:86740a56073b	306
AnnaBridge	143:86740a56073b	307	} LL_TIM_ENCODER_InitTypeDef;
AnnaBridge	143:86740a56073b	308
AnnaBridge	143:86740a56073b	309
AnnaBridge	143:86740a56073b	310	/**
AnnaBridge	143:86740a56073b	311	* @}
AnnaBridge	143:86740a56073b	312	*/
AnnaBridge	143:86740a56073b	313	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	143:86740a56073b	314
AnnaBridge	143:86740a56073b	315	/* Exported constants --------------------------------------------------------*/
AnnaBridge	143:86740a56073b	316	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
AnnaBridge	143:86740a56073b	317	* @{
AnnaBridge	143:86740a56073b	318	*/
AnnaBridge	143:86740a56073b	319
AnnaBridge	143:86740a56073b	320	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	143:86740a56073b	321	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
AnnaBridge	143:86740a56073b	322	* @{
AnnaBridge	143:86740a56073b	323	*/
AnnaBridge	143:86740a56073b	324	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
AnnaBridge	143:86740a56073b	325	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
AnnaBridge	143:86740a56073b	326	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
AnnaBridge	143:86740a56073b	327	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
AnnaBridge	143:86740a56073b	328	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
AnnaBridge	143:86740a56073b	329	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
AnnaBridge	143:86740a56073b	330	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
AnnaBridge	143:86740a56073b	331	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
AnnaBridge	143:86740a56073b	332	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
AnnaBridge	143:86740a56073b	333	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
AnnaBridge	143:86740a56073b	334	/**
AnnaBridge	143:86740a56073b	335	* @}
AnnaBridge	143:86740a56073b	336	*/
AnnaBridge	143:86740a56073b	337
AnnaBridge	143:86740a56073b	338	/** @defgroup TIM_LL_EC_IT IT Defines
AnnaBridge	143:86740a56073b	339	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
AnnaBridge	143:86740a56073b	340	* @{
AnnaBridge	143:86740a56073b	341	*/
AnnaBridge	143:86740a56073b	342	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
AnnaBridge	143:86740a56073b	343	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
AnnaBridge	143:86740a56073b	344	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
AnnaBridge	143:86740a56073b	345	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
AnnaBridge	143:86740a56073b	346	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
AnnaBridge	143:86740a56073b	347	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
AnnaBridge	143:86740a56073b	348	/**
AnnaBridge	143:86740a56073b	349	* @}
AnnaBridge	143:86740a56073b	350	*/
AnnaBridge	143:86740a56073b	351
AnnaBridge	143:86740a56073b	352	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
AnnaBridge	143:86740a56073b	353	* @{
AnnaBridge	143:86740a56073b	354	*/
AnnaBridge	143:86740a56073b	355	#define LL_TIM_UPDATESOURCE_REGULAR ((uint32_t)0x00000000U) /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
AnnaBridge	143:86740a56073b	356	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
AnnaBridge	143:86740a56073b	357	/**
AnnaBridge	143:86740a56073b	358	* @}
AnnaBridge	143:86740a56073b	359	*/
AnnaBridge	143:86740a56073b	360
AnnaBridge	143:86740a56073b	361	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
AnnaBridge	143:86740a56073b	362	* @{
AnnaBridge	143:86740a56073b	363	*/
AnnaBridge	143:86740a56073b	364	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
AnnaBridge	143:86740a56073b	365	#define LL_TIM_ONEPULSEMODE_REPETITIVE ((uint32_t)0x00000000U) /!< Counter stops counting at the next update event /
AnnaBridge	143:86740a56073b	366	/**
AnnaBridge	143:86740a56073b	367	* @}
AnnaBridge	143:86740a56073b	368	*/
AnnaBridge	143:86740a56073b	369
AnnaBridge	143:86740a56073b	370	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
AnnaBridge	143:86740a56073b	371	* @{
AnnaBridge	143:86740a56073b	372	*/
AnnaBridge	143:86740a56073b	373	#define LL_TIM_COUNTERMODE_UP ((uint32_t)0x00000000U) /!<Counter used as upcounter /
AnnaBridge	143:86740a56073b	374	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
AnnaBridge	143:86740a56073b	375	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
AnnaBridge	143:86740a56073b	376	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
AnnaBridge	143:86740a56073b	377	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
AnnaBridge	143:86740a56073b	378	/**
AnnaBridge	143:86740a56073b	379	* @}
AnnaBridge	143:86740a56073b	380	*/
AnnaBridge	143:86740a56073b	381
AnnaBridge	143:86740a56073b	382	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
AnnaBridge	143:86740a56073b	383	* @{
AnnaBridge	143:86740a56073b	384	*/
AnnaBridge	143:86740a56073b	385	#define LL_TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x00000000U) /!< tDTS=tCK_INT /
AnnaBridge	143:86740a56073b	386	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
AnnaBridge	143:86740a56073b	387	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
AnnaBridge	143:86740a56073b	388	/**
AnnaBridge	143:86740a56073b	389	* @}
AnnaBridge	143:86740a56073b	390	*/
AnnaBridge	143:86740a56073b	391
AnnaBridge	143:86740a56073b	392	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
AnnaBridge	143:86740a56073b	393	* @{
AnnaBridge	143:86740a56073b	394	*/
AnnaBridge	143:86740a56073b	395	#define LL_TIM_COUNTERDIRECTION_UP ((uint32_t)0x00000000U) /!< Timer counter counts up /
AnnaBridge	143:86740a56073b	396	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
AnnaBridge	143:86740a56073b	397	/**
AnnaBridge	143:86740a56073b	398	* @}
AnnaBridge	143:86740a56073b	399	*/
AnnaBridge	143:86740a56073b	400
AnnaBridge	143:86740a56073b	401
AnnaBridge	143:86740a56073b	402	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
AnnaBridge	143:86740a56073b	403	* @{
AnnaBridge	143:86740a56073b	404	*/
AnnaBridge	143:86740a56073b	405	#define LL_TIM_CCDMAREQUEST_CC ((uint32_t)0x00000000U) /!< CCx DMA request sent when CCx event occurs /
AnnaBridge	143:86740a56073b	406	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
AnnaBridge	143:86740a56073b	407	/**
AnnaBridge	143:86740a56073b	408	* @}
AnnaBridge	143:86740a56073b	409	*/
AnnaBridge	143:86740a56073b	410
AnnaBridge	143:86740a56073b	411
AnnaBridge	143:86740a56073b	412	/** @defgroup TIM_LL_EC_CHANNEL Channel
AnnaBridge	143:86740a56073b	413	* @{
AnnaBridge	143:86740a56073b	414	*/
AnnaBridge	143:86740a56073b	415	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
AnnaBridge	143:86740a56073b	416	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
AnnaBridge	143:86740a56073b	417	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
AnnaBridge	143:86740a56073b	418	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
AnnaBridge	143:86740a56073b	419	/**
AnnaBridge	143:86740a56073b	420	* @}
AnnaBridge	143:86740a56073b	421	*/
AnnaBridge	143:86740a56073b	422
AnnaBridge	143:86740a56073b	423	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	143:86740a56073b	424	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
AnnaBridge	143:86740a56073b	425	* @{
AnnaBridge	143:86740a56073b	426	*/
AnnaBridge	143:86740a56073b	427	#define LL_TIM_OCSTATE_DISABLE ((uint32_t)0x00000000U) /!< OCx is not active /
AnnaBridge	143:86740a56073b	428	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
AnnaBridge	143:86740a56073b	429	/**
AnnaBridge	143:86740a56073b	430	* @}
AnnaBridge	143:86740a56073b	431	*/
AnnaBridge	143:86740a56073b	432	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	143:86740a56073b	433
AnnaBridge	143:86740a56073b	434	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
AnnaBridge	143:86740a56073b	435	* @{
AnnaBridge	143:86740a56073b	436	*/
AnnaBridge	143:86740a56073b	437	#define LL_TIM_OCMODE_FROZEN ((uint32_t)0x00000000U) /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
AnnaBridge	143:86740a56073b	438	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
AnnaBridge	143:86740a56073b	439	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
AnnaBridge	143:86740a56073b	440	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
AnnaBridge	143:86740a56073b	441	#define LL_TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) /!<OCyREF is forced low/
AnnaBridge	143:86740a56073b	442	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
AnnaBridge	143:86740a56073b	443	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
AnnaBridge	143:86740a56073b	444	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
AnnaBridge	143:86740a56073b	445	/**
AnnaBridge	143:86740a56073b	446	* @}
AnnaBridge	143:86740a56073b	447	*/
AnnaBridge	143:86740a56073b	448
AnnaBridge	143:86740a56073b	449	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
AnnaBridge	143:86740a56073b	450	* @{
AnnaBridge	143:86740a56073b	451	*/
AnnaBridge	143:86740a56073b	452	#define LL_TIM_OCPOLARITY_HIGH ((uint32_t)0x00000000U) /!< OCxactive high/
AnnaBridge	143:86740a56073b	453	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
AnnaBridge	143:86740a56073b	454	/**
AnnaBridge	143:86740a56073b	455	* @}
AnnaBridge	143:86740a56073b	456	*/
AnnaBridge	143:86740a56073b	457
AnnaBridge	143:86740a56073b	458
AnnaBridge	143:86740a56073b	459
AnnaBridge	143:86740a56073b	460	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
AnnaBridge	143:86740a56073b	461	* @{
AnnaBridge	143:86740a56073b	462	*/
AnnaBridge	143:86740a56073b	463	#define LL_TIM_ACTIVEINPUT_DIRECTTI (uint32_t)(TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
AnnaBridge	143:86740a56073b	464	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (uint32_t)(TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
AnnaBridge	143:86740a56073b	465	#define LL_TIM_ACTIVEINPUT_TRC (uint32_t)(TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
AnnaBridge	143:86740a56073b	466	/**
AnnaBridge	143:86740a56073b	467	* @}
AnnaBridge	143:86740a56073b	468	*/
AnnaBridge	143:86740a56073b	469
AnnaBridge	143:86740a56073b	470	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
AnnaBridge	143:86740a56073b	471	* @{
AnnaBridge	143:86740a56073b	472	*/
AnnaBridge	143:86740a56073b	473	#define LL_TIM_ICPSC_DIV1 ((uint32_t)0x00000000U) /!< No prescaler, capture is done each time an edge is detected on the capture input /
AnnaBridge	143:86740a56073b	474	#define LL_TIM_ICPSC_DIV2 (uint32_t)(TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
AnnaBridge	143:86740a56073b	475	#define LL_TIM_ICPSC_DIV4 (uint32_t)(TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
AnnaBridge	143:86740a56073b	476	#define LL_TIM_ICPSC_DIV8 (uint32_t)(TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
AnnaBridge	143:86740a56073b	477	/**
AnnaBridge	143:86740a56073b	478	* @}
AnnaBridge	143:86740a56073b	479	*/
AnnaBridge	143:86740a56073b	480
AnnaBridge	143:86740a56073b	481	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
AnnaBridge	143:86740a56073b	482	* @{
AnnaBridge	143:86740a56073b	483	*/
AnnaBridge	143:86740a56073b	484	#define LL_TIM_IC_FILTER_FDIV1 ((uint32_t)0x00000000U) /!< No filter, sampling is done at fDTS /
AnnaBridge	143:86740a56073b	485	#define LL_TIM_IC_FILTER_FDIV1_N2 (uint32_t)(TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	143:86740a56073b	486	#define LL_TIM_IC_FILTER_FDIV1_N4 (uint32_t)(TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	143:86740a56073b	487	#define LL_TIM_IC_FILTER_FDIV1_N8 (uint32_t)((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	143:86740a56073b	488	#define LL_TIM_IC_FILTER_FDIV2_N6 (uint32_t)(TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	143:86740a56073b	489	#define LL_TIM_IC_FILTER_FDIV2_N8 (uint32_t)((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	143:86740a56073b	490	#define LL_TIM_IC_FILTER_FDIV4_N6 (uint32_t)((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	143:86740a56073b	491	#define LL_TIM_IC_FILTER_FDIV4_N8 (uint32_t)((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	143:86740a56073b	492	#define LL_TIM_IC_FILTER_FDIV8_N6 (uint32_t)(TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
AnnaBridge	143:86740a56073b	493	#define LL_TIM_IC_FILTER_FDIV8_N8 (uint32_t)((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	143:86740a56073b	494	#define LL_TIM_IC_FILTER_FDIV16_N5 (uint32_t)((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	143:86740a56073b	495	#define LL_TIM_IC_FILTER_FDIV16_N6 (uint32_t)((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	143:86740a56073b	496	#define LL_TIM_IC_FILTER_FDIV16_N8 (uint32_t)((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	143:86740a56073b	497	#define LL_TIM_IC_FILTER_FDIV32_N5 (uint32_t)((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	143:86740a56073b	498	#define LL_TIM_IC_FILTER_FDIV32_N6 (uint32_t)((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	143:86740a56073b	499	#define LL_TIM_IC_FILTER_FDIV32_N8 (uint32_t)(TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	143:86740a56073b	500	/**
AnnaBridge	143:86740a56073b	501	* @}
AnnaBridge	143:86740a56073b	502	*/
AnnaBridge	143:86740a56073b	503
AnnaBridge	143:86740a56073b	504	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
AnnaBridge	143:86740a56073b	505	* @{
AnnaBridge	143:86740a56073b	506	*/
AnnaBridge	143:86740a56073b	507	#define LL_TIM_IC_POLARITY_RISING ((uint32_t)0x00000000U) /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
AnnaBridge	143:86740a56073b	508	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
AnnaBridge	143:86740a56073b	509	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
AnnaBridge	143:86740a56073b	510	/**
AnnaBridge	143:86740a56073b	511	* @}
AnnaBridge	143:86740a56073b	512	*/
AnnaBridge	143:86740a56073b	513
AnnaBridge	143:86740a56073b	514	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
AnnaBridge	143:86740a56073b	515	* @{
AnnaBridge	143:86740a56073b	516	*/
AnnaBridge	143:86740a56073b	517	#define LL_TIM_CLOCKSOURCE_INTERNAL ((uint32_t)0x00000000U) /!< The timer is clocked by the internal clock provided from the RCC /
AnnaBridge	143:86740a56073b	518	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0 ) /!< Counter counts at each rising or falling edge on a selected inpu t/
AnnaBridge	143:86740a56073b	519	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
AnnaBridge	143:86740a56073b	520	/**
AnnaBridge	143:86740a56073b	521	* @}
AnnaBridge	143:86740a56073b	522	*/
AnnaBridge	143:86740a56073b	523
AnnaBridge	143:86740a56073b	524	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
AnnaBridge	143:86740a56073b	525	* @{
AnnaBridge	143:86740a56073b	526	*/
AnnaBridge	143:86740a56073b	527	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
AnnaBridge	143:86740a56073b	528	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
AnnaBridge	143:86740a56073b	529	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l /
AnnaBridge	143:86740a56073b	530	/**
AnnaBridge	143:86740a56073b	531	* @}
AnnaBridge	143:86740a56073b	532	*/
AnnaBridge	143:86740a56073b	533
AnnaBridge	143:86740a56073b	534	/** @defgroup TIM_LL_EC_TRGO Trigger Output
AnnaBridge	143:86740a56073b	535	* @{
AnnaBridge	143:86740a56073b	536	*/
AnnaBridge	143:86740a56073b	537	#define LL_TIM_TRGO_RESET ((uint32_t)0x00000000U) /!< UG bit from the TIMx_EGR register is used as trigger output /
AnnaBridge	143:86740a56073b	538	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
AnnaBridge	143:86740a56073b	539	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
AnnaBridge	143:86740a56073b	540	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
AnnaBridge	143:86740a56073b	541	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
AnnaBridge	143:86740a56073b	542	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
AnnaBridge	143:86740a56073b	543	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
AnnaBridge	143:86740a56073b	544	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
AnnaBridge	143:86740a56073b	545	/**
AnnaBridge	143:86740a56073b	546	* @}
AnnaBridge	143:86740a56073b	547	*/
AnnaBridge	143:86740a56073b	548
AnnaBridge	143:86740a56073b	549
AnnaBridge	143:86740a56073b	550	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
AnnaBridge	143:86740a56073b	551	* @{
AnnaBridge	143:86740a56073b	552	*/
AnnaBridge	143:86740a56073b	553	#define LL_TIM_SLAVEMODE_DISABLED ((uint32_t)0x00000000U) /!< Slave mode disabled /
AnnaBridge	143:86740a56073b	554	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
AnnaBridge	143:86740a56073b	555	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
AnnaBridge	143:86740a56073b	556	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
AnnaBridge	143:86740a56073b	557	/**
AnnaBridge	143:86740a56073b	558	* @}
AnnaBridge	143:86740a56073b	559	*/
AnnaBridge	143:86740a56073b	560
AnnaBridge	143:86740a56073b	561	/** @defgroup TIM_LL_EC_TS Trigger Selection
AnnaBridge	143:86740a56073b	562	* @{
AnnaBridge	143:86740a56073b	563	*/
AnnaBridge	143:86740a56073b	564	#define LL_TIM_TS_ITR0 ((uint32_t)0x00000000U) /!< Internal Trigger 0 (ITR0) is used as trigger input /
AnnaBridge	143:86740a56073b	565	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
AnnaBridge	143:86740a56073b	566	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
AnnaBridge	143:86740a56073b	567	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
AnnaBridge	143:86740a56073b	568	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
AnnaBridge	143:86740a56073b	569	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
AnnaBridge	143:86740a56073b	570	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
AnnaBridge	143:86740a56073b	571	#define LL_TIM_TS_ETRF TIM_SMCR_TS /!< Filtered external Trigger (ETRF) is used as trigger input /
AnnaBridge	143:86740a56073b	572	/**
AnnaBridge	143:86740a56073b	573	* @}
AnnaBridge	143:86740a56073b	574	*/
AnnaBridge	143:86740a56073b	575
AnnaBridge	143:86740a56073b	576	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
AnnaBridge	143:86740a56073b	577	* @{
AnnaBridge	143:86740a56073b	578	*/
AnnaBridge	143:86740a56073b	579	#define LL_TIM_ETR_POLARITY_NONINVERTED ((uint32_t)0x00000000U) /!< ETR is non-inverted, active at high level or rising edge /
AnnaBridge	143:86740a56073b	580	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
AnnaBridge	143:86740a56073b	581	/**
AnnaBridge	143:86740a56073b	582	* @}
AnnaBridge	143:86740a56073b	583	*/
AnnaBridge	143:86740a56073b	584
AnnaBridge	143:86740a56073b	585	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
AnnaBridge	143:86740a56073b	586	* @{
AnnaBridge	143:86740a56073b	587	*/
AnnaBridge	143:86740a56073b	588	#define LL_TIM_ETR_PRESCALER_DIV1 ((uint32_t)0x00000000U) /!< ETR prescaler OFF /
AnnaBridge	143:86740a56073b	589	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
AnnaBridge	143:86740a56073b	590	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
AnnaBridge	143:86740a56073b	591	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
AnnaBridge	143:86740a56073b	592	/**
AnnaBridge	143:86740a56073b	593	* @}
AnnaBridge	143:86740a56073b	594	*/
AnnaBridge	143:86740a56073b	595
AnnaBridge	143:86740a56073b	596	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
AnnaBridge	143:86740a56073b	597	* @{
AnnaBridge	143:86740a56073b	598	*/
AnnaBridge	143:86740a56073b	599	#define LL_TIM_ETR_FILTER_FDIV1 ((uint32_t)0x00000000U) /!< No filter, sampling is done at fDTS /
AnnaBridge	143:86740a56073b	600	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	143:86740a56073b	601	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	143:86740a56073b	602	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	143:86740a56073b	603	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	143:86740a56073b	604	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	143:86740a56073b	605	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 ) /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	143:86740a56073b	606	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	143:86740a56073b	607	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	143:86740a56073b	608	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	143:86740a56073b	609	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 ) /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	143:86740a56073b	610	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	143:86740a56073b	611	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 ) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	143:86740a56073b	612	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	143:86740a56073b	613	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	143:86740a56073b	614	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	143:86740a56073b	615	/**
AnnaBridge	143:86740a56073b	616	* @}
AnnaBridge	143:86740a56073b	617	*/
AnnaBridge	143:86740a56073b	618
AnnaBridge	143:86740a56073b	619
AnnaBridge	143:86740a56073b	620
AnnaBridge	143:86740a56073b	621
AnnaBridge	143:86740a56073b	622
AnnaBridge	143:86740a56073b	623
AnnaBridge	143:86740a56073b	624
AnnaBridge	143:86740a56073b	625	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
AnnaBridge	143:86740a56073b	626	* @{
AnnaBridge	143:86740a56073b	627	*/
AnnaBridge	143:86740a56073b	628	#define LL_TIM_DMABURST_BASEADDR_CR1 ((uint32_t)0x00000000U) /!< TIMx_CR1 register is the DMA base address for DMA burst / /!< TIMx_CR1 register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	629	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	630	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	631	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	632	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	633	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	634	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	635	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	636	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	637	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	638	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	639	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	640	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	641	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	642	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	643	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	644	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	645	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	646	#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1) /!< TIMx_CCMR3 register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	647	#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR5 register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	648	#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) /!< TIMx_CCR6 register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	649	#define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_OR1 register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	650	#define LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_OR2 register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	651	#define LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_OR3 register is the DMA base address for DMA burst /
AnnaBridge	143:86740a56073b	652	/**
AnnaBridge	143:86740a56073b	653	* @}
AnnaBridge	143:86740a56073b	654	*/
AnnaBridge	143:86740a56073b	655
AnnaBridge	143:86740a56073b	656	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
AnnaBridge	143:86740a56073b	657	* @{
AnnaBridge	143:86740a56073b	658	*/
AnnaBridge	143:86740a56073b	659	#define LL_TIM_DMABURST_LENGTH_1TRANSFER ((uint32_t)0x00000000U) /!< Transfer is done to 1 register starting from the DMA burst base address /
AnnaBridge	143:86740a56073b	660	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
AnnaBridge	143:86740a56073b	661	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
AnnaBridge	143:86740a56073b	662	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
AnnaBridge	143:86740a56073b	663	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
AnnaBridge	143:86740a56073b	664	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
AnnaBridge	143:86740a56073b	665	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
AnnaBridge	143:86740a56073b	666	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
AnnaBridge	143:86740a56073b	667	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
AnnaBridge	143:86740a56073b	668	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
AnnaBridge	143:86740a56073b	669	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
AnnaBridge	143:86740a56073b	670	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
AnnaBridge	143:86740a56073b	671	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
AnnaBridge	143:86740a56073b	672	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
AnnaBridge	143:86740a56073b	673	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
AnnaBridge	143:86740a56073b	674	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
AnnaBridge	143:86740a56073b	675	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
AnnaBridge	143:86740a56073b	676	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
AnnaBridge	143:86740a56073b	677	/**
AnnaBridge	143:86740a56073b	678	* @}
AnnaBridge	143:86740a56073b	679	*/
AnnaBridge	143:86740a56073b	680
AnnaBridge	143:86740a56073b	681
AnnaBridge	143:86740a56073b	682	/** @defgroup TIM_LL_EC_TIM2_ETR_RMP TIM2 External Trigger Remap
AnnaBridge	143:86740a56073b	683	* @{
AnnaBridge	143:86740a56073b	684	*/
AnnaBridge	143:86740a56073b	685	#define LL_TIM_TIM2_ETR_RMP_GPIO ((uint32_t)0x00000000U \| TIM2_OR_RMP_MASK) /!< TIM2_ETR is connected to Ored GPIO /
AnnaBridge	143:86740a56073b	686	#if defined(TIM_TIM2_REMAP_HSI_SUPPORT)
AnnaBridge	143:86740a56073b	687	#define LL_TIM_TIM2_ETR_RMP_HSI (TIM2_OR_ETR_RMP_1 \| TIM2_OR_ETR_RMP_0 \| TIM2_OR_RMP_MASK) /!< TIM2_ETR is connected to HSI /
AnnaBridge	143:86740a56073b	688	#endif /* defined(TIM_TIM2_REMAP_HSI_SUPPORT) */
AnnaBridge	143:86740a56073b	689	#if defined(TIM_TIM2_REMAP_HSI48_SUPPORT)
AnnaBridge	143:86740a56073b	690	#define LL_TIM_TIM2_ETR_RMP_HSI48 (TIM2_OR_ETR_RMP_2 \| TIM2_OR_RMP_MASK) /!< TIM2_ETR is connected to HSI48 /
AnnaBridge	143:86740a56073b	691	#endif /* defined(TIM_TIM2_REMAP_HSI48_SUPPORT) */
AnnaBridge	143:86740a56073b	692	#define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR_ETR_RMP_2 \| TIM2_OR_ETR_RMP_0 \| TIM2_OR_RMP_MASK) /!< TIM2_ETR is connected to LSE /
AnnaBridge	143:86740a56073b	693	#define LL_TIM_TIM2_ETR_RMP_COMP2 (TIM2_OR_ETR_RMP_2 \| TIM2_OR_ETR_RMP_1 \| TIM2_OR_RMP_MASK) /!< TIM2_ETR is connected to COMP2_OUT /
AnnaBridge	143:86740a56073b	694	#define LL_TIM_TIM2_ETR_RMP_COMP1 (TIM2_OR_ETR_RMP \| TIM2_OR_RMP_MASK) /!< TIM2_ETR is connected to COMP1_OUT /
AnnaBridge	143:86740a56073b	695
AnnaBridge	143:86740a56073b	696	/**
AnnaBridge	143:86740a56073b	697	* @}
AnnaBridge	143:86740a56073b	698	*/
AnnaBridge	143:86740a56073b	699
AnnaBridge	143:86740a56073b	700	/** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 Timer Input Ch4 Remap
AnnaBridge	143:86740a56073b	701	* @{
AnnaBridge	143:86740a56073b	702	*/
AnnaBridge	143:86740a56073b	703	#define LL_TIM_TIM2_TI4_RMP_GPIO ((uint32_t)0x00000000U \| TIM2_OR_RMP_MASK) /!< TIM2 input capture 4 is connected to GPIO /
AnnaBridge	143:86740a56073b	704	#define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR_TI4_RMP_0 \| TIM2_OR_RMP_MASK) /!< TIM2 input capture 4 is connected to COMP2_OUT /
AnnaBridge	143:86740a56073b	705	#define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR_TI4_RMP_1 \| TIM2_OR_RMP_MASK) /!< TIM2 input capture 4 is connected to COMP1_OUT /
AnnaBridge	143:86740a56073b	706	/**
AnnaBridge	143:86740a56073b	707	* @}
AnnaBridge	143:86740a56073b	708	*/
AnnaBridge	143:86740a56073b	709
AnnaBridge	143:86740a56073b	710	#if defined(TIM3_OR_ETR_RMP)
AnnaBridge	143:86740a56073b	711	/** @defgroup TIM_LL_EC_TIM3_ETR_RMP TIM3 External Trigger Remap
AnnaBridge	143:86740a56073b	712	* @{
AnnaBridge	143:86740a56073b	713	*/
AnnaBridge	143:86740a56073b	714	#define LL_TIM_TIM3_ETR_RMP_GPIO ((uint32_t)0x00000000U \| TIM3_OR_RMP_MASK) /!< TIM3_ETR is connected to GPIO /
AnnaBridge	143:86740a56073b	715	#define LL_TIM_TIM3_ETR_RMP_HSI48DIV6 (TIM3_OR_ETR_RMP_1 \| TIM3_OR_RMP_MASK) /!< TIM3_ETR is connected to HSI48 divided by 6 /
AnnaBridge	143:86740a56073b	716	/**
AnnaBridge	143:86740a56073b	717	* @}
AnnaBridge	143:86740a56073b	718	*/
AnnaBridge	143:86740a56073b	719	#endif /* defined(TIM3_OR_ETR_RMP) */
AnnaBridge	143:86740a56073b	720
AnnaBridge	143:86740a56073b	721	#if defined(TIM3_OR_TI1_RMP) \|\| defined(TIM3_OR_TI2_RMP) \|\| defined(TIM3_OR_TI4_RMP)
AnnaBridge	143:86740a56073b	722	/** @defgroup TIM_LL_EC_TIM3_TI_RMP TIM3 External Inputs Remap
AnnaBridge	143:86740a56073b	723	* @{
AnnaBridge	143:86740a56073b	724	*/
AnnaBridge	143:86740a56073b	725	#define LL_TIM_TIM3_TI_RMP_TI1_USB_SOF ((uint32_t)0x00000000U \| TIM3_OR_RMP_MASK) /!< TIM3_TI1 input is connected to USB_SOF /
AnnaBridge	143:86740a56073b	726	#define LL_TIM_TIM3_TI_RMP_TI1_GPIO (TIM3_OR_TI1_RMP \| TIM3_OR_RMP_MASK) /!< TIM3_TI1 input is connected to PE3, PA6, PC6 or PB4 /
AnnaBridge	143:86740a56073b	727
AnnaBridge	143:86740a56073b	728	#define LL_TIM_TIM3_TI_RMP_TI2_GPIO_DEF ((uint32_t)0x00000000U \| TIM3_OR_RMP_MASK) /!< Mapping PB5 to TIM22_CH2 /
AnnaBridge	143:86740a56073b	729	#define LL_TIM_TIM3_TI_RMP_TI2_GPIOB5_AF4 (TIM3_OR_TI2_RMP \| TIM3_OR_RMP_MASK) /!< Mapping PB5 to TIM3_CH2 /
AnnaBridge	143:86740a56073b	730
AnnaBridge	143:86740a56073b	731	#define LL_TIM_TIM3_TI_RMP_TI4_GPIO_DEF ((uint32_t)0x00000000U \| TIM3_OR_RMP_MASK) /!< Mapping PC9 to USB_OE /
AnnaBridge	143:86740a56073b	732	#define LL_TIM_TIM3_TI_RMP_TI4_GPIOC9_AF2 (TIM3_OR_TI4_RMP \| TIM3_OR_RMP_MASK) /!< Mapping PC9 to TIM3_CH4 /
AnnaBridge	143:86740a56073b	733	/**
AnnaBridge	143:86740a56073b	734	* @}
AnnaBridge	143:86740a56073b	735	*/
AnnaBridge	143:86740a56073b	736	#endif /defined(TIM3_OR_TI1_RMP) or defined(TIM3_OR_TI2_RMP) or defined(TIM3_OR_TI4_RMP)/
AnnaBridge	143:86740a56073b	737
AnnaBridge	143:86740a56073b	738	/** @defgroup TIM_LL_EC_TIM21_ETR_RMP TIM21 External Trigger Remap
AnnaBridge	143:86740a56073b	739	* @{
AnnaBridge	143:86740a56073b	740	*/
AnnaBridge	143:86740a56073b	741	#define LL_TIM_TIM21_ETR_RMP_GPIO ((uint32_t)0x00000000U \| TIM21_OR_RMP_MASK) /!< TIM21_ETR is connected to Ored GPIO1 /
AnnaBridge	143:86740a56073b	742	#define LL_TIM_TIM21_ETR_RMP_COMP2 (TIM21_OR_ETR_RMP_0 \| TIM21_OR_RMP_MASK) /!< TIM21_ETR is connected to COMP2_OUT /
AnnaBridge	143:86740a56073b	743	#define LL_TIM_TIM21_ETR_RMP_COMP1 (TIM21_OR_ETR_RMP_1 \| TIM21_OR_RMP_MASK) /!< TIM21_ETR is connected to COMP1_OUT /
AnnaBridge	143:86740a56073b	744	#define LL_TIM_TIM21_ETR_RMP_LSE (TIM21_OR_ETR_RMP \| TIM21_OR_RMP_MASK) /!< TIM21_ETR is connected to LSE /
AnnaBridge	143:86740a56073b	745	/**
AnnaBridge	143:86740a56073b	746	* @}
AnnaBridge	143:86740a56073b	747	*/
AnnaBridge	143:86740a56073b	748
AnnaBridge	143:86740a56073b	749	/** @defgroup TIM_LL_EC_TIM21_TI1_RMP TIM21 External Input Ch1 Remap
AnnaBridge	143:86740a56073b	750	* @{
AnnaBridge	143:86740a56073b	751	*/
AnnaBridge	143:86740a56073b	752	#define LL_TIM_TIM21_TI1_RMP_GPIO ((uint32_t)0x00000000U \| TIM21_OR_RMP_MASK) /!< TIM21_TI1 is connected to Ored GPIO1 /
AnnaBridge	143:86740a56073b	753	#define LL_TIM_TIM21_TI1_RMP_RTC_WK (TIM21_OR_TI1_RMP_0 \| TIM21_OR_RMP_MASK) /!< TIM21_TI1 is connected to RTC_WAKEUP /
AnnaBridge	143:86740a56073b	754	#define LL_TIM_TIM21_TI1_RMP_HSE_RTC (TIM21_OR_TI1_RMP_1 \| TIM21_OR_RMP_MASK) /!< TIM21_TI1 is connected to HSE_RTC /
AnnaBridge	143:86740a56073b	755	#define LL_TIM_TIM21_TI1_RMP_MSI (TIM21_OR_TI1_RMP_1 \| TIM21_OR_TI1_RMP_0 \| TIM21_OR_RMP_MASK) /!< TIM21_TI1 is connected to MSI /
AnnaBridge	143:86740a56073b	756	#define LL_TIM_TIM21_TI1_RMP_LSE (TIM21_OR_TI1_RMP_2 \| TIM21_OR_RMP_MASK) /!< TIM21_TI1 is connected to LSE /
AnnaBridge	143:86740a56073b	757	#define LL_TIM_TIM21_TI1_RMP_LSI (TIM21_OR_TI1_RMP_2 \| TIM21_OR_TI1_RMP_0 \| TIM21_OR_RMP_MASK) /!< TIM21_TI1 is connected to LSI /
AnnaBridge	143:86740a56073b	758	#define LL_TIM_TIM21_TI1_RMP_COMP1 (TIM21_OR_TI1_RMP_2 \| TIM21_OR_TI1_RMP_1 \| TIM21_OR_RMP_MASK) /!< TIM21_TI1 is connected to COMP1_OUT /
AnnaBridge	143:86740a56073b	759	#define LL_TIM_TIM21_TI1_RMP_MCO (TIM21_OR_TI1_RMP \| TIM21_OR_RMP_MASK) /!< TIM21_TI1 is connected to MCO /
AnnaBridge	143:86740a56073b	760	/**
AnnaBridge	143:86740a56073b	761	* @}
AnnaBridge	143:86740a56073b	762	*/
AnnaBridge	143:86740a56073b	763
AnnaBridge	143:86740a56073b	764	/** @defgroup TIM_LL_EC_TIM21_TI2_RMP TIM21 External Input Ch2 Remap
AnnaBridge	143:86740a56073b	765	* @{
AnnaBridge	143:86740a56073b	766	*/
AnnaBridge	143:86740a56073b	767	#define LL_TIM_TIM21_TI2_RMP_GPIO ((uint32_t)0x00000000U \| TIM21_OR_RMP_MASK) /!< TIM21_TI2 is connected to Ored GPIO1 /
AnnaBridge	143:86740a56073b	768	#define LL_TIM_TIM21_TI2_RMP_COMP2 (TIM21_OR_TI2_RMP \| TIM21_OR_RMP_MASK) /!< TIM21_TI2 is connected to COMP2_OUT /
AnnaBridge	143:86740a56073b	769	/**
AnnaBridge	143:86740a56073b	770	* @}
AnnaBridge	143:86740a56073b	771	*/
AnnaBridge	143:86740a56073b	772
AnnaBridge	143:86740a56073b	773	#if defined(TIM22_OR_ETR_RMP)
AnnaBridge	143:86740a56073b	774
AnnaBridge	143:86740a56073b	775	/** @defgroup TIM_LL_EC_TIM22_ETR_RMP TIM22 External Trigger Remap
AnnaBridge	143:86740a56073b	776	* @{
AnnaBridge	143:86740a56073b	777	*/
AnnaBridge	143:86740a56073b	778	#define LL_TIM_TIM22_ETR_RMP_GPIO ((uint32_t)0x00000000U \| TIM22_OR_RMP_MASK) /!< TIM22_ETR is connected to GPIO /
AnnaBridge	143:86740a56073b	779	#define LL_TIM_TIM22_ETR_RMP_COMP2 (TIM22_OR_ETR_RMP_0 \| TIM22_OR_RMP_MASK) /!< TIM22_ETR is connected to COMP2_OUT /
AnnaBridge	143:86740a56073b	780	#define LL_TIM_TIM22_ETR_RMP_COMP1 (TIM22_OR_ETR_RMP_1 \| TIM22_OR_RMP_MASK) /!< TIM22_ETR is connected to COMP1_OUT /
AnnaBridge	143:86740a56073b	781	#define LL_TIM_TIM22_ETR_RMP_LSE (TIM22_OR_ETR_RMP \| TIM22_OR_RMP_MASK) /!< TIM22_ETR is connected to LSE /
AnnaBridge	143:86740a56073b	782	/**
AnnaBridge	143:86740a56073b	783	* @}
AnnaBridge	143:86740a56073b	784	*/
AnnaBridge	143:86740a56073b	785	#endif /* defined(TIM22_OR_ETR_RMP) */
AnnaBridge	143:86740a56073b	786
AnnaBridge	143:86740a56073b	787	#if defined(TIM22_OR_TI1_RMP)
AnnaBridge	143:86740a56073b	788	/** @defgroup TIM_LL_EC_TIM22_TI1_RMP TIM22 External Input Ch1 Remap
AnnaBridge	143:86740a56073b	789	* @{
AnnaBridge	143:86740a56073b	790	*/
AnnaBridge	143:86740a56073b	791	#define LL_TIM_TIM22_TI1_RMP_GPIO1 ((uint32_t)0x00000000U \| TIM22_OR_RMP_MASK) /!< TIM22_TI1 is connected to GPIO1 /
AnnaBridge	143:86740a56073b	792	#define LL_TIM_TIM22_TI1_RMP_COMP2 (TIM22_OR_TI1_RMP_0 \| TIM22_OR_RMP_MASK) /!< TIM22_TI1 is connected to COMP2_OUT /
AnnaBridge	143:86740a56073b	793	#define LL_TIM_TIM22_TI1_RMP_COMP1 (TIM22_OR_TI1_RMP_1 \| TIM22_OR_RMP_MASK) /!< TIM22_TI1 is connected to COMP1_OUT /
AnnaBridge	143:86740a56073b	794	#define LL_TIM_TIM22_TI1_RMP_GPIO2 (TIM22_OR_TI1_RMP \| TIM22_OR_RMP_MASK) /!< TIM22_TI1 is connected to GPIO2 /
AnnaBridge	143:86740a56073b	795	/**
AnnaBridge	143:86740a56073b	796	* @}
AnnaBridge	143:86740a56073b	797	*/
AnnaBridge	143:86740a56073b	798	#endif /* defined(TIM22_OR_TI1_RMP) */
AnnaBridge	143:86740a56073b	799
AnnaBridge	143:86740a56073b	800
AnnaBridge	143:86740a56073b	801	/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
AnnaBridge	143:86740a56073b	802	* @{
AnnaBridge	143:86740a56073b	803	*/
AnnaBridge	143:86740a56073b	804	#define LL_TIM_OCREF_CLR_INT_NC ((uint32_t)0x00000000U ) /!< OCREF_CLR_INT is not connected /
AnnaBridge	143:86740a56073b	805	#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /!< OCREF_CLR_INT is connected to ETRF /
AnnaBridge	143:86740a56073b	806	/**
AnnaBridge	143:86740a56073b	807	* @}
AnnaBridge	143:86740a56073b	808	*/
AnnaBridge	143:86740a56073b	809
AnnaBridge	143:86740a56073b	810
AnnaBridge	143:86740a56073b	811	/**
AnnaBridge	143:86740a56073b	812	* @}
AnnaBridge	143:86740a56073b	813	*/
AnnaBridge	143:86740a56073b	814
AnnaBridge	143:86740a56073b	815	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	816	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
AnnaBridge	143:86740a56073b	817	* @{
AnnaBridge	143:86740a56073b	818	*/
AnnaBridge	143:86740a56073b	819
AnnaBridge	143:86740a56073b	820	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	143:86740a56073b	821	* @{
AnnaBridge	143:86740a56073b	822	*/
AnnaBridge	143:86740a56073b	823	/**
AnnaBridge	143:86740a56073b	824	* @brief Write a value in TIM register.
AnnaBridge	143:86740a56073b	825	* @param __INSTANCE__ TIM Instance
AnnaBridge	143:86740a56073b	826	* @param __REG__ Register to be written
AnnaBridge	143:86740a56073b	827	* @param __VALUE__ Value to be written in the register
AnnaBridge	143:86740a56073b	828	* @retval None
AnnaBridge	143:86740a56073b	829	*/
AnnaBridge	143:86740a56073b	830	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	143:86740a56073b	831
AnnaBridge	143:86740a56073b	832	/**
AnnaBridge	143:86740a56073b	833	* @brief Read a value in TIM register.
AnnaBridge	143:86740a56073b	834	* @param __INSTANCE__ TIM Instance
AnnaBridge	143:86740a56073b	835	* @param __REG__ Register to be read
AnnaBridge	143:86740a56073b	836	* @retval Register value
AnnaBridge	143:86740a56073b	837	*/
AnnaBridge	143:86740a56073b	838	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	143:86740a56073b	839	/**
AnnaBridge	143:86740a56073b	840	* @}
AnnaBridge	143:86740a56073b	841	*/
AnnaBridge	143:86740a56073b	842
AnnaBridge	143:86740a56073b	843	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
AnnaBridge	143:86740a56073b	844	* @{
AnnaBridge	143:86740a56073b	845	*/
AnnaBridge	143:86740a56073b	846
AnnaBridge	143:86740a56073b	847
AnnaBridge	143:86740a56073b	848	/**
AnnaBridge	143:86740a56073b	849	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
AnnaBridge	143:86740a56073b	850	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
AnnaBridge	143:86740a56073b	851	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	143:86740a56073b	852	* @param __CNTCLK__ counter clock frequency (in Hz)
AnnaBridge	143:86740a56073b	853	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	143:86740a56073b	854	*/
AnnaBridge	143:86740a56073b	855	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
AnnaBridge	143:86740a56073b	856	((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
AnnaBridge	143:86740a56073b	857
AnnaBridge	143:86740a56073b	858	/**
AnnaBridge	143:86740a56073b	859	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
AnnaBridge	143:86740a56073b	860	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
AnnaBridge	143:86740a56073b	861	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	143:86740a56073b	862	* @param __PSC__ prescaler
AnnaBridge	143:86740a56073b	863	* @param __FREQ__ output signal frequency (in Hz)
AnnaBridge	143:86740a56073b	864	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	143:86740a56073b	865	*/
AnnaBridge	143:86740a56073b	866	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
AnnaBridge	143:86740a56073b	867	(((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
AnnaBridge	143:86740a56073b	868
AnnaBridge	143:86740a56073b	869	/**
AnnaBridge	143:86740a56073b	870	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
AnnaBridge	143:86740a56073b	871	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
AnnaBridge	143:86740a56073b	872	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	143:86740a56073b	873	* @param __PSC__ prescaler
AnnaBridge	143:86740a56073b	874	* @param __DELAY__ timer output compare active/inactive delay (in us)
AnnaBridge	143:86740a56073b	875	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	143:86740a56073b	876	*/
AnnaBridge	143:86740a56073b	877	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
AnnaBridge	143:86740a56073b	878	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
AnnaBridge	143:86740a56073b	879	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
AnnaBridge	143:86740a56073b	880
AnnaBridge	143:86740a56073b	881	/**
AnnaBridge	143:86740a56073b	882	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
AnnaBridge	143:86740a56073b	883	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
AnnaBridge	143:86740a56073b	884	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	143:86740a56073b	885	* @param __PSC__ prescaler
AnnaBridge	143:86740a56073b	886	* @param __DELAY__ timer output compare active/inactive delay (in us)
AnnaBridge	143:86740a56073b	887	* @param __PULSE__ pulse duration (in us)
AnnaBridge	143:86740a56073b	888	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	143:86740a56073b	889	*/
AnnaBridge	143:86740a56073b	890	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
AnnaBridge	143:86740a56073b	891	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
AnnaBridge	143:86740a56073b	892	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
AnnaBridge	143:86740a56073b	893
AnnaBridge	143:86740a56073b	894	/**
AnnaBridge	143:86740a56073b	895	* @brief HELPER macro retrieving the ratio of the input capture prescaler
AnnaBridge	143:86740a56073b	896	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
AnnaBridge	143:86740a56073b	897	* @param __ICPSC__ This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	898	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	143:86740a56073b	899	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	143:86740a56073b	900	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	143:86740a56073b	901	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	143:86740a56073b	902	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
AnnaBridge	143:86740a56073b	903	*/
AnnaBridge	143:86740a56073b	904	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
AnnaBridge	143:86740a56073b	905	((uint32_t)((uint32_t)0x01U << (((__ICPSC__) >> 16U) >> TIM_POSITION_ICPSC)))
AnnaBridge	143:86740a56073b	906
AnnaBridge	143:86740a56073b	907
AnnaBridge	143:86740a56073b	908	/**
AnnaBridge	143:86740a56073b	909	* @}
AnnaBridge	143:86740a56073b	910	*/
AnnaBridge	143:86740a56073b	911
AnnaBridge	143:86740a56073b	912
AnnaBridge	143:86740a56073b	913	/**
AnnaBridge	143:86740a56073b	914	* @}
AnnaBridge	143:86740a56073b	915	*/
AnnaBridge	143:86740a56073b	916
AnnaBridge	143:86740a56073b	917	/* Exported functions --------------------------------------------------------*/
AnnaBridge	143:86740a56073b	918	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
AnnaBridge	143:86740a56073b	919	* @{
AnnaBridge	143:86740a56073b	920	*/
AnnaBridge	143:86740a56073b	921
AnnaBridge	143:86740a56073b	922	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
AnnaBridge	143:86740a56073b	923	* @{
AnnaBridge	143:86740a56073b	924	*/
AnnaBridge	143:86740a56073b	925	/**
AnnaBridge	143:86740a56073b	926	* @brief Enable timer counter.
AnnaBridge	143:86740a56073b	927	* @rmtoll CR1 CEN LL_TIM_EnableCounter
AnnaBridge	143:86740a56073b	928	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	929	* @retval None
AnnaBridge	143:86740a56073b	930	*/
AnnaBridge	143:86740a56073b	931	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	932	{
AnnaBridge	143:86740a56073b	933	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
AnnaBridge	143:86740a56073b	934	}
AnnaBridge	143:86740a56073b	935
AnnaBridge	143:86740a56073b	936	/**
AnnaBridge	143:86740a56073b	937	* @brief Disable timer counter.
AnnaBridge	143:86740a56073b	938	* @rmtoll CR1 CEN LL_TIM_DisableCounter
AnnaBridge	143:86740a56073b	939	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	940	* @retval None
AnnaBridge	143:86740a56073b	941	*/
AnnaBridge	143:86740a56073b	942	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	943	{
AnnaBridge	143:86740a56073b	944	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
AnnaBridge	143:86740a56073b	945	}
AnnaBridge	143:86740a56073b	946
AnnaBridge	143:86740a56073b	947	/**
AnnaBridge	143:86740a56073b	948	* @brief Indicates whether the timer counter is enabled.
AnnaBridge	143:86740a56073b	949	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
AnnaBridge	143:86740a56073b	950	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	951	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	952	*/
AnnaBridge	143:86740a56073b	953	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	954	{
AnnaBridge	143:86740a56073b	955	return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
AnnaBridge	143:86740a56073b	956	}
AnnaBridge	143:86740a56073b	957
AnnaBridge	143:86740a56073b	958	/**
AnnaBridge	143:86740a56073b	959	* @brief Enable update event generation.
AnnaBridge	143:86740a56073b	960	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
AnnaBridge	143:86740a56073b	961	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	962	* @retval None
AnnaBridge	143:86740a56073b	963	*/
AnnaBridge	143:86740a56073b	964	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	965	{
AnnaBridge	143:86740a56073b	966	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
AnnaBridge	143:86740a56073b	967	}
AnnaBridge	143:86740a56073b	968
AnnaBridge	143:86740a56073b	969	/**
AnnaBridge	143:86740a56073b	970	* @brief Disable update event generation.
AnnaBridge	143:86740a56073b	971	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
AnnaBridge	143:86740a56073b	972	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	973	* @retval None
AnnaBridge	143:86740a56073b	974	*/
AnnaBridge	143:86740a56073b	975	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	976	{
AnnaBridge	143:86740a56073b	977	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
AnnaBridge	143:86740a56073b	978	}
AnnaBridge	143:86740a56073b	979
AnnaBridge	143:86740a56073b	980	/**
AnnaBridge	143:86740a56073b	981	* @brief Indicates whether update event generation is enabled.
AnnaBridge	143:86740a56073b	982	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
AnnaBridge	143:86740a56073b	983	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	984	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	985	*/
AnnaBridge	143:86740a56073b	986	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	987	{
AnnaBridge	143:86740a56073b	988	return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
AnnaBridge	143:86740a56073b	989	}
AnnaBridge	143:86740a56073b	990
AnnaBridge	143:86740a56073b	991	/**
AnnaBridge	143:86740a56073b	992	* @brief Set update event source
AnnaBridge	143:86740a56073b	993	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
AnnaBridge	143:86740a56073b	994	* generate an update interrupt or DMA request if enabled:
AnnaBridge	143:86740a56073b	995	* - Counter overflow/underflow
AnnaBridge	143:86740a56073b	996	* - Setting the UG bit
AnnaBridge	143:86740a56073b	997	* - Update generation through the slave mode controller
AnnaBridge	143:86740a56073b	998	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
AnnaBridge	143:86740a56073b	999	* overflow/underflow generates an update interrupt or DMA request if enabled.
AnnaBridge	143:86740a56073b	1000	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
AnnaBridge	143:86740a56073b	1001	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1002	* @param UpdateSource This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1003	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
AnnaBridge	143:86740a56073b	1004	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
AnnaBridge	143:86740a56073b	1005	* @retval None
AnnaBridge	143:86740a56073b	1006	*/
AnnaBridge	143:86740a56073b	1007	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx, uint32_t UpdateSource)
AnnaBridge	143:86740a56073b	1008	{
AnnaBridge	143:86740a56073b	1009	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
AnnaBridge	143:86740a56073b	1010	}
AnnaBridge	143:86740a56073b	1011
AnnaBridge	143:86740a56073b	1012	/**
AnnaBridge	143:86740a56073b	1013	* @brief Get actual event update source
AnnaBridge	143:86740a56073b	1014	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
AnnaBridge	143:86740a56073b	1015	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1016	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	1017	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
AnnaBridge	143:86740a56073b	1018	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
AnnaBridge	143:86740a56073b	1019	*/
AnnaBridge	143:86740a56073b	1020	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	1021	{
AnnaBridge	143:86740a56073b	1022	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
AnnaBridge	143:86740a56073b	1023	}
AnnaBridge	143:86740a56073b	1024
AnnaBridge	143:86740a56073b	1025	/**
AnnaBridge	143:86740a56073b	1026	* @brief Set one pulse mode (one shot v.s. repetitive).
AnnaBridge	143:86740a56073b	1027	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
AnnaBridge	143:86740a56073b	1028	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1029	* @param OnePulseMode This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1030	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
AnnaBridge	143:86740a56073b	1031	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
AnnaBridge	143:86740a56073b	1032	* @retval None
AnnaBridge	143:86740a56073b	1033	*/
AnnaBridge	143:86740a56073b	1034	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx, uint32_t OnePulseMode)
AnnaBridge	143:86740a56073b	1035	{
AnnaBridge	143:86740a56073b	1036	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
AnnaBridge	143:86740a56073b	1037	}
AnnaBridge	143:86740a56073b	1038
AnnaBridge	143:86740a56073b	1039	/**
AnnaBridge	143:86740a56073b	1040	* @brief Get actual one pulse mode.
AnnaBridge	143:86740a56073b	1041	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
AnnaBridge	143:86740a56073b	1042	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1043	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	1044	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
AnnaBridge	143:86740a56073b	1045	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
AnnaBridge	143:86740a56073b	1046	*/
AnnaBridge	143:86740a56073b	1047	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	1048	{
AnnaBridge	143:86740a56073b	1049	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
AnnaBridge	143:86740a56073b	1050	}
AnnaBridge	143:86740a56073b	1051
AnnaBridge	143:86740a56073b	1052	/**
AnnaBridge	143:86740a56073b	1053	* @brief Set the timer counter counting mode.
AnnaBridge	143:86740a56073b	1054	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
AnnaBridge	143:86740a56073b	1055	* check whether or not the counter mode selection feature is supported
AnnaBridge	143:86740a56073b	1056	* by a timer instance.
AnnaBridge	143:86740a56073b	1057	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
AnnaBridge	143:86740a56073b	1058	* CR1 CMS LL_TIM_SetCounterMode
AnnaBridge	143:86740a56073b	1059	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1060	* @param CounterMode This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1061	* @arg @ref LL_TIM_COUNTERMODE_UP
AnnaBridge	143:86740a56073b	1062	* @arg @ref LL_TIM_COUNTERMODE_DOWN
AnnaBridge	143:86740a56073b	1063	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
AnnaBridge	143:86740a56073b	1064	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
AnnaBridge	143:86740a56073b	1065	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
AnnaBridge	143:86740a56073b	1066	* @retval None
AnnaBridge	143:86740a56073b	1067	*/
AnnaBridge	143:86740a56073b	1068	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef * TIMx, uint32_t CounterMode)
AnnaBridge	143:86740a56073b	1069	{
AnnaBridge	143:86740a56073b	1070	MODIFY_REG(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS, CounterMode);
AnnaBridge	143:86740a56073b	1071	}
AnnaBridge	143:86740a56073b	1072
AnnaBridge	143:86740a56073b	1073	/**
AnnaBridge	143:86740a56073b	1074	* @brief Get actual counter mode.
AnnaBridge	143:86740a56073b	1075	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
AnnaBridge	143:86740a56073b	1076	* check whether or not the counter mode selection feature is supported
AnnaBridge	143:86740a56073b	1077	* by a timer instance.
AnnaBridge	143:86740a56073b	1078	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
AnnaBridge	143:86740a56073b	1079	* CR1 CMS LL_TIM_GetCounterMode
AnnaBridge	143:86740a56073b	1080	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1081	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	1082	* @arg @ref LL_TIM_COUNTERMODE_UP
AnnaBridge	143:86740a56073b	1083	* @arg @ref LL_TIM_COUNTERMODE_DOWN
AnnaBridge	143:86740a56073b	1084	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
AnnaBridge	143:86740a56073b	1085	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
AnnaBridge	143:86740a56073b	1086	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
AnnaBridge	143:86740a56073b	1087	*/
AnnaBridge	143:86740a56073b	1088	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	1089	{
AnnaBridge	143:86740a56073b	1090	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
AnnaBridge	143:86740a56073b	1091	}
AnnaBridge	143:86740a56073b	1092
AnnaBridge	143:86740a56073b	1093	/**
AnnaBridge	143:86740a56073b	1094	* @brief Enable auto-reload (ARR) preload.
AnnaBridge	143:86740a56073b	1095	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
AnnaBridge	143:86740a56073b	1096	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1097	* @retval None
AnnaBridge	143:86740a56073b	1098	*/
AnnaBridge	143:86740a56073b	1099	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	1100	{
AnnaBridge	143:86740a56073b	1101	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
AnnaBridge	143:86740a56073b	1102	}
AnnaBridge	143:86740a56073b	1103
AnnaBridge	143:86740a56073b	1104	/**
AnnaBridge	143:86740a56073b	1105	* @brief Disable auto-reload (ARR) preload.
AnnaBridge	143:86740a56073b	1106	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
AnnaBridge	143:86740a56073b	1107	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1108	* @retval None
AnnaBridge	143:86740a56073b	1109	*/
AnnaBridge	143:86740a56073b	1110	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	1111	{
AnnaBridge	143:86740a56073b	1112	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
AnnaBridge	143:86740a56073b	1113	}
AnnaBridge	143:86740a56073b	1114
AnnaBridge	143:86740a56073b	1115	/**
AnnaBridge	143:86740a56073b	1116	* @brief Indicates whether auto-reload (ARR) preload is enabled.
AnnaBridge	143:86740a56073b	1117	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
AnnaBridge	143:86740a56073b	1118	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1119	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1120	*/
AnnaBridge	143:86740a56073b	1121	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	1122	{
AnnaBridge	143:86740a56073b	1123	return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
AnnaBridge	143:86740a56073b	1124	}
AnnaBridge	143:86740a56073b	1125
AnnaBridge	143:86740a56073b	1126	/**
AnnaBridge	143:86740a56073b	1127	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
AnnaBridge	143:86740a56073b	1128	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
AnnaBridge	143:86740a56073b	1129	* whether or not the clock division feature is supported by the timer
AnnaBridge	143:86740a56073b	1130	* instance.
AnnaBridge	143:86740a56073b	1131	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
AnnaBridge	143:86740a56073b	1132	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1133	* @param ClockDivision This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1134	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	143:86740a56073b	1135	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	143:86740a56073b	1136	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	143:86740a56073b	1137	* @retval None
AnnaBridge	143:86740a56073b	1138	*/
AnnaBridge	143:86740a56073b	1139	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef * TIMx, uint32_t ClockDivision)
AnnaBridge	143:86740a56073b	1140	{
AnnaBridge	143:86740a56073b	1141	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
AnnaBridge	143:86740a56073b	1142	}
AnnaBridge	143:86740a56073b	1143
AnnaBridge	143:86740a56073b	1144	/**
AnnaBridge	143:86740a56073b	1145	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
AnnaBridge	143:86740a56073b	1146	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
AnnaBridge	143:86740a56073b	1147	* whether or not the clock division feature is supported by the timer
AnnaBridge	143:86740a56073b	1148	* instance.
AnnaBridge	143:86740a56073b	1149	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
AnnaBridge	143:86740a56073b	1150	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1151	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	1152	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	143:86740a56073b	1153	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	143:86740a56073b	1154	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	143:86740a56073b	1155	*/
AnnaBridge	143:86740a56073b	1156	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	1157	{
AnnaBridge	143:86740a56073b	1158	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
AnnaBridge	143:86740a56073b	1159	}
AnnaBridge	143:86740a56073b	1160
AnnaBridge	143:86740a56073b	1161	/**
AnnaBridge	143:86740a56073b	1162	* @brief Set the counter value.
AnnaBridge	143:86740a56073b	1163	* @rmtoll CNT CNT LL_TIM_SetCounter
AnnaBridge	143:86740a56073b	1164	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1165	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF)
AnnaBridge	143:86740a56073b	1166	* @retval None
AnnaBridge	143:86740a56073b	1167	*/
AnnaBridge	143:86740a56073b	1168	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef * TIMx, uint32_t Counter)
AnnaBridge	143:86740a56073b	1169	{
AnnaBridge	143:86740a56073b	1170	WRITE_REG(TIMx->CNT, Counter);
AnnaBridge	143:86740a56073b	1171	}
AnnaBridge	143:86740a56073b	1172
AnnaBridge	143:86740a56073b	1173	/**
AnnaBridge	143:86740a56073b	1174	* @brief Get the counter value.
AnnaBridge	143:86740a56073b	1175	* @rmtoll CNT CNT LL_TIM_GetCounter
AnnaBridge	143:86740a56073b	1176	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1177	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF)
AnnaBridge	143:86740a56073b	1178	*/
AnnaBridge	143:86740a56073b	1179	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	1180	{
AnnaBridge	143:86740a56073b	1181	return (uint32_t)(READ_REG(TIMx->CNT));
AnnaBridge	143:86740a56073b	1182	}
AnnaBridge	143:86740a56073b	1183
AnnaBridge	143:86740a56073b	1184	/**
AnnaBridge	143:86740a56073b	1185	* @brief Get the current direction of the counter
AnnaBridge	143:86740a56073b	1186	* @rmtoll CR1 DIR LL_TIM_GetDirection
AnnaBridge	143:86740a56073b	1187	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1188	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	1189	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
AnnaBridge	143:86740a56073b	1190	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
AnnaBridge	143:86740a56073b	1191	*/
AnnaBridge	143:86740a56073b	1192	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	1193	{
AnnaBridge	143:86740a56073b	1194	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
AnnaBridge	143:86740a56073b	1195	}
AnnaBridge	143:86740a56073b	1196
AnnaBridge	143:86740a56073b	1197	/**
AnnaBridge	143:86740a56073b	1198	* @brief Set the prescaler value.
AnnaBridge	143:86740a56073b	1199	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
AnnaBridge	143:86740a56073b	1200	* @note The prescaler can be changed on the fly as this control register is buffered. The new
AnnaBridge	143:86740a56073b	1201	* prescaler ratio is taken into account at the next update event.
AnnaBridge	143:86740a56073b	1202	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
AnnaBridge	143:86740a56073b	1203	* @rmtoll PSC PSC LL_TIM_SetPrescaler
AnnaBridge	143:86740a56073b	1204	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1205	* @param Prescaler between Min_Data=0 and Max_Data=65535
AnnaBridge	143:86740a56073b	1206	* @retval None
AnnaBridge	143:86740a56073b	1207	*/
AnnaBridge	143:86740a56073b	1208	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef * TIMx, uint32_t Prescaler)
AnnaBridge	143:86740a56073b	1209	{
AnnaBridge	143:86740a56073b	1210	WRITE_REG(TIMx->PSC, Prescaler);
AnnaBridge	143:86740a56073b	1211	}
AnnaBridge	143:86740a56073b	1212
AnnaBridge	143:86740a56073b	1213	/**
AnnaBridge	143:86740a56073b	1214	* @brief Get the prescaler value.
AnnaBridge	143:86740a56073b	1215	* @rmtoll PSC PSC LL_TIM_GetPrescaler
AnnaBridge	143:86740a56073b	1216	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1217	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
AnnaBridge	143:86740a56073b	1218	*/
AnnaBridge	143:86740a56073b	1219	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	1220	{
AnnaBridge	143:86740a56073b	1221	return (uint32_t)(READ_REG(TIMx->PSC));
AnnaBridge	143:86740a56073b	1222	}
AnnaBridge	143:86740a56073b	1223
AnnaBridge	143:86740a56073b	1224	/**
AnnaBridge	143:86740a56073b	1225	* @brief Set the auto-reload value.
AnnaBridge	143:86740a56073b	1226	* @note The counter is blocked while the auto-reload value is null.
AnnaBridge	143:86740a56073b	1227	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
AnnaBridge	143:86740a56073b	1228	* @rmtoll ARR ARR LL_TIM_SetAutoReload
AnnaBridge	143:86740a56073b	1229	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1230	* @param AutoReload between Min_Data=0 and Max_Data=65535
AnnaBridge	143:86740a56073b	1231	* @retval None
AnnaBridge	143:86740a56073b	1232	*/
AnnaBridge	143:86740a56073b	1233	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef * TIMx, uint32_t AutoReload)
AnnaBridge	143:86740a56073b	1234	{
AnnaBridge	143:86740a56073b	1235	WRITE_REG(TIMx->ARR, AutoReload);
AnnaBridge	143:86740a56073b	1236	}
AnnaBridge	143:86740a56073b	1237
AnnaBridge	143:86740a56073b	1238	/**
AnnaBridge	143:86740a56073b	1239	* @brief Get the auto-reload value.
AnnaBridge	143:86740a56073b	1240	* @rmtoll ARR ARR LL_TIM_GetAutoReload
AnnaBridge	143:86740a56073b	1241	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1242	* @retval Auto-reload value
AnnaBridge	143:86740a56073b	1243	*/
AnnaBridge	143:86740a56073b	1244	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	1245	{
AnnaBridge	143:86740a56073b	1246	return (uint32_t)(READ_REG(TIMx->ARR));
AnnaBridge	143:86740a56073b	1247	}
AnnaBridge	143:86740a56073b	1248
AnnaBridge	143:86740a56073b	1249
AnnaBridge	143:86740a56073b	1250
AnnaBridge	143:86740a56073b	1251	/**
AnnaBridge	143:86740a56073b	1252	* @}
AnnaBridge	143:86740a56073b	1253	*/
AnnaBridge	143:86740a56073b	1254
AnnaBridge	143:86740a56073b	1255	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
AnnaBridge	143:86740a56073b	1256	* @{
AnnaBridge	143:86740a56073b	1257	*/
AnnaBridge	143:86740a56073b	1258
AnnaBridge	143:86740a56073b	1259	/**
AnnaBridge	143:86740a56073b	1260	* @brief Set the trigger of the capture/compare DMA request.
AnnaBridge	143:86740a56073b	1261	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
AnnaBridge	143:86740a56073b	1262	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1263	* @param DMAReqTrigger This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1264	* @arg @ref LL_TIM_CCDMAREQUEST_CC
AnnaBridge	143:86740a56073b	1265	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
AnnaBridge	143:86740a56073b	1266	* @retval None
AnnaBridge	143:86740a56073b	1267	*/
AnnaBridge	143:86740a56073b	1268	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx, uint32_t DMAReqTrigger)
AnnaBridge	143:86740a56073b	1269	{
AnnaBridge	143:86740a56073b	1270	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
AnnaBridge	143:86740a56073b	1271	}
AnnaBridge	143:86740a56073b	1272
AnnaBridge	143:86740a56073b	1273	/**
AnnaBridge	143:86740a56073b	1274	* @brief Get actual trigger of the capture/compare DMA request.
AnnaBridge	143:86740a56073b	1275	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
AnnaBridge	143:86740a56073b	1276	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1277	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	1278	* @arg @ref LL_TIM_CCDMAREQUEST_CC
AnnaBridge	143:86740a56073b	1279	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
AnnaBridge	143:86740a56073b	1280	*/
AnnaBridge	143:86740a56073b	1281	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	1282	{
AnnaBridge	143:86740a56073b	1283	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
AnnaBridge	143:86740a56073b	1284	}
AnnaBridge	143:86740a56073b	1285
AnnaBridge	143:86740a56073b	1286
AnnaBridge	143:86740a56073b	1287	/**
AnnaBridge	143:86740a56073b	1288	* @brief Enable capture/compare channels.
AnnaBridge	143:86740a56073b	1289	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
AnnaBridge	143:86740a56073b	1290	* CCER CC2E LL_TIM_CC_EnableChannel\n
AnnaBridge	143:86740a56073b	1291	* CCER CC3E LL_TIM_CC_EnableChannel\n
AnnaBridge	143:86740a56073b	1292	* CCER CC4E LL_TIM_CC_EnableChannel
AnnaBridge	143:86740a56073b	1293	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1294	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	143:86740a56073b	1295	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1296	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1297	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1298	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1299	* @retval None
AnnaBridge	143:86740a56073b	1300	*/
AnnaBridge	143:86740a56073b	1301	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx, uint32_t Channels)
AnnaBridge	143:86740a56073b	1302	{
AnnaBridge	143:86740a56073b	1303	SET_BIT(TIMx->CCER, Channels);
AnnaBridge	143:86740a56073b	1304	}
AnnaBridge	143:86740a56073b	1305
AnnaBridge	143:86740a56073b	1306	/**
AnnaBridge	143:86740a56073b	1307	* @brief Disable capture/compare channels.
AnnaBridge	143:86740a56073b	1308	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
AnnaBridge	143:86740a56073b	1309	* CCER CC2E LL_TIM_CC_DisableChannel\n
AnnaBridge	143:86740a56073b	1310	* CCER CC3E LL_TIM_CC_DisableChannel\n
AnnaBridge	143:86740a56073b	1311	* CCER CC4E LL_TIM_CC_DisableChannel
AnnaBridge	143:86740a56073b	1312	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1313	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	143:86740a56073b	1314	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1315	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1316	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1317	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1318	* @retval None
AnnaBridge	143:86740a56073b	1319	*/
AnnaBridge	143:86740a56073b	1320	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx, uint32_t Channels)
AnnaBridge	143:86740a56073b	1321	{
AnnaBridge	143:86740a56073b	1322	CLEAR_BIT(TIMx->CCER, Channels);
AnnaBridge	143:86740a56073b	1323	}
AnnaBridge	143:86740a56073b	1324
AnnaBridge	143:86740a56073b	1325	/**
AnnaBridge	143:86740a56073b	1326	* @brief Indicate whether channel(s) is(are) enabled.
AnnaBridge	143:86740a56073b	1327	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	143:86740a56073b	1328	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	143:86740a56073b	1329	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	143:86740a56073b	1330	* CCER CC4E LL_TIM_CC_IsEnabledChannel
AnnaBridge	143:86740a56073b	1331	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1332	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	143:86740a56073b	1333	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1334	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1335	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1336	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1337	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1338	*/
AnnaBridge	143:86740a56073b	1339	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef * TIMx, uint32_t Channels)
AnnaBridge	143:86740a56073b	1340	{
AnnaBridge	143:86740a56073b	1341	return (READ_BIT(TIMx->CCER, Channels) == (Channels));
AnnaBridge	143:86740a56073b	1342	}
AnnaBridge	143:86740a56073b	1343
AnnaBridge	143:86740a56073b	1344	/**
AnnaBridge	143:86740a56073b	1345	* @}
AnnaBridge	143:86740a56073b	1346	*/
AnnaBridge	143:86740a56073b	1347
AnnaBridge	143:86740a56073b	1348	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
AnnaBridge	143:86740a56073b	1349	* @{
AnnaBridge	143:86740a56073b	1350	*/
AnnaBridge	143:86740a56073b	1351	/**
AnnaBridge	143:86740a56073b	1352	* @brief Configure an output channel.
AnnaBridge	143:86740a56073b	1353	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
AnnaBridge	143:86740a56073b	1354	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
AnnaBridge	143:86740a56073b	1355	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
AnnaBridge	143:86740a56073b	1356	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
AnnaBridge	143:86740a56073b	1357	* CCER CC1P LL_TIM_OC_ConfigOutput\n
AnnaBridge	143:86740a56073b	1358	* CCER CC2P LL_TIM_OC_ConfigOutput\n
AnnaBridge	143:86740a56073b	1359	* CCER CC3P LL_TIM_OC_ConfigOutput\n
AnnaBridge	143:86740a56073b	1360	* CCER CC4P LL_TIM_OC_ConfigOutput\n
AnnaBridge	143:86740a56073b	1361	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1362	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1363	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1364	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1365	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1366	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1367	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	143:86740a56073b	1368	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	143:86740a56073b	1369	* @retval None
AnnaBridge	143:86740a56073b	1370	*/
AnnaBridge	143:86740a56073b	1371	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	143:86740a56073b	1372	{
AnnaBridge	143:86740a56073b	1373	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	1374	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	143:86740a56073b	1375	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	143:86740a56073b	1376	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	143:86740a56073b	1377	}
AnnaBridge	143:86740a56073b	1378
AnnaBridge	143:86740a56073b	1379	/**
AnnaBridge	143:86740a56073b	1380	* @brief Define the behavior of the output reference signal OCxREF from which
AnnaBridge	143:86740a56073b	1381	* OCx and OCxN (when relevant) are derived.
AnnaBridge	143:86740a56073b	1382	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
AnnaBridge	143:86740a56073b	1383	* CCMR1 OC2M LL_TIM_OC_SetMode\n
AnnaBridge	143:86740a56073b	1384	* CCMR2 OC3M LL_TIM_OC_SetMode\n
AnnaBridge	143:86740a56073b	1385	* CCMR2 OC4M LL_TIM_OC_SetMode
AnnaBridge	143:86740a56073b	1386	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1387	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1388	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1389	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1390	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1391	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1392	* @param Mode This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1393	* @arg @ref LL_TIM_OCMODE_FROZEN
AnnaBridge	143:86740a56073b	1394	* @arg @ref LL_TIM_OCMODE_ACTIVE
AnnaBridge	143:86740a56073b	1395	* @arg @ref LL_TIM_OCMODE_INACTIVE
AnnaBridge	143:86740a56073b	1396	* @arg @ref LL_TIM_OCMODE_TOGGLE
AnnaBridge	143:86740a56073b	1397	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
AnnaBridge	143:86740a56073b	1398	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
AnnaBridge	143:86740a56073b	1399	* @arg @ref LL_TIM_OCMODE_PWM1
AnnaBridge	143:86740a56073b	1400	* @arg @ref LL_TIM_OCMODE_PWM2
AnnaBridge	143:86740a56073b	1401	* @retval None
AnnaBridge	143:86740a56073b	1402	*/
AnnaBridge	143:86740a56073b	1403	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Mode)
AnnaBridge	143:86740a56073b	1404	{
AnnaBridge	143:86740a56073b	1405	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	1406	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	143:86740a56073b	1407	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
AnnaBridge	143:86740a56073b	1408	}
AnnaBridge	143:86740a56073b	1409
AnnaBridge	143:86740a56073b	1410	/**
AnnaBridge	143:86740a56073b	1411	* @brief Get the output compare mode of an output channel.
AnnaBridge	143:86740a56073b	1412	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
AnnaBridge	143:86740a56073b	1413	* CCMR1 OC2M LL_TIM_OC_GetMode\n
AnnaBridge	143:86740a56073b	1414	* CCMR2 OC3M LL_TIM_OC_GetMode\n
AnnaBridge	143:86740a56073b	1415	* CCMR2 OC4M LL_TIM_OC_GetMode
AnnaBridge	143:86740a56073b	1416	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1417	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1418	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1419	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1420	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1421	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1422	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	1423	* @arg @ref LL_TIM_OCMODE_FROZEN
AnnaBridge	143:86740a56073b	1424	* @arg @ref LL_TIM_OCMODE_ACTIVE
AnnaBridge	143:86740a56073b	1425	* @arg @ref LL_TIM_OCMODE_INACTIVE
AnnaBridge	143:86740a56073b	1426	* @arg @ref LL_TIM_OCMODE_TOGGLE
AnnaBridge	143:86740a56073b	1427	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
AnnaBridge	143:86740a56073b	1428	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
AnnaBridge	143:86740a56073b	1429	* @arg @ref LL_TIM_OCMODE_PWM1
AnnaBridge	143:86740a56073b	1430	* @arg @ref LL_TIM_OCMODE_PWM2
AnnaBridge	143:86740a56073b	1431	*/
AnnaBridge	143:86740a56073b	1432	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef * TIMx, uint32_t Channel)
AnnaBridge	143:86740a56073b	1433	{
AnnaBridge	143:86740a56073b	1434	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	1435	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	143:86740a56073b	1436	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
AnnaBridge	143:86740a56073b	1437	}
AnnaBridge	143:86740a56073b	1438
AnnaBridge	143:86740a56073b	1439	/**
AnnaBridge	143:86740a56073b	1440	* @brief Set the polarity of an output channel.
AnnaBridge	143:86740a56073b	1441	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
AnnaBridge	143:86740a56073b	1442	* CCER CC2P LL_TIM_OC_SetPolarity\n
AnnaBridge	143:86740a56073b	1443	* CCER CC3P LL_TIM_OC_SetPolarity\n
AnnaBridge	143:86740a56073b	1444	* CCER CC4P LL_TIM_OC_SetPolarity
AnnaBridge	143:86740a56073b	1445	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1446	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1447	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1448	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1449	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1450	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1451	* @param Polarity This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1452	* @arg @ref LL_TIM_OCPOLARITY_HIGH
AnnaBridge	143:86740a56073b	1453	* @arg @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	143:86740a56073b	1454	* @retval None
AnnaBridge	143:86740a56073b	1455	*/
AnnaBridge	143:86740a56073b	1456	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Polarity)
AnnaBridge	143:86740a56073b	1457	{
AnnaBridge	143:86740a56073b	1458	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	1459	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	143:86740a56073b	1460	}
AnnaBridge	143:86740a56073b	1461
AnnaBridge	143:86740a56073b	1462	/**
AnnaBridge	143:86740a56073b	1463	* @brief Get the polarity of an output channel.
AnnaBridge	143:86740a56073b	1464	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
AnnaBridge	143:86740a56073b	1465	* CCER CC2P LL_TIM_OC_GetPolarity\n
AnnaBridge	143:86740a56073b	1466	* CCER CC3P LL_TIM_OC_GetPolarity\n
AnnaBridge	143:86740a56073b	1467	* CCER CC4P LL_TIM_OC_GetPolarity
AnnaBridge	143:86740a56073b	1468	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1469	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1470	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1471	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1472	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1473	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1474	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	1475	* @arg @ref LL_TIM_OCPOLARITY_HIGH
AnnaBridge	143:86740a56073b	1476	* @arg @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	143:86740a56073b	1477	*/
AnnaBridge	143:86740a56073b	1478	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef * TIMx, uint32_t Channel)
AnnaBridge	143:86740a56073b	1479	{
AnnaBridge	143:86740a56073b	1480	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	1481	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	143:86740a56073b	1482	}
AnnaBridge	143:86740a56073b	1483
AnnaBridge	143:86740a56073b	1484
AnnaBridge	143:86740a56073b	1485	/**
AnnaBridge	143:86740a56073b	1486	* @brief Enable fast mode for the output channel.
AnnaBridge	143:86740a56073b	1487	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
AnnaBridge	143:86740a56073b	1488	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
AnnaBridge	143:86740a56073b	1489	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
AnnaBridge	143:86740a56073b	1490	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
AnnaBridge	143:86740a56073b	1491	* CCMR2 OC4FE LL_TIM_OC_EnableFast
AnnaBridge	143:86740a56073b	1492	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1493	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1494	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1495	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1496	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1497	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1498	* @retval None
AnnaBridge	143:86740a56073b	1499	*/
AnnaBridge	143:86740a56073b	1500	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx, uint32_t Channel)
AnnaBridge	143:86740a56073b	1501	{
AnnaBridge	143:86740a56073b	1502	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	1503	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	143:86740a56073b	1504	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	143:86740a56073b	1505
AnnaBridge	143:86740a56073b	1506	}
AnnaBridge	143:86740a56073b	1507
AnnaBridge	143:86740a56073b	1508	/**
AnnaBridge	143:86740a56073b	1509	* @brief Disable fast mode for the output channel.
AnnaBridge	143:86740a56073b	1510	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
AnnaBridge	143:86740a56073b	1511	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
AnnaBridge	143:86740a56073b	1512	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
AnnaBridge	143:86740a56073b	1513	* CCMR2 OC4FE LL_TIM_OC_DisableFast
AnnaBridge	143:86740a56073b	1514	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1515	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1516	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1517	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1518	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1519	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1520	* @retval None
AnnaBridge	143:86740a56073b	1521	*/
AnnaBridge	143:86740a56073b	1522	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx, uint32_t Channel)
AnnaBridge	143:86740a56073b	1523	{
AnnaBridge	143:86740a56073b	1524	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	1525	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	143:86740a56073b	1526	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	143:86740a56073b	1527
AnnaBridge	143:86740a56073b	1528	}
AnnaBridge	143:86740a56073b	1529
AnnaBridge	143:86740a56073b	1530	/**
AnnaBridge	143:86740a56073b	1531	* @brief Indicates whether fast mode is enabled for the output channel.
AnnaBridge	143:86740a56073b	1532	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	143:86740a56073b	1533	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	143:86740a56073b	1534	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	143:86740a56073b	1535	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	143:86740a56073b	1536	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1537	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1538	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1539	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1540	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1541	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1542	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1543	*/
AnnaBridge	143:86740a56073b	1544	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef * TIMx, uint32_t Channel)
AnnaBridge	143:86740a56073b	1545	{
AnnaBridge	143:86740a56073b	1546	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	1547	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	143:86740a56073b	1548	register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	143:86740a56073b	1549	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	143:86740a56073b	1550	}
AnnaBridge	143:86740a56073b	1551
AnnaBridge	143:86740a56073b	1552	/**
AnnaBridge	143:86740a56073b	1553	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
AnnaBridge	143:86740a56073b	1554	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
AnnaBridge	143:86740a56073b	1555	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
AnnaBridge	143:86740a56073b	1556	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
AnnaBridge	143:86740a56073b	1557	* CCMR2 OC4PE LL_TIM_OC_EnablePreload
AnnaBridge	143:86740a56073b	1558	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1559	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1560	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1561	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1562	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1563	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1564	* @retval None
AnnaBridge	143:86740a56073b	1565	*/
AnnaBridge	143:86740a56073b	1566	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx, uint32_t Channel)
AnnaBridge	143:86740a56073b	1567	{
AnnaBridge	143:86740a56073b	1568	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	1569	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	143:86740a56073b	1570	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	143:86740a56073b	1571	}
AnnaBridge	143:86740a56073b	1572
AnnaBridge	143:86740a56073b	1573	/**
AnnaBridge	143:86740a56073b	1574	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
AnnaBridge	143:86740a56073b	1575	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
AnnaBridge	143:86740a56073b	1576	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
AnnaBridge	143:86740a56073b	1577	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
AnnaBridge	143:86740a56073b	1578	* CCMR2 OC4PE LL_TIM_OC_DisablePreload
AnnaBridge	143:86740a56073b	1579	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1580	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1581	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1582	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1583	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1584	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1585	* @retval None
AnnaBridge	143:86740a56073b	1586	*/
AnnaBridge	143:86740a56073b	1587	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx, uint32_t Channel)
AnnaBridge	143:86740a56073b	1588	{
AnnaBridge	143:86740a56073b	1589	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	1590	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	143:86740a56073b	1591	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	143:86740a56073b	1592	}
AnnaBridge	143:86740a56073b	1593
AnnaBridge	143:86740a56073b	1594	/**
AnnaBridge	143:86740a56073b	1595	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
AnnaBridge	143:86740a56073b	1596	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	143:86740a56073b	1597	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	143:86740a56073b	1598	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	143:86740a56073b	1599	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	143:86740a56073b	1600	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1601	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1602	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1603	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1604	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1605	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1606	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1607	*/
AnnaBridge	143:86740a56073b	1608	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef * TIMx, uint32_t Channel)
AnnaBridge	143:86740a56073b	1609	{
AnnaBridge	143:86740a56073b	1610	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	1611	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	143:86740a56073b	1612	register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	143:86740a56073b	1613	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	143:86740a56073b	1614	}
AnnaBridge	143:86740a56073b	1615
AnnaBridge	143:86740a56073b	1616	/**
AnnaBridge	143:86740a56073b	1617	* @brief Enable clearing the output channel on an external event.
AnnaBridge	143:86740a56073b	1618	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
AnnaBridge	143:86740a56073b	1619	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	143:86740a56073b	1620	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	143:86740a56073b	1621	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
AnnaBridge	143:86740a56073b	1622	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
AnnaBridge	143:86740a56073b	1623	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
AnnaBridge	143:86740a56073b	1624	* CCMR2 OC4CE LL_TIM_OC_EnableClear
AnnaBridge	143:86740a56073b	1625	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1626	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1627	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1628	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1629	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1630	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1631	* @retval None
AnnaBridge	143:86740a56073b	1632	*/
AnnaBridge	143:86740a56073b	1633	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx, uint32_t Channel)
AnnaBridge	143:86740a56073b	1634	{
AnnaBridge	143:86740a56073b	1635	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	1636	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	143:86740a56073b	1637	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	143:86740a56073b	1638	}
AnnaBridge	143:86740a56073b	1639
AnnaBridge	143:86740a56073b	1640	/**
AnnaBridge	143:86740a56073b	1641	* @brief Disable clearing the output channel on an external event.
AnnaBridge	143:86740a56073b	1642	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	143:86740a56073b	1643	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	143:86740a56073b	1644	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
AnnaBridge	143:86740a56073b	1645	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
AnnaBridge	143:86740a56073b	1646	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
AnnaBridge	143:86740a56073b	1647	* CCMR2 OC4CE LL_TIM_OC_DisableClear
AnnaBridge	143:86740a56073b	1648	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1649	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1650	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1651	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1652	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1653	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1654	* @retval None
AnnaBridge	143:86740a56073b	1655	*/
AnnaBridge	143:86740a56073b	1656	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx, uint32_t Channel)
AnnaBridge	143:86740a56073b	1657	{
AnnaBridge	143:86740a56073b	1658	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	1659	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	143:86740a56073b	1660	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	143:86740a56073b	1661	}
AnnaBridge	143:86740a56073b	1662
AnnaBridge	143:86740a56073b	1663	/**
AnnaBridge	143:86740a56073b	1664	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
AnnaBridge	143:86740a56073b	1665	* @note This function enables clearing the output channel on an external event.
AnnaBridge	143:86740a56073b	1666	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
AnnaBridge	143:86740a56073b	1667	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	143:86740a56073b	1668	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	143:86740a56073b	1669	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	143:86740a56073b	1670	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	143:86740a56073b	1671	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	143:86740a56073b	1672	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	143:86740a56073b	1673	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1674	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1675	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1676	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1677	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1678	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1679	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1680	*/
AnnaBridge	143:86740a56073b	1681	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef * TIMx, uint32_t Channel)
AnnaBridge	143:86740a56073b	1682	{
AnnaBridge	143:86740a56073b	1683	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	1684	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	143:86740a56073b	1685	register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	143:86740a56073b	1686	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	143:86740a56073b	1687	}
AnnaBridge	143:86740a56073b	1688
AnnaBridge	143:86740a56073b	1689
AnnaBridge	143:86740a56073b	1690	/**
AnnaBridge	143:86740a56073b	1691	* @brief Set compare value for output channel 1 (TIMx_CCR1).
AnnaBridge	143:86740a56073b	1692	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	1693	* output channel 1 is supported by a timer instance.
AnnaBridge	143:86740a56073b	1694	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
AnnaBridge	143:86740a56073b	1695	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1696	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	143:86740a56073b	1697	* @retval None
AnnaBridge	143:86740a56073b	1698	*/
AnnaBridge	143:86740a56073b	1699	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx, uint32_t CompareValue)
AnnaBridge	143:86740a56073b	1700	{
AnnaBridge	143:86740a56073b	1701	WRITE_REG(TIMx->CCR1, CompareValue);
AnnaBridge	143:86740a56073b	1702	}
AnnaBridge	143:86740a56073b	1703
AnnaBridge	143:86740a56073b	1704	/**
AnnaBridge	143:86740a56073b	1705	* @brief Set compare value for output channel 2 (TIMx_CCR2).
AnnaBridge	143:86740a56073b	1706	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	1707	* output channel 2 is supported by a timer instance.
AnnaBridge	143:86740a56073b	1708	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
AnnaBridge	143:86740a56073b	1709	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1710	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	143:86740a56073b	1711	* @retval None
AnnaBridge	143:86740a56073b	1712	*/
AnnaBridge	143:86740a56073b	1713	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx, uint32_t CompareValue)
AnnaBridge	143:86740a56073b	1714	{
AnnaBridge	143:86740a56073b	1715	WRITE_REG(TIMx->CCR2, CompareValue);
AnnaBridge	143:86740a56073b	1716	}
AnnaBridge	143:86740a56073b	1717
AnnaBridge	143:86740a56073b	1718	/**
AnnaBridge	143:86740a56073b	1719	* @brief Set compare value for output channel 3 (TIMx_CCR3).
AnnaBridge	143:86740a56073b	1720	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	1721	* output channel is supported by a timer instance.
AnnaBridge	143:86740a56073b	1722	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
AnnaBridge	143:86740a56073b	1723	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1724	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	143:86740a56073b	1725	* @retval None
AnnaBridge	143:86740a56073b	1726	*/
AnnaBridge	143:86740a56073b	1727	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx, uint32_t CompareValue)
AnnaBridge	143:86740a56073b	1728	{
AnnaBridge	143:86740a56073b	1729	WRITE_REG(TIMx->CCR3, CompareValue);
AnnaBridge	143:86740a56073b	1730	}
AnnaBridge	143:86740a56073b	1731
AnnaBridge	143:86740a56073b	1732	/**
AnnaBridge	143:86740a56073b	1733	* @brief Set compare value for output channel 4 (TIMx_CCR4).
AnnaBridge	143:86740a56073b	1734	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	1735	* output channel 4 is supported by a timer instance.
AnnaBridge	143:86740a56073b	1736	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
AnnaBridge	143:86740a56073b	1737	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1738	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	143:86740a56073b	1739	* @retval None
AnnaBridge	143:86740a56073b	1740	*/
AnnaBridge	143:86740a56073b	1741	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx, uint32_t CompareValue)
AnnaBridge	143:86740a56073b	1742	{
AnnaBridge	143:86740a56073b	1743	WRITE_REG(TIMx->CCR4, CompareValue);
AnnaBridge	143:86740a56073b	1744	}
AnnaBridge	143:86740a56073b	1745
AnnaBridge	143:86740a56073b	1746
AnnaBridge	143:86740a56073b	1747	/**
AnnaBridge	143:86740a56073b	1748	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
AnnaBridge	143:86740a56073b	1749	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	1750	* output channel 1 is supported by a timer instance.
AnnaBridge	143:86740a56073b	1751	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
AnnaBridge	143:86740a56073b	1752	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1753	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	143:86740a56073b	1754	*/
AnnaBridge	143:86740a56073b	1755	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	1756	{
AnnaBridge	143:86740a56073b	1757	return (uint32_t)(READ_REG(TIMx->CCR1));
AnnaBridge	143:86740a56073b	1758	}
AnnaBridge	143:86740a56073b	1759
AnnaBridge	143:86740a56073b	1760	/**
AnnaBridge	143:86740a56073b	1761	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
AnnaBridge	143:86740a56073b	1762	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	1763	* output channel 2 is supported by a timer instance.
AnnaBridge	143:86740a56073b	1764	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
AnnaBridge	143:86740a56073b	1765	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1766	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	143:86740a56073b	1767	*/
AnnaBridge	143:86740a56073b	1768	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	1769	{
AnnaBridge	143:86740a56073b	1770	return (uint32_t)(READ_REG(TIMx->CCR2));
AnnaBridge	143:86740a56073b	1771	}
AnnaBridge	143:86740a56073b	1772
AnnaBridge	143:86740a56073b	1773	/**
AnnaBridge	143:86740a56073b	1774	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
AnnaBridge	143:86740a56073b	1775	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	1776	* output channel 3 is supported by a timer instance.
AnnaBridge	143:86740a56073b	1777	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
AnnaBridge	143:86740a56073b	1778	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1779	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	143:86740a56073b	1780	*/
AnnaBridge	143:86740a56073b	1781	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	1782	{
AnnaBridge	143:86740a56073b	1783	return (uint32_t)(READ_REG(TIMx->CCR3));
AnnaBridge	143:86740a56073b	1784	}
AnnaBridge	143:86740a56073b	1785
AnnaBridge	143:86740a56073b	1786	/**
AnnaBridge	143:86740a56073b	1787	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
AnnaBridge	143:86740a56073b	1788	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	1789	* output channel 4 is supported by a timer instance.
AnnaBridge	143:86740a56073b	1790	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
AnnaBridge	143:86740a56073b	1791	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1792	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	143:86740a56073b	1793	*/
AnnaBridge	143:86740a56073b	1794	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	1795	{
AnnaBridge	143:86740a56073b	1796	return (uint32_t)(READ_REG(TIMx->CCR4));
AnnaBridge	143:86740a56073b	1797	}
AnnaBridge	143:86740a56073b	1798
AnnaBridge	143:86740a56073b	1799
AnnaBridge	143:86740a56073b	1800
AnnaBridge	143:86740a56073b	1801	/**
AnnaBridge	143:86740a56073b	1802	* @}
AnnaBridge	143:86740a56073b	1803	*/
AnnaBridge	143:86740a56073b	1804
AnnaBridge	143:86740a56073b	1805	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
AnnaBridge	143:86740a56073b	1806	* @{
AnnaBridge	143:86740a56073b	1807	*/
AnnaBridge	143:86740a56073b	1808	/**
AnnaBridge	143:86740a56073b	1809	* @brief Configure input channel.
AnnaBridge	143:86740a56073b	1810	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
AnnaBridge	143:86740a56073b	1811	* CCMR1 IC1PSC LL_TIM_IC_Config\n
AnnaBridge	143:86740a56073b	1812	* CCMR1 IC1F LL_TIM_IC_Config\n
AnnaBridge	143:86740a56073b	1813	* CCMR1 CC2S LL_TIM_IC_Config\n
AnnaBridge	143:86740a56073b	1814	* CCMR1 IC2PSC LL_TIM_IC_Config\n
AnnaBridge	143:86740a56073b	1815	* CCMR1 IC2F LL_TIM_IC_Config\n
AnnaBridge	143:86740a56073b	1816	* CCMR2 CC3S LL_TIM_IC_Config\n
AnnaBridge	143:86740a56073b	1817	* CCMR2 IC3PSC LL_TIM_IC_Config\n
AnnaBridge	143:86740a56073b	1818	* CCMR2 IC3F LL_TIM_IC_Config\n
AnnaBridge	143:86740a56073b	1819	* CCMR2 CC4S LL_TIM_IC_Config\n
AnnaBridge	143:86740a56073b	1820	* CCMR2 IC4PSC LL_TIM_IC_Config\n
AnnaBridge	143:86740a56073b	1821	* CCMR2 IC4F LL_TIM_IC_Config\n
AnnaBridge	143:86740a56073b	1822	* CCER CC1P LL_TIM_IC_Config\n
AnnaBridge	143:86740a56073b	1823	* CCER CC1NP LL_TIM_IC_Config\n
AnnaBridge	143:86740a56073b	1824	* CCER CC2P LL_TIM_IC_Config\n
AnnaBridge	143:86740a56073b	1825	* CCER CC2NP LL_TIM_IC_Config\n
AnnaBridge	143:86740a56073b	1826	* CCER CC3P LL_TIM_IC_Config\n
AnnaBridge	143:86740a56073b	1827	* CCER CC3NP LL_TIM_IC_Config\n
AnnaBridge	143:86740a56073b	1828	* CCER CC4P LL_TIM_IC_Config\n
AnnaBridge	143:86740a56073b	1829	* CCER CC4NP LL_TIM_IC_Config
AnnaBridge	143:86740a56073b	1830	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1831	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1832	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1833	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1834	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1835	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1836	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	143:86740a56073b	1837	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	143:86740a56073b	1838	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
AnnaBridge	143:86740a56073b	1839	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	143:86740a56073b	1840	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	143:86740a56073b	1841	* @retval None
AnnaBridge	143:86740a56073b	1842	*/
AnnaBridge	143:86740a56073b	1843	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	143:86740a56073b	1844	{
AnnaBridge	143:86740a56073b	1845	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	1846	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	143:86740a56073b	1847	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), ((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	143:86740a56073b	1848	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), (Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	143:86740a56073b	1849	}
AnnaBridge	143:86740a56073b	1850
AnnaBridge	143:86740a56073b	1851	/**
AnnaBridge	143:86740a56073b	1852	* @brief Set the active input.
AnnaBridge	143:86740a56073b	1853	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
AnnaBridge	143:86740a56073b	1854	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
AnnaBridge	143:86740a56073b	1855	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
AnnaBridge	143:86740a56073b	1856	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
AnnaBridge	143:86740a56073b	1857	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1858	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1859	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1860	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1861	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1862	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1863	* @param ICActiveInput This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1864	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
AnnaBridge	143:86740a56073b	1865	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
AnnaBridge	143:86740a56073b	1866	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	143:86740a56073b	1867	* @retval None
AnnaBridge	143:86740a56073b	1868	*/
AnnaBridge	143:86740a56073b	1869	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICActiveInput)
AnnaBridge	143:86740a56073b	1870	{
AnnaBridge	143:86740a56073b	1871	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	1872	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	143:86740a56073b	1873	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	143:86740a56073b	1874	}
AnnaBridge	143:86740a56073b	1875
AnnaBridge	143:86740a56073b	1876	/**
AnnaBridge	143:86740a56073b	1877	* @brief Get the current active input.
AnnaBridge	143:86740a56073b	1878	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
AnnaBridge	143:86740a56073b	1879	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
AnnaBridge	143:86740a56073b	1880	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
AnnaBridge	143:86740a56073b	1881	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
AnnaBridge	143:86740a56073b	1882	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1883	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1884	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1885	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1886	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1887	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1888	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	1889	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
AnnaBridge	143:86740a56073b	1890	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
AnnaBridge	143:86740a56073b	1891	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	143:86740a56073b	1892	*/
AnnaBridge	143:86740a56073b	1893	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef * TIMx, uint32_t Channel)
AnnaBridge	143:86740a56073b	1894	{
AnnaBridge	143:86740a56073b	1895	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	1896	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	143:86740a56073b	1897	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	143:86740a56073b	1898	}
AnnaBridge	143:86740a56073b	1899
AnnaBridge	143:86740a56073b	1900	/**
AnnaBridge	143:86740a56073b	1901	* @brief Set the prescaler of input channel.
AnnaBridge	143:86740a56073b	1902	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	143:86740a56073b	1903	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	143:86740a56073b	1904	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	143:86740a56073b	1905	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
AnnaBridge	143:86740a56073b	1906	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1907	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1908	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1909	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1910	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1911	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1912	* @param ICPrescaler This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1913	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	143:86740a56073b	1914	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	143:86740a56073b	1915	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	143:86740a56073b	1916	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	143:86740a56073b	1917	* @retval None
AnnaBridge	143:86740a56073b	1918	*/
AnnaBridge	143:86740a56073b	1919	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICPrescaler)
AnnaBridge	143:86740a56073b	1920	{
AnnaBridge	143:86740a56073b	1921	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	1922	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	143:86740a56073b	1923	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	143:86740a56073b	1924	}
AnnaBridge	143:86740a56073b	1925
AnnaBridge	143:86740a56073b	1926	/**
AnnaBridge	143:86740a56073b	1927	* @brief Get the current prescaler value acting on an input channel.
AnnaBridge	143:86740a56073b	1928	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	143:86740a56073b	1929	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	143:86740a56073b	1930	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	143:86740a56073b	1931	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
AnnaBridge	143:86740a56073b	1932	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1933	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1934	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1935	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1936	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1937	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1938	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	1939	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	143:86740a56073b	1940	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	143:86740a56073b	1941	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	143:86740a56073b	1942	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	143:86740a56073b	1943	*/
AnnaBridge	143:86740a56073b	1944	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef * TIMx, uint32_t Channel)
AnnaBridge	143:86740a56073b	1945	{
AnnaBridge	143:86740a56073b	1946	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	1947	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	143:86740a56073b	1948	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	143:86740a56073b	1949	}
AnnaBridge	143:86740a56073b	1950
AnnaBridge	143:86740a56073b	1951	/**
AnnaBridge	143:86740a56073b	1952	* @brief Set the input filter duration.
AnnaBridge	143:86740a56073b	1953	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
AnnaBridge	143:86740a56073b	1954	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
AnnaBridge	143:86740a56073b	1955	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
AnnaBridge	143:86740a56073b	1956	* CCMR2 IC4F LL_TIM_IC_SetFilter
AnnaBridge	143:86740a56073b	1957	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1958	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1959	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1960	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1961	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	1962	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	1963	* @param ICFilter This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1964	* @arg @ref LL_TIM_IC_FILTER_FDIV1
AnnaBridge	143:86740a56073b	1965	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
AnnaBridge	143:86740a56073b	1966	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
AnnaBridge	143:86740a56073b	1967	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
AnnaBridge	143:86740a56073b	1968	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
AnnaBridge	143:86740a56073b	1969	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
AnnaBridge	143:86740a56073b	1970	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
AnnaBridge	143:86740a56073b	1971	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
AnnaBridge	143:86740a56073b	1972	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
AnnaBridge	143:86740a56073b	1973	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
AnnaBridge	143:86740a56073b	1974	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
AnnaBridge	143:86740a56073b	1975	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
AnnaBridge	143:86740a56073b	1976	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
AnnaBridge	143:86740a56073b	1977	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
AnnaBridge	143:86740a56073b	1978	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
AnnaBridge	143:86740a56073b	1979	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	143:86740a56073b	1980	* @retval None
AnnaBridge	143:86740a56073b	1981	*/
AnnaBridge	143:86740a56073b	1982	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICFilter)
AnnaBridge	143:86740a56073b	1983	{
AnnaBridge	143:86740a56073b	1984	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	1985	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	143:86740a56073b	1986	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	143:86740a56073b	1987	}
AnnaBridge	143:86740a56073b	1988
AnnaBridge	143:86740a56073b	1989	/**
AnnaBridge	143:86740a56073b	1990	* @brief Get the input filter duration.
AnnaBridge	143:86740a56073b	1991	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
AnnaBridge	143:86740a56073b	1992	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
AnnaBridge	143:86740a56073b	1993	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
AnnaBridge	143:86740a56073b	1994	* CCMR2 IC4F LL_TIM_IC_GetFilter
AnnaBridge	143:86740a56073b	1995	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	1996	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1997	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	1998	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	1999	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	2000	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	2001	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	2002	* @arg @ref LL_TIM_IC_FILTER_FDIV1
AnnaBridge	143:86740a56073b	2003	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
AnnaBridge	143:86740a56073b	2004	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
AnnaBridge	143:86740a56073b	2005	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
AnnaBridge	143:86740a56073b	2006	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
AnnaBridge	143:86740a56073b	2007	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
AnnaBridge	143:86740a56073b	2008	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
AnnaBridge	143:86740a56073b	2009	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
AnnaBridge	143:86740a56073b	2010	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
AnnaBridge	143:86740a56073b	2011	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
AnnaBridge	143:86740a56073b	2012	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
AnnaBridge	143:86740a56073b	2013	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
AnnaBridge	143:86740a56073b	2014	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
AnnaBridge	143:86740a56073b	2015	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
AnnaBridge	143:86740a56073b	2016	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
AnnaBridge	143:86740a56073b	2017	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	143:86740a56073b	2018	*/
AnnaBridge	143:86740a56073b	2019	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef * TIMx, uint32_t Channel)
AnnaBridge	143:86740a56073b	2020	{
AnnaBridge	143:86740a56073b	2021	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	2022	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	143:86740a56073b	2023	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U );
AnnaBridge	143:86740a56073b	2024	}
AnnaBridge	143:86740a56073b	2025
AnnaBridge	143:86740a56073b	2026	/**
AnnaBridge	143:86740a56073b	2027	* @brief Set the input channel polarity.
AnnaBridge	143:86740a56073b	2028	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
AnnaBridge	143:86740a56073b	2029	* CCER CC1NP LL_TIM_IC_SetPolarity\n
AnnaBridge	143:86740a56073b	2030	* CCER CC2P LL_TIM_IC_SetPolarity\n
AnnaBridge	143:86740a56073b	2031	* CCER CC2NP LL_TIM_IC_SetPolarity\n
AnnaBridge	143:86740a56073b	2032	* CCER CC3P LL_TIM_IC_SetPolarity\n
AnnaBridge	143:86740a56073b	2033	* CCER CC3NP LL_TIM_IC_SetPolarity\n
AnnaBridge	143:86740a56073b	2034	* CCER CC4P LL_TIM_IC_SetPolarity\n
AnnaBridge	143:86740a56073b	2035	* CCER CC4NP LL_TIM_IC_SetPolarity
AnnaBridge	143:86740a56073b	2036	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2037	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	2038	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	2039	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	2040	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	2041	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	2042	* @param ICPolarity This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	2043	* @arg @ref LL_TIM_IC_POLARITY_RISING
AnnaBridge	143:86740a56073b	2044	* @arg @ref LL_TIM_IC_POLARITY_FALLING
AnnaBridge	143:86740a56073b	2045	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	143:86740a56073b	2046	* @retval None
AnnaBridge	143:86740a56073b	2047	*/
AnnaBridge	143:86740a56073b	2048	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICPolarity)
AnnaBridge	143:86740a56073b	2049	{
AnnaBridge	143:86740a56073b	2050	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	2051	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), ICPolarity << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	143:86740a56073b	2052	}
AnnaBridge	143:86740a56073b	2053
AnnaBridge	143:86740a56073b	2054	/**
AnnaBridge	143:86740a56073b	2055	* @brief Get the current input channel polarity.
AnnaBridge	143:86740a56073b	2056	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
AnnaBridge	143:86740a56073b	2057	* CCER CC1NP LL_TIM_IC_GetPolarity\n
AnnaBridge	143:86740a56073b	2058	* CCER CC2P LL_TIM_IC_GetPolarity\n
AnnaBridge	143:86740a56073b	2059	* CCER CC2NP LL_TIM_IC_GetPolarity\n
AnnaBridge	143:86740a56073b	2060	* CCER CC3P LL_TIM_IC_GetPolarity\n
AnnaBridge	143:86740a56073b	2061	* CCER CC3NP LL_TIM_IC_GetPolarity\n
AnnaBridge	143:86740a56073b	2062	* CCER CC4P LL_TIM_IC_GetPolarity\n
AnnaBridge	143:86740a56073b	2063	* CCER CC4NP LL_TIM_IC_GetPolarity
AnnaBridge	143:86740a56073b	2064	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2065	* @param Channel This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	2066	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	143:86740a56073b	2067	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	143:86740a56073b	2068	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	143:86740a56073b	2069	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	143:86740a56073b	2070	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	2071	* @arg @ref LL_TIM_IC_POLARITY_RISING
AnnaBridge	143:86740a56073b	2072	* @arg @ref LL_TIM_IC_POLARITY_FALLING
AnnaBridge	143:86740a56073b	2073	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	143:86740a56073b	2074	*/
AnnaBridge	143:86740a56073b	2075	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef * TIMx, uint32_t Channel)
AnnaBridge	143:86740a56073b	2076	{
AnnaBridge	143:86740a56073b	2077	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	143:86740a56073b	2078	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	143:86740a56073b	2079	}
AnnaBridge	143:86740a56073b	2080
AnnaBridge	143:86740a56073b	2081	/**
AnnaBridge	143:86740a56073b	2082	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
AnnaBridge	143:86740a56073b	2083	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	2084	* a timer instance provides an XOR input.
AnnaBridge	143:86740a56073b	2085	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
AnnaBridge	143:86740a56073b	2086	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2087	* @retval None
AnnaBridge	143:86740a56073b	2088	*/
AnnaBridge	143:86740a56073b	2089	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2090	{
AnnaBridge	143:86740a56073b	2091	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
AnnaBridge	143:86740a56073b	2092	}
AnnaBridge	143:86740a56073b	2093
AnnaBridge	143:86740a56073b	2094	/**
AnnaBridge	143:86740a56073b	2095	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
AnnaBridge	143:86740a56073b	2096	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	2097	* a timer instance provides an XOR input.
AnnaBridge	143:86740a56073b	2098	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
AnnaBridge	143:86740a56073b	2099	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2100	* @retval None
AnnaBridge	143:86740a56073b	2101	*/
AnnaBridge	143:86740a56073b	2102	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2103	{
AnnaBridge	143:86740a56073b	2104	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
AnnaBridge	143:86740a56073b	2105	}
AnnaBridge	143:86740a56073b	2106
AnnaBridge	143:86740a56073b	2107	/**
AnnaBridge	143:86740a56073b	2108	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
AnnaBridge	143:86740a56073b	2109	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	2110	* a timer instance provides an XOR input.
AnnaBridge	143:86740a56073b	2111	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
AnnaBridge	143:86740a56073b	2112	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2113	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	2114	*/
AnnaBridge	143:86740a56073b	2115	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2116	{
AnnaBridge	143:86740a56073b	2117	return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
AnnaBridge	143:86740a56073b	2118	}
AnnaBridge	143:86740a56073b	2119
AnnaBridge	143:86740a56073b	2120	/**
AnnaBridge	143:86740a56073b	2121	* @brief Get captured value for input channel 1.
AnnaBridge	143:86740a56073b	2122	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	2123	* input channel 1 is supported by a timer instance.
AnnaBridge	143:86740a56073b	2124	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
AnnaBridge	143:86740a56073b	2125	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2126	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	143:86740a56073b	2127	*/
AnnaBridge	143:86740a56073b	2128	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2129	{
AnnaBridge	143:86740a56073b	2130	return (uint32_t)(READ_REG(TIMx->CCR1));
AnnaBridge	143:86740a56073b	2131	}
AnnaBridge	143:86740a56073b	2132
AnnaBridge	143:86740a56073b	2133	/**
AnnaBridge	143:86740a56073b	2134	* @brief Get captured value for input channel 2.
AnnaBridge	143:86740a56073b	2135	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	2136	* input channel 2 is supported by a timer instance.
AnnaBridge	143:86740a56073b	2137	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
AnnaBridge	143:86740a56073b	2138	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2139	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	143:86740a56073b	2140	*/
AnnaBridge	143:86740a56073b	2141	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2142	{
AnnaBridge	143:86740a56073b	2143	return (uint32_t)(READ_REG(TIMx->CCR2));
AnnaBridge	143:86740a56073b	2144	}
AnnaBridge	143:86740a56073b	2145
AnnaBridge	143:86740a56073b	2146	/**
AnnaBridge	143:86740a56073b	2147	* @brief Get captured value for input channel 3.
AnnaBridge	143:86740a56073b	2148	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	2149	* input channel 3 is supported by a timer instance.
AnnaBridge	143:86740a56073b	2150	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
AnnaBridge	143:86740a56073b	2151	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2152	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	143:86740a56073b	2153	*/
AnnaBridge	143:86740a56073b	2154	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2155	{
AnnaBridge	143:86740a56073b	2156	return (uint32_t)(READ_REG(TIMx->CCR3));
AnnaBridge	143:86740a56073b	2157	}
AnnaBridge	143:86740a56073b	2158
AnnaBridge	143:86740a56073b	2159	/**
AnnaBridge	143:86740a56073b	2160	* @brief Get captured value for input channel 4.
AnnaBridge	143:86740a56073b	2161	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	2162	* input channel 4 is supported by a timer instance.
AnnaBridge	143:86740a56073b	2163	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
AnnaBridge	143:86740a56073b	2164	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2165	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	143:86740a56073b	2166	*/
AnnaBridge	143:86740a56073b	2167	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2168	{
AnnaBridge	143:86740a56073b	2169	return (uint32_t)(READ_REG(TIMx->CCR4));
AnnaBridge	143:86740a56073b	2170	}
AnnaBridge	143:86740a56073b	2171
AnnaBridge	143:86740a56073b	2172	/**
AnnaBridge	143:86740a56073b	2173	* @}
AnnaBridge	143:86740a56073b	2174	*/
AnnaBridge	143:86740a56073b	2175
AnnaBridge	143:86740a56073b	2176	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
AnnaBridge	143:86740a56073b	2177	* @{
AnnaBridge	143:86740a56073b	2178	*/
AnnaBridge	143:86740a56073b	2179	/**
AnnaBridge	143:86740a56073b	2180	* @brief Enable external clock mode 2.
AnnaBridge	143:86740a56073b	2181	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
AnnaBridge	143:86740a56073b	2182	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	143:86740a56073b	2183	* whether or not a timer instance supports external clock mode2.
AnnaBridge	143:86740a56073b	2184	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
AnnaBridge	143:86740a56073b	2185	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2186	* @retval None
AnnaBridge	143:86740a56073b	2187	*/
AnnaBridge	143:86740a56073b	2188	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2189	{
AnnaBridge	143:86740a56073b	2190	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
AnnaBridge	143:86740a56073b	2191	}
AnnaBridge	143:86740a56073b	2192
AnnaBridge	143:86740a56073b	2193	/**
AnnaBridge	143:86740a56073b	2194	* @brief Disable external clock mode 2.
AnnaBridge	143:86740a56073b	2195	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	143:86740a56073b	2196	* whether or not a timer instance supports external clock mode2.
AnnaBridge	143:86740a56073b	2197	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
AnnaBridge	143:86740a56073b	2198	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2199	* @retval None
AnnaBridge	143:86740a56073b	2200	*/
AnnaBridge	143:86740a56073b	2201	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2202	{
AnnaBridge	143:86740a56073b	2203	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
AnnaBridge	143:86740a56073b	2204	}
AnnaBridge	143:86740a56073b	2205
AnnaBridge	143:86740a56073b	2206	/**
AnnaBridge	143:86740a56073b	2207	* @brief Indicate whether external clock mode 2 is enabled.
AnnaBridge	143:86740a56073b	2208	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	143:86740a56073b	2209	* whether or not a timer instance supports external clock mode2.
AnnaBridge	143:86740a56073b	2210	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
AnnaBridge	143:86740a56073b	2211	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2212	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	2213	*/
AnnaBridge	143:86740a56073b	2214	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2215	{
AnnaBridge	143:86740a56073b	2216	return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
AnnaBridge	143:86740a56073b	2217	}
AnnaBridge	143:86740a56073b	2218
AnnaBridge	143:86740a56073b	2219	/**
AnnaBridge	143:86740a56073b	2220	* @brief Set the clock source of the counter clock.
AnnaBridge	143:86740a56073b	2221	* @note when selected clock source is external clock mode 1, the timer input
AnnaBridge	143:86740a56073b	2222	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
AnnaBridge	143:86740a56073b	2223	* function. This timer input must be configured by calling
AnnaBridge	143:86740a56073b	2224	* the @ref LL_TIM_IC_Config() function.
AnnaBridge	143:86740a56073b	2225	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
AnnaBridge	143:86740a56073b	2226	* whether or not a timer instance supports external clock mode1.
AnnaBridge	143:86740a56073b	2227	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	143:86740a56073b	2228	* whether or not a timer instance supports external clock mode2.
AnnaBridge	143:86740a56073b	2229	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
AnnaBridge	143:86740a56073b	2230	* SMCR ECE LL_TIM_SetClockSource
AnnaBridge	143:86740a56073b	2231	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2232	* @param ClockSource This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	2233	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
AnnaBridge	143:86740a56073b	2234	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
AnnaBridge	143:86740a56073b	2235	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
AnnaBridge	143:86740a56073b	2236	* @retval None
AnnaBridge	143:86740a56073b	2237	*/
AnnaBridge	143:86740a56073b	2238	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef * TIMx, uint32_t ClockSource)
AnnaBridge	143:86740a56073b	2239	{
AnnaBridge	143:86740a56073b	2240	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
AnnaBridge	143:86740a56073b	2241	}
AnnaBridge	143:86740a56073b	2242
AnnaBridge	143:86740a56073b	2243	/**
AnnaBridge	143:86740a56073b	2244	* @brief Set the encoder interface mode.
AnnaBridge	143:86740a56073b	2245	* @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
AnnaBridge	143:86740a56073b	2246	* whether or not a timer instance supports the encoder mode.
AnnaBridge	143:86740a56073b	2247	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
AnnaBridge	143:86740a56073b	2248	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2249	* @param EncoderMode This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	2250	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
AnnaBridge	143:86740a56073b	2251	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
AnnaBridge	143:86740a56073b	2252	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
AnnaBridge	143:86740a56073b	2253	* @retval None
AnnaBridge	143:86740a56073b	2254	*/
AnnaBridge	143:86740a56073b	2255	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx, uint32_t EncoderMode)
AnnaBridge	143:86740a56073b	2256	{
AnnaBridge	143:86740a56073b	2257	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
AnnaBridge	143:86740a56073b	2258	}
AnnaBridge	143:86740a56073b	2259
AnnaBridge	143:86740a56073b	2260	/**
AnnaBridge	143:86740a56073b	2261	* @}
AnnaBridge	143:86740a56073b	2262	*/
AnnaBridge	143:86740a56073b	2263
AnnaBridge	143:86740a56073b	2264	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
AnnaBridge	143:86740a56073b	2265	* @{
AnnaBridge	143:86740a56073b	2266	*/
AnnaBridge	143:86740a56073b	2267	/**
AnnaBridge	143:86740a56073b	2268	* @brief Set the trigger output (TRGO) used for timer synchronization .
AnnaBridge	143:86740a56073b	2269	* @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
AnnaBridge	143:86740a56073b	2270	* whether or not a timer instance can operate as a master timer.
AnnaBridge	143:86740a56073b	2271	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
AnnaBridge	143:86740a56073b	2272	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2273	* @param TimerSynchronization This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	2274	* @arg @ref LL_TIM_TRGO_RESET
AnnaBridge	143:86740a56073b	2275	* @arg @ref LL_TIM_TRGO_ENABLE
AnnaBridge	143:86740a56073b	2276	* @arg @ref LL_TIM_TRGO_UPDATE
AnnaBridge	143:86740a56073b	2277	* @arg @ref LL_TIM_TRGO_CC1IF
AnnaBridge	143:86740a56073b	2278	* @arg @ref LL_TIM_TRGO_OC1REF
AnnaBridge	143:86740a56073b	2279	* @arg @ref LL_TIM_TRGO_OC2REF
AnnaBridge	143:86740a56073b	2280	* @arg @ref LL_TIM_TRGO_OC3REF
AnnaBridge	143:86740a56073b	2281	* @arg @ref LL_TIM_TRGO_OC4REF
AnnaBridge	143:86740a56073b	2282	* @retval None
AnnaBridge	143:86740a56073b	2283	*/
AnnaBridge	143:86740a56073b	2284	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx, uint32_t TimerSynchronization)
AnnaBridge	143:86740a56073b	2285	{
AnnaBridge	143:86740a56073b	2286	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
AnnaBridge	143:86740a56073b	2287	}
AnnaBridge	143:86740a56073b	2288
AnnaBridge	143:86740a56073b	2289
AnnaBridge	143:86740a56073b	2290	/**
AnnaBridge	143:86740a56073b	2291	* @brief Set the synchronization mode of a slave timer.
AnnaBridge	143:86740a56073b	2292	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	2293	* a timer instance can operate as a slave timer.
AnnaBridge	143:86740a56073b	2294	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
AnnaBridge	143:86740a56073b	2295	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2296	* @param SlaveMode This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	2297	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
AnnaBridge	143:86740a56073b	2298	* @arg @ref LL_TIM_SLAVEMODE_RESET
AnnaBridge	143:86740a56073b	2299	* @arg @ref LL_TIM_SLAVEMODE_GATED
AnnaBridge	143:86740a56073b	2300	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
AnnaBridge	143:86740a56073b	2301	* @retval None
AnnaBridge	143:86740a56073b	2302	*/
AnnaBridge	143:86740a56073b	2303	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx, uint32_t SlaveMode)
AnnaBridge	143:86740a56073b	2304	{
AnnaBridge	143:86740a56073b	2305	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
AnnaBridge	143:86740a56073b	2306	}
AnnaBridge	143:86740a56073b	2307
AnnaBridge	143:86740a56073b	2308	/**
AnnaBridge	143:86740a56073b	2309	* @brief Set the selects the trigger input to be used to synchronize the counter.
AnnaBridge	143:86740a56073b	2310	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	2311	* a timer instance can operate as a slave timer.
AnnaBridge	143:86740a56073b	2312	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
AnnaBridge	143:86740a56073b	2313	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2314	* @param TriggerInput This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	2315	* @arg @ref LL_TIM_TS_ITR0
AnnaBridge	143:86740a56073b	2316	* @arg @ref LL_TIM_TS_ITR1
AnnaBridge	143:86740a56073b	2317	* @arg @ref LL_TIM_TS_ITR2
AnnaBridge	143:86740a56073b	2318	* @arg @ref LL_TIM_TS_ITR3
AnnaBridge	143:86740a56073b	2319	* @arg @ref LL_TIM_TS_TI1F_ED
AnnaBridge	143:86740a56073b	2320	* @arg @ref LL_TIM_TS_TI1FP1
AnnaBridge	143:86740a56073b	2321	* @arg @ref LL_TIM_TS_TI2FP2
AnnaBridge	143:86740a56073b	2322	* @arg @ref LL_TIM_TS_ETRF
AnnaBridge	143:86740a56073b	2323	* @retval None
AnnaBridge	143:86740a56073b	2324	*/
AnnaBridge	143:86740a56073b	2325	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx, uint32_t TriggerInput)
AnnaBridge	143:86740a56073b	2326	{
AnnaBridge	143:86740a56073b	2327	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
AnnaBridge	143:86740a56073b	2328	}
AnnaBridge	143:86740a56073b	2329
AnnaBridge	143:86740a56073b	2330	/**
AnnaBridge	143:86740a56073b	2331	* @brief Enable the Master/Slave mode.
AnnaBridge	143:86740a56073b	2332	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	2333	* a timer instance can operate as a slave timer.
AnnaBridge	143:86740a56073b	2334	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
AnnaBridge	143:86740a56073b	2335	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2336	* @retval None
AnnaBridge	143:86740a56073b	2337	*/
AnnaBridge	143:86740a56073b	2338	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2339	{
AnnaBridge	143:86740a56073b	2340	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
AnnaBridge	143:86740a56073b	2341	}
AnnaBridge	143:86740a56073b	2342
AnnaBridge	143:86740a56073b	2343	/**
AnnaBridge	143:86740a56073b	2344	* @brief Disable the Master/Slave mode.
AnnaBridge	143:86740a56073b	2345	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	2346	* a timer instance can operate as a slave timer.
AnnaBridge	143:86740a56073b	2347	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
AnnaBridge	143:86740a56073b	2348	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2349	* @retval None
AnnaBridge	143:86740a56073b	2350	*/
AnnaBridge	143:86740a56073b	2351	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2352	{
AnnaBridge	143:86740a56073b	2353	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
AnnaBridge	143:86740a56073b	2354	}
AnnaBridge	143:86740a56073b	2355
AnnaBridge	143:86740a56073b	2356	/**
AnnaBridge	143:86740a56073b	2357	* @brief Indicates whether the Master/Slave mode is enabled.
AnnaBridge	143:86740a56073b	2358	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	2359	* a timer instance can operate as a slave timer.
AnnaBridge	143:86740a56073b	2360	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
AnnaBridge	143:86740a56073b	2361	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2362	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	2363	*/
AnnaBridge	143:86740a56073b	2364	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2365	{
AnnaBridge	143:86740a56073b	2366	return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
AnnaBridge	143:86740a56073b	2367	}
AnnaBridge	143:86740a56073b	2368
AnnaBridge	143:86740a56073b	2369	/**
AnnaBridge	143:86740a56073b	2370	* @brief Configure the external trigger (ETR) input.
AnnaBridge	143:86740a56073b	2371	* @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	2372	* a timer instance provides an external trigger input.
AnnaBridge	143:86740a56073b	2373	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
AnnaBridge	143:86740a56073b	2374	* SMCR ETPS LL_TIM_ConfigETR\n
AnnaBridge	143:86740a56073b	2375	* SMCR ETF LL_TIM_ConfigETR
AnnaBridge	143:86740a56073b	2376	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2377	* @param ETRPolarity This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	2378	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
AnnaBridge	143:86740a56073b	2379	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
AnnaBridge	143:86740a56073b	2380	* @param ETRPrescaler This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	2381	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
AnnaBridge	143:86740a56073b	2382	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
AnnaBridge	143:86740a56073b	2383	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
AnnaBridge	143:86740a56073b	2384	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
AnnaBridge	143:86740a56073b	2385	* @param ETRFilter This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	2386	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
AnnaBridge	143:86740a56073b	2387	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
AnnaBridge	143:86740a56073b	2388	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
AnnaBridge	143:86740a56073b	2389	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
AnnaBridge	143:86740a56073b	2390	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
AnnaBridge	143:86740a56073b	2391	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
AnnaBridge	143:86740a56073b	2392	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
AnnaBridge	143:86740a56073b	2393	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
AnnaBridge	143:86740a56073b	2394	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
AnnaBridge	143:86740a56073b	2395	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
AnnaBridge	143:86740a56073b	2396	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
AnnaBridge	143:86740a56073b	2397	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
AnnaBridge	143:86740a56073b	2398	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
AnnaBridge	143:86740a56073b	2399	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
AnnaBridge	143:86740a56073b	2400	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
AnnaBridge	143:86740a56073b	2401	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
AnnaBridge	143:86740a56073b	2402	* @retval None
AnnaBridge	143:86740a56073b	2403	*/
AnnaBridge	143:86740a56073b	2404	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef * TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
AnnaBridge	143:86740a56073b	2405	{
AnnaBridge	143:86740a56073b	2406	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
AnnaBridge	143:86740a56073b	2407	}
AnnaBridge	143:86740a56073b	2408
AnnaBridge	143:86740a56073b	2409
AnnaBridge	143:86740a56073b	2410	/**
AnnaBridge	143:86740a56073b	2411	* @}
AnnaBridge	143:86740a56073b	2412	*/
AnnaBridge	143:86740a56073b	2413
AnnaBridge	143:86740a56073b	2414
AnnaBridge	143:86740a56073b	2415	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
AnnaBridge	143:86740a56073b	2416	* @{
AnnaBridge	143:86740a56073b	2417	*/
AnnaBridge	143:86740a56073b	2418	/**
AnnaBridge	143:86740a56073b	2419	* @brief Configures the timer DMA burst feature.
AnnaBridge	143:86740a56073b	2420	* @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
AnnaBridge	143:86740a56073b	2421	* not a timer instance supports the DMA burst mode.
AnnaBridge	143:86740a56073b	2422	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
AnnaBridge	143:86740a56073b	2423	* DCR DBA LL_TIM_ConfigDMABurst
AnnaBridge	143:86740a56073b	2424	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2425	* @param DMABurstBaseAddress This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	2426	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
AnnaBridge	143:86740a56073b	2427	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
AnnaBridge	143:86740a56073b	2428	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
AnnaBridge	143:86740a56073b	2429	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
AnnaBridge	143:86740a56073b	2430	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
AnnaBridge	143:86740a56073b	2431	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
AnnaBridge	143:86740a56073b	2432	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
AnnaBridge	143:86740a56073b	2433	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
AnnaBridge	143:86740a56073b	2434	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
AnnaBridge	143:86740a56073b	2435	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
AnnaBridge	143:86740a56073b	2436	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
AnnaBridge	143:86740a56073b	2437	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
AnnaBridge	143:86740a56073b	2438	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
AnnaBridge	143:86740a56073b	2439	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
AnnaBridge	143:86740a56073b	2440	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
AnnaBridge	143:86740a56073b	2441	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
AnnaBridge	143:86740a56073b	2442	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
AnnaBridge	143:86740a56073b	2443	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
AnnaBridge	143:86740a56073b	2444	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
AnnaBridge	143:86740a56073b	2445	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
AnnaBridge	143:86740a56073b	2446	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
AnnaBridge	143:86740a56073b	2447	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
AnnaBridge	143:86740a56073b	2448	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR2
AnnaBridge	143:86740a56073b	2449	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR3
AnnaBridge	143:86740a56073b	2450	* @param DMABurstLength This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	2451	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
AnnaBridge	143:86740a56073b	2452	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
AnnaBridge	143:86740a56073b	2453	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
AnnaBridge	143:86740a56073b	2454	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
AnnaBridge	143:86740a56073b	2455	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
AnnaBridge	143:86740a56073b	2456	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
AnnaBridge	143:86740a56073b	2457	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
AnnaBridge	143:86740a56073b	2458	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
AnnaBridge	143:86740a56073b	2459	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
AnnaBridge	143:86740a56073b	2460	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
AnnaBridge	143:86740a56073b	2461	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
AnnaBridge	143:86740a56073b	2462	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
AnnaBridge	143:86740a56073b	2463	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
AnnaBridge	143:86740a56073b	2464	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
AnnaBridge	143:86740a56073b	2465	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
AnnaBridge	143:86740a56073b	2466	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
AnnaBridge	143:86740a56073b	2467	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
AnnaBridge	143:86740a56073b	2468	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
AnnaBridge	143:86740a56073b	2469	* @retval None
AnnaBridge	143:86740a56073b	2470	*/
AnnaBridge	143:86740a56073b	2471	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
AnnaBridge	143:86740a56073b	2472	{
AnnaBridge	143:86740a56073b	2473	MODIFY_REG(TIMx->DCR, TIM_DCR_DBL \| TIM_DCR_DBA, DMABurstBaseAddress \| DMABurstLength);
AnnaBridge	143:86740a56073b	2474	}
AnnaBridge	143:86740a56073b	2475
AnnaBridge	143:86740a56073b	2476	/**
AnnaBridge	143:86740a56073b	2477	* @}
AnnaBridge	143:86740a56073b	2478	*/
AnnaBridge	143:86740a56073b	2479
AnnaBridge	143:86740a56073b	2480	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
AnnaBridge	143:86740a56073b	2481	* @{
AnnaBridge	143:86740a56073b	2482	*/
AnnaBridge	143:86740a56073b	2483	/**
AnnaBridge	143:86740a56073b	2484	* @brief Remap TIM inputs (input channel, internal/external triggers).
AnnaBridge	143:86740a56073b	2485	* @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	143:86740a56073b	2486	* a some timer inputs can be remapped.
AnnaBridge	143:86740a56073b	2487	* @rmtoll TIM2_OR ETR_RMP LL_TIM_SetRemap\n
AnnaBridge	143:86740a56073b	2488	* TIM2_OR TI4_RMP LL_TIM_SetRemap\n
AnnaBridge	143:86740a56073b	2489	* TIM21_OR ETR_RMP LL_TIM_SetRemap\n
AnnaBridge	143:86740a56073b	2490	* TIM21_OR TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	143:86740a56073b	2491	* TIM21_OR TI2_RMP LL_TIM_SetRemap\n
AnnaBridge	143:86740a56073b	2492	* TIM22_OR ETR_RMP LL_TIM_SetRemap\n
AnnaBridge	143:86740a56073b	2493	* TIM22_OR TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	143:86740a56073b	2494	* TIM3_OR ETR_RMP LL_TIM_SetRemap\n
AnnaBridge	143:86740a56073b	2495	* TIM3_OR TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	143:86740a56073b	2496	* TIM3_OR TI2_RMP LL_TIM_SetRemap\n
AnnaBridge	143:86740a56073b	2497	* TIM3_OR TI4_RMP LL_TIM_SetRemap
AnnaBridge	143:86740a56073b	2498	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2499	* @param Remap Remap params depends on the TIMx. Description available only
AnnaBridge	143:86740a56073b	2500	* in CHM version of the User Manual (not in .pdf).
AnnaBridge	143:86740a56073b	2501	* Otherwise see Reference Manual description of OR registers.
AnnaBridge	143:86740a56073b	2502	*
AnnaBridge	143:86740a56073b	2503	* Below description summarizes "Timer Instance" and "Remap" param combinations:
AnnaBridge	143:86740a56073b	2504	*
AnnaBridge	143:86740a56073b	2505	* TIM2: any combination of ETR_RMP, TI4_RMP where
AnnaBridge	143:86740a56073b	2506	*
AnnaBridge	143:86740a56073b	2507	* . . ETR_RMP can be one of the following values
AnnaBridge	143:86740a56073b	2508	* @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
AnnaBridge	143:86740a56073b	2509	* @arg @ref LL_TIM_TIM2_ETR_RMP_HSI (*)
AnnaBridge	143:86740a56073b	2510	* @arg @ref LL_TIM_TIM2_ETR_RMP_HSI48 (*)
AnnaBridge	143:86740a56073b	2511	* @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
AnnaBridge	143:86740a56073b	2512	* @arg @ref LL_TIM_TIM2_ETR_RMP_COMP2
AnnaBridge	143:86740a56073b	2513	* @arg @ref LL_TIM_TIM2_ETR_RMP_COMP1
AnnaBridge	143:86740a56073b	2514	*
AnnaBridge	143:86740a56073b	2515	* . . TI4_RMP can be one of the following values
AnnaBridge	143:86740a56073b	2516	* @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
AnnaBridge	143:86740a56073b	2517	* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
AnnaBridge	143:86740a56073b	2518	* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
AnnaBridge	143:86740a56073b	2519	*
AnnaBridge	143:86740a56073b	2520	* TIM3: any combination of the following values (**)
AnnaBridge	143:86740a56073b	2521	*
AnnaBridge	143:86740a56073b	2522	* . . ETR_RMP can be one of the following values (**)
AnnaBridge	143:86740a56073b	2523	* @arg @ref LL_TIM_TIM3_ETR_RMP_GPIO
AnnaBridge	143:86740a56073b	2524	* @arg @ref LL_TIM_TIM3_ETR_RMP_HSI48DIV6
AnnaBridge	143:86740a56073b	2525	*
AnnaBridge	143:86740a56073b	2526	* . . TI_RMP_TI1 can be one of the following values (**)
AnnaBridge	143:86740a56073b	2527	* @arg @ref LL_TIM_TIM3_TI_RMP_TI1_USB_SOF
AnnaBridge	143:86740a56073b	2528	* @arg @ref LL_TIM_TIM3_TI_RMP_TI1_GPIO
AnnaBridge	143:86740a56073b	2529	*
AnnaBridge	143:86740a56073b	2530	* . . TI_RMP_TI2 can be one of the following values (**)
AnnaBridge	143:86740a56073b	2531	* @arg @ref LL_TIM_TIM3_TI_RMP_TI2_GPIO_DEF
AnnaBridge	143:86740a56073b	2532	* @arg @ref LL_TIM_TIM3_TI_RMP_TI2_GPIOB5_AF4
AnnaBridge	143:86740a56073b	2533	*
AnnaBridge	143:86740a56073b	2534	* . . TI_RMP_TI4 can be one of the following values (**)
AnnaBridge	143:86740a56073b	2535	* @arg @ref LL_TIM_TIM3_TI_RMP_TI4_GPIO_DEF
AnnaBridge	143:86740a56073b	2536	* @arg @ref LL_TIM_TIM3_TI_RMP_TI4_GPIOC9_AF2
AnnaBridge	143:86740a56073b	2537	*
AnnaBridge	143:86740a56073b	2538	* TIM21: any combination of ETR_RMP, TI1_RMP, TI2_RMP where
AnnaBridge	143:86740a56073b	2539	*
AnnaBridge	143:86740a56073b	2540	* . . ETR_RMP can be one of the following values
AnnaBridge	143:86740a56073b	2541	* @arg @ref LL_TIM_TIM21_ETR_RMP_GPIO
AnnaBridge	143:86740a56073b	2542	* @arg @ref LL_TIM_TIM21_ETR_RMP_COMP2
AnnaBridge	143:86740a56073b	2543	* @arg @ref LL_TIM_TIM21_ETR_RMP_COMP1
AnnaBridge	143:86740a56073b	2544	* @arg @ref LL_TIM_TIM21_ETR_RMP_LSE
AnnaBridge	143:86740a56073b	2545	*
AnnaBridge	143:86740a56073b	2546	* . . TI1_RMP can be one of the following values
AnnaBridge	143:86740a56073b	2547	* @arg @ref LL_TIM_TIM21_TI1_RMP_GPIO
AnnaBridge	143:86740a56073b	2548	* @arg @ref LL_TIM_TIM21_TI1_RMP_RTC_WK
AnnaBridge	143:86740a56073b	2549	* @arg @ref LL_TIM_TIM21_TI1_RMP_HSE_RTC
AnnaBridge	143:86740a56073b	2550	* @arg @ref LL_TIM_TIM21_TI1_RMP_MSI
AnnaBridge	143:86740a56073b	2551	* @arg @ref LL_TIM_TIM21_TI1_RMP_LSE
AnnaBridge	143:86740a56073b	2552	* @arg @ref LL_TIM_TIM21_TI1_RMP_LSI
AnnaBridge	143:86740a56073b	2553	* @arg @ref LL_TIM_TIM21_TI1_RMP_COMP1
AnnaBridge	143:86740a56073b	2554	* @arg @ref LL_TIM_TIM21_TI1_RMP_MCO
AnnaBridge	143:86740a56073b	2555	*
AnnaBridge	143:86740a56073b	2556	* . . TI2_RMP can be one of the following values
AnnaBridge	143:86740a56073b	2557	* @arg @ref LL_TIM_TIM21_TI2_RMP_GPIO
AnnaBridge	143:86740a56073b	2558	* @arg @ref LL_TIM_TIM21_TI2_RMP_COMP2
AnnaBridge	143:86740a56073b	2559	*
AnnaBridge	143:86740a56073b	2560	* TIM22: any combination of ETR_RMP, TI1_RMP where (**)
AnnaBridge	143:86740a56073b	2561	*
AnnaBridge	143:86740a56073b	2562	* . . ETR_RMP can be one of the following values (**)
AnnaBridge	143:86740a56073b	2563	* @arg @ref LL_TIM_TIM22_ETR_RMP_GPIO
AnnaBridge	143:86740a56073b	2564	* @arg @ref LL_TIM_TIM22_ETR_RMP_COMP2
AnnaBridge	143:86740a56073b	2565	* @arg @ref LL_TIM_TIM22_ETR_RMP_COMP1
AnnaBridge	143:86740a56073b	2566	* @arg @ref LL_TIM_TIM22_ETR_RMP_LSE
AnnaBridge	143:86740a56073b	2567	*
AnnaBridge	143:86740a56073b	2568	* . . TI1_RMP can be one of the following values (**)
AnnaBridge	143:86740a56073b	2569	* @arg @ref LL_TIM_TIM22_TI1_RMP_GPIO1
AnnaBridge	143:86740a56073b	2570	* @arg @ref LL_TIM_TIM22_TI1_RMP_COMP2
AnnaBridge	143:86740a56073b	2571	* @arg @ref LL_TIM_TIM22_TI1_RMP_COMP1
AnnaBridge	143:86740a56073b	2572	* @arg @ref LL_TIM_TIM22_TI1_RMP_GPIO2
AnnaBridge	143:86740a56073b	2573	*
AnnaBridge	143:86740a56073b	2574	* (*) Value not defined in all devices. \n
AnnaBridge	143:86740a56073b	2575	* (*) Register not available in all devices.
AnnaBridge	143:86740a56073b	2576	* @retval None
AnnaBridge	143:86740a56073b	2577	*/
AnnaBridge	143:86740a56073b	2578	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef * TIMx, uint32_t Remap)
AnnaBridge	143:86740a56073b	2579	{
AnnaBridge	143:86740a56073b	2580	MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
AnnaBridge	143:86740a56073b	2581	}
AnnaBridge	143:86740a56073b	2582
AnnaBridge	143:86740a56073b	2583	/**
AnnaBridge	143:86740a56073b	2584	* @}
AnnaBridge	143:86740a56073b	2585	*/
AnnaBridge	143:86740a56073b	2586
AnnaBridge	143:86740a56073b	2587	/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
AnnaBridge	143:86740a56073b	2588	* @{
AnnaBridge	143:86740a56073b	2589	*/
AnnaBridge	143:86740a56073b	2590	/**
AnnaBridge	143:86740a56073b	2591	* @brief Set the OCREF clear source
AnnaBridge	143:86740a56073b	2592	* @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
AnnaBridge	143:86740a56073b	2593	* @note This function can only be used in Output compare and PWM modes.
AnnaBridge	143:86740a56073b	2594	* @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
AnnaBridge	143:86740a56073b	2595	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2596	* @param OCRefClearInputSource This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	2597	* @arg @ref LL_TIM_OCREF_CLR_INT_NC
AnnaBridge	143:86740a56073b	2598	* @arg @ref LL_TIM_OCREF_CLR_INT_ETR
AnnaBridge	143:86740a56073b	2599	* @retval None
AnnaBridge	143:86740a56073b	2600	*/
AnnaBridge	143:86740a56073b	2601
AnnaBridge	143:86740a56073b	2602	__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx, uint32_t OCRefClearInputSource)
AnnaBridge	143:86740a56073b	2603	{
AnnaBridge	143:86740a56073b	2604	MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
AnnaBridge	143:86740a56073b	2605	}
AnnaBridge	143:86740a56073b	2606	/**
AnnaBridge	143:86740a56073b	2607	* @}
AnnaBridge	143:86740a56073b	2608	*/
AnnaBridge	143:86740a56073b	2609
AnnaBridge	143:86740a56073b	2610	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
AnnaBridge	143:86740a56073b	2611	* @{
AnnaBridge	143:86740a56073b	2612	*/
AnnaBridge	143:86740a56073b	2613	/**
AnnaBridge	143:86740a56073b	2614	* @brief Clear the update interrupt flag (UIF).
AnnaBridge	143:86740a56073b	2615	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
AnnaBridge	143:86740a56073b	2616	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2617	* @retval None
AnnaBridge	143:86740a56073b	2618	*/
AnnaBridge	143:86740a56073b	2619	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2620	{
AnnaBridge	143:86740a56073b	2621	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
AnnaBridge	143:86740a56073b	2622	}
AnnaBridge	143:86740a56073b	2623
AnnaBridge	143:86740a56073b	2624	/**
AnnaBridge	143:86740a56073b	2625	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
AnnaBridge	143:86740a56073b	2626	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
AnnaBridge	143:86740a56073b	2627	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2628	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	2629	*/
AnnaBridge	143:86740a56073b	2630	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2631	{
AnnaBridge	143:86740a56073b	2632	return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
AnnaBridge	143:86740a56073b	2633	}
AnnaBridge	143:86740a56073b	2634
AnnaBridge	143:86740a56073b	2635	/**
AnnaBridge	143:86740a56073b	2636	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
AnnaBridge	143:86740a56073b	2637	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
AnnaBridge	143:86740a56073b	2638	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2639	* @retval None
AnnaBridge	143:86740a56073b	2640	*/
AnnaBridge	143:86740a56073b	2641	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2642	{
AnnaBridge	143:86740a56073b	2643	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
AnnaBridge	143:86740a56073b	2644	}
AnnaBridge	143:86740a56073b	2645
AnnaBridge	143:86740a56073b	2646	/**
AnnaBridge	143:86740a56073b	2647	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
AnnaBridge	143:86740a56073b	2648	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
AnnaBridge	143:86740a56073b	2649	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2650	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	2651	*/
AnnaBridge	143:86740a56073b	2652	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2653	{
AnnaBridge	143:86740a56073b	2654	return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
AnnaBridge	143:86740a56073b	2655	}
AnnaBridge	143:86740a56073b	2656
AnnaBridge	143:86740a56073b	2657	/**
AnnaBridge	143:86740a56073b	2658	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
AnnaBridge	143:86740a56073b	2659	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
AnnaBridge	143:86740a56073b	2660	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2661	* @retval None
AnnaBridge	143:86740a56073b	2662	*/
AnnaBridge	143:86740a56073b	2663	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2664	{
AnnaBridge	143:86740a56073b	2665	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
AnnaBridge	143:86740a56073b	2666	}
AnnaBridge	143:86740a56073b	2667
AnnaBridge	143:86740a56073b	2668	/**
AnnaBridge	143:86740a56073b	2669	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
AnnaBridge	143:86740a56073b	2670	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
AnnaBridge	143:86740a56073b	2671	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2672	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	2673	*/
AnnaBridge	143:86740a56073b	2674	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2675	{
AnnaBridge	143:86740a56073b	2676	return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
AnnaBridge	143:86740a56073b	2677	}
AnnaBridge	143:86740a56073b	2678
AnnaBridge	143:86740a56073b	2679	/**
AnnaBridge	143:86740a56073b	2680	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
AnnaBridge	143:86740a56073b	2681	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
AnnaBridge	143:86740a56073b	2682	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2683	* @retval None
AnnaBridge	143:86740a56073b	2684	*/
AnnaBridge	143:86740a56073b	2685	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2686	{
AnnaBridge	143:86740a56073b	2687	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
AnnaBridge	143:86740a56073b	2688	}
AnnaBridge	143:86740a56073b	2689
AnnaBridge	143:86740a56073b	2690	/**
AnnaBridge	143:86740a56073b	2691	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
AnnaBridge	143:86740a56073b	2692	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
AnnaBridge	143:86740a56073b	2693	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2694	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	2695	*/
AnnaBridge	143:86740a56073b	2696	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2697	{
AnnaBridge	143:86740a56073b	2698	return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
AnnaBridge	143:86740a56073b	2699	}
AnnaBridge	143:86740a56073b	2700
AnnaBridge	143:86740a56073b	2701	/**
AnnaBridge	143:86740a56073b	2702	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
AnnaBridge	143:86740a56073b	2703	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
AnnaBridge	143:86740a56073b	2704	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2705	* @retval None
AnnaBridge	143:86740a56073b	2706	*/
AnnaBridge	143:86740a56073b	2707	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2708	{
AnnaBridge	143:86740a56073b	2709	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
AnnaBridge	143:86740a56073b	2710	}
AnnaBridge	143:86740a56073b	2711
AnnaBridge	143:86740a56073b	2712	/**
AnnaBridge	143:86740a56073b	2713	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
AnnaBridge	143:86740a56073b	2714	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
AnnaBridge	143:86740a56073b	2715	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2716	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	2717	*/
AnnaBridge	143:86740a56073b	2718	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2719	{
AnnaBridge	143:86740a56073b	2720	return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
AnnaBridge	143:86740a56073b	2721	}
AnnaBridge	143:86740a56073b	2722
AnnaBridge	143:86740a56073b	2723
AnnaBridge	143:86740a56073b	2724
AnnaBridge	143:86740a56073b	2725
AnnaBridge	143:86740a56073b	2726	/**
AnnaBridge	143:86740a56073b	2727	* @brief Clear the trigger interrupt flag (TIF).
AnnaBridge	143:86740a56073b	2728	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
AnnaBridge	143:86740a56073b	2729	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2730	* @retval None
AnnaBridge	143:86740a56073b	2731	*/
AnnaBridge	143:86740a56073b	2732	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2733	{
AnnaBridge	143:86740a56073b	2734	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
AnnaBridge	143:86740a56073b	2735	}
AnnaBridge	143:86740a56073b	2736
AnnaBridge	143:86740a56073b	2737	/**
AnnaBridge	143:86740a56073b	2738	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
AnnaBridge	143:86740a56073b	2739	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
AnnaBridge	143:86740a56073b	2740	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2741	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	2742	*/
AnnaBridge	143:86740a56073b	2743	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2744	{
AnnaBridge	143:86740a56073b	2745	return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
AnnaBridge	143:86740a56073b	2746	}
AnnaBridge	143:86740a56073b	2747
AnnaBridge	143:86740a56073b	2748
AnnaBridge	143:86740a56073b	2749
AnnaBridge	143:86740a56073b	2750	/**
AnnaBridge	143:86740a56073b	2751	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
AnnaBridge	143:86740a56073b	2752	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
AnnaBridge	143:86740a56073b	2753	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2754	* @retval None
AnnaBridge	143:86740a56073b	2755	*/
AnnaBridge	143:86740a56073b	2756	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2757	{
AnnaBridge	143:86740a56073b	2758	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
AnnaBridge	143:86740a56073b	2759	}
AnnaBridge	143:86740a56073b	2760
AnnaBridge	143:86740a56073b	2761	/**
AnnaBridge	143:86740a56073b	2762	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
AnnaBridge	143:86740a56073b	2763	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
AnnaBridge	143:86740a56073b	2764	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2765	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	2766	*/
AnnaBridge	143:86740a56073b	2767	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2768	{
AnnaBridge	143:86740a56073b	2769	return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
AnnaBridge	143:86740a56073b	2770	}
AnnaBridge	143:86740a56073b	2771
AnnaBridge	143:86740a56073b	2772	/**
AnnaBridge	143:86740a56073b	2773	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
AnnaBridge	143:86740a56073b	2774	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
AnnaBridge	143:86740a56073b	2775	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2776	* @retval None
AnnaBridge	143:86740a56073b	2777	*/
AnnaBridge	143:86740a56073b	2778	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2779	{
AnnaBridge	143:86740a56073b	2780	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
AnnaBridge	143:86740a56073b	2781	}
AnnaBridge	143:86740a56073b	2782
AnnaBridge	143:86740a56073b	2783	/**
AnnaBridge	143:86740a56073b	2784	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
AnnaBridge	143:86740a56073b	2785	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
AnnaBridge	143:86740a56073b	2786	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2787	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	2788	*/
AnnaBridge	143:86740a56073b	2789	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2790	{
AnnaBridge	143:86740a56073b	2791	return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
AnnaBridge	143:86740a56073b	2792	}
AnnaBridge	143:86740a56073b	2793
AnnaBridge	143:86740a56073b	2794	/**
AnnaBridge	143:86740a56073b	2795	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
AnnaBridge	143:86740a56073b	2796	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
AnnaBridge	143:86740a56073b	2797	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2798	* @retval None
AnnaBridge	143:86740a56073b	2799	*/
AnnaBridge	143:86740a56073b	2800	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2801	{
AnnaBridge	143:86740a56073b	2802	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
AnnaBridge	143:86740a56073b	2803	}
AnnaBridge	143:86740a56073b	2804
AnnaBridge	143:86740a56073b	2805	/**
AnnaBridge	143:86740a56073b	2806	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
AnnaBridge	143:86740a56073b	2807	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
AnnaBridge	143:86740a56073b	2808	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2809	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	2810	*/
AnnaBridge	143:86740a56073b	2811	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2812	{
AnnaBridge	143:86740a56073b	2813	return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
AnnaBridge	143:86740a56073b	2814	}
AnnaBridge	143:86740a56073b	2815
AnnaBridge	143:86740a56073b	2816	/**
AnnaBridge	143:86740a56073b	2817	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
AnnaBridge	143:86740a56073b	2818	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
AnnaBridge	143:86740a56073b	2819	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2820	* @retval None
AnnaBridge	143:86740a56073b	2821	*/
AnnaBridge	143:86740a56073b	2822	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2823	{
AnnaBridge	143:86740a56073b	2824	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
AnnaBridge	143:86740a56073b	2825	}
AnnaBridge	143:86740a56073b	2826
AnnaBridge	143:86740a56073b	2827	/**
AnnaBridge	143:86740a56073b	2828	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
AnnaBridge	143:86740a56073b	2829	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
AnnaBridge	143:86740a56073b	2830	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2831	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	2832	*/
AnnaBridge	143:86740a56073b	2833	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2834	{
AnnaBridge	143:86740a56073b	2835	return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
AnnaBridge	143:86740a56073b	2836	}
AnnaBridge	143:86740a56073b	2837
AnnaBridge	143:86740a56073b	2838
AnnaBridge	143:86740a56073b	2839	/**
AnnaBridge	143:86740a56073b	2840	* @}
AnnaBridge	143:86740a56073b	2841	*/
AnnaBridge	143:86740a56073b	2842
AnnaBridge	143:86740a56073b	2843	/** @defgroup TIM_LL_EF_IT_Management IT-Management
AnnaBridge	143:86740a56073b	2844	* @{
AnnaBridge	143:86740a56073b	2845	*/
AnnaBridge	143:86740a56073b	2846	/**
AnnaBridge	143:86740a56073b	2847	* @brief Enable update interrupt (UIE).
AnnaBridge	143:86740a56073b	2848	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
AnnaBridge	143:86740a56073b	2849	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2850	* @retval None
AnnaBridge	143:86740a56073b	2851	*/
AnnaBridge	143:86740a56073b	2852	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2853	{
AnnaBridge	143:86740a56073b	2854	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
AnnaBridge	143:86740a56073b	2855	}
AnnaBridge	143:86740a56073b	2856
AnnaBridge	143:86740a56073b	2857	/**
AnnaBridge	143:86740a56073b	2858	* @brief Disable update interrupt (UIE).
AnnaBridge	143:86740a56073b	2859	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
AnnaBridge	143:86740a56073b	2860	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2861	* @retval None
AnnaBridge	143:86740a56073b	2862	*/
AnnaBridge	143:86740a56073b	2863	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2864	{
AnnaBridge	143:86740a56073b	2865	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
AnnaBridge	143:86740a56073b	2866	}
AnnaBridge	143:86740a56073b	2867
AnnaBridge	143:86740a56073b	2868	/**
AnnaBridge	143:86740a56073b	2869	* @brief Indicates whether the update interrupt (UIE) is enabled.
AnnaBridge	143:86740a56073b	2870	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
AnnaBridge	143:86740a56073b	2871	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2872	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	2873	*/
AnnaBridge	143:86740a56073b	2874	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2875	{
AnnaBridge	143:86740a56073b	2876	return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
AnnaBridge	143:86740a56073b	2877	}
AnnaBridge	143:86740a56073b	2878
AnnaBridge	143:86740a56073b	2879	/**
AnnaBridge	143:86740a56073b	2880	* @brief Enable capture/compare 1 interrupt (CC1IE).
AnnaBridge	143:86740a56073b	2881	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
AnnaBridge	143:86740a56073b	2882	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2883	* @retval None
AnnaBridge	143:86740a56073b	2884	*/
AnnaBridge	143:86740a56073b	2885	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2886	{
AnnaBridge	143:86740a56073b	2887	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
AnnaBridge	143:86740a56073b	2888	}
AnnaBridge	143:86740a56073b	2889
AnnaBridge	143:86740a56073b	2890	/**
AnnaBridge	143:86740a56073b	2891	* @brief Disable capture/compare 1 interrupt (CC1IE).
AnnaBridge	143:86740a56073b	2892	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
AnnaBridge	143:86740a56073b	2893	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2894	* @retval None
AnnaBridge	143:86740a56073b	2895	*/
AnnaBridge	143:86740a56073b	2896	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2897	{
AnnaBridge	143:86740a56073b	2898	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
AnnaBridge	143:86740a56073b	2899	}
AnnaBridge	143:86740a56073b	2900
AnnaBridge	143:86740a56073b	2901	/**
AnnaBridge	143:86740a56073b	2902	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
AnnaBridge	143:86740a56073b	2903	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
AnnaBridge	143:86740a56073b	2904	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2905	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	2906	*/
AnnaBridge	143:86740a56073b	2907	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2908	{
AnnaBridge	143:86740a56073b	2909	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
AnnaBridge	143:86740a56073b	2910	}
AnnaBridge	143:86740a56073b	2911
AnnaBridge	143:86740a56073b	2912	/**
AnnaBridge	143:86740a56073b	2913	* @brief Enable capture/compare 2 interrupt (CC2IE).
AnnaBridge	143:86740a56073b	2914	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
AnnaBridge	143:86740a56073b	2915	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2916	* @retval None
AnnaBridge	143:86740a56073b	2917	*/
AnnaBridge	143:86740a56073b	2918	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2919	{
AnnaBridge	143:86740a56073b	2920	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
AnnaBridge	143:86740a56073b	2921	}
AnnaBridge	143:86740a56073b	2922
AnnaBridge	143:86740a56073b	2923	/**
AnnaBridge	143:86740a56073b	2924	* @brief Disable capture/compare 2 interrupt (CC2IE).
AnnaBridge	143:86740a56073b	2925	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
AnnaBridge	143:86740a56073b	2926	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2927	* @retval None
AnnaBridge	143:86740a56073b	2928	*/
AnnaBridge	143:86740a56073b	2929	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2930	{
AnnaBridge	143:86740a56073b	2931	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
AnnaBridge	143:86740a56073b	2932	}
AnnaBridge	143:86740a56073b	2933
AnnaBridge	143:86740a56073b	2934	/**
AnnaBridge	143:86740a56073b	2935	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
AnnaBridge	143:86740a56073b	2936	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
AnnaBridge	143:86740a56073b	2937	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2938	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	2939	*/
AnnaBridge	143:86740a56073b	2940	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2941	{
AnnaBridge	143:86740a56073b	2942	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
AnnaBridge	143:86740a56073b	2943	}
AnnaBridge	143:86740a56073b	2944
AnnaBridge	143:86740a56073b	2945	/**
AnnaBridge	143:86740a56073b	2946	* @brief Enable capture/compare 3 interrupt (CC3IE).
AnnaBridge	143:86740a56073b	2947	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
AnnaBridge	143:86740a56073b	2948	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2949	* @retval None
AnnaBridge	143:86740a56073b	2950	*/
AnnaBridge	143:86740a56073b	2951	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2952	{
AnnaBridge	143:86740a56073b	2953	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
AnnaBridge	143:86740a56073b	2954	}
AnnaBridge	143:86740a56073b	2955
AnnaBridge	143:86740a56073b	2956	/**
AnnaBridge	143:86740a56073b	2957	* @brief Disable capture/compare 3 interrupt (CC3IE).
AnnaBridge	143:86740a56073b	2958	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
AnnaBridge	143:86740a56073b	2959	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2960	* @retval None
AnnaBridge	143:86740a56073b	2961	*/
AnnaBridge	143:86740a56073b	2962	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2963	{
AnnaBridge	143:86740a56073b	2964	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
AnnaBridge	143:86740a56073b	2965	}
AnnaBridge	143:86740a56073b	2966
AnnaBridge	143:86740a56073b	2967	/**
AnnaBridge	143:86740a56073b	2968	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
AnnaBridge	143:86740a56073b	2969	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
AnnaBridge	143:86740a56073b	2970	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2971	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	2972	*/
AnnaBridge	143:86740a56073b	2973	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2974	{
AnnaBridge	143:86740a56073b	2975	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
AnnaBridge	143:86740a56073b	2976	}
AnnaBridge	143:86740a56073b	2977
AnnaBridge	143:86740a56073b	2978	/**
AnnaBridge	143:86740a56073b	2979	* @brief Enable capture/compare 4 interrupt (CC4IE).
AnnaBridge	143:86740a56073b	2980	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
AnnaBridge	143:86740a56073b	2981	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2982	* @retval None
AnnaBridge	143:86740a56073b	2983	*/
AnnaBridge	143:86740a56073b	2984	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2985	{
AnnaBridge	143:86740a56073b	2986	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
AnnaBridge	143:86740a56073b	2987	}
AnnaBridge	143:86740a56073b	2988
AnnaBridge	143:86740a56073b	2989	/**
AnnaBridge	143:86740a56073b	2990	* @brief Disable capture/compare 4 interrupt (CC4IE).
AnnaBridge	143:86740a56073b	2991	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
AnnaBridge	143:86740a56073b	2992	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	2993	* @retval None
AnnaBridge	143:86740a56073b	2994	*/
AnnaBridge	143:86740a56073b	2995	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	2996	{
AnnaBridge	143:86740a56073b	2997	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
AnnaBridge	143:86740a56073b	2998	}
AnnaBridge	143:86740a56073b	2999
AnnaBridge	143:86740a56073b	3000	/**
AnnaBridge	143:86740a56073b	3001	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
AnnaBridge	143:86740a56073b	3002	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
AnnaBridge	143:86740a56073b	3003	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3004	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	3005	*/
AnnaBridge	143:86740a56073b	3006	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3007	{
AnnaBridge	143:86740a56073b	3008	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
AnnaBridge	143:86740a56073b	3009	}
AnnaBridge	143:86740a56073b	3010
AnnaBridge	143:86740a56073b	3011
AnnaBridge	143:86740a56073b	3012	/**
AnnaBridge	143:86740a56073b	3013	* @brief Enable trigger interrupt (TIE).
AnnaBridge	143:86740a56073b	3014	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
AnnaBridge	143:86740a56073b	3015	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3016	* @retval None
AnnaBridge	143:86740a56073b	3017	*/
AnnaBridge	143:86740a56073b	3018	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3019	{
AnnaBridge	143:86740a56073b	3020	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
AnnaBridge	143:86740a56073b	3021	}
AnnaBridge	143:86740a56073b	3022
AnnaBridge	143:86740a56073b	3023	/**
AnnaBridge	143:86740a56073b	3024	* @brief Disable trigger interrupt (TIE).
AnnaBridge	143:86740a56073b	3025	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
AnnaBridge	143:86740a56073b	3026	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3027	* @retval None
AnnaBridge	143:86740a56073b	3028	*/
AnnaBridge	143:86740a56073b	3029	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3030	{
AnnaBridge	143:86740a56073b	3031	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
AnnaBridge	143:86740a56073b	3032	}
AnnaBridge	143:86740a56073b	3033
AnnaBridge	143:86740a56073b	3034	/**
AnnaBridge	143:86740a56073b	3035	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
AnnaBridge	143:86740a56073b	3036	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
AnnaBridge	143:86740a56073b	3037	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3038	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	3039	*/
AnnaBridge	143:86740a56073b	3040	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3041	{
AnnaBridge	143:86740a56073b	3042	return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
AnnaBridge	143:86740a56073b	3043	}
AnnaBridge	143:86740a56073b	3044
AnnaBridge	143:86740a56073b	3045
AnnaBridge	143:86740a56073b	3046	/**
AnnaBridge	143:86740a56073b	3047	* @}
AnnaBridge	143:86740a56073b	3048	*/
AnnaBridge	143:86740a56073b	3049
AnnaBridge	143:86740a56073b	3050	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
AnnaBridge	143:86740a56073b	3051	* @{
AnnaBridge	143:86740a56073b	3052	*/
AnnaBridge	143:86740a56073b	3053	/**
AnnaBridge	143:86740a56073b	3054	* @brief Enable update DMA request (UDE).
AnnaBridge	143:86740a56073b	3055	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
AnnaBridge	143:86740a56073b	3056	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3057	* @retval None
AnnaBridge	143:86740a56073b	3058	*/
AnnaBridge	143:86740a56073b	3059	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3060	{
AnnaBridge	143:86740a56073b	3061	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
AnnaBridge	143:86740a56073b	3062	}
AnnaBridge	143:86740a56073b	3063
AnnaBridge	143:86740a56073b	3064	/**
AnnaBridge	143:86740a56073b	3065	* @brief Disable update DMA request (UDE).
AnnaBridge	143:86740a56073b	3066	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
AnnaBridge	143:86740a56073b	3067	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3068	* @retval None
AnnaBridge	143:86740a56073b	3069	*/
AnnaBridge	143:86740a56073b	3070	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3071	{
AnnaBridge	143:86740a56073b	3072	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
AnnaBridge	143:86740a56073b	3073	}
AnnaBridge	143:86740a56073b	3074
AnnaBridge	143:86740a56073b	3075	/**
AnnaBridge	143:86740a56073b	3076	* @brief Indicates whether the update DMA request (UDE) is enabled.
AnnaBridge	143:86740a56073b	3077	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
AnnaBridge	143:86740a56073b	3078	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3079	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	3080	*/
AnnaBridge	143:86740a56073b	3081	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3082	{
AnnaBridge	143:86740a56073b	3083	return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
AnnaBridge	143:86740a56073b	3084	}
AnnaBridge	143:86740a56073b	3085
AnnaBridge	143:86740a56073b	3086	/**
AnnaBridge	143:86740a56073b	3087	* @brief Enable capture/compare 1 DMA request (CC1DE).
AnnaBridge	143:86740a56073b	3088	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
AnnaBridge	143:86740a56073b	3089	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3090	* @retval None
AnnaBridge	143:86740a56073b	3091	*/
AnnaBridge	143:86740a56073b	3092	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3093	{
AnnaBridge	143:86740a56073b	3094	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
AnnaBridge	143:86740a56073b	3095	}
AnnaBridge	143:86740a56073b	3096
AnnaBridge	143:86740a56073b	3097	/**
AnnaBridge	143:86740a56073b	3098	* @brief Disable capture/compare 1 DMA request (CC1DE).
AnnaBridge	143:86740a56073b	3099	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
AnnaBridge	143:86740a56073b	3100	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3101	* @retval None
AnnaBridge	143:86740a56073b	3102	*/
AnnaBridge	143:86740a56073b	3103	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3104	{
AnnaBridge	143:86740a56073b	3105	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
AnnaBridge	143:86740a56073b	3106	}
AnnaBridge	143:86740a56073b	3107
AnnaBridge	143:86740a56073b	3108	/**
AnnaBridge	143:86740a56073b	3109	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
AnnaBridge	143:86740a56073b	3110	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
AnnaBridge	143:86740a56073b	3111	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3112	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	3113	*/
AnnaBridge	143:86740a56073b	3114	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3115	{
AnnaBridge	143:86740a56073b	3116	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
AnnaBridge	143:86740a56073b	3117	}
AnnaBridge	143:86740a56073b	3118
AnnaBridge	143:86740a56073b	3119	/**
AnnaBridge	143:86740a56073b	3120	* @brief Enable capture/compare 2 DMA request (CC2DE).
AnnaBridge	143:86740a56073b	3121	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
AnnaBridge	143:86740a56073b	3122	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3123	* @retval None
AnnaBridge	143:86740a56073b	3124	*/
AnnaBridge	143:86740a56073b	3125	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3126	{
AnnaBridge	143:86740a56073b	3127	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
AnnaBridge	143:86740a56073b	3128	}
AnnaBridge	143:86740a56073b	3129
AnnaBridge	143:86740a56073b	3130	/**
AnnaBridge	143:86740a56073b	3131	* @brief Disable capture/compare 2 DMA request (CC2DE).
AnnaBridge	143:86740a56073b	3132	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
AnnaBridge	143:86740a56073b	3133	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3134	* @retval None
AnnaBridge	143:86740a56073b	3135	*/
AnnaBridge	143:86740a56073b	3136	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3137	{
AnnaBridge	143:86740a56073b	3138	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
AnnaBridge	143:86740a56073b	3139	}
AnnaBridge	143:86740a56073b	3140
AnnaBridge	143:86740a56073b	3141	/**
AnnaBridge	143:86740a56073b	3142	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
AnnaBridge	143:86740a56073b	3143	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
AnnaBridge	143:86740a56073b	3144	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3145	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	3146	*/
AnnaBridge	143:86740a56073b	3147	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3148	{
AnnaBridge	143:86740a56073b	3149	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
AnnaBridge	143:86740a56073b	3150	}
AnnaBridge	143:86740a56073b	3151
AnnaBridge	143:86740a56073b	3152	/**
AnnaBridge	143:86740a56073b	3153	* @brief Enable capture/compare 3 DMA request (CC3DE).
AnnaBridge	143:86740a56073b	3154	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
AnnaBridge	143:86740a56073b	3155	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3156	* @retval None
AnnaBridge	143:86740a56073b	3157	*/
AnnaBridge	143:86740a56073b	3158	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3159	{
AnnaBridge	143:86740a56073b	3160	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
AnnaBridge	143:86740a56073b	3161	}
AnnaBridge	143:86740a56073b	3162
AnnaBridge	143:86740a56073b	3163	/**
AnnaBridge	143:86740a56073b	3164	* @brief Disable capture/compare 3 DMA request (CC3DE).
AnnaBridge	143:86740a56073b	3165	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
AnnaBridge	143:86740a56073b	3166	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3167	* @retval None
AnnaBridge	143:86740a56073b	3168	*/
AnnaBridge	143:86740a56073b	3169	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3170	{
AnnaBridge	143:86740a56073b	3171	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
AnnaBridge	143:86740a56073b	3172	}
AnnaBridge	143:86740a56073b	3173
AnnaBridge	143:86740a56073b	3174	/**
AnnaBridge	143:86740a56073b	3175	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
AnnaBridge	143:86740a56073b	3176	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
AnnaBridge	143:86740a56073b	3177	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3178	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	3179	*/
AnnaBridge	143:86740a56073b	3180	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3181	{
AnnaBridge	143:86740a56073b	3182	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
AnnaBridge	143:86740a56073b	3183	}
AnnaBridge	143:86740a56073b	3184
AnnaBridge	143:86740a56073b	3185	/**
AnnaBridge	143:86740a56073b	3186	* @brief Enable capture/compare 4 DMA request (CC4DE).
AnnaBridge	143:86740a56073b	3187	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
AnnaBridge	143:86740a56073b	3188	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3189	* @retval None
AnnaBridge	143:86740a56073b	3190	*/
AnnaBridge	143:86740a56073b	3191	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3192	{
AnnaBridge	143:86740a56073b	3193	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
AnnaBridge	143:86740a56073b	3194	}
AnnaBridge	143:86740a56073b	3195
AnnaBridge	143:86740a56073b	3196	/**
AnnaBridge	143:86740a56073b	3197	* @brief Disable capture/compare 4 DMA request (CC4DE).
AnnaBridge	143:86740a56073b	3198	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
AnnaBridge	143:86740a56073b	3199	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3200	* @retval None
AnnaBridge	143:86740a56073b	3201	*/
AnnaBridge	143:86740a56073b	3202	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3203	{
AnnaBridge	143:86740a56073b	3204	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
AnnaBridge	143:86740a56073b	3205	}
AnnaBridge	143:86740a56073b	3206
AnnaBridge	143:86740a56073b	3207	/**
AnnaBridge	143:86740a56073b	3208	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
AnnaBridge	143:86740a56073b	3209	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
AnnaBridge	143:86740a56073b	3210	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3211	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	3212	*/
AnnaBridge	143:86740a56073b	3213	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3214	{
AnnaBridge	143:86740a56073b	3215	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
AnnaBridge	143:86740a56073b	3216	}
AnnaBridge	143:86740a56073b	3217
AnnaBridge	143:86740a56073b	3218
AnnaBridge	143:86740a56073b	3219	/**
AnnaBridge	143:86740a56073b	3220	* @brief Enable trigger interrupt (TDE).
AnnaBridge	143:86740a56073b	3221	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
AnnaBridge	143:86740a56073b	3222	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3223	* @retval None
AnnaBridge	143:86740a56073b	3224	*/
AnnaBridge	143:86740a56073b	3225	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3226	{
AnnaBridge	143:86740a56073b	3227	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
AnnaBridge	143:86740a56073b	3228	}
AnnaBridge	143:86740a56073b	3229
AnnaBridge	143:86740a56073b	3230	/**
AnnaBridge	143:86740a56073b	3231	* @brief Disable trigger interrupt (TDE).
AnnaBridge	143:86740a56073b	3232	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
AnnaBridge	143:86740a56073b	3233	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3234	* @retval None
AnnaBridge	143:86740a56073b	3235	*/
AnnaBridge	143:86740a56073b	3236	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3237	{
AnnaBridge	143:86740a56073b	3238	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
AnnaBridge	143:86740a56073b	3239	}
AnnaBridge	143:86740a56073b	3240
AnnaBridge	143:86740a56073b	3241	/**
AnnaBridge	143:86740a56073b	3242	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
AnnaBridge	143:86740a56073b	3243	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
AnnaBridge	143:86740a56073b	3244	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3245	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	3246	*/
AnnaBridge	143:86740a56073b	3247	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3248	{
AnnaBridge	143:86740a56073b	3249	return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
AnnaBridge	143:86740a56073b	3250	}
AnnaBridge	143:86740a56073b	3251
AnnaBridge	143:86740a56073b	3252	/**
AnnaBridge	143:86740a56073b	3253	* @}
AnnaBridge	143:86740a56073b	3254	*/
AnnaBridge	143:86740a56073b	3255
AnnaBridge	143:86740a56073b	3256	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
AnnaBridge	143:86740a56073b	3257	* @{
AnnaBridge	143:86740a56073b	3258	*/
AnnaBridge	143:86740a56073b	3259	/**
AnnaBridge	143:86740a56073b	3260	* @brief Generate an update event.
AnnaBridge	143:86740a56073b	3261	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
AnnaBridge	143:86740a56073b	3262	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3263	* @retval None
AnnaBridge	143:86740a56073b	3264	*/
AnnaBridge	143:86740a56073b	3265	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3266	{
AnnaBridge	143:86740a56073b	3267	SET_BIT(TIMx->EGR, TIM_EGR_UG);
AnnaBridge	143:86740a56073b	3268	}
AnnaBridge	143:86740a56073b	3269
AnnaBridge	143:86740a56073b	3270	/**
AnnaBridge	143:86740a56073b	3271	* @brief Generate Capture/Compare 1 event.
AnnaBridge	143:86740a56073b	3272	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
AnnaBridge	143:86740a56073b	3273	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3274	* @retval None
AnnaBridge	143:86740a56073b	3275	*/
AnnaBridge	143:86740a56073b	3276	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3277	{
AnnaBridge	143:86740a56073b	3278	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
AnnaBridge	143:86740a56073b	3279	}
AnnaBridge	143:86740a56073b	3280
AnnaBridge	143:86740a56073b	3281	/**
AnnaBridge	143:86740a56073b	3282	* @brief Generate Capture/Compare 2 event.
AnnaBridge	143:86740a56073b	3283	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
AnnaBridge	143:86740a56073b	3284	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3285	* @retval None
AnnaBridge	143:86740a56073b	3286	*/
AnnaBridge	143:86740a56073b	3287	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3288	{
AnnaBridge	143:86740a56073b	3289	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
AnnaBridge	143:86740a56073b	3290	}
AnnaBridge	143:86740a56073b	3291
AnnaBridge	143:86740a56073b	3292	/**
AnnaBridge	143:86740a56073b	3293	* @brief Generate Capture/Compare 3 event.
AnnaBridge	143:86740a56073b	3294	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
AnnaBridge	143:86740a56073b	3295	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3296	* @retval None
AnnaBridge	143:86740a56073b	3297	*/
AnnaBridge	143:86740a56073b	3298	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3299	{
AnnaBridge	143:86740a56073b	3300	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
AnnaBridge	143:86740a56073b	3301	}
AnnaBridge	143:86740a56073b	3302
AnnaBridge	143:86740a56073b	3303	/**
AnnaBridge	143:86740a56073b	3304	* @brief Generate Capture/Compare 4 event.
AnnaBridge	143:86740a56073b	3305	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
AnnaBridge	143:86740a56073b	3306	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3307	* @retval None
AnnaBridge	143:86740a56073b	3308	*/
AnnaBridge	143:86740a56073b	3309	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3310	{
AnnaBridge	143:86740a56073b	3311	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
AnnaBridge	143:86740a56073b	3312	}
AnnaBridge	143:86740a56073b	3313
AnnaBridge	143:86740a56073b	3314
AnnaBridge	143:86740a56073b	3315	/**
AnnaBridge	143:86740a56073b	3316	* @brief Generate trigger event.
AnnaBridge	143:86740a56073b	3317	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
AnnaBridge	143:86740a56073b	3318	* @param TIMx Timer instance
AnnaBridge	143:86740a56073b	3319	* @retval None
AnnaBridge	143:86740a56073b	3320	*/
AnnaBridge	143:86740a56073b	3321	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)
AnnaBridge	143:86740a56073b	3322	{
AnnaBridge	143:86740a56073b	3323	SET_BIT(TIMx->EGR, TIM_EGR_TG);
AnnaBridge	143:86740a56073b	3324	}
AnnaBridge	143:86740a56073b	3325
AnnaBridge	143:86740a56073b	3326
AnnaBridge	143:86740a56073b	3327
AnnaBridge	143:86740a56073b	3328	/**
AnnaBridge	143:86740a56073b	3329	* @}
AnnaBridge	143:86740a56073b	3330	*/
AnnaBridge	143:86740a56073b	3331
AnnaBridge	143:86740a56073b	3332	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	143:86740a56073b	3333	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
AnnaBridge	143:86740a56073b	3334	* @{
AnnaBridge	143:86740a56073b	3335	*/
AnnaBridge	143:86740a56073b	3336
AnnaBridge	143:86740a56073b	3337	ErrorStatus LL_TIM_DeInit(TIM_TypeDef* TIMx);
AnnaBridge	143:86740a56073b	3338	void LL_TIM_StructInit(LL_TIM_InitTypeDef* TIM_InitStruct);
AnnaBridge	143:86740a56073b	3339	ErrorStatus LL_TIM_Init(TIM_TypeDef* TIMx, LL_TIM_InitTypeDef* TIM_InitStruct);
AnnaBridge	143:86740a56073b	3340	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef* TIM_OC_InitStruct);
AnnaBridge	143:86740a56073b	3341	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef* TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef* TIM_OC_InitStruct);
AnnaBridge	143:86740a56073b	3342	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef* TIM_ICInitStruct);
AnnaBridge	143:86740a56073b	3343	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef* TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef* TIM_IC_InitStruct);
AnnaBridge	143:86740a56073b	3344	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef* TIM_EncoderInitStruct);
AnnaBridge	143:86740a56073b	3345	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef* TIMx, LL_TIM_ENCODER_InitTypeDef* TIM_EncoderInitStruct);
AnnaBridge	143:86740a56073b	3346	/**
AnnaBridge	143:86740a56073b	3347	* @}
AnnaBridge	143:86740a56073b	3348	*/
AnnaBridge	143:86740a56073b	3349	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	143:86740a56073b	3350
AnnaBridge	143:86740a56073b	3351	/**
AnnaBridge	143:86740a56073b	3352	* @}
AnnaBridge	143:86740a56073b	3353	*/
AnnaBridge	143:86740a56073b	3354
AnnaBridge	143:86740a56073b	3355	/**
AnnaBridge	143:86740a56073b	3356	* @}
AnnaBridge	143:86740a56073b	3357	*/
AnnaBridge	143:86740a56073b	3358
AnnaBridge	143:86740a56073b	3359	#endif /* TIM1 \|\| TIM3 \|\| TIM21 \|\| TIM22 \|\| TIM6 \|\| TIM7 */
AnnaBridge	143:86740a56073b	3360
AnnaBridge	143:86740a56073b	3361	/**
AnnaBridge	143:86740a56073b	3362	* @}
AnnaBridge	143:86740a56073b	3363	*/
AnnaBridge	143:86740a56073b	3364
AnnaBridge	143:86740a56073b	3365	#ifdef __cplusplus
AnnaBridge	143:86740a56073b	3366	}
AnnaBridge	143:86740a56073b	3367	#endif
AnnaBridge	143:86740a56073b	3368
AnnaBridge	143:86740a56073b	3369	#endif /* __STM32L0xx_LL_TIM_H */
AnnaBridge	143:86740a56073b	3370
AnnaBridge	143:86740a56073b	3371	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/