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TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_spi.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:30:20 2017 +0100
Revision:: 143:86740a56073b
Child:: 167:84c0a372a020

Release 143 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	143:86740a56073b	1	/**
AnnaBridge	143:86740a56073b	2	******************************************************************************
AnnaBridge	143:86740a56073b	3	* @file stm32l0xx_ll_spi.h
AnnaBridge	143:86740a56073b	4	* @author MCD Application Team
AnnaBridge	143:86740a56073b	5	* @version V1.7.0
AnnaBridge	143:86740a56073b	6	* @date 31-May-2016
AnnaBridge	143:86740a56073b	7	* @brief Header file of SPI LL module.
AnnaBridge	143:86740a56073b	8	******************************************************************************
AnnaBridge	143:86740a56073b	9	* @attention
AnnaBridge	143:86740a56073b	10	*
AnnaBridge	143:86740a56073b	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	143:86740a56073b	12	*
AnnaBridge	143:86740a56073b	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	143:86740a56073b	14	* are permitted provided that the following conditions are met:
AnnaBridge	143:86740a56073b	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	143:86740a56073b	16	* this list of conditions and the following disclaimer.
AnnaBridge	143:86740a56073b	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	143:86740a56073b	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	143:86740a56073b	19	* and/or other materials provided with the distribution.
AnnaBridge	143:86740a56073b	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	143:86740a56073b	21	* may be used to endorse or promote products derived from this software
AnnaBridge	143:86740a56073b	22	* without specific prior written permission.
AnnaBridge	143:86740a56073b	23	*
AnnaBridge	143:86740a56073b	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	143:86740a56073b	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	143:86740a56073b	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	143:86740a56073b	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	143:86740a56073b	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	143:86740a56073b	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	143:86740a56073b	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	143:86740a56073b	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	143:86740a56073b	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	143:86740a56073b	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	143:86740a56073b	34	*
AnnaBridge	143:86740a56073b	35	******************************************************************************
AnnaBridge	143:86740a56073b	36	*/
AnnaBridge	143:86740a56073b	37
AnnaBridge	143:86740a56073b	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	143:86740a56073b	39	#ifndef __STM32L0xx_LL_SPI_H
AnnaBridge	143:86740a56073b	40	#define __STM32L0xx_LL_SPI_H
AnnaBridge	143:86740a56073b	41
AnnaBridge	143:86740a56073b	42	#ifdef __cplusplus
AnnaBridge	143:86740a56073b	43	extern "C" {
AnnaBridge	143:86740a56073b	44	#endif
AnnaBridge	143:86740a56073b	45
AnnaBridge	143:86740a56073b	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	47	#include "stm32l0xx.h"
AnnaBridge	143:86740a56073b	48
AnnaBridge	143:86740a56073b	49	/** @addtogroup STM32L0xx_LL_Driver
AnnaBridge	143:86740a56073b	50	* @{
AnnaBridge	143:86740a56073b	51	*/
AnnaBridge	143:86740a56073b	52
AnnaBridge	143:86740a56073b	53	#if defined (SPI1) \|\| defined (SPI2)
AnnaBridge	143:86740a56073b	54
AnnaBridge	143:86740a56073b	55	/** @defgroup SPI_LL SPI
AnnaBridge	143:86740a56073b	56	* @{
AnnaBridge	143:86740a56073b	57	*/
AnnaBridge	143:86740a56073b	58
AnnaBridge	143:86740a56073b	59	/* Private types -------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	60	/* Private variables ---------------------------------------------------------*/
AnnaBridge	143:86740a56073b	61	/* Private macros ------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	62
AnnaBridge	143:86740a56073b	63	/* Exported types ------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	64	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	143:86740a56073b	65	/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
AnnaBridge	143:86740a56073b	66	* @{
AnnaBridge	143:86740a56073b	67	*/
AnnaBridge	143:86740a56073b	68
AnnaBridge	143:86740a56073b	69	/**
AnnaBridge	143:86740a56073b	70	* @brief SPI Init structures definition
AnnaBridge	143:86740a56073b	71	*/
AnnaBridge	143:86740a56073b	72	typedef struct
AnnaBridge	143:86740a56073b	73	{
AnnaBridge	143:86740a56073b	74	uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
AnnaBridge	143:86740a56073b	75	This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
AnnaBridge	143:86740a56073b	76
AnnaBridge	143:86740a56073b	77	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
AnnaBridge	143:86740a56073b	78
AnnaBridge	143:86740a56073b	79	uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
AnnaBridge	143:86740a56073b	80	This parameter can be a value of @ref SPI_LL_EC_MODE.
AnnaBridge	143:86740a56073b	81
AnnaBridge	143:86740a56073b	82	This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
AnnaBridge	143:86740a56073b	83
AnnaBridge	143:86740a56073b	84	uint32_t DataWidth; /*!< Specifies the SPI data width.
AnnaBridge	143:86740a56073b	85	This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
AnnaBridge	143:86740a56073b	86
AnnaBridge	143:86740a56073b	87	This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
AnnaBridge	143:86740a56073b	88
AnnaBridge	143:86740a56073b	89	uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
AnnaBridge	143:86740a56073b	90	This parameter can be a value of @ref SPI_LL_EC_POLARITY.
AnnaBridge	143:86740a56073b	91
AnnaBridge	143:86740a56073b	92	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
AnnaBridge	143:86740a56073b	93
AnnaBridge	143:86740a56073b	94	uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
AnnaBridge	143:86740a56073b	95	This parameter can be a value of @ref SPI_LL_EC_PHASE.
AnnaBridge	143:86740a56073b	96
AnnaBridge	143:86740a56073b	97	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
AnnaBridge	143:86740a56073b	98
AnnaBridge	143:86740a56073b	99	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
AnnaBridge	143:86740a56073b	100	This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
AnnaBridge	143:86740a56073b	101
AnnaBridge	143:86740a56073b	102	This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
AnnaBridge	143:86740a56073b	103
AnnaBridge	143:86740a56073b	104	uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
AnnaBridge	143:86740a56073b	105	This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
AnnaBridge	143:86740a56073b	106	@note The communication clock is derived from the master clock. The slave clock does not need to be set.
AnnaBridge	143:86740a56073b	107
AnnaBridge	143:86740a56073b	108	This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
AnnaBridge	143:86740a56073b	109
AnnaBridge	143:86740a56073b	110	uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
AnnaBridge	143:86740a56073b	111	This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
AnnaBridge	143:86740a56073b	112
AnnaBridge	143:86740a56073b	113	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
AnnaBridge	143:86740a56073b	114
AnnaBridge	143:86740a56073b	115	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
AnnaBridge	143:86740a56073b	116	This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
AnnaBridge	143:86740a56073b	117
AnnaBridge	143:86740a56073b	118	This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
AnnaBridge	143:86740a56073b	119
AnnaBridge	143:86740a56073b	120	uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
AnnaBridge	143:86740a56073b	121	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
AnnaBridge	143:86740a56073b	122
AnnaBridge	143:86740a56073b	123	This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
AnnaBridge	143:86740a56073b	124
AnnaBridge	143:86740a56073b	125	} LL_SPI_InitTypeDef;
AnnaBridge	143:86740a56073b	126
AnnaBridge	143:86740a56073b	127	/**
AnnaBridge	143:86740a56073b	128	* @}
AnnaBridge	143:86740a56073b	129	*/
AnnaBridge	143:86740a56073b	130	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	143:86740a56073b	131
AnnaBridge	143:86740a56073b	132	/* Exported constants --------------------------------------------------------*/
AnnaBridge	143:86740a56073b	133	/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
AnnaBridge	143:86740a56073b	134	* @{
AnnaBridge	143:86740a56073b	135	*/
AnnaBridge	143:86740a56073b	136
AnnaBridge	143:86740a56073b	137	/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	143:86740a56073b	138	* @brief Flags defines which can be used with LL_SPI_ReadReg function
AnnaBridge	143:86740a56073b	139	* @{
AnnaBridge	143:86740a56073b	140	*/
AnnaBridge	143:86740a56073b	141	#define LL_SPI_SR_RXNE SPI_SR_RXNE /!< Rx buffer not empty flag /
AnnaBridge	143:86740a56073b	142	#define LL_SPI_SR_TXE SPI_SR_TXE /!< Tx buffer empty flag /
AnnaBridge	143:86740a56073b	143	#define LL_SPI_SR_BSY SPI_SR_BSY /!< Busy flag /
AnnaBridge	143:86740a56073b	144	#define LL_SPI_SR_UDR SPI_SR_UDR /!< Underrun flag /
AnnaBridge	143:86740a56073b	145	#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /!< CRC error flag /
AnnaBridge	143:86740a56073b	146	#define LL_SPI_SR_MODF SPI_SR_MODF /!< Mode fault flag /
AnnaBridge	143:86740a56073b	147	#define LL_SPI_SR_OVR SPI_SR_OVR /!< Overrun flag /
AnnaBridge	143:86740a56073b	148	#define LL_SPI_SR_FRE SPI_SR_FRE /!< TI mode frame format error flag /
AnnaBridge	143:86740a56073b	149	/**
AnnaBridge	143:86740a56073b	150	* @}
AnnaBridge	143:86740a56073b	151	*/
AnnaBridge	143:86740a56073b	152
AnnaBridge	143:86740a56073b	153	/** @defgroup SPI_LL_EC_IT IT Defines
AnnaBridge	143:86740a56073b	154	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
AnnaBridge	143:86740a56073b	155	* @{
AnnaBridge	143:86740a56073b	156	*/
AnnaBridge	143:86740a56073b	157	#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
AnnaBridge	143:86740a56073b	158	#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
AnnaBridge	143:86740a56073b	159	#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /!< Error interrupt enable /
AnnaBridge	143:86740a56073b	160	/**
AnnaBridge	143:86740a56073b	161	* @}
AnnaBridge	143:86740a56073b	162	*/
AnnaBridge	143:86740a56073b	163
AnnaBridge	143:86740a56073b	164	/** @defgroup SPI_LL_EC_MODE Operation Mode
AnnaBridge	143:86740a56073b	165	* @{
AnnaBridge	143:86740a56073b	166	*/
AnnaBridge	143:86740a56073b	167	#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI) /!< Master configuration /
AnnaBridge	143:86740a56073b	168	#define LL_SPI_MODE_SLAVE ((uint32_t)0x00000000U) /!< Slave configuration /
AnnaBridge	143:86740a56073b	169	/**
AnnaBridge	143:86740a56073b	170	* @}
AnnaBridge	143:86740a56073b	171	*/
AnnaBridge	143:86740a56073b	172
AnnaBridge	143:86740a56073b	173	/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
AnnaBridge	143:86740a56073b	174	* @{
AnnaBridge	143:86740a56073b	175	*/
AnnaBridge	143:86740a56073b	176	#define LL_SPI_PROTOCOL_MOTOROLA ((uint32_t)0x00000000U) /!< Motorola mode. Used as default value /
AnnaBridge	143:86740a56073b	177	#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /!< TI mode /
AnnaBridge	143:86740a56073b	178	/**
AnnaBridge	143:86740a56073b	179	* @}
AnnaBridge	143:86740a56073b	180	*/
AnnaBridge	143:86740a56073b	181
AnnaBridge	143:86740a56073b	182	/** @defgroup SPI_LL_EC_PHASE Clock Phase
AnnaBridge	143:86740a56073b	183	* @{
AnnaBridge	143:86740a56073b	184	*/
AnnaBridge	143:86740a56073b	185	#define LL_SPI_PHASE_1EDGE ((uint32_t)0x00000000U) /!< First clock transition is the first data capture edge /
AnnaBridge	143:86740a56073b	186	#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /!< Second clock transition is the first data capture edge /
AnnaBridge	143:86740a56073b	187	/**
AnnaBridge	143:86740a56073b	188	* @}
AnnaBridge	143:86740a56073b	189	*/
AnnaBridge	143:86740a56073b	190
AnnaBridge	143:86740a56073b	191	/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
AnnaBridge	143:86740a56073b	192	* @{
AnnaBridge	143:86740a56073b	193	*/
AnnaBridge	143:86740a56073b	194	#define LL_SPI_POLARITY_LOW ((uint32_t)0x00000000U) /!< Clock to 0 when idle /
AnnaBridge	143:86740a56073b	195	#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /!< Clock to 1 when idle /
AnnaBridge	143:86740a56073b	196	/**
AnnaBridge	143:86740a56073b	197	* @}
AnnaBridge	143:86740a56073b	198	*/
AnnaBridge	143:86740a56073b	199
AnnaBridge	143:86740a56073b	200	/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
AnnaBridge	143:86740a56073b	201	* @{
AnnaBridge	143:86740a56073b	202	*/
AnnaBridge	143:86740a56073b	203	#define LL_SPI_BAUDRATEPRESCALER_DIV2 ((uint32_t)0x00000000U) /!< BaudRate control equal to fPCLK/2 /
AnnaBridge	143:86740a56073b	204	#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/4 /
AnnaBridge	143:86740a56073b	205	#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/8 /
AnnaBridge	143:86740a56073b	206	#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/16 /
AnnaBridge	143:86740a56073b	207	#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /!< BaudRate control equal to fPCLK/32 /
AnnaBridge	143:86740a56073b	208	#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/64 /
AnnaBridge	143:86740a56073b	209	#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 \| SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/128 /
AnnaBridge	143:86740a56073b	210	#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 \| SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/256 /
AnnaBridge	143:86740a56073b	211	/**
AnnaBridge	143:86740a56073b	212	* @}
AnnaBridge	143:86740a56073b	213	*/
AnnaBridge	143:86740a56073b	214
AnnaBridge	143:86740a56073b	215	/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
AnnaBridge	143:86740a56073b	216	* @{
AnnaBridge	143:86740a56073b	217	*/
AnnaBridge	143:86740a56073b	218	#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /!< Data is transmitted/received with the LSB first /
AnnaBridge	143:86740a56073b	219	#define LL_SPI_MSB_FIRST ((uint32_t)0x00000000U) /!< Data is transmitted/received with the MSB first /
AnnaBridge	143:86740a56073b	220	/**
AnnaBridge	143:86740a56073b	221	* @}
AnnaBridge	143:86740a56073b	222	*/
AnnaBridge	143:86740a56073b	223
AnnaBridge	143:86740a56073b	224	/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
AnnaBridge	143:86740a56073b	225	* @{
AnnaBridge	143:86740a56073b	226	*/
AnnaBridge	143:86740a56073b	227	#define LL_SPI_FULL_DUPLEX ((uint32_t)0x00000000U) /!< Full-Duplex mode. Rx and Tx transfer on 2 lines /
AnnaBridge	143:86740a56073b	228	#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /!< Simplex Rx mode. Rx transfer only on 1 line /
AnnaBridge	143:86740a56073b	229	#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /!< Half-Duplex Rx mode. Rx transfer on 1 line /
AnnaBridge	143:86740a56073b	230	#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE) /!< Half-Duplex Tx mode. Tx transfer on 1 line /
AnnaBridge	143:86740a56073b	231	/**
AnnaBridge	143:86740a56073b	232	* @}
AnnaBridge	143:86740a56073b	233	*/
AnnaBridge	143:86740a56073b	234
AnnaBridge	143:86740a56073b	235	/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
AnnaBridge	143:86740a56073b	236	* @{
AnnaBridge	143:86740a56073b	237	*/
AnnaBridge	143:86740a56073b	238	#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /!< NSS managed internally. NSS pin not used and free /
AnnaBridge	143:86740a56073b	239	#define LL_SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U) /!< NSS pin used in Input. Only used in Master mode /
AnnaBridge	143:86740a56073b	240	#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /!< NSS pin used in Output. Only used in Slave mode as chip select /
AnnaBridge	143:86740a56073b	241	/**
AnnaBridge	143:86740a56073b	242	* @}
AnnaBridge	143:86740a56073b	243	*/
AnnaBridge	143:86740a56073b	244
AnnaBridge	143:86740a56073b	245	/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
AnnaBridge	143:86740a56073b	246	* @{
AnnaBridge	143:86740a56073b	247	*/
AnnaBridge	143:86740a56073b	248	#define LL_SPI_DATAWIDTH_8BIT ((uint32_t)0x00000000U) /!< Data length for SPI transfer: 8 bits /
AnnaBridge	143:86740a56073b	249	#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /!< Data length for SPI transfer: 16 bits /
AnnaBridge	143:86740a56073b	250	/**
AnnaBridge	143:86740a56073b	251	* @}
AnnaBridge	143:86740a56073b	252	*/
AnnaBridge	143:86740a56073b	253	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	143:86740a56073b	254
AnnaBridge	143:86740a56073b	255	/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
AnnaBridge	143:86740a56073b	256	* @{
AnnaBridge	143:86740a56073b	257	*/
AnnaBridge	143:86740a56073b	258	#define LL_SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U) /!< CRC calculation disabled /
AnnaBridge	143:86740a56073b	259	#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /!< CRC calculation enabled /
AnnaBridge	143:86740a56073b	260	/**
AnnaBridge	143:86740a56073b	261	* @}
AnnaBridge	143:86740a56073b	262	*/
AnnaBridge	143:86740a56073b	263	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	143:86740a56073b	264
AnnaBridge	143:86740a56073b	265	/**
AnnaBridge	143:86740a56073b	266	* @}
AnnaBridge	143:86740a56073b	267	*/
AnnaBridge	143:86740a56073b	268
AnnaBridge	143:86740a56073b	269	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	270	/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
AnnaBridge	143:86740a56073b	271	* @{
AnnaBridge	143:86740a56073b	272	*/
AnnaBridge	143:86740a56073b	273
AnnaBridge	143:86740a56073b	274	/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	143:86740a56073b	275	* @{
AnnaBridge	143:86740a56073b	276	*/
AnnaBridge	143:86740a56073b	277
AnnaBridge	143:86740a56073b	278	/**
AnnaBridge	143:86740a56073b	279	* @brief Write a value in SPI register
AnnaBridge	143:86740a56073b	280	* @param __INSTANCE__ SPI Instance
AnnaBridge	143:86740a56073b	281	* @param __REG__ Register to be written
AnnaBridge	143:86740a56073b	282	* @param __VALUE__ Value to be written in the register
AnnaBridge	143:86740a56073b	283	* @retval None
AnnaBridge	143:86740a56073b	284	*/
AnnaBridge	143:86740a56073b	285	#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	143:86740a56073b	286
AnnaBridge	143:86740a56073b	287	/**
AnnaBridge	143:86740a56073b	288	* @brief Read a value in SPI register
AnnaBridge	143:86740a56073b	289	* @param __INSTANCE__ SPI Instance
AnnaBridge	143:86740a56073b	290	* @param __REG__ Register to be read
AnnaBridge	143:86740a56073b	291	* @retval Register value
AnnaBridge	143:86740a56073b	292	*/
AnnaBridge	143:86740a56073b	293	#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	143:86740a56073b	294	/**
AnnaBridge	143:86740a56073b	295	* @}
AnnaBridge	143:86740a56073b	296	*/
AnnaBridge	143:86740a56073b	297
AnnaBridge	143:86740a56073b	298	/**
AnnaBridge	143:86740a56073b	299	* @}
AnnaBridge	143:86740a56073b	300	*/
AnnaBridge	143:86740a56073b	301
AnnaBridge	143:86740a56073b	302	/* Exported functions --------------------------------------------------------*/
AnnaBridge	143:86740a56073b	303	/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
AnnaBridge	143:86740a56073b	304	* @{
AnnaBridge	143:86740a56073b	305	*/
AnnaBridge	143:86740a56073b	306
AnnaBridge	143:86740a56073b	307	/** @defgroup SPI_LL_EF_Configuration Configuration
AnnaBridge	143:86740a56073b	308	* @{
AnnaBridge	143:86740a56073b	309	*/
AnnaBridge	143:86740a56073b	310
AnnaBridge	143:86740a56073b	311	/**
AnnaBridge	143:86740a56073b	312	* @brief Enable SPI peripheral
AnnaBridge	143:86740a56073b	313	* @rmtoll CR1 SPE LL_SPI_Enable
AnnaBridge	143:86740a56073b	314	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	315	* @retval None
AnnaBridge	143:86740a56073b	316	*/
AnnaBridge	143:86740a56073b	317	__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	318	{
AnnaBridge	143:86740a56073b	319	SET_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	143:86740a56073b	320	}
AnnaBridge	143:86740a56073b	321
AnnaBridge	143:86740a56073b	322	/**
AnnaBridge	143:86740a56073b	323	* @brief Disable SPI peripheral
AnnaBridge	143:86740a56073b	324	* @note When disabling the SPI, follow the procedure described in the Reference Manual.
AnnaBridge	143:86740a56073b	325	* @rmtoll CR1 SPE LL_SPI_Disable
AnnaBridge	143:86740a56073b	326	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	327	* @retval None
AnnaBridge	143:86740a56073b	328	*/
AnnaBridge	143:86740a56073b	329	__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	330	{
AnnaBridge	143:86740a56073b	331	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	143:86740a56073b	332	}
AnnaBridge	143:86740a56073b	333
AnnaBridge	143:86740a56073b	334	/**
AnnaBridge	143:86740a56073b	335	* @brief Check if SPI peripheral is enabled
AnnaBridge	143:86740a56073b	336	* @rmtoll CR1 SPE LL_SPI_IsEnabled
AnnaBridge	143:86740a56073b	337	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	338	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	339	*/
AnnaBridge	143:86740a56073b	340	__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	341	{
AnnaBridge	143:86740a56073b	342	return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
AnnaBridge	143:86740a56073b	343	}
AnnaBridge	143:86740a56073b	344
AnnaBridge	143:86740a56073b	345	/**
AnnaBridge	143:86740a56073b	346	* @brief Set SPI operation mode to Master or Slave
AnnaBridge	143:86740a56073b	347	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	143:86740a56073b	348	* @rmtoll CR1 MSTR LL_SPI_SetMode\n
AnnaBridge	143:86740a56073b	349	* CR1 SSI LL_SPI_SetMode
AnnaBridge	143:86740a56073b	350	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	351	* @param Mode This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	352	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	143:86740a56073b	353	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	143:86740a56073b	354	* @retval None
AnnaBridge	143:86740a56073b	355	*/
AnnaBridge	143:86740a56073b	356	__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
AnnaBridge	143:86740a56073b	357	{
AnnaBridge	143:86740a56073b	358	MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI, Mode);
AnnaBridge	143:86740a56073b	359	}
AnnaBridge	143:86740a56073b	360
AnnaBridge	143:86740a56073b	361	/**
AnnaBridge	143:86740a56073b	362	* @brief Get SPI operation mode (Master or Slave)
AnnaBridge	143:86740a56073b	363	* @rmtoll CR1 MSTR LL_SPI_GetMode\n
AnnaBridge	143:86740a56073b	364	* CR1 SSI LL_SPI_GetMode
AnnaBridge	143:86740a56073b	365	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	366	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	367	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	143:86740a56073b	368	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	143:86740a56073b	369	*/
AnnaBridge	143:86740a56073b	370	__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	371	{
AnnaBridge	143:86740a56073b	372	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI));
AnnaBridge	143:86740a56073b	373	}
AnnaBridge	143:86740a56073b	374
AnnaBridge	143:86740a56073b	375	/**
AnnaBridge	143:86740a56073b	376	* @brief Set serial protocol used
AnnaBridge	143:86740a56073b	377	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	143:86740a56073b	378	* @rmtoll CR2 FRF LL_SPI_SetStandard
AnnaBridge	143:86740a56073b	379	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	380	* @param Standard This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	381	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge	143:86740a56073b	382	* @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge	143:86740a56073b	383	* @retval None
AnnaBridge	143:86740a56073b	384	*/
AnnaBridge	143:86740a56073b	385	__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge	143:86740a56073b	386	{
AnnaBridge	143:86740a56073b	387	MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
AnnaBridge	143:86740a56073b	388	}
AnnaBridge	143:86740a56073b	389
AnnaBridge	143:86740a56073b	390	/**
AnnaBridge	143:86740a56073b	391	* @brief Get serial protocol used
AnnaBridge	143:86740a56073b	392	* @rmtoll CR2 FRF LL_SPI_GetStandard
AnnaBridge	143:86740a56073b	393	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	394	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	395	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge	143:86740a56073b	396	* @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge	143:86740a56073b	397	*/
AnnaBridge	143:86740a56073b	398	__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	399	{
AnnaBridge	143:86740a56073b	400	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
AnnaBridge	143:86740a56073b	401	}
AnnaBridge	143:86740a56073b	402
AnnaBridge	143:86740a56073b	403	/**
AnnaBridge	143:86740a56073b	404	* @brief Set clock phase
AnnaBridge	143:86740a56073b	405	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	143:86740a56073b	406	* This bit is not used in SPI TI mode.
AnnaBridge	143:86740a56073b	407	* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
AnnaBridge	143:86740a56073b	408	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	409	* @param ClockPhase This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	410	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	143:86740a56073b	411	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	143:86740a56073b	412	* @retval None
AnnaBridge	143:86740a56073b	413	*/
AnnaBridge	143:86740a56073b	414	__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
AnnaBridge	143:86740a56073b	415	{
AnnaBridge	143:86740a56073b	416	MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
AnnaBridge	143:86740a56073b	417	}
AnnaBridge	143:86740a56073b	418
AnnaBridge	143:86740a56073b	419	/**
AnnaBridge	143:86740a56073b	420	* @brief Get clock phase
AnnaBridge	143:86740a56073b	421	* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
AnnaBridge	143:86740a56073b	422	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	423	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	424	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	143:86740a56073b	425	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	143:86740a56073b	426	*/
AnnaBridge	143:86740a56073b	427	__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	428	{
AnnaBridge	143:86740a56073b	429	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
AnnaBridge	143:86740a56073b	430	}
AnnaBridge	143:86740a56073b	431
AnnaBridge	143:86740a56073b	432	/**
AnnaBridge	143:86740a56073b	433	* @brief Set clock polarity
AnnaBridge	143:86740a56073b	434	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	143:86740a56073b	435	* This bit is not used in SPI TI mode.
AnnaBridge	143:86740a56073b	436	* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
AnnaBridge	143:86740a56073b	437	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	438	* @param ClockPolarity This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	439	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	143:86740a56073b	440	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	143:86740a56073b	441	* @retval None
AnnaBridge	143:86740a56073b	442	*/
AnnaBridge	143:86740a56073b	443	__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge	143:86740a56073b	444	{
AnnaBridge	143:86740a56073b	445	MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
AnnaBridge	143:86740a56073b	446	}
AnnaBridge	143:86740a56073b	447
AnnaBridge	143:86740a56073b	448	/**
AnnaBridge	143:86740a56073b	449	* @brief Get clock polarity
AnnaBridge	143:86740a56073b	450	* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
AnnaBridge	143:86740a56073b	451	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	452	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	453	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	143:86740a56073b	454	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	143:86740a56073b	455	*/
AnnaBridge	143:86740a56073b	456	__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	457	{
AnnaBridge	143:86740a56073b	458	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
AnnaBridge	143:86740a56073b	459	}
AnnaBridge	143:86740a56073b	460
AnnaBridge	143:86740a56073b	461	/**
AnnaBridge	143:86740a56073b	462	* @brief Set baud rate prescaler
AnnaBridge	143:86740a56073b	463	* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
AnnaBridge	143:86740a56073b	464	* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
AnnaBridge	143:86740a56073b	465	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	466	* @param BaudRate This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	467	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	143:86740a56073b	468	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	143:86740a56073b	469	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	143:86740a56073b	470	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	143:86740a56073b	471	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	143:86740a56073b	472	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	143:86740a56073b	473	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	143:86740a56073b	474	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	143:86740a56073b	475	* @retval None
AnnaBridge	143:86740a56073b	476	*/
AnnaBridge	143:86740a56073b	477	__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
AnnaBridge	143:86740a56073b	478	{
AnnaBridge	143:86740a56073b	479	MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
AnnaBridge	143:86740a56073b	480	}
AnnaBridge	143:86740a56073b	481
AnnaBridge	143:86740a56073b	482	/**
AnnaBridge	143:86740a56073b	483	* @brief Get baud rate prescaler
AnnaBridge	143:86740a56073b	484	* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
AnnaBridge	143:86740a56073b	485	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	486	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	487	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	143:86740a56073b	488	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	143:86740a56073b	489	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	143:86740a56073b	490	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	143:86740a56073b	491	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	143:86740a56073b	492	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	143:86740a56073b	493	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	143:86740a56073b	494	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	143:86740a56073b	495	*/
AnnaBridge	143:86740a56073b	496	__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	497	{
AnnaBridge	143:86740a56073b	498	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
AnnaBridge	143:86740a56073b	499	}
AnnaBridge	143:86740a56073b	500
AnnaBridge	143:86740a56073b	501	/**
AnnaBridge	143:86740a56073b	502	* @brief Set transfer bit order
AnnaBridge	143:86740a56073b	503	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	143:86740a56073b	504	* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
AnnaBridge	143:86740a56073b	505	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	506	* @param BitOrder This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	507	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	143:86740a56073b	508	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	143:86740a56073b	509	* @retval None
AnnaBridge	143:86740a56073b	510	*/
AnnaBridge	143:86740a56073b	511	__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
AnnaBridge	143:86740a56073b	512	{
AnnaBridge	143:86740a56073b	513	MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
AnnaBridge	143:86740a56073b	514	}
AnnaBridge	143:86740a56073b	515
AnnaBridge	143:86740a56073b	516	/**
AnnaBridge	143:86740a56073b	517	* @brief Get transfer bit order
AnnaBridge	143:86740a56073b	518	* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
AnnaBridge	143:86740a56073b	519	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	520	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	521	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	143:86740a56073b	522	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	143:86740a56073b	523	*/
AnnaBridge	143:86740a56073b	524	__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	525	{
AnnaBridge	143:86740a56073b	526	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
AnnaBridge	143:86740a56073b	527	}
AnnaBridge	143:86740a56073b	528
AnnaBridge	143:86740a56073b	529	/**
AnnaBridge	143:86740a56073b	530	* @brief Set transfer direction mode
AnnaBridge	143:86740a56073b	531	* @note For Half-Duplex mode, Rx Direction is set by default.
AnnaBridge	143:86740a56073b	532	* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
AnnaBridge	143:86740a56073b	533	* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
AnnaBridge	143:86740a56073b	534	* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
AnnaBridge	143:86740a56073b	535	* CR1 BIDIOE LL_SPI_SetTransferDirection
AnnaBridge	143:86740a56073b	536	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	537	* @param TransferDirection This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	538	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	143:86740a56073b	539	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	143:86740a56073b	540	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	143:86740a56073b	541	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	143:86740a56073b	542	* @retval None
AnnaBridge	143:86740a56073b	543	*/
AnnaBridge	143:86740a56073b	544	__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
AnnaBridge	143:86740a56073b	545	{
AnnaBridge	143:86740a56073b	546	MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE, TransferDirection);
AnnaBridge	143:86740a56073b	547	}
AnnaBridge	143:86740a56073b	548
AnnaBridge	143:86740a56073b	549	/**
AnnaBridge	143:86740a56073b	550	* @brief Get transfer direction mode
AnnaBridge	143:86740a56073b	551	* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
AnnaBridge	143:86740a56073b	552	* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
AnnaBridge	143:86740a56073b	553	* CR1 BIDIOE LL_SPI_GetTransferDirection
AnnaBridge	143:86740a56073b	554	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	555	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	556	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	143:86740a56073b	557	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	143:86740a56073b	558	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	143:86740a56073b	559	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	143:86740a56073b	560	*/
AnnaBridge	143:86740a56073b	561	__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	562	{
AnnaBridge	143:86740a56073b	563	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE));
AnnaBridge	143:86740a56073b	564	}
AnnaBridge	143:86740a56073b	565
AnnaBridge	143:86740a56073b	566	/**
AnnaBridge	143:86740a56073b	567	* @brief Set frame data width
AnnaBridge	143:86740a56073b	568	* @rmtoll CR1 DFF LL_SPI_SetDataWidth
AnnaBridge	143:86740a56073b	569	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	570	* @param DataWidth This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	571	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	143:86740a56073b	572	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	143:86740a56073b	573	* @retval None
AnnaBridge	143:86740a56073b	574	*/
AnnaBridge	143:86740a56073b	575	__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
AnnaBridge	143:86740a56073b	576	{
AnnaBridge	143:86740a56073b	577	MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
AnnaBridge	143:86740a56073b	578	}
AnnaBridge	143:86740a56073b	579
AnnaBridge	143:86740a56073b	580	/**
AnnaBridge	143:86740a56073b	581	* @brief Get frame data width
AnnaBridge	143:86740a56073b	582	* @rmtoll CR1 DFF LL_SPI_GetDataWidth
AnnaBridge	143:86740a56073b	583	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	584	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	585	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	143:86740a56073b	586	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	143:86740a56073b	587	*/
AnnaBridge	143:86740a56073b	588	__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	589	{
AnnaBridge	143:86740a56073b	590	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
AnnaBridge	143:86740a56073b	591	}
AnnaBridge	143:86740a56073b	592
AnnaBridge	143:86740a56073b	593	/**
AnnaBridge	143:86740a56073b	594	* @}
AnnaBridge	143:86740a56073b	595	*/
AnnaBridge	143:86740a56073b	596
AnnaBridge	143:86740a56073b	597	/** @defgroup SPI_LL_EF_CRC_Management CRC Management
AnnaBridge	143:86740a56073b	598	* @{
AnnaBridge	143:86740a56073b	599	*/
AnnaBridge	143:86740a56073b	600
AnnaBridge	143:86740a56073b	601	/**
AnnaBridge	143:86740a56073b	602	* @brief Enable CRC
AnnaBridge	143:86740a56073b	603	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	143:86740a56073b	604	* @rmtoll CR1 CRCEN LL_SPI_EnableCRC
AnnaBridge	143:86740a56073b	605	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	606	* @retval None
AnnaBridge	143:86740a56073b	607	*/
AnnaBridge	143:86740a56073b	608	__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	609	{
AnnaBridge	143:86740a56073b	610	SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge	143:86740a56073b	611	}
AnnaBridge	143:86740a56073b	612
AnnaBridge	143:86740a56073b	613	/**
AnnaBridge	143:86740a56073b	614	* @brief Disable CRC
AnnaBridge	143:86740a56073b	615	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	143:86740a56073b	616	* @rmtoll CR1 CRCEN LL_SPI_DisableCRC
AnnaBridge	143:86740a56073b	617	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	618	* @retval None
AnnaBridge	143:86740a56073b	619	*/
AnnaBridge	143:86740a56073b	620	__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	621	{
AnnaBridge	143:86740a56073b	622	CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge	143:86740a56073b	623	}
AnnaBridge	143:86740a56073b	624
AnnaBridge	143:86740a56073b	625	/**
AnnaBridge	143:86740a56073b	626	* @brief Check if CRC is enabled
AnnaBridge	143:86740a56073b	627	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	143:86740a56073b	628	* @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
AnnaBridge	143:86740a56073b	629	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	630	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	631	*/
AnnaBridge	143:86740a56073b	632	__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	633	{
AnnaBridge	143:86740a56073b	634	return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
AnnaBridge	143:86740a56073b	635	}
AnnaBridge	143:86740a56073b	636
AnnaBridge	143:86740a56073b	637	/**
AnnaBridge	143:86740a56073b	638	* @brief Set CRCNext to transfer CRC on the line
AnnaBridge	143:86740a56073b	639	* @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
AnnaBridge	143:86740a56073b	640	* @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
AnnaBridge	143:86740a56073b	641	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	642	* @retval None
AnnaBridge	143:86740a56073b	643	*/
AnnaBridge	143:86740a56073b	644	__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	645	{
AnnaBridge	143:86740a56073b	646	SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
AnnaBridge	143:86740a56073b	647	}
AnnaBridge	143:86740a56073b	648
AnnaBridge	143:86740a56073b	649	/**
AnnaBridge	143:86740a56073b	650	* @brief Set polynomial for CRC calculation
AnnaBridge	143:86740a56073b	651	* @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
AnnaBridge	143:86740a56073b	652	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	653	* @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	143:86740a56073b	654	* @retval None
AnnaBridge	143:86740a56073b	655	*/
AnnaBridge	143:86740a56073b	656	__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
AnnaBridge	143:86740a56073b	657	{
AnnaBridge	143:86740a56073b	658	WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
AnnaBridge	143:86740a56073b	659	}
AnnaBridge	143:86740a56073b	660
AnnaBridge	143:86740a56073b	661	/**
AnnaBridge	143:86740a56073b	662	* @brief Get polynomial for CRC calculation
AnnaBridge	143:86740a56073b	663	* @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
AnnaBridge	143:86740a56073b	664	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	665	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	143:86740a56073b	666	*/
AnnaBridge	143:86740a56073b	667	__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	668	{
AnnaBridge	143:86740a56073b	669	return (uint32_t)(READ_REG(SPIx->CRCPR));
AnnaBridge	143:86740a56073b	670	}
AnnaBridge	143:86740a56073b	671
AnnaBridge	143:86740a56073b	672	/**
AnnaBridge	143:86740a56073b	673	* @brief Get Rx CRC
AnnaBridge	143:86740a56073b	674	* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
AnnaBridge	143:86740a56073b	675	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	676	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	143:86740a56073b	677	*/
AnnaBridge	143:86740a56073b	678	__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	679	{
AnnaBridge	143:86740a56073b	680	return (uint32_t)(READ_REG(SPIx->RXCRCR));
AnnaBridge	143:86740a56073b	681	}
AnnaBridge	143:86740a56073b	682
AnnaBridge	143:86740a56073b	683	/**
AnnaBridge	143:86740a56073b	684	* @brief Get Tx CRC
AnnaBridge	143:86740a56073b	685	* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
AnnaBridge	143:86740a56073b	686	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	687	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	143:86740a56073b	688	*/
AnnaBridge	143:86740a56073b	689	__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	690	{
AnnaBridge	143:86740a56073b	691	return (uint32_t)(READ_REG(SPIx->TXCRCR));
AnnaBridge	143:86740a56073b	692	}
AnnaBridge	143:86740a56073b	693
AnnaBridge	143:86740a56073b	694	/**
AnnaBridge	143:86740a56073b	695	* @}
AnnaBridge	143:86740a56073b	696	*/
AnnaBridge	143:86740a56073b	697
AnnaBridge	143:86740a56073b	698	/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
AnnaBridge	143:86740a56073b	699	* @{
AnnaBridge	143:86740a56073b	700	*/
AnnaBridge	143:86740a56073b	701
AnnaBridge	143:86740a56073b	702	/**
AnnaBridge	143:86740a56073b	703	* @brief Set NSS mode
AnnaBridge	143:86740a56073b	704	* @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
AnnaBridge	143:86740a56073b	705	* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
AnnaBridge	143:86740a56073b	706	* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
AnnaBridge	143:86740a56073b	707	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	708	* @param NSS This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	709	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	143:86740a56073b	710	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	143:86740a56073b	711	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	143:86740a56073b	712	* @retval None
AnnaBridge	143:86740a56073b	713	*/
AnnaBridge	143:86740a56073b	714	__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
AnnaBridge	143:86740a56073b	715	{
AnnaBridge	143:86740a56073b	716	MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
AnnaBridge	143:86740a56073b	717	MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
AnnaBridge	143:86740a56073b	718	}
AnnaBridge	143:86740a56073b	719
AnnaBridge	143:86740a56073b	720	/**
AnnaBridge	143:86740a56073b	721	* @brief Get NSS mode
AnnaBridge	143:86740a56073b	722	* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
AnnaBridge	143:86740a56073b	723	* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
AnnaBridge	143:86740a56073b	724	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	725	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	726	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	143:86740a56073b	727	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	143:86740a56073b	728	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	143:86740a56073b	729	*/
AnnaBridge	143:86740a56073b	730	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	731	{
AnnaBridge	143:86740a56073b	732	register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
AnnaBridge	143:86740a56073b	733	register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
AnnaBridge	143:86740a56073b	734	return (Ssm \| Ssoe);
AnnaBridge	143:86740a56073b	735	}
AnnaBridge	143:86740a56073b	736
AnnaBridge	143:86740a56073b	737	/**
AnnaBridge	143:86740a56073b	738	* @}
AnnaBridge	143:86740a56073b	739	*/
AnnaBridge	143:86740a56073b	740
AnnaBridge	143:86740a56073b	741	/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
AnnaBridge	143:86740a56073b	742	* @{
AnnaBridge	143:86740a56073b	743	*/
AnnaBridge	143:86740a56073b	744
AnnaBridge	143:86740a56073b	745	/**
AnnaBridge	143:86740a56073b	746	* @brief Check if Rx buffer is not empty
AnnaBridge	143:86740a56073b	747	* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
AnnaBridge	143:86740a56073b	748	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	749	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	750	*/
AnnaBridge	143:86740a56073b	751	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	752	{
AnnaBridge	143:86740a56073b	753	return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
AnnaBridge	143:86740a56073b	754	}
AnnaBridge	143:86740a56073b	755
AnnaBridge	143:86740a56073b	756	/**
AnnaBridge	143:86740a56073b	757	* @brief Check if Tx buffer is empty
AnnaBridge	143:86740a56073b	758	* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
AnnaBridge	143:86740a56073b	759	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	760	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	761	*/
AnnaBridge	143:86740a56073b	762	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	763	{
AnnaBridge	143:86740a56073b	764	return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
AnnaBridge	143:86740a56073b	765	}
AnnaBridge	143:86740a56073b	766
AnnaBridge	143:86740a56073b	767	/**
AnnaBridge	143:86740a56073b	768	* @brief Get CRC error flag
AnnaBridge	143:86740a56073b	769	* @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
AnnaBridge	143:86740a56073b	770	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	771	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	772	*/
AnnaBridge	143:86740a56073b	773	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	774	{
AnnaBridge	143:86740a56073b	775	return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
AnnaBridge	143:86740a56073b	776	}
AnnaBridge	143:86740a56073b	777
AnnaBridge	143:86740a56073b	778	/**
AnnaBridge	143:86740a56073b	779	* @brief Get mode fault error flag
AnnaBridge	143:86740a56073b	780	* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
AnnaBridge	143:86740a56073b	781	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	782	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	783	*/
AnnaBridge	143:86740a56073b	784	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	785	{
AnnaBridge	143:86740a56073b	786	return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
AnnaBridge	143:86740a56073b	787	}
AnnaBridge	143:86740a56073b	788
AnnaBridge	143:86740a56073b	789	/**
AnnaBridge	143:86740a56073b	790	* @brief Get overrun error flag
AnnaBridge	143:86740a56073b	791	* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
AnnaBridge	143:86740a56073b	792	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	793	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	794	*/
AnnaBridge	143:86740a56073b	795	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	796	{
AnnaBridge	143:86740a56073b	797	return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
AnnaBridge	143:86740a56073b	798	}
AnnaBridge	143:86740a56073b	799
AnnaBridge	143:86740a56073b	800	/**
AnnaBridge	143:86740a56073b	801	* @brief Get busy flag
AnnaBridge	143:86740a56073b	802	* @note The BSY flag is cleared under any one of the following conditions:
AnnaBridge	143:86740a56073b	803	* -When the SPI is correctly disabled
AnnaBridge	143:86740a56073b	804	* -When a fault is detected in Master mode (MODF bit set to 1)
AnnaBridge	143:86740a56073b	805	* -In Master mode, when it finishes a data transmission and no new data is ready to be
AnnaBridge	143:86740a56073b	806	* sent
AnnaBridge	143:86740a56073b	807	* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
AnnaBridge	143:86740a56073b	808	* each data transfer.
AnnaBridge	143:86740a56073b	809	* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
AnnaBridge	143:86740a56073b	810	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	811	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	812	*/
AnnaBridge	143:86740a56073b	813	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	814	{
AnnaBridge	143:86740a56073b	815	return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
AnnaBridge	143:86740a56073b	816	}
AnnaBridge	143:86740a56073b	817
AnnaBridge	143:86740a56073b	818	/**
AnnaBridge	143:86740a56073b	819	* @brief Get frame format error flag
AnnaBridge	143:86740a56073b	820	* @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
AnnaBridge	143:86740a56073b	821	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	822	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	823	*/
AnnaBridge	143:86740a56073b	824	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	825	{
AnnaBridge	143:86740a56073b	826	return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
AnnaBridge	143:86740a56073b	827	}
AnnaBridge	143:86740a56073b	828
AnnaBridge	143:86740a56073b	829	/**
AnnaBridge	143:86740a56073b	830	* @brief Clear CRC error flag
AnnaBridge	143:86740a56073b	831	* @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
AnnaBridge	143:86740a56073b	832	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	833	* @retval None
AnnaBridge	143:86740a56073b	834	*/
AnnaBridge	143:86740a56073b	835	__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	836	{
AnnaBridge	143:86740a56073b	837	CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
AnnaBridge	143:86740a56073b	838	}
AnnaBridge	143:86740a56073b	839
AnnaBridge	143:86740a56073b	840	/**
AnnaBridge	143:86740a56073b	841	* @brief Clear mode fault error flag
AnnaBridge	143:86740a56073b	842	* @note Clearing this flag is done by a read access to the SPIx_SR
AnnaBridge	143:86740a56073b	843	* register followed by a write access to the SPIx_CR1 register
AnnaBridge	143:86740a56073b	844	* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
AnnaBridge	143:86740a56073b	845	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	846	* @retval None
AnnaBridge	143:86740a56073b	847	*/
AnnaBridge	143:86740a56073b	848	__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	849	{
AnnaBridge	143:86740a56073b	850	__IO uint32_t tmpreg;
AnnaBridge	143:86740a56073b	851	tmpreg = SPIx->SR;
AnnaBridge	143:86740a56073b	852	(void) tmpreg;
AnnaBridge	143:86740a56073b	853	tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	143:86740a56073b	854	(void) tmpreg;
AnnaBridge	143:86740a56073b	855	}
AnnaBridge	143:86740a56073b	856
AnnaBridge	143:86740a56073b	857	/**
AnnaBridge	143:86740a56073b	858	* @brief Clear overrun error flag
AnnaBridge	143:86740a56073b	859	* @note Clearing this flag is done by a read access to the SPIx_DR
AnnaBridge	143:86740a56073b	860	* register followed by a read access to the SPIx_SR register
AnnaBridge	143:86740a56073b	861	* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
AnnaBridge	143:86740a56073b	862	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	863	* @retval None
AnnaBridge	143:86740a56073b	864	*/
AnnaBridge	143:86740a56073b	865	__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	866	{
AnnaBridge	143:86740a56073b	867	__IO uint32_t tmpreg;
AnnaBridge	143:86740a56073b	868	tmpreg = SPIx->DR;
AnnaBridge	143:86740a56073b	869	(void) tmpreg;
AnnaBridge	143:86740a56073b	870	tmpreg = SPIx->SR;
AnnaBridge	143:86740a56073b	871	(void) tmpreg;
AnnaBridge	143:86740a56073b	872	}
AnnaBridge	143:86740a56073b	873
AnnaBridge	143:86740a56073b	874	/**
AnnaBridge	143:86740a56073b	875	* @brief Clear frame format error flag
AnnaBridge	143:86740a56073b	876	* @note Clearing this flag is done by reading SPIx_SR register
AnnaBridge	143:86740a56073b	877	* @rmtoll SR FRE LL_SPI_ClearFlag_FRE
AnnaBridge	143:86740a56073b	878	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	879	* @retval None
AnnaBridge	143:86740a56073b	880	*/
AnnaBridge	143:86740a56073b	881	__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	882	{
AnnaBridge	143:86740a56073b	883	__IO uint32_t tmpreg;
AnnaBridge	143:86740a56073b	884	tmpreg = SPIx->SR;
AnnaBridge	143:86740a56073b	885	(void) tmpreg;
AnnaBridge	143:86740a56073b	886	}
AnnaBridge	143:86740a56073b	887
AnnaBridge	143:86740a56073b	888	/**
AnnaBridge	143:86740a56073b	889	* @}
AnnaBridge	143:86740a56073b	890	*/
AnnaBridge	143:86740a56073b	891
AnnaBridge	143:86740a56073b	892	/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
AnnaBridge	143:86740a56073b	893	* @{
AnnaBridge	143:86740a56073b	894	*/
AnnaBridge	143:86740a56073b	895
AnnaBridge	143:86740a56073b	896	/**
AnnaBridge	143:86740a56073b	897	* @brief Enable error interrupt
AnnaBridge	143:86740a56073b	898	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge	143:86740a56073b	899	* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
AnnaBridge	143:86740a56073b	900	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	901	* @retval None
AnnaBridge	143:86740a56073b	902	*/
AnnaBridge	143:86740a56073b	903	__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	904	{
AnnaBridge	143:86740a56073b	905	SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge	143:86740a56073b	906	}
AnnaBridge	143:86740a56073b	907
AnnaBridge	143:86740a56073b	908	/**
AnnaBridge	143:86740a56073b	909	* @brief Enable Rx buffer not empty interrupt
AnnaBridge	143:86740a56073b	910	* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
AnnaBridge	143:86740a56073b	911	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	912	* @retval None
AnnaBridge	143:86740a56073b	913	*/
AnnaBridge	143:86740a56073b	914	__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	915	{
AnnaBridge	143:86740a56073b	916	SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge	143:86740a56073b	917	}
AnnaBridge	143:86740a56073b	918
AnnaBridge	143:86740a56073b	919	/**
AnnaBridge	143:86740a56073b	920	* @brief Enable Tx buffer empty interrupt
AnnaBridge	143:86740a56073b	921	* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
AnnaBridge	143:86740a56073b	922	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	923	* @retval None
AnnaBridge	143:86740a56073b	924	*/
AnnaBridge	143:86740a56073b	925	__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	926	{
AnnaBridge	143:86740a56073b	927	SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge	143:86740a56073b	928	}
AnnaBridge	143:86740a56073b	929
AnnaBridge	143:86740a56073b	930	/**
AnnaBridge	143:86740a56073b	931	* @brief Disable error interrupt
AnnaBridge	143:86740a56073b	932	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge	143:86740a56073b	933	* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
AnnaBridge	143:86740a56073b	934	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	935	* @retval None
AnnaBridge	143:86740a56073b	936	*/
AnnaBridge	143:86740a56073b	937	__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	938	{
AnnaBridge	143:86740a56073b	939	CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge	143:86740a56073b	940	}
AnnaBridge	143:86740a56073b	941
AnnaBridge	143:86740a56073b	942	/**
AnnaBridge	143:86740a56073b	943	* @brief Disable Rx buffer not empty interrupt
AnnaBridge	143:86740a56073b	944	* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
AnnaBridge	143:86740a56073b	945	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	946	* @retval None
AnnaBridge	143:86740a56073b	947	*/
AnnaBridge	143:86740a56073b	948	__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	949	{
AnnaBridge	143:86740a56073b	950	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge	143:86740a56073b	951	}
AnnaBridge	143:86740a56073b	952
AnnaBridge	143:86740a56073b	953	/**
AnnaBridge	143:86740a56073b	954	* @brief Disable Tx buffer empty interrupt
AnnaBridge	143:86740a56073b	955	* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
AnnaBridge	143:86740a56073b	956	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	957	* @retval None
AnnaBridge	143:86740a56073b	958	*/
AnnaBridge	143:86740a56073b	959	__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	960	{
AnnaBridge	143:86740a56073b	961	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge	143:86740a56073b	962	}
AnnaBridge	143:86740a56073b	963
AnnaBridge	143:86740a56073b	964	/**
AnnaBridge	143:86740a56073b	965	* @brief Check if error interrupt is enabled
AnnaBridge	143:86740a56073b	966	* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
AnnaBridge	143:86740a56073b	967	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	968	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	969	*/
AnnaBridge	143:86740a56073b	970	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	971	{
AnnaBridge	143:86740a56073b	972	return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
AnnaBridge	143:86740a56073b	973	}
AnnaBridge	143:86740a56073b	974
AnnaBridge	143:86740a56073b	975	/**
AnnaBridge	143:86740a56073b	976	* @brief Check if Rx buffer not empty interrupt is enabled
AnnaBridge	143:86740a56073b	977	* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
AnnaBridge	143:86740a56073b	978	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	979	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	980	*/
AnnaBridge	143:86740a56073b	981	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	982	{
AnnaBridge	143:86740a56073b	983	return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
AnnaBridge	143:86740a56073b	984	}
AnnaBridge	143:86740a56073b	985
AnnaBridge	143:86740a56073b	986	/**
AnnaBridge	143:86740a56073b	987	* @brief Check if Tx buffer empty interrupt
AnnaBridge	143:86740a56073b	988	* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
AnnaBridge	143:86740a56073b	989	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	990	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	991	*/
AnnaBridge	143:86740a56073b	992	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	993	{
AnnaBridge	143:86740a56073b	994	return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
AnnaBridge	143:86740a56073b	995	}
AnnaBridge	143:86740a56073b	996
AnnaBridge	143:86740a56073b	997	/**
AnnaBridge	143:86740a56073b	998	* @}
AnnaBridge	143:86740a56073b	999	*/
AnnaBridge	143:86740a56073b	1000
AnnaBridge	143:86740a56073b	1001	/** @defgroup SPI_LL_EF_DMA_Management DMA Management
AnnaBridge	143:86740a56073b	1002	* @{
AnnaBridge	143:86740a56073b	1003	*/
AnnaBridge	143:86740a56073b	1004
AnnaBridge	143:86740a56073b	1005	/**
AnnaBridge	143:86740a56073b	1006	* @brief Enable DMA Rx
AnnaBridge	143:86740a56073b	1007	* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
AnnaBridge	143:86740a56073b	1008	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1009	* @retval None
AnnaBridge	143:86740a56073b	1010	*/
AnnaBridge	143:86740a56073b	1011	__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1012	{
AnnaBridge	143:86740a56073b	1013	SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	143:86740a56073b	1014	}
AnnaBridge	143:86740a56073b	1015
AnnaBridge	143:86740a56073b	1016	/**
AnnaBridge	143:86740a56073b	1017	* @brief Disable DMA Rx
AnnaBridge	143:86740a56073b	1018	* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
AnnaBridge	143:86740a56073b	1019	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1020	* @retval None
AnnaBridge	143:86740a56073b	1021	*/
AnnaBridge	143:86740a56073b	1022	__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1023	{
AnnaBridge	143:86740a56073b	1024	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	143:86740a56073b	1025	}
AnnaBridge	143:86740a56073b	1026
AnnaBridge	143:86740a56073b	1027	/**
AnnaBridge	143:86740a56073b	1028	* @brief Check if DMA Rx is enabled
AnnaBridge	143:86740a56073b	1029	* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
AnnaBridge	143:86740a56073b	1030	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1031	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1032	*/
AnnaBridge	143:86740a56073b	1033	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1034	{
AnnaBridge	143:86740a56073b	1035	return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
AnnaBridge	143:86740a56073b	1036	}
AnnaBridge	143:86740a56073b	1037
AnnaBridge	143:86740a56073b	1038	/**
AnnaBridge	143:86740a56073b	1039	* @brief Enable DMA Tx
AnnaBridge	143:86740a56073b	1040	* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
AnnaBridge	143:86740a56073b	1041	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1042	* @retval None
AnnaBridge	143:86740a56073b	1043	*/
AnnaBridge	143:86740a56073b	1044	__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1045	{
AnnaBridge	143:86740a56073b	1046	SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge	143:86740a56073b	1047	}
AnnaBridge	143:86740a56073b	1048
AnnaBridge	143:86740a56073b	1049	/**
AnnaBridge	143:86740a56073b	1050	* @brief Disable DMA Tx
AnnaBridge	143:86740a56073b	1051	* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
AnnaBridge	143:86740a56073b	1052	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1053	* @retval None
AnnaBridge	143:86740a56073b	1054	*/
AnnaBridge	143:86740a56073b	1055	__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1056	{
AnnaBridge	143:86740a56073b	1057	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge	143:86740a56073b	1058	}
AnnaBridge	143:86740a56073b	1059
AnnaBridge	143:86740a56073b	1060	/**
AnnaBridge	143:86740a56073b	1061	* @brief Check if DMA Tx is enabled
AnnaBridge	143:86740a56073b	1062	* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
AnnaBridge	143:86740a56073b	1063	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1064	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1065	*/
AnnaBridge	143:86740a56073b	1066	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1067	{
AnnaBridge	143:86740a56073b	1068	return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
AnnaBridge	143:86740a56073b	1069	}
AnnaBridge	143:86740a56073b	1070
AnnaBridge	143:86740a56073b	1071	/**
AnnaBridge	143:86740a56073b	1072	* @brief Get the data register address used for DMA transfer
AnnaBridge	143:86740a56073b	1073	* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
AnnaBridge	143:86740a56073b	1074	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1075	* @retval Address of data register
AnnaBridge	143:86740a56073b	1076	*/
AnnaBridge	143:86740a56073b	1077	__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1078	{
AnnaBridge	143:86740a56073b	1079	return (uint32_t) & (SPIx->DR);
AnnaBridge	143:86740a56073b	1080	}
AnnaBridge	143:86740a56073b	1081
AnnaBridge	143:86740a56073b	1082	/**
AnnaBridge	143:86740a56073b	1083	* @}
AnnaBridge	143:86740a56073b	1084	*/
AnnaBridge	143:86740a56073b	1085
AnnaBridge	143:86740a56073b	1086	/** @defgroup SPI_LL_EF_DATA_Management DATA Management
AnnaBridge	143:86740a56073b	1087	* @{
AnnaBridge	143:86740a56073b	1088	*/
AnnaBridge	143:86740a56073b	1089
AnnaBridge	143:86740a56073b	1090	/**
AnnaBridge	143:86740a56073b	1091	* @brief Read 8-Bits in the data register
AnnaBridge	143:86740a56073b	1092	* @rmtoll DR DR LL_SPI_ReceiveData8
AnnaBridge	143:86740a56073b	1093	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1094	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	143:86740a56073b	1095	*/
AnnaBridge	143:86740a56073b	1096	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1097	{
AnnaBridge	143:86740a56073b	1098	return (uint8_t)(READ_REG(SPIx->DR));
AnnaBridge	143:86740a56073b	1099	}
AnnaBridge	143:86740a56073b	1100
AnnaBridge	143:86740a56073b	1101	/**
AnnaBridge	143:86740a56073b	1102	* @brief Read 16-Bits in the data register
AnnaBridge	143:86740a56073b	1103	* @rmtoll DR DR LL_SPI_ReceiveData16
AnnaBridge	143:86740a56073b	1104	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1105	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	143:86740a56073b	1106	*/
AnnaBridge	143:86740a56073b	1107	__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1108	{
AnnaBridge	143:86740a56073b	1109	return (uint16_t)(READ_REG(SPIx->DR));
AnnaBridge	143:86740a56073b	1110	}
AnnaBridge	143:86740a56073b	1111
AnnaBridge	143:86740a56073b	1112	/**
AnnaBridge	143:86740a56073b	1113	* @brief Write 8-Bits in the data register
AnnaBridge	143:86740a56073b	1114	* @rmtoll DR DR LL_SPI_TransmitData8
AnnaBridge	143:86740a56073b	1115	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1116	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	143:86740a56073b	1117	* @retval None
AnnaBridge	143:86740a56073b	1118	*/
AnnaBridge	143:86740a56073b	1119	__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
AnnaBridge	143:86740a56073b	1120	{
AnnaBridge	143:86740a56073b	1121	((__IO uint8_t )&SPIx->DR) = TxData;
AnnaBridge	143:86740a56073b	1122	}
AnnaBridge	143:86740a56073b	1123
AnnaBridge	143:86740a56073b	1124	/**
AnnaBridge	143:86740a56073b	1125	* @brief Write 16-Bits in the data register
AnnaBridge	143:86740a56073b	1126	* @rmtoll DR DR LL_SPI_TransmitData16
AnnaBridge	143:86740a56073b	1127	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1128	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	143:86740a56073b	1129	* @retval None
AnnaBridge	143:86740a56073b	1130	*/
AnnaBridge	143:86740a56073b	1131	__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge	143:86740a56073b	1132	{
AnnaBridge	143:86740a56073b	1133	((__IO uint16_t )&SPIx->DR) = TxData;
AnnaBridge	143:86740a56073b	1134	}
AnnaBridge	143:86740a56073b	1135
AnnaBridge	143:86740a56073b	1136	/**
AnnaBridge	143:86740a56073b	1137	* @}
AnnaBridge	143:86740a56073b	1138	*/
AnnaBridge	143:86740a56073b	1139	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	143:86740a56073b	1140	/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	143:86740a56073b	1141	* @{
AnnaBridge	143:86740a56073b	1142	*/
AnnaBridge	143:86740a56073b	1143
AnnaBridge	143:86740a56073b	1144	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
AnnaBridge	143:86740a56073b	1145	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct);
AnnaBridge	143:86740a56073b	1146	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
AnnaBridge	143:86740a56073b	1147
AnnaBridge	143:86740a56073b	1148	/**
AnnaBridge	143:86740a56073b	1149	* @}
AnnaBridge	143:86740a56073b	1150	*/
AnnaBridge	143:86740a56073b	1151	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	143:86740a56073b	1152	/**
AnnaBridge	143:86740a56073b	1153	* @}
AnnaBridge	143:86740a56073b	1154	*/
AnnaBridge	143:86740a56073b	1155
AnnaBridge	143:86740a56073b	1156	/**
AnnaBridge	143:86740a56073b	1157	* @}
AnnaBridge	143:86740a56073b	1158	*/
AnnaBridge	143:86740a56073b	1159
AnnaBridge	143:86740a56073b	1160	#if defined(SPI_I2S_SUPPORT)
AnnaBridge	143:86740a56073b	1161	/** @defgroup I2S_LL I2S
AnnaBridge	143:86740a56073b	1162	* @{
AnnaBridge	143:86740a56073b	1163	*/
AnnaBridge	143:86740a56073b	1164
AnnaBridge	143:86740a56073b	1165	/* Private variables ---------------------------------------------------------*/
AnnaBridge	143:86740a56073b	1166	/* Private constants ---------------------------------------------------------*/
AnnaBridge	143:86740a56073b	1167	/* Private macros ------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	1168
AnnaBridge	143:86740a56073b	1169	/* Exported types ------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	1170	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	143:86740a56073b	1171	/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
AnnaBridge	143:86740a56073b	1172	* @{
AnnaBridge	143:86740a56073b	1173	*/
AnnaBridge	143:86740a56073b	1174
AnnaBridge	143:86740a56073b	1175	/**
AnnaBridge	143:86740a56073b	1176	* @brief I2S Init structure definition
AnnaBridge	143:86740a56073b	1177	*/
AnnaBridge	143:86740a56073b	1178
AnnaBridge	143:86740a56073b	1179	typedef struct
AnnaBridge	143:86740a56073b	1180	{
AnnaBridge	143:86740a56073b	1181	uint32_t Mode; /*!< Specifies the I2S operating mode.
AnnaBridge	143:86740a56073b	1182	This parameter can be a value of @ref I2S_LL_EC_MODE
AnnaBridge	143:86740a56073b	1183
AnnaBridge	143:86740a56073b	1184	This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
AnnaBridge	143:86740a56073b	1185
AnnaBridge	143:86740a56073b	1186	uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
AnnaBridge	143:86740a56073b	1187	This parameter can be a value of @ref I2S_LL_EC_STANDARD
AnnaBridge	143:86740a56073b	1188
AnnaBridge	143:86740a56073b	1189	This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
AnnaBridge	143:86740a56073b	1190
AnnaBridge	143:86740a56073b	1191
AnnaBridge	143:86740a56073b	1192	uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
AnnaBridge	143:86740a56073b	1193	This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
AnnaBridge	143:86740a56073b	1194
AnnaBridge	143:86740a56073b	1195	This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
AnnaBridge	143:86740a56073b	1196
AnnaBridge	143:86740a56073b	1197
AnnaBridge	143:86740a56073b	1198	uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
AnnaBridge	143:86740a56073b	1199	This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
AnnaBridge	143:86740a56073b	1200
AnnaBridge	143:86740a56073b	1201	This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
AnnaBridge	143:86740a56073b	1202
AnnaBridge	143:86740a56073b	1203
AnnaBridge	143:86740a56073b	1204	uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
AnnaBridge	143:86740a56073b	1205	This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
AnnaBridge	143:86740a56073b	1206
AnnaBridge	143:86740a56073b	1207	Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
AnnaBridge	143:86740a56073b	1208	and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
AnnaBridge	143:86740a56073b	1209
AnnaBridge	143:86740a56073b	1210
AnnaBridge	143:86740a56073b	1211	uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
AnnaBridge	143:86740a56073b	1212	This parameter can be a value of @ref I2S_LL_EC_POLARITY
AnnaBridge	143:86740a56073b	1213
AnnaBridge	143:86740a56073b	1214	This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
AnnaBridge	143:86740a56073b	1215
AnnaBridge	143:86740a56073b	1216	} LL_I2S_InitTypeDef;
AnnaBridge	143:86740a56073b	1217
AnnaBridge	143:86740a56073b	1218	/**
AnnaBridge	143:86740a56073b	1219	* @}
AnnaBridge	143:86740a56073b	1220	*/
AnnaBridge	143:86740a56073b	1221	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	143:86740a56073b	1222
AnnaBridge	143:86740a56073b	1223	/* Exported constants --------------------------------------------------------*/
AnnaBridge	143:86740a56073b	1224	/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
AnnaBridge	143:86740a56073b	1225	* @{
AnnaBridge	143:86740a56073b	1226	*/
AnnaBridge	143:86740a56073b	1227
AnnaBridge	143:86740a56073b	1228	/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	143:86740a56073b	1229	* @brief Flags defines which can be used with LL_I2S_ReadReg function
AnnaBridge	143:86740a56073b	1230	* @{
AnnaBridge	143:86740a56073b	1231	*/
AnnaBridge	143:86740a56073b	1232	#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /!< Rx buffer not empty flag /
AnnaBridge	143:86740a56073b	1233	#define LL_I2S_SR_TXE LL_SPI_SR_TXE /!< Tx buffer empty flag /
AnnaBridge	143:86740a56073b	1234	#define LL_I2S_SR_BSY LL_SPI_SR_BSY /!< Busy flag /
AnnaBridge	143:86740a56073b	1235	#define LL_I2S_SR_UDR LL_SPI_SR_UDR /!< Underrun flag /
AnnaBridge	143:86740a56073b	1236	#define LL_I2S_SR_OVR LL_SPI_SR_OVR /!< Overrun flag /
AnnaBridge	143:86740a56073b	1237	#define LL_I2S_SR_FRE LL_SPI_SR_FRE /!< TI mode frame format error flag /
AnnaBridge	143:86740a56073b	1238	/**
AnnaBridge	143:86740a56073b	1239	* @}
AnnaBridge	143:86740a56073b	1240	*/
AnnaBridge	143:86740a56073b	1241
AnnaBridge	143:86740a56073b	1242	/** @defgroup SPI_LL_EC_IT IT Defines
AnnaBridge	143:86740a56073b	1243	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
AnnaBridge	143:86740a56073b	1244	* @{
AnnaBridge	143:86740a56073b	1245	*/
AnnaBridge	143:86740a56073b	1246	#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
AnnaBridge	143:86740a56073b	1247	#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
AnnaBridge	143:86740a56073b	1248	#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /!< Error interrupt enable /
AnnaBridge	143:86740a56073b	1249	/**
AnnaBridge	143:86740a56073b	1250	* @}
AnnaBridge	143:86740a56073b	1251	*/
AnnaBridge	143:86740a56073b	1252
AnnaBridge	143:86740a56073b	1253	/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
AnnaBridge	143:86740a56073b	1254	* @{
AnnaBridge	143:86740a56073b	1255	*/
AnnaBridge	143:86740a56073b	1256	#define LL_I2S_DATAFORMAT_16B ((uint32_t)0x00000000U) /!< Data length 16 bits, Channel lenght 16bit /
AnnaBridge	143:86740a56073b	1257	#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /!< Data length 16 bits, Channel lenght 32bit /
AnnaBridge	143:86740a56073b	1258	#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_0) /!< Data length 24 bits, Channel lenght 32bit /
AnnaBridge	143:86740a56073b	1259	#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_1) /!< Data length 16 bits, Channel lenght 32bit /
AnnaBridge	143:86740a56073b	1260	/**
AnnaBridge	143:86740a56073b	1261	* @}
AnnaBridge	143:86740a56073b	1262	*/
AnnaBridge	143:86740a56073b	1263
AnnaBridge	143:86740a56073b	1264	/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
AnnaBridge	143:86740a56073b	1265	* @{
AnnaBridge	143:86740a56073b	1266	*/
AnnaBridge	143:86740a56073b	1267	#define LL_I2S_POLARITY_LOW ((uint32_t)0x00000000U) /!< Clock steady state is low level /
AnnaBridge	143:86740a56073b	1268	#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /!< Clock steady state is high level /
AnnaBridge	143:86740a56073b	1269	/**
AnnaBridge	143:86740a56073b	1270	* @}
AnnaBridge	143:86740a56073b	1271	*/
AnnaBridge	143:86740a56073b	1272
AnnaBridge	143:86740a56073b	1273	/** @defgroup I2S_LL_EC_STANDARD I2s Standard
AnnaBridge	143:86740a56073b	1274	* @{
AnnaBridge	143:86740a56073b	1275	*/
AnnaBridge	143:86740a56073b	1276	#define LL_I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U) /!< I2S standard philips /
AnnaBridge	143:86740a56073b	1277	#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /!< MSB justified standard (left justified) /
AnnaBridge	143:86740a56073b	1278	#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /!< LSB justified standard (right justified) /
AnnaBridge	143:86740a56073b	1279	#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1) /!< PCM standard, short frame synchronization /
AnnaBridge	143:86740a56073b	1280	#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1 \| SPI_I2SCFGR_PCMSYNC) /!< PCM standard, long frame synchronization /
AnnaBridge	143:86740a56073b	1281	/**
AnnaBridge	143:86740a56073b	1282	* @}
AnnaBridge	143:86740a56073b	1283	*/
AnnaBridge	143:86740a56073b	1284
AnnaBridge	143:86740a56073b	1285	/** @defgroup I2S_LL_EC_MODE Operation Mode
AnnaBridge	143:86740a56073b	1286	* @{
AnnaBridge	143:86740a56073b	1287	*/
AnnaBridge	143:86740a56073b	1288	#define LL_I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U) /!< Slave Tx configuration /
AnnaBridge	143:86740a56073b	1289	#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /!< Slave Rx configuration /
AnnaBridge	143:86740a56073b	1290	#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /!< Master Tx configuration /
AnnaBridge	143:86740a56073b	1291	#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 \| SPI_I2SCFGR_I2SCFG_1) /!< Master Rx configuration /
AnnaBridge	143:86740a56073b	1292	/**
AnnaBridge	143:86740a56073b	1293	* @}
AnnaBridge	143:86740a56073b	1294	*/
AnnaBridge	143:86740a56073b	1295
AnnaBridge	143:86740a56073b	1296	/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
AnnaBridge	143:86740a56073b	1297	* @{
AnnaBridge	143:86740a56073b	1298	*/
AnnaBridge	143:86740a56073b	1299	#define LL_I2S_PRESCALER_PARITY_EVEN ((uint32_t)0x00000000U) /!< Odd factor: Real divider value is = I2SDIV 2 */
AnnaBridge	143:86740a56073b	1300	#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /!< Odd factor: Real divider value is = (I2SDIV 2)+1 */
AnnaBridge	143:86740a56073b	1301	/**
AnnaBridge	143:86740a56073b	1302	* @}
AnnaBridge	143:86740a56073b	1303	*/
AnnaBridge	143:86740a56073b	1304
AnnaBridge	143:86740a56073b	1305	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	143:86740a56073b	1306
AnnaBridge	143:86740a56073b	1307	/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
AnnaBridge	143:86740a56073b	1308	* @{
AnnaBridge	143:86740a56073b	1309	*/
AnnaBridge	143:86740a56073b	1310	#define LL_I2S_MCLK_OUTPUT_DISABLE ((uint32_t)0x00000000U) /!< Master clock output is disabled /
AnnaBridge	143:86740a56073b	1311	#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /!< Master clock output is enabled /
AnnaBridge	143:86740a56073b	1312	/**
AnnaBridge	143:86740a56073b	1313	* @}
AnnaBridge	143:86740a56073b	1314	*/
AnnaBridge	143:86740a56073b	1315
AnnaBridge	143:86740a56073b	1316	/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
AnnaBridge	143:86740a56073b	1317	* @{
AnnaBridge	143:86740a56073b	1318	*/
AnnaBridge	143:86740a56073b	1319
AnnaBridge	143:86740a56073b	1320	#define LL_I2S_AUDIOFREQ_192K ((uint32_t)192000) /!< Audio Frequency configuration 192000 Hz /
AnnaBridge	143:86740a56073b	1321	#define LL_I2S_AUDIOFREQ_96K ((uint32_t) 96000) /!< Audio Frequency configuration 96000 Hz /
AnnaBridge	143:86740a56073b	1322	#define LL_I2S_AUDIOFREQ_48K ((uint32_t) 48000) /!< Audio Frequency configuration 48000 Hz /
AnnaBridge	143:86740a56073b	1323	#define LL_I2S_AUDIOFREQ_44K ((uint32_t) 44100) /!< Audio Frequency configuration 44100 Hz /
AnnaBridge	143:86740a56073b	1324	#define LL_I2S_AUDIOFREQ_32K ((uint32_t) 32000) /!< Audio Frequency configuration 32000 Hz /
AnnaBridge	143:86740a56073b	1325	#define LL_I2S_AUDIOFREQ_22K ((uint32_t) 22050) /!< Audio Frequency configuration 22050 Hz /
AnnaBridge	143:86740a56073b	1326	#define LL_I2S_AUDIOFREQ_16K ((uint32_t) 16000) /!< Audio Frequency configuration 16000 Hz /
AnnaBridge	143:86740a56073b	1327	#define LL_I2S_AUDIOFREQ_11K ((uint32_t) 11025) /!< Audio Frequency configuration 11025 Hz /
AnnaBridge	143:86740a56073b	1328	#define LL_I2S_AUDIOFREQ_8K ((uint32_t) 8000) /!< Audio Frequency configuration 8000 Hz /
AnnaBridge	143:86740a56073b	1329	#define LL_I2S_AUDIOFREQ_DEFAULT ((uint32_t) 2) /!< Audio Freq not specified. Register I2SDIV = 2 /
AnnaBridge	143:86740a56073b	1330	/**
AnnaBridge	143:86740a56073b	1331	* @}
AnnaBridge	143:86740a56073b	1332	*/
AnnaBridge	143:86740a56073b	1333	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	143:86740a56073b	1334
AnnaBridge	143:86740a56073b	1335	/**
AnnaBridge	143:86740a56073b	1336	* @}
AnnaBridge	143:86740a56073b	1337	*/
AnnaBridge	143:86740a56073b	1338
AnnaBridge	143:86740a56073b	1339	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	1340	/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
AnnaBridge	143:86740a56073b	1341	* @{
AnnaBridge	143:86740a56073b	1342	*/
AnnaBridge	143:86740a56073b	1343
AnnaBridge	143:86740a56073b	1344	/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	143:86740a56073b	1345	* @{
AnnaBridge	143:86740a56073b	1346	*/
AnnaBridge	143:86740a56073b	1347
AnnaBridge	143:86740a56073b	1348	/**
AnnaBridge	143:86740a56073b	1349	* @brief Write a value in I2S register
AnnaBridge	143:86740a56073b	1350	* @param __INSTANCE__ I2S Instance
AnnaBridge	143:86740a56073b	1351	* @param __REG__ Register to be written
AnnaBridge	143:86740a56073b	1352	* @param __VALUE__ Value to be written in the register
AnnaBridge	143:86740a56073b	1353	* @retval None
AnnaBridge	143:86740a56073b	1354	*/
AnnaBridge	143:86740a56073b	1355	#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	143:86740a56073b	1356
AnnaBridge	143:86740a56073b	1357	/**
AnnaBridge	143:86740a56073b	1358	* @brief Read a value in I2S register
AnnaBridge	143:86740a56073b	1359	* @param __INSTANCE__ I2S Instance
AnnaBridge	143:86740a56073b	1360	* @param __REG__ Register to be read
AnnaBridge	143:86740a56073b	1361	* @retval Register value
AnnaBridge	143:86740a56073b	1362	*/
AnnaBridge	143:86740a56073b	1363	#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	143:86740a56073b	1364	/**
AnnaBridge	143:86740a56073b	1365	* @}
AnnaBridge	143:86740a56073b	1366	*/
AnnaBridge	143:86740a56073b	1367
AnnaBridge	143:86740a56073b	1368	/**
AnnaBridge	143:86740a56073b	1369	* @}
AnnaBridge	143:86740a56073b	1370	*/
AnnaBridge	143:86740a56073b	1371
AnnaBridge	143:86740a56073b	1372
AnnaBridge	143:86740a56073b	1373	/* Exported functions --------------------------------------------------------*/
AnnaBridge	143:86740a56073b	1374
AnnaBridge	143:86740a56073b	1375	/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
AnnaBridge	143:86740a56073b	1376	* @{
AnnaBridge	143:86740a56073b	1377	*/
AnnaBridge	143:86740a56073b	1378
AnnaBridge	143:86740a56073b	1379	/** @defgroup I2S_LL_EF_Configuration Configuration
AnnaBridge	143:86740a56073b	1380	* @{
AnnaBridge	143:86740a56073b	1381	*/
AnnaBridge	143:86740a56073b	1382
AnnaBridge	143:86740a56073b	1383	/**
AnnaBridge	143:86740a56073b	1384	* @brief Select I2S mode and Enable I2S peripheral
AnnaBridge	143:86740a56073b	1385	* @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
AnnaBridge	143:86740a56073b	1386	* I2SCFGR I2SE LL_I2S_Enable
AnnaBridge	143:86740a56073b	1387	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1388	* @retval None
AnnaBridge	143:86740a56073b	1389	*/
AnnaBridge	143:86740a56073b	1390	__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1391	{
AnnaBridge	143:86740a56073b	1392	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
AnnaBridge	143:86740a56073b	1393	}
AnnaBridge	143:86740a56073b	1394
AnnaBridge	143:86740a56073b	1395	/**
AnnaBridge	143:86740a56073b	1396	* @brief Disable I2S peripheral
AnnaBridge	143:86740a56073b	1397	* @rmtoll I2SCFGR I2SE LL_I2S_Disable
AnnaBridge	143:86740a56073b	1398	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1399	* @retval None
AnnaBridge	143:86740a56073b	1400	*/
AnnaBridge	143:86740a56073b	1401	__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1402	{
AnnaBridge	143:86740a56073b	1403	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
AnnaBridge	143:86740a56073b	1404	}
AnnaBridge	143:86740a56073b	1405
AnnaBridge	143:86740a56073b	1406	/**
AnnaBridge	143:86740a56073b	1407	* @brief Check if I2S peripheral is enabled
AnnaBridge	143:86740a56073b	1408	* @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
AnnaBridge	143:86740a56073b	1409	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1410	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1411	*/
AnnaBridge	143:86740a56073b	1412	__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1413	{
AnnaBridge	143:86740a56073b	1414	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
AnnaBridge	143:86740a56073b	1415	}
AnnaBridge	143:86740a56073b	1416
AnnaBridge	143:86740a56073b	1417	/**
AnnaBridge	143:86740a56073b	1418	* @brief Set I2S Data frame length
AnnaBridge	143:86740a56073b	1419	* @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
AnnaBridge	143:86740a56073b	1420	* I2SCFGR CHLEN LL_I2S_SetDataFormat
AnnaBridge	143:86740a56073b	1421	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1422	* @param DataFormat This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1423	* @arg @ref LL_I2S_DATAFORMAT_16B
AnnaBridge	143:86740a56073b	1424	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
AnnaBridge	143:86740a56073b	1425	* @arg @ref LL_I2S_DATAFORMAT_24B
AnnaBridge	143:86740a56073b	1426	* @arg @ref LL_I2S_DATAFORMAT_32B
AnnaBridge	143:86740a56073b	1427	* @retval None
AnnaBridge	143:86740a56073b	1428	*/
AnnaBridge	143:86740a56073b	1429	__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
AnnaBridge	143:86740a56073b	1430	{
AnnaBridge	143:86740a56073b	1431	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN, DataFormat);
AnnaBridge	143:86740a56073b	1432	}
AnnaBridge	143:86740a56073b	1433
AnnaBridge	143:86740a56073b	1434	/**
AnnaBridge	143:86740a56073b	1435	* @brief Get I2S Data frame length
AnnaBridge	143:86740a56073b	1436	* @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
AnnaBridge	143:86740a56073b	1437	* I2SCFGR CHLEN LL_I2S_GetDataFormat
AnnaBridge	143:86740a56073b	1438	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1439	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	1440	* @arg @ref LL_I2S_DATAFORMAT_16B
AnnaBridge	143:86740a56073b	1441	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
AnnaBridge	143:86740a56073b	1442	* @arg @ref LL_I2S_DATAFORMAT_24B
AnnaBridge	143:86740a56073b	1443	* @arg @ref LL_I2S_DATAFORMAT_32B
AnnaBridge	143:86740a56073b	1444	*/
AnnaBridge	143:86740a56073b	1445	__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1446	{
AnnaBridge	143:86740a56073b	1447	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN));
AnnaBridge	143:86740a56073b	1448	}
AnnaBridge	143:86740a56073b	1449
AnnaBridge	143:86740a56073b	1450	/**
AnnaBridge	143:86740a56073b	1451	* @brief Set I2S clock polarity
AnnaBridge	143:86740a56073b	1452	* @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
AnnaBridge	143:86740a56073b	1453	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1454	* @param ClockPolarity This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1455	* @arg @ref LL_I2S_POLARITY_LOW
AnnaBridge	143:86740a56073b	1456	* @arg @ref LL_I2S_POLARITY_HIGH
AnnaBridge	143:86740a56073b	1457	* @retval None
AnnaBridge	143:86740a56073b	1458	*/
AnnaBridge	143:86740a56073b	1459	__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge	143:86740a56073b	1460	{
AnnaBridge	143:86740a56073b	1461	SET_BIT(SPIx->I2SCFGR, ClockPolarity);
AnnaBridge	143:86740a56073b	1462	}
AnnaBridge	143:86740a56073b	1463
AnnaBridge	143:86740a56073b	1464	/**
AnnaBridge	143:86740a56073b	1465	* @brief Get I2S clock polarity
AnnaBridge	143:86740a56073b	1466	* @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
AnnaBridge	143:86740a56073b	1467	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1468	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	1469	* @arg @ref LL_I2S_POLARITY_LOW
AnnaBridge	143:86740a56073b	1470	* @arg @ref LL_I2S_POLARITY_HIGH
AnnaBridge	143:86740a56073b	1471	*/
AnnaBridge	143:86740a56073b	1472	__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1473	{
AnnaBridge	143:86740a56073b	1474	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
AnnaBridge	143:86740a56073b	1475	}
AnnaBridge	143:86740a56073b	1476
AnnaBridge	143:86740a56073b	1477	/**
AnnaBridge	143:86740a56073b	1478	* @brief Set I2S Standard Protocol
AnnaBridge	143:86740a56073b	1479	* @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
AnnaBridge	143:86740a56073b	1480	* I2SCFGR PCMSYNC LL_I2S_SetStandard
AnnaBridge	143:86740a56073b	1481	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1482	* @param Standard This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1483	* @arg @ref LL_I2S_STANDARD_PHILIPS
AnnaBridge	143:86740a56073b	1484	* @arg @ref LL_I2S_STANDARD_MSB
AnnaBridge	143:86740a56073b	1485	* @arg @ref LL_I2S_STANDARD_LSB
AnnaBridge	143:86740a56073b	1486	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
AnnaBridge	143:86740a56073b	1487	* @arg @ref LL_I2S_STANDARD_PCM_LONG
AnnaBridge	143:86740a56073b	1488	* @retval None
AnnaBridge	143:86740a56073b	1489	*/
AnnaBridge	143:86740a56073b	1490	__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge	143:86740a56073b	1491	{
AnnaBridge	143:86740a56073b	1492	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC, Standard);
AnnaBridge	143:86740a56073b	1493	}
AnnaBridge	143:86740a56073b	1494
AnnaBridge	143:86740a56073b	1495	/**
AnnaBridge	143:86740a56073b	1496	* @brief Get I2S Standard Protocol
AnnaBridge	143:86740a56073b	1497	* @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
AnnaBridge	143:86740a56073b	1498	* I2SCFGR PCMSYNC LL_I2S_GetStandard
AnnaBridge	143:86740a56073b	1499	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1500	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	1501	* @arg @ref LL_I2S_STANDARD_PHILIPS
AnnaBridge	143:86740a56073b	1502	* @arg @ref LL_I2S_STANDARD_MSB
AnnaBridge	143:86740a56073b	1503	* @arg @ref LL_I2S_STANDARD_LSB
AnnaBridge	143:86740a56073b	1504	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
AnnaBridge	143:86740a56073b	1505	* @arg @ref LL_I2S_STANDARD_PCM_LONG
AnnaBridge	143:86740a56073b	1506	*/
AnnaBridge	143:86740a56073b	1507	__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1508	{
AnnaBridge	143:86740a56073b	1509	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC));
AnnaBridge	143:86740a56073b	1510	}
AnnaBridge	143:86740a56073b	1511
AnnaBridge	143:86740a56073b	1512	/**
AnnaBridge	143:86740a56073b	1513	* @brief Set I2S Transfer Mode
AnnaBridge	143:86740a56073b	1514	* @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
AnnaBridge	143:86740a56073b	1515	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1516	* @param Mode This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1517	* @arg @ref LL_I2S_MODE_SLAVE_TX
AnnaBridge	143:86740a56073b	1518	* @arg @ref LL_I2S_MODE_SLAVE_RX
AnnaBridge	143:86740a56073b	1519	* @arg @ref LL_I2S_MODE_MASTER_TX
AnnaBridge	143:86740a56073b	1520	* @arg @ref LL_I2S_MODE_MASTER_RX
AnnaBridge	143:86740a56073b	1521	* @retval None
AnnaBridge	143:86740a56073b	1522	*/
AnnaBridge	143:86740a56073b	1523	__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
AnnaBridge	143:86740a56073b	1524	{
AnnaBridge	143:86740a56073b	1525	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
AnnaBridge	143:86740a56073b	1526	}
AnnaBridge	143:86740a56073b	1527
AnnaBridge	143:86740a56073b	1528	/**
AnnaBridge	143:86740a56073b	1529	* @brief Get I2S Transfer Mode
AnnaBridge	143:86740a56073b	1530	* @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
AnnaBridge	143:86740a56073b	1531	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1532	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	1533	* @arg @ref LL_I2S_MODE_SLAVE_TX
AnnaBridge	143:86740a56073b	1534	* @arg @ref LL_I2S_MODE_SLAVE_RX
AnnaBridge	143:86740a56073b	1535	* @arg @ref LL_I2S_MODE_MASTER_TX
AnnaBridge	143:86740a56073b	1536	* @arg @ref LL_I2S_MODE_MASTER_RX
AnnaBridge	143:86740a56073b	1537	*/
AnnaBridge	143:86740a56073b	1538	__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1539	{
AnnaBridge	143:86740a56073b	1540	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
AnnaBridge	143:86740a56073b	1541	}
AnnaBridge	143:86740a56073b	1542
AnnaBridge	143:86740a56073b	1543	/**
AnnaBridge	143:86740a56073b	1544	* @brief Set I2S linear prescaler
AnnaBridge	143:86740a56073b	1545	* @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
AnnaBridge	143:86740a56073b	1546	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1547	* @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
AnnaBridge	143:86740a56073b	1548	* @retval None
AnnaBridge	143:86740a56073b	1549	*/
AnnaBridge	143:86740a56073b	1550	__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
AnnaBridge	143:86740a56073b	1551	{
AnnaBridge	143:86740a56073b	1552	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
AnnaBridge	143:86740a56073b	1553	}
AnnaBridge	143:86740a56073b	1554
AnnaBridge	143:86740a56073b	1555	/**
AnnaBridge	143:86740a56073b	1556	* @brief Get I2S linear prescaler
AnnaBridge	143:86740a56073b	1557	* @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
AnnaBridge	143:86740a56073b	1558	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1559	* @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
AnnaBridge	143:86740a56073b	1560	*/
AnnaBridge	143:86740a56073b	1561	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1562	{
AnnaBridge	143:86740a56073b	1563	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
AnnaBridge	143:86740a56073b	1564	}
AnnaBridge	143:86740a56073b	1565
AnnaBridge	143:86740a56073b	1566	/**
AnnaBridge	143:86740a56073b	1567	* @brief Set I2S parity prescaler
AnnaBridge	143:86740a56073b	1568	* @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
AnnaBridge	143:86740a56073b	1569	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1570	* @param PrescalerParity This parameter can be one of the following values:
AnnaBridge	143:86740a56073b	1571	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
AnnaBridge	143:86740a56073b	1572	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
AnnaBridge	143:86740a56073b	1573	* @retval None
AnnaBridge	143:86740a56073b	1574	*/
AnnaBridge	143:86740a56073b	1575	__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
AnnaBridge	143:86740a56073b	1576	{
AnnaBridge	143:86740a56073b	1577	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
AnnaBridge	143:86740a56073b	1578	}
AnnaBridge	143:86740a56073b	1579
AnnaBridge	143:86740a56073b	1580	/**
AnnaBridge	143:86740a56073b	1581	* @brief Get I2S parity prescaler
AnnaBridge	143:86740a56073b	1582	* @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
AnnaBridge	143:86740a56073b	1583	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1584	* @retval Returned value can be one of the following values:
AnnaBridge	143:86740a56073b	1585	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
AnnaBridge	143:86740a56073b	1586	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
AnnaBridge	143:86740a56073b	1587	*/
AnnaBridge	143:86740a56073b	1588	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1589	{
AnnaBridge	143:86740a56073b	1590	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
AnnaBridge	143:86740a56073b	1591	}
AnnaBridge	143:86740a56073b	1592
AnnaBridge	143:86740a56073b	1593	/**
AnnaBridge	143:86740a56073b	1594	* @brief Enable the Master Clock Ouput (Pin MCK)
AnnaBridge	143:86740a56073b	1595	* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
AnnaBridge	143:86740a56073b	1596	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1597	* @retval None
AnnaBridge	143:86740a56073b	1598	*/
AnnaBridge	143:86740a56073b	1599	__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1600	{
AnnaBridge	143:86740a56073b	1601	SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
AnnaBridge	143:86740a56073b	1602	}
AnnaBridge	143:86740a56073b	1603
AnnaBridge	143:86740a56073b	1604	/**
AnnaBridge	143:86740a56073b	1605	* @brief Disable the Master Clock Ouput (Pin MCK)
AnnaBridge	143:86740a56073b	1606	* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
AnnaBridge	143:86740a56073b	1607	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1608	* @retval None
AnnaBridge	143:86740a56073b	1609	*/
AnnaBridge	143:86740a56073b	1610	__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1611	{
AnnaBridge	143:86740a56073b	1612	CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
AnnaBridge	143:86740a56073b	1613	}
AnnaBridge	143:86740a56073b	1614
AnnaBridge	143:86740a56073b	1615	/**
AnnaBridge	143:86740a56073b	1616	* @brief Check if the Master Clock Ouput (Pin MCK) is enabled
AnnaBridge	143:86740a56073b	1617	* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
AnnaBridge	143:86740a56073b	1618	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1619	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1620	*/
AnnaBridge	143:86740a56073b	1621	__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1622	{
AnnaBridge	143:86740a56073b	1623	return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
AnnaBridge	143:86740a56073b	1624	}
AnnaBridge	143:86740a56073b	1625
AnnaBridge	143:86740a56073b	1626	#if defined(SPI_I2SCFGR_ASTRTEN)
AnnaBridge	143:86740a56073b	1627	/**
AnnaBridge	143:86740a56073b	1628	* @brief Enable Asynchronous Start
AnnaBridge	143:86740a56073b	1629	* @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
AnnaBridge	143:86740a56073b	1630	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1631	* @retval None
AnnaBridge	143:86740a56073b	1632	*/
AnnaBridge	143:86740a56073b	1633	__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1634	{
AnnaBridge	143:86740a56073b	1635	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
AnnaBridge	143:86740a56073b	1636	}
AnnaBridge	143:86740a56073b	1637
AnnaBridge	143:86740a56073b	1638	/**
AnnaBridge	143:86740a56073b	1639	* @brief Disable Asynchronous Start
AnnaBridge	143:86740a56073b	1640	* @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
AnnaBridge	143:86740a56073b	1641	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1642	* @retval None
AnnaBridge	143:86740a56073b	1643	*/
AnnaBridge	143:86740a56073b	1644	__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1645	{
AnnaBridge	143:86740a56073b	1646	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
AnnaBridge	143:86740a56073b	1647	}
AnnaBridge	143:86740a56073b	1648
AnnaBridge	143:86740a56073b	1649	/**
AnnaBridge	143:86740a56073b	1650	* @brief Check if Asynchronous Start is enabled
AnnaBridge	143:86740a56073b	1651	* @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
AnnaBridge	143:86740a56073b	1652	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1653	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1654	*/
AnnaBridge	143:86740a56073b	1655	__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1656	{
AnnaBridge	143:86740a56073b	1657	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN));
AnnaBridge	143:86740a56073b	1658	}
AnnaBridge	143:86740a56073b	1659	#endif /* SPI_I2SCFGR_ASTRTEN */
AnnaBridge	143:86740a56073b	1660
AnnaBridge	143:86740a56073b	1661	/**
AnnaBridge	143:86740a56073b	1662	* @}
AnnaBridge	143:86740a56073b	1663	*/
AnnaBridge	143:86740a56073b	1664
AnnaBridge	143:86740a56073b	1665	/** @defgroup I2S_LL_EF_FLAG FLAG Management
AnnaBridge	143:86740a56073b	1666	* @{
AnnaBridge	143:86740a56073b	1667	*/
AnnaBridge	143:86740a56073b	1668
AnnaBridge	143:86740a56073b	1669	/**
AnnaBridge	143:86740a56073b	1670	* @brief Check if Rx buffer is not empty
AnnaBridge	143:86740a56073b	1671	* @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
AnnaBridge	143:86740a56073b	1672	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1673	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1674	*/
AnnaBridge	143:86740a56073b	1675	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1676	{
AnnaBridge	143:86740a56073b	1677	return LL_SPI_IsActiveFlag_RXNE(SPIx);
AnnaBridge	143:86740a56073b	1678	}
AnnaBridge	143:86740a56073b	1679
AnnaBridge	143:86740a56073b	1680	/**
AnnaBridge	143:86740a56073b	1681	* @brief Check if Tx buffer is empty
AnnaBridge	143:86740a56073b	1682	* @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
AnnaBridge	143:86740a56073b	1683	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1684	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1685	*/
AnnaBridge	143:86740a56073b	1686	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1687	{
AnnaBridge	143:86740a56073b	1688	return LL_SPI_IsActiveFlag_TXE(SPIx);
AnnaBridge	143:86740a56073b	1689	}
AnnaBridge	143:86740a56073b	1690
AnnaBridge	143:86740a56073b	1691	/**
AnnaBridge	143:86740a56073b	1692	* @brief Get Busy flag
AnnaBridge	143:86740a56073b	1693	* @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
AnnaBridge	143:86740a56073b	1694	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1695	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1696	*/
AnnaBridge	143:86740a56073b	1697	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1698	{
AnnaBridge	143:86740a56073b	1699	return LL_SPI_IsActiveFlag_BSY(SPIx);
AnnaBridge	143:86740a56073b	1700	}
AnnaBridge	143:86740a56073b	1701
AnnaBridge	143:86740a56073b	1702	/**
AnnaBridge	143:86740a56073b	1703	* @brief Get Overrun error flag
AnnaBridge	143:86740a56073b	1704	* @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
AnnaBridge	143:86740a56073b	1705	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1706	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1707	*/
AnnaBridge	143:86740a56073b	1708	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1709	{
AnnaBridge	143:86740a56073b	1710	return LL_SPI_IsActiveFlag_OVR(SPIx);
AnnaBridge	143:86740a56073b	1711	}
AnnaBridge	143:86740a56073b	1712
AnnaBridge	143:86740a56073b	1713	/**
AnnaBridge	143:86740a56073b	1714	* @brief Get Underrun error flag
AnnaBridge	143:86740a56073b	1715	* @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
AnnaBridge	143:86740a56073b	1716	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1717	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1718	*/
AnnaBridge	143:86740a56073b	1719	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1720	{
AnnaBridge	143:86740a56073b	1721	return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
AnnaBridge	143:86740a56073b	1722	}
AnnaBridge	143:86740a56073b	1723
AnnaBridge	143:86740a56073b	1724	/**
AnnaBridge	143:86740a56073b	1725	* @brief Get Frame format error flag
AnnaBridge	143:86740a56073b	1726	* @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
AnnaBridge	143:86740a56073b	1727	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1728	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1729	*/
AnnaBridge	143:86740a56073b	1730	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1731	{
AnnaBridge	143:86740a56073b	1732	return LL_SPI_IsActiveFlag_FRE(SPIx);
AnnaBridge	143:86740a56073b	1733	}
AnnaBridge	143:86740a56073b	1734
AnnaBridge	143:86740a56073b	1735	/**
AnnaBridge	143:86740a56073b	1736	* @brief Get Channel side flag.
AnnaBridge	143:86740a56073b	1737	* @note 0: Channel Left has to be transmitted or has been received\n
AnnaBridge	143:86740a56073b	1738	* 1: Channel Right has to be transmitted or has been received\n
AnnaBridge	143:86740a56073b	1739	* It has no significance in PCM mode.
AnnaBridge	143:86740a56073b	1740	* @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
AnnaBridge	143:86740a56073b	1741	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1742	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1743	*/
AnnaBridge	143:86740a56073b	1744	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1745	{
AnnaBridge	143:86740a56073b	1746	return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
AnnaBridge	143:86740a56073b	1747	}
AnnaBridge	143:86740a56073b	1748
AnnaBridge	143:86740a56073b	1749	/**
AnnaBridge	143:86740a56073b	1750	* @brief Clear Overrun error flag
AnnaBridge	143:86740a56073b	1751	* @rmtoll SR OVR LL_I2S_ClearFlag_OVR
AnnaBridge	143:86740a56073b	1752	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1753	* @retval None
AnnaBridge	143:86740a56073b	1754	*/
AnnaBridge	143:86740a56073b	1755	__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1756	{
AnnaBridge	143:86740a56073b	1757	LL_SPI_ClearFlag_OVR(SPIx);
AnnaBridge	143:86740a56073b	1758	}
AnnaBridge	143:86740a56073b	1759
AnnaBridge	143:86740a56073b	1760	/**
AnnaBridge	143:86740a56073b	1761	* @brief Clear Underrun error flag
AnnaBridge	143:86740a56073b	1762	* @rmtoll SR UDR LL_I2S_ClearFlag_UDR
AnnaBridge	143:86740a56073b	1763	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1764	* @retval None
AnnaBridge	143:86740a56073b	1765	*/
AnnaBridge	143:86740a56073b	1766	__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1767	{
AnnaBridge	143:86740a56073b	1768	__IO uint32_t tmpreg;
AnnaBridge	143:86740a56073b	1769	tmpreg = SPIx->SR;
AnnaBridge	143:86740a56073b	1770	(void)tmpreg;
AnnaBridge	143:86740a56073b	1771	}
AnnaBridge	143:86740a56073b	1772
AnnaBridge	143:86740a56073b	1773	/**
AnnaBridge	143:86740a56073b	1774	* @brief Clear Frame format error flag
AnnaBridge	143:86740a56073b	1775	* @rmtoll SR FRE LL_I2S_ClearFlag_FRE
AnnaBridge	143:86740a56073b	1776	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1777	* @retval None
AnnaBridge	143:86740a56073b	1778	*/
AnnaBridge	143:86740a56073b	1779	__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1780	{
AnnaBridge	143:86740a56073b	1781	LL_SPI_ClearFlag_FRE(SPIx);
AnnaBridge	143:86740a56073b	1782	}
AnnaBridge	143:86740a56073b	1783
AnnaBridge	143:86740a56073b	1784	/**
AnnaBridge	143:86740a56073b	1785	* @}
AnnaBridge	143:86740a56073b	1786	*/
AnnaBridge	143:86740a56073b	1787
AnnaBridge	143:86740a56073b	1788	/** @defgroup I2S_LL_EF_IT Interrupt Management
AnnaBridge	143:86740a56073b	1789	* @{
AnnaBridge	143:86740a56073b	1790	*/
AnnaBridge	143:86740a56073b	1791
AnnaBridge	143:86740a56073b	1792	/**
AnnaBridge	143:86740a56073b	1793	* @brief Enable error IT
AnnaBridge	143:86740a56073b	1794	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
AnnaBridge	143:86740a56073b	1795	* @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
AnnaBridge	143:86740a56073b	1796	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1797	* @retval None
AnnaBridge	143:86740a56073b	1798	*/
AnnaBridge	143:86740a56073b	1799	__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1800	{
AnnaBridge	143:86740a56073b	1801	LL_SPI_EnableIT_ERR(SPIx);
AnnaBridge	143:86740a56073b	1802	}
AnnaBridge	143:86740a56073b	1803
AnnaBridge	143:86740a56073b	1804	/**
AnnaBridge	143:86740a56073b	1805	* @brief Enable Rx buffer not empty IT
AnnaBridge	143:86740a56073b	1806	* @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
AnnaBridge	143:86740a56073b	1807	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1808	* @retval None
AnnaBridge	143:86740a56073b	1809	*/
AnnaBridge	143:86740a56073b	1810	__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1811	{
AnnaBridge	143:86740a56073b	1812	LL_SPI_EnableIT_RXNE(SPIx);
AnnaBridge	143:86740a56073b	1813	}
AnnaBridge	143:86740a56073b	1814
AnnaBridge	143:86740a56073b	1815	/**
AnnaBridge	143:86740a56073b	1816	* @brief Enable Tx buffer empty IT
AnnaBridge	143:86740a56073b	1817	* @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
AnnaBridge	143:86740a56073b	1818	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1819	* @retval None
AnnaBridge	143:86740a56073b	1820	*/
AnnaBridge	143:86740a56073b	1821	__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1822	{
AnnaBridge	143:86740a56073b	1823	LL_SPI_EnableIT_TXE(SPIx);
AnnaBridge	143:86740a56073b	1824	}
AnnaBridge	143:86740a56073b	1825
AnnaBridge	143:86740a56073b	1826	/**
AnnaBridge	143:86740a56073b	1827	* @brief Disable Error IT
AnnaBridge	143:86740a56073b	1828	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
AnnaBridge	143:86740a56073b	1829	* @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
AnnaBridge	143:86740a56073b	1830	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1831	* @retval None
AnnaBridge	143:86740a56073b	1832	*/
AnnaBridge	143:86740a56073b	1833	__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1834	{
AnnaBridge	143:86740a56073b	1835	LL_SPI_DisableIT_ERR(SPIx);
AnnaBridge	143:86740a56073b	1836	}
AnnaBridge	143:86740a56073b	1837
AnnaBridge	143:86740a56073b	1838	/**
AnnaBridge	143:86740a56073b	1839	* @brief Disable Rx buffer not empty IT
AnnaBridge	143:86740a56073b	1840	* @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
AnnaBridge	143:86740a56073b	1841	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1842	* @retval None
AnnaBridge	143:86740a56073b	1843	*/
AnnaBridge	143:86740a56073b	1844	__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1845	{
AnnaBridge	143:86740a56073b	1846	LL_SPI_DisableIT_RXNE(SPIx);
AnnaBridge	143:86740a56073b	1847	}
AnnaBridge	143:86740a56073b	1848
AnnaBridge	143:86740a56073b	1849	/**
AnnaBridge	143:86740a56073b	1850	* @brief Disable Tx buffer empty IT
AnnaBridge	143:86740a56073b	1851	* @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
AnnaBridge	143:86740a56073b	1852	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1853	* @retval None
AnnaBridge	143:86740a56073b	1854	*/
AnnaBridge	143:86740a56073b	1855	__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1856	{
AnnaBridge	143:86740a56073b	1857	LL_SPI_DisableIT_TXE(SPIx);
AnnaBridge	143:86740a56073b	1858	}
AnnaBridge	143:86740a56073b	1859
AnnaBridge	143:86740a56073b	1860	/**
AnnaBridge	143:86740a56073b	1861	* @brief Check if ERR IT is enabled
AnnaBridge	143:86740a56073b	1862	* @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
AnnaBridge	143:86740a56073b	1863	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1864	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1865	*/
AnnaBridge	143:86740a56073b	1866	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1867	{
AnnaBridge	143:86740a56073b	1868	return LL_SPI_IsEnabledIT_ERR(SPIx);
AnnaBridge	143:86740a56073b	1869	}
AnnaBridge	143:86740a56073b	1870
AnnaBridge	143:86740a56073b	1871	/**
AnnaBridge	143:86740a56073b	1872	* @brief Check if RXNE IT is enabled
AnnaBridge	143:86740a56073b	1873	* @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
AnnaBridge	143:86740a56073b	1874	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1875	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1876	*/
AnnaBridge	143:86740a56073b	1877	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1878	{
AnnaBridge	143:86740a56073b	1879	return LL_SPI_IsEnabledIT_RXNE(SPIx);
AnnaBridge	143:86740a56073b	1880	}
AnnaBridge	143:86740a56073b	1881
AnnaBridge	143:86740a56073b	1882	/**
AnnaBridge	143:86740a56073b	1883	* @brief Check if TXE IT is enabled
AnnaBridge	143:86740a56073b	1884	* @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
AnnaBridge	143:86740a56073b	1885	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1886	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1887	*/
AnnaBridge	143:86740a56073b	1888	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1889	{
AnnaBridge	143:86740a56073b	1890	return LL_SPI_IsEnabledIT_TXE(SPIx);
AnnaBridge	143:86740a56073b	1891	}
AnnaBridge	143:86740a56073b	1892
AnnaBridge	143:86740a56073b	1893	/**
AnnaBridge	143:86740a56073b	1894	* @}
AnnaBridge	143:86740a56073b	1895	*/
AnnaBridge	143:86740a56073b	1896
AnnaBridge	143:86740a56073b	1897	/** @defgroup I2S_LL_EF_DMA DMA Management
AnnaBridge	143:86740a56073b	1898	* @{
AnnaBridge	143:86740a56073b	1899	*/
AnnaBridge	143:86740a56073b	1900
AnnaBridge	143:86740a56073b	1901	/**
AnnaBridge	143:86740a56073b	1902	* @brief Enable DMA Rx
AnnaBridge	143:86740a56073b	1903	* @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
AnnaBridge	143:86740a56073b	1904	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1905	* @retval None
AnnaBridge	143:86740a56073b	1906	*/
AnnaBridge	143:86740a56073b	1907	__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1908	{
AnnaBridge	143:86740a56073b	1909	LL_SPI_EnableDMAReq_RX(SPIx);
AnnaBridge	143:86740a56073b	1910	}
AnnaBridge	143:86740a56073b	1911
AnnaBridge	143:86740a56073b	1912	/**
AnnaBridge	143:86740a56073b	1913	* @brief Disable DMA Rx
AnnaBridge	143:86740a56073b	1914	* @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
AnnaBridge	143:86740a56073b	1915	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1916	* @retval None
AnnaBridge	143:86740a56073b	1917	*/
AnnaBridge	143:86740a56073b	1918	__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1919	{
AnnaBridge	143:86740a56073b	1920	LL_SPI_DisableDMAReq_RX(SPIx);
AnnaBridge	143:86740a56073b	1921	}
AnnaBridge	143:86740a56073b	1922
AnnaBridge	143:86740a56073b	1923	/**
AnnaBridge	143:86740a56073b	1924	* @brief Check if DMA Rx is enabled
AnnaBridge	143:86740a56073b	1925	* @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
AnnaBridge	143:86740a56073b	1926	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1927	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1928	*/
AnnaBridge	143:86740a56073b	1929	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1930	{
AnnaBridge	143:86740a56073b	1931	return LL_SPI_IsEnabledDMAReq_RX(SPIx);
AnnaBridge	143:86740a56073b	1932	}
AnnaBridge	143:86740a56073b	1933
AnnaBridge	143:86740a56073b	1934	/**
AnnaBridge	143:86740a56073b	1935	* @brief Enable DMA Tx
AnnaBridge	143:86740a56073b	1936	* @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
AnnaBridge	143:86740a56073b	1937	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1938	* @retval None
AnnaBridge	143:86740a56073b	1939	*/
AnnaBridge	143:86740a56073b	1940	__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1941	{
AnnaBridge	143:86740a56073b	1942	LL_SPI_EnableDMAReq_TX(SPIx);
AnnaBridge	143:86740a56073b	1943	}
AnnaBridge	143:86740a56073b	1944
AnnaBridge	143:86740a56073b	1945	/**
AnnaBridge	143:86740a56073b	1946	* @brief Disable DMA Tx
AnnaBridge	143:86740a56073b	1947	* @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
AnnaBridge	143:86740a56073b	1948	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1949	* @retval None
AnnaBridge	143:86740a56073b	1950	*/
AnnaBridge	143:86740a56073b	1951	__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1952	{
AnnaBridge	143:86740a56073b	1953	LL_SPI_DisableDMAReq_TX(SPIx);
AnnaBridge	143:86740a56073b	1954	}
AnnaBridge	143:86740a56073b	1955
AnnaBridge	143:86740a56073b	1956	/**
AnnaBridge	143:86740a56073b	1957	* @brief Check if DMA Tx is enabled
AnnaBridge	143:86740a56073b	1958	* @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
AnnaBridge	143:86740a56073b	1959	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1960	* @retval State of bit (1 or 0).
AnnaBridge	143:86740a56073b	1961	*/
AnnaBridge	143:86740a56073b	1962	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1963	{
AnnaBridge	143:86740a56073b	1964	return LL_SPI_IsEnabledDMAReq_TX(SPIx);
AnnaBridge	143:86740a56073b	1965	}
AnnaBridge	143:86740a56073b	1966
AnnaBridge	143:86740a56073b	1967	/**
AnnaBridge	143:86740a56073b	1968	* @}
AnnaBridge	143:86740a56073b	1969	*/
AnnaBridge	143:86740a56073b	1970
AnnaBridge	143:86740a56073b	1971	/** @defgroup I2S_LL_EF_DATA DATA Management
AnnaBridge	143:86740a56073b	1972	* @{
AnnaBridge	143:86740a56073b	1973	*/
AnnaBridge	143:86740a56073b	1974
AnnaBridge	143:86740a56073b	1975	/**
AnnaBridge	143:86740a56073b	1976	* @brief Read 16-Bits in data register
AnnaBridge	143:86740a56073b	1977	* @rmtoll DR DR LL_I2S_ReceiveData16
AnnaBridge	143:86740a56073b	1978	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1979	* @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
AnnaBridge	143:86740a56073b	1980	*/
AnnaBridge	143:86740a56073b	1981	__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge	143:86740a56073b	1982	{
AnnaBridge	143:86740a56073b	1983	return LL_SPI_ReceiveData16(SPIx);
AnnaBridge	143:86740a56073b	1984	}
AnnaBridge	143:86740a56073b	1985
AnnaBridge	143:86740a56073b	1986	/**
AnnaBridge	143:86740a56073b	1987	* @brief Write 16-Bits in data register
AnnaBridge	143:86740a56073b	1988	* @rmtoll DR DR LL_I2S_TransmitData16
AnnaBridge	143:86740a56073b	1989	* @param SPIx SPI Instance
AnnaBridge	143:86740a56073b	1990	* @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
AnnaBridge	143:86740a56073b	1991	* @retval None
AnnaBridge	143:86740a56073b	1992	*/
AnnaBridge	143:86740a56073b	1993	__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge	143:86740a56073b	1994	{
AnnaBridge	143:86740a56073b	1995	LL_SPI_TransmitData16(SPIx, TxData);
AnnaBridge	143:86740a56073b	1996	}
AnnaBridge	143:86740a56073b	1997
AnnaBridge	143:86740a56073b	1998	/**
AnnaBridge	143:86740a56073b	1999	* @}
AnnaBridge	143:86740a56073b	2000	*/
AnnaBridge	143:86740a56073b	2001
AnnaBridge	143:86740a56073b	2002	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	143:86740a56073b	2003	/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	143:86740a56073b	2004	* @{
AnnaBridge	143:86740a56073b	2005	*/
AnnaBridge	143:86740a56073b	2006
AnnaBridge	143:86740a56073b	2007	ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
AnnaBridge	143:86740a56073b	2008	ErrorStatus LL_I2S_Init(SPI_TypeDef SPIx, LL_I2S_InitTypeDef I2S_InitStruct);
AnnaBridge	143:86740a56073b	2009	void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
AnnaBridge	143:86740a56073b	2010	void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
AnnaBridge	143:86740a56073b	2011
AnnaBridge	143:86740a56073b	2012	/**
AnnaBridge	143:86740a56073b	2013	* @}
AnnaBridge	143:86740a56073b	2014	*/
AnnaBridge	143:86740a56073b	2015	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	143:86740a56073b	2016
AnnaBridge	143:86740a56073b	2017	/**
AnnaBridge	143:86740a56073b	2018	* @}
AnnaBridge	143:86740a56073b	2019	*/
AnnaBridge	143:86740a56073b	2020
AnnaBridge	143:86740a56073b	2021	/**
AnnaBridge	143:86740a56073b	2022	* @}
AnnaBridge	143:86740a56073b	2023	*/
AnnaBridge	143:86740a56073b	2024	#endif /* SPI_I2S_SUPPORT */
AnnaBridge	143:86740a56073b	2025
AnnaBridge	143:86740a56073b	2026	#endif /* defined (SPI1) \|\| defined (SPI2) */
AnnaBridge	143:86740a56073b	2027
AnnaBridge	143:86740a56073b	2028	/**
AnnaBridge	143:86740a56073b	2029	* @}
AnnaBridge	143:86740a56073b	2030	*/
AnnaBridge	143:86740a56073b	2031
AnnaBridge	143:86740a56073b	2032	#ifdef __cplusplus
AnnaBridge	143:86740a56073b	2033	}
AnnaBridge	143:86740a56073b	2034	#endif
AnnaBridge	143:86740a56073b	2035
AnnaBridge	143:86740a56073b	2036	#endif /* __STM32L0xx_LL_SPI_H */
AnnaBridge	143:86740a56073b	2037
AnnaBridge	143:86740a56073b	2038	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/