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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32LG_STK3600/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_rtc.h@139:856d2700e60b, 2017-03-30 (annotated)

Committer:
<>
Date:
Thu Mar 30 13:26:47 2017 +0100
Revision:
139:856d2700e60b
Parent:
128:9bcdf88f62b0 
Release 139 of the mbed library



Ports for Upcoming Targets



3934: [Silicon Labs] Update to HAL and devices https://github.com/ARMmbed/mbed-os/pull/3934



Known Issues



There is an issue with LPC1768 failing the 'Semihost file system' test with this release.



Fixes and Changes



3691: [TLS / hw acceleration] AES ECB for NUCLEO_F439ZI https://github.com/ARMmbed/mbed-os/pull/3691

3869: NCS36510: Default range changed from 0 to 950mV - ADC  https://github.com/ARMmbed/mbed-os/pull/3869

3893: [STM32F7] Update STM32 Cube version v1.6.0 https://github.com/ARMmbed/mbed-os/pull/3893

3917: Fix  mistake register setting in serial_format() https://github.com/ARMmbed/mbed-os/pull/3917

3927: [DELTA_DFBM_NQ620] Add RC calibration setting and revise mbed_overrides.c https://github.com/ARMmbed/mbed-os/pull/3927

3918: [NUC472/M453] Support unique locally administered MAC address and other driver updates https://github.com/ARMmbed/mbed-os/pull/3918

3920: Heap size adjusted to work for both tls-client and mbed-client https://github.com/ARMmbed/mbed-os/pull/3920

3969: NUCLEO_F302R8: Add missing PB_8/PB_9 CAN pins https://github.com/ARMmbed/mbed-os/pull/3969

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**************************************************************************//**
<> 128:9bcdf88f62b0 2 * @file efm32lg_rtc.h
<> 128:9bcdf88f62b0 3 * @brief EFM32LG_RTC register and bit field definitions
<> 139:856d2700e60b 4 * @version 5.1.2
<> 128:9bcdf88f62b0 5 ******************************************************************************
<> 128:9bcdf88f62b0 6 * @section License
<> 139:856d2700e60b 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 *
<> 128:9bcdf88f62b0 10 * Permission is granted to anyone to use this software for any purpose,
<> 128:9bcdf88f62b0 11 * including commercial applications, and to alter it and redistribute it
<> 128:9bcdf88f62b0 12 * freely, subject to the following restrictions:
<> 128:9bcdf88f62b0 13 *
<> 128:9bcdf88f62b0 14 * 1. The origin of this software must not be misrepresented; you must not
<> 128:9bcdf88f62b0 15 * claim that you wrote the original software.@n
<> 128:9bcdf88f62b0 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 128:9bcdf88f62b0 17 * misrepresented as being the original software.@n
<> 128:9bcdf88f62b0 18 * 3. This notice may not be removed or altered from any source distribution.
<> 128:9bcdf88f62b0 19 *
<> 128:9bcdf88f62b0 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 128:9bcdf88f62b0 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 128:9bcdf88f62b0 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 128:9bcdf88f62b0 23 * kind, including, but not limited to, any implied warranties of
<> 128:9bcdf88f62b0 24 * merchantability or fitness for any particular purpose or warranties against
<> 128:9bcdf88f62b0 25 * infringement of any proprietary rights of a third party.
<> 128:9bcdf88f62b0 26 *
<> 128:9bcdf88f62b0 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 128:9bcdf88f62b0 28 * incidental, or special damages, or any other relief, or for any claim by
<> 128:9bcdf88f62b0 29 * any third party, arising from your use of this Software.
<> 128:9bcdf88f62b0 30 *
<> 128:9bcdf88f62b0 31 *****************************************************************************/
<> 128:9bcdf88f62b0 32 /**************************************************************************//**
<> 128:9bcdf88f62b0 33 * @addtogroup Parts
<> 128:9bcdf88f62b0 34 * @{
<> 128:9bcdf88f62b0 35 ******************************************************************************/
<> 128:9bcdf88f62b0 36 /**************************************************************************//**
<> 128:9bcdf88f62b0 37 * @defgroup EFM32LG_RTC
<> 128:9bcdf88f62b0 38 * @{
<> 128:9bcdf88f62b0 39 * @brief EFM32LG_RTC Register Declaration
<> 128:9bcdf88f62b0 40 *****************************************************************************/
<> 128:9bcdf88f62b0 41 typedef struct
<> 128:9bcdf88f62b0 42 {
<> 128:9bcdf88f62b0 43 __IOM uint32_t CTRL; /**< Control Register */
<> 128:9bcdf88f62b0 44 __IOM uint32_t CNT; /**< Counter Value Register */
<> 128:9bcdf88f62b0 45 __IOM uint32_t COMP0; /**< Compare Value Register 0 */
<> 128:9bcdf88f62b0 46 __IOM uint32_t COMP1; /**< Compare Value Register 1 */
<> 128:9bcdf88f62b0 47 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 128:9bcdf88f62b0 48 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 128:9bcdf88f62b0 49 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 128:9bcdf88f62b0 50 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 128:9bcdf88f62b0 51
<> 128:9bcdf88f62b0 52 __IOM uint32_t FREEZE; /**< Freeze Register */
<> 128:9bcdf88f62b0 53 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
<> 128:9bcdf88f62b0 54 } RTC_TypeDef; /** @} */
<> 128:9bcdf88f62b0 55
<> 128:9bcdf88f62b0 56 /**************************************************************************//**
<> 128:9bcdf88f62b0 57 * @defgroup EFM32LG_RTC_BitFields
<> 128:9bcdf88f62b0 58 * @{
<> 128:9bcdf88f62b0 59 *****************************************************************************/
<> 128:9bcdf88f62b0 60
<> 128:9bcdf88f62b0 61 /* Bit fields for RTC CTRL */
<> 128:9bcdf88f62b0 62 #define _RTC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTC_CTRL */
<> 128:9bcdf88f62b0 63 #define _RTC_CTRL_MASK 0x00000007UL /**< Mask for RTC_CTRL */
<> 128:9bcdf88f62b0 64 #define RTC_CTRL_EN (0x1UL << 0) /**< RTC Enable */
<> 128:9bcdf88f62b0 65 #define _RTC_CTRL_EN_SHIFT 0 /**< Shift value for RTC_EN */
<> 128:9bcdf88f62b0 66 #define _RTC_CTRL_EN_MASK 0x1UL /**< Bit mask for RTC_EN */
<> 128:9bcdf88f62b0 67 #define _RTC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */
<> 128:9bcdf88f62b0 68 #define RTC_CTRL_EN_DEFAULT (_RTC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CTRL */
<> 128:9bcdf88f62b0 69 #define RTC_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */
<> 128:9bcdf88f62b0 70 #define _RTC_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for RTC_DEBUGRUN */
<> 128:9bcdf88f62b0 71 #define _RTC_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for RTC_DEBUGRUN */
<> 128:9bcdf88f62b0 72 #define _RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */
<> 128:9bcdf88f62b0 73 #define RTC_CTRL_DEBUGRUN_DEFAULT (_RTC_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_CTRL */
<> 128:9bcdf88f62b0 74 #define RTC_CTRL_COMP0TOP (0x1UL << 2) /**< Compare Channel 0 is Top Value */
<> 128:9bcdf88f62b0 75 #define _RTC_CTRL_COMP0TOP_SHIFT 2 /**< Shift value for RTC_COMP0TOP */
<> 128:9bcdf88f62b0 76 #define _RTC_CTRL_COMP0TOP_MASK 0x4UL /**< Bit mask for RTC_COMP0TOP */
<> 128:9bcdf88f62b0 77 #define _RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */
<> 128:9bcdf88f62b0 78 #define _RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL /**< Mode DISABLE for RTC_CTRL */
<> 128:9bcdf88f62b0 79 #define _RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL /**< Mode ENABLE for RTC_CTRL */
<> 128:9bcdf88f62b0 80 #define RTC_CTRL_COMP0TOP_DEFAULT (_RTC_CTRL_COMP0TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_CTRL */
<> 128:9bcdf88f62b0 81 #define RTC_CTRL_COMP0TOP_DISABLE (_RTC_CTRL_COMP0TOP_DISABLE << 2) /**< Shifted mode DISABLE for RTC_CTRL */
<> 128:9bcdf88f62b0 82 #define RTC_CTRL_COMP0TOP_ENABLE (_RTC_CTRL_COMP0TOP_ENABLE << 2) /**< Shifted mode ENABLE for RTC_CTRL */
<> 128:9bcdf88f62b0 83
<> 128:9bcdf88f62b0 84 /* Bit fields for RTC CNT */
<> 128:9bcdf88f62b0 85 #define _RTC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTC_CNT */
<> 128:9bcdf88f62b0 86 #define _RTC_CNT_MASK 0x00FFFFFFUL /**< Mask for RTC_CNT */
<> 128:9bcdf88f62b0 87 #define _RTC_CNT_CNT_SHIFT 0 /**< Shift value for RTC_CNT */
<> 128:9bcdf88f62b0 88 #define _RTC_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for RTC_CNT */
<> 128:9bcdf88f62b0 89 #define _RTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CNT */
<> 128:9bcdf88f62b0 90 #define RTC_CNT_CNT_DEFAULT (_RTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CNT */
<> 128:9bcdf88f62b0 91
<> 128:9bcdf88f62b0 92 /* Bit fields for RTC COMP0 */
<> 128:9bcdf88f62b0 93 #define _RTC_COMP0_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP0 */
<> 128:9bcdf88f62b0 94 #define _RTC_COMP0_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP0 */
<> 128:9bcdf88f62b0 95 #define _RTC_COMP0_COMP0_SHIFT 0 /**< Shift value for RTC_COMP0 */
<> 128:9bcdf88f62b0 96 #define _RTC_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP0 */
<> 128:9bcdf88f62b0 97 #define _RTC_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP0 */
<> 128:9bcdf88f62b0 98 #define RTC_COMP0_COMP0_DEFAULT (_RTC_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP0 */
<> 128:9bcdf88f62b0 99
<> 128:9bcdf88f62b0 100 /* Bit fields for RTC COMP1 */
<> 128:9bcdf88f62b0 101 #define _RTC_COMP1_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP1 */
<> 128:9bcdf88f62b0 102 #define _RTC_COMP1_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP1 */
<> 128:9bcdf88f62b0 103 #define _RTC_COMP1_COMP1_SHIFT 0 /**< Shift value for RTC_COMP1 */
<> 128:9bcdf88f62b0 104 #define _RTC_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP1 */
<> 128:9bcdf88f62b0 105 #define _RTC_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP1 */
<> 128:9bcdf88f62b0 106 #define RTC_COMP1_COMP1_DEFAULT (_RTC_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP1 */
<> 128:9bcdf88f62b0 107
<> 128:9bcdf88f62b0 108 /* Bit fields for RTC IF */
<> 128:9bcdf88f62b0 109 #define _RTC_IF_RESETVALUE 0x00000000UL /**< Default value for RTC_IF */
<> 128:9bcdf88f62b0 110 #define _RTC_IF_MASK 0x00000007UL /**< Mask for RTC_IF */
<> 128:9bcdf88f62b0 111 #define RTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
<> 128:9bcdf88f62b0 112 #define _RTC_IF_OF_SHIFT 0 /**< Shift value for RTC_OF */
<> 128:9bcdf88f62b0 113 #define _RTC_IF_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
<> 128:9bcdf88f62b0 114 #define _RTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */
<> 128:9bcdf88f62b0 115 #define RTC_IF_OF_DEFAULT (_RTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IF */
<> 128:9bcdf88f62b0 116 #define RTC_IF_COMP0 (0x1UL << 1) /**< Compare Match 0 Interrupt Flag */
<> 128:9bcdf88f62b0 117 #define _RTC_IF_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
<> 128:9bcdf88f62b0 118 #define _RTC_IF_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
<> 128:9bcdf88f62b0 119 #define _RTC_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */
<> 128:9bcdf88f62b0 120 #define RTC_IF_COMP0_DEFAULT (_RTC_IF_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IF */
<> 128:9bcdf88f62b0 121 #define RTC_IF_COMP1 (0x1UL << 2) /**< Compare Match 1 Interrupt Flag */
<> 128:9bcdf88f62b0 122 #define _RTC_IF_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
<> 128:9bcdf88f62b0 123 #define _RTC_IF_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
<> 128:9bcdf88f62b0 124 #define _RTC_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */
<> 128:9bcdf88f62b0 125 #define RTC_IF_COMP1_DEFAULT (_RTC_IF_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IF */
<> 128:9bcdf88f62b0 126
<> 128:9bcdf88f62b0 127 /* Bit fields for RTC IFS */
<> 128:9bcdf88f62b0 128 #define _RTC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTC_IFS */
<> 128:9bcdf88f62b0 129 #define _RTC_IFS_MASK 0x00000007UL /**< Mask for RTC_IFS */
<> 128:9bcdf88f62b0 130 #define RTC_IFS_OF (0x1UL << 0) /**< Set Overflow Interrupt Flag */
<> 128:9bcdf88f62b0 131 #define _RTC_IFS_OF_SHIFT 0 /**< Shift value for RTC_OF */
<> 128:9bcdf88f62b0 132 #define _RTC_IFS_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
<> 128:9bcdf88f62b0 133 #define _RTC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */
<> 128:9bcdf88f62b0 134 #define RTC_IFS_OF_DEFAULT (_RTC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFS */
<> 128:9bcdf88f62b0 135 #define RTC_IFS_COMP0 (0x1UL << 1) /**< Set Compare match 0 Interrupt Flag */
<> 128:9bcdf88f62b0 136 #define _RTC_IFS_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
<> 128:9bcdf88f62b0 137 #define _RTC_IFS_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
<> 128:9bcdf88f62b0 138 #define _RTC_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */
<> 128:9bcdf88f62b0 139 #define RTC_IFS_COMP0_DEFAULT (_RTC_IFS_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFS */
<> 128:9bcdf88f62b0 140 #define RTC_IFS_COMP1 (0x1UL << 2) /**< Set Compare match 1 Interrupt Flag */
<> 128:9bcdf88f62b0 141 #define _RTC_IFS_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
<> 128:9bcdf88f62b0 142 #define _RTC_IFS_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
<> 128:9bcdf88f62b0 143 #define _RTC_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */
<> 128:9bcdf88f62b0 144 #define RTC_IFS_COMP1_DEFAULT (_RTC_IFS_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFS */
<> 128:9bcdf88f62b0 145
<> 128:9bcdf88f62b0 146 /* Bit fields for RTC IFC */
<> 128:9bcdf88f62b0 147 #define _RTC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTC_IFC */
<> 128:9bcdf88f62b0 148 #define _RTC_IFC_MASK 0x00000007UL /**< Mask for RTC_IFC */
<> 128:9bcdf88f62b0 149 #define RTC_IFC_OF (0x1UL << 0) /**< Clear Overflow Interrupt Flag */
<> 128:9bcdf88f62b0 150 #define _RTC_IFC_OF_SHIFT 0 /**< Shift value for RTC_OF */
<> 128:9bcdf88f62b0 151 #define _RTC_IFC_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
<> 128:9bcdf88f62b0 152 #define _RTC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */
<> 128:9bcdf88f62b0 153 #define RTC_IFC_OF_DEFAULT (_RTC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFC */
<> 128:9bcdf88f62b0 154 #define RTC_IFC_COMP0 (0x1UL << 1) /**< Clear Compare match 0 Interrupt Flag */
<> 128:9bcdf88f62b0 155 #define _RTC_IFC_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
<> 128:9bcdf88f62b0 156 #define _RTC_IFC_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
<> 128:9bcdf88f62b0 157 #define _RTC_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */
<> 128:9bcdf88f62b0 158 #define RTC_IFC_COMP0_DEFAULT (_RTC_IFC_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFC */
<> 128:9bcdf88f62b0 159 #define RTC_IFC_COMP1 (0x1UL << 2) /**< Clear Compare match 1 Interrupt Flag */
<> 128:9bcdf88f62b0 160 #define _RTC_IFC_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
<> 128:9bcdf88f62b0 161 #define _RTC_IFC_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
<> 128:9bcdf88f62b0 162 #define _RTC_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */
<> 128:9bcdf88f62b0 163 #define RTC_IFC_COMP1_DEFAULT (_RTC_IFC_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFC */
<> 128:9bcdf88f62b0 164
<> 128:9bcdf88f62b0 165 /* Bit fields for RTC IEN */
<> 128:9bcdf88f62b0 166 #define _RTC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTC_IEN */
<> 128:9bcdf88f62b0 167 #define _RTC_IEN_MASK 0x00000007UL /**< Mask for RTC_IEN */
<> 128:9bcdf88f62b0 168 #define RTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */
<> 128:9bcdf88f62b0 169 #define _RTC_IEN_OF_SHIFT 0 /**< Shift value for RTC_OF */
<> 128:9bcdf88f62b0 170 #define _RTC_IEN_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
<> 128:9bcdf88f62b0 171 #define _RTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */
<> 128:9bcdf88f62b0 172 #define RTC_IEN_OF_DEFAULT (_RTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IEN */
<> 128:9bcdf88f62b0 173 #define RTC_IEN_COMP0 (0x1UL << 1) /**< Compare Match 0 Interrupt Enable */
<> 128:9bcdf88f62b0 174 #define _RTC_IEN_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
<> 128:9bcdf88f62b0 175 #define _RTC_IEN_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
<> 128:9bcdf88f62b0 176 #define _RTC_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */
<> 128:9bcdf88f62b0 177 #define RTC_IEN_COMP0_DEFAULT (_RTC_IEN_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IEN */
<> 128:9bcdf88f62b0 178 #define RTC_IEN_COMP1 (0x1UL << 2) /**< Compare Match 1 Interrupt Enable */
<> 128:9bcdf88f62b0 179 #define _RTC_IEN_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
<> 128:9bcdf88f62b0 180 #define _RTC_IEN_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
<> 128:9bcdf88f62b0 181 #define _RTC_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */
<> 128:9bcdf88f62b0 182 #define RTC_IEN_COMP1_DEFAULT (_RTC_IEN_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IEN */
<> 128:9bcdf88f62b0 183
<> 128:9bcdf88f62b0 184 /* Bit fields for RTC FREEZE */
<> 128:9bcdf88f62b0 185 #define _RTC_FREEZE_RESETVALUE 0x00000000UL /**< Default value for RTC_FREEZE */
<> 128:9bcdf88f62b0 186 #define _RTC_FREEZE_MASK 0x00000001UL /**< Mask for RTC_FREEZE */
<> 128:9bcdf88f62b0 187 #define RTC_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
<> 128:9bcdf88f62b0 188 #define _RTC_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for RTC_REGFREEZE */
<> 128:9bcdf88f62b0 189 #define _RTC_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for RTC_REGFREEZE */
<> 128:9bcdf88f62b0 190 #define _RTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_FREEZE */
<> 128:9bcdf88f62b0 191 #define _RTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for RTC_FREEZE */
<> 128:9bcdf88f62b0 192 #define _RTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for RTC_FREEZE */
<> 128:9bcdf88f62b0 193 #define RTC_FREEZE_REGFREEZE_DEFAULT (_RTC_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_FREEZE */
<> 128:9bcdf88f62b0 194 #define RTC_FREEZE_REGFREEZE_UPDATE (_RTC_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for RTC_FREEZE */
<> 128:9bcdf88f62b0 195 #define RTC_FREEZE_REGFREEZE_FREEZE (_RTC_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for RTC_FREEZE */
<> 128:9bcdf88f62b0 196
<> 128:9bcdf88f62b0 197 /* Bit fields for RTC SYNCBUSY */
<> 128:9bcdf88f62b0 198 #define _RTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTC_SYNCBUSY */
<> 128:9bcdf88f62b0 199 #define _RTC_SYNCBUSY_MASK 0x00000007UL /**< Mask for RTC_SYNCBUSY */
<> 128:9bcdf88f62b0 200 #define RTC_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
<> 128:9bcdf88f62b0 201 #define _RTC_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for RTC_CTRL */
<> 128:9bcdf88f62b0 202 #define _RTC_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for RTC_CTRL */
<> 128:9bcdf88f62b0 203 #define _RTC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */
<> 128:9bcdf88f62b0 204 #define RTC_SYNCBUSY_CTRL_DEFAULT (_RTC_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
<> 128:9bcdf88f62b0 205 #define RTC_SYNCBUSY_COMP0 (0x1UL << 1) /**< COMP0 Register Busy */
<> 128:9bcdf88f62b0 206 #define _RTC_SYNCBUSY_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
<> 128:9bcdf88f62b0 207 #define _RTC_SYNCBUSY_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
<> 128:9bcdf88f62b0 208 #define _RTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */
<> 128:9bcdf88f62b0 209 #define RTC_SYNCBUSY_COMP0_DEFAULT (_RTC_SYNCBUSY_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
<> 128:9bcdf88f62b0 210 #define RTC_SYNCBUSY_COMP1 (0x1UL << 2) /**< COMP1 Register Busy */
<> 128:9bcdf88f62b0 211 #define _RTC_SYNCBUSY_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
<> 128:9bcdf88f62b0 212 #define _RTC_SYNCBUSY_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
<> 128:9bcdf88f62b0 213 #define _RTC_SYNCBUSY_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */
<> 128:9bcdf88f62b0 214 #define RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
<> 128:9bcdf88f62b0 215
<> 128:9bcdf88f62b0 216 /** @} End of group EFM32LG_RTC */
<> 128:9bcdf88f62b0 217 /** @} End of group Parts */
<> 128:9bcdf88f62b0 218