mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32LG_STK3600/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_leuart.h@139:856d2700e60b, 2017-03-30 (annotated)

Committer:
<>
Date:
Thu Mar 30 13:26:47 2017 +0100
Revision:
139:856d2700e60b
Parent:
128:9bcdf88f62b0 
Release 139 of the mbed library



Ports for Upcoming Targets



3934: [Silicon Labs] Update to HAL and devices https://github.com/ARMmbed/mbed-os/pull/3934



Known Issues



There is an issue with LPC1768 failing the 'Semihost file system' test with this release.



Fixes and Changes



3691: [TLS / hw acceleration] AES ECB for NUCLEO_F439ZI https://github.com/ARMmbed/mbed-os/pull/3691

3869: NCS36510: Default range changed from 0 to 950mV - ADC  https://github.com/ARMmbed/mbed-os/pull/3869

3893: [STM32F7] Update STM32 Cube version v1.6.0 https://github.com/ARMmbed/mbed-os/pull/3893

3917: Fix  mistake register setting in serial_format() https://github.com/ARMmbed/mbed-os/pull/3917

3927: [DELTA_DFBM_NQ620] Add RC calibration setting and revise mbed_overrides.c https://github.com/ARMmbed/mbed-os/pull/3927

3918: [NUC472/M453] Support unique locally administered MAC address and other driver updates https://github.com/ARMmbed/mbed-os/pull/3918

3920: Heap size adjusted to work for both tls-client and mbed-client https://github.com/ARMmbed/mbed-os/pull/3920

3969: NUCLEO_F302R8: Add missing PB_8/PB_9 CAN pins https://github.com/ARMmbed/mbed-os/pull/3969

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**************************************************************************//**
<> 128:9bcdf88f62b0 2 * @file efm32lg_leuart.h
<> 128:9bcdf88f62b0 3 * @brief EFM32LG_LEUART register and bit field definitions
<> 139:856d2700e60b 4 * @version 5.1.2
<> 128:9bcdf88f62b0 5 ******************************************************************************
<> 128:9bcdf88f62b0 6 * @section License
<> 139:856d2700e60b 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 *
<> 128:9bcdf88f62b0 10 * Permission is granted to anyone to use this software for any purpose,
<> 128:9bcdf88f62b0 11 * including commercial applications, and to alter it and redistribute it
<> 128:9bcdf88f62b0 12 * freely, subject to the following restrictions:
<> 128:9bcdf88f62b0 13 *
<> 128:9bcdf88f62b0 14 * 1. The origin of this software must not be misrepresented; you must not
<> 128:9bcdf88f62b0 15 * claim that you wrote the original software.@n
<> 128:9bcdf88f62b0 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 128:9bcdf88f62b0 17 * misrepresented as being the original software.@n
<> 128:9bcdf88f62b0 18 * 3. This notice may not be removed or altered from any source distribution.
<> 128:9bcdf88f62b0 19 *
<> 128:9bcdf88f62b0 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 128:9bcdf88f62b0 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 128:9bcdf88f62b0 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 128:9bcdf88f62b0 23 * kind, including, but not limited to, any implied warranties of
<> 128:9bcdf88f62b0 24 * merchantability or fitness for any particular purpose or warranties against
<> 128:9bcdf88f62b0 25 * infringement of any proprietary rights of a third party.
<> 128:9bcdf88f62b0 26 *
<> 128:9bcdf88f62b0 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 128:9bcdf88f62b0 28 * incidental, or special damages, or any other relief, or for any claim by
<> 128:9bcdf88f62b0 29 * any third party, arising from your use of this Software.
<> 128:9bcdf88f62b0 30 *
<> 128:9bcdf88f62b0 31 *****************************************************************************/
<> 128:9bcdf88f62b0 32 /**************************************************************************//**
<> 128:9bcdf88f62b0 33 * @addtogroup Parts
<> 128:9bcdf88f62b0 34 * @{
<> 128:9bcdf88f62b0 35 ******************************************************************************/
<> 128:9bcdf88f62b0 36 /**************************************************************************//**
<> 128:9bcdf88f62b0 37 * @defgroup EFM32LG_LEUART
<> 128:9bcdf88f62b0 38 * @{
<> 128:9bcdf88f62b0 39 * @brief EFM32LG_LEUART Register Declaration
<> 128:9bcdf88f62b0 40 *****************************************************************************/
<> 128:9bcdf88f62b0 41 typedef struct
<> 128:9bcdf88f62b0 42 {
<> 128:9bcdf88f62b0 43 __IOM uint32_t CTRL; /**< Control Register */
<> 128:9bcdf88f62b0 44 __IOM uint32_t CMD; /**< Command Register */
<> 128:9bcdf88f62b0 45 __IM uint32_t STATUS; /**< Status Register */
<> 128:9bcdf88f62b0 46 __IOM uint32_t CLKDIV; /**< Clock Control Register */
<> 128:9bcdf88f62b0 47 __IOM uint32_t STARTFRAME; /**< Start Frame Register */
<> 128:9bcdf88f62b0 48 __IOM uint32_t SIGFRAME; /**< Signal Frame Register */
<> 128:9bcdf88f62b0 49 __IM uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */
<> 128:9bcdf88f62b0 50 __IM uint32_t RXDATA; /**< Receive Buffer Data Register */
<> 128:9bcdf88f62b0 51 __IM uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */
<> 128:9bcdf88f62b0 52 __IOM uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */
<> 128:9bcdf88f62b0 53 __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
<> 128:9bcdf88f62b0 54 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 128:9bcdf88f62b0 55 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 128:9bcdf88f62b0 56 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 128:9bcdf88f62b0 57 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 128:9bcdf88f62b0 58 __IOM uint32_t PULSECTRL; /**< Pulse Control Register */
<> 128:9bcdf88f62b0 59
<> 128:9bcdf88f62b0 60 __IOM uint32_t FREEZE; /**< Freeze Register */
<> 128:9bcdf88f62b0 61 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
<> 128:9bcdf88f62b0 62
<> 128:9bcdf88f62b0 63 uint32_t RESERVED0[3]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 64 __IOM uint32_t ROUTE; /**< I/O Routing Register */
<> 128:9bcdf88f62b0 65 uint32_t RESERVED1[21]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 66 __IOM uint32_t INPUT; /**< LEUART Input Register */
<> 128:9bcdf88f62b0 67 } LEUART_TypeDef; /** @} */
<> 128:9bcdf88f62b0 68
<> 128:9bcdf88f62b0 69 /**************************************************************************//**
<> 128:9bcdf88f62b0 70 * @defgroup EFM32LG_LEUART_BitFields
<> 128:9bcdf88f62b0 71 * @{
<> 128:9bcdf88f62b0 72 *****************************************************************************/
<> 128:9bcdf88f62b0 73
<> 128:9bcdf88f62b0 74 /* Bit fields for LEUART CTRL */
<> 128:9bcdf88f62b0 75 #define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */
<> 128:9bcdf88f62b0 76 #define _LEUART_CTRL_MASK 0x0000FFFFUL /**< Mask for LEUART_CTRL */
<> 128:9bcdf88f62b0 77 #define LEUART_CTRL_AUTOTRI (0x1UL << 0) /**< Automatic Transmitter Tristate */
<> 128:9bcdf88f62b0 78 #define _LEUART_CTRL_AUTOTRI_SHIFT 0 /**< Shift value for LEUART_AUTOTRI */
<> 128:9bcdf88f62b0 79 #define _LEUART_CTRL_AUTOTRI_MASK 0x1UL /**< Bit mask for LEUART_AUTOTRI */
<> 128:9bcdf88f62b0 80 #define _LEUART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 81 #define LEUART_CTRL_AUTOTRI_DEFAULT (_LEUART_CTRL_AUTOTRI_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 82 #define LEUART_CTRL_DATABITS (0x1UL << 1) /**< Data-Bit Mode */
<> 128:9bcdf88f62b0 83 #define _LEUART_CTRL_DATABITS_SHIFT 1 /**< Shift value for LEUART_DATABITS */
<> 128:9bcdf88f62b0 84 #define _LEUART_CTRL_DATABITS_MASK 0x2UL /**< Bit mask for LEUART_DATABITS */
<> 128:9bcdf88f62b0 85 #define _LEUART_CTRL_DATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 86 #define _LEUART_CTRL_DATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for LEUART_CTRL */
<> 128:9bcdf88f62b0 87 #define _LEUART_CTRL_DATABITS_NINE 0x00000001UL /**< Mode NINE for LEUART_CTRL */
<> 128:9bcdf88f62b0 88 #define LEUART_CTRL_DATABITS_DEFAULT (_LEUART_CTRL_DATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 89 #define LEUART_CTRL_DATABITS_EIGHT (_LEUART_CTRL_DATABITS_EIGHT << 1) /**< Shifted mode EIGHT for LEUART_CTRL */
<> 128:9bcdf88f62b0 90 #define LEUART_CTRL_DATABITS_NINE (_LEUART_CTRL_DATABITS_NINE << 1) /**< Shifted mode NINE for LEUART_CTRL */
<> 128:9bcdf88f62b0 91 #define _LEUART_CTRL_PARITY_SHIFT 2 /**< Shift value for LEUART_PARITY */
<> 128:9bcdf88f62b0 92 #define _LEUART_CTRL_PARITY_MASK 0xCUL /**< Bit mask for LEUART_PARITY */
<> 128:9bcdf88f62b0 93 #define _LEUART_CTRL_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 94 #define _LEUART_CTRL_PARITY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */
<> 128:9bcdf88f62b0 95 #define _LEUART_CTRL_PARITY_EVEN 0x00000002UL /**< Mode EVEN for LEUART_CTRL */
<> 128:9bcdf88f62b0 96 #define _LEUART_CTRL_PARITY_ODD 0x00000003UL /**< Mode ODD for LEUART_CTRL */
<> 128:9bcdf88f62b0 97 #define LEUART_CTRL_PARITY_DEFAULT (_LEUART_CTRL_PARITY_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 98 #define LEUART_CTRL_PARITY_NONE (_LEUART_CTRL_PARITY_NONE << 2) /**< Shifted mode NONE for LEUART_CTRL */
<> 128:9bcdf88f62b0 99 #define LEUART_CTRL_PARITY_EVEN (_LEUART_CTRL_PARITY_EVEN << 2) /**< Shifted mode EVEN for LEUART_CTRL */
<> 128:9bcdf88f62b0 100 #define LEUART_CTRL_PARITY_ODD (_LEUART_CTRL_PARITY_ODD << 2) /**< Shifted mode ODD for LEUART_CTRL */
<> 128:9bcdf88f62b0 101 #define LEUART_CTRL_STOPBITS (0x1UL << 4) /**< Stop-Bit Mode */
<> 128:9bcdf88f62b0 102 #define _LEUART_CTRL_STOPBITS_SHIFT 4 /**< Shift value for LEUART_STOPBITS */
<> 128:9bcdf88f62b0 103 #define _LEUART_CTRL_STOPBITS_MASK 0x10UL /**< Bit mask for LEUART_STOPBITS */
<> 128:9bcdf88f62b0 104 #define _LEUART_CTRL_STOPBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 105 #define _LEUART_CTRL_STOPBITS_ONE 0x00000000UL /**< Mode ONE for LEUART_CTRL */
<> 128:9bcdf88f62b0 106 #define _LEUART_CTRL_STOPBITS_TWO 0x00000001UL /**< Mode TWO for LEUART_CTRL */
<> 128:9bcdf88f62b0 107 #define LEUART_CTRL_STOPBITS_DEFAULT (_LEUART_CTRL_STOPBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 108 #define LEUART_CTRL_STOPBITS_ONE (_LEUART_CTRL_STOPBITS_ONE << 4) /**< Shifted mode ONE for LEUART_CTRL */
<> 128:9bcdf88f62b0 109 #define LEUART_CTRL_STOPBITS_TWO (_LEUART_CTRL_STOPBITS_TWO << 4) /**< Shifted mode TWO for LEUART_CTRL */
<> 128:9bcdf88f62b0 110 #define LEUART_CTRL_INV (0x1UL << 5) /**< Invert Input And Output */
<> 128:9bcdf88f62b0 111 #define _LEUART_CTRL_INV_SHIFT 5 /**< Shift value for LEUART_INV */
<> 128:9bcdf88f62b0 112 #define _LEUART_CTRL_INV_MASK 0x20UL /**< Bit mask for LEUART_INV */
<> 128:9bcdf88f62b0 113 #define _LEUART_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 114 #define LEUART_CTRL_INV_DEFAULT (_LEUART_CTRL_INV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 115 #define LEUART_CTRL_ERRSDMA (0x1UL << 6) /**< Clear RX DMA On Error */
<> 128:9bcdf88f62b0 116 #define _LEUART_CTRL_ERRSDMA_SHIFT 6 /**< Shift value for LEUART_ERRSDMA */
<> 128:9bcdf88f62b0 117 #define _LEUART_CTRL_ERRSDMA_MASK 0x40UL /**< Bit mask for LEUART_ERRSDMA */
<> 128:9bcdf88f62b0 118 #define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 119 #define LEUART_CTRL_ERRSDMA_DEFAULT (_LEUART_CTRL_ERRSDMA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 120 #define LEUART_CTRL_LOOPBK (0x1UL << 7) /**< Loopback Enable */
<> 128:9bcdf88f62b0 121 #define _LEUART_CTRL_LOOPBK_SHIFT 7 /**< Shift value for LEUART_LOOPBK */
<> 128:9bcdf88f62b0 122 #define _LEUART_CTRL_LOOPBK_MASK 0x80UL /**< Bit mask for LEUART_LOOPBK */
<> 128:9bcdf88f62b0 123 #define _LEUART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 124 #define LEUART_CTRL_LOOPBK_DEFAULT (_LEUART_CTRL_LOOPBK_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 125 #define LEUART_CTRL_SFUBRX (0x1UL << 8) /**< Start-Frame UnBlock RX */
<> 128:9bcdf88f62b0 126 #define _LEUART_CTRL_SFUBRX_SHIFT 8 /**< Shift value for LEUART_SFUBRX */
<> 128:9bcdf88f62b0 127 #define _LEUART_CTRL_SFUBRX_MASK 0x100UL /**< Bit mask for LEUART_SFUBRX */
<> 128:9bcdf88f62b0 128 #define _LEUART_CTRL_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 129 #define LEUART_CTRL_SFUBRX_DEFAULT (_LEUART_CTRL_SFUBRX_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 130 #define LEUART_CTRL_MPM (0x1UL << 9) /**< Multi-Processor Mode */
<> 128:9bcdf88f62b0 131 #define _LEUART_CTRL_MPM_SHIFT 9 /**< Shift value for LEUART_MPM */
<> 128:9bcdf88f62b0 132 #define _LEUART_CTRL_MPM_MASK 0x200UL /**< Bit mask for LEUART_MPM */
<> 128:9bcdf88f62b0 133 #define _LEUART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 134 #define LEUART_CTRL_MPM_DEFAULT (_LEUART_CTRL_MPM_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 135 #define LEUART_CTRL_MPAB (0x1UL << 10) /**< Multi-Processor Address-Bit */
<> 128:9bcdf88f62b0 136 #define _LEUART_CTRL_MPAB_SHIFT 10 /**< Shift value for LEUART_MPAB */
<> 128:9bcdf88f62b0 137 #define _LEUART_CTRL_MPAB_MASK 0x400UL /**< Bit mask for LEUART_MPAB */
<> 128:9bcdf88f62b0 138 #define _LEUART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 139 #define LEUART_CTRL_MPAB_DEFAULT (_LEUART_CTRL_MPAB_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 140 #define LEUART_CTRL_BIT8DV (0x1UL << 11) /**< Bit 8 Default Value */
<> 128:9bcdf88f62b0 141 #define _LEUART_CTRL_BIT8DV_SHIFT 11 /**< Shift value for LEUART_BIT8DV */
<> 128:9bcdf88f62b0 142 #define _LEUART_CTRL_BIT8DV_MASK 0x800UL /**< Bit mask for LEUART_BIT8DV */
<> 128:9bcdf88f62b0 143 #define _LEUART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 144 #define LEUART_CTRL_BIT8DV_DEFAULT (_LEUART_CTRL_BIT8DV_DEFAULT << 11) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 145 #define LEUART_CTRL_RXDMAWU (0x1UL << 12) /**< RX DMA Wakeup */
<> 128:9bcdf88f62b0 146 #define _LEUART_CTRL_RXDMAWU_SHIFT 12 /**< Shift value for LEUART_RXDMAWU */
<> 128:9bcdf88f62b0 147 #define _LEUART_CTRL_RXDMAWU_MASK 0x1000UL /**< Bit mask for LEUART_RXDMAWU */
<> 128:9bcdf88f62b0 148 #define _LEUART_CTRL_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 149 #define LEUART_CTRL_RXDMAWU_DEFAULT (_LEUART_CTRL_RXDMAWU_DEFAULT << 12) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 150 #define LEUART_CTRL_TXDMAWU (0x1UL << 13) /**< TX DMA Wakeup */
<> 128:9bcdf88f62b0 151 #define _LEUART_CTRL_TXDMAWU_SHIFT 13 /**< Shift value for LEUART_TXDMAWU */
<> 128:9bcdf88f62b0 152 #define _LEUART_CTRL_TXDMAWU_MASK 0x2000UL /**< Bit mask for LEUART_TXDMAWU */
<> 128:9bcdf88f62b0 153 #define _LEUART_CTRL_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 154 #define LEUART_CTRL_TXDMAWU_DEFAULT (_LEUART_CTRL_TXDMAWU_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 155 #define _LEUART_CTRL_TXDELAY_SHIFT 14 /**< Shift value for LEUART_TXDELAY */
<> 128:9bcdf88f62b0 156 #define _LEUART_CTRL_TXDELAY_MASK 0xC000UL /**< Bit mask for LEUART_TXDELAY */
<> 128:9bcdf88f62b0 157 #define _LEUART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 158 #define _LEUART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */
<> 128:9bcdf88f62b0 159 #define _LEUART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for LEUART_CTRL */
<> 128:9bcdf88f62b0 160 #define _LEUART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for LEUART_CTRL */
<> 128:9bcdf88f62b0 161 #define _LEUART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for LEUART_CTRL */
<> 128:9bcdf88f62b0 162 #define LEUART_CTRL_TXDELAY_DEFAULT (_LEUART_CTRL_TXDELAY_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_CTRL */
<> 128:9bcdf88f62b0 163 #define LEUART_CTRL_TXDELAY_NONE (_LEUART_CTRL_TXDELAY_NONE << 14) /**< Shifted mode NONE for LEUART_CTRL */
<> 128:9bcdf88f62b0 164 #define LEUART_CTRL_TXDELAY_SINGLE (_LEUART_CTRL_TXDELAY_SINGLE << 14) /**< Shifted mode SINGLE for LEUART_CTRL */
<> 128:9bcdf88f62b0 165 #define LEUART_CTRL_TXDELAY_DOUBLE (_LEUART_CTRL_TXDELAY_DOUBLE << 14) /**< Shifted mode DOUBLE for LEUART_CTRL */
<> 128:9bcdf88f62b0 166 #define LEUART_CTRL_TXDELAY_TRIPLE (_LEUART_CTRL_TXDELAY_TRIPLE << 14) /**< Shifted mode TRIPLE for LEUART_CTRL */
<> 128:9bcdf88f62b0 167
<> 128:9bcdf88f62b0 168 /* Bit fields for LEUART CMD */
<> 128:9bcdf88f62b0 169 #define _LEUART_CMD_RESETVALUE 0x00000000UL /**< Default value for LEUART_CMD */
<> 128:9bcdf88f62b0 170 #define _LEUART_CMD_MASK 0x000000FFUL /**< Mask for LEUART_CMD */
<> 128:9bcdf88f62b0 171 #define LEUART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */
<> 128:9bcdf88f62b0 172 #define _LEUART_CMD_RXEN_SHIFT 0 /**< Shift value for LEUART_RXEN */
<> 128:9bcdf88f62b0 173 #define _LEUART_CMD_RXEN_MASK 0x1UL /**< Bit mask for LEUART_RXEN */
<> 128:9bcdf88f62b0 174 #define _LEUART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
<> 128:9bcdf88f62b0 175 #define LEUART_CMD_RXEN_DEFAULT (_LEUART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CMD */
<> 128:9bcdf88f62b0 176 #define LEUART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */
<> 128:9bcdf88f62b0 177 #define _LEUART_CMD_RXDIS_SHIFT 1 /**< Shift value for LEUART_RXDIS */
<> 128:9bcdf88f62b0 178 #define _LEUART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for LEUART_RXDIS */
<> 128:9bcdf88f62b0 179 #define _LEUART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
<> 128:9bcdf88f62b0 180 #define LEUART_CMD_RXDIS_DEFAULT (_LEUART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CMD */
<> 128:9bcdf88f62b0 181 #define LEUART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */
<> 128:9bcdf88f62b0 182 #define _LEUART_CMD_TXEN_SHIFT 2 /**< Shift value for LEUART_TXEN */
<> 128:9bcdf88f62b0 183 #define _LEUART_CMD_TXEN_MASK 0x4UL /**< Bit mask for LEUART_TXEN */
<> 128:9bcdf88f62b0 184 #define _LEUART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
<> 128:9bcdf88f62b0 185 #define LEUART_CMD_TXEN_DEFAULT (_LEUART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CMD */
<> 128:9bcdf88f62b0 186 #define LEUART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */
<> 128:9bcdf88f62b0 187 #define _LEUART_CMD_TXDIS_SHIFT 3 /**< Shift value for LEUART_TXDIS */
<> 128:9bcdf88f62b0 188 #define _LEUART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for LEUART_TXDIS */
<> 128:9bcdf88f62b0 189 #define _LEUART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
<> 128:9bcdf88f62b0 190 #define LEUART_CMD_TXDIS_DEFAULT (_LEUART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CMD */
<> 128:9bcdf88f62b0 191 #define LEUART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */
<> 128:9bcdf88f62b0 192 #define _LEUART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for LEUART_RXBLOCKEN */
<> 128:9bcdf88f62b0 193 #define _LEUART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for LEUART_RXBLOCKEN */
<> 128:9bcdf88f62b0 194 #define _LEUART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
<> 128:9bcdf88f62b0 195 #define LEUART_CMD_RXBLOCKEN_DEFAULT (_LEUART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CMD */
<> 128:9bcdf88f62b0 196 #define LEUART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */
<> 128:9bcdf88f62b0 197 #define _LEUART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for LEUART_RXBLOCKDIS */
<> 128:9bcdf88f62b0 198 #define _LEUART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for LEUART_RXBLOCKDIS */
<> 128:9bcdf88f62b0 199 #define _LEUART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
<> 128:9bcdf88f62b0 200 #define LEUART_CMD_RXBLOCKDIS_DEFAULT (_LEUART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CMD */
<> 128:9bcdf88f62b0 201 #define LEUART_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
<> 128:9bcdf88f62b0 202 #define _LEUART_CMD_CLEARTX_SHIFT 6 /**< Shift value for LEUART_CLEARTX */
<> 128:9bcdf88f62b0 203 #define _LEUART_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for LEUART_CLEARTX */
<> 128:9bcdf88f62b0 204 #define _LEUART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
<> 128:9bcdf88f62b0 205 #define LEUART_CMD_CLEARTX_DEFAULT (_LEUART_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CMD */
<> 128:9bcdf88f62b0 206 #define LEUART_CMD_CLEARRX (0x1UL << 7) /**< Clear RX */
<> 128:9bcdf88f62b0 207 #define _LEUART_CMD_CLEARRX_SHIFT 7 /**< Shift value for LEUART_CLEARRX */
<> 128:9bcdf88f62b0 208 #define _LEUART_CMD_CLEARRX_MASK 0x80UL /**< Bit mask for LEUART_CLEARRX */
<> 128:9bcdf88f62b0 209 #define _LEUART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
<> 128:9bcdf88f62b0 210 #define LEUART_CMD_CLEARRX_DEFAULT (_LEUART_CMD_CLEARRX_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CMD */
<> 128:9bcdf88f62b0 211
<> 128:9bcdf88f62b0 212 /* Bit fields for LEUART STATUS */
<> 128:9bcdf88f62b0 213 #define _LEUART_STATUS_RESETVALUE 0x00000010UL /**< Default value for LEUART_STATUS */
<> 128:9bcdf88f62b0 214 #define _LEUART_STATUS_MASK 0x0000003FUL /**< Mask for LEUART_STATUS */
<> 128:9bcdf88f62b0 215 #define LEUART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */
<> 128:9bcdf88f62b0 216 #define _LEUART_STATUS_RXENS_SHIFT 0 /**< Shift value for LEUART_RXENS */
<> 128:9bcdf88f62b0 217 #define _LEUART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for LEUART_RXENS */
<> 128:9bcdf88f62b0 218 #define _LEUART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
<> 128:9bcdf88f62b0 219 #define LEUART_STATUS_RXENS_DEFAULT (_LEUART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STATUS */
<> 128:9bcdf88f62b0 220 #define LEUART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */
<> 128:9bcdf88f62b0 221 #define _LEUART_STATUS_TXENS_SHIFT 1 /**< Shift value for LEUART_TXENS */
<> 128:9bcdf88f62b0 222 #define _LEUART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for LEUART_TXENS */
<> 128:9bcdf88f62b0 223 #define _LEUART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
<> 128:9bcdf88f62b0 224 #define LEUART_STATUS_TXENS_DEFAULT (_LEUART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_STATUS */
<> 128:9bcdf88f62b0 225 #define LEUART_STATUS_RXBLOCK (0x1UL << 2) /**< Block Incoming Data */
<> 128:9bcdf88f62b0 226 #define _LEUART_STATUS_RXBLOCK_SHIFT 2 /**< Shift value for LEUART_RXBLOCK */
<> 128:9bcdf88f62b0 227 #define _LEUART_STATUS_RXBLOCK_MASK 0x4UL /**< Bit mask for LEUART_RXBLOCK */
<> 128:9bcdf88f62b0 228 #define _LEUART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
<> 128:9bcdf88f62b0 229 #define LEUART_STATUS_RXBLOCK_DEFAULT (_LEUART_STATUS_RXBLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_STATUS */
<> 128:9bcdf88f62b0 230 #define LEUART_STATUS_TXC (0x1UL << 3) /**< TX Complete */
<> 128:9bcdf88f62b0 231 #define _LEUART_STATUS_TXC_SHIFT 3 /**< Shift value for LEUART_TXC */
<> 128:9bcdf88f62b0 232 #define _LEUART_STATUS_TXC_MASK 0x8UL /**< Bit mask for LEUART_TXC */
<> 128:9bcdf88f62b0 233 #define _LEUART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
<> 128:9bcdf88f62b0 234 #define LEUART_STATUS_TXC_DEFAULT (_LEUART_STATUS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_STATUS */
<> 128:9bcdf88f62b0 235 #define LEUART_STATUS_TXBL (0x1UL << 4) /**< TX Buffer Level */
<> 128:9bcdf88f62b0 236 #define _LEUART_STATUS_TXBL_SHIFT 4 /**< Shift value for LEUART_TXBL */
<> 128:9bcdf88f62b0 237 #define _LEUART_STATUS_TXBL_MASK 0x10UL /**< Bit mask for LEUART_TXBL */
<> 128:9bcdf88f62b0 238 #define _LEUART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */
<> 128:9bcdf88f62b0 239 #define LEUART_STATUS_TXBL_DEFAULT (_LEUART_STATUS_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_STATUS */
<> 128:9bcdf88f62b0 240 #define LEUART_STATUS_RXDATAV (0x1UL << 5) /**< RX Data Valid */
<> 128:9bcdf88f62b0 241 #define _LEUART_STATUS_RXDATAV_SHIFT 5 /**< Shift value for LEUART_RXDATAV */
<> 128:9bcdf88f62b0 242 #define _LEUART_STATUS_RXDATAV_MASK 0x20UL /**< Bit mask for LEUART_RXDATAV */
<> 128:9bcdf88f62b0 243 #define _LEUART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
<> 128:9bcdf88f62b0 244 #define LEUART_STATUS_RXDATAV_DEFAULT (_LEUART_STATUS_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_STATUS */
<> 128:9bcdf88f62b0 245
<> 128:9bcdf88f62b0 246 /* Bit fields for LEUART CLKDIV */
<> 128:9bcdf88f62b0 247 #define _LEUART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for LEUART_CLKDIV */
<> 128:9bcdf88f62b0 248 #define _LEUART_CLKDIV_MASK 0x00007FF8UL /**< Mask for LEUART_CLKDIV */
<> 128:9bcdf88f62b0 249 #define _LEUART_CLKDIV_DIV_SHIFT 3 /**< Shift value for LEUART_DIV */
<> 128:9bcdf88f62b0 250 #define _LEUART_CLKDIV_DIV_MASK 0x7FF8UL /**< Bit mask for LEUART_DIV */
<> 128:9bcdf88f62b0 251 #define _LEUART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CLKDIV */
<> 128:9bcdf88f62b0 252 #define LEUART_CLKDIV_DIV_DEFAULT (_LEUART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CLKDIV */
<> 128:9bcdf88f62b0 253
<> 128:9bcdf88f62b0 254 /* Bit fields for LEUART STARTFRAME */
<> 128:9bcdf88f62b0 255 #define _LEUART_STARTFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_STARTFRAME */
<> 128:9bcdf88f62b0 256 #define _LEUART_STARTFRAME_MASK 0x000001FFUL /**< Mask for LEUART_STARTFRAME */
<> 128:9bcdf88f62b0 257 #define _LEUART_STARTFRAME_STARTFRAME_SHIFT 0 /**< Shift value for LEUART_STARTFRAME */
<> 128:9bcdf88f62b0 258 #define _LEUART_STARTFRAME_STARTFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_STARTFRAME */
<> 128:9bcdf88f62b0 259 #define _LEUART_STARTFRAME_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STARTFRAME */
<> 128:9bcdf88f62b0 260 #define LEUART_STARTFRAME_STARTFRAME_DEFAULT (_LEUART_STARTFRAME_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STARTFRAME */
<> 128:9bcdf88f62b0 261
<> 128:9bcdf88f62b0 262 /* Bit fields for LEUART SIGFRAME */
<> 128:9bcdf88f62b0 263 #define _LEUART_SIGFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_SIGFRAME */
<> 128:9bcdf88f62b0 264 #define _LEUART_SIGFRAME_MASK 0x000001FFUL /**< Mask for LEUART_SIGFRAME */
<> 128:9bcdf88f62b0 265 #define _LEUART_SIGFRAME_SIGFRAME_SHIFT 0 /**< Shift value for LEUART_SIGFRAME */
<> 128:9bcdf88f62b0 266 #define _LEUART_SIGFRAME_SIGFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_SIGFRAME */
<> 128:9bcdf88f62b0 267 #define _LEUART_SIGFRAME_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SIGFRAME */
<> 128:9bcdf88f62b0 268 #define LEUART_SIGFRAME_SIGFRAME_DEFAULT (_LEUART_SIGFRAME_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SIGFRAME */
<> 128:9bcdf88f62b0 269
<> 128:9bcdf88f62b0 270 /* Bit fields for LEUART RXDATAX */
<> 128:9bcdf88f62b0 271 #define _LEUART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAX */
<> 128:9bcdf88f62b0 272 #define _LEUART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAX */
<> 128:9bcdf88f62b0 273 #define _LEUART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */
<> 128:9bcdf88f62b0 274 #define _LEUART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATA */
<> 128:9bcdf88f62b0 275 #define _LEUART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
<> 128:9bcdf88f62b0 276 #define LEUART_RXDATAX_RXDATA_DEFAULT (_LEUART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
<> 128:9bcdf88f62b0 277 #define LEUART_RXDATAX_PERR (0x1UL << 14) /**< Receive Data Parity Error */
<> 128:9bcdf88f62b0 278 #define _LEUART_RXDATAX_PERR_SHIFT 14 /**< Shift value for LEUART_PERR */
<> 128:9bcdf88f62b0 279 #define _LEUART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for LEUART_PERR */
<> 128:9bcdf88f62b0 280 #define _LEUART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
<> 128:9bcdf88f62b0 281 #define LEUART_RXDATAX_PERR_DEFAULT (_LEUART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
<> 128:9bcdf88f62b0 282 #define LEUART_RXDATAX_FERR (0x1UL << 15) /**< Receive Data Framing Error */
<> 128:9bcdf88f62b0 283 #define _LEUART_RXDATAX_FERR_SHIFT 15 /**< Shift value for LEUART_FERR */
<> 128:9bcdf88f62b0 284 #define _LEUART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for LEUART_FERR */
<> 128:9bcdf88f62b0 285 #define _LEUART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
<> 128:9bcdf88f62b0 286 #define LEUART_RXDATAX_FERR_DEFAULT (_LEUART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
<> 128:9bcdf88f62b0 287
<> 128:9bcdf88f62b0 288 /* Bit fields for LEUART RXDATA */
<> 128:9bcdf88f62b0 289 #define _LEUART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATA */
<> 128:9bcdf88f62b0 290 #define _LEUART_RXDATA_MASK 0x000000FFUL /**< Mask for LEUART_RXDATA */
<> 128:9bcdf88f62b0 291 #define _LEUART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */
<> 128:9bcdf88f62b0 292 #define _LEUART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for LEUART_RXDATA */
<> 128:9bcdf88f62b0 293 #define _LEUART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATA */
<> 128:9bcdf88f62b0 294 #define LEUART_RXDATA_RXDATA_DEFAULT (_LEUART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATA */
<> 128:9bcdf88f62b0 295
<> 128:9bcdf88f62b0 296 /* Bit fields for LEUART RXDATAXP */
<> 128:9bcdf88f62b0 297 #define _LEUART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAXP */
<> 128:9bcdf88f62b0 298 #define _LEUART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAXP */
<> 128:9bcdf88f62b0 299 #define _LEUART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for LEUART_RXDATAP */
<> 128:9bcdf88f62b0 300 #define _LEUART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATAP */
<> 128:9bcdf88f62b0 301 #define _LEUART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
<> 128:9bcdf88f62b0 302 #define LEUART_RXDATAXP_RXDATAP_DEFAULT (_LEUART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
<> 128:9bcdf88f62b0 303 #define LEUART_RXDATAXP_PERRP (0x1UL << 14) /**< Receive Data Parity Error Peek */
<> 128:9bcdf88f62b0 304 #define _LEUART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for LEUART_PERRP */
<> 128:9bcdf88f62b0 305 #define _LEUART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for LEUART_PERRP */
<> 128:9bcdf88f62b0 306 #define _LEUART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
<> 128:9bcdf88f62b0 307 #define LEUART_RXDATAXP_PERRP_DEFAULT (_LEUART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
<> 128:9bcdf88f62b0 308 #define LEUART_RXDATAXP_FERRP (0x1UL << 15) /**< Receive Data Framing Error Peek */
<> 128:9bcdf88f62b0 309 #define _LEUART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for LEUART_FERRP */
<> 128:9bcdf88f62b0 310 #define _LEUART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for LEUART_FERRP */
<> 128:9bcdf88f62b0 311 #define _LEUART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
<> 128:9bcdf88f62b0 312 #define LEUART_RXDATAXP_FERRP_DEFAULT (_LEUART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
<> 128:9bcdf88f62b0 313
<> 128:9bcdf88f62b0 314 /* Bit fields for LEUART TXDATAX */
<> 128:9bcdf88f62b0 315 #define _LEUART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATAX */
<> 128:9bcdf88f62b0 316 #define _LEUART_TXDATAX_MASK 0x0000E1FFUL /**< Mask for LEUART_TXDATAX */
<> 128:9bcdf88f62b0 317 #define _LEUART_TXDATAX_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */
<> 128:9bcdf88f62b0 318 #define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_TXDATA */
<> 128:9bcdf88f62b0 319 #define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
<> 128:9bcdf88f62b0 320 #define LEUART_TXDATAX_TXDATA_DEFAULT (_LEUART_TXDATAX_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
<> 128:9bcdf88f62b0 321 #define LEUART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */
<> 128:9bcdf88f62b0 322 #define _LEUART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for LEUART_TXBREAK */
<> 128:9bcdf88f62b0 323 #define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for LEUART_TXBREAK */
<> 128:9bcdf88f62b0 324 #define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
<> 128:9bcdf88f62b0 325 #define LEUART_TXDATAX_TXBREAK_DEFAULT (_LEUART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
<> 128:9bcdf88f62b0 326 #define LEUART_TXDATAX_TXDISAT (0x1UL << 14) /**< Disable TX After Transmission */
<> 128:9bcdf88f62b0 327 #define _LEUART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for LEUART_TXDISAT */
<> 128:9bcdf88f62b0 328 #define _LEUART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for LEUART_TXDISAT */
<> 128:9bcdf88f62b0 329 #define _LEUART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
<> 128:9bcdf88f62b0 330 #define LEUART_TXDATAX_TXDISAT_DEFAULT (_LEUART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
<> 128:9bcdf88f62b0 331 #define LEUART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */
<> 128:9bcdf88f62b0 332 #define _LEUART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for LEUART_RXENAT */
<> 128:9bcdf88f62b0 333 #define _LEUART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for LEUART_RXENAT */
<> 128:9bcdf88f62b0 334 #define _LEUART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
<> 128:9bcdf88f62b0 335 #define LEUART_TXDATAX_RXENAT_DEFAULT (_LEUART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
<> 128:9bcdf88f62b0 336
<> 128:9bcdf88f62b0 337 /* Bit fields for LEUART TXDATA */
<> 128:9bcdf88f62b0 338 #define _LEUART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATA */
<> 128:9bcdf88f62b0 339 #define _LEUART_TXDATA_MASK 0x000000FFUL /**< Mask for LEUART_TXDATA */
<> 128:9bcdf88f62b0 340 #define _LEUART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */
<> 128:9bcdf88f62b0 341 #define _LEUART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for LEUART_TXDATA */
<> 128:9bcdf88f62b0 342 #define _LEUART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATA */
<> 128:9bcdf88f62b0 343 #define LEUART_TXDATA_TXDATA_DEFAULT (_LEUART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATA */
<> 128:9bcdf88f62b0 344
<> 128:9bcdf88f62b0 345 /* Bit fields for LEUART IF */
<> 128:9bcdf88f62b0 346 #define _LEUART_IF_RESETVALUE 0x00000002UL /**< Default value for LEUART_IF */
<> 128:9bcdf88f62b0 347 #define _LEUART_IF_MASK 0x000007FFUL /**< Mask for LEUART_IF */
<> 128:9bcdf88f62b0 348 #define LEUART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */
<> 128:9bcdf88f62b0 349 #define _LEUART_IF_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
<> 128:9bcdf88f62b0 350 #define _LEUART_IF_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
<> 128:9bcdf88f62b0 351 #define _LEUART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 352 #define LEUART_IF_TXC_DEFAULT (_LEUART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 353 #define LEUART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */
<> 128:9bcdf88f62b0 354 #define _LEUART_IF_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */
<> 128:9bcdf88f62b0 355 #define _LEUART_IF_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */
<> 128:9bcdf88f62b0 356 #define _LEUART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 357 #define LEUART_IF_TXBL_DEFAULT (_LEUART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 358 #define LEUART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */
<> 128:9bcdf88f62b0 359 #define _LEUART_IF_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */
<> 128:9bcdf88f62b0 360 #define _LEUART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */
<> 128:9bcdf88f62b0 361 #define _LEUART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 362 #define LEUART_IF_RXDATAV_DEFAULT (_LEUART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 363 #define LEUART_IF_RXOF (0x1UL << 3) /**< RX Overflow Interrupt Flag */
<> 128:9bcdf88f62b0 364 #define _LEUART_IF_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
<> 128:9bcdf88f62b0 365 #define _LEUART_IF_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
<> 128:9bcdf88f62b0 366 #define _LEUART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 367 #define LEUART_IF_RXOF_DEFAULT (_LEUART_IF_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 368 #define LEUART_IF_RXUF (0x1UL << 4) /**< RX Underflow Interrupt Flag */
<> 128:9bcdf88f62b0 369 #define _LEUART_IF_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
<> 128:9bcdf88f62b0 370 #define _LEUART_IF_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
<> 128:9bcdf88f62b0 371 #define _LEUART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 372 #define LEUART_IF_RXUF_DEFAULT (_LEUART_IF_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 373 #define LEUART_IF_TXOF (0x1UL << 5) /**< TX Overflow Interrupt Flag */
<> 128:9bcdf88f62b0 374 #define _LEUART_IF_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
<> 128:9bcdf88f62b0 375 #define _LEUART_IF_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
<> 128:9bcdf88f62b0 376 #define _LEUART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 377 #define LEUART_IF_TXOF_DEFAULT (_LEUART_IF_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 378 #define LEUART_IF_PERR (0x1UL << 6) /**< Parity Error Interrupt Flag */
<> 128:9bcdf88f62b0 379 #define _LEUART_IF_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
<> 128:9bcdf88f62b0 380 #define _LEUART_IF_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
<> 128:9bcdf88f62b0 381 #define _LEUART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 382 #define LEUART_IF_PERR_DEFAULT (_LEUART_IF_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 383 #define LEUART_IF_FERR (0x1UL << 7) /**< Framing Error Interrupt Flag */
<> 128:9bcdf88f62b0 384 #define _LEUART_IF_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
<> 128:9bcdf88f62b0 385 #define _LEUART_IF_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
<> 128:9bcdf88f62b0 386 #define _LEUART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 387 #define LEUART_IF_FERR_DEFAULT (_LEUART_IF_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 388 #define LEUART_IF_MPAF (0x1UL << 8) /**< Multi-Processor Address Frame Interrupt Flag */
<> 128:9bcdf88f62b0 389 #define _LEUART_IF_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
<> 128:9bcdf88f62b0 390 #define _LEUART_IF_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
<> 128:9bcdf88f62b0 391 #define _LEUART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 392 #define LEUART_IF_MPAF_DEFAULT (_LEUART_IF_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 393 #define LEUART_IF_STARTF (0x1UL << 9) /**< Start Frame Interrupt Flag */
<> 128:9bcdf88f62b0 394 #define _LEUART_IF_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
<> 128:9bcdf88f62b0 395 #define _LEUART_IF_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
<> 128:9bcdf88f62b0 396 #define _LEUART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 397 #define LEUART_IF_STARTF_DEFAULT (_LEUART_IF_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 398 #define LEUART_IF_SIGF (0x1UL << 10) /**< Signal Frame Interrupt Flag */
<> 128:9bcdf88f62b0 399 #define _LEUART_IF_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
<> 128:9bcdf88f62b0 400 #define _LEUART_IF_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
<> 128:9bcdf88f62b0 401 #define _LEUART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 402 #define LEUART_IF_SIGF_DEFAULT (_LEUART_IF_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IF */
<> 128:9bcdf88f62b0 403
<> 128:9bcdf88f62b0 404 /* Bit fields for LEUART IFS */
<> 128:9bcdf88f62b0 405 #define _LEUART_IFS_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFS */
<> 128:9bcdf88f62b0 406 #define _LEUART_IFS_MASK 0x000007F9UL /**< Mask for LEUART_IFS */
<> 128:9bcdf88f62b0 407 #define LEUART_IFS_TXC (0x1UL << 0) /**< Set TX Complete Interrupt Flag */
<> 128:9bcdf88f62b0 408 #define _LEUART_IFS_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
<> 128:9bcdf88f62b0 409 #define _LEUART_IFS_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
<> 128:9bcdf88f62b0 410 #define _LEUART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
<> 128:9bcdf88f62b0 411 #define LEUART_IFS_TXC_DEFAULT (_LEUART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFS */
<> 128:9bcdf88f62b0 412 #define LEUART_IFS_RXOF (0x1UL << 3) /**< Set RX Overflow Interrupt Flag */
<> 128:9bcdf88f62b0 413 #define _LEUART_IFS_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
<> 128:9bcdf88f62b0 414 #define _LEUART_IFS_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
<> 128:9bcdf88f62b0 415 #define _LEUART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
<> 128:9bcdf88f62b0 416 #define LEUART_IFS_RXOF_DEFAULT (_LEUART_IFS_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFS */
<> 128:9bcdf88f62b0 417 #define LEUART_IFS_RXUF (0x1UL << 4) /**< Set RX Underflow Interrupt Flag */
<> 128:9bcdf88f62b0 418 #define _LEUART_IFS_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
<> 128:9bcdf88f62b0 419 #define _LEUART_IFS_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
<> 128:9bcdf88f62b0 420 #define _LEUART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
<> 128:9bcdf88f62b0 421 #define LEUART_IFS_RXUF_DEFAULT (_LEUART_IFS_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFS */
<> 128:9bcdf88f62b0 422 #define LEUART_IFS_TXOF (0x1UL << 5) /**< Set TX Overflow Interrupt Flag */
<> 128:9bcdf88f62b0 423 #define _LEUART_IFS_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
<> 128:9bcdf88f62b0 424 #define _LEUART_IFS_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
<> 128:9bcdf88f62b0 425 #define _LEUART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
<> 128:9bcdf88f62b0 426 #define LEUART_IFS_TXOF_DEFAULT (_LEUART_IFS_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFS */
<> 128:9bcdf88f62b0 427 #define LEUART_IFS_PERR (0x1UL << 6) /**< Set Parity Error Interrupt Flag */
<> 128:9bcdf88f62b0 428 #define _LEUART_IFS_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
<> 128:9bcdf88f62b0 429 #define _LEUART_IFS_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
<> 128:9bcdf88f62b0 430 #define _LEUART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
<> 128:9bcdf88f62b0 431 #define LEUART_IFS_PERR_DEFAULT (_LEUART_IFS_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFS */
<> 128:9bcdf88f62b0 432 #define LEUART_IFS_FERR (0x1UL << 7) /**< Set Framing Error Interrupt Flag */
<> 128:9bcdf88f62b0 433 #define _LEUART_IFS_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
<> 128:9bcdf88f62b0 434 #define _LEUART_IFS_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
<> 128:9bcdf88f62b0 435 #define _LEUART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
<> 128:9bcdf88f62b0 436 #define LEUART_IFS_FERR_DEFAULT (_LEUART_IFS_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFS */
<> 128:9bcdf88f62b0 437 #define LEUART_IFS_MPAF (0x1UL << 8) /**< Set Multi-Processor Address Frame Interrupt Flag */
<> 128:9bcdf88f62b0 438 #define _LEUART_IFS_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
<> 128:9bcdf88f62b0 439 #define _LEUART_IFS_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
<> 128:9bcdf88f62b0 440 #define _LEUART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
<> 128:9bcdf88f62b0 441 #define LEUART_IFS_MPAF_DEFAULT (_LEUART_IFS_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFS */
<> 128:9bcdf88f62b0 442 #define LEUART_IFS_STARTF (0x1UL << 9) /**< Set Start Frame Interrupt Flag */
<> 128:9bcdf88f62b0 443 #define _LEUART_IFS_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
<> 128:9bcdf88f62b0 444 #define _LEUART_IFS_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
<> 128:9bcdf88f62b0 445 #define _LEUART_IFS_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
<> 128:9bcdf88f62b0 446 #define LEUART_IFS_STARTF_DEFAULT (_LEUART_IFS_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFS */
<> 128:9bcdf88f62b0 447 #define LEUART_IFS_SIGF (0x1UL << 10) /**< Set Signal Frame Interrupt Flag */
<> 128:9bcdf88f62b0 448 #define _LEUART_IFS_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
<> 128:9bcdf88f62b0 449 #define _LEUART_IFS_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
<> 128:9bcdf88f62b0 450 #define _LEUART_IFS_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
<> 128:9bcdf88f62b0 451 #define LEUART_IFS_SIGF_DEFAULT (_LEUART_IFS_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFS */
<> 128:9bcdf88f62b0 452
<> 128:9bcdf88f62b0 453 /* Bit fields for LEUART IFC */
<> 128:9bcdf88f62b0 454 #define _LEUART_IFC_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFC */
<> 128:9bcdf88f62b0 455 #define _LEUART_IFC_MASK 0x000007F9UL /**< Mask for LEUART_IFC */
<> 128:9bcdf88f62b0 456 #define LEUART_IFC_TXC (0x1UL << 0) /**< Clear TX Complete Interrupt Flag */
<> 128:9bcdf88f62b0 457 #define _LEUART_IFC_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
<> 128:9bcdf88f62b0 458 #define _LEUART_IFC_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
<> 128:9bcdf88f62b0 459 #define _LEUART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
<> 128:9bcdf88f62b0 460 #define LEUART_IFC_TXC_DEFAULT (_LEUART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFC */
<> 128:9bcdf88f62b0 461 #define LEUART_IFC_RXOF (0x1UL << 3) /**< Clear RX Overflow Interrupt Flag */
<> 128:9bcdf88f62b0 462 #define _LEUART_IFC_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
<> 128:9bcdf88f62b0 463 #define _LEUART_IFC_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
<> 128:9bcdf88f62b0 464 #define _LEUART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
<> 128:9bcdf88f62b0 465 #define LEUART_IFC_RXOF_DEFAULT (_LEUART_IFC_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFC */
<> 128:9bcdf88f62b0 466 #define LEUART_IFC_RXUF (0x1UL << 4) /**< Clear RX Underflow Interrupt Flag */
<> 128:9bcdf88f62b0 467 #define _LEUART_IFC_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
<> 128:9bcdf88f62b0 468 #define _LEUART_IFC_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
<> 128:9bcdf88f62b0 469 #define _LEUART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
<> 128:9bcdf88f62b0 470 #define LEUART_IFC_RXUF_DEFAULT (_LEUART_IFC_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFC */
<> 128:9bcdf88f62b0 471 #define LEUART_IFC_TXOF (0x1UL << 5) /**< Clear TX Overflow Interrupt Flag */
<> 128:9bcdf88f62b0 472 #define _LEUART_IFC_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
<> 128:9bcdf88f62b0 473 #define _LEUART_IFC_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
<> 128:9bcdf88f62b0 474 #define _LEUART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
<> 128:9bcdf88f62b0 475 #define LEUART_IFC_TXOF_DEFAULT (_LEUART_IFC_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFC */
<> 128:9bcdf88f62b0 476 #define LEUART_IFC_PERR (0x1UL << 6) /**< Clear Parity Error Interrupt Flag */
<> 128:9bcdf88f62b0 477 #define _LEUART_IFC_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
<> 128:9bcdf88f62b0 478 #define _LEUART_IFC_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
<> 128:9bcdf88f62b0 479 #define _LEUART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
<> 128:9bcdf88f62b0 480 #define LEUART_IFC_PERR_DEFAULT (_LEUART_IFC_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFC */
<> 128:9bcdf88f62b0 481 #define LEUART_IFC_FERR (0x1UL << 7) /**< Clear Framing Error Interrupt Flag */
<> 128:9bcdf88f62b0 482 #define _LEUART_IFC_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
<> 128:9bcdf88f62b0 483 #define _LEUART_IFC_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
<> 128:9bcdf88f62b0 484 #define _LEUART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
<> 128:9bcdf88f62b0 485 #define LEUART_IFC_FERR_DEFAULT (_LEUART_IFC_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFC */
<> 128:9bcdf88f62b0 486 #define LEUART_IFC_MPAF (0x1UL << 8) /**< Clear Multi-Processor Address Frame Interrupt Flag */
<> 128:9bcdf88f62b0 487 #define _LEUART_IFC_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
<> 128:9bcdf88f62b0 488 #define _LEUART_IFC_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
<> 128:9bcdf88f62b0 489 #define _LEUART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
<> 128:9bcdf88f62b0 490 #define LEUART_IFC_MPAF_DEFAULT (_LEUART_IFC_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFC */
<> 128:9bcdf88f62b0 491 #define LEUART_IFC_STARTF (0x1UL << 9) /**< Clear Start-Frame Interrupt Flag */
<> 128:9bcdf88f62b0 492 #define _LEUART_IFC_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
<> 128:9bcdf88f62b0 493 #define _LEUART_IFC_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
<> 128:9bcdf88f62b0 494 #define _LEUART_IFC_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
<> 128:9bcdf88f62b0 495 #define LEUART_IFC_STARTF_DEFAULT (_LEUART_IFC_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFC */
<> 128:9bcdf88f62b0 496 #define LEUART_IFC_SIGF (0x1UL << 10) /**< Clear Signal-Frame Interrupt Flag */
<> 128:9bcdf88f62b0 497 #define _LEUART_IFC_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
<> 128:9bcdf88f62b0 498 #define _LEUART_IFC_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
<> 128:9bcdf88f62b0 499 #define _LEUART_IFC_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
<> 128:9bcdf88f62b0 500 #define LEUART_IFC_SIGF_DEFAULT (_LEUART_IFC_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFC */
<> 128:9bcdf88f62b0 501
<> 128:9bcdf88f62b0 502 /* Bit fields for LEUART IEN */
<> 128:9bcdf88f62b0 503 #define _LEUART_IEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_IEN */
<> 128:9bcdf88f62b0 504 #define _LEUART_IEN_MASK 0x000007FFUL /**< Mask for LEUART_IEN */
<> 128:9bcdf88f62b0 505 #define LEUART_IEN_TXC (0x1UL << 0) /**< TX Complete Interrupt Enable */
<> 128:9bcdf88f62b0 506 #define _LEUART_IEN_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
<> 128:9bcdf88f62b0 507 #define _LEUART_IEN_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
<> 128:9bcdf88f62b0 508 #define _LEUART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 509 #define LEUART_IEN_TXC_DEFAULT (_LEUART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 510 #define LEUART_IEN_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Enable */
<> 128:9bcdf88f62b0 511 #define _LEUART_IEN_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */
<> 128:9bcdf88f62b0 512 #define _LEUART_IEN_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */
<> 128:9bcdf88f62b0 513 #define _LEUART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 514 #define LEUART_IEN_TXBL_DEFAULT (_LEUART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 515 #define LEUART_IEN_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Enable */
<> 128:9bcdf88f62b0 516 #define _LEUART_IEN_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */
<> 128:9bcdf88f62b0 517 #define _LEUART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */
<> 128:9bcdf88f62b0 518 #define _LEUART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 519 #define LEUART_IEN_RXDATAV_DEFAULT (_LEUART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 520 #define LEUART_IEN_RXOF (0x1UL << 3) /**< RX Overflow Interrupt Enable */
<> 128:9bcdf88f62b0 521 #define _LEUART_IEN_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
<> 128:9bcdf88f62b0 522 #define _LEUART_IEN_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
<> 128:9bcdf88f62b0 523 #define _LEUART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 524 #define LEUART_IEN_RXOF_DEFAULT (_LEUART_IEN_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 525 #define LEUART_IEN_RXUF (0x1UL << 4) /**< RX Underflow Interrupt Enable */
<> 128:9bcdf88f62b0 526 #define _LEUART_IEN_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
<> 128:9bcdf88f62b0 527 #define _LEUART_IEN_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
<> 128:9bcdf88f62b0 528 #define _LEUART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 529 #define LEUART_IEN_RXUF_DEFAULT (_LEUART_IEN_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 530 #define LEUART_IEN_TXOF (0x1UL << 5) /**< TX Overflow Interrupt Enable */
<> 128:9bcdf88f62b0 531 #define _LEUART_IEN_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
<> 128:9bcdf88f62b0 532 #define _LEUART_IEN_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
<> 128:9bcdf88f62b0 533 #define _LEUART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 534 #define LEUART_IEN_TXOF_DEFAULT (_LEUART_IEN_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 535 #define LEUART_IEN_PERR (0x1UL << 6) /**< Parity Error Interrupt Enable */
<> 128:9bcdf88f62b0 536 #define _LEUART_IEN_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
<> 128:9bcdf88f62b0 537 #define _LEUART_IEN_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
<> 128:9bcdf88f62b0 538 #define _LEUART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 539 #define LEUART_IEN_PERR_DEFAULT (_LEUART_IEN_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 540 #define LEUART_IEN_FERR (0x1UL << 7) /**< Framing Error Interrupt Enable */
<> 128:9bcdf88f62b0 541 #define _LEUART_IEN_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
<> 128:9bcdf88f62b0 542 #define _LEUART_IEN_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
<> 128:9bcdf88f62b0 543 #define _LEUART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 544 #define LEUART_IEN_FERR_DEFAULT (_LEUART_IEN_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 545 #define LEUART_IEN_MPAF (0x1UL << 8) /**< Multi-Processor Address Frame Interrupt Enable */
<> 128:9bcdf88f62b0 546 #define _LEUART_IEN_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
<> 128:9bcdf88f62b0 547 #define _LEUART_IEN_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
<> 128:9bcdf88f62b0 548 #define _LEUART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 549 #define LEUART_IEN_MPAF_DEFAULT (_LEUART_IEN_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 550 #define LEUART_IEN_STARTF (0x1UL << 9) /**< Start Frame Interrupt Enable */
<> 128:9bcdf88f62b0 551 #define _LEUART_IEN_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
<> 128:9bcdf88f62b0 552 #define _LEUART_IEN_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
<> 128:9bcdf88f62b0 553 #define _LEUART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 554 #define LEUART_IEN_STARTF_DEFAULT (_LEUART_IEN_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 555 #define LEUART_IEN_SIGF (0x1UL << 10) /**< Signal Frame Interrupt Enable */
<> 128:9bcdf88f62b0 556 #define _LEUART_IEN_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
<> 128:9bcdf88f62b0 557 #define _LEUART_IEN_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
<> 128:9bcdf88f62b0 558 #define _LEUART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 559 #define LEUART_IEN_SIGF_DEFAULT (_LEUART_IEN_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IEN */
<> 128:9bcdf88f62b0 560
<> 128:9bcdf88f62b0 561 /* Bit fields for LEUART PULSECTRL */
<> 128:9bcdf88f62b0 562 #define _LEUART_PULSECTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_PULSECTRL */
<> 128:9bcdf88f62b0 563 #define _LEUART_PULSECTRL_MASK 0x0000003FUL /**< Mask for LEUART_PULSECTRL */
<> 128:9bcdf88f62b0 564 #define _LEUART_PULSECTRL_PULSEW_SHIFT 0 /**< Shift value for LEUART_PULSEW */
<> 128:9bcdf88f62b0 565 #define _LEUART_PULSECTRL_PULSEW_MASK 0xFUL /**< Bit mask for LEUART_PULSEW */
<> 128:9bcdf88f62b0 566 #define _LEUART_PULSECTRL_PULSEW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
<> 128:9bcdf88f62b0 567 #define LEUART_PULSECTRL_PULSEW_DEFAULT (_LEUART_PULSECTRL_PULSEW_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
<> 128:9bcdf88f62b0 568 #define LEUART_PULSECTRL_PULSEEN (0x1UL << 4) /**< Pulse Generator/Extender Enable */
<> 128:9bcdf88f62b0 569 #define _LEUART_PULSECTRL_PULSEEN_SHIFT 4 /**< Shift value for LEUART_PULSEEN */
<> 128:9bcdf88f62b0 570 #define _LEUART_PULSECTRL_PULSEEN_MASK 0x10UL /**< Bit mask for LEUART_PULSEEN */
<> 128:9bcdf88f62b0 571 #define _LEUART_PULSECTRL_PULSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
<> 128:9bcdf88f62b0 572 #define LEUART_PULSECTRL_PULSEEN_DEFAULT (_LEUART_PULSECTRL_PULSEEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
<> 128:9bcdf88f62b0 573 #define LEUART_PULSECTRL_PULSEFILT (0x1UL << 5) /**< Pulse Filter */
<> 128:9bcdf88f62b0 574 #define _LEUART_PULSECTRL_PULSEFILT_SHIFT 5 /**< Shift value for LEUART_PULSEFILT */
<> 128:9bcdf88f62b0 575 #define _LEUART_PULSECTRL_PULSEFILT_MASK 0x20UL /**< Bit mask for LEUART_PULSEFILT */
<> 128:9bcdf88f62b0 576 #define _LEUART_PULSECTRL_PULSEFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
<> 128:9bcdf88f62b0 577 #define LEUART_PULSECTRL_PULSEFILT_DEFAULT (_LEUART_PULSECTRL_PULSEFILT_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
<> 128:9bcdf88f62b0 578
<> 128:9bcdf88f62b0 579 /* Bit fields for LEUART FREEZE */
<> 128:9bcdf88f62b0 580 #define _LEUART_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LEUART_FREEZE */
<> 128:9bcdf88f62b0 581 #define _LEUART_FREEZE_MASK 0x00000001UL /**< Mask for LEUART_FREEZE */
<> 128:9bcdf88f62b0 582 #define LEUART_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
<> 128:9bcdf88f62b0 583 #define _LEUART_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LEUART_REGFREEZE */
<> 128:9bcdf88f62b0 584 #define _LEUART_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LEUART_REGFREEZE */
<> 128:9bcdf88f62b0 585 #define _LEUART_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_FREEZE */
<> 128:9bcdf88f62b0 586 #define _LEUART_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LEUART_FREEZE */
<> 128:9bcdf88f62b0 587 #define _LEUART_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LEUART_FREEZE */
<> 128:9bcdf88f62b0 588 #define LEUART_FREEZE_REGFREEZE_DEFAULT (_LEUART_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_FREEZE */
<> 128:9bcdf88f62b0 589 #define LEUART_FREEZE_REGFREEZE_UPDATE (_LEUART_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LEUART_FREEZE */
<> 128:9bcdf88f62b0 590 #define LEUART_FREEZE_REGFREEZE_FREEZE (_LEUART_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LEUART_FREEZE */
<> 128:9bcdf88f62b0 591
<> 128:9bcdf88f62b0 592 /* Bit fields for LEUART SYNCBUSY */
<> 128:9bcdf88f62b0 593 #define _LEUART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LEUART_SYNCBUSY */
<> 128:9bcdf88f62b0 594 #define _LEUART_SYNCBUSY_MASK 0x000000FFUL /**< Mask for LEUART_SYNCBUSY */
<> 128:9bcdf88f62b0 595 #define LEUART_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
<> 128:9bcdf88f62b0 596 #define _LEUART_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LEUART_CTRL */
<> 128:9bcdf88f62b0 597 #define _LEUART_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LEUART_CTRL */
<> 128:9bcdf88f62b0 598 #define _LEUART_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
<> 128:9bcdf88f62b0 599 #define LEUART_SYNCBUSY_CTRL_DEFAULT (_LEUART_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
<> 128:9bcdf88f62b0 600 #define LEUART_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
<> 128:9bcdf88f62b0 601 #define _LEUART_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LEUART_CMD */
<> 128:9bcdf88f62b0 602 #define _LEUART_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LEUART_CMD */
<> 128:9bcdf88f62b0 603 #define _LEUART_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
<> 128:9bcdf88f62b0 604 #define LEUART_SYNCBUSY_CMD_DEFAULT (_LEUART_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
<> 128:9bcdf88f62b0 605 #define LEUART_SYNCBUSY_CLKDIV (0x1UL << 2) /**< CLKDIV Register Busy */
<> 128:9bcdf88f62b0 606 #define _LEUART_SYNCBUSY_CLKDIV_SHIFT 2 /**< Shift value for LEUART_CLKDIV */
<> 128:9bcdf88f62b0 607 #define _LEUART_SYNCBUSY_CLKDIV_MASK 0x4UL /**< Bit mask for LEUART_CLKDIV */
<> 128:9bcdf88f62b0 608 #define _LEUART_SYNCBUSY_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
<> 128:9bcdf88f62b0 609 #define LEUART_SYNCBUSY_CLKDIV_DEFAULT (_LEUART_SYNCBUSY_CLKDIV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
<> 128:9bcdf88f62b0 610 #define LEUART_SYNCBUSY_STARTFRAME (0x1UL << 3) /**< STARTFRAME Register Busy */
<> 128:9bcdf88f62b0 611 #define _LEUART_SYNCBUSY_STARTFRAME_SHIFT 3 /**< Shift value for LEUART_STARTFRAME */
<> 128:9bcdf88f62b0 612 #define _LEUART_SYNCBUSY_STARTFRAME_MASK 0x8UL /**< Bit mask for LEUART_STARTFRAME */
<> 128:9bcdf88f62b0 613 #define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
<> 128:9bcdf88f62b0 614 #define LEUART_SYNCBUSY_STARTFRAME_DEFAULT (_LEUART_SYNCBUSY_STARTFRAME_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
<> 128:9bcdf88f62b0 615 #define LEUART_SYNCBUSY_SIGFRAME (0x1UL << 4) /**< SIGFRAME Register Busy */
<> 128:9bcdf88f62b0 616 #define _LEUART_SYNCBUSY_SIGFRAME_SHIFT 4 /**< Shift value for LEUART_SIGFRAME */
<> 128:9bcdf88f62b0 617 #define _LEUART_SYNCBUSY_SIGFRAME_MASK 0x10UL /**< Bit mask for LEUART_SIGFRAME */
<> 128:9bcdf88f62b0 618 #define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
<> 128:9bcdf88f62b0 619 #define LEUART_SYNCBUSY_SIGFRAME_DEFAULT (_LEUART_SYNCBUSY_SIGFRAME_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
<> 128:9bcdf88f62b0 620 #define LEUART_SYNCBUSY_TXDATAX (0x1UL << 5) /**< TXDATAX Register Busy */
<> 128:9bcdf88f62b0 621 #define _LEUART_SYNCBUSY_TXDATAX_SHIFT 5 /**< Shift value for LEUART_TXDATAX */
<> 128:9bcdf88f62b0 622 #define _LEUART_SYNCBUSY_TXDATAX_MASK 0x20UL /**< Bit mask for LEUART_TXDATAX */
<> 128:9bcdf88f62b0 623 #define _LEUART_SYNCBUSY_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
<> 128:9bcdf88f62b0 624 #define LEUART_SYNCBUSY_TXDATAX_DEFAULT (_LEUART_SYNCBUSY_TXDATAX_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
<> 128:9bcdf88f62b0 625 #define LEUART_SYNCBUSY_TXDATA (0x1UL << 6) /**< TXDATA Register Busy */
<> 128:9bcdf88f62b0 626 #define _LEUART_SYNCBUSY_TXDATA_SHIFT 6 /**< Shift value for LEUART_TXDATA */
<> 128:9bcdf88f62b0 627 #define _LEUART_SYNCBUSY_TXDATA_MASK 0x40UL /**< Bit mask for LEUART_TXDATA */
<> 128:9bcdf88f62b0 628 #define _LEUART_SYNCBUSY_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
<> 128:9bcdf88f62b0 629 #define LEUART_SYNCBUSY_TXDATA_DEFAULT (_LEUART_SYNCBUSY_TXDATA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
<> 128:9bcdf88f62b0 630 #define LEUART_SYNCBUSY_PULSECTRL (0x1UL << 7) /**< PULSECTRL Register Busy */
<> 128:9bcdf88f62b0 631 #define _LEUART_SYNCBUSY_PULSECTRL_SHIFT 7 /**< Shift value for LEUART_PULSECTRL */
<> 128:9bcdf88f62b0 632 #define _LEUART_SYNCBUSY_PULSECTRL_MASK 0x80UL /**< Bit mask for LEUART_PULSECTRL */
<> 128:9bcdf88f62b0 633 #define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
<> 128:9bcdf88f62b0 634 #define LEUART_SYNCBUSY_PULSECTRL_DEFAULT (_LEUART_SYNCBUSY_PULSECTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
<> 128:9bcdf88f62b0 635
<> 128:9bcdf88f62b0 636 /* Bit fields for LEUART ROUTE */
<> 128:9bcdf88f62b0 637 #define _LEUART_ROUTE_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTE */
<> 128:9bcdf88f62b0 638 #define _LEUART_ROUTE_MASK 0x00000703UL /**< Mask for LEUART_ROUTE */
<> 128:9bcdf88f62b0 639 #define LEUART_ROUTE_RXPEN (0x1UL << 0) /**< RX Pin Enable */
<> 128:9bcdf88f62b0 640 #define _LEUART_ROUTE_RXPEN_SHIFT 0 /**< Shift value for LEUART_RXPEN */
<> 128:9bcdf88f62b0 641 #define _LEUART_ROUTE_RXPEN_MASK 0x1UL /**< Bit mask for LEUART_RXPEN */
<> 128:9bcdf88f62b0 642 #define _LEUART_ROUTE_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTE */
<> 128:9bcdf88f62b0 643 #define LEUART_ROUTE_RXPEN_DEFAULT (_LEUART_ROUTE_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTE */
<> 128:9bcdf88f62b0 644 #define LEUART_ROUTE_TXPEN (0x1UL << 1) /**< TX Pin Enable */
<> 128:9bcdf88f62b0 645 #define _LEUART_ROUTE_TXPEN_SHIFT 1 /**< Shift value for LEUART_TXPEN */
<> 128:9bcdf88f62b0 646 #define _LEUART_ROUTE_TXPEN_MASK 0x2UL /**< Bit mask for LEUART_TXPEN */
<> 128:9bcdf88f62b0 647 #define _LEUART_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTE */
<> 128:9bcdf88f62b0 648 #define LEUART_ROUTE_TXPEN_DEFAULT (_LEUART_ROUTE_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_ROUTE */
<> 128:9bcdf88f62b0 649 #define _LEUART_ROUTE_LOCATION_SHIFT 8 /**< Shift value for LEUART_LOCATION */
<> 128:9bcdf88f62b0 650 #define _LEUART_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for LEUART_LOCATION */
<> 128:9bcdf88f62b0 651 #define _LEUART_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTE */
<> 128:9bcdf88f62b0 652 #define _LEUART_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTE */
<> 128:9bcdf88f62b0 653 #define _LEUART_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTE */
<> 128:9bcdf88f62b0 654 #define _LEUART_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTE */
<> 128:9bcdf88f62b0 655 #define _LEUART_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTE */
<> 128:9bcdf88f62b0 656 #define _LEUART_ROUTE_LOCATION_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTE */
<> 128:9bcdf88f62b0 657 #define LEUART_ROUTE_LOCATION_LOC0 (_LEUART_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for LEUART_ROUTE */
<> 128:9bcdf88f62b0 658 #define LEUART_ROUTE_LOCATION_DEFAULT (_LEUART_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_ROUTE */
<> 128:9bcdf88f62b0 659 #define LEUART_ROUTE_LOCATION_LOC1 (_LEUART_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for LEUART_ROUTE */
<> 128:9bcdf88f62b0 660 #define LEUART_ROUTE_LOCATION_LOC2 (_LEUART_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for LEUART_ROUTE */
<> 128:9bcdf88f62b0 661 #define LEUART_ROUTE_LOCATION_LOC3 (_LEUART_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for LEUART_ROUTE */
<> 128:9bcdf88f62b0 662 #define LEUART_ROUTE_LOCATION_LOC4 (_LEUART_ROUTE_LOCATION_LOC4 << 8) /**< Shifted mode LOC4 for LEUART_ROUTE */
<> 128:9bcdf88f62b0 663
<> 128:9bcdf88f62b0 664 /* Bit fields for LEUART INPUT */
<> 128:9bcdf88f62b0 665 #define _LEUART_INPUT_RESETVALUE 0x00000000UL /**< Default value for LEUART_INPUT */
<> 128:9bcdf88f62b0 666 #define _LEUART_INPUT_MASK 0x0000001FUL /**< Mask for LEUART_INPUT */
<> 128:9bcdf88f62b0 667 #define _LEUART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for LEUART_RXPRSSEL */
<> 128:9bcdf88f62b0 668 #define _LEUART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for LEUART_RXPRSSEL */
<> 128:9bcdf88f62b0 669 #define _LEUART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */
<> 128:9bcdf88f62b0 670 #define _LEUART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LEUART_INPUT */
<> 128:9bcdf88f62b0 671 #define _LEUART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LEUART_INPUT */
<> 128:9bcdf88f62b0 672 #define _LEUART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LEUART_INPUT */
<> 128:9bcdf88f62b0 673 #define _LEUART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LEUART_INPUT */
<> 128:9bcdf88f62b0 674 #define _LEUART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LEUART_INPUT */
<> 128:9bcdf88f62b0 675 #define _LEUART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LEUART_INPUT */
<> 128:9bcdf88f62b0 676 #define _LEUART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LEUART_INPUT */
<> 128:9bcdf88f62b0 677 #define _LEUART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LEUART_INPUT */
<> 128:9bcdf88f62b0 678 #define _LEUART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LEUART_INPUT */
<> 128:9bcdf88f62b0 679 #define _LEUART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LEUART_INPUT */
<> 128:9bcdf88f62b0 680 #define _LEUART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LEUART_INPUT */
<> 128:9bcdf88f62b0 681 #define _LEUART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LEUART_INPUT */
<> 128:9bcdf88f62b0 682 #define LEUART_INPUT_RXPRSSEL_DEFAULT (_LEUART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_INPUT */
<> 128:9bcdf88f62b0 683 #define LEUART_INPUT_RXPRSSEL_PRSCH0 (_LEUART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LEUART_INPUT */
<> 128:9bcdf88f62b0 684 #define LEUART_INPUT_RXPRSSEL_PRSCH1 (_LEUART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LEUART_INPUT */
<> 128:9bcdf88f62b0 685 #define LEUART_INPUT_RXPRSSEL_PRSCH2 (_LEUART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LEUART_INPUT */
<> 128:9bcdf88f62b0 686 #define LEUART_INPUT_RXPRSSEL_PRSCH3 (_LEUART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LEUART_INPUT */
<> 128:9bcdf88f62b0 687 #define LEUART_INPUT_RXPRSSEL_PRSCH4 (_LEUART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LEUART_INPUT */
<> 128:9bcdf88f62b0 688 #define LEUART_INPUT_RXPRSSEL_PRSCH5 (_LEUART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LEUART_INPUT */
<> 128:9bcdf88f62b0 689 #define LEUART_INPUT_RXPRSSEL_PRSCH6 (_LEUART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LEUART_INPUT */
<> 128:9bcdf88f62b0 690 #define LEUART_INPUT_RXPRSSEL_PRSCH7 (_LEUART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LEUART_INPUT */
<> 128:9bcdf88f62b0 691 #define LEUART_INPUT_RXPRSSEL_PRSCH8 (_LEUART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LEUART_INPUT */
<> 128:9bcdf88f62b0 692 #define LEUART_INPUT_RXPRSSEL_PRSCH9 (_LEUART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LEUART_INPUT */
<> 128:9bcdf88f62b0 693 #define LEUART_INPUT_RXPRSSEL_PRSCH10 (_LEUART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LEUART_INPUT */
<> 128:9bcdf88f62b0 694 #define LEUART_INPUT_RXPRSSEL_PRSCH11 (_LEUART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LEUART_INPUT */
<> 128:9bcdf88f62b0 695 #define LEUART_INPUT_RXPRS (0x1UL << 4) /**< PRS RX Enable */
<> 128:9bcdf88f62b0 696 #define _LEUART_INPUT_RXPRS_SHIFT 4 /**< Shift value for LEUART_RXPRS */
<> 128:9bcdf88f62b0 697 #define _LEUART_INPUT_RXPRS_MASK 0x10UL /**< Bit mask for LEUART_RXPRS */
<> 128:9bcdf88f62b0 698 #define _LEUART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */
<> 128:9bcdf88f62b0 699 #define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_INPUT */
<> 128:9bcdf88f62b0 700
<> 128:9bcdf88f62b0 701 /** @} End of group EFM32LG_LEUART */
<> 128:9bcdf88f62b0 702 /** @} End of group Parts */
<> 128:9bcdf88f62b0 703