mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32LG_STK3600/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/efm32lg_ebi.h@139:856d2700e60b, 2017-03-30 (annotated)

Committer:
<>
Date:
Thu Mar 30 13:26:47 2017 +0100
Revision:
139:856d2700e60b
Parent:
128:9bcdf88f62b0 
Release 139 of the mbed library



Ports for Upcoming Targets



3934: [Silicon Labs] Update to HAL and devices https://github.com/ARMmbed/mbed-os/pull/3934



Known Issues



There is an issue with LPC1768 failing the 'Semihost file system' test with this release.



Fixes and Changes



3691: [TLS / hw acceleration] AES ECB for NUCLEO_F439ZI https://github.com/ARMmbed/mbed-os/pull/3691

3869: NCS36510: Default range changed from 0 to 950mV - ADC  https://github.com/ARMmbed/mbed-os/pull/3869

3893: [STM32F7] Update STM32 Cube version v1.6.0 https://github.com/ARMmbed/mbed-os/pull/3893

3917: Fix  mistake register setting in serial_format() https://github.com/ARMmbed/mbed-os/pull/3917

3927: [DELTA_DFBM_NQ620] Add RC calibration setting and revise mbed_overrides.c https://github.com/ARMmbed/mbed-os/pull/3927

3918: [NUC472/M453] Support unique locally administered MAC address and other driver updates https://github.com/ARMmbed/mbed-os/pull/3918

3920: Heap size adjusted to work for both tls-client and mbed-client https://github.com/ARMmbed/mbed-os/pull/3920

3969: NUCLEO_F302R8: Add missing PB_8/PB_9 CAN pins https://github.com/ARMmbed/mbed-os/pull/3969

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**************************************************************************//**
<> 128:9bcdf88f62b0 2 * @file efm32lg_ebi.h
<> 128:9bcdf88f62b0 3 * @brief EFM32LG_EBI register and bit field definitions
<> 139:856d2700e60b 4 * @version 5.1.2
<> 128:9bcdf88f62b0 5 ******************************************************************************
<> 128:9bcdf88f62b0 6 * @section License
<> 139:856d2700e60b 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 *
<> 128:9bcdf88f62b0 10 * Permission is granted to anyone to use this software for any purpose,
<> 128:9bcdf88f62b0 11 * including commercial applications, and to alter it and redistribute it
<> 128:9bcdf88f62b0 12 * freely, subject to the following restrictions:
<> 128:9bcdf88f62b0 13 *
<> 128:9bcdf88f62b0 14 * 1. The origin of this software must not be misrepresented; you must not
<> 128:9bcdf88f62b0 15 * claim that you wrote the original software.@n
<> 128:9bcdf88f62b0 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 128:9bcdf88f62b0 17 * misrepresented as being the original software.@n
<> 128:9bcdf88f62b0 18 * 3. This notice may not be removed or altered from any source distribution.
<> 128:9bcdf88f62b0 19 *
<> 128:9bcdf88f62b0 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 128:9bcdf88f62b0 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 128:9bcdf88f62b0 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 128:9bcdf88f62b0 23 * kind, including, but not limited to, any implied warranties of
<> 128:9bcdf88f62b0 24 * merchantability or fitness for any particular purpose or warranties against
<> 128:9bcdf88f62b0 25 * infringement of any proprietary rights of a third party.
<> 128:9bcdf88f62b0 26 *
<> 128:9bcdf88f62b0 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 128:9bcdf88f62b0 28 * incidental, or special damages, or any other relief, or for any claim by
<> 128:9bcdf88f62b0 29 * any third party, arising from your use of this Software.
<> 128:9bcdf88f62b0 30 *
<> 128:9bcdf88f62b0 31 *****************************************************************************/
<> 128:9bcdf88f62b0 32 /**************************************************************************//**
<> 128:9bcdf88f62b0 33 * @addtogroup Parts
<> 128:9bcdf88f62b0 34 * @{
<> 128:9bcdf88f62b0 35 ******************************************************************************/
<> 128:9bcdf88f62b0 36 /**************************************************************************//**
<> 128:9bcdf88f62b0 37 * @defgroup EFM32LG_EBI
<> 128:9bcdf88f62b0 38 * @{
<> 128:9bcdf88f62b0 39 * @brief EFM32LG_EBI Register Declaration
<> 128:9bcdf88f62b0 40 *****************************************************************************/
<> 128:9bcdf88f62b0 41 typedef struct
<> 128:9bcdf88f62b0 42 {
<> 128:9bcdf88f62b0 43 __IOM uint32_t CTRL; /**< Control Register */
<> 128:9bcdf88f62b0 44 __IOM uint32_t ADDRTIMING; /**< Address Timing Register */
<> 128:9bcdf88f62b0 45 __IOM uint32_t RDTIMING; /**< Read Timing Register */
<> 128:9bcdf88f62b0 46 __IOM uint32_t WRTIMING; /**< Write Timing Register */
<> 128:9bcdf88f62b0 47 __IOM uint32_t POLARITY; /**< Polarity Register */
<> 128:9bcdf88f62b0 48 __IOM uint32_t ROUTE; /**< I/O Routing Register */
<> 128:9bcdf88f62b0 49 __IOM uint32_t ADDRTIMING1; /**< Address Timing Register 1 */
<> 128:9bcdf88f62b0 50 __IOM uint32_t RDTIMING1; /**< Read Timing Register 1 */
<> 128:9bcdf88f62b0 51 __IOM uint32_t WRTIMING1; /**< Write Timing Register 1 */
<> 128:9bcdf88f62b0 52 __IOM uint32_t POLARITY1; /**< Polarity Register 1 */
<> 128:9bcdf88f62b0 53 __IOM uint32_t ADDRTIMING2; /**< Address Timing Register 2 */
<> 128:9bcdf88f62b0 54 __IOM uint32_t RDTIMING2; /**< Read Timing Register 2 */
<> 128:9bcdf88f62b0 55 __IOM uint32_t WRTIMING2; /**< Write Timing Register 2 */
<> 128:9bcdf88f62b0 56 __IOM uint32_t POLARITY2; /**< Polarity Register 2 */
<> 128:9bcdf88f62b0 57 __IOM uint32_t ADDRTIMING3; /**< Address Timing Register 3 */
<> 128:9bcdf88f62b0 58 __IOM uint32_t RDTIMING3; /**< Read Timing Register 3 */
<> 128:9bcdf88f62b0 59 __IOM uint32_t WRTIMING3; /**< Write Timing Register 3 */
<> 128:9bcdf88f62b0 60 __IOM uint32_t POLARITY3; /**< Polarity Register 3 */
<> 128:9bcdf88f62b0 61 __IOM uint32_t PAGECTRL; /**< Page Control Register */
<> 128:9bcdf88f62b0 62 __IOM uint32_t NANDCTRL; /**< NAND Control Register */
<> 128:9bcdf88f62b0 63 __IOM uint32_t CMD; /**< Command Register */
<> 128:9bcdf88f62b0 64 __IM uint32_t STATUS; /**< Status Register */
<> 128:9bcdf88f62b0 65 __IM uint32_t ECCPARITY; /**< ECC Parity register */
<> 128:9bcdf88f62b0 66 __IOM uint32_t TFTCTRL; /**< TFT Control Register */
<> 128:9bcdf88f62b0 67 __IM uint32_t TFTSTATUS; /**< TFT Status Register */
<> 128:9bcdf88f62b0 68 __IOM uint32_t TFTFRAMEBASE; /**< TFT Frame Base Register */
<> 128:9bcdf88f62b0 69 __IOM uint32_t TFTSTRIDE; /**< TFT Stride Register */
<> 128:9bcdf88f62b0 70 __IOM uint32_t TFTSIZE; /**< TFT Size Register */
<> 128:9bcdf88f62b0 71 __IOM uint32_t TFTHPORCH; /**< TFT Horizontal Porch Register */
<> 128:9bcdf88f62b0 72 __IOM uint32_t TFTVPORCH; /**< TFT Vertical Porch Register */
<> 128:9bcdf88f62b0 73 __IOM uint32_t TFTTIMING; /**< TFT Timing Register */
<> 128:9bcdf88f62b0 74 __IOM uint32_t TFTPOLARITY; /**< TFT Polarity Register */
<> 128:9bcdf88f62b0 75 __IOM uint32_t TFTDD; /**< TFT Direct Drive Data Register */
<> 128:9bcdf88f62b0 76 __IOM uint32_t TFTALPHA; /**< TFT Alpha Blending Register */
<> 128:9bcdf88f62b0 77 __IOM uint32_t TFTPIXEL0; /**< TFT Pixel 0 Register */
<> 128:9bcdf88f62b0 78 __IOM uint32_t TFTPIXEL1; /**< TFT Pixel 1 Register */
<> 128:9bcdf88f62b0 79 __IM uint32_t TFTPIXEL; /**< TFT Alpha Blending Result Pixel Register */
<> 128:9bcdf88f62b0 80 __IOM uint32_t TFTMASK; /**< TFT Masking Register */
<> 128:9bcdf88f62b0 81 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 128:9bcdf88f62b0 82 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 128:9bcdf88f62b0 83 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 128:9bcdf88f62b0 84 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 128:9bcdf88f62b0 85 } EBI_TypeDef; /** @} */
<> 128:9bcdf88f62b0 86
<> 128:9bcdf88f62b0 87 /**************************************************************************//**
<> 128:9bcdf88f62b0 88 * @defgroup EFM32LG_EBI_BitFields
<> 128:9bcdf88f62b0 89 * @{
<> 128:9bcdf88f62b0 90 *****************************************************************************/
<> 128:9bcdf88f62b0 91
<> 128:9bcdf88f62b0 92 /* Bit fields for EBI CTRL */
<> 128:9bcdf88f62b0 93 #define _EBI_CTRL_RESETVALUE 0x00000000UL /**< Default value for EBI_CTRL */
<> 128:9bcdf88f62b0 94 #define _EBI_CTRL_MASK 0xCFFFFFFFUL /**< Mask for EBI_CTRL */
<> 128:9bcdf88f62b0 95 #define _EBI_CTRL_MODE_SHIFT 0 /**< Shift value for EBI_MODE */
<> 128:9bcdf88f62b0 96 #define _EBI_CTRL_MODE_MASK 0x3UL /**< Bit mask for EBI_MODE */
<> 128:9bcdf88f62b0 97 #define _EBI_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 98 #define _EBI_CTRL_MODE_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */
<> 128:9bcdf88f62b0 99 #define _EBI_CTRL_MODE_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */
<> 128:9bcdf88f62b0 100 #define _EBI_CTRL_MODE_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */
<> 128:9bcdf88f62b0 101 #define _EBI_CTRL_MODE_D16 0x00000003UL /**< Mode D16 for EBI_CTRL */
<> 128:9bcdf88f62b0 102 #define EBI_CTRL_MODE_DEFAULT (_EBI_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 103 #define EBI_CTRL_MODE_D8A8 (_EBI_CTRL_MODE_D8A8 << 0) /**< Shifted mode D8A8 for EBI_CTRL */
<> 128:9bcdf88f62b0 104 #define EBI_CTRL_MODE_D16A16ALE (_EBI_CTRL_MODE_D16A16ALE << 0) /**< Shifted mode D16A16ALE for EBI_CTRL */
<> 128:9bcdf88f62b0 105 #define EBI_CTRL_MODE_D8A24ALE (_EBI_CTRL_MODE_D8A24ALE << 0) /**< Shifted mode D8A24ALE for EBI_CTRL */
<> 128:9bcdf88f62b0 106 #define EBI_CTRL_MODE_D16 (_EBI_CTRL_MODE_D16 << 0) /**< Shifted mode D16 for EBI_CTRL */
<> 128:9bcdf88f62b0 107 #define _EBI_CTRL_MODE1_SHIFT 2 /**< Shift value for EBI_MODE1 */
<> 128:9bcdf88f62b0 108 #define _EBI_CTRL_MODE1_MASK 0xCUL /**< Bit mask for EBI_MODE1 */
<> 128:9bcdf88f62b0 109 #define _EBI_CTRL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 110 #define _EBI_CTRL_MODE1_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */
<> 128:9bcdf88f62b0 111 #define _EBI_CTRL_MODE1_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */
<> 128:9bcdf88f62b0 112 #define _EBI_CTRL_MODE1_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */
<> 128:9bcdf88f62b0 113 #define _EBI_CTRL_MODE1_D16 0x00000003UL /**< Mode D16 for EBI_CTRL */
<> 128:9bcdf88f62b0 114 #define EBI_CTRL_MODE1_DEFAULT (_EBI_CTRL_MODE1_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 115 #define EBI_CTRL_MODE1_D8A8 (_EBI_CTRL_MODE1_D8A8 << 2) /**< Shifted mode D8A8 for EBI_CTRL */
<> 128:9bcdf88f62b0 116 #define EBI_CTRL_MODE1_D16A16ALE (_EBI_CTRL_MODE1_D16A16ALE << 2) /**< Shifted mode D16A16ALE for EBI_CTRL */
<> 128:9bcdf88f62b0 117 #define EBI_CTRL_MODE1_D8A24ALE (_EBI_CTRL_MODE1_D8A24ALE << 2) /**< Shifted mode D8A24ALE for EBI_CTRL */
<> 128:9bcdf88f62b0 118 #define EBI_CTRL_MODE1_D16 (_EBI_CTRL_MODE1_D16 << 2) /**< Shifted mode D16 for EBI_CTRL */
<> 128:9bcdf88f62b0 119 #define _EBI_CTRL_MODE2_SHIFT 4 /**< Shift value for EBI_MODE2 */
<> 128:9bcdf88f62b0 120 #define _EBI_CTRL_MODE2_MASK 0x30UL /**< Bit mask for EBI_MODE2 */
<> 128:9bcdf88f62b0 121 #define _EBI_CTRL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 122 #define _EBI_CTRL_MODE2_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */
<> 128:9bcdf88f62b0 123 #define _EBI_CTRL_MODE2_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */
<> 128:9bcdf88f62b0 124 #define _EBI_CTRL_MODE2_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */
<> 128:9bcdf88f62b0 125 #define _EBI_CTRL_MODE2_D16 0x00000003UL /**< Mode D16 for EBI_CTRL */
<> 128:9bcdf88f62b0 126 #define EBI_CTRL_MODE2_DEFAULT (_EBI_CTRL_MODE2_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 127 #define EBI_CTRL_MODE2_D8A8 (_EBI_CTRL_MODE2_D8A8 << 4) /**< Shifted mode D8A8 for EBI_CTRL */
<> 128:9bcdf88f62b0 128 #define EBI_CTRL_MODE2_D16A16ALE (_EBI_CTRL_MODE2_D16A16ALE << 4) /**< Shifted mode D16A16ALE for EBI_CTRL */
<> 128:9bcdf88f62b0 129 #define EBI_CTRL_MODE2_D8A24ALE (_EBI_CTRL_MODE2_D8A24ALE << 4) /**< Shifted mode D8A24ALE for EBI_CTRL */
<> 128:9bcdf88f62b0 130 #define EBI_CTRL_MODE2_D16 (_EBI_CTRL_MODE2_D16 << 4) /**< Shifted mode D16 for EBI_CTRL */
<> 128:9bcdf88f62b0 131 #define _EBI_CTRL_MODE3_SHIFT 6 /**< Shift value for EBI_MODE3 */
<> 128:9bcdf88f62b0 132 #define _EBI_CTRL_MODE3_MASK 0xC0UL /**< Bit mask for EBI_MODE3 */
<> 128:9bcdf88f62b0 133 #define _EBI_CTRL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 134 #define _EBI_CTRL_MODE3_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */
<> 128:9bcdf88f62b0 135 #define _EBI_CTRL_MODE3_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */
<> 128:9bcdf88f62b0 136 #define _EBI_CTRL_MODE3_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */
<> 128:9bcdf88f62b0 137 #define _EBI_CTRL_MODE3_D16 0x00000003UL /**< Mode D16 for EBI_CTRL */
<> 128:9bcdf88f62b0 138 #define EBI_CTRL_MODE3_DEFAULT (_EBI_CTRL_MODE3_DEFAULT << 6) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 139 #define EBI_CTRL_MODE3_D8A8 (_EBI_CTRL_MODE3_D8A8 << 6) /**< Shifted mode D8A8 for EBI_CTRL */
<> 128:9bcdf88f62b0 140 #define EBI_CTRL_MODE3_D16A16ALE (_EBI_CTRL_MODE3_D16A16ALE << 6) /**< Shifted mode D16A16ALE for EBI_CTRL */
<> 128:9bcdf88f62b0 141 #define EBI_CTRL_MODE3_D8A24ALE (_EBI_CTRL_MODE3_D8A24ALE << 6) /**< Shifted mode D8A24ALE for EBI_CTRL */
<> 128:9bcdf88f62b0 142 #define EBI_CTRL_MODE3_D16 (_EBI_CTRL_MODE3_D16 << 6) /**< Shifted mode D16 for EBI_CTRL */
<> 128:9bcdf88f62b0 143 #define EBI_CTRL_BANK0EN (0x1UL << 8) /**< Bank 0 Enable */
<> 128:9bcdf88f62b0 144 #define _EBI_CTRL_BANK0EN_SHIFT 8 /**< Shift value for EBI_BANK0EN */
<> 128:9bcdf88f62b0 145 #define _EBI_CTRL_BANK0EN_MASK 0x100UL /**< Bit mask for EBI_BANK0EN */
<> 128:9bcdf88f62b0 146 #define _EBI_CTRL_BANK0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 147 #define EBI_CTRL_BANK0EN_DEFAULT (_EBI_CTRL_BANK0EN_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 148 #define EBI_CTRL_BANK1EN (0x1UL << 9) /**< Bank 1 Enable */
<> 128:9bcdf88f62b0 149 #define _EBI_CTRL_BANK1EN_SHIFT 9 /**< Shift value for EBI_BANK1EN */
<> 128:9bcdf88f62b0 150 #define _EBI_CTRL_BANK1EN_MASK 0x200UL /**< Bit mask for EBI_BANK1EN */
<> 128:9bcdf88f62b0 151 #define _EBI_CTRL_BANK1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 152 #define EBI_CTRL_BANK1EN_DEFAULT (_EBI_CTRL_BANK1EN_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 153 #define EBI_CTRL_BANK2EN (0x1UL << 10) /**< Bank 2 Enable */
<> 128:9bcdf88f62b0 154 #define _EBI_CTRL_BANK2EN_SHIFT 10 /**< Shift value for EBI_BANK2EN */
<> 128:9bcdf88f62b0 155 #define _EBI_CTRL_BANK2EN_MASK 0x400UL /**< Bit mask for EBI_BANK2EN */
<> 128:9bcdf88f62b0 156 #define _EBI_CTRL_BANK2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 157 #define EBI_CTRL_BANK2EN_DEFAULT (_EBI_CTRL_BANK2EN_DEFAULT << 10) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 158 #define EBI_CTRL_BANK3EN (0x1UL << 11) /**< Bank 3 Enable */
<> 128:9bcdf88f62b0 159 #define _EBI_CTRL_BANK3EN_SHIFT 11 /**< Shift value for EBI_BANK3EN */
<> 128:9bcdf88f62b0 160 #define _EBI_CTRL_BANK3EN_MASK 0x800UL /**< Bit mask for EBI_BANK3EN */
<> 128:9bcdf88f62b0 161 #define _EBI_CTRL_BANK3EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 162 #define EBI_CTRL_BANK3EN_DEFAULT (_EBI_CTRL_BANK3EN_DEFAULT << 11) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 163 #define EBI_CTRL_NOIDLE (0x1UL << 12) /**< No idle cycle insertion on bank 0. */
<> 128:9bcdf88f62b0 164 #define _EBI_CTRL_NOIDLE_SHIFT 12 /**< Shift value for EBI_NOIDLE */
<> 128:9bcdf88f62b0 165 #define _EBI_CTRL_NOIDLE_MASK 0x1000UL /**< Bit mask for EBI_NOIDLE */
<> 128:9bcdf88f62b0 166 #define _EBI_CTRL_NOIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 167 #define EBI_CTRL_NOIDLE_DEFAULT (_EBI_CTRL_NOIDLE_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 168 #define EBI_CTRL_NOIDLE1 (0x1UL << 13) /**< No idle cycle insertion on bank 1. */
<> 128:9bcdf88f62b0 169 #define _EBI_CTRL_NOIDLE1_SHIFT 13 /**< Shift value for EBI_NOIDLE1 */
<> 128:9bcdf88f62b0 170 #define _EBI_CTRL_NOIDLE1_MASK 0x2000UL /**< Bit mask for EBI_NOIDLE1 */
<> 128:9bcdf88f62b0 171 #define _EBI_CTRL_NOIDLE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 172 #define EBI_CTRL_NOIDLE1_DEFAULT (_EBI_CTRL_NOIDLE1_DEFAULT << 13) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 173 #define EBI_CTRL_NOIDLE2 (0x1UL << 14) /**< No idle cycle insertion on bank 2. */
<> 128:9bcdf88f62b0 174 #define _EBI_CTRL_NOIDLE2_SHIFT 14 /**< Shift value for EBI_NOIDLE2 */
<> 128:9bcdf88f62b0 175 #define _EBI_CTRL_NOIDLE2_MASK 0x4000UL /**< Bit mask for EBI_NOIDLE2 */
<> 128:9bcdf88f62b0 176 #define _EBI_CTRL_NOIDLE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 177 #define EBI_CTRL_NOIDLE2_DEFAULT (_EBI_CTRL_NOIDLE2_DEFAULT << 14) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 178 #define EBI_CTRL_NOIDLE3 (0x1UL << 15) /**< No idle cycle insertion on bank 3. */
<> 128:9bcdf88f62b0 179 #define _EBI_CTRL_NOIDLE3_SHIFT 15 /**< Shift value for EBI_NOIDLE3 */
<> 128:9bcdf88f62b0 180 #define _EBI_CTRL_NOIDLE3_MASK 0x8000UL /**< Bit mask for EBI_NOIDLE3 */
<> 128:9bcdf88f62b0 181 #define _EBI_CTRL_NOIDLE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 182 #define EBI_CTRL_NOIDLE3_DEFAULT (_EBI_CTRL_NOIDLE3_DEFAULT << 15) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 183 #define EBI_CTRL_ARDYEN (0x1UL << 16) /**< ARDY Enable */
<> 128:9bcdf88f62b0 184 #define _EBI_CTRL_ARDYEN_SHIFT 16 /**< Shift value for EBI_ARDYEN */
<> 128:9bcdf88f62b0 185 #define _EBI_CTRL_ARDYEN_MASK 0x10000UL /**< Bit mask for EBI_ARDYEN */
<> 128:9bcdf88f62b0 186 #define _EBI_CTRL_ARDYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 187 #define EBI_CTRL_ARDYEN_DEFAULT (_EBI_CTRL_ARDYEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 188 #define EBI_CTRL_ARDYTODIS (0x1UL << 17) /**< ARDY Timeout Disable */
<> 128:9bcdf88f62b0 189 #define _EBI_CTRL_ARDYTODIS_SHIFT 17 /**< Shift value for EBI_ARDYTODIS */
<> 128:9bcdf88f62b0 190 #define _EBI_CTRL_ARDYTODIS_MASK 0x20000UL /**< Bit mask for EBI_ARDYTODIS */
<> 128:9bcdf88f62b0 191 #define _EBI_CTRL_ARDYTODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 192 #define EBI_CTRL_ARDYTODIS_DEFAULT (_EBI_CTRL_ARDYTODIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 193 #define EBI_CTRL_ARDY1EN (0x1UL << 18) /**< ARDY Enable for bank 1 */
<> 128:9bcdf88f62b0 194 #define _EBI_CTRL_ARDY1EN_SHIFT 18 /**< Shift value for EBI_ARDY1EN */
<> 128:9bcdf88f62b0 195 #define _EBI_CTRL_ARDY1EN_MASK 0x40000UL /**< Bit mask for EBI_ARDY1EN */
<> 128:9bcdf88f62b0 196 #define _EBI_CTRL_ARDY1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 197 #define EBI_CTRL_ARDY1EN_DEFAULT (_EBI_CTRL_ARDY1EN_DEFAULT << 18) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 198 #define EBI_CTRL_ARDYTO1DIS (0x1UL << 19) /**< ARDY Timeout Disable for bank 1 */
<> 128:9bcdf88f62b0 199 #define _EBI_CTRL_ARDYTO1DIS_SHIFT 19 /**< Shift value for EBI_ARDYTO1DIS */
<> 128:9bcdf88f62b0 200 #define _EBI_CTRL_ARDYTO1DIS_MASK 0x80000UL /**< Bit mask for EBI_ARDYTO1DIS */
<> 128:9bcdf88f62b0 201 #define _EBI_CTRL_ARDYTO1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 202 #define EBI_CTRL_ARDYTO1DIS_DEFAULT (_EBI_CTRL_ARDYTO1DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 203 #define EBI_CTRL_ARDY2EN (0x1UL << 20) /**< ARDY Enable for bank 2 */
<> 128:9bcdf88f62b0 204 #define _EBI_CTRL_ARDY2EN_SHIFT 20 /**< Shift value for EBI_ARDY2EN */
<> 128:9bcdf88f62b0 205 #define _EBI_CTRL_ARDY2EN_MASK 0x100000UL /**< Bit mask for EBI_ARDY2EN */
<> 128:9bcdf88f62b0 206 #define _EBI_CTRL_ARDY2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 207 #define EBI_CTRL_ARDY2EN_DEFAULT (_EBI_CTRL_ARDY2EN_DEFAULT << 20) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 208 #define EBI_CTRL_ARDYTO2DIS (0x1UL << 21) /**< ARDY Timeout Disable for bank 2 */
<> 128:9bcdf88f62b0 209 #define _EBI_CTRL_ARDYTO2DIS_SHIFT 21 /**< Shift value for EBI_ARDYTO2DIS */
<> 128:9bcdf88f62b0 210 #define _EBI_CTRL_ARDYTO2DIS_MASK 0x200000UL /**< Bit mask for EBI_ARDYTO2DIS */
<> 128:9bcdf88f62b0 211 #define _EBI_CTRL_ARDYTO2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 212 #define EBI_CTRL_ARDYTO2DIS_DEFAULT (_EBI_CTRL_ARDYTO2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 213 #define EBI_CTRL_ARDY3EN (0x1UL << 22) /**< ARDY Enable for bank 3 */
<> 128:9bcdf88f62b0 214 #define _EBI_CTRL_ARDY3EN_SHIFT 22 /**< Shift value for EBI_ARDY3EN */
<> 128:9bcdf88f62b0 215 #define _EBI_CTRL_ARDY3EN_MASK 0x400000UL /**< Bit mask for EBI_ARDY3EN */
<> 128:9bcdf88f62b0 216 #define _EBI_CTRL_ARDY3EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 217 #define EBI_CTRL_ARDY3EN_DEFAULT (_EBI_CTRL_ARDY3EN_DEFAULT << 22) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 218 #define EBI_CTRL_ARDYTO3DIS (0x1UL << 23) /**< ARDY Timeout Disable for bank 3 */
<> 128:9bcdf88f62b0 219 #define _EBI_CTRL_ARDYTO3DIS_SHIFT 23 /**< Shift value for EBI_ARDYTO3DIS */
<> 128:9bcdf88f62b0 220 #define _EBI_CTRL_ARDYTO3DIS_MASK 0x800000UL /**< Bit mask for EBI_ARDYTO3DIS */
<> 128:9bcdf88f62b0 221 #define _EBI_CTRL_ARDYTO3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 222 #define EBI_CTRL_ARDYTO3DIS_DEFAULT (_EBI_CTRL_ARDYTO3DIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 223 #define EBI_CTRL_BL (0x1UL << 24) /**< Byte Lane Enable for bank 0 */
<> 128:9bcdf88f62b0 224 #define _EBI_CTRL_BL_SHIFT 24 /**< Shift value for EBI_BL */
<> 128:9bcdf88f62b0 225 #define _EBI_CTRL_BL_MASK 0x1000000UL /**< Bit mask for EBI_BL */
<> 128:9bcdf88f62b0 226 #define _EBI_CTRL_BL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 227 #define EBI_CTRL_BL_DEFAULT (_EBI_CTRL_BL_DEFAULT << 24) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 228 #define EBI_CTRL_BL1 (0x1UL << 25) /**< Byte Lane Enable for bank 1 */
<> 128:9bcdf88f62b0 229 #define _EBI_CTRL_BL1_SHIFT 25 /**< Shift value for EBI_BL1 */
<> 128:9bcdf88f62b0 230 #define _EBI_CTRL_BL1_MASK 0x2000000UL /**< Bit mask for EBI_BL1 */
<> 128:9bcdf88f62b0 231 #define _EBI_CTRL_BL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 232 #define EBI_CTRL_BL1_DEFAULT (_EBI_CTRL_BL1_DEFAULT << 25) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 233 #define EBI_CTRL_BL2 (0x1UL << 26) /**< Byte Lane Enable for bank 2 */
<> 128:9bcdf88f62b0 234 #define _EBI_CTRL_BL2_SHIFT 26 /**< Shift value for EBI_BL2 */
<> 128:9bcdf88f62b0 235 #define _EBI_CTRL_BL2_MASK 0x4000000UL /**< Bit mask for EBI_BL2 */
<> 128:9bcdf88f62b0 236 #define _EBI_CTRL_BL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 237 #define EBI_CTRL_BL2_DEFAULT (_EBI_CTRL_BL2_DEFAULT << 26) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 238 #define EBI_CTRL_BL3 (0x1UL << 27) /**< Byte Lane Enable for bank 3 */
<> 128:9bcdf88f62b0 239 #define _EBI_CTRL_BL3_SHIFT 27 /**< Shift value for EBI_BL3 */
<> 128:9bcdf88f62b0 240 #define _EBI_CTRL_BL3_MASK 0x8000000UL /**< Bit mask for EBI_BL3 */
<> 128:9bcdf88f62b0 241 #define _EBI_CTRL_BL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 242 #define EBI_CTRL_BL3_DEFAULT (_EBI_CTRL_BL3_DEFAULT << 27) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 243 #define EBI_CTRL_ITS (0x1UL << 30) /**< Individual Timing Set, Line Polarity and Mode Definition Enable */
<> 128:9bcdf88f62b0 244 #define _EBI_CTRL_ITS_SHIFT 30 /**< Shift value for EBI_ITS */
<> 128:9bcdf88f62b0 245 #define _EBI_CTRL_ITS_MASK 0x40000000UL /**< Bit mask for EBI_ITS */
<> 128:9bcdf88f62b0 246 #define _EBI_CTRL_ITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 247 #define EBI_CTRL_ITS_DEFAULT (_EBI_CTRL_ITS_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 248 #define EBI_CTRL_ALTMAP (0x1UL << 31) /**< Alternative Address Map Enable */
<> 128:9bcdf88f62b0 249 #define _EBI_CTRL_ALTMAP_SHIFT 31 /**< Shift value for EBI_ALTMAP */
<> 128:9bcdf88f62b0 250 #define _EBI_CTRL_ALTMAP_MASK 0x80000000UL /**< Bit mask for EBI_ALTMAP */
<> 128:9bcdf88f62b0 251 #define _EBI_CTRL_ALTMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 252 #define EBI_CTRL_ALTMAP_DEFAULT (_EBI_CTRL_ALTMAP_DEFAULT << 31) /**< Shifted mode DEFAULT for EBI_CTRL */
<> 128:9bcdf88f62b0 253
<> 128:9bcdf88f62b0 254 /* Bit fields for EBI ADDRTIMING */
<> 128:9bcdf88f62b0 255 #define _EBI_ADDRTIMING_RESETVALUE 0x00000303UL /**< Default value for EBI_ADDRTIMING */
<> 128:9bcdf88f62b0 256 #define _EBI_ADDRTIMING_MASK 0x10000303UL /**< Mask for EBI_ADDRTIMING */
<> 128:9bcdf88f62b0 257 #define _EBI_ADDRTIMING_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */
<> 128:9bcdf88f62b0 258 #define _EBI_ADDRTIMING_ADDRSETUP_MASK 0x3UL /**< Bit mask for EBI_ADDRSETUP */
<> 128:9bcdf88f62b0 259 #define _EBI_ADDRTIMING_ADDRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING */
<> 128:9bcdf88f62b0 260 #define EBI_ADDRTIMING_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */
<> 128:9bcdf88f62b0 261 #define _EBI_ADDRTIMING_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */
<> 128:9bcdf88f62b0 262 #define _EBI_ADDRTIMING_ADDRHOLD_MASK 0x300UL /**< Bit mask for EBI_ADDRHOLD */
<> 128:9bcdf88f62b0 263 #define _EBI_ADDRTIMING_ADDRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING */
<> 128:9bcdf88f62b0 264 #define EBI_ADDRTIMING_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */
<> 128:9bcdf88f62b0 265 #define EBI_ADDRTIMING_HALFALE (0x1UL << 28) /**< Half Cycle ALE Strobe Duration Enable */
<> 128:9bcdf88f62b0 266 #define _EBI_ADDRTIMING_HALFALE_SHIFT 28 /**< Shift value for EBI_HALFALE */
<> 128:9bcdf88f62b0 267 #define _EBI_ADDRTIMING_HALFALE_MASK 0x10000000UL /**< Bit mask for EBI_HALFALE */
<> 128:9bcdf88f62b0 268 #define _EBI_ADDRTIMING_HALFALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING */
<> 128:9bcdf88f62b0 269 #define EBI_ADDRTIMING_HALFALE_DEFAULT (_EBI_ADDRTIMING_HALFALE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */
<> 128:9bcdf88f62b0 270
<> 128:9bcdf88f62b0 271 /* Bit fields for EBI RDTIMING */
<> 128:9bcdf88f62b0 272 #define _EBI_RDTIMING_RESETVALUE 0x00033F03UL /**< Default value for EBI_RDTIMING */
<> 128:9bcdf88f62b0 273 #define _EBI_RDTIMING_MASK 0x70033F03UL /**< Mask for EBI_RDTIMING */
<> 128:9bcdf88f62b0 274 #define _EBI_RDTIMING_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */
<> 128:9bcdf88f62b0 275 #define _EBI_RDTIMING_RDSETUP_MASK 0x3UL /**< Bit mask for EBI_RDSETUP */
<> 128:9bcdf88f62b0 276 #define _EBI_RDTIMING_RDSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING */
<> 128:9bcdf88f62b0 277 #define EBI_RDTIMING_RDSETUP_DEFAULT (_EBI_RDTIMING_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING */
<> 128:9bcdf88f62b0 278 #define _EBI_RDTIMING_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */
<> 128:9bcdf88f62b0 279 #define _EBI_RDTIMING_RDSTRB_MASK 0x3F00UL /**< Bit mask for EBI_RDSTRB */
<> 128:9bcdf88f62b0 280 #define _EBI_RDTIMING_RDSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_RDTIMING */
<> 128:9bcdf88f62b0 281 #define EBI_RDTIMING_RDSTRB_DEFAULT (_EBI_RDTIMING_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING */
<> 128:9bcdf88f62b0 282 #define _EBI_RDTIMING_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */
<> 128:9bcdf88f62b0 283 #define _EBI_RDTIMING_RDHOLD_MASK 0x30000UL /**< Bit mask for EBI_RDHOLD */
<> 128:9bcdf88f62b0 284 #define _EBI_RDTIMING_RDHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING */
<> 128:9bcdf88f62b0 285 #define EBI_RDTIMING_RDHOLD_DEFAULT (_EBI_RDTIMING_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING */
<> 128:9bcdf88f62b0 286 #define EBI_RDTIMING_HALFRE (0x1UL << 28) /**< Half Cycle REn Strobe Duration Enable */
<> 128:9bcdf88f62b0 287 #define _EBI_RDTIMING_HALFRE_SHIFT 28 /**< Shift value for EBI_HALFRE */
<> 128:9bcdf88f62b0 288 #define _EBI_RDTIMING_HALFRE_MASK 0x10000000UL /**< Bit mask for EBI_HALFRE */
<> 128:9bcdf88f62b0 289 #define _EBI_RDTIMING_HALFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */
<> 128:9bcdf88f62b0 290 #define EBI_RDTIMING_HALFRE_DEFAULT (_EBI_RDTIMING_HALFRE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_RDTIMING */
<> 128:9bcdf88f62b0 291 #define EBI_RDTIMING_PREFETCH (0x1UL << 29) /**< Prefetch Enable */
<> 128:9bcdf88f62b0 292 #define _EBI_RDTIMING_PREFETCH_SHIFT 29 /**< Shift value for EBI_PREFETCH */
<> 128:9bcdf88f62b0 293 #define _EBI_RDTIMING_PREFETCH_MASK 0x20000000UL /**< Bit mask for EBI_PREFETCH */
<> 128:9bcdf88f62b0 294 #define _EBI_RDTIMING_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */
<> 128:9bcdf88f62b0 295 #define EBI_RDTIMING_PREFETCH_DEFAULT (_EBI_RDTIMING_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING */
<> 128:9bcdf88f62b0 296 #define EBI_RDTIMING_PAGEMODE (0x1UL << 30) /**< Page Mode Access Enable */
<> 128:9bcdf88f62b0 297 #define _EBI_RDTIMING_PAGEMODE_SHIFT 30 /**< Shift value for EBI_PAGEMODE */
<> 128:9bcdf88f62b0 298 #define _EBI_RDTIMING_PAGEMODE_MASK 0x40000000UL /**< Bit mask for EBI_PAGEMODE */
<> 128:9bcdf88f62b0 299 #define _EBI_RDTIMING_PAGEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */
<> 128:9bcdf88f62b0 300 #define EBI_RDTIMING_PAGEMODE_DEFAULT (_EBI_RDTIMING_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING */
<> 128:9bcdf88f62b0 301
<> 128:9bcdf88f62b0 302 /* Bit fields for EBI WRTIMING */
<> 128:9bcdf88f62b0 303 #define _EBI_WRTIMING_RESETVALUE 0x00033F03UL /**< Default value for EBI_WRTIMING */
<> 128:9bcdf88f62b0 304 #define _EBI_WRTIMING_MASK 0x30033F03UL /**< Mask for EBI_WRTIMING */
<> 128:9bcdf88f62b0 305 #define _EBI_WRTIMING_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */
<> 128:9bcdf88f62b0 306 #define _EBI_WRTIMING_WRSETUP_MASK 0x3UL /**< Bit mask for EBI_WRSETUP */
<> 128:9bcdf88f62b0 307 #define _EBI_WRTIMING_WRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING */
<> 128:9bcdf88f62b0 308 #define EBI_WRTIMING_WRSETUP_DEFAULT (_EBI_WRTIMING_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING */
<> 128:9bcdf88f62b0 309 #define _EBI_WRTIMING_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */
<> 128:9bcdf88f62b0 310 #define _EBI_WRTIMING_WRSTRB_MASK 0x3F00UL /**< Bit mask for EBI_WRSTRB */
<> 128:9bcdf88f62b0 311 #define _EBI_WRTIMING_WRSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_WRTIMING */
<> 128:9bcdf88f62b0 312 #define EBI_WRTIMING_WRSTRB_DEFAULT (_EBI_WRTIMING_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING */
<> 128:9bcdf88f62b0 313 #define _EBI_WRTIMING_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */
<> 128:9bcdf88f62b0 314 #define _EBI_WRTIMING_WRHOLD_MASK 0x30000UL /**< Bit mask for EBI_WRHOLD */
<> 128:9bcdf88f62b0 315 #define _EBI_WRTIMING_WRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING */
<> 128:9bcdf88f62b0 316 #define EBI_WRTIMING_WRHOLD_DEFAULT (_EBI_WRTIMING_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING */
<> 128:9bcdf88f62b0 317 #define EBI_WRTIMING_HALFWE (0x1UL << 28) /**< Half Cycle WEn Strobe Duration Enable */
<> 128:9bcdf88f62b0 318 #define _EBI_WRTIMING_HALFWE_SHIFT 28 /**< Shift value for EBI_HALFWE */
<> 128:9bcdf88f62b0 319 #define _EBI_WRTIMING_HALFWE_MASK 0x10000000UL /**< Bit mask for EBI_HALFWE */
<> 128:9bcdf88f62b0 320 #define _EBI_WRTIMING_HALFWE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING */
<> 128:9bcdf88f62b0 321 #define EBI_WRTIMING_HALFWE_DEFAULT (_EBI_WRTIMING_HALFWE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_WRTIMING */
<> 128:9bcdf88f62b0 322 #define EBI_WRTIMING_WBUFDIS (0x1UL << 29) /**< Write Buffer Disable */
<> 128:9bcdf88f62b0 323 #define _EBI_WRTIMING_WBUFDIS_SHIFT 29 /**< Shift value for EBI_WBUFDIS */
<> 128:9bcdf88f62b0 324 #define _EBI_WRTIMING_WBUFDIS_MASK 0x20000000UL /**< Bit mask for EBI_WBUFDIS */
<> 128:9bcdf88f62b0 325 #define _EBI_WRTIMING_WBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING */
<> 128:9bcdf88f62b0 326 #define EBI_WRTIMING_WBUFDIS_DEFAULT (_EBI_WRTIMING_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING */
<> 128:9bcdf88f62b0 327
<> 128:9bcdf88f62b0 328 /* Bit fields for EBI POLARITY */
<> 128:9bcdf88f62b0 329 #define _EBI_POLARITY_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY */
<> 128:9bcdf88f62b0 330 #define _EBI_POLARITY_MASK 0x0000003FUL /**< Mask for EBI_POLARITY */
<> 128:9bcdf88f62b0 331 #define EBI_POLARITY_CSPOL (0x1UL << 0) /**< Chip Select Polarity */
<> 128:9bcdf88f62b0 332 #define _EBI_POLARITY_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */
<> 128:9bcdf88f62b0 333 #define _EBI_POLARITY_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */
<> 128:9bcdf88f62b0 334 #define _EBI_POLARITY_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
<> 128:9bcdf88f62b0 335 #define _EBI_POLARITY_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
<> 128:9bcdf88f62b0 336 #define _EBI_POLARITY_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
<> 128:9bcdf88f62b0 337 #define EBI_POLARITY_CSPOL_DEFAULT (_EBI_POLARITY_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY */
<> 128:9bcdf88f62b0 338 #define EBI_POLARITY_CSPOL_ACTIVELOW (_EBI_POLARITY_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
<> 128:9bcdf88f62b0 339 #define EBI_POLARITY_CSPOL_ACTIVEHIGH (_EBI_POLARITY_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
<> 128:9bcdf88f62b0 340 #define EBI_POLARITY_REPOL (0x1UL << 1) /**< Read Enable Polarity */
<> 128:9bcdf88f62b0 341 #define _EBI_POLARITY_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */
<> 128:9bcdf88f62b0 342 #define _EBI_POLARITY_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */
<> 128:9bcdf88f62b0 343 #define _EBI_POLARITY_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
<> 128:9bcdf88f62b0 344 #define _EBI_POLARITY_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
<> 128:9bcdf88f62b0 345 #define _EBI_POLARITY_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
<> 128:9bcdf88f62b0 346 #define EBI_POLARITY_REPOL_DEFAULT (_EBI_POLARITY_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY */
<> 128:9bcdf88f62b0 347 #define EBI_POLARITY_REPOL_ACTIVELOW (_EBI_POLARITY_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
<> 128:9bcdf88f62b0 348 #define EBI_POLARITY_REPOL_ACTIVEHIGH (_EBI_POLARITY_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
<> 128:9bcdf88f62b0 349 #define EBI_POLARITY_WEPOL (0x1UL << 2) /**< Write Enable Polarity */
<> 128:9bcdf88f62b0 350 #define _EBI_POLARITY_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */
<> 128:9bcdf88f62b0 351 #define _EBI_POLARITY_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */
<> 128:9bcdf88f62b0 352 #define _EBI_POLARITY_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
<> 128:9bcdf88f62b0 353 #define _EBI_POLARITY_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
<> 128:9bcdf88f62b0 354 #define _EBI_POLARITY_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
<> 128:9bcdf88f62b0 355 #define EBI_POLARITY_WEPOL_DEFAULT (_EBI_POLARITY_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY */
<> 128:9bcdf88f62b0 356 #define EBI_POLARITY_WEPOL_ACTIVELOW (_EBI_POLARITY_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
<> 128:9bcdf88f62b0 357 #define EBI_POLARITY_WEPOL_ACTIVEHIGH (_EBI_POLARITY_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
<> 128:9bcdf88f62b0 358 #define EBI_POLARITY_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */
<> 128:9bcdf88f62b0 359 #define _EBI_POLARITY_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */
<> 128:9bcdf88f62b0 360 #define _EBI_POLARITY_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */
<> 128:9bcdf88f62b0 361 #define _EBI_POLARITY_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
<> 128:9bcdf88f62b0 362 #define _EBI_POLARITY_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
<> 128:9bcdf88f62b0 363 #define _EBI_POLARITY_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
<> 128:9bcdf88f62b0 364 #define EBI_POLARITY_ALEPOL_DEFAULT (_EBI_POLARITY_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY */
<> 128:9bcdf88f62b0 365 #define EBI_POLARITY_ALEPOL_ACTIVELOW (_EBI_POLARITY_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
<> 128:9bcdf88f62b0 366 #define EBI_POLARITY_ALEPOL_ACTIVEHIGH (_EBI_POLARITY_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
<> 128:9bcdf88f62b0 367 #define EBI_POLARITY_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */
<> 128:9bcdf88f62b0 368 #define _EBI_POLARITY_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */
<> 128:9bcdf88f62b0 369 #define _EBI_POLARITY_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */
<> 128:9bcdf88f62b0 370 #define _EBI_POLARITY_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
<> 128:9bcdf88f62b0 371 #define _EBI_POLARITY_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
<> 128:9bcdf88f62b0 372 #define _EBI_POLARITY_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
<> 128:9bcdf88f62b0 373 #define EBI_POLARITY_ARDYPOL_DEFAULT (_EBI_POLARITY_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY */
<> 128:9bcdf88f62b0 374 #define EBI_POLARITY_ARDYPOL_ACTIVELOW (_EBI_POLARITY_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
<> 128:9bcdf88f62b0 375 #define EBI_POLARITY_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
<> 128:9bcdf88f62b0 376 #define EBI_POLARITY_BLPOL (0x1UL << 5) /**< BL Polarity */
<> 128:9bcdf88f62b0 377 #define _EBI_POLARITY_BLPOL_SHIFT 5 /**< Shift value for EBI_BLPOL */
<> 128:9bcdf88f62b0 378 #define _EBI_POLARITY_BLPOL_MASK 0x20UL /**< Bit mask for EBI_BLPOL */
<> 128:9bcdf88f62b0 379 #define _EBI_POLARITY_BLPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
<> 128:9bcdf88f62b0 380 #define _EBI_POLARITY_BLPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
<> 128:9bcdf88f62b0 381 #define _EBI_POLARITY_BLPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
<> 128:9bcdf88f62b0 382 #define EBI_POLARITY_BLPOL_DEFAULT (_EBI_POLARITY_BLPOL_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_POLARITY */
<> 128:9bcdf88f62b0 383 #define EBI_POLARITY_BLPOL_ACTIVELOW (_EBI_POLARITY_BLPOL_ACTIVELOW << 5) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
<> 128:9bcdf88f62b0 384 #define EBI_POLARITY_BLPOL_ACTIVEHIGH (_EBI_POLARITY_BLPOL_ACTIVEHIGH << 5) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
<> 128:9bcdf88f62b0 385
<> 128:9bcdf88f62b0 386 /* Bit fields for EBI ROUTE */
<> 128:9bcdf88f62b0 387 #define _EBI_ROUTE_RESETVALUE 0x00000000UL /**< Default value for EBI_ROUTE */
<> 128:9bcdf88f62b0 388 #define _EBI_ROUTE_MASK 0x777F10FFUL /**< Mask for EBI_ROUTE */
<> 128:9bcdf88f62b0 389 #define EBI_ROUTE_EBIPEN (0x1UL << 0) /**< EBI Pin Enable */
<> 128:9bcdf88f62b0 390 #define _EBI_ROUTE_EBIPEN_SHIFT 0 /**< Shift value for EBI_EBIPEN */
<> 128:9bcdf88f62b0 391 #define _EBI_ROUTE_EBIPEN_MASK 0x1UL /**< Bit mask for EBI_EBIPEN */
<> 128:9bcdf88f62b0 392 #define _EBI_ROUTE_EBIPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 393 #define EBI_ROUTE_EBIPEN_DEFAULT (_EBI_ROUTE_EBIPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 394 #define EBI_ROUTE_CS0PEN (0x1UL << 1) /**< EBI_CS0 Pin Enable */
<> 128:9bcdf88f62b0 395 #define _EBI_ROUTE_CS0PEN_SHIFT 1 /**< Shift value for EBI_CS0PEN */
<> 128:9bcdf88f62b0 396 #define _EBI_ROUTE_CS0PEN_MASK 0x2UL /**< Bit mask for EBI_CS0PEN */
<> 128:9bcdf88f62b0 397 #define _EBI_ROUTE_CS0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 398 #define EBI_ROUTE_CS0PEN_DEFAULT (_EBI_ROUTE_CS0PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 399 #define EBI_ROUTE_CS1PEN (0x1UL << 2) /**< EBI_CS1 Pin Enable */
<> 128:9bcdf88f62b0 400 #define _EBI_ROUTE_CS1PEN_SHIFT 2 /**< Shift value for EBI_CS1PEN */
<> 128:9bcdf88f62b0 401 #define _EBI_ROUTE_CS1PEN_MASK 0x4UL /**< Bit mask for EBI_CS1PEN */
<> 128:9bcdf88f62b0 402 #define _EBI_ROUTE_CS1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 403 #define EBI_ROUTE_CS1PEN_DEFAULT (_EBI_ROUTE_CS1PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 404 #define EBI_ROUTE_CS2PEN (0x1UL << 3) /**< EBI_CS2 Pin Enable */
<> 128:9bcdf88f62b0 405 #define _EBI_ROUTE_CS2PEN_SHIFT 3 /**< Shift value for EBI_CS2PEN */
<> 128:9bcdf88f62b0 406 #define _EBI_ROUTE_CS2PEN_MASK 0x8UL /**< Bit mask for EBI_CS2PEN */
<> 128:9bcdf88f62b0 407 #define _EBI_ROUTE_CS2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 408 #define EBI_ROUTE_CS2PEN_DEFAULT (_EBI_ROUTE_CS2PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 409 #define EBI_ROUTE_CS3PEN (0x1UL << 4) /**< EBI_CS3 Pin Enable */
<> 128:9bcdf88f62b0 410 #define _EBI_ROUTE_CS3PEN_SHIFT 4 /**< Shift value for EBI_CS3PEN */
<> 128:9bcdf88f62b0 411 #define _EBI_ROUTE_CS3PEN_MASK 0x10UL /**< Bit mask for EBI_CS3PEN */
<> 128:9bcdf88f62b0 412 #define _EBI_ROUTE_CS3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 413 #define EBI_ROUTE_CS3PEN_DEFAULT (_EBI_ROUTE_CS3PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 414 #define EBI_ROUTE_ALEPEN (0x1UL << 5) /**< EBI_ALE Pin Enable */
<> 128:9bcdf88f62b0 415 #define _EBI_ROUTE_ALEPEN_SHIFT 5 /**< Shift value for EBI_ALEPEN */
<> 128:9bcdf88f62b0 416 #define _EBI_ROUTE_ALEPEN_MASK 0x20UL /**< Bit mask for EBI_ALEPEN */
<> 128:9bcdf88f62b0 417 #define _EBI_ROUTE_ALEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 418 #define EBI_ROUTE_ALEPEN_DEFAULT (_EBI_ROUTE_ALEPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 419 #define EBI_ROUTE_ARDYPEN (0x1UL << 6) /**< EBI_ARDY Pin Enable */
<> 128:9bcdf88f62b0 420 #define _EBI_ROUTE_ARDYPEN_SHIFT 6 /**< Shift value for EBI_ARDYPEN */
<> 128:9bcdf88f62b0 421 #define _EBI_ROUTE_ARDYPEN_MASK 0x40UL /**< Bit mask for EBI_ARDYPEN */
<> 128:9bcdf88f62b0 422 #define _EBI_ROUTE_ARDYPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 423 #define EBI_ROUTE_ARDYPEN_DEFAULT (_EBI_ROUTE_ARDYPEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 424 #define EBI_ROUTE_BLPEN (0x1UL << 7) /**< EBI_BL[1:0] Pin Enable */
<> 128:9bcdf88f62b0 425 #define _EBI_ROUTE_BLPEN_SHIFT 7 /**< Shift value for EBI_BLPEN */
<> 128:9bcdf88f62b0 426 #define _EBI_ROUTE_BLPEN_MASK 0x80UL /**< Bit mask for EBI_BLPEN */
<> 128:9bcdf88f62b0 427 #define _EBI_ROUTE_BLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 428 #define EBI_ROUTE_BLPEN_DEFAULT (_EBI_ROUTE_BLPEN_DEFAULT << 7) /**< Shifted mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 429 #define EBI_ROUTE_NANDPEN (0x1UL << 12) /**< NANDRE and NANDWE Pin Enable */
<> 128:9bcdf88f62b0 430 #define _EBI_ROUTE_NANDPEN_SHIFT 12 /**< Shift value for EBI_NANDPEN */
<> 128:9bcdf88f62b0 431 #define _EBI_ROUTE_NANDPEN_MASK 0x1000UL /**< Bit mask for EBI_NANDPEN */
<> 128:9bcdf88f62b0 432 #define _EBI_ROUTE_NANDPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 433 #define EBI_ROUTE_NANDPEN_DEFAULT (_EBI_ROUTE_NANDPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 434 #define _EBI_ROUTE_ALB_SHIFT 16 /**< Shift value for EBI_ALB */
<> 128:9bcdf88f62b0 435 #define _EBI_ROUTE_ALB_MASK 0x30000UL /**< Bit mask for EBI_ALB */
<> 128:9bcdf88f62b0 436 #define _EBI_ROUTE_ALB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 437 #define _EBI_ROUTE_ALB_A0 0x00000000UL /**< Mode A0 for EBI_ROUTE */
<> 128:9bcdf88f62b0 438 #define _EBI_ROUTE_ALB_A8 0x00000001UL /**< Mode A8 for EBI_ROUTE */
<> 128:9bcdf88f62b0 439 #define _EBI_ROUTE_ALB_A16 0x00000002UL /**< Mode A16 for EBI_ROUTE */
<> 128:9bcdf88f62b0 440 #define _EBI_ROUTE_ALB_A24 0x00000003UL /**< Mode A24 for EBI_ROUTE */
<> 128:9bcdf88f62b0 441 #define EBI_ROUTE_ALB_DEFAULT (_EBI_ROUTE_ALB_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 442 #define EBI_ROUTE_ALB_A0 (_EBI_ROUTE_ALB_A0 << 16) /**< Shifted mode A0 for EBI_ROUTE */
<> 128:9bcdf88f62b0 443 #define EBI_ROUTE_ALB_A8 (_EBI_ROUTE_ALB_A8 << 16) /**< Shifted mode A8 for EBI_ROUTE */
<> 128:9bcdf88f62b0 444 #define EBI_ROUTE_ALB_A16 (_EBI_ROUTE_ALB_A16 << 16) /**< Shifted mode A16 for EBI_ROUTE */
<> 128:9bcdf88f62b0 445 #define EBI_ROUTE_ALB_A24 (_EBI_ROUTE_ALB_A24 << 16) /**< Shifted mode A24 for EBI_ROUTE */
<> 128:9bcdf88f62b0 446 #define _EBI_ROUTE_APEN_SHIFT 18 /**< Shift value for EBI_APEN */
<> 128:9bcdf88f62b0 447 #define _EBI_ROUTE_APEN_MASK 0x7C0000UL /**< Bit mask for EBI_APEN */
<> 128:9bcdf88f62b0 448 #define _EBI_ROUTE_APEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 449 #define _EBI_ROUTE_APEN_A0 0x00000000UL /**< Mode A0 for EBI_ROUTE */
<> 128:9bcdf88f62b0 450 #define _EBI_ROUTE_APEN_A5 0x00000005UL /**< Mode A5 for EBI_ROUTE */
<> 128:9bcdf88f62b0 451 #define _EBI_ROUTE_APEN_A6 0x00000006UL /**< Mode A6 for EBI_ROUTE */
<> 128:9bcdf88f62b0 452 #define _EBI_ROUTE_APEN_A7 0x00000007UL /**< Mode A7 for EBI_ROUTE */
<> 128:9bcdf88f62b0 453 #define _EBI_ROUTE_APEN_A8 0x00000008UL /**< Mode A8 for EBI_ROUTE */
<> 128:9bcdf88f62b0 454 #define _EBI_ROUTE_APEN_A9 0x00000009UL /**< Mode A9 for EBI_ROUTE */
<> 128:9bcdf88f62b0 455 #define _EBI_ROUTE_APEN_A10 0x0000000AUL /**< Mode A10 for EBI_ROUTE */
<> 128:9bcdf88f62b0 456 #define _EBI_ROUTE_APEN_A11 0x0000000BUL /**< Mode A11 for EBI_ROUTE */
<> 128:9bcdf88f62b0 457 #define _EBI_ROUTE_APEN_A12 0x0000000CUL /**< Mode A12 for EBI_ROUTE */
<> 128:9bcdf88f62b0 458 #define _EBI_ROUTE_APEN_A13 0x0000000DUL /**< Mode A13 for EBI_ROUTE */
<> 128:9bcdf88f62b0 459 #define _EBI_ROUTE_APEN_A14 0x0000000EUL /**< Mode A14 for EBI_ROUTE */
<> 128:9bcdf88f62b0 460 #define _EBI_ROUTE_APEN_A15 0x0000000FUL /**< Mode A15 for EBI_ROUTE */
<> 128:9bcdf88f62b0 461 #define _EBI_ROUTE_APEN_A16 0x00000010UL /**< Mode A16 for EBI_ROUTE */
<> 128:9bcdf88f62b0 462 #define _EBI_ROUTE_APEN_A17 0x00000011UL /**< Mode A17 for EBI_ROUTE */
<> 128:9bcdf88f62b0 463 #define _EBI_ROUTE_APEN_A18 0x00000012UL /**< Mode A18 for EBI_ROUTE */
<> 128:9bcdf88f62b0 464 #define _EBI_ROUTE_APEN_A19 0x00000013UL /**< Mode A19 for EBI_ROUTE */
<> 128:9bcdf88f62b0 465 #define _EBI_ROUTE_APEN_A20 0x00000014UL /**< Mode A20 for EBI_ROUTE */
<> 128:9bcdf88f62b0 466 #define _EBI_ROUTE_APEN_A21 0x00000015UL /**< Mode A21 for EBI_ROUTE */
<> 128:9bcdf88f62b0 467 #define _EBI_ROUTE_APEN_A22 0x00000016UL /**< Mode A22 for EBI_ROUTE */
<> 128:9bcdf88f62b0 468 #define _EBI_ROUTE_APEN_A23 0x00000017UL /**< Mode A23 for EBI_ROUTE */
<> 128:9bcdf88f62b0 469 #define _EBI_ROUTE_APEN_A24 0x00000018UL /**< Mode A24 for EBI_ROUTE */
<> 128:9bcdf88f62b0 470 #define _EBI_ROUTE_APEN_A25 0x00000019UL /**< Mode A25 for EBI_ROUTE */
<> 128:9bcdf88f62b0 471 #define _EBI_ROUTE_APEN_A26 0x0000001AUL /**< Mode A26 for EBI_ROUTE */
<> 128:9bcdf88f62b0 472 #define _EBI_ROUTE_APEN_A27 0x0000001BUL /**< Mode A27 for EBI_ROUTE */
<> 128:9bcdf88f62b0 473 #define _EBI_ROUTE_APEN_A28 0x0000001CUL /**< Mode A28 for EBI_ROUTE */
<> 128:9bcdf88f62b0 474 #define EBI_ROUTE_APEN_DEFAULT (_EBI_ROUTE_APEN_DEFAULT << 18) /**< Shifted mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 475 #define EBI_ROUTE_APEN_A0 (_EBI_ROUTE_APEN_A0 << 18) /**< Shifted mode A0 for EBI_ROUTE */
<> 128:9bcdf88f62b0 476 #define EBI_ROUTE_APEN_A5 (_EBI_ROUTE_APEN_A5 << 18) /**< Shifted mode A5 for EBI_ROUTE */
<> 128:9bcdf88f62b0 477 #define EBI_ROUTE_APEN_A6 (_EBI_ROUTE_APEN_A6 << 18) /**< Shifted mode A6 for EBI_ROUTE */
<> 128:9bcdf88f62b0 478 #define EBI_ROUTE_APEN_A7 (_EBI_ROUTE_APEN_A7 << 18) /**< Shifted mode A7 for EBI_ROUTE */
<> 128:9bcdf88f62b0 479 #define EBI_ROUTE_APEN_A8 (_EBI_ROUTE_APEN_A8 << 18) /**< Shifted mode A8 for EBI_ROUTE */
<> 128:9bcdf88f62b0 480 #define EBI_ROUTE_APEN_A9 (_EBI_ROUTE_APEN_A9 << 18) /**< Shifted mode A9 for EBI_ROUTE */
<> 128:9bcdf88f62b0 481 #define EBI_ROUTE_APEN_A10 (_EBI_ROUTE_APEN_A10 << 18) /**< Shifted mode A10 for EBI_ROUTE */
<> 128:9bcdf88f62b0 482 #define EBI_ROUTE_APEN_A11 (_EBI_ROUTE_APEN_A11 << 18) /**< Shifted mode A11 for EBI_ROUTE */
<> 128:9bcdf88f62b0 483 #define EBI_ROUTE_APEN_A12 (_EBI_ROUTE_APEN_A12 << 18) /**< Shifted mode A12 for EBI_ROUTE */
<> 128:9bcdf88f62b0 484 #define EBI_ROUTE_APEN_A13 (_EBI_ROUTE_APEN_A13 << 18) /**< Shifted mode A13 for EBI_ROUTE */
<> 128:9bcdf88f62b0 485 #define EBI_ROUTE_APEN_A14 (_EBI_ROUTE_APEN_A14 << 18) /**< Shifted mode A14 for EBI_ROUTE */
<> 128:9bcdf88f62b0 486 #define EBI_ROUTE_APEN_A15 (_EBI_ROUTE_APEN_A15 << 18) /**< Shifted mode A15 for EBI_ROUTE */
<> 128:9bcdf88f62b0 487 #define EBI_ROUTE_APEN_A16 (_EBI_ROUTE_APEN_A16 << 18) /**< Shifted mode A16 for EBI_ROUTE */
<> 128:9bcdf88f62b0 488 #define EBI_ROUTE_APEN_A17 (_EBI_ROUTE_APEN_A17 << 18) /**< Shifted mode A17 for EBI_ROUTE */
<> 128:9bcdf88f62b0 489 #define EBI_ROUTE_APEN_A18 (_EBI_ROUTE_APEN_A18 << 18) /**< Shifted mode A18 for EBI_ROUTE */
<> 128:9bcdf88f62b0 490 #define EBI_ROUTE_APEN_A19 (_EBI_ROUTE_APEN_A19 << 18) /**< Shifted mode A19 for EBI_ROUTE */
<> 128:9bcdf88f62b0 491 #define EBI_ROUTE_APEN_A20 (_EBI_ROUTE_APEN_A20 << 18) /**< Shifted mode A20 for EBI_ROUTE */
<> 128:9bcdf88f62b0 492 #define EBI_ROUTE_APEN_A21 (_EBI_ROUTE_APEN_A21 << 18) /**< Shifted mode A21 for EBI_ROUTE */
<> 128:9bcdf88f62b0 493 #define EBI_ROUTE_APEN_A22 (_EBI_ROUTE_APEN_A22 << 18) /**< Shifted mode A22 for EBI_ROUTE */
<> 128:9bcdf88f62b0 494 #define EBI_ROUTE_APEN_A23 (_EBI_ROUTE_APEN_A23 << 18) /**< Shifted mode A23 for EBI_ROUTE */
<> 128:9bcdf88f62b0 495 #define EBI_ROUTE_APEN_A24 (_EBI_ROUTE_APEN_A24 << 18) /**< Shifted mode A24 for EBI_ROUTE */
<> 128:9bcdf88f62b0 496 #define EBI_ROUTE_APEN_A25 (_EBI_ROUTE_APEN_A25 << 18) /**< Shifted mode A25 for EBI_ROUTE */
<> 128:9bcdf88f62b0 497 #define EBI_ROUTE_APEN_A26 (_EBI_ROUTE_APEN_A26 << 18) /**< Shifted mode A26 for EBI_ROUTE */
<> 128:9bcdf88f62b0 498 #define EBI_ROUTE_APEN_A27 (_EBI_ROUTE_APEN_A27 << 18) /**< Shifted mode A27 for EBI_ROUTE */
<> 128:9bcdf88f62b0 499 #define EBI_ROUTE_APEN_A28 (_EBI_ROUTE_APEN_A28 << 18) /**< Shifted mode A28 for EBI_ROUTE */
<> 128:9bcdf88f62b0 500 #define EBI_ROUTE_TFTPEN (0x1UL << 24) /**< EBI_TFT Pin Enable */
<> 128:9bcdf88f62b0 501 #define _EBI_ROUTE_TFTPEN_SHIFT 24 /**< Shift value for EBI_TFTPEN */
<> 128:9bcdf88f62b0 502 #define _EBI_ROUTE_TFTPEN_MASK 0x1000000UL /**< Bit mask for EBI_TFTPEN */
<> 128:9bcdf88f62b0 503 #define _EBI_ROUTE_TFTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 504 #define EBI_ROUTE_TFTPEN_DEFAULT (_EBI_ROUTE_TFTPEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 505 #define EBI_ROUTE_DATAENPEN (0x1UL << 25) /**< EBI_TFT Pin Enable */
<> 128:9bcdf88f62b0 506 #define _EBI_ROUTE_DATAENPEN_SHIFT 25 /**< Shift value for EBI_DATAENPEN */
<> 128:9bcdf88f62b0 507 #define _EBI_ROUTE_DATAENPEN_MASK 0x2000000UL /**< Bit mask for EBI_DATAENPEN */
<> 128:9bcdf88f62b0 508 #define _EBI_ROUTE_DATAENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 509 #define EBI_ROUTE_DATAENPEN_DEFAULT (_EBI_ROUTE_DATAENPEN_DEFAULT << 25) /**< Shifted mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 510 #define EBI_ROUTE_CSTFTPEN (0x1UL << 26) /**< EBI_CSTFT Pin Enable */
<> 128:9bcdf88f62b0 511 #define _EBI_ROUTE_CSTFTPEN_SHIFT 26 /**< Shift value for EBI_CSTFTPEN */
<> 128:9bcdf88f62b0 512 #define _EBI_ROUTE_CSTFTPEN_MASK 0x4000000UL /**< Bit mask for EBI_CSTFTPEN */
<> 128:9bcdf88f62b0 513 #define _EBI_ROUTE_CSTFTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 514 #define EBI_ROUTE_CSTFTPEN_DEFAULT (_EBI_ROUTE_CSTFTPEN_DEFAULT << 26) /**< Shifted mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 515 #define _EBI_ROUTE_LOCATION_SHIFT 28 /**< Shift value for EBI_LOCATION */
<> 128:9bcdf88f62b0 516 #define _EBI_ROUTE_LOCATION_MASK 0x70000000UL /**< Bit mask for EBI_LOCATION */
<> 128:9bcdf88f62b0 517 #define _EBI_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for EBI_ROUTE */
<> 128:9bcdf88f62b0 518 #define _EBI_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 519 #define _EBI_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for EBI_ROUTE */
<> 128:9bcdf88f62b0 520 #define _EBI_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for EBI_ROUTE */
<> 128:9bcdf88f62b0 521 #define EBI_ROUTE_LOCATION_LOC0 (_EBI_ROUTE_LOCATION_LOC0 << 28) /**< Shifted mode LOC0 for EBI_ROUTE */
<> 128:9bcdf88f62b0 522 #define EBI_ROUTE_LOCATION_DEFAULT (_EBI_ROUTE_LOCATION_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ROUTE */
<> 128:9bcdf88f62b0 523 #define EBI_ROUTE_LOCATION_LOC1 (_EBI_ROUTE_LOCATION_LOC1 << 28) /**< Shifted mode LOC1 for EBI_ROUTE */
<> 128:9bcdf88f62b0 524 #define EBI_ROUTE_LOCATION_LOC2 (_EBI_ROUTE_LOCATION_LOC2 << 28) /**< Shifted mode LOC2 for EBI_ROUTE */
<> 128:9bcdf88f62b0 525
<> 128:9bcdf88f62b0 526 /* Bit fields for EBI ADDRTIMING1 */
<> 128:9bcdf88f62b0 527 #define _EBI_ADDRTIMING1_RESETVALUE 0x00000303UL /**< Default value for EBI_ADDRTIMING1 */
<> 128:9bcdf88f62b0 528 #define _EBI_ADDRTIMING1_MASK 0x10000303UL /**< Mask for EBI_ADDRTIMING1 */
<> 128:9bcdf88f62b0 529 #define _EBI_ADDRTIMING1_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */
<> 128:9bcdf88f62b0 530 #define _EBI_ADDRTIMING1_ADDRSETUP_MASK 0x3UL /**< Bit mask for EBI_ADDRSETUP */
<> 128:9bcdf88f62b0 531 #define _EBI_ADDRTIMING1_ADDRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING1 */
<> 128:9bcdf88f62b0 532 #define EBI_ADDRTIMING1_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING1_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING1 */
<> 128:9bcdf88f62b0 533 #define _EBI_ADDRTIMING1_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */
<> 128:9bcdf88f62b0 534 #define _EBI_ADDRTIMING1_ADDRHOLD_MASK 0x300UL /**< Bit mask for EBI_ADDRHOLD */
<> 128:9bcdf88f62b0 535 #define _EBI_ADDRTIMING1_ADDRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING1 */
<> 128:9bcdf88f62b0 536 #define EBI_ADDRTIMING1_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING1_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING1 */
<> 128:9bcdf88f62b0 537 #define EBI_ADDRTIMING1_HALFALE (0x1UL << 28) /**< Half Cycle ALE Strobe Duration Enable */
<> 128:9bcdf88f62b0 538 #define _EBI_ADDRTIMING1_HALFALE_SHIFT 28 /**< Shift value for EBI_HALFALE */
<> 128:9bcdf88f62b0 539 #define _EBI_ADDRTIMING1_HALFALE_MASK 0x10000000UL /**< Bit mask for EBI_HALFALE */
<> 128:9bcdf88f62b0 540 #define _EBI_ADDRTIMING1_HALFALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING1 */
<> 128:9bcdf88f62b0 541 #define EBI_ADDRTIMING1_HALFALE_DEFAULT (_EBI_ADDRTIMING1_HALFALE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ADDRTIMING1 */
<> 128:9bcdf88f62b0 542
<> 128:9bcdf88f62b0 543 /* Bit fields for EBI RDTIMING1 */
<> 128:9bcdf88f62b0 544 #define _EBI_RDTIMING1_RESETVALUE 0x00033F03UL /**< Default value for EBI_RDTIMING1 */
<> 128:9bcdf88f62b0 545 #define _EBI_RDTIMING1_MASK 0x70033F03UL /**< Mask for EBI_RDTIMING1 */
<> 128:9bcdf88f62b0 546 #define _EBI_RDTIMING1_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */
<> 128:9bcdf88f62b0 547 #define _EBI_RDTIMING1_RDSETUP_MASK 0x3UL /**< Bit mask for EBI_RDSETUP */
<> 128:9bcdf88f62b0 548 #define _EBI_RDTIMING1_RDSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING1 */
<> 128:9bcdf88f62b0 549 #define EBI_RDTIMING1_RDSETUP_DEFAULT (_EBI_RDTIMING1_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */
<> 128:9bcdf88f62b0 550 #define _EBI_RDTIMING1_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */
<> 128:9bcdf88f62b0 551 #define _EBI_RDTIMING1_RDSTRB_MASK 0x3F00UL /**< Bit mask for EBI_RDSTRB */
<> 128:9bcdf88f62b0 552 #define _EBI_RDTIMING1_RDSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_RDTIMING1 */
<> 128:9bcdf88f62b0 553 #define EBI_RDTIMING1_RDSTRB_DEFAULT (_EBI_RDTIMING1_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */
<> 128:9bcdf88f62b0 554 #define _EBI_RDTIMING1_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */
<> 128:9bcdf88f62b0 555 #define _EBI_RDTIMING1_RDHOLD_MASK 0x30000UL /**< Bit mask for EBI_RDHOLD */
<> 128:9bcdf88f62b0 556 #define _EBI_RDTIMING1_RDHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING1 */
<> 128:9bcdf88f62b0 557 #define EBI_RDTIMING1_RDHOLD_DEFAULT (_EBI_RDTIMING1_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */
<> 128:9bcdf88f62b0 558 #define EBI_RDTIMING1_HALFRE (0x1UL << 28) /**< Half Cycle REn Strobe Duration Enable */
<> 128:9bcdf88f62b0 559 #define _EBI_RDTIMING1_HALFRE_SHIFT 28 /**< Shift value for EBI_HALFRE */
<> 128:9bcdf88f62b0 560 #define _EBI_RDTIMING1_HALFRE_MASK 0x10000000UL /**< Bit mask for EBI_HALFRE */
<> 128:9bcdf88f62b0 561 #define _EBI_RDTIMING1_HALFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING1 */
<> 128:9bcdf88f62b0 562 #define EBI_RDTIMING1_HALFRE_DEFAULT (_EBI_RDTIMING1_HALFRE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */
<> 128:9bcdf88f62b0 563 #define EBI_RDTIMING1_PREFETCH (0x1UL << 29) /**< Prefetch Enable */
<> 128:9bcdf88f62b0 564 #define _EBI_RDTIMING1_PREFETCH_SHIFT 29 /**< Shift value for EBI_PREFETCH */
<> 128:9bcdf88f62b0 565 #define _EBI_RDTIMING1_PREFETCH_MASK 0x20000000UL /**< Bit mask for EBI_PREFETCH */
<> 128:9bcdf88f62b0 566 #define _EBI_RDTIMING1_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING1 */
<> 128:9bcdf88f62b0 567 #define EBI_RDTIMING1_PREFETCH_DEFAULT (_EBI_RDTIMING1_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */
<> 128:9bcdf88f62b0 568 #define EBI_RDTIMING1_PAGEMODE (0x1UL << 30) /**< Page Mode Access Enable */
<> 128:9bcdf88f62b0 569 #define _EBI_RDTIMING1_PAGEMODE_SHIFT 30 /**< Shift value for EBI_PAGEMODE */
<> 128:9bcdf88f62b0 570 #define _EBI_RDTIMING1_PAGEMODE_MASK 0x40000000UL /**< Bit mask for EBI_PAGEMODE */
<> 128:9bcdf88f62b0 571 #define _EBI_RDTIMING1_PAGEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING1 */
<> 128:9bcdf88f62b0 572 #define EBI_RDTIMING1_PAGEMODE_DEFAULT (_EBI_RDTIMING1_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */
<> 128:9bcdf88f62b0 573
<> 128:9bcdf88f62b0 574 /* Bit fields for EBI WRTIMING1 */
<> 128:9bcdf88f62b0 575 #define _EBI_WRTIMING1_RESETVALUE 0x00033F03UL /**< Default value for EBI_WRTIMING1 */
<> 128:9bcdf88f62b0 576 #define _EBI_WRTIMING1_MASK 0x30033F03UL /**< Mask for EBI_WRTIMING1 */
<> 128:9bcdf88f62b0 577 #define _EBI_WRTIMING1_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */
<> 128:9bcdf88f62b0 578 #define _EBI_WRTIMING1_WRSETUP_MASK 0x3UL /**< Bit mask for EBI_WRSETUP */
<> 128:9bcdf88f62b0 579 #define _EBI_WRTIMING1_WRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING1 */
<> 128:9bcdf88f62b0 580 #define EBI_WRTIMING1_WRSETUP_DEFAULT (_EBI_WRTIMING1_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */
<> 128:9bcdf88f62b0 581 #define _EBI_WRTIMING1_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */
<> 128:9bcdf88f62b0 582 #define _EBI_WRTIMING1_WRSTRB_MASK 0x3F00UL /**< Bit mask for EBI_WRSTRB */
<> 128:9bcdf88f62b0 583 #define _EBI_WRTIMING1_WRSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_WRTIMING1 */
<> 128:9bcdf88f62b0 584 #define EBI_WRTIMING1_WRSTRB_DEFAULT (_EBI_WRTIMING1_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */
<> 128:9bcdf88f62b0 585 #define _EBI_WRTIMING1_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */
<> 128:9bcdf88f62b0 586 #define _EBI_WRTIMING1_WRHOLD_MASK 0x30000UL /**< Bit mask for EBI_WRHOLD */
<> 128:9bcdf88f62b0 587 #define _EBI_WRTIMING1_WRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING1 */
<> 128:9bcdf88f62b0 588 #define EBI_WRTIMING1_WRHOLD_DEFAULT (_EBI_WRTIMING1_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */
<> 128:9bcdf88f62b0 589 #define EBI_WRTIMING1_HALFWE (0x1UL << 28) /**< Half Cycle WEn Strobe Duration Enable */
<> 128:9bcdf88f62b0 590 #define _EBI_WRTIMING1_HALFWE_SHIFT 28 /**< Shift value for EBI_HALFWE */
<> 128:9bcdf88f62b0 591 #define _EBI_WRTIMING1_HALFWE_MASK 0x10000000UL /**< Bit mask for EBI_HALFWE */
<> 128:9bcdf88f62b0 592 #define _EBI_WRTIMING1_HALFWE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING1 */
<> 128:9bcdf88f62b0 593 #define EBI_WRTIMING1_HALFWE_DEFAULT (_EBI_WRTIMING1_HALFWE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */
<> 128:9bcdf88f62b0 594 #define EBI_WRTIMING1_WBUFDIS (0x1UL << 29) /**< Write Buffer Disable */
<> 128:9bcdf88f62b0 595 #define _EBI_WRTIMING1_WBUFDIS_SHIFT 29 /**< Shift value for EBI_WBUFDIS */
<> 128:9bcdf88f62b0 596 #define _EBI_WRTIMING1_WBUFDIS_MASK 0x20000000UL /**< Bit mask for EBI_WBUFDIS */
<> 128:9bcdf88f62b0 597 #define _EBI_WRTIMING1_WBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING1 */
<> 128:9bcdf88f62b0 598 #define EBI_WRTIMING1_WBUFDIS_DEFAULT (_EBI_WRTIMING1_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */
<> 128:9bcdf88f62b0 599
<> 128:9bcdf88f62b0 600 /* Bit fields for EBI POLARITY1 */
<> 128:9bcdf88f62b0 601 #define _EBI_POLARITY1_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 602 #define _EBI_POLARITY1_MASK 0x0000003FUL /**< Mask for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 603 #define EBI_POLARITY1_CSPOL (0x1UL << 0) /**< Chip Select Polarity */
<> 128:9bcdf88f62b0 604 #define _EBI_POLARITY1_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */
<> 128:9bcdf88f62b0 605 #define _EBI_POLARITY1_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */
<> 128:9bcdf88f62b0 606 #define _EBI_POLARITY1_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 607 #define _EBI_POLARITY1_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 608 #define _EBI_POLARITY1_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 609 #define EBI_POLARITY1_CSPOL_DEFAULT (_EBI_POLARITY1_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 610 #define EBI_POLARITY1_CSPOL_ACTIVELOW (_EBI_POLARITY1_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 611 #define EBI_POLARITY1_CSPOL_ACTIVEHIGH (_EBI_POLARITY1_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 612 #define EBI_POLARITY1_REPOL (0x1UL << 1) /**< Read Enable Polarity */
<> 128:9bcdf88f62b0 613 #define _EBI_POLARITY1_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */
<> 128:9bcdf88f62b0 614 #define _EBI_POLARITY1_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */
<> 128:9bcdf88f62b0 615 #define _EBI_POLARITY1_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 616 #define _EBI_POLARITY1_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 617 #define _EBI_POLARITY1_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 618 #define EBI_POLARITY1_REPOL_DEFAULT (_EBI_POLARITY1_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 619 #define EBI_POLARITY1_REPOL_ACTIVELOW (_EBI_POLARITY1_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 620 #define EBI_POLARITY1_REPOL_ACTIVEHIGH (_EBI_POLARITY1_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 621 #define EBI_POLARITY1_WEPOL (0x1UL << 2) /**< Write Enable Polarity */
<> 128:9bcdf88f62b0 622 #define _EBI_POLARITY1_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */
<> 128:9bcdf88f62b0 623 #define _EBI_POLARITY1_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */
<> 128:9bcdf88f62b0 624 #define _EBI_POLARITY1_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 625 #define _EBI_POLARITY1_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 626 #define _EBI_POLARITY1_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 627 #define EBI_POLARITY1_WEPOL_DEFAULT (_EBI_POLARITY1_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 628 #define EBI_POLARITY1_WEPOL_ACTIVELOW (_EBI_POLARITY1_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 629 #define EBI_POLARITY1_WEPOL_ACTIVEHIGH (_EBI_POLARITY1_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 630 #define EBI_POLARITY1_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */
<> 128:9bcdf88f62b0 631 #define _EBI_POLARITY1_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */
<> 128:9bcdf88f62b0 632 #define _EBI_POLARITY1_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */
<> 128:9bcdf88f62b0 633 #define _EBI_POLARITY1_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 634 #define _EBI_POLARITY1_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 635 #define _EBI_POLARITY1_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 636 #define EBI_POLARITY1_ALEPOL_DEFAULT (_EBI_POLARITY1_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 637 #define EBI_POLARITY1_ALEPOL_ACTIVELOW (_EBI_POLARITY1_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 638 #define EBI_POLARITY1_ALEPOL_ACTIVEHIGH (_EBI_POLARITY1_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 639 #define EBI_POLARITY1_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */
<> 128:9bcdf88f62b0 640 #define _EBI_POLARITY1_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */
<> 128:9bcdf88f62b0 641 #define _EBI_POLARITY1_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */
<> 128:9bcdf88f62b0 642 #define _EBI_POLARITY1_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 643 #define _EBI_POLARITY1_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 644 #define _EBI_POLARITY1_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 645 #define EBI_POLARITY1_ARDYPOL_DEFAULT (_EBI_POLARITY1_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 646 #define EBI_POLARITY1_ARDYPOL_ACTIVELOW (_EBI_POLARITY1_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 647 #define EBI_POLARITY1_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY1_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 648 #define EBI_POLARITY1_BLPOL (0x1UL << 5) /**< BL Polarity */
<> 128:9bcdf88f62b0 649 #define _EBI_POLARITY1_BLPOL_SHIFT 5 /**< Shift value for EBI_BLPOL */
<> 128:9bcdf88f62b0 650 #define _EBI_POLARITY1_BLPOL_MASK 0x20UL /**< Bit mask for EBI_BLPOL */
<> 128:9bcdf88f62b0 651 #define _EBI_POLARITY1_BLPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 652 #define _EBI_POLARITY1_BLPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 653 #define _EBI_POLARITY1_BLPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 654 #define EBI_POLARITY1_BLPOL_DEFAULT (_EBI_POLARITY1_BLPOL_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 655 #define EBI_POLARITY1_BLPOL_ACTIVELOW (_EBI_POLARITY1_BLPOL_ACTIVELOW << 5) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 656 #define EBI_POLARITY1_BLPOL_ACTIVEHIGH (_EBI_POLARITY1_BLPOL_ACTIVEHIGH << 5) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */
<> 128:9bcdf88f62b0 657
<> 128:9bcdf88f62b0 658 /* Bit fields for EBI ADDRTIMING2 */
<> 128:9bcdf88f62b0 659 #define _EBI_ADDRTIMING2_RESETVALUE 0x00000303UL /**< Default value for EBI_ADDRTIMING2 */
<> 128:9bcdf88f62b0 660 #define _EBI_ADDRTIMING2_MASK 0x10000303UL /**< Mask for EBI_ADDRTIMING2 */
<> 128:9bcdf88f62b0 661 #define _EBI_ADDRTIMING2_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */
<> 128:9bcdf88f62b0 662 #define _EBI_ADDRTIMING2_ADDRSETUP_MASK 0x3UL /**< Bit mask for EBI_ADDRSETUP */
<> 128:9bcdf88f62b0 663 #define _EBI_ADDRTIMING2_ADDRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING2 */
<> 128:9bcdf88f62b0 664 #define EBI_ADDRTIMING2_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING2_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING2 */
<> 128:9bcdf88f62b0 665 #define _EBI_ADDRTIMING2_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */
<> 128:9bcdf88f62b0 666 #define _EBI_ADDRTIMING2_ADDRHOLD_MASK 0x300UL /**< Bit mask for EBI_ADDRHOLD */
<> 128:9bcdf88f62b0 667 #define _EBI_ADDRTIMING2_ADDRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING2 */
<> 128:9bcdf88f62b0 668 #define EBI_ADDRTIMING2_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING2_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING2 */
<> 128:9bcdf88f62b0 669 #define EBI_ADDRTIMING2_HALFALE (0x1UL << 28) /**< Half Cycle ALE Strobe Duration Enable */
<> 128:9bcdf88f62b0 670 #define _EBI_ADDRTIMING2_HALFALE_SHIFT 28 /**< Shift value for EBI_HALFALE */
<> 128:9bcdf88f62b0 671 #define _EBI_ADDRTIMING2_HALFALE_MASK 0x10000000UL /**< Bit mask for EBI_HALFALE */
<> 128:9bcdf88f62b0 672 #define _EBI_ADDRTIMING2_HALFALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING2 */
<> 128:9bcdf88f62b0 673 #define EBI_ADDRTIMING2_HALFALE_DEFAULT (_EBI_ADDRTIMING2_HALFALE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ADDRTIMING2 */
<> 128:9bcdf88f62b0 674
<> 128:9bcdf88f62b0 675 /* Bit fields for EBI RDTIMING2 */
<> 128:9bcdf88f62b0 676 #define _EBI_RDTIMING2_RESETVALUE 0x00033F03UL /**< Default value for EBI_RDTIMING2 */
<> 128:9bcdf88f62b0 677 #define _EBI_RDTIMING2_MASK 0x70033F03UL /**< Mask for EBI_RDTIMING2 */
<> 128:9bcdf88f62b0 678 #define _EBI_RDTIMING2_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */
<> 128:9bcdf88f62b0 679 #define _EBI_RDTIMING2_RDSETUP_MASK 0x3UL /**< Bit mask for EBI_RDSETUP */
<> 128:9bcdf88f62b0 680 #define _EBI_RDTIMING2_RDSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING2 */
<> 128:9bcdf88f62b0 681 #define EBI_RDTIMING2_RDSETUP_DEFAULT (_EBI_RDTIMING2_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */
<> 128:9bcdf88f62b0 682 #define _EBI_RDTIMING2_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */
<> 128:9bcdf88f62b0 683 #define _EBI_RDTIMING2_RDSTRB_MASK 0x3F00UL /**< Bit mask for EBI_RDSTRB */
<> 128:9bcdf88f62b0 684 #define _EBI_RDTIMING2_RDSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_RDTIMING2 */
<> 128:9bcdf88f62b0 685 #define EBI_RDTIMING2_RDSTRB_DEFAULT (_EBI_RDTIMING2_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */
<> 128:9bcdf88f62b0 686 #define _EBI_RDTIMING2_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */
<> 128:9bcdf88f62b0 687 #define _EBI_RDTIMING2_RDHOLD_MASK 0x30000UL /**< Bit mask for EBI_RDHOLD */
<> 128:9bcdf88f62b0 688 #define _EBI_RDTIMING2_RDHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING2 */
<> 128:9bcdf88f62b0 689 #define EBI_RDTIMING2_RDHOLD_DEFAULT (_EBI_RDTIMING2_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */
<> 128:9bcdf88f62b0 690 #define EBI_RDTIMING2_HALFRE (0x1UL << 28) /**< Half Cycle REn Strobe Duration Enable */
<> 128:9bcdf88f62b0 691 #define _EBI_RDTIMING2_HALFRE_SHIFT 28 /**< Shift value for EBI_HALFRE */
<> 128:9bcdf88f62b0 692 #define _EBI_RDTIMING2_HALFRE_MASK 0x10000000UL /**< Bit mask for EBI_HALFRE */
<> 128:9bcdf88f62b0 693 #define _EBI_RDTIMING2_HALFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING2 */
<> 128:9bcdf88f62b0 694 #define EBI_RDTIMING2_HALFRE_DEFAULT (_EBI_RDTIMING2_HALFRE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */
<> 128:9bcdf88f62b0 695 #define EBI_RDTIMING2_PREFETCH (0x1UL << 29) /**< Prefetch Enable */
<> 128:9bcdf88f62b0 696 #define _EBI_RDTIMING2_PREFETCH_SHIFT 29 /**< Shift value for EBI_PREFETCH */
<> 128:9bcdf88f62b0 697 #define _EBI_RDTIMING2_PREFETCH_MASK 0x20000000UL /**< Bit mask for EBI_PREFETCH */
<> 128:9bcdf88f62b0 698 #define _EBI_RDTIMING2_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING2 */
<> 128:9bcdf88f62b0 699 #define EBI_RDTIMING2_PREFETCH_DEFAULT (_EBI_RDTIMING2_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */
<> 128:9bcdf88f62b0 700 #define EBI_RDTIMING2_PAGEMODE (0x1UL << 30) /**< Page Mode Access Enable */
<> 128:9bcdf88f62b0 701 #define _EBI_RDTIMING2_PAGEMODE_SHIFT 30 /**< Shift value for EBI_PAGEMODE */
<> 128:9bcdf88f62b0 702 #define _EBI_RDTIMING2_PAGEMODE_MASK 0x40000000UL /**< Bit mask for EBI_PAGEMODE */
<> 128:9bcdf88f62b0 703 #define _EBI_RDTIMING2_PAGEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING2 */
<> 128:9bcdf88f62b0 704 #define EBI_RDTIMING2_PAGEMODE_DEFAULT (_EBI_RDTIMING2_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */
<> 128:9bcdf88f62b0 705
<> 128:9bcdf88f62b0 706 /* Bit fields for EBI WRTIMING2 */
<> 128:9bcdf88f62b0 707 #define _EBI_WRTIMING2_RESETVALUE 0x00033F03UL /**< Default value for EBI_WRTIMING2 */
<> 128:9bcdf88f62b0 708 #define _EBI_WRTIMING2_MASK 0x30033F03UL /**< Mask for EBI_WRTIMING2 */
<> 128:9bcdf88f62b0 709 #define _EBI_WRTIMING2_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */
<> 128:9bcdf88f62b0 710 #define _EBI_WRTIMING2_WRSETUP_MASK 0x3UL /**< Bit mask for EBI_WRSETUP */
<> 128:9bcdf88f62b0 711 #define _EBI_WRTIMING2_WRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING2 */
<> 128:9bcdf88f62b0 712 #define EBI_WRTIMING2_WRSETUP_DEFAULT (_EBI_WRTIMING2_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */
<> 128:9bcdf88f62b0 713 #define _EBI_WRTIMING2_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */
<> 128:9bcdf88f62b0 714 #define _EBI_WRTIMING2_WRSTRB_MASK 0x3F00UL /**< Bit mask for EBI_WRSTRB */
<> 128:9bcdf88f62b0 715 #define _EBI_WRTIMING2_WRSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_WRTIMING2 */
<> 128:9bcdf88f62b0 716 #define EBI_WRTIMING2_WRSTRB_DEFAULT (_EBI_WRTIMING2_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */
<> 128:9bcdf88f62b0 717 #define _EBI_WRTIMING2_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */
<> 128:9bcdf88f62b0 718 #define _EBI_WRTIMING2_WRHOLD_MASK 0x30000UL /**< Bit mask for EBI_WRHOLD */
<> 128:9bcdf88f62b0 719 #define _EBI_WRTIMING2_WRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING2 */
<> 128:9bcdf88f62b0 720 #define EBI_WRTIMING2_WRHOLD_DEFAULT (_EBI_WRTIMING2_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */
<> 128:9bcdf88f62b0 721 #define EBI_WRTIMING2_HALFWE (0x1UL << 28) /**< Half Cycle WEn Strobe Duration Enable */
<> 128:9bcdf88f62b0 722 #define _EBI_WRTIMING2_HALFWE_SHIFT 28 /**< Shift value for EBI_HALFWE */
<> 128:9bcdf88f62b0 723 #define _EBI_WRTIMING2_HALFWE_MASK 0x10000000UL /**< Bit mask for EBI_HALFWE */
<> 128:9bcdf88f62b0 724 #define _EBI_WRTIMING2_HALFWE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING2 */
<> 128:9bcdf88f62b0 725 #define EBI_WRTIMING2_HALFWE_DEFAULT (_EBI_WRTIMING2_HALFWE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */
<> 128:9bcdf88f62b0 726 #define EBI_WRTIMING2_WBUFDIS (0x1UL << 29) /**< Write Buffer Disable */
<> 128:9bcdf88f62b0 727 #define _EBI_WRTIMING2_WBUFDIS_SHIFT 29 /**< Shift value for EBI_WBUFDIS */
<> 128:9bcdf88f62b0 728 #define _EBI_WRTIMING2_WBUFDIS_MASK 0x20000000UL /**< Bit mask for EBI_WBUFDIS */
<> 128:9bcdf88f62b0 729 #define _EBI_WRTIMING2_WBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING2 */
<> 128:9bcdf88f62b0 730 #define EBI_WRTIMING2_WBUFDIS_DEFAULT (_EBI_WRTIMING2_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */
<> 128:9bcdf88f62b0 731
<> 128:9bcdf88f62b0 732 /* Bit fields for EBI POLARITY2 */
<> 128:9bcdf88f62b0 733 #define _EBI_POLARITY2_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 734 #define _EBI_POLARITY2_MASK 0x0000003FUL /**< Mask for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 735 #define EBI_POLARITY2_CSPOL (0x1UL << 0) /**< Chip Select Polarity */
<> 128:9bcdf88f62b0 736 #define _EBI_POLARITY2_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */
<> 128:9bcdf88f62b0 737 #define _EBI_POLARITY2_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */
<> 128:9bcdf88f62b0 738 #define _EBI_POLARITY2_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 739 #define _EBI_POLARITY2_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 740 #define _EBI_POLARITY2_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 741 #define EBI_POLARITY2_CSPOL_DEFAULT (_EBI_POLARITY2_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 742 #define EBI_POLARITY2_CSPOL_ACTIVELOW (_EBI_POLARITY2_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 743 #define EBI_POLARITY2_CSPOL_ACTIVEHIGH (_EBI_POLARITY2_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 744 #define EBI_POLARITY2_REPOL (0x1UL << 1) /**< Read Enable Polarity */
<> 128:9bcdf88f62b0 745 #define _EBI_POLARITY2_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */
<> 128:9bcdf88f62b0 746 #define _EBI_POLARITY2_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */
<> 128:9bcdf88f62b0 747 #define _EBI_POLARITY2_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 748 #define _EBI_POLARITY2_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 749 #define _EBI_POLARITY2_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 750 #define EBI_POLARITY2_REPOL_DEFAULT (_EBI_POLARITY2_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 751 #define EBI_POLARITY2_REPOL_ACTIVELOW (_EBI_POLARITY2_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 752 #define EBI_POLARITY2_REPOL_ACTIVEHIGH (_EBI_POLARITY2_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 753 #define EBI_POLARITY2_WEPOL (0x1UL << 2) /**< Write Enable Polarity */
<> 128:9bcdf88f62b0 754 #define _EBI_POLARITY2_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */
<> 128:9bcdf88f62b0 755 #define _EBI_POLARITY2_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */
<> 128:9bcdf88f62b0 756 #define _EBI_POLARITY2_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 757 #define _EBI_POLARITY2_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 758 #define _EBI_POLARITY2_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 759 #define EBI_POLARITY2_WEPOL_DEFAULT (_EBI_POLARITY2_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 760 #define EBI_POLARITY2_WEPOL_ACTIVELOW (_EBI_POLARITY2_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 761 #define EBI_POLARITY2_WEPOL_ACTIVEHIGH (_EBI_POLARITY2_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 762 #define EBI_POLARITY2_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */
<> 128:9bcdf88f62b0 763 #define _EBI_POLARITY2_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */
<> 128:9bcdf88f62b0 764 #define _EBI_POLARITY2_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */
<> 128:9bcdf88f62b0 765 #define _EBI_POLARITY2_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 766 #define _EBI_POLARITY2_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 767 #define _EBI_POLARITY2_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 768 #define EBI_POLARITY2_ALEPOL_DEFAULT (_EBI_POLARITY2_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 769 #define EBI_POLARITY2_ALEPOL_ACTIVELOW (_EBI_POLARITY2_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 770 #define EBI_POLARITY2_ALEPOL_ACTIVEHIGH (_EBI_POLARITY2_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 771 #define EBI_POLARITY2_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */
<> 128:9bcdf88f62b0 772 #define _EBI_POLARITY2_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */
<> 128:9bcdf88f62b0 773 #define _EBI_POLARITY2_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */
<> 128:9bcdf88f62b0 774 #define _EBI_POLARITY2_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 775 #define _EBI_POLARITY2_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 776 #define _EBI_POLARITY2_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 777 #define EBI_POLARITY2_ARDYPOL_DEFAULT (_EBI_POLARITY2_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 778 #define EBI_POLARITY2_ARDYPOL_ACTIVELOW (_EBI_POLARITY2_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 779 #define EBI_POLARITY2_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY2_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 780 #define EBI_POLARITY2_BLPOL (0x1UL << 5) /**< BL Polarity */
<> 128:9bcdf88f62b0 781 #define _EBI_POLARITY2_BLPOL_SHIFT 5 /**< Shift value for EBI_BLPOL */
<> 128:9bcdf88f62b0 782 #define _EBI_POLARITY2_BLPOL_MASK 0x20UL /**< Bit mask for EBI_BLPOL */
<> 128:9bcdf88f62b0 783 #define _EBI_POLARITY2_BLPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 784 #define _EBI_POLARITY2_BLPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 785 #define _EBI_POLARITY2_BLPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 786 #define EBI_POLARITY2_BLPOL_DEFAULT (_EBI_POLARITY2_BLPOL_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 787 #define EBI_POLARITY2_BLPOL_ACTIVELOW (_EBI_POLARITY2_BLPOL_ACTIVELOW << 5) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 788 #define EBI_POLARITY2_BLPOL_ACTIVEHIGH (_EBI_POLARITY2_BLPOL_ACTIVEHIGH << 5) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */
<> 128:9bcdf88f62b0 789
<> 128:9bcdf88f62b0 790 /* Bit fields for EBI ADDRTIMING3 */
<> 128:9bcdf88f62b0 791 #define _EBI_ADDRTIMING3_RESETVALUE 0x00000303UL /**< Default value for EBI_ADDRTIMING3 */
<> 128:9bcdf88f62b0 792 #define _EBI_ADDRTIMING3_MASK 0x10000303UL /**< Mask for EBI_ADDRTIMING3 */
<> 128:9bcdf88f62b0 793 #define _EBI_ADDRTIMING3_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */
<> 128:9bcdf88f62b0 794 #define _EBI_ADDRTIMING3_ADDRSETUP_MASK 0x3UL /**< Bit mask for EBI_ADDRSETUP */
<> 128:9bcdf88f62b0 795 #define _EBI_ADDRTIMING3_ADDRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING3 */
<> 128:9bcdf88f62b0 796 #define EBI_ADDRTIMING3_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING3_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING3 */
<> 128:9bcdf88f62b0 797 #define _EBI_ADDRTIMING3_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */
<> 128:9bcdf88f62b0 798 #define _EBI_ADDRTIMING3_ADDRHOLD_MASK 0x300UL /**< Bit mask for EBI_ADDRHOLD */
<> 128:9bcdf88f62b0 799 #define _EBI_ADDRTIMING3_ADDRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_ADDRTIMING3 */
<> 128:9bcdf88f62b0 800 #define EBI_ADDRTIMING3_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING3_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING3 */
<> 128:9bcdf88f62b0 801 #define EBI_ADDRTIMING3_HALFALE (0x1UL << 28) /**< Half Cycle ALE Strobe Duration Enable */
<> 128:9bcdf88f62b0 802 #define _EBI_ADDRTIMING3_HALFALE_SHIFT 28 /**< Shift value for EBI_HALFALE */
<> 128:9bcdf88f62b0 803 #define _EBI_ADDRTIMING3_HALFALE_MASK 0x10000000UL /**< Bit mask for EBI_HALFALE */
<> 128:9bcdf88f62b0 804 #define _EBI_ADDRTIMING3_HALFALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING3 */
<> 128:9bcdf88f62b0 805 #define EBI_ADDRTIMING3_HALFALE_DEFAULT (_EBI_ADDRTIMING3_HALFALE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ADDRTIMING3 */
<> 128:9bcdf88f62b0 806
<> 128:9bcdf88f62b0 807 /* Bit fields for EBI RDTIMING3 */
<> 128:9bcdf88f62b0 808 #define _EBI_RDTIMING3_RESETVALUE 0x00033F03UL /**< Default value for EBI_RDTIMING3 */
<> 128:9bcdf88f62b0 809 #define _EBI_RDTIMING3_MASK 0x70033F03UL /**< Mask for EBI_RDTIMING3 */
<> 128:9bcdf88f62b0 810 #define _EBI_RDTIMING3_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */
<> 128:9bcdf88f62b0 811 #define _EBI_RDTIMING3_RDSETUP_MASK 0x3UL /**< Bit mask for EBI_RDSETUP */
<> 128:9bcdf88f62b0 812 #define _EBI_RDTIMING3_RDSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING3 */
<> 128:9bcdf88f62b0 813 #define EBI_RDTIMING3_RDSETUP_DEFAULT (_EBI_RDTIMING3_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */
<> 128:9bcdf88f62b0 814 #define _EBI_RDTIMING3_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */
<> 128:9bcdf88f62b0 815 #define _EBI_RDTIMING3_RDSTRB_MASK 0x3F00UL /**< Bit mask for EBI_RDSTRB */
<> 128:9bcdf88f62b0 816 #define _EBI_RDTIMING3_RDSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_RDTIMING3 */
<> 128:9bcdf88f62b0 817 #define EBI_RDTIMING3_RDSTRB_DEFAULT (_EBI_RDTIMING3_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */
<> 128:9bcdf88f62b0 818 #define _EBI_RDTIMING3_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */
<> 128:9bcdf88f62b0 819 #define _EBI_RDTIMING3_RDHOLD_MASK 0x30000UL /**< Bit mask for EBI_RDHOLD */
<> 128:9bcdf88f62b0 820 #define _EBI_RDTIMING3_RDHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_RDTIMING3 */
<> 128:9bcdf88f62b0 821 #define EBI_RDTIMING3_RDHOLD_DEFAULT (_EBI_RDTIMING3_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */
<> 128:9bcdf88f62b0 822 #define EBI_RDTIMING3_HALFRE (0x1UL << 28) /**< Half Cycle REn Strobe Duration Enable */
<> 128:9bcdf88f62b0 823 #define _EBI_RDTIMING3_HALFRE_SHIFT 28 /**< Shift value for EBI_HALFRE */
<> 128:9bcdf88f62b0 824 #define _EBI_RDTIMING3_HALFRE_MASK 0x10000000UL /**< Bit mask for EBI_HALFRE */
<> 128:9bcdf88f62b0 825 #define _EBI_RDTIMING3_HALFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING3 */
<> 128:9bcdf88f62b0 826 #define EBI_RDTIMING3_HALFRE_DEFAULT (_EBI_RDTIMING3_HALFRE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */
<> 128:9bcdf88f62b0 827 #define EBI_RDTIMING3_PREFETCH (0x1UL << 29) /**< Prefetch Enable */
<> 128:9bcdf88f62b0 828 #define _EBI_RDTIMING3_PREFETCH_SHIFT 29 /**< Shift value for EBI_PREFETCH */
<> 128:9bcdf88f62b0 829 #define _EBI_RDTIMING3_PREFETCH_MASK 0x20000000UL /**< Bit mask for EBI_PREFETCH */
<> 128:9bcdf88f62b0 830 #define _EBI_RDTIMING3_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING3 */
<> 128:9bcdf88f62b0 831 #define EBI_RDTIMING3_PREFETCH_DEFAULT (_EBI_RDTIMING3_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */
<> 128:9bcdf88f62b0 832 #define EBI_RDTIMING3_PAGEMODE (0x1UL << 30) /**< Page Mode Access Enable */
<> 128:9bcdf88f62b0 833 #define _EBI_RDTIMING3_PAGEMODE_SHIFT 30 /**< Shift value for EBI_PAGEMODE */
<> 128:9bcdf88f62b0 834 #define _EBI_RDTIMING3_PAGEMODE_MASK 0x40000000UL /**< Bit mask for EBI_PAGEMODE */
<> 128:9bcdf88f62b0 835 #define _EBI_RDTIMING3_PAGEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING3 */
<> 128:9bcdf88f62b0 836 #define EBI_RDTIMING3_PAGEMODE_DEFAULT (_EBI_RDTIMING3_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */
<> 128:9bcdf88f62b0 837
<> 128:9bcdf88f62b0 838 /* Bit fields for EBI WRTIMING3 */
<> 128:9bcdf88f62b0 839 #define _EBI_WRTIMING3_RESETVALUE 0x00033F03UL /**< Default value for EBI_WRTIMING3 */
<> 128:9bcdf88f62b0 840 #define _EBI_WRTIMING3_MASK 0x30033F03UL /**< Mask for EBI_WRTIMING3 */
<> 128:9bcdf88f62b0 841 #define _EBI_WRTIMING3_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */
<> 128:9bcdf88f62b0 842 #define _EBI_WRTIMING3_WRSETUP_MASK 0x3UL /**< Bit mask for EBI_WRSETUP */
<> 128:9bcdf88f62b0 843 #define _EBI_WRTIMING3_WRSETUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING3 */
<> 128:9bcdf88f62b0 844 #define EBI_WRTIMING3_WRSETUP_DEFAULT (_EBI_WRTIMING3_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */
<> 128:9bcdf88f62b0 845 #define _EBI_WRTIMING3_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */
<> 128:9bcdf88f62b0 846 #define _EBI_WRTIMING3_WRSTRB_MASK 0x3F00UL /**< Bit mask for EBI_WRSTRB */
<> 128:9bcdf88f62b0 847 #define _EBI_WRTIMING3_WRSTRB_DEFAULT 0x0000003FUL /**< Mode DEFAULT for EBI_WRTIMING3 */
<> 128:9bcdf88f62b0 848 #define EBI_WRTIMING3_WRSTRB_DEFAULT (_EBI_WRTIMING3_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */
<> 128:9bcdf88f62b0 849 #define _EBI_WRTIMING3_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */
<> 128:9bcdf88f62b0 850 #define _EBI_WRTIMING3_WRHOLD_MASK 0x30000UL /**< Bit mask for EBI_WRHOLD */
<> 128:9bcdf88f62b0 851 #define _EBI_WRTIMING3_WRHOLD_DEFAULT 0x00000003UL /**< Mode DEFAULT for EBI_WRTIMING3 */
<> 128:9bcdf88f62b0 852 #define EBI_WRTIMING3_WRHOLD_DEFAULT (_EBI_WRTIMING3_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */
<> 128:9bcdf88f62b0 853 #define EBI_WRTIMING3_HALFWE (0x1UL << 28) /**< Half Cycle WEn Strobe Duration Enable */
<> 128:9bcdf88f62b0 854 #define _EBI_WRTIMING3_HALFWE_SHIFT 28 /**< Shift value for EBI_HALFWE */
<> 128:9bcdf88f62b0 855 #define _EBI_WRTIMING3_HALFWE_MASK 0x10000000UL /**< Bit mask for EBI_HALFWE */
<> 128:9bcdf88f62b0 856 #define _EBI_WRTIMING3_HALFWE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING3 */
<> 128:9bcdf88f62b0 857 #define EBI_WRTIMING3_HALFWE_DEFAULT (_EBI_WRTIMING3_HALFWE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */
<> 128:9bcdf88f62b0 858 #define EBI_WRTIMING3_WBUFDIS (0x1UL << 29) /**< Write Buffer Disable */
<> 128:9bcdf88f62b0 859 #define _EBI_WRTIMING3_WBUFDIS_SHIFT 29 /**< Shift value for EBI_WBUFDIS */
<> 128:9bcdf88f62b0 860 #define _EBI_WRTIMING3_WBUFDIS_MASK 0x20000000UL /**< Bit mask for EBI_WBUFDIS */
<> 128:9bcdf88f62b0 861 #define _EBI_WRTIMING3_WBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING3 */
<> 128:9bcdf88f62b0 862 #define EBI_WRTIMING3_WBUFDIS_DEFAULT (_EBI_WRTIMING3_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */
<> 128:9bcdf88f62b0 863
<> 128:9bcdf88f62b0 864 /* Bit fields for EBI POLARITY3 */
<> 128:9bcdf88f62b0 865 #define _EBI_POLARITY3_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 866 #define _EBI_POLARITY3_MASK 0x0000003FUL /**< Mask for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 867 #define EBI_POLARITY3_CSPOL (0x1UL << 0) /**< Chip Select Polarity */
<> 128:9bcdf88f62b0 868 #define _EBI_POLARITY3_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */
<> 128:9bcdf88f62b0 869 #define _EBI_POLARITY3_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */
<> 128:9bcdf88f62b0 870 #define _EBI_POLARITY3_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 871 #define _EBI_POLARITY3_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 872 #define _EBI_POLARITY3_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 873 #define EBI_POLARITY3_CSPOL_DEFAULT (_EBI_POLARITY3_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 874 #define EBI_POLARITY3_CSPOL_ACTIVELOW (_EBI_POLARITY3_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 875 #define EBI_POLARITY3_CSPOL_ACTIVEHIGH (_EBI_POLARITY3_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 876 #define EBI_POLARITY3_REPOL (0x1UL << 1) /**< Read Enable Polarity */
<> 128:9bcdf88f62b0 877 #define _EBI_POLARITY3_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */
<> 128:9bcdf88f62b0 878 #define _EBI_POLARITY3_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */
<> 128:9bcdf88f62b0 879 #define _EBI_POLARITY3_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 880 #define _EBI_POLARITY3_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 881 #define _EBI_POLARITY3_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 882 #define EBI_POLARITY3_REPOL_DEFAULT (_EBI_POLARITY3_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 883 #define EBI_POLARITY3_REPOL_ACTIVELOW (_EBI_POLARITY3_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 884 #define EBI_POLARITY3_REPOL_ACTIVEHIGH (_EBI_POLARITY3_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 885 #define EBI_POLARITY3_WEPOL (0x1UL << 2) /**< Write Enable Polarity */
<> 128:9bcdf88f62b0 886 #define _EBI_POLARITY3_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */
<> 128:9bcdf88f62b0 887 #define _EBI_POLARITY3_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */
<> 128:9bcdf88f62b0 888 #define _EBI_POLARITY3_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 889 #define _EBI_POLARITY3_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 890 #define _EBI_POLARITY3_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 891 #define EBI_POLARITY3_WEPOL_DEFAULT (_EBI_POLARITY3_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 892 #define EBI_POLARITY3_WEPOL_ACTIVELOW (_EBI_POLARITY3_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 893 #define EBI_POLARITY3_WEPOL_ACTIVEHIGH (_EBI_POLARITY3_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 894 #define EBI_POLARITY3_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */
<> 128:9bcdf88f62b0 895 #define _EBI_POLARITY3_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */
<> 128:9bcdf88f62b0 896 #define _EBI_POLARITY3_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */
<> 128:9bcdf88f62b0 897 #define _EBI_POLARITY3_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 898 #define _EBI_POLARITY3_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 899 #define _EBI_POLARITY3_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 900 #define EBI_POLARITY3_ALEPOL_DEFAULT (_EBI_POLARITY3_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 901 #define EBI_POLARITY3_ALEPOL_ACTIVELOW (_EBI_POLARITY3_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 902 #define EBI_POLARITY3_ALEPOL_ACTIVEHIGH (_EBI_POLARITY3_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 903 #define EBI_POLARITY3_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */
<> 128:9bcdf88f62b0 904 #define _EBI_POLARITY3_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */
<> 128:9bcdf88f62b0 905 #define _EBI_POLARITY3_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */
<> 128:9bcdf88f62b0 906 #define _EBI_POLARITY3_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 907 #define _EBI_POLARITY3_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 908 #define _EBI_POLARITY3_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 909 #define EBI_POLARITY3_ARDYPOL_DEFAULT (_EBI_POLARITY3_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 910 #define EBI_POLARITY3_ARDYPOL_ACTIVELOW (_EBI_POLARITY3_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 911 #define EBI_POLARITY3_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY3_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 912 #define EBI_POLARITY3_BLPOL (0x1UL << 5) /**< BL Polarity */
<> 128:9bcdf88f62b0 913 #define _EBI_POLARITY3_BLPOL_SHIFT 5 /**< Shift value for EBI_BLPOL */
<> 128:9bcdf88f62b0 914 #define _EBI_POLARITY3_BLPOL_MASK 0x20UL /**< Bit mask for EBI_BLPOL */
<> 128:9bcdf88f62b0 915 #define _EBI_POLARITY3_BLPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 916 #define _EBI_POLARITY3_BLPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 917 #define _EBI_POLARITY3_BLPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 918 #define EBI_POLARITY3_BLPOL_DEFAULT (_EBI_POLARITY3_BLPOL_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 919 #define EBI_POLARITY3_BLPOL_ACTIVELOW (_EBI_POLARITY3_BLPOL_ACTIVELOW << 5) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 920 #define EBI_POLARITY3_BLPOL_ACTIVEHIGH (_EBI_POLARITY3_BLPOL_ACTIVEHIGH << 5) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */
<> 128:9bcdf88f62b0 921
<> 128:9bcdf88f62b0 922 /* Bit fields for EBI PAGECTRL */
<> 128:9bcdf88f62b0 923 #define _EBI_PAGECTRL_RESETVALUE 0x00000700UL /**< Default value for EBI_PAGECTRL */
<> 128:9bcdf88f62b0 924 #define _EBI_PAGECTRL_MASK 0x07F00713UL /**< Mask for EBI_PAGECTRL */
<> 128:9bcdf88f62b0 925 #define _EBI_PAGECTRL_PAGELEN_SHIFT 0 /**< Shift value for EBI_PAGELEN */
<> 128:9bcdf88f62b0 926 #define _EBI_PAGECTRL_PAGELEN_MASK 0x3UL /**< Bit mask for EBI_PAGELEN */
<> 128:9bcdf88f62b0 927 #define _EBI_PAGECTRL_PAGELEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_PAGECTRL */
<> 128:9bcdf88f62b0 928 #define _EBI_PAGECTRL_PAGELEN_MEMBER4 0x00000000UL /**< Mode MEMBER4 for EBI_PAGECTRL */
<> 128:9bcdf88f62b0 929 #define _EBI_PAGECTRL_PAGELEN_MEMBER8 0x00000001UL /**< Mode MEMBER8 for EBI_PAGECTRL */
<> 128:9bcdf88f62b0 930 #define _EBI_PAGECTRL_PAGELEN_MEMBER16 0x00000002UL /**< Mode MEMBER16 for EBI_PAGECTRL */
<> 128:9bcdf88f62b0 931 #define _EBI_PAGECTRL_PAGELEN_MEMBER32 0x00000003UL /**< Mode MEMBER32 for EBI_PAGECTRL */
<> 128:9bcdf88f62b0 932 #define EBI_PAGECTRL_PAGELEN_DEFAULT (_EBI_PAGECTRL_PAGELEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_PAGECTRL */
<> 128:9bcdf88f62b0 933 #define EBI_PAGECTRL_PAGELEN_MEMBER4 (_EBI_PAGECTRL_PAGELEN_MEMBER4 << 0) /**< Shifted mode MEMBER4 for EBI_PAGECTRL */
<> 128:9bcdf88f62b0 934 #define EBI_PAGECTRL_PAGELEN_MEMBER8 (_EBI_PAGECTRL_PAGELEN_MEMBER8 << 0) /**< Shifted mode MEMBER8 for EBI_PAGECTRL */
<> 128:9bcdf88f62b0 935 #define EBI_PAGECTRL_PAGELEN_MEMBER16 (_EBI_PAGECTRL_PAGELEN_MEMBER16 << 0) /**< Shifted mode MEMBER16 for EBI_PAGECTRL */
<> 128:9bcdf88f62b0 936 #define EBI_PAGECTRL_PAGELEN_MEMBER32 (_EBI_PAGECTRL_PAGELEN_MEMBER32 << 0) /**< Shifted mode MEMBER32 for EBI_PAGECTRL */
<> 128:9bcdf88f62b0 937 #define EBI_PAGECTRL_INCHIT (0x1UL << 4) /**< Intrapage hit only on incremental addresses */
<> 128:9bcdf88f62b0 938 #define _EBI_PAGECTRL_INCHIT_SHIFT 4 /**< Shift value for EBI_INCHIT */
<> 128:9bcdf88f62b0 939 #define _EBI_PAGECTRL_INCHIT_MASK 0x10UL /**< Bit mask for EBI_INCHIT */
<> 128:9bcdf88f62b0 940 #define _EBI_PAGECTRL_INCHIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_PAGECTRL */
<> 128:9bcdf88f62b0 941 #define EBI_PAGECTRL_INCHIT_DEFAULT (_EBI_PAGECTRL_INCHIT_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_PAGECTRL */
<> 128:9bcdf88f62b0 942 #define _EBI_PAGECTRL_RDPA_SHIFT 8 /**< Shift value for EBI_RDPA */
<> 128:9bcdf88f62b0 943 #define _EBI_PAGECTRL_RDPA_MASK 0x700UL /**< Bit mask for EBI_RDPA */
<> 128:9bcdf88f62b0 944 #define _EBI_PAGECTRL_RDPA_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_PAGECTRL */
<> 128:9bcdf88f62b0 945 #define EBI_PAGECTRL_RDPA_DEFAULT (_EBI_PAGECTRL_RDPA_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_PAGECTRL */
<> 128:9bcdf88f62b0 946 #define _EBI_PAGECTRL_KEEPOPEN_SHIFT 20 /**< Shift value for EBI_KEEPOPEN */
<> 128:9bcdf88f62b0 947 #define _EBI_PAGECTRL_KEEPOPEN_MASK 0x7F00000UL /**< Bit mask for EBI_KEEPOPEN */
<> 128:9bcdf88f62b0 948 #define _EBI_PAGECTRL_KEEPOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_PAGECTRL */
<> 128:9bcdf88f62b0 949 #define EBI_PAGECTRL_KEEPOPEN_DEFAULT (_EBI_PAGECTRL_KEEPOPEN_DEFAULT << 20) /**< Shifted mode DEFAULT for EBI_PAGECTRL */
<> 128:9bcdf88f62b0 950
<> 128:9bcdf88f62b0 951 /* Bit fields for EBI NANDCTRL */
<> 128:9bcdf88f62b0 952 #define _EBI_NANDCTRL_RESETVALUE 0x00000000UL /**< Default value for EBI_NANDCTRL */
<> 128:9bcdf88f62b0 953 #define _EBI_NANDCTRL_MASK 0x00000031UL /**< Mask for EBI_NANDCTRL */
<> 128:9bcdf88f62b0 954 #define EBI_NANDCTRL_EN (0x1UL << 0) /**< NAND Flash control enable */
<> 128:9bcdf88f62b0 955 #define _EBI_NANDCTRL_EN_SHIFT 0 /**< Shift value for EBI_EN */
<> 128:9bcdf88f62b0 956 #define _EBI_NANDCTRL_EN_MASK 0x1UL /**< Bit mask for EBI_EN */
<> 128:9bcdf88f62b0 957 #define _EBI_NANDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_NANDCTRL */
<> 128:9bcdf88f62b0 958 #define EBI_NANDCTRL_EN_DEFAULT (_EBI_NANDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_NANDCTRL */
<> 128:9bcdf88f62b0 959 #define _EBI_NANDCTRL_BANKSEL_SHIFT 4 /**< Shift value for EBI_BANKSEL */
<> 128:9bcdf88f62b0 960 #define _EBI_NANDCTRL_BANKSEL_MASK 0x30UL /**< Bit mask for EBI_BANKSEL */
<> 128:9bcdf88f62b0 961 #define _EBI_NANDCTRL_BANKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_NANDCTRL */
<> 128:9bcdf88f62b0 962 #define _EBI_NANDCTRL_BANKSEL_BANK0 0x00000000UL /**< Mode BANK0 for EBI_NANDCTRL */
<> 128:9bcdf88f62b0 963 #define _EBI_NANDCTRL_BANKSEL_BANK1 0x00000001UL /**< Mode BANK1 for EBI_NANDCTRL */
<> 128:9bcdf88f62b0 964 #define _EBI_NANDCTRL_BANKSEL_BANK2 0x00000002UL /**< Mode BANK2 for EBI_NANDCTRL */
<> 128:9bcdf88f62b0 965 #define _EBI_NANDCTRL_BANKSEL_BANK3 0x00000003UL /**< Mode BANK3 for EBI_NANDCTRL */
<> 128:9bcdf88f62b0 966 #define EBI_NANDCTRL_BANKSEL_DEFAULT (_EBI_NANDCTRL_BANKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_NANDCTRL */
<> 128:9bcdf88f62b0 967 #define EBI_NANDCTRL_BANKSEL_BANK0 (_EBI_NANDCTRL_BANKSEL_BANK0 << 4) /**< Shifted mode BANK0 for EBI_NANDCTRL */
<> 128:9bcdf88f62b0 968 #define EBI_NANDCTRL_BANKSEL_BANK1 (_EBI_NANDCTRL_BANKSEL_BANK1 << 4) /**< Shifted mode BANK1 for EBI_NANDCTRL */
<> 128:9bcdf88f62b0 969 #define EBI_NANDCTRL_BANKSEL_BANK2 (_EBI_NANDCTRL_BANKSEL_BANK2 << 4) /**< Shifted mode BANK2 for EBI_NANDCTRL */
<> 128:9bcdf88f62b0 970 #define EBI_NANDCTRL_BANKSEL_BANK3 (_EBI_NANDCTRL_BANKSEL_BANK3 << 4) /**< Shifted mode BANK3 for EBI_NANDCTRL */
<> 128:9bcdf88f62b0 971
<> 128:9bcdf88f62b0 972 /* Bit fields for EBI CMD */
<> 128:9bcdf88f62b0 973 #define _EBI_CMD_RESETVALUE 0x00000000UL /**< Default value for EBI_CMD */
<> 128:9bcdf88f62b0 974 #define _EBI_CMD_MASK 0x00000007UL /**< Mask for EBI_CMD */
<> 128:9bcdf88f62b0 975 #define EBI_CMD_ECCSTART (0x1UL << 0) /**< Error Correction Code Generation Start */
<> 128:9bcdf88f62b0 976 #define _EBI_CMD_ECCSTART_SHIFT 0 /**< Shift value for EBI_ECCSTART */
<> 128:9bcdf88f62b0 977 #define _EBI_CMD_ECCSTART_MASK 0x1UL /**< Bit mask for EBI_ECCSTART */
<> 128:9bcdf88f62b0 978 #define _EBI_CMD_ECCSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CMD */
<> 128:9bcdf88f62b0 979 #define EBI_CMD_ECCSTART_DEFAULT (_EBI_CMD_ECCSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_CMD */
<> 128:9bcdf88f62b0 980 #define EBI_CMD_ECCSTOP (0x1UL << 1) /**< Error Correction Code Generation Stop */
<> 128:9bcdf88f62b0 981 #define _EBI_CMD_ECCSTOP_SHIFT 1 /**< Shift value for EBI_ECCSTOP */
<> 128:9bcdf88f62b0 982 #define _EBI_CMD_ECCSTOP_MASK 0x2UL /**< Bit mask for EBI_ECCSTOP */
<> 128:9bcdf88f62b0 983 #define _EBI_CMD_ECCSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CMD */
<> 128:9bcdf88f62b0 984 #define EBI_CMD_ECCSTOP_DEFAULT (_EBI_CMD_ECCSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_CMD */
<> 128:9bcdf88f62b0 985 #define EBI_CMD_ECCCLEAR (0x1UL << 2) /**< Error Correction Code Clear */
<> 128:9bcdf88f62b0 986 #define _EBI_CMD_ECCCLEAR_SHIFT 2 /**< Shift value for EBI_ECCCLEAR */
<> 128:9bcdf88f62b0 987 #define _EBI_CMD_ECCCLEAR_MASK 0x4UL /**< Bit mask for EBI_ECCCLEAR */
<> 128:9bcdf88f62b0 988 #define _EBI_CMD_ECCCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CMD */
<> 128:9bcdf88f62b0 989 #define EBI_CMD_ECCCLEAR_DEFAULT (_EBI_CMD_ECCCLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_CMD */
<> 128:9bcdf88f62b0 990
<> 128:9bcdf88f62b0 991 /* Bit fields for EBI STATUS */
<> 128:9bcdf88f62b0 992 #define _EBI_STATUS_RESETVALUE 0x00000000UL /**< Default value for EBI_STATUS */
<> 128:9bcdf88f62b0 993 #define _EBI_STATUS_MASK 0x00003711UL /**< Mask for EBI_STATUS */
<> 128:9bcdf88f62b0 994 #define EBI_STATUS_AHBACT (0x1UL << 0) /**< EBI Busy with AHB Transaction. */
<> 128:9bcdf88f62b0 995 #define _EBI_STATUS_AHBACT_SHIFT 0 /**< Shift value for EBI_AHBACT */
<> 128:9bcdf88f62b0 996 #define _EBI_STATUS_AHBACT_MASK 0x1UL /**< Bit mask for EBI_AHBACT */
<> 128:9bcdf88f62b0 997 #define _EBI_STATUS_AHBACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */
<> 128:9bcdf88f62b0 998 #define EBI_STATUS_AHBACT_DEFAULT (_EBI_STATUS_AHBACT_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_STATUS */
<> 128:9bcdf88f62b0 999 #define EBI_STATUS_ECCACT (0x1UL << 4) /**< EBI ECC Generation Active. */
<> 128:9bcdf88f62b0 1000 #define _EBI_STATUS_ECCACT_SHIFT 4 /**< Shift value for EBI_ECCACT */
<> 128:9bcdf88f62b0 1001 #define _EBI_STATUS_ECCACT_MASK 0x10UL /**< Bit mask for EBI_ECCACT */
<> 128:9bcdf88f62b0 1002 #define _EBI_STATUS_ECCACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */
<> 128:9bcdf88f62b0 1003 #define EBI_STATUS_ECCACT_DEFAULT (_EBI_STATUS_ECCACT_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_STATUS */
<> 128:9bcdf88f62b0 1004 #define EBI_STATUS_TFTPIXEL0EMPTY (0x1UL << 8) /**< EBI_TFTPIXEL0 is empty. */
<> 128:9bcdf88f62b0 1005 #define _EBI_STATUS_TFTPIXEL0EMPTY_SHIFT 8 /**< Shift value for EBI_TFTPIXEL0EMPTY */
<> 128:9bcdf88f62b0 1006 #define _EBI_STATUS_TFTPIXEL0EMPTY_MASK 0x100UL /**< Bit mask for EBI_TFTPIXEL0EMPTY */
<> 128:9bcdf88f62b0 1007 #define _EBI_STATUS_TFTPIXEL0EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */
<> 128:9bcdf88f62b0 1008 #define EBI_STATUS_TFTPIXEL0EMPTY_DEFAULT (_EBI_STATUS_TFTPIXEL0EMPTY_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_STATUS */
<> 128:9bcdf88f62b0 1009 #define EBI_STATUS_TFTPIXEL1EMPTY (0x1UL << 9) /**< EBI_TFTPIXEL1 is empty. */
<> 128:9bcdf88f62b0 1010 #define _EBI_STATUS_TFTPIXEL1EMPTY_SHIFT 9 /**< Shift value for EBI_TFTPIXEL1EMPTY */
<> 128:9bcdf88f62b0 1011 #define _EBI_STATUS_TFTPIXEL1EMPTY_MASK 0x200UL /**< Bit mask for EBI_TFTPIXEL1EMPTY */
<> 128:9bcdf88f62b0 1012 #define _EBI_STATUS_TFTPIXEL1EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */
<> 128:9bcdf88f62b0 1013 #define EBI_STATUS_TFTPIXEL1EMPTY_DEFAULT (_EBI_STATUS_TFTPIXEL1EMPTY_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_STATUS */
<> 128:9bcdf88f62b0 1014 #define EBI_STATUS_TFTPIXELFULL (0x1UL << 10) /**< EBI_TFTPIXEL0 is full. */
<> 128:9bcdf88f62b0 1015 #define _EBI_STATUS_TFTPIXELFULL_SHIFT 10 /**< Shift value for EBI_TFTPIXELFULL */
<> 128:9bcdf88f62b0 1016 #define _EBI_STATUS_TFTPIXELFULL_MASK 0x400UL /**< Bit mask for EBI_TFTPIXELFULL */
<> 128:9bcdf88f62b0 1017 #define _EBI_STATUS_TFTPIXELFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */
<> 128:9bcdf88f62b0 1018 #define EBI_STATUS_TFTPIXELFULL_DEFAULT (_EBI_STATUS_TFTPIXELFULL_DEFAULT << 10) /**< Shifted mode DEFAULT for EBI_STATUS */
<> 128:9bcdf88f62b0 1019 #define EBI_STATUS_DDACT (0x1UL << 12) /**< EBI Busy with Direct Drive Transactions. */
<> 128:9bcdf88f62b0 1020 #define _EBI_STATUS_DDACT_SHIFT 12 /**< Shift value for EBI_DDACT */
<> 128:9bcdf88f62b0 1021 #define _EBI_STATUS_DDACT_MASK 0x1000UL /**< Bit mask for EBI_DDACT */
<> 128:9bcdf88f62b0 1022 #define _EBI_STATUS_DDACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */
<> 128:9bcdf88f62b0 1023 #define EBI_STATUS_DDACT_DEFAULT (_EBI_STATUS_DDACT_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_STATUS */
<> 128:9bcdf88f62b0 1024 #define EBI_STATUS_TFTDDEMPTY (0x1UL << 13) /**< EBI_TFTDD register is empty. */
<> 128:9bcdf88f62b0 1025 #define _EBI_STATUS_TFTDDEMPTY_SHIFT 13 /**< Shift value for EBI_TFTDDEMPTY */
<> 128:9bcdf88f62b0 1026 #define _EBI_STATUS_TFTDDEMPTY_MASK 0x2000UL /**< Bit mask for EBI_TFTDDEMPTY */
<> 128:9bcdf88f62b0 1027 #define _EBI_STATUS_TFTDDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */
<> 128:9bcdf88f62b0 1028 #define EBI_STATUS_TFTDDEMPTY_DEFAULT (_EBI_STATUS_TFTDDEMPTY_DEFAULT << 13) /**< Shifted mode DEFAULT for EBI_STATUS */
<> 128:9bcdf88f62b0 1029
<> 128:9bcdf88f62b0 1030 /* Bit fields for EBI ECCPARITY */
<> 128:9bcdf88f62b0 1031 #define _EBI_ECCPARITY_RESETVALUE 0x00000000UL /**< Default value for EBI_ECCPARITY */
<> 128:9bcdf88f62b0 1032 #define _EBI_ECCPARITY_MASK 0xFFFFFFFFUL /**< Mask for EBI_ECCPARITY */
<> 128:9bcdf88f62b0 1033 #define _EBI_ECCPARITY_ECCPARITY_SHIFT 0 /**< Shift value for EBI_ECCPARITY */
<> 128:9bcdf88f62b0 1034 #define _EBI_ECCPARITY_ECCPARITY_MASK 0xFFFFFFFFUL /**< Bit mask for EBI_ECCPARITY */
<> 128:9bcdf88f62b0 1035 #define _EBI_ECCPARITY_ECCPARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ECCPARITY */
<> 128:9bcdf88f62b0 1036 #define EBI_ECCPARITY_ECCPARITY_DEFAULT (_EBI_ECCPARITY_ECCPARITY_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ECCPARITY */
<> 128:9bcdf88f62b0 1037
<> 128:9bcdf88f62b0 1038 /* Bit fields for EBI TFTCTRL */
<> 128:9bcdf88f62b0 1039 #define _EBI_TFTCTRL_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1040 #define _EBI_TFTCTRL_MASK 0x01311F1FUL /**< Mask for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1041 #define _EBI_TFTCTRL_DD_SHIFT 0 /**< Shift value for EBI_DD */
<> 128:9bcdf88f62b0 1042 #define _EBI_TFTCTRL_DD_MASK 0x3UL /**< Bit mask for EBI_DD */
<> 128:9bcdf88f62b0 1043 #define _EBI_TFTCTRL_DD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1044 #define _EBI_TFTCTRL_DD_DISABLED 0x00000000UL /**< Mode DISABLED for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1045 #define _EBI_TFTCTRL_DD_INTERNAL 0x00000001UL /**< Mode INTERNAL for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1046 #define _EBI_TFTCTRL_DD_EXTERNAL 0x00000002UL /**< Mode EXTERNAL for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1047 #define EBI_TFTCTRL_DD_DEFAULT (_EBI_TFTCTRL_DD_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1048 #define EBI_TFTCTRL_DD_DISABLED (_EBI_TFTCTRL_DD_DISABLED << 0) /**< Shifted mode DISABLED for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1049 #define EBI_TFTCTRL_DD_INTERNAL (_EBI_TFTCTRL_DD_INTERNAL << 0) /**< Shifted mode INTERNAL for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1050 #define EBI_TFTCTRL_DD_EXTERNAL (_EBI_TFTCTRL_DD_EXTERNAL << 0) /**< Shifted mode EXTERNAL for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1051 #define _EBI_TFTCTRL_MASKBLEND_SHIFT 2 /**< Shift value for EBI_MASKBLEND */
<> 128:9bcdf88f62b0 1052 #define _EBI_TFTCTRL_MASKBLEND_MASK 0x1CUL /**< Bit mask for EBI_MASKBLEND */
<> 128:9bcdf88f62b0 1053 #define _EBI_TFTCTRL_MASKBLEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1054 #define _EBI_TFTCTRL_MASKBLEND_DISABLED 0x00000000UL /**< Mode DISABLED for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1055 #define _EBI_TFTCTRL_MASKBLEND_IMASK 0x00000001UL /**< Mode IMASK for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1056 #define _EBI_TFTCTRL_MASKBLEND_IALPHA 0x00000002UL /**< Mode IALPHA for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1057 #define _EBI_TFTCTRL_MASKBLEND_IMASKIALPHA 0x00000003UL /**< Mode IMASKIALPHA for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1058 #define _EBI_TFTCTRL_MASKBLEND_EMASK 0x00000005UL /**< Mode EMASK for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1059 #define _EBI_TFTCTRL_MASKBLEND_EALPHA 0x00000006UL /**< Mode EALPHA for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1060 #define _EBI_TFTCTRL_MASKBLEND_EMASKEALPHA 0x00000007UL /**< Mode EMASKEALPHA for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1061 #define EBI_TFTCTRL_MASKBLEND_DEFAULT (_EBI_TFTCTRL_MASKBLEND_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1062 #define EBI_TFTCTRL_MASKBLEND_DISABLED (_EBI_TFTCTRL_MASKBLEND_DISABLED << 2) /**< Shifted mode DISABLED for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1063 #define EBI_TFTCTRL_MASKBLEND_IMASK (_EBI_TFTCTRL_MASKBLEND_IMASK << 2) /**< Shifted mode IMASK for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1064 #define EBI_TFTCTRL_MASKBLEND_IALPHA (_EBI_TFTCTRL_MASKBLEND_IALPHA << 2) /**< Shifted mode IALPHA for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1065 #define EBI_TFTCTRL_MASKBLEND_IMASKIALPHA (_EBI_TFTCTRL_MASKBLEND_IMASKIALPHA << 2) /**< Shifted mode IMASKIALPHA for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1066 #define EBI_TFTCTRL_MASKBLEND_EMASK (_EBI_TFTCTRL_MASKBLEND_EMASK << 2) /**< Shifted mode EMASK for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1067 #define EBI_TFTCTRL_MASKBLEND_EALPHA (_EBI_TFTCTRL_MASKBLEND_EALPHA << 2) /**< Shifted mode EALPHA for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1068 #define EBI_TFTCTRL_MASKBLEND_EMASKEALPHA (_EBI_TFTCTRL_MASKBLEND_EMASKEALPHA << 2) /**< Shifted mode EMASKEALPHA for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1069 #define EBI_TFTCTRL_SHIFTDCLKEN (0x1UL << 8) /**< TFT EBI_DCLK Shift Enable */
<> 128:9bcdf88f62b0 1070 #define _EBI_TFTCTRL_SHIFTDCLKEN_SHIFT 8 /**< Shift value for EBI_SHIFTDCLKEN */
<> 128:9bcdf88f62b0 1071 #define _EBI_TFTCTRL_SHIFTDCLKEN_MASK 0x100UL /**< Bit mask for EBI_SHIFTDCLKEN */
<> 128:9bcdf88f62b0 1072 #define _EBI_TFTCTRL_SHIFTDCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1073 #define EBI_TFTCTRL_SHIFTDCLKEN_DEFAULT (_EBI_TFTCTRL_SHIFTDCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1074 #define EBI_TFTCTRL_FBCTRIG (0x1UL << 9) /**< TFT Frame Base Copy Trigger */
<> 128:9bcdf88f62b0 1075 #define _EBI_TFTCTRL_FBCTRIG_SHIFT 9 /**< Shift value for EBI_FBCTRIG */
<> 128:9bcdf88f62b0 1076 #define _EBI_TFTCTRL_FBCTRIG_MASK 0x200UL /**< Bit mask for EBI_FBCTRIG */
<> 128:9bcdf88f62b0 1077 #define _EBI_TFTCTRL_FBCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1078 #define _EBI_TFTCTRL_FBCTRIG_VSYNC 0x00000000UL /**< Mode VSYNC for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1079 #define _EBI_TFTCTRL_FBCTRIG_HSYNC 0x00000001UL /**< Mode HSYNC for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1080 #define EBI_TFTCTRL_FBCTRIG_DEFAULT (_EBI_TFTCTRL_FBCTRIG_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1081 #define EBI_TFTCTRL_FBCTRIG_VSYNC (_EBI_TFTCTRL_FBCTRIG_VSYNC << 9) /**< Shifted mode VSYNC for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1082 #define EBI_TFTCTRL_FBCTRIG_HSYNC (_EBI_TFTCTRL_FBCTRIG_HSYNC << 9) /**< Shifted mode HSYNC for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1083 #define _EBI_TFTCTRL_INTERLEAVE_SHIFT 10 /**< Shift value for EBI_INTERLEAVE */
<> 128:9bcdf88f62b0 1084 #define _EBI_TFTCTRL_INTERLEAVE_MASK 0xC00UL /**< Bit mask for EBI_INTERLEAVE */
<> 128:9bcdf88f62b0 1085 #define _EBI_TFTCTRL_INTERLEAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1086 #define _EBI_TFTCTRL_INTERLEAVE_UNLIMITED 0x00000000UL /**< Mode UNLIMITED for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1087 #define _EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK 0x00000001UL /**< Mode ONEPERDCLK for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1088 #define _EBI_TFTCTRL_INTERLEAVE_PORCH 0x00000002UL /**< Mode PORCH for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1089 #define EBI_TFTCTRL_INTERLEAVE_DEFAULT (_EBI_TFTCTRL_INTERLEAVE_DEFAULT << 10) /**< Shifted mode DEFAULT for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1090 #define EBI_TFTCTRL_INTERLEAVE_UNLIMITED (_EBI_TFTCTRL_INTERLEAVE_UNLIMITED << 10) /**< Shifted mode UNLIMITED for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1091 #define EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK (_EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK << 10) /**< Shifted mode ONEPERDCLK for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1092 #define EBI_TFTCTRL_INTERLEAVE_PORCH (_EBI_TFTCTRL_INTERLEAVE_PORCH << 10) /**< Shifted mode PORCH for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1093 #define EBI_TFTCTRL_COLOR1SRC (0x1UL << 12) /**< Masking/Alpha Blending Color1 Source */
<> 128:9bcdf88f62b0 1094 #define _EBI_TFTCTRL_COLOR1SRC_SHIFT 12 /**< Shift value for EBI_COLOR1SRC */
<> 128:9bcdf88f62b0 1095 #define _EBI_TFTCTRL_COLOR1SRC_MASK 0x1000UL /**< Bit mask for EBI_COLOR1SRC */
<> 128:9bcdf88f62b0 1096 #define _EBI_TFTCTRL_COLOR1SRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1097 #define _EBI_TFTCTRL_COLOR1SRC_MEM 0x00000000UL /**< Mode MEM for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1098 #define _EBI_TFTCTRL_COLOR1SRC_PIXEL1 0x00000001UL /**< Mode PIXEL1 for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1099 #define EBI_TFTCTRL_COLOR1SRC_DEFAULT (_EBI_TFTCTRL_COLOR1SRC_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1100 #define EBI_TFTCTRL_COLOR1SRC_MEM (_EBI_TFTCTRL_COLOR1SRC_MEM << 12) /**< Shifted mode MEM for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1101 #define EBI_TFTCTRL_COLOR1SRC_PIXEL1 (_EBI_TFTCTRL_COLOR1SRC_PIXEL1 << 12) /**< Shifted mode PIXEL1 for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1102 #define EBI_TFTCTRL_WIDTH (0x1UL << 16) /**< TFT Transaction Width */
<> 128:9bcdf88f62b0 1103 #define _EBI_TFTCTRL_WIDTH_SHIFT 16 /**< Shift value for EBI_WIDTH */
<> 128:9bcdf88f62b0 1104 #define _EBI_TFTCTRL_WIDTH_MASK 0x10000UL /**< Bit mask for EBI_WIDTH */
<> 128:9bcdf88f62b0 1105 #define _EBI_TFTCTRL_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1106 #define _EBI_TFTCTRL_WIDTH_BYTE 0x00000000UL /**< Mode BYTE for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1107 #define _EBI_TFTCTRL_WIDTH_HALFWORD 0x00000001UL /**< Mode HALFWORD for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1108 #define EBI_TFTCTRL_WIDTH_DEFAULT (_EBI_TFTCTRL_WIDTH_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1109 #define EBI_TFTCTRL_WIDTH_BYTE (_EBI_TFTCTRL_WIDTH_BYTE << 16) /**< Shifted mode BYTE for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1110 #define EBI_TFTCTRL_WIDTH_HALFWORD (_EBI_TFTCTRL_WIDTH_HALFWORD << 16) /**< Shifted mode HALFWORD for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1111 #define _EBI_TFTCTRL_BANKSEL_SHIFT 20 /**< Shift value for EBI_BANKSEL */
<> 128:9bcdf88f62b0 1112 #define _EBI_TFTCTRL_BANKSEL_MASK 0x300000UL /**< Bit mask for EBI_BANKSEL */
<> 128:9bcdf88f62b0 1113 #define _EBI_TFTCTRL_BANKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1114 #define _EBI_TFTCTRL_BANKSEL_BANK0 0x00000000UL /**< Mode BANK0 for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1115 #define _EBI_TFTCTRL_BANKSEL_BANK1 0x00000001UL /**< Mode BANK1 for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1116 #define _EBI_TFTCTRL_BANKSEL_BANK2 0x00000002UL /**< Mode BANK2 for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1117 #define _EBI_TFTCTRL_BANKSEL_BANK3 0x00000003UL /**< Mode BANK3 for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1118 #define EBI_TFTCTRL_BANKSEL_DEFAULT (_EBI_TFTCTRL_BANKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1119 #define EBI_TFTCTRL_BANKSEL_BANK0 (_EBI_TFTCTRL_BANKSEL_BANK0 << 20) /**< Shifted mode BANK0 for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1120 #define EBI_TFTCTRL_BANKSEL_BANK1 (_EBI_TFTCTRL_BANKSEL_BANK1 << 20) /**< Shifted mode BANK1 for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1121 #define EBI_TFTCTRL_BANKSEL_BANK2 (_EBI_TFTCTRL_BANKSEL_BANK2 << 20) /**< Shifted mode BANK2 for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1122 #define EBI_TFTCTRL_BANKSEL_BANK3 (_EBI_TFTCTRL_BANKSEL_BANK3 << 20) /**< Shifted mode BANK3 for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1123 #define EBI_TFTCTRL_RGBMODE (0x1UL << 24) /**< TFT RGB Mode */
<> 128:9bcdf88f62b0 1124 #define _EBI_TFTCTRL_RGBMODE_SHIFT 24 /**< Shift value for EBI_RGBMODE */
<> 128:9bcdf88f62b0 1125 #define _EBI_TFTCTRL_RGBMODE_MASK 0x1000000UL /**< Bit mask for EBI_RGBMODE */
<> 128:9bcdf88f62b0 1126 #define _EBI_TFTCTRL_RGBMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1127 #define _EBI_TFTCTRL_RGBMODE_RGB565 0x00000000UL /**< Mode RGB565 for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1128 #define _EBI_TFTCTRL_RGBMODE_RGB555 0x00000001UL /**< Mode RGB555 for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1129 #define EBI_TFTCTRL_RGBMODE_DEFAULT (_EBI_TFTCTRL_RGBMODE_DEFAULT << 24) /**< Shifted mode DEFAULT for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1130 #define EBI_TFTCTRL_RGBMODE_RGB565 (_EBI_TFTCTRL_RGBMODE_RGB565 << 24) /**< Shifted mode RGB565 for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1131 #define EBI_TFTCTRL_RGBMODE_RGB555 (_EBI_TFTCTRL_RGBMODE_RGB555 << 24) /**< Shifted mode RGB555 for EBI_TFTCTRL */
<> 128:9bcdf88f62b0 1132
<> 128:9bcdf88f62b0 1133 /* Bit fields for EBI TFTSTATUS */
<> 128:9bcdf88f62b0 1134 #define _EBI_TFTSTATUS_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTSTATUS */
<> 128:9bcdf88f62b0 1135 #define _EBI_TFTSTATUS_MASK 0x07FF07FFUL /**< Mask for EBI_TFTSTATUS */
<> 128:9bcdf88f62b0 1136 #define _EBI_TFTSTATUS_HCNT_SHIFT 0 /**< Shift value for EBI_HCNT */
<> 128:9bcdf88f62b0 1137 #define _EBI_TFTSTATUS_HCNT_MASK 0x7FFUL /**< Bit mask for EBI_HCNT */
<> 128:9bcdf88f62b0 1138 #define _EBI_TFTSTATUS_HCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSTATUS */
<> 128:9bcdf88f62b0 1139 #define EBI_TFTSTATUS_HCNT_DEFAULT (_EBI_TFTSTATUS_HCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTSTATUS */
<> 128:9bcdf88f62b0 1140 #define _EBI_TFTSTATUS_VCNT_SHIFT 16 /**< Shift value for EBI_VCNT */
<> 128:9bcdf88f62b0 1141 #define _EBI_TFTSTATUS_VCNT_MASK 0x7FF0000UL /**< Bit mask for EBI_VCNT */
<> 128:9bcdf88f62b0 1142 #define _EBI_TFTSTATUS_VCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSTATUS */
<> 128:9bcdf88f62b0 1143 #define EBI_TFTSTATUS_VCNT_DEFAULT (_EBI_TFTSTATUS_VCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_TFTSTATUS */
<> 128:9bcdf88f62b0 1144
<> 128:9bcdf88f62b0 1145 /* Bit fields for EBI TFTFRAMEBASE */
<> 128:9bcdf88f62b0 1146 #define _EBI_TFTFRAMEBASE_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTFRAMEBASE */
<> 128:9bcdf88f62b0 1147 #define _EBI_TFTFRAMEBASE_MASK 0x0FFFFFFFUL /**< Mask for EBI_TFTFRAMEBASE */
<> 128:9bcdf88f62b0 1148 #define _EBI_TFTFRAMEBASE_FRAMEBASE_SHIFT 0 /**< Shift value for EBI_FRAMEBASE */
<> 128:9bcdf88f62b0 1149 #define _EBI_TFTFRAMEBASE_FRAMEBASE_MASK 0xFFFFFFFUL /**< Bit mask for EBI_FRAMEBASE */
<> 128:9bcdf88f62b0 1150 #define _EBI_TFTFRAMEBASE_FRAMEBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTFRAMEBASE */
<> 128:9bcdf88f62b0 1151 #define EBI_TFTFRAMEBASE_FRAMEBASE_DEFAULT (_EBI_TFTFRAMEBASE_FRAMEBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTFRAMEBASE */
<> 128:9bcdf88f62b0 1152
<> 128:9bcdf88f62b0 1153 /* Bit fields for EBI TFTSTRIDE */
<> 128:9bcdf88f62b0 1154 #define _EBI_TFTSTRIDE_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTSTRIDE */
<> 128:9bcdf88f62b0 1155 #define _EBI_TFTSTRIDE_MASK 0x00000FFFUL /**< Mask for EBI_TFTSTRIDE */
<> 128:9bcdf88f62b0 1156 #define _EBI_TFTSTRIDE_HSTRIDE_SHIFT 0 /**< Shift value for EBI_HSTRIDE */
<> 128:9bcdf88f62b0 1157 #define _EBI_TFTSTRIDE_HSTRIDE_MASK 0xFFFUL /**< Bit mask for EBI_HSTRIDE */
<> 128:9bcdf88f62b0 1158 #define _EBI_TFTSTRIDE_HSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSTRIDE */
<> 128:9bcdf88f62b0 1159 #define EBI_TFTSTRIDE_HSTRIDE_DEFAULT (_EBI_TFTSTRIDE_HSTRIDE_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTSTRIDE */
<> 128:9bcdf88f62b0 1160
<> 128:9bcdf88f62b0 1161 /* Bit fields for EBI TFTSIZE */
<> 128:9bcdf88f62b0 1162 #define _EBI_TFTSIZE_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTSIZE */
<> 128:9bcdf88f62b0 1163 #define _EBI_TFTSIZE_MASK 0x03FF03FFUL /**< Mask for EBI_TFTSIZE */
<> 128:9bcdf88f62b0 1164 #define _EBI_TFTSIZE_HSZ_SHIFT 0 /**< Shift value for EBI_HSZ */
<> 128:9bcdf88f62b0 1165 #define _EBI_TFTSIZE_HSZ_MASK 0x3FFUL /**< Bit mask for EBI_HSZ */
<> 128:9bcdf88f62b0 1166 #define _EBI_TFTSIZE_HSZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSIZE */
<> 128:9bcdf88f62b0 1167 #define EBI_TFTSIZE_HSZ_DEFAULT (_EBI_TFTSIZE_HSZ_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTSIZE */
<> 128:9bcdf88f62b0 1168 #define _EBI_TFTSIZE_VSZ_SHIFT 16 /**< Shift value for EBI_VSZ */
<> 128:9bcdf88f62b0 1169 #define _EBI_TFTSIZE_VSZ_MASK 0x3FF0000UL /**< Bit mask for EBI_VSZ */
<> 128:9bcdf88f62b0 1170 #define _EBI_TFTSIZE_VSZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSIZE */
<> 128:9bcdf88f62b0 1171 #define EBI_TFTSIZE_VSZ_DEFAULT (_EBI_TFTSIZE_VSZ_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_TFTSIZE */
<> 128:9bcdf88f62b0 1172
<> 128:9bcdf88f62b0 1173 /* Bit fields for EBI TFTHPORCH */
<> 128:9bcdf88f62b0 1174 #define _EBI_TFTHPORCH_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTHPORCH */
<> 128:9bcdf88f62b0 1175 #define _EBI_TFTHPORCH_MASK 0x33FCFF7FUL /**< Mask for EBI_TFTHPORCH */
<> 128:9bcdf88f62b0 1176 #define _EBI_TFTHPORCH_HSYNC_SHIFT 0 /**< Shift value for EBI_HSYNC */
<> 128:9bcdf88f62b0 1177 #define _EBI_TFTHPORCH_HSYNC_MASK 0x7FUL /**< Bit mask for EBI_HSYNC */
<> 128:9bcdf88f62b0 1178 #define _EBI_TFTHPORCH_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTHPORCH */
<> 128:9bcdf88f62b0 1179 #define EBI_TFTHPORCH_HSYNC_DEFAULT (_EBI_TFTHPORCH_HSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTHPORCH */
<> 128:9bcdf88f62b0 1180 #define _EBI_TFTHPORCH_HFPORCH_SHIFT 8 /**< Shift value for EBI_HFPORCH */
<> 128:9bcdf88f62b0 1181 #define _EBI_TFTHPORCH_HFPORCH_MASK 0xFF00UL /**< Bit mask for EBI_HFPORCH */
<> 128:9bcdf88f62b0 1182 #define _EBI_TFTHPORCH_HFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTHPORCH */
<> 128:9bcdf88f62b0 1183 #define EBI_TFTHPORCH_HFPORCH_DEFAULT (_EBI_TFTHPORCH_HFPORCH_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_TFTHPORCH */
<> 128:9bcdf88f62b0 1184 #define _EBI_TFTHPORCH_HBPORCH_SHIFT 18 /**< Shift value for EBI_HBPORCH */
<> 128:9bcdf88f62b0 1185 #define _EBI_TFTHPORCH_HBPORCH_MASK 0x3FC0000UL /**< Bit mask for EBI_HBPORCH */
<> 128:9bcdf88f62b0 1186 #define _EBI_TFTHPORCH_HBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTHPORCH */
<> 128:9bcdf88f62b0 1187 #define EBI_TFTHPORCH_HBPORCH_DEFAULT (_EBI_TFTHPORCH_HBPORCH_DEFAULT << 18) /**< Shifted mode DEFAULT for EBI_TFTHPORCH */
<> 128:9bcdf88f62b0 1188 #define _EBI_TFTHPORCH_HSYNCSTART_SHIFT 28 /**< Shift value for EBI_HSYNCSTART */
<> 128:9bcdf88f62b0 1189 #define _EBI_TFTHPORCH_HSYNCSTART_MASK 0x30000000UL /**< Bit mask for EBI_HSYNCSTART */
<> 128:9bcdf88f62b0 1190 #define _EBI_TFTHPORCH_HSYNCSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTHPORCH */
<> 128:9bcdf88f62b0 1191 #define EBI_TFTHPORCH_HSYNCSTART_DEFAULT (_EBI_TFTHPORCH_HSYNCSTART_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_TFTHPORCH */
<> 128:9bcdf88f62b0 1192
<> 128:9bcdf88f62b0 1193 /* Bit fields for EBI TFTVPORCH */
<> 128:9bcdf88f62b0 1194 #define _EBI_TFTVPORCH_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTVPORCH */
<> 128:9bcdf88f62b0 1195 #define _EBI_TFTVPORCH_MASK 0x03FCFF7FUL /**< Mask for EBI_TFTVPORCH */
<> 128:9bcdf88f62b0 1196 #define _EBI_TFTVPORCH_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */
<> 128:9bcdf88f62b0 1197 #define _EBI_TFTVPORCH_VSYNC_MASK 0x7FUL /**< Bit mask for EBI_VSYNC */
<> 128:9bcdf88f62b0 1198 #define _EBI_TFTVPORCH_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTVPORCH */
<> 128:9bcdf88f62b0 1199 #define EBI_TFTVPORCH_VSYNC_DEFAULT (_EBI_TFTVPORCH_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTVPORCH */
<> 128:9bcdf88f62b0 1200 #define _EBI_TFTVPORCH_VFPORCH_SHIFT 8 /**< Shift value for EBI_VFPORCH */
<> 128:9bcdf88f62b0 1201 #define _EBI_TFTVPORCH_VFPORCH_MASK 0xFF00UL /**< Bit mask for EBI_VFPORCH */
<> 128:9bcdf88f62b0 1202 #define _EBI_TFTVPORCH_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTVPORCH */
<> 128:9bcdf88f62b0 1203 #define EBI_TFTVPORCH_VFPORCH_DEFAULT (_EBI_TFTVPORCH_VFPORCH_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_TFTVPORCH */
<> 128:9bcdf88f62b0 1204 #define _EBI_TFTVPORCH_VBPORCH_SHIFT 18 /**< Shift value for EBI_VBPORCH */
<> 128:9bcdf88f62b0 1205 #define _EBI_TFTVPORCH_VBPORCH_MASK 0x3FC0000UL /**< Bit mask for EBI_VBPORCH */
<> 128:9bcdf88f62b0 1206 #define _EBI_TFTVPORCH_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTVPORCH */
<> 128:9bcdf88f62b0 1207 #define EBI_TFTVPORCH_VBPORCH_DEFAULT (_EBI_TFTVPORCH_VBPORCH_DEFAULT << 18) /**< Shifted mode DEFAULT for EBI_TFTVPORCH */
<> 128:9bcdf88f62b0 1208
<> 128:9bcdf88f62b0 1209 /* Bit fields for EBI TFTTIMING */
<> 128:9bcdf88f62b0 1210 #define _EBI_TFTTIMING_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTTIMING */
<> 128:9bcdf88f62b0 1211 #define _EBI_TFTTIMING_MASK 0x337FF7FFUL /**< Mask for EBI_TFTTIMING */
<> 128:9bcdf88f62b0 1212 #define _EBI_TFTTIMING_DCLKPERIOD_SHIFT 0 /**< Shift value for EBI_DCLKPERIOD */
<> 128:9bcdf88f62b0 1213 #define _EBI_TFTTIMING_DCLKPERIOD_MASK 0x7FFUL /**< Bit mask for EBI_DCLKPERIOD */
<> 128:9bcdf88f62b0 1214 #define _EBI_TFTTIMING_DCLKPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTTIMING */
<> 128:9bcdf88f62b0 1215 #define EBI_TFTTIMING_DCLKPERIOD_DEFAULT (_EBI_TFTTIMING_DCLKPERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTTIMING */
<> 128:9bcdf88f62b0 1216 #define _EBI_TFTTIMING_TFTSTART_SHIFT 12 /**< Shift value for EBI_TFTSTART */
<> 128:9bcdf88f62b0 1217 #define _EBI_TFTTIMING_TFTSTART_MASK 0x7FF000UL /**< Bit mask for EBI_TFTSTART */
<> 128:9bcdf88f62b0 1218 #define _EBI_TFTTIMING_TFTSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTTIMING */
<> 128:9bcdf88f62b0 1219 #define EBI_TFTTIMING_TFTSTART_DEFAULT (_EBI_TFTTIMING_TFTSTART_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_TFTTIMING */
<> 128:9bcdf88f62b0 1220 #define _EBI_TFTTIMING_TFTSETUP_SHIFT 24 /**< Shift value for EBI_TFTSETUP */
<> 128:9bcdf88f62b0 1221 #define _EBI_TFTTIMING_TFTSETUP_MASK 0x3000000UL /**< Bit mask for EBI_TFTSETUP */
<> 128:9bcdf88f62b0 1222 #define _EBI_TFTTIMING_TFTSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTTIMING */
<> 128:9bcdf88f62b0 1223 #define EBI_TFTTIMING_TFTSETUP_DEFAULT (_EBI_TFTTIMING_TFTSETUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EBI_TFTTIMING */
<> 128:9bcdf88f62b0 1224 #define _EBI_TFTTIMING_TFTHOLD_SHIFT 28 /**< Shift value for EBI_TFTHOLD */
<> 128:9bcdf88f62b0 1225 #define _EBI_TFTTIMING_TFTHOLD_MASK 0x30000000UL /**< Bit mask for EBI_TFTHOLD */
<> 128:9bcdf88f62b0 1226 #define _EBI_TFTTIMING_TFTHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTTIMING */
<> 128:9bcdf88f62b0 1227 #define EBI_TFTTIMING_TFTHOLD_DEFAULT (_EBI_TFTTIMING_TFTHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_TFTTIMING */
<> 128:9bcdf88f62b0 1228
<> 128:9bcdf88f62b0 1229 /* Bit fields for EBI TFTPOLARITY */
<> 128:9bcdf88f62b0 1230 #define _EBI_TFTPOLARITY_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1231 #define _EBI_TFTPOLARITY_MASK 0x0000001FUL /**< Mask for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1232 #define EBI_TFTPOLARITY_CSPOL (0x1UL << 0) /**< TFT Chip Select Polarity */
<> 128:9bcdf88f62b0 1233 #define _EBI_TFTPOLARITY_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */
<> 128:9bcdf88f62b0 1234 #define _EBI_TFTPOLARITY_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */
<> 128:9bcdf88f62b0 1235 #define _EBI_TFTPOLARITY_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1236 #define _EBI_TFTPOLARITY_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1237 #define _EBI_TFTPOLARITY_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1238 #define EBI_TFTPOLARITY_CSPOL_DEFAULT (_EBI_TFTPOLARITY_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1239 #define EBI_TFTPOLARITY_CSPOL_ACTIVELOW (_EBI_TFTPOLARITY_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1240 #define EBI_TFTPOLARITY_CSPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1241 #define EBI_TFTPOLARITY_DCLKPOL (0x1UL << 1) /**< TFT DCLK Polarity */
<> 128:9bcdf88f62b0 1242 #define _EBI_TFTPOLARITY_DCLKPOL_SHIFT 1 /**< Shift value for EBI_DCLKPOL */
<> 128:9bcdf88f62b0 1243 #define _EBI_TFTPOLARITY_DCLKPOL_MASK 0x2UL /**< Bit mask for EBI_DCLKPOL */
<> 128:9bcdf88f62b0 1244 #define _EBI_TFTPOLARITY_DCLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1245 #define _EBI_TFTPOLARITY_DCLKPOL_ACTIVEFALLING 0x00000000UL /**< Mode ACTIVEFALLING for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1246 #define _EBI_TFTPOLARITY_DCLKPOL_ACTIVERISING 0x00000001UL /**< Mode ACTIVERISING for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1247 #define EBI_TFTPOLARITY_DCLKPOL_DEFAULT (_EBI_TFTPOLARITY_DCLKPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1248 #define EBI_TFTPOLARITY_DCLKPOL_ACTIVEFALLING (_EBI_TFTPOLARITY_DCLKPOL_ACTIVEFALLING << 1) /**< Shifted mode ACTIVEFALLING for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1249 #define EBI_TFTPOLARITY_DCLKPOL_ACTIVERISING (_EBI_TFTPOLARITY_DCLKPOL_ACTIVERISING << 1) /**< Shifted mode ACTIVERISING for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1250 #define EBI_TFTPOLARITY_DATAENPOL (0x1UL << 2) /**< TFT DATAEN Polarity */
<> 128:9bcdf88f62b0 1251 #define _EBI_TFTPOLARITY_DATAENPOL_SHIFT 2 /**< Shift value for EBI_DATAENPOL */
<> 128:9bcdf88f62b0 1252 #define _EBI_TFTPOLARITY_DATAENPOL_MASK 0x4UL /**< Bit mask for EBI_DATAENPOL */
<> 128:9bcdf88f62b0 1253 #define _EBI_TFTPOLARITY_DATAENPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1254 #define _EBI_TFTPOLARITY_DATAENPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1255 #define _EBI_TFTPOLARITY_DATAENPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1256 #define EBI_TFTPOLARITY_DATAENPOL_DEFAULT (_EBI_TFTPOLARITY_DATAENPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1257 #define EBI_TFTPOLARITY_DATAENPOL_ACTIVELOW (_EBI_TFTPOLARITY_DATAENPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1258 #define EBI_TFTPOLARITY_DATAENPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_DATAENPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1259 #define EBI_TFTPOLARITY_HSYNCPOL (0x1UL << 3) /**< Address Latch Polarity */
<> 128:9bcdf88f62b0 1260 #define _EBI_TFTPOLARITY_HSYNCPOL_SHIFT 3 /**< Shift value for EBI_HSYNCPOL */
<> 128:9bcdf88f62b0 1261 #define _EBI_TFTPOLARITY_HSYNCPOL_MASK 0x8UL /**< Bit mask for EBI_HSYNCPOL */
<> 128:9bcdf88f62b0 1262 #define _EBI_TFTPOLARITY_HSYNCPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1263 #define _EBI_TFTPOLARITY_HSYNCPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1264 #define _EBI_TFTPOLARITY_HSYNCPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1265 #define EBI_TFTPOLARITY_HSYNCPOL_DEFAULT (_EBI_TFTPOLARITY_HSYNCPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1266 #define EBI_TFTPOLARITY_HSYNCPOL_ACTIVELOW (_EBI_TFTPOLARITY_HSYNCPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1267 #define EBI_TFTPOLARITY_HSYNCPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_HSYNCPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1268 #define EBI_TFTPOLARITY_VSYNCPOL (0x1UL << 4) /**< VSYNC Polarity */
<> 128:9bcdf88f62b0 1269 #define _EBI_TFTPOLARITY_VSYNCPOL_SHIFT 4 /**< Shift value for EBI_VSYNCPOL */
<> 128:9bcdf88f62b0 1270 #define _EBI_TFTPOLARITY_VSYNCPOL_MASK 0x10UL /**< Bit mask for EBI_VSYNCPOL */
<> 128:9bcdf88f62b0 1271 #define _EBI_TFTPOLARITY_VSYNCPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1272 #define _EBI_TFTPOLARITY_VSYNCPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1273 #define _EBI_TFTPOLARITY_VSYNCPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1274 #define EBI_TFTPOLARITY_VSYNCPOL_DEFAULT (_EBI_TFTPOLARITY_VSYNCPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1275 #define EBI_TFTPOLARITY_VSYNCPOL_ACTIVELOW (_EBI_TFTPOLARITY_VSYNCPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1276 #define EBI_TFTPOLARITY_VSYNCPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_VSYNCPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */
<> 128:9bcdf88f62b0 1277
<> 128:9bcdf88f62b0 1278 /* Bit fields for EBI TFTDD */
<> 128:9bcdf88f62b0 1279 #define _EBI_TFTDD_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTDD */
<> 128:9bcdf88f62b0 1280 #define _EBI_TFTDD_MASK 0x0000FFFFUL /**< Mask for EBI_TFTDD */
<> 128:9bcdf88f62b0 1281 #define _EBI_TFTDD_DATA_SHIFT 0 /**< Shift value for EBI_DATA */
<> 128:9bcdf88f62b0 1282 #define _EBI_TFTDD_DATA_MASK 0xFFFFUL /**< Bit mask for EBI_DATA */
<> 128:9bcdf88f62b0 1283 #define _EBI_TFTDD_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTDD */
<> 128:9bcdf88f62b0 1284 #define EBI_TFTDD_DATA_DEFAULT (_EBI_TFTDD_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTDD */
<> 128:9bcdf88f62b0 1285
<> 128:9bcdf88f62b0 1286 /* Bit fields for EBI TFTALPHA */
<> 128:9bcdf88f62b0 1287 #define _EBI_TFTALPHA_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTALPHA */
<> 128:9bcdf88f62b0 1288 #define _EBI_TFTALPHA_MASK 0x000001FFUL /**< Mask for EBI_TFTALPHA */
<> 128:9bcdf88f62b0 1289 #define _EBI_TFTALPHA_ALPHA_SHIFT 0 /**< Shift value for EBI_ALPHA */
<> 128:9bcdf88f62b0 1290 #define _EBI_TFTALPHA_ALPHA_MASK 0x1FFUL /**< Bit mask for EBI_ALPHA */
<> 128:9bcdf88f62b0 1291 #define _EBI_TFTALPHA_ALPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTALPHA */
<> 128:9bcdf88f62b0 1292 #define EBI_TFTALPHA_ALPHA_DEFAULT (_EBI_TFTALPHA_ALPHA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTALPHA */
<> 128:9bcdf88f62b0 1293
<> 128:9bcdf88f62b0 1294 /* Bit fields for EBI TFTPIXEL0 */
<> 128:9bcdf88f62b0 1295 #define _EBI_TFTPIXEL0_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTPIXEL0 */
<> 128:9bcdf88f62b0 1296 #define _EBI_TFTPIXEL0_MASK 0x0000FFFFUL /**< Mask for EBI_TFTPIXEL0 */
<> 128:9bcdf88f62b0 1297 #define _EBI_TFTPIXEL0_DATA_SHIFT 0 /**< Shift value for EBI_DATA */
<> 128:9bcdf88f62b0 1298 #define _EBI_TFTPIXEL0_DATA_MASK 0xFFFFUL /**< Bit mask for EBI_DATA */
<> 128:9bcdf88f62b0 1299 #define _EBI_TFTPIXEL0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPIXEL0 */
<> 128:9bcdf88f62b0 1300 #define EBI_TFTPIXEL0_DATA_DEFAULT (_EBI_TFTPIXEL0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPIXEL0 */
<> 128:9bcdf88f62b0 1301
<> 128:9bcdf88f62b0 1302 /* Bit fields for EBI TFTPIXEL1 */
<> 128:9bcdf88f62b0 1303 #define _EBI_TFTPIXEL1_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTPIXEL1 */
<> 128:9bcdf88f62b0 1304 #define _EBI_TFTPIXEL1_MASK 0x0000FFFFUL /**< Mask for EBI_TFTPIXEL1 */
<> 128:9bcdf88f62b0 1305 #define _EBI_TFTPIXEL1_DATA_SHIFT 0 /**< Shift value for EBI_DATA */
<> 128:9bcdf88f62b0 1306 #define _EBI_TFTPIXEL1_DATA_MASK 0xFFFFUL /**< Bit mask for EBI_DATA */
<> 128:9bcdf88f62b0 1307 #define _EBI_TFTPIXEL1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPIXEL1 */
<> 128:9bcdf88f62b0 1308 #define EBI_TFTPIXEL1_DATA_DEFAULT (_EBI_TFTPIXEL1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPIXEL1 */
<> 128:9bcdf88f62b0 1309
<> 128:9bcdf88f62b0 1310 /* Bit fields for EBI TFTPIXEL */
<> 128:9bcdf88f62b0 1311 #define _EBI_TFTPIXEL_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTPIXEL */
<> 128:9bcdf88f62b0 1312 #define _EBI_TFTPIXEL_MASK 0x0000FFFFUL /**< Mask for EBI_TFTPIXEL */
<> 128:9bcdf88f62b0 1313 #define _EBI_TFTPIXEL_DATA_SHIFT 0 /**< Shift value for EBI_DATA */
<> 128:9bcdf88f62b0 1314 #define _EBI_TFTPIXEL_DATA_MASK 0xFFFFUL /**< Bit mask for EBI_DATA */
<> 128:9bcdf88f62b0 1315 #define _EBI_TFTPIXEL_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPIXEL */
<> 128:9bcdf88f62b0 1316 #define EBI_TFTPIXEL_DATA_DEFAULT (_EBI_TFTPIXEL_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPIXEL */
<> 128:9bcdf88f62b0 1317
<> 128:9bcdf88f62b0 1318 /* Bit fields for EBI TFTMASK */
<> 128:9bcdf88f62b0 1319 #define _EBI_TFTMASK_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTMASK */
<> 128:9bcdf88f62b0 1320 #define _EBI_TFTMASK_MASK 0x0000FFFFUL /**< Mask for EBI_TFTMASK */
<> 128:9bcdf88f62b0 1321 #define _EBI_TFTMASK_TFTMASK_SHIFT 0 /**< Shift value for EBI_TFTMASK */
<> 128:9bcdf88f62b0 1322 #define _EBI_TFTMASK_TFTMASK_MASK 0xFFFFUL /**< Bit mask for EBI_TFTMASK */
<> 128:9bcdf88f62b0 1323 #define _EBI_TFTMASK_TFTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTMASK */
<> 128:9bcdf88f62b0 1324 #define EBI_TFTMASK_TFTMASK_DEFAULT (_EBI_TFTMASK_TFTMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTMASK */
<> 128:9bcdf88f62b0 1325
<> 128:9bcdf88f62b0 1326 /* Bit fields for EBI IF */
<> 128:9bcdf88f62b0 1327 #define _EBI_IF_RESETVALUE 0x00000000UL /**< Default value for EBI_IF */
<> 128:9bcdf88f62b0 1328 #define _EBI_IF_MASK 0x0000003FUL /**< Mask for EBI_IF */
<> 128:9bcdf88f62b0 1329 #define EBI_IF_VSYNC (0x1UL << 0) /**< Vertical Sync Interrupt Flag */
<> 128:9bcdf88f62b0 1330 #define _EBI_IF_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */
<> 128:9bcdf88f62b0 1331 #define _EBI_IF_VSYNC_MASK 0x1UL /**< Bit mask for EBI_VSYNC */
<> 128:9bcdf88f62b0 1332 #define _EBI_IF_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */
<> 128:9bcdf88f62b0 1333 #define EBI_IF_VSYNC_DEFAULT (_EBI_IF_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_IF */
<> 128:9bcdf88f62b0 1334 #define EBI_IF_HSYNC (0x1UL << 1) /**< Horizontal Sync Interrupt Flag */
<> 128:9bcdf88f62b0 1335 #define _EBI_IF_HSYNC_SHIFT 1 /**< Shift value for EBI_HSYNC */
<> 128:9bcdf88f62b0 1336 #define _EBI_IF_HSYNC_MASK 0x2UL /**< Bit mask for EBI_HSYNC */
<> 128:9bcdf88f62b0 1337 #define _EBI_IF_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */
<> 128:9bcdf88f62b0 1338 #define EBI_IF_HSYNC_DEFAULT (_EBI_IF_HSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_IF */
<> 128:9bcdf88f62b0 1339 #define EBI_IF_VBPORCH (0x1UL << 2) /**< Vertical Back Porch Interrupt Flag */
<> 128:9bcdf88f62b0 1340 #define _EBI_IF_VBPORCH_SHIFT 2 /**< Shift value for EBI_VBPORCH */
<> 128:9bcdf88f62b0 1341 #define _EBI_IF_VBPORCH_MASK 0x4UL /**< Bit mask for EBI_VBPORCH */
<> 128:9bcdf88f62b0 1342 #define _EBI_IF_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */
<> 128:9bcdf88f62b0 1343 #define EBI_IF_VBPORCH_DEFAULT (_EBI_IF_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IF */
<> 128:9bcdf88f62b0 1344 #define EBI_IF_VFPORCH (0x1UL << 3) /**< Vertical Front Porch Interrupt Flag */
<> 128:9bcdf88f62b0 1345 #define _EBI_IF_VFPORCH_SHIFT 3 /**< Shift value for EBI_VFPORCH */
<> 128:9bcdf88f62b0 1346 #define _EBI_IF_VFPORCH_MASK 0x8UL /**< Bit mask for EBI_VFPORCH */
<> 128:9bcdf88f62b0 1347 #define _EBI_IF_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */
<> 128:9bcdf88f62b0 1348 #define EBI_IF_VFPORCH_DEFAULT (_EBI_IF_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IF */
<> 128:9bcdf88f62b0 1349 #define EBI_IF_DDEMPTY (0x1UL << 4) /**< Direct Drive Data Empty Interrupt Flag */
<> 128:9bcdf88f62b0 1350 #define _EBI_IF_DDEMPTY_SHIFT 4 /**< Shift value for EBI_DDEMPTY */
<> 128:9bcdf88f62b0 1351 #define _EBI_IF_DDEMPTY_MASK 0x10UL /**< Bit mask for EBI_DDEMPTY */
<> 128:9bcdf88f62b0 1352 #define _EBI_IF_DDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */
<> 128:9bcdf88f62b0 1353 #define EBI_IF_DDEMPTY_DEFAULT (_EBI_IF_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IF */
<> 128:9bcdf88f62b0 1354 #define EBI_IF_DDJIT (0x1UL << 5) /**< Direct Drive Jitter Interrupt Flag */
<> 128:9bcdf88f62b0 1355 #define _EBI_IF_DDJIT_SHIFT 5 /**< Shift value for EBI_DDJIT */
<> 128:9bcdf88f62b0 1356 #define _EBI_IF_DDJIT_MASK 0x20UL /**< Bit mask for EBI_DDJIT */
<> 128:9bcdf88f62b0 1357 #define _EBI_IF_DDJIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */
<> 128:9bcdf88f62b0 1358 #define EBI_IF_DDJIT_DEFAULT (_EBI_IF_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IF */
<> 128:9bcdf88f62b0 1359
<> 128:9bcdf88f62b0 1360 /* Bit fields for EBI IFS */
<> 128:9bcdf88f62b0 1361 #define _EBI_IFS_RESETVALUE 0x00000000UL /**< Default value for EBI_IFS */
<> 128:9bcdf88f62b0 1362 #define _EBI_IFS_MASK 0x0000003FUL /**< Mask for EBI_IFS */
<> 128:9bcdf88f62b0 1363 #define EBI_IFS_VSYNC (0x1UL << 0) /**< Vertical Sync Interrupt Flag Set */
<> 128:9bcdf88f62b0 1364 #define _EBI_IFS_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */
<> 128:9bcdf88f62b0 1365 #define _EBI_IFS_VSYNC_MASK 0x1UL /**< Bit mask for EBI_VSYNC */
<> 128:9bcdf88f62b0 1366 #define _EBI_IFS_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */
<> 128:9bcdf88f62b0 1367 #define EBI_IFS_VSYNC_DEFAULT (_EBI_IFS_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_IFS */
<> 128:9bcdf88f62b0 1368 #define EBI_IFS_HSYNC (0x1UL << 1) /**< Horizontal Sync Interrupt Flag Set */
<> 128:9bcdf88f62b0 1369 #define _EBI_IFS_HSYNC_SHIFT 1 /**< Shift value for EBI_HSYNC */
<> 128:9bcdf88f62b0 1370 #define _EBI_IFS_HSYNC_MASK 0x2UL /**< Bit mask for EBI_HSYNC */
<> 128:9bcdf88f62b0 1371 #define _EBI_IFS_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */
<> 128:9bcdf88f62b0 1372 #define EBI_IFS_HSYNC_DEFAULT (_EBI_IFS_HSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_IFS */
<> 128:9bcdf88f62b0 1373 #define EBI_IFS_VBPORCH (0x1UL << 2) /**< Vertical Back Porch Interrupt Flag Set */
<> 128:9bcdf88f62b0 1374 #define _EBI_IFS_VBPORCH_SHIFT 2 /**< Shift value for EBI_VBPORCH */
<> 128:9bcdf88f62b0 1375 #define _EBI_IFS_VBPORCH_MASK 0x4UL /**< Bit mask for EBI_VBPORCH */
<> 128:9bcdf88f62b0 1376 #define _EBI_IFS_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */
<> 128:9bcdf88f62b0 1377 #define EBI_IFS_VBPORCH_DEFAULT (_EBI_IFS_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IFS */
<> 128:9bcdf88f62b0 1378 #define EBI_IFS_VFPORCH (0x1UL << 3) /**< Vertical Front Porch Interrupt Flag Set */
<> 128:9bcdf88f62b0 1379 #define _EBI_IFS_VFPORCH_SHIFT 3 /**< Shift value for EBI_VFPORCH */
<> 128:9bcdf88f62b0 1380 #define _EBI_IFS_VFPORCH_MASK 0x8UL /**< Bit mask for EBI_VFPORCH */
<> 128:9bcdf88f62b0 1381 #define _EBI_IFS_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */
<> 128:9bcdf88f62b0 1382 #define EBI_IFS_VFPORCH_DEFAULT (_EBI_IFS_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IFS */
<> 128:9bcdf88f62b0 1383 #define EBI_IFS_DDEMPTY (0x1UL << 4) /**< Direct Drive Data Empty Interrupt Flag Set */
<> 128:9bcdf88f62b0 1384 #define _EBI_IFS_DDEMPTY_SHIFT 4 /**< Shift value for EBI_DDEMPTY */
<> 128:9bcdf88f62b0 1385 #define _EBI_IFS_DDEMPTY_MASK 0x10UL /**< Bit mask for EBI_DDEMPTY */
<> 128:9bcdf88f62b0 1386 #define _EBI_IFS_DDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */
<> 128:9bcdf88f62b0 1387 #define EBI_IFS_DDEMPTY_DEFAULT (_EBI_IFS_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IFS */
<> 128:9bcdf88f62b0 1388 #define EBI_IFS_DDJIT (0x1UL << 5) /**< Direct Drive Jitter Interrupt Flag Set */
<> 128:9bcdf88f62b0 1389 #define _EBI_IFS_DDJIT_SHIFT 5 /**< Shift value for EBI_DDJIT */
<> 128:9bcdf88f62b0 1390 #define _EBI_IFS_DDJIT_MASK 0x20UL /**< Bit mask for EBI_DDJIT */
<> 128:9bcdf88f62b0 1391 #define _EBI_IFS_DDJIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */
<> 128:9bcdf88f62b0 1392 #define EBI_IFS_DDJIT_DEFAULT (_EBI_IFS_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IFS */
<> 128:9bcdf88f62b0 1393
<> 128:9bcdf88f62b0 1394 /* Bit fields for EBI IFC */
<> 128:9bcdf88f62b0 1395 #define _EBI_IFC_RESETVALUE 0x00000000UL /**< Default value for EBI_IFC */
<> 128:9bcdf88f62b0 1396 #define _EBI_IFC_MASK 0x0000003FUL /**< Mask for EBI_IFC */
<> 128:9bcdf88f62b0 1397 #define EBI_IFC_VSYNC (0x1UL << 0) /**< Vertical Sync Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1398 #define _EBI_IFC_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */
<> 128:9bcdf88f62b0 1399 #define _EBI_IFC_VSYNC_MASK 0x1UL /**< Bit mask for EBI_VSYNC */
<> 128:9bcdf88f62b0 1400 #define _EBI_IFC_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */
<> 128:9bcdf88f62b0 1401 #define EBI_IFC_VSYNC_DEFAULT (_EBI_IFC_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_IFC */
<> 128:9bcdf88f62b0 1402 #define EBI_IFC_HSYNC (0x1UL << 1) /**< Horizontal Sync Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1403 #define _EBI_IFC_HSYNC_SHIFT 1 /**< Shift value for EBI_HSYNC */
<> 128:9bcdf88f62b0 1404 #define _EBI_IFC_HSYNC_MASK 0x2UL /**< Bit mask for EBI_HSYNC */
<> 128:9bcdf88f62b0 1405 #define _EBI_IFC_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */
<> 128:9bcdf88f62b0 1406 #define EBI_IFC_HSYNC_DEFAULT (_EBI_IFC_HSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_IFC */
<> 128:9bcdf88f62b0 1407 #define EBI_IFC_VBPORCH (0x1UL << 2) /**< Vertical Back Porch Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1408 #define _EBI_IFC_VBPORCH_SHIFT 2 /**< Shift value for EBI_VBPORCH */
<> 128:9bcdf88f62b0 1409 #define _EBI_IFC_VBPORCH_MASK 0x4UL /**< Bit mask for EBI_VBPORCH */
<> 128:9bcdf88f62b0 1410 #define _EBI_IFC_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */
<> 128:9bcdf88f62b0 1411 #define EBI_IFC_VBPORCH_DEFAULT (_EBI_IFC_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IFC */
<> 128:9bcdf88f62b0 1412 #define EBI_IFC_VFPORCH (0x1UL << 3) /**< Vertical Front Porch Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1413 #define _EBI_IFC_VFPORCH_SHIFT 3 /**< Shift value for EBI_VFPORCH */
<> 128:9bcdf88f62b0 1414 #define _EBI_IFC_VFPORCH_MASK 0x8UL /**< Bit mask for EBI_VFPORCH */
<> 128:9bcdf88f62b0 1415 #define _EBI_IFC_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */
<> 128:9bcdf88f62b0 1416 #define EBI_IFC_VFPORCH_DEFAULT (_EBI_IFC_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IFC */
<> 128:9bcdf88f62b0 1417 #define EBI_IFC_DDEMPTY (0x1UL << 4) /**< Direct Drive Data Empty Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1418 #define _EBI_IFC_DDEMPTY_SHIFT 4 /**< Shift value for EBI_DDEMPTY */
<> 128:9bcdf88f62b0 1419 #define _EBI_IFC_DDEMPTY_MASK 0x10UL /**< Bit mask for EBI_DDEMPTY */
<> 128:9bcdf88f62b0 1420 #define _EBI_IFC_DDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */
<> 128:9bcdf88f62b0 1421 #define EBI_IFC_DDEMPTY_DEFAULT (_EBI_IFC_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IFC */
<> 128:9bcdf88f62b0 1422 #define EBI_IFC_DDJIT (0x1UL << 5) /**< Direct Drive Jitter Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1423 #define _EBI_IFC_DDJIT_SHIFT 5 /**< Shift value for EBI_DDJIT */
<> 128:9bcdf88f62b0 1424 #define _EBI_IFC_DDJIT_MASK 0x20UL /**< Bit mask for EBI_DDJIT */
<> 128:9bcdf88f62b0 1425 #define _EBI_IFC_DDJIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */
<> 128:9bcdf88f62b0 1426 #define EBI_IFC_DDJIT_DEFAULT (_EBI_IFC_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IFC */
<> 128:9bcdf88f62b0 1427
<> 128:9bcdf88f62b0 1428 /* Bit fields for EBI IEN */
<> 128:9bcdf88f62b0 1429 #define _EBI_IEN_RESETVALUE 0x00000000UL /**< Default value for EBI_IEN */
<> 128:9bcdf88f62b0 1430 #define _EBI_IEN_MASK 0x0000003FUL /**< Mask for EBI_IEN */
<> 128:9bcdf88f62b0 1431 #define EBI_IEN_VSYNC (0x1UL << 0) /**< Vertical Sync Interrupt Enable */
<> 128:9bcdf88f62b0 1432 #define _EBI_IEN_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */
<> 128:9bcdf88f62b0 1433 #define _EBI_IEN_VSYNC_MASK 0x1UL /**< Bit mask for EBI_VSYNC */
<> 128:9bcdf88f62b0 1434 #define _EBI_IEN_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */
<> 128:9bcdf88f62b0 1435 #define EBI_IEN_VSYNC_DEFAULT (_EBI_IEN_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_IEN */
<> 128:9bcdf88f62b0 1436 #define EBI_IEN_HSYNC (0x1UL << 1) /**< Horizontal Sync Interrupt Enable */
<> 128:9bcdf88f62b0 1437 #define _EBI_IEN_HSYNC_SHIFT 1 /**< Shift value for EBI_HSYNC */
<> 128:9bcdf88f62b0 1438 #define _EBI_IEN_HSYNC_MASK 0x2UL /**< Bit mask for EBI_HSYNC */
<> 128:9bcdf88f62b0 1439 #define _EBI_IEN_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */
<> 128:9bcdf88f62b0 1440 #define EBI_IEN_HSYNC_DEFAULT (_EBI_IEN_HSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_IEN */
<> 128:9bcdf88f62b0 1441 #define EBI_IEN_VBPORCH (0x1UL << 2) /**< Vertical Back Porch Interrupt Enable */
<> 128:9bcdf88f62b0 1442 #define _EBI_IEN_VBPORCH_SHIFT 2 /**< Shift value for EBI_VBPORCH */
<> 128:9bcdf88f62b0 1443 #define _EBI_IEN_VBPORCH_MASK 0x4UL /**< Bit mask for EBI_VBPORCH */
<> 128:9bcdf88f62b0 1444 #define _EBI_IEN_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */
<> 128:9bcdf88f62b0 1445 #define EBI_IEN_VBPORCH_DEFAULT (_EBI_IEN_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IEN */
<> 128:9bcdf88f62b0 1446 #define EBI_IEN_VFPORCH (0x1UL << 3) /**< Vertical Front Porch Interrupt Enable */
<> 128:9bcdf88f62b0 1447 #define _EBI_IEN_VFPORCH_SHIFT 3 /**< Shift value for EBI_VFPORCH */
<> 128:9bcdf88f62b0 1448 #define _EBI_IEN_VFPORCH_MASK 0x8UL /**< Bit mask for EBI_VFPORCH */
<> 128:9bcdf88f62b0 1449 #define _EBI_IEN_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */
<> 128:9bcdf88f62b0 1450 #define EBI_IEN_VFPORCH_DEFAULT (_EBI_IEN_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IEN */
<> 128:9bcdf88f62b0 1451 #define EBI_IEN_DDEMPTY (0x1UL << 4) /**< Direct Drive Data Empty Interrupt Enable */
<> 128:9bcdf88f62b0 1452 #define _EBI_IEN_DDEMPTY_SHIFT 4 /**< Shift value for EBI_DDEMPTY */
<> 128:9bcdf88f62b0 1453 #define _EBI_IEN_DDEMPTY_MASK 0x10UL /**< Bit mask for EBI_DDEMPTY */
<> 128:9bcdf88f62b0 1454 #define _EBI_IEN_DDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */
<> 128:9bcdf88f62b0 1455 #define EBI_IEN_DDEMPTY_DEFAULT (_EBI_IEN_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IEN */
<> 128:9bcdf88f62b0 1456 #define EBI_IEN_DDJIT (0x1UL << 5) /**< Direct Drive Jitter Interrupt Enable */
<> 128:9bcdf88f62b0 1457 #define _EBI_IEN_DDJIT_SHIFT 5 /**< Shift value for EBI_DDJIT */
<> 128:9bcdf88f62b0 1458 #define _EBI_IEN_DDJIT_MASK 0x20UL /**< Bit mask for EBI_DDJIT */
<> 128:9bcdf88f62b0 1459 #define _EBI_IEN_DDJIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */
<> 128:9bcdf88f62b0 1460 #define EBI_IEN_DDJIT_DEFAULT (_EBI_IEN_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IEN */
<> 128:9bcdf88f62b0 1461
<> 128:9bcdf88f62b0 1462 /** @} End of group EFM32LG_EBI */
<> 128:9bcdf88f62b0 1463 /** @} End of group Parts */
<> 128:9bcdf88f62b0 1464