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TARGET_MTB_ADV_WISE_1530/cmsis_gcc.h@167:84c0a372a020, 2018-05-11 (annotated)

Committer:: AnnaBridge
Date:: Fri May 11 16:51:14 2018 +0100
Revision:: 167:84c0a372a020
Child:: 169:a7c7b631e539

mbed library. Release version 162

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	167:84c0a372a020	1	/************************************************************************//
AnnaBridge	167:84c0a372a020	2	* @file cmsis_gcc.h
AnnaBridge	167:84c0a372a020	3	* @brief CMSIS compiler GCC header file
AnnaBridge	167:84c0a372a020	4	* @version V5.0.2
AnnaBridge	167:84c0a372a020	5	* @date 13. February 2017
AnnaBridge	167:84c0a372a020	6	******************************************************************************/
AnnaBridge	167:84c0a372a020	7	/*
AnnaBridge	167:84c0a372a020	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge	167:84c0a372a020	9	*
AnnaBridge	167:84c0a372a020	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	167:84c0a372a020	11	*
AnnaBridge	167:84c0a372a020	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	167:84c0a372a020	13	* not use this file except in compliance with the License.
AnnaBridge	167:84c0a372a020	14	* You may obtain a copy of the License at
AnnaBridge	167:84c0a372a020	15	*
AnnaBridge	167:84c0a372a020	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	167:84c0a372a020	17	*
AnnaBridge	167:84c0a372a020	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	167:84c0a372a020	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	167:84c0a372a020	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	167:84c0a372a020	21	* See the License for the specific language governing permissions and
AnnaBridge	167:84c0a372a020	22	* limitations under the License.
AnnaBridge	167:84c0a372a020	23	*/
AnnaBridge	167:84c0a372a020	24
AnnaBridge	167:84c0a372a020	25	#ifndef __CMSIS_GCC_H
AnnaBridge	167:84c0a372a020	26	#define __CMSIS_GCC_H
AnnaBridge	167:84c0a372a020	27
AnnaBridge	167:84c0a372a020	28	/* ignore some GCC warnings */
AnnaBridge	167:84c0a372a020	29	#pragma GCC diagnostic push
AnnaBridge	167:84c0a372a020	30	#pragma GCC diagnostic ignored "-Wsign-conversion"
AnnaBridge	167:84c0a372a020	31	#pragma GCC diagnostic ignored "-Wconversion"
AnnaBridge	167:84c0a372a020	32	#pragma GCC diagnostic ignored "-Wunused-parameter"
AnnaBridge	167:84c0a372a020	33
AnnaBridge	167:84c0a372a020	34	/* Fallback for __has_builtin */
AnnaBridge	167:84c0a372a020	35	#ifndef __has_builtin
AnnaBridge	167:84c0a372a020	36	#define __has_builtin(x) (0)
AnnaBridge	167:84c0a372a020	37	#endif
AnnaBridge	167:84c0a372a020	38
AnnaBridge	167:84c0a372a020	39	/* CMSIS compiler specific defines */
AnnaBridge	167:84c0a372a020	40	#ifndef __ASM
AnnaBridge	167:84c0a372a020	41	#define __ASM __asm
AnnaBridge	167:84c0a372a020	42	#endif
AnnaBridge	167:84c0a372a020	43	#ifndef __INLINE
AnnaBridge	167:84c0a372a020	44	#define __INLINE inline
AnnaBridge	167:84c0a372a020	45	#endif
AnnaBridge	167:84c0a372a020	46	#ifndef __STATIC_INLINE
AnnaBridge	167:84c0a372a020	47	#define __STATIC_INLINE static inline
AnnaBridge	167:84c0a372a020	48	#endif
AnnaBridge	167:84c0a372a020	49	#ifndef __NO_RETURN
AnnaBridge	167:84c0a372a020	50	#define __NO_RETURN __attribute__((noreturn))
AnnaBridge	167:84c0a372a020	51	#endif
AnnaBridge	167:84c0a372a020	52	#ifndef __USED
AnnaBridge	167:84c0a372a020	53	#define __USED __attribute__((used))
AnnaBridge	167:84c0a372a020	54	#endif
AnnaBridge	167:84c0a372a020	55	#ifndef __WEAK
AnnaBridge	167:84c0a372a020	56	#define __WEAK __attribute__((weak))
AnnaBridge	167:84c0a372a020	57	#endif
AnnaBridge	167:84c0a372a020	58	#ifndef __PACKED
AnnaBridge	167:84c0a372a020	59	#define __PACKED __attribute__((packed, aligned(1)))
AnnaBridge	167:84c0a372a020	60	#endif
AnnaBridge	167:84c0a372a020	61	#ifndef __PACKED_STRUCT
AnnaBridge	167:84c0a372a020	62	#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
AnnaBridge	167:84c0a372a020	63	#endif
AnnaBridge	167:84c0a372a020	64	#ifndef __PACKED_UNION
AnnaBridge	167:84c0a372a020	65	#define __PACKED_UNION union __attribute__((packed, aligned(1)))
AnnaBridge	167:84c0a372a020	66	#endif
AnnaBridge	167:84c0a372a020	67	#ifndef __UNALIGNED_UINT32 /* deprecated */
AnnaBridge	167:84c0a372a020	68	#pragma GCC diagnostic push
AnnaBridge	167:84c0a372a020	69	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	167:84c0a372a020	70	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	167:84c0a372a020	71	struct __attribute__((packed)) T_UINT32 { uint32_t v; };
AnnaBridge	167:84c0a372a020	72	#pragma GCC diagnostic pop
AnnaBridge	167:84c0a372a020	73	#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
AnnaBridge	167:84c0a372a020	74	#endif
AnnaBridge	167:84c0a372a020	75	#ifndef __UNALIGNED_UINT16_WRITE
AnnaBridge	167:84c0a372a020	76	#pragma GCC diagnostic push
AnnaBridge	167:84c0a372a020	77	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	167:84c0a372a020	78	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	167:84c0a372a020	79	__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
AnnaBridge	167:84c0a372a020	80	#pragma GCC diagnostic pop
AnnaBridge	167:84c0a372a020	81	#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE )(void )(addr))->v) = (val))
AnnaBridge	167:84c0a372a020	82	#endif
AnnaBridge	167:84c0a372a020	83	#ifndef __UNALIGNED_UINT16_READ
AnnaBridge	167:84c0a372a020	84	#pragma GCC diagnostic push
AnnaBridge	167:84c0a372a020	85	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	167:84c0a372a020	86	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	167:84c0a372a020	87	__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
AnnaBridge	167:84c0a372a020	88	#pragma GCC diagnostic pop
AnnaBridge	167:84c0a372a020	89	#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ )(const void )(addr))->v)
AnnaBridge	167:84c0a372a020	90	#endif
AnnaBridge	167:84c0a372a020	91	#ifndef __UNALIGNED_UINT32_WRITE
AnnaBridge	167:84c0a372a020	92	#pragma GCC diagnostic push
AnnaBridge	167:84c0a372a020	93	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	167:84c0a372a020	94	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	167:84c0a372a020	95	__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
AnnaBridge	167:84c0a372a020	96	#pragma GCC diagnostic pop
AnnaBridge	167:84c0a372a020	97	#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE )(void )(addr))->v) = (val))
AnnaBridge	167:84c0a372a020	98	#endif
AnnaBridge	167:84c0a372a020	99	#ifndef __UNALIGNED_UINT32_READ
AnnaBridge	167:84c0a372a020	100	#pragma GCC diagnostic push
AnnaBridge	167:84c0a372a020	101	#pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge	167:84c0a372a020	102	#pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge	167:84c0a372a020	103	__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
AnnaBridge	167:84c0a372a020	104	#pragma GCC diagnostic pop
AnnaBridge	167:84c0a372a020	105	#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ )(const void )(addr))->v)
AnnaBridge	167:84c0a372a020	106	#endif
AnnaBridge	167:84c0a372a020	107	#ifndef __ALIGNED
AnnaBridge	167:84c0a372a020	108	#define __ALIGNED(x) __attribute__((aligned(x)))
AnnaBridge	167:84c0a372a020	109	#endif
AnnaBridge	167:84c0a372a020	110	#ifndef __RESTRICT
AnnaBridge	167:84c0a372a020	111	#define __RESTRICT __restrict
AnnaBridge	167:84c0a372a020	112	#endif
AnnaBridge	167:84c0a372a020	113
AnnaBridge	167:84c0a372a020	114
AnnaBridge	167:84c0a372a020	115	/* ########################### Core Function Access ########################### */
AnnaBridge	167:84c0a372a020	116	/** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:84c0a372a020	117	\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
AnnaBridge	167:84c0a372a020	118	@{
AnnaBridge	167:84c0a372a020	119	*/
AnnaBridge	167:84c0a372a020	120
AnnaBridge	167:84c0a372a020	121	/**
AnnaBridge	167:84c0a372a020	122	\brief Enable IRQ Interrupts
AnnaBridge	167:84c0a372a020	123	\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
AnnaBridge	167:84c0a372a020	124	Can only be executed in Privileged modes.
AnnaBridge	167:84c0a372a020	125	*/
AnnaBridge	167:84c0a372a020	126	__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
AnnaBridge	167:84c0a372a020	127	{
AnnaBridge	167:84c0a372a020	128	__ASM volatile ("cpsie i" : : : "memory");
AnnaBridge	167:84c0a372a020	129	}
AnnaBridge	167:84c0a372a020	130
AnnaBridge	167:84c0a372a020	131
AnnaBridge	167:84c0a372a020	132	/**
AnnaBridge	167:84c0a372a020	133	\brief Disable IRQ Interrupts
AnnaBridge	167:84c0a372a020	134	\details Disables IRQ interrupts by setting the I-bit in the CPSR.
AnnaBridge	167:84c0a372a020	135	Can only be executed in Privileged modes.
AnnaBridge	167:84c0a372a020	136	*/
AnnaBridge	167:84c0a372a020	137	__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
AnnaBridge	167:84c0a372a020	138	{
AnnaBridge	167:84c0a372a020	139	__ASM volatile ("cpsid i" : : : "memory");
AnnaBridge	167:84c0a372a020	140	}
AnnaBridge	167:84c0a372a020	141
AnnaBridge	167:84c0a372a020	142
AnnaBridge	167:84c0a372a020	143	/**
AnnaBridge	167:84c0a372a020	144	\brief Get Control Register
AnnaBridge	167:84c0a372a020	145	\details Returns the content of the Control Register.
AnnaBridge	167:84c0a372a020	146	\return Control Register value
AnnaBridge	167:84c0a372a020	147	*/
AnnaBridge	167:84c0a372a020	148	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
AnnaBridge	167:84c0a372a020	149	{
AnnaBridge	167:84c0a372a020	150	uint32_t result;
AnnaBridge	167:84c0a372a020	151
AnnaBridge	167:84c0a372a020	152	__ASM volatile ("MRS %0, control" : "=r" (result) );
AnnaBridge	167:84c0a372a020	153	return(result);
AnnaBridge	167:84c0a372a020	154	}
AnnaBridge	167:84c0a372a020	155
AnnaBridge	167:84c0a372a020	156
AnnaBridge	167:84c0a372a020	157	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	158	/**
AnnaBridge	167:84c0a372a020	159	\brief Get Control Register (non-secure)
AnnaBridge	167:84c0a372a020	160	\details Returns the content of the non-secure Control Register when in secure mode.
AnnaBridge	167:84c0a372a020	161	\return non-secure Control Register value
AnnaBridge	167:84c0a372a020	162	*/
AnnaBridge	167:84c0a372a020	163	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
AnnaBridge	167:84c0a372a020	164	{
AnnaBridge	167:84c0a372a020	165	uint32_t result;
AnnaBridge	167:84c0a372a020	166
AnnaBridge	167:84c0a372a020	167	__ASM volatile ("MRS %0, control_ns" : "=r" (result) );
AnnaBridge	167:84c0a372a020	168	return(result);
AnnaBridge	167:84c0a372a020	169	}
AnnaBridge	167:84c0a372a020	170	#endif
AnnaBridge	167:84c0a372a020	171
AnnaBridge	167:84c0a372a020	172
AnnaBridge	167:84c0a372a020	173	/**
AnnaBridge	167:84c0a372a020	174	\brief Set Control Register
AnnaBridge	167:84c0a372a020	175	\details Writes the given value to the Control Register.
AnnaBridge	167:84c0a372a020	176	\param [in] control Control Register value to set
AnnaBridge	167:84c0a372a020	177	*/
AnnaBridge	167:84c0a372a020	178	__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
AnnaBridge	167:84c0a372a020	179	{
AnnaBridge	167:84c0a372a020	180	__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
AnnaBridge	167:84c0a372a020	181	}
AnnaBridge	167:84c0a372a020	182
AnnaBridge	167:84c0a372a020	183
AnnaBridge	167:84c0a372a020	184	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	185	/**
AnnaBridge	167:84c0a372a020	186	\brief Set Control Register (non-secure)
AnnaBridge	167:84c0a372a020	187	\details Writes the given value to the non-secure Control Register when in secure state.
AnnaBridge	167:84c0a372a020	188	\param [in] control Control Register value to set
AnnaBridge	167:84c0a372a020	189	*/
AnnaBridge	167:84c0a372a020	190	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
AnnaBridge	167:84c0a372a020	191	{
AnnaBridge	167:84c0a372a020	192	__ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
AnnaBridge	167:84c0a372a020	193	}
AnnaBridge	167:84c0a372a020	194	#endif
AnnaBridge	167:84c0a372a020	195
AnnaBridge	167:84c0a372a020	196
AnnaBridge	167:84c0a372a020	197	/**
AnnaBridge	167:84c0a372a020	198	\brief Get IPSR Register
AnnaBridge	167:84c0a372a020	199	\details Returns the content of the IPSR Register.
AnnaBridge	167:84c0a372a020	200	\return IPSR Register value
AnnaBridge	167:84c0a372a020	201	*/
AnnaBridge	167:84c0a372a020	202	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
AnnaBridge	167:84c0a372a020	203	{
AnnaBridge	167:84c0a372a020	204	uint32_t result;
AnnaBridge	167:84c0a372a020	205
AnnaBridge	167:84c0a372a020	206	__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
AnnaBridge	167:84c0a372a020	207	return(result);
AnnaBridge	167:84c0a372a020	208	}
AnnaBridge	167:84c0a372a020	209
AnnaBridge	167:84c0a372a020	210
AnnaBridge	167:84c0a372a020	211	/**
AnnaBridge	167:84c0a372a020	212	\brief Get APSR Register
AnnaBridge	167:84c0a372a020	213	\details Returns the content of the APSR Register.
AnnaBridge	167:84c0a372a020	214	\return APSR Register value
AnnaBridge	167:84c0a372a020	215	*/
AnnaBridge	167:84c0a372a020	216	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
AnnaBridge	167:84c0a372a020	217	{
AnnaBridge	167:84c0a372a020	218	uint32_t result;
AnnaBridge	167:84c0a372a020	219
AnnaBridge	167:84c0a372a020	220	__ASM volatile ("MRS %0, apsr" : "=r" (result) );
AnnaBridge	167:84c0a372a020	221	return(result);
AnnaBridge	167:84c0a372a020	222	}
AnnaBridge	167:84c0a372a020	223
AnnaBridge	167:84c0a372a020	224
AnnaBridge	167:84c0a372a020	225	/**
AnnaBridge	167:84c0a372a020	226	\brief Get xPSR Register
AnnaBridge	167:84c0a372a020	227	\details Returns the content of the xPSR Register.
AnnaBridge	167:84c0a372a020	228	\return xPSR Register value
AnnaBridge	167:84c0a372a020	229	*/
AnnaBridge	167:84c0a372a020	230	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
AnnaBridge	167:84c0a372a020	231	{
AnnaBridge	167:84c0a372a020	232	uint32_t result;
AnnaBridge	167:84c0a372a020	233
AnnaBridge	167:84c0a372a020	234	__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
AnnaBridge	167:84c0a372a020	235	return(result);
AnnaBridge	167:84c0a372a020	236	}
AnnaBridge	167:84c0a372a020	237
AnnaBridge	167:84c0a372a020	238
AnnaBridge	167:84c0a372a020	239	/**
AnnaBridge	167:84c0a372a020	240	\brief Get Process Stack Pointer
AnnaBridge	167:84c0a372a020	241	\details Returns the current value of the Process Stack Pointer (PSP).
AnnaBridge	167:84c0a372a020	242	\return PSP Register value
AnnaBridge	167:84c0a372a020	243	*/
AnnaBridge	167:84c0a372a020	244	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
AnnaBridge	167:84c0a372a020	245	{
AnnaBridge	167:84c0a372a020	246	register uint32_t result;
AnnaBridge	167:84c0a372a020	247
AnnaBridge	167:84c0a372a020	248	__ASM volatile ("MRS %0, psp" : "=r" (result) );
AnnaBridge	167:84c0a372a020	249	return(result);
AnnaBridge	167:84c0a372a020	250	}
AnnaBridge	167:84c0a372a020	251
AnnaBridge	167:84c0a372a020	252
AnnaBridge	167:84c0a372a020	253	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	254	/**
AnnaBridge	167:84c0a372a020	255	\brief Get Process Stack Pointer (non-secure)
AnnaBridge	167:84c0a372a020	256	\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge	167:84c0a372a020	257	\return PSP Register value
AnnaBridge	167:84c0a372a020	258	*/
AnnaBridge	167:84c0a372a020	259	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
AnnaBridge	167:84c0a372a020	260	{
AnnaBridge	167:84c0a372a020	261	register uint32_t result;
AnnaBridge	167:84c0a372a020	262
AnnaBridge	167:84c0a372a020	263	__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
AnnaBridge	167:84c0a372a020	264	return(result);
AnnaBridge	167:84c0a372a020	265	}
AnnaBridge	167:84c0a372a020	266	#endif
AnnaBridge	167:84c0a372a020	267
AnnaBridge	167:84c0a372a020	268
AnnaBridge	167:84c0a372a020	269	/**
AnnaBridge	167:84c0a372a020	270	\brief Set Process Stack Pointer
AnnaBridge	167:84c0a372a020	271	\details Assigns the given value to the Process Stack Pointer (PSP).
AnnaBridge	167:84c0a372a020	272	\param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge	167:84c0a372a020	273	*/
AnnaBridge	167:84c0a372a020	274	__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
AnnaBridge	167:84c0a372a020	275	{
AnnaBridge	167:84c0a372a020	276	__ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
AnnaBridge	167:84c0a372a020	277	}
AnnaBridge	167:84c0a372a020	278
AnnaBridge	167:84c0a372a020	279
AnnaBridge	167:84c0a372a020	280	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	281	/**
AnnaBridge	167:84c0a372a020	282	\brief Set Process Stack Pointer (non-secure)
AnnaBridge	167:84c0a372a020	283	\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge	167:84c0a372a020	284	\param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge	167:84c0a372a020	285	*/
AnnaBridge	167:84c0a372a020	286	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
AnnaBridge	167:84c0a372a020	287	{
AnnaBridge	167:84c0a372a020	288	__ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
AnnaBridge	167:84c0a372a020	289	}
AnnaBridge	167:84c0a372a020	290	#endif
AnnaBridge	167:84c0a372a020	291
AnnaBridge	167:84c0a372a020	292
AnnaBridge	167:84c0a372a020	293	/**
AnnaBridge	167:84c0a372a020	294	\brief Get Main Stack Pointer
AnnaBridge	167:84c0a372a020	295	\details Returns the current value of the Main Stack Pointer (MSP).
AnnaBridge	167:84c0a372a020	296	\return MSP Register value
AnnaBridge	167:84c0a372a020	297	*/
AnnaBridge	167:84c0a372a020	298	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
AnnaBridge	167:84c0a372a020	299	{
AnnaBridge	167:84c0a372a020	300	register uint32_t result;
AnnaBridge	167:84c0a372a020	301
AnnaBridge	167:84c0a372a020	302	__ASM volatile ("MRS %0, msp" : "=r" (result) );
AnnaBridge	167:84c0a372a020	303	return(result);
AnnaBridge	167:84c0a372a020	304	}
AnnaBridge	167:84c0a372a020	305
AnnaBridge	167:84c0a372a020	306
AnnaBridge	167:84c0a372a020	307	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	308	/**
AnnaBridge	167:84c0a372a020	309	\brief Get Main Stack Pointer (non-secure)
AnnaBridge	167:84c0a372a020	310	\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge	167:84c0a372a020	311	\return MSP Register value
AnnaBridge	167:84c0a372a020	312	*/
AnnaBridge	167:84c0a372a020	313	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
AnnaBridge	167:84c0a372a020	314	{
AnnaBridge	167:84c0a372a020	315	register uint32_t result;
AnnaBridge	167:84c0a372a020	316
AnnaBridge	167:84c0a372a020	317	__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
AnnaBridge	167:84c0a372a020	318	return(result);
AnnaBridge	167:84c0a372a020	319	}
AnnaBridge	167:84c0a372a020	320	#endif
AnnaBridge	167:84c0a372a020	321
AnnaBridge	167:84c0a372a020	322
AnnaBridge	167:84c0a372a020	323	/**
AnnaBridge	167:84c0a372a020	324	\brief Set Main Stack Pointer
AnnaBridge	167:84c0a372a020	325	\details Assigns the given value to the Main Stack Pointer (MSP).
AnnaBridge	167:84c0a372a020	326	\param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge	167:84c0a372a020	327	*/
AnnaBridge	167:84c0a372a020	328	__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
AnnaBridge	167:84c0a372a020	329	{
AnnaBridge	167:84c0a372a020	330	__ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
AnnaBridge	167:84c0a372a020	331	}
AnnaBridge	167:84c0a372a020	332
AnnaBridge	167:84c0a372a020	333
AnnaBridge	167:84c0a372a020	334	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	335	/**
AnnaBridge	167:84c0a372a020	336	\brief Set Main Stack Pointer (non-secure)
AnnaBridge	167:84c0a372a020	337	\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge	167:84c0a372a020	338	\param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge	167:84c0a372a020	339	*/
AnnaBridge	167:84c0a372a020	340	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
AnnaBridge	167:84c0a372a020	341	{
AnnaBridge	167:84c0a372a020	342	__ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
AnnaBridge	167:84c0a372a020	343	}
AnnaBridge	167:84c0a372a020	344	#endif
AnnaBridge	167:84c0a372a020	345
AnnaBridge	167:84c0a372a020	346
AnnaBridge	167:84c0a372a020	347	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	348	/**
AnnaBridge	167:84c0a372a020	349	\brief Get Stack Pointer (non-secure)
AnnaBridge	167:84c0a372a020	350	\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge	167:84c0a372a020	351	\return SP Register value
AnnaBridge	167:84c0a372a020	352	*/
AnnaBridge	167:84c0a372a020	353	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
AnnaBridge	167:84c0a372a020	354	{
AnnaBridge	167:84c0a372a020	355	register uint32_t result;
AnnaBridge	167:84c0a372a020	356
AnnaBridge	167:84c0a372a020	357	__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
AnnaBridge	167:84c0a372a020	358	return(result);
AnnaBridge	167:84c0a372a020	359	}
AnnaBridge	167:84c0a372a020	360
AnnaBridge	167:84c0a372a020	361
AnnaBridge	167:84c0a372a020	362	/**
AnnaBridge	167:84c0a372a020	363	\brief Set Stack Pointer (non-secure)
AnnaBridge	167:84c0a372a020	364	\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge	167:84c0a372a020	365	\param [in] topOfStack Stack Pointer value to set
AnnaBridge	167:84c0a372a020	366	*/
AnnaBridge	167:84c0a372a020	367	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
AnnaBridge	167:84c0a372a020	368	{
AnnaBridge	167:84c0a372a020	369	__ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
AnnaBridge	167:84c0a372a020	370	}
AnnaBridge	167:84c0a372a020	371	#endif
AnnaBridge	167:84c0a372a020	372
AnnaBridge	167:84c0a372a020	373
AnnaBridge	167:84c0a372a020	374	/**
AnnaBridge	167:84c0a372a020	375	\brief Get Priority Mask
AnnaBridge	167:84c0a372a020	376	\details Returns the current state of the priority mask bit from the Priority Mask Register.
AnnaBridge	167:84c0a372a020	377	\return Priority Mask value
AnnaBridge	167:84c0a372a020	378	*/
AnnaBridge	167:84c0a372a020	379	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
AnnaBridge	167:84c0a372a020	380	{
AnnaBridge	167:84c0a372a020	381	uint32_t result;
AnnaBridge	167:84c0a372a020	382
AnnaBridge	167:84c0a372a020	383	__ASM volatile ("MRS %0, primask" : "=r" (result) );
AnnaBridge	167:84c0a372a020	384	return(result);
AnnaBridge	167:84c0a372a020	385	}
AnnaBridge	167:84c0a372a020	386
AnnaBridge	167:84c0a372a020	387
AnnaBridge	167:84c0a372a020	388	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	389	/**
AnnaBridge	167:84c0a372a020	390	\brief Get Priority Mask (non-secure)
AnnaBridge	167:84c0a372a020	391	\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
AnnaBridge	167:84c0a372a020	392	\return Priority Mask value
AnnaBridge	167:84c0a372a020	393	*/
AnnaBridge	167:84c0a372a020	394	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
AnnaBridge	167:84c0a372a020	395	{
AnnaBridge	167:84c0a372a020	396	uint32_t result;
AnnaBridge	167:84c0a372a020	397
AnnaBridge	167:84c0a372a020	398	__ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
AnnaBridge	167:84c0a372a020	399	return(result);
AnnaBridge	167:84c0a372a020	400	}
AnnaBridge	167:84c0a372a020	401	#endif
AnnaBridge	167:84c0a372a020	402
AnnaBridge	167:84c0a372a020	403
AnnaBridge	167:84c0a372a020	404	/**
AnnaBridge	167:84c0a372a020	405	\brief Set Priority Mask
AnnaBridge	167:84c0a372a020	406	\details Assigns the given value to the Priority Mask Register.
AnnaBridge	167:84c0a372a020	407	\param [in] priMask Priority Mask
AnnaBridge	167:84c0a372a020	408	*/
AnnaBridge	167:84c0a372a020	409	__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
AnnaBridge	167:84c0a372a020	410	{
AnnaBridge	167:84c0a372a020	411	__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
AnnaBridge	167:84c0a372a020	412	}
AnnaBridge	167:84c0a372a020	413
AnnaBridge	167:84c0a372a020	414
AnnaBridge	167:84c0a372a020	415	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	416	/**
AnnaBridge	167:84c0a372a020	417	\brief Set Priority Mask (non-secure)
AnnaBridge	167:84c0a372a020	418	\details Assigns the given value to the non-secure Priority Mask Register when in secure state.
AnnaBridge	167:84c0a372a020	419	\param [in] priMask Priority Mask
AnnaBridge	167:84c0a372a020	420	*/
AnnaBridge	167:84c0a372a020	421	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
AnnaBridge	167:84c0a372a020	422	{
AnnaBridge	167:84c0a372a020	423	__ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
AnnaBridge	167:84c0a372a020	424	}
AnnaBridge	167:84c0a372a020	425	#endif
AnnaBridge	167:84c0a372a020	426
AnnaBridge	167:84c0a372a020	427
AnnaBridge	167:84c0a372a020	428	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	429	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	430	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	167:84c0a372a020	431	/**
AnnaBridge	167:84c0a372a020	432	\brief Enable FIQ
AnnaBridge	167:84c0a372a020	433	\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
AnnaBridge	167:84c0a372a020	434	Can only be executed in Privileged modes.
AnnaBridge	167:84c0a372a020	435	*/
AnnaBridge	167:84c0a372a020	436	__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
AnnaBridge	167:84c0a372a020	437	{
AnnaBridge	167:84c0a372a020	438	__ASM volatile ("cpsie f" : : : "memory");
AnnaBridge	167:84c0a372a020	439	}
AnnaBridge	167:84c0a372a020	440
AnnaBridge	167:84c0a372a020	441
AnnaBridge	167:84c0a372a020	442	/**
AnnaBridge	167:84c0a372a020	443	\brief Disable FIQ
AnnaBridge	167:84c0a372a020	444	\details Disables FIQ interrupts by setting the F-bit in the CPSR.
AnnaBridge	167:84c0a372a020	445	Can only be executed in Privileged modes.
AnnaBridge	167:84c0a372a020	446	*/
AnnaBridge	167:84c0a372a020	447	__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
AnnaBridge	167:84c0a372a020	448	{
AnnaBridge	167:84c0a372a020	449	__ASM volatile ("cpsid f" : : : "memory");
AnnaBridge	167:84c0a372a020	450	}
AnnaBridge	167:84c0a372a020	451
AnnaBridge	167:84c0a372a020	452
AnnaBridge	167:84c0a372a020	453	/**
AnnaBridge	167:84c0a372a020	454	\brief Get Base Priority
AnnaBridge	167:84c0a372a020	455	\details Returns the current value of the Base Priority register.
AnnaBridge	167:84c0a372a020	456	\return Base Priority register value
AnnaBridge	167:84c0a372a020	457	*/
AnnaBridge	167:84c0a372a020	458	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
AnnaBridge	167:84c0a372a020	459	{
AnnaBridge	167:84c0a372a020	460	uint32_t result;
AnnaBridge	167:84c0a372a020	461
AnnaBridge	167:84c0a372a020	462	__ASM volatile ("MRS %0, basepri" : "=r" (result) );
AnnaBridge	167:84c0a372a020	463	return(result);
AnnaBridge	167:84c0a372a020	464	}
AnnaBridge	167:84c0a372a020	465
AnnaBridge	167:84c0a372a020	466
AnnaBridge	167:84c0a372a020	467	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	468	/**
AnnaBridge	167:84c0a372a020	469	\brief Get Base Priority (non-secure)
AnnaBridge	167:84c0a372a020	470	\details Returns the current value of the non-secure Base Priority register when in secure state.
AnnaBridge	167:84c0a372a020	471	\return Base Priority register value
AnnaBridge	167:84c0a372a020	472	*/
AnnaBridge	167:84c0a372a020	473	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
AnnaBridge	167:84c0a372a020	474	{
AnnaBridge	167:84c0a372a020	475	uint32_t result;
AnnaBridge	167:84c0a372a020	476
AnnaBridge	167:84c0a372a020	477	__ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
AnnaBridge	167:84c0a372a020	478	return(result);
AnnaBridge	167:84c0a372a020	479	}
AnnaBridge	167:84c0a372a020	480	#endif
AnnaBridge	167:84c0a372a020	481
AnnaBridge	167:84c0a372a020	482
AnnaBridge	167:84c0a372a020	483	/**
AnnaBridge	167:84c0a372a020	484	\brief Set Base Priority
AnnaBridge	167:84c0a372a020	485	\details Assigns the given value to the Base Priority register.
AnnaBridge	167:84c0a372a020	486	\param [in] basePri Base Priority value to set
AnnaBridge	167:84c0a372a020	487	*/
AnnaBridge	167:84c0a372a020	488	__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
AnnaBridge	167:84c0a372a020	489	{
AnnaBridge	167:84c0a372a020	490	__ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
AnnaBridge	167:84c0a372a020	491	}
AnnaBridge	167:84c0a372a020	492
AnnaBridge	167:84c0a372a020	493
AnnaBridge	167:84c0a372a020	494	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	495	/**
AnnaBridge	167:84c0a372a020	496	\brief Set Base Priority (non-secure)
AnnaBridge	167:84c0a372a020	497	\details Assigns the given value to the non-secure Base Priority register when in secure state.
AnnaBridge	167:84c0a372a020	498	\param [in] basePri Base Priority value to set
AnnaBridge	167:84c0a372a020	499	*/
AnnaBridge	167:84c0a372a020	500	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
AnnaBridge	167:84c0a372a020	501	{
AnnaBridge	167:84c0a372a020	502	__ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
AnnaBridge	167:84c0a372a020	503	}
AnnaBridge	167:84c0a372a020	504	#endif
AnnaBridge	167:84c0a372a020	505
AnnaBridge	167:84c0a372a020	506
AnnaBridge	167:84c0a372a020	507	/**
AnnaBridge	167:84c0a372a020	508	\brief Set Base Priority with condition
AnnaBridge	167:84c0a372a020	509	\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
AnnaBridge	167:84c0a372a020	510	or the new value increases the BASEPRI priority level.
AnnaBridge	167:84c0a372a020	511	\param [in] basePri Base Priority value to set
AnnaBridge	167:84c0a372a020	512	*/
AnnaBridge	167:84c0a372a020	513	__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
AnnaBridge	167:84c0a372a020	514	{
AnnaBridge	167:84c0a372a020	515	__ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
AnnaBridge	167:84c0a372a020	516	}
AnnaBridge	167:84c0a372a020	517
AnnaBridge	167:84c0a372a020	518
AnnaBridge	167:84c0a372a020	519	/**
AnnaBridge	167:84c0a372a020	520	\brief Get Fault Mask
AnnaBridge	167:84c0a372a020	521	\details Returns the current value of the Fault Mask register.
AnnaBridge	167:84c0a372a020	522	\return Fault Mask register value
AnnaBridge	167:84c0a372a020	523	*/
AnnaBridge	167:84c0a372a020	524	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
AnnaBridge	167:84c0a372a020	525	{
AnnaBridge	167:84c0a372a020	526	uint32_t result;
AnnaBridge	167:84c0a372a020	527
AnnaBridge	167:84c0a372a020	528	__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
AnnaBridge	167:84c0a372a020	529	return(result);
AnnaBridge	167:84c0a372a020	530	}
AnnaBridge	167:84c0a372a020	531
AnnaBridge	167:84c0a372a020	532
AnnaBridge	167:84c0a372a020	533	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	534	/**
AnnaBridge	167:84c0a372a020	535	\brief Get Fault Mask (non-secure)
AnnaBridge	167:84c0a372a020	536	\details Returns the current value of the non-secure Fault Mask register when in secure state.
AnnaBridge	167:84c0a372a020	537	\return Fault Mask register value
AnnaBridge	167:84c0a372a020	538	*/
AnnaBridge	167:84c0a372a020	539	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
AnnaBridge	167:84c0a372a020	540	{
AnnaBridge	167:84c0a372a020	541	uint32_t result;
AnnaBridge	167:84c0a372a020	542
AnnaBridge	167:84c0a372a020	543	__ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
AnnaBridge	167:84c0a372a020	544	return(result);
AnnaBridge	167:84c0a372a020	545	}
AnnaBridge	167:84c0a372a020	546	#endif
AnnaBridge	167:84c0a372a020	547
AnnaBridge	167:84c0a372a020	548
AnnaBridge	167:84c0a372a020	549	/**
AnnaBridge	167:84c0a372a020	550	\brief Set Fault Mask
AnnaBridge	167:84c0a372a020	551	\details Assigns the given value to the Fault Mask register.
AnnaBridge	167:84c0a372a020	552	\param [in] faultMask Fault Mask value to set
AnnaBridge	167:84c0a372a020	553	*/
AnnaBridge	167:84c0a372a020	554	__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
AnnaBridge	167:84c0a372a020	555	{
AnnaBridge	167:84c0a372a020	556	__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
AnnaBridge	167:84c0a372a020	557	}
AnnaBridge	167:84c0a372a020	558
AnnaBridge	167:84c0a372a020	559
AnnaBridge	167:84c0a372a020	560	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge	167:84c0a372a020	561	/**
AnnaBridge	167:84c0a372a020	562	\brief Set Fault Mask (non-secure)
AnnaBridge	167:84c0a372a020	563	\details Assigns the given value to the non-secure Fault Mask register when in secure state.
AnnaBridge	167:84c0a372a020	564	\param [in] faultMask Fault Mask value to set
AnnaBridge	167:84c0a372a020	565	*/
AnnaBridge	167:84c0a372a020	566	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
AnnaBridge	167:84c0a372a020	567	{
AnnaBridge	167:84c0a372a020	568	__ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
AnnaBridge	167:84c0a372a020	569	}
AnnaBridge	167:84c0a372a020	570	#endif
AnnaBridge	167:84c0a372a020	571
AnnaBridge	167:84c0a372a020	572	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	573	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	574	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge	167:84c0a372a020	575
AnnaBridge	167:84c0a372a020	576
AnnaBridge	167:84c0a372a020	577	#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	578	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge	167:84c0a372a020	579
AnnaBridge	167:84c0a372a020	580	/**
AnnaBridge	167:84c0a372a020	581	\brief Get Process Stack Pointer Limit
AnnaBridge	167:84c0a372a020	582	\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
AnnaBridge	167:84c0a372a020	583	\return PSPLIM Register value
AnnaBridge	167:84c0a372a020	584	*/
AnnaBridge	167:84c0a372a020	585	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
AnnaBridge	167:84c0a372a020	586	{
AnnaBridge	167:84c0a372a020	587	register uint32_t result;
AnnaBridge	167:84c0a372a020	588
AnnaBridge	167:84c0a372a020	589	__ASM volatile ("MRS %0, psplim" : "=r" (result) );
AnnaBridge	167:84c0a372a020	590	return(result);
AnnaBridge	167:84c0a372a020	591	}
AnnaBridge	167:84c0a372a020	592
AnnaBridge	167:84c0a372a020	593
AnnaBridge	167:84c0a372a020	594	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge	167:84c0a372a020	595	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	167:84c0a372a020	596	/**
AnnaBridge	167:84c0a372a020	597	\brief Get Process Stack Pointer Limit (non-secure)
AnnaBridge	167:84c0a372a020	598	\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge	167:84c0a372a020	599	\return PSPLIM Register value
AnnaBridge	167:84c0a372a020	600	*/
AnnaBridge	167:84c0a372a020	601	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
AnnaBridge	167:84c0a372a020	602	{
AnnaBridge	167:84c0a372a020	603	register uint32_t result;
AnnaBridge	167:84c0a372a020	604
AnnaBridge	167:84c0a372a020	605	__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
AnnaBridge	167:84c0a372a020	606	return(result);
AnnaBridge	167:84c0a372a020	607	}
AnnaBridge	167:84c0a372a020	608	#endif
AnnaBridge	167:84c0a372a020	609
AnnaBridge	167:84c0a372a020	610
AnnaBridge	167:84c0a372a020	611	/**
AnnaBridge	167:84c0a372a020	612	\brief Set Process Stack Pointer Limit
AnnaBridge	167:84c0a372a020	613	\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
AnnaBridge	167:84c0a372a020	614	\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge	167:84c0a372a020	615	*/
AnnaBridge	167:84c0a372a020	616	__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
AnnaBridge	167:84c0a372a020	617	{
AnnaBridge	167:84c0a372a020	618	__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
AnnaBridge	167:84c0a372a020	619	}
AnnaBridge	167:84c0a372a020	620
AnnaBridge	167:84c0a372a020	621
AnnaBridge	167:84c0a372a020	622	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge	167:84c0a372a020	623	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	167:84c0a372a020	624	/**
AnnaBridge	167:84c0a372a020	625	\brief Set Process Stack Pointer (non-secure)
AnnaBridge	167:84c0a372a020	626	\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge	167:84c0a372a020	627	\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge	167:84c0a372a020	628	*/
AnnaBridge	167:84c0a372a020	629	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
AnnaBridge	167:84c0a372a020	630	{
AnnaBridge	167:84c0a372a020	631	__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
AnnaBridge	167:84c0a372a020	632	}
AnnaBridge	167:84c0a372a020	633	#endif
AnnaBridge	167:84c0a372a020	634
AnnaBridge	167:84c0a372a020	635
AnnaBridge	167:84c0a372a020	636	/**
AnnaBridge	167:84c0a372a020	637	\brief Get Main Stack Pointer Limit
AnnaBridge	167:84c0a372a020	638	\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
AnnaBridge	167:84c0a372a020	639	\return MSPLIM Register value
AnnaBridge	167:84c0a372a020	640	*/
AnnaBridge	167:84c0a372a020	641	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
AnnaBridge	167:84c0a372a020	642	{
AnnaBridge	167:84c0a372a020	643	register uint32_t result;
AnnaBridge	167:84c0a372a020	644
AnnaBridge	167:84c0a372a020	645	__ASM volatile ("MRS %0, msplim" : "=r" (result) );
AnnaBridge	167:84c0a372a020	646
AnnaBridge	167:84c0a372a020	647	return(result);
AnnaBridge	167:84c0a372a020	648	}
AnnaBridge	167:84c0a372a020	649
AnnaBridge	167:84c0a372a020	650
AnnaBridge	167:84c0a372a020	651	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge	167:84c0a372a020	652	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	167:84c0a372a020	653	/**
AnnaBridge	167:84c0a372a020	654	\brief Get Main Stack Pointer Limit (non-secure)
AnnaBridge	167:84c0a372a020	655	\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
AnnaBridge	167:84c0a372a020	656	\return MSPLIM Register value
AnnaBridge	167:84c0a372a020	657	*/
AnnaBridge	167:84c0a372a020	658	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
AnnaBridge	167:84c0a372a020	659	{
AnnaBridge	167:84c0a372a020	660	register uint32_t result;
AnnaBridge	167:84c0a372a020	661
AnnaBridge	167:84c0a372a020	662	__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
AnnaBridge	167:84c0a372a020	663	return(result);
AnnaBridge	167:84c0a372a020	664	}
AnnaBridge	167:84c0a372a020	665	#endif
AnnaBridge	167:84c0a372a020	666
AnnaBridge	167:84c0a372a020	667
AnnaBridge	167:84c0a372a020	668	/**
AnnaBridge	167:84c0a372a020	669	\brief Set Main Stack Pointer Limit
AnnaBridge	167:84c0a372a020	670	\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
AnnaBridge	167:84c0a372a020	671	\param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
AnnaBridge	167:84c0a372a020	672	*/
AnnaBridge	167:84c0a372a020	673	__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
AnnaBridge	167:84c0a372a020	674	{
AnnaBridge	167:84c0a372a020	675	__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
AnnaBridge	167:84c0a372a020	676	}
AnnaBridge	167:84c0a372a020	677
AnnaBridge	167:84c0a372a020	678
AnnaBridge	167:84c0a372a020	679	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge	167:84c0a372a020	680	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	167:84c0a372a020	681	/**
AnnaBridge	167:84c0a372a020	682	\brief Set Main Stack Pointer Limit (non-secure)
AnnaBridge	167:84c0a372a020	683	\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
AnnaBridge	167:84c0a372a020	684	\param [in] MainStackPtrLimit Main Stack Pointer value to set
AnnaBridge	167:84c0a372a020	685	*/
AnnaBridge	167:84c0a372a020	686	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
AnnaBridge	167:84c0a372a020	687	{
AnnaBridge	167:84c0a372a020	688	__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
AnnaBridge	167:84c0a372a020	689	}
AnnaBridge	167:84c0a372a020	690	#endif
AnnaBridge	167:84c0a372a020	691
AnnaBridge	167:84c0a372a020	692	#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	693	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge	167:84c0a372a020	694
AnnaBridge	167:84c0a372a020	695
AnnaBridge	167:84c0a372a020	696	#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	697	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	167:84c0a372a020	698
AnnaBridge	167:84c0a372a020	699	/**
AnnaBridge	167:84c0a372a020	700	\brief Get FPSCR
AnnaBridge	167:84c0a372a020	701	\details Returns the current value of the Floating Point Status/Control register.
AnnaBridge	167:84c0a372a020	702	\return Floating Point Status/Control register value
AnnaBridge	167:84c0a372a020	703	*/
AnnaBridge	167:84c0a372a020	704	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
AnnaBridge	167:84c0a372a020	705	{
AnnaBridge	167:84c0a372a020	706	#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge	167:84c0a372a020	707	(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge	167:84c0a372a020	708	#if __has_builtin(__builtin_arm_get_fpscr) \|\| (__GNUC__ > 7) \|\| (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
AnnaBridge	167:84c0a372a020	709	/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
AnnaBridge	167:84c0a372a020	710	return __builtin_arm_get_fpscr();
AnnaBridge	167:84c0a372a020	711	#else
AnnaBridge	167:84c0a372a020	712	uint32_t result;
AnnaBridge	167:84c0a372a020	713
AnnaBridge	167:84c0a372a020	714	__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
AnnaBridge	167:84c0a372a020	715	return(result);
AnnaBridge	167:84c0a372a020	716	#endif
AnnaBridge	167:84c0a372a020	717	#else
AnnaBridge	167:84c0a372a020	718	return(0U);
AnnaBridge	167:84c0a372a020	719	#endif
AnnaBridge	167:84c0a372a020	720	}
AnnaBridge	167:84c0a372a020	721
AnnaBridge	167:84c0a372a020	722
AnnaBridge	167:84c0a372a020	723	/**
AnnaBridge	167:84c0a372a020	724	\brief Set FPSCR
AnnaBridge	167:84c0a372a020	725	\details Assigns the given value to the Floating Point Status/Control register.
AnnaBridge	167:84c0a372a020	726	\param [in] fpscr Floating Point Status/Control value to set
AnnaBridge	167:84c0a372a020	727	*/
AnnaBridge	167:84c0a372a020	728	__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
AnnaBridge	167:84c0a372a020	729	{
AnnaBridge	167:84c0a372a020	730	#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge	167:84c0a372a020	731	(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge	167:84c0a372a020	732	#if __has_builtin(__builtin_arm_set_fpscr) \|\| (__GNUC__ > 7) \|\| (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
AnnaBridge	167:84c0a372a020	733	/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
AnnaBridge	167:84c0a372a020	734	__builtin_arm_set_fpscr(fpscr);
AnnaBridge	167:84c0a372a020	735	#else
AnnaBridge	167:84c0a372a020	736	__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
AnnaBridge	167:84c0a372a020	737	#endif
AnnaBridge	167:84c0a372a020	738	#else
AnnaBridge	167:84c0a372a020	739	(void)fpscr;
AnnaBridge	167:84c0a372a020	740	#endif
AnnaBridge	167:84c0a372a020	741	}
AnnaBridge	167:84c0a372a020	742
AnnaBridge	167:84c0a372a020	743	#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	744	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge	167:84c0a372a020	745
AnnaBridge	167:84c0a372a020	746
AnnaBridge	167:84c0a372a020	747
AnnaBridge	167:84c0a372a020	748	/@} end of CMSIS_Core_RegAccFunctions /
AnnaBridge	167:84c0a372a020	749
AnnaBridge	167:84c0a372a020	750
AnnaBridge	167:84c0a372a020	751	/* ########################## Core Instruction Access ######################### */
AnnaBridge	167:84c0a372a020	752	/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
AnnaBridge	167:84c0a372a020	753	Access to dedicated instructions
AnnaBridge	167:84c0a372a020	754	@{
AnnaBridge	167:84c0a372a020	755	*/
AnnaBridge	167:84c0a372a020	756
AnnaBridge	167:84c0a372a020	757	/* Define macros for porting to both thumb1 and thumb2.
AnnaBridge	167:84c0a372a020	758	* For thumb1, use low register (r0-r7), specified by constraint "l"
AnnaBridge	167:84c0a372a020	759	* Otherwise, use general registers, specified by constraint "r" */
AnnaBridge	167:84c0a372a020	760	#if defined (__thumb__) && !defined (__thumb2__)
AnnaBridge	167:84c0a372a020	761	#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
AnnaBridge	167:84c0a372a020	762	#define __CMSIS_GCC_RW_REG(r) "+l" (r)
AnnaBridge	167:84c0a372a020	763	#define __CMSIS_GCC_USE_REG(r) "l" (r)
AnnaBridge	167:84c0a372a020	764	#else
AnnaBridge	167:84c0a372a020	765	#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
AnnaBridge	167:84c0a372a020	766	#define __CMSIS_GCC_RW_REG(r) "+r" (r)
AnnaBridge	167:84c0a372a020	767	#define __CMSIS_GCC_USE_REG(r) "r" (r)
AnnaBridge	167:84c0a372a020	768	#endif
AnnaBridge	167:84c0a372a020	769
AnnaBridge	167:84c0a372a020	770	/**
AnnaBridge	167:84c0a372a020	771	\brief No Operation
AnnaBridge	167:84c0a372a020	772	\details No Operation does nothing. This instruction can be used for code alignment purposes.
AnnaBridge	167:84c0a372a020	773	*/
AnnaBridge	167:84c0a372a020	774	//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
AnnaBridge	167:84c0a372a020	775	//{
AnnaBridge	167:84c0a372a020	776	// __ASM volatile ("nop");
AnnaBridge	167:84c0a372a020	777	//}
AnnaBridge	167:84c0a372a020	778	#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */
AnnaBridge	167:84c0a372a020	779
AnnaBridge	167:84c0a372a020	780	/**
AnnaBridge	167:84c0a372a020	781	\brief Wait For Interrupt
AnnaBridge	167:84c0a372a020	782	\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
AnnaBridge	167:84c0a372a020	783	*/
AnnaBridge	167:84c0a372a020	784	//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
AnnaBridge	167:84c0a372a020	785	//{
AnnaBridge	167:84c0a372a020	786	// __ASM volatile ("wfi");
AnnaBridge	167:84c0a372a020	787	//}
AnnaBridge	167:84c0a372a020	788	#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */
AnnaBridge	167:84c0a372a020	789
AnnaBridge	167:84c0a372a020	790
AnnaBridge	167:84c0a372a020	791	/**
AnnaBridge	167:84c0a372a020	792	\brief Wait For Event
AnnaBridge	167:84c0a372a020	793	\details Wait For Event is a hint instruction that permits the processor to enter
AnnaBridge	167:84c0a372a020	794	a low-power state until one of a number of events occurs.
AnnaBridge	167:84c0a372a020	795	*/
AnnaBridge	167:84c0a372a020	796	//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
AnnaBridge	167:84c0a372a020	797	//{
AnnaBridge	167:84c0a372a020	798	// __ASM volatile ("wfe");
AnnaBridge	167:84c0a372a020	799	//}
AnnaBridge	167:84c0a372a020	800	#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */
AnnaBridge	167:84c0a372a020	801
AnnaBridge	167:84c0a372a020	802
AnnaBridge	167:84c0a372a020	803	/**
AnnaBridge	167:84c0a372a020	804	\brief Send Event
AnnaBridge	167:84c0a372a020	805	\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
AnnaBridge	167:84c0a372a020	806	*/
AnnaBridge	167:84c0a372a020	807	//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
AnnaBridge	167:84c0a372a020	808	//{
AnnaBridge	167:84c0a372a020	809	// __ASM volatile ("sev");
AnnaBridge	167:84c0a372a020	810	//}
AnnaBridge	167:84c0a372a020	811	#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */
AnnaBridge	167:84c0a372a020	812
AnnaBridge	167:84c0a372a020	813
AnnaBridge	167:84c0a372a020	814	/**
AnnaBridge	167:84c0a372a020	815	\brief Instruction Synchronization Barrier
AnnaBridge	167:84c0a372a020	816	\details Instruction Synchronization Barrier flushes the pipeline in the processor,
AnnaBridge	167:84c0a372a020	817	so that all instructions following the ISB are fetched from cache or memory,
AnnaBridge	167:84c0a372a020	818	after the instruction has been completed.
AnnaBridge	167:84c0a372a020	819	*/
AnnaBridge	167:84c0a372a020	820	__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
AnnaBridge	167:84c0a372a020	821	{
AnnaBridge	167:84c0a372a020	822	__ASM volatile ("isb 0xF":::"memory");
AnnaBridge	167:84c0a372a020	823	}
AnnaBridge	167:84c0a372a020	824
AnnaBridge	167:84c0a372a020	825
AnnaBridge	167:84c0a372a020	826	/**
AnnaBridge	167:84c0a372a020	827	\brief Data Synchronization Barrier
AnnaBridge	167:84c0a372a020	828	\details Acts as a special kind of Data Memory Barrier.
AnnaBridge	167:84c0a372a020	829	It completes when all explicit memory accesses before this instruction complete.
AnnaBridge	167:84c0a372a020	830	*/
AnnaBridge	167:84c0a372a020	831	__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
AnnaBridge	167:84c0a372a020	832	{
AnnaBridge	167:84c0a372a020	833	__ASM volatile ("dsb 0xF":::"memory");
AnnaBridge	167:84c0a372a020	834	}
AnnaBridge	167:84c0a372a020	835
AnnaBridge	167:84c0a372a020	836
AnnaBridge	167:84c0a372a020	837	/**
AnnaBridge	167:84c0a372a020	838	\brief Data Memory Barrier
AnnaBridge	167:84c0a372a020	839	\details Ensures the apparent order of the explicit memory operations before
AnnaBridge	167:84c0a372a020	840	and after the instruction, without ensuring their completion.
AnnaBridge	167:84c0a372a020	841	*/
AnnaBridge	167:84c0a372a020	842	__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
AnnaBridge	167:84c0a372a020	843	{
AnnaBridge	167:84c0a372a020	844	__ASM volatile ("dmb 0xF":::"memory");
AnnaBridge	167:84c0a372a020	845	}
AnnaBridge	167:84c0a372a020	846
AnnaBridge	167:84c0a372a020	847
AnnaBridge	167:84c0a372a020	848	/**
AnnaBridge	167:84c0a372a020	849	\brief Reverse byte order (32 bit)
AnnaBridge	167:84c0a372a020	850	\details Reverses the byte order in unsigned integer value.
AnnaBridge	167:84c0a372a020	851	\param [in] value Value to reverse
AnnaBridge	167:84c0a372a020	852	\return Reversed value
AnnaBridge	167:84c0a372a020	853	*/
AnnaBridge	167:84c0a372a020	854	__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
AnnaBridge	167:84c0a372a020	855	{
AnnaBridge	167:84c0a372a020	856	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
AnnaBridge	167:84c0a372a020	857	return __builtin_bswap32(value);
AnnaBridge	167:84c0a372a020	858	#else
AnnaBridge	167:84c0a372a020	859	uint32_t result;
AnnaBridge	167:84c0a372a020	860
AnnaBridge	167:84c0a372a020	861	__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge	167:84c0a372a020	862	return(result);
AnnaBridge	167:84c0a372a020	863	#endif
AnnaBridge	167:84c0a372a020	864	}
AnnaBridge	167:84c0a372a020	865
AnnaBridge	167:84c0a372a020	866
AnnaBridge	167:84c0a372a020	867	/**
AnnaBridge	167:84c0a372a020	868	\brief Reverse byte order (16 bit)
AnnaBridge	167:84c0a372a020	869	\details Reverses the byte order in unsigned short value.
AnnaBridge	167:84c0a372a020	870	\param [in] value Value to reverse
AnnaBridge	167:84c0a372a020	871	\return Reversed value
AnnaBridge	167:84c0a372a020	872	*/
AnnaBridge	167:84c0a372a020	873	__attribute__((always_inline)) __STATIC_INLINE uint16_t __REV16(uint16_t value)
AnnaBridge	167:84c0a372a020	874	{
AnnaBridge	167:84c0a372a020	875	uint16_t result;
AnnaBridge	167:84c0a372a020	876
AnnaBridge	167:84c0a372a020	877	__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge	167:84c0a372a020	878	return(result);
AnnaBridge	167:84c0a372a020	879	}
AnnaBridge	167:84c0a372a020	880
AnnaBridge	167:84c0a372a020	881
AnnaBridge	167:84c0a372a020	882	/**
AnnaBridge	167:84c0a372a020	883	\brief Reverse byte order in signed short value
AnnaBridge	167:84c0a372a020	884	\details Reverses the byte order in a signed short value with sign extension to integer.
AnnaBridge	167:84c0a372a020	885	\param [in] value Value to reverse
AnnaBridge	167:84c0a372a020	886	\return Reversed value
AnnaBridge	167:84c0a372a020	887	*/
AnnaBridge	167:84c0a372a020	888	__attribute__((always_inline)) __STATIC_INLINE int16_t __REVSH(int16_t value)
AnnaBridge	167:84c0a372a020	889	{
AnnaBridge	167:84c0a372a020	890	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	167:84c0a372a020	891	return (int16_t)__builtin_bswap16(value);
AnnaBridge	167:84c0a372a020	892	#else
AnnaBridge	167:84c0a372a020	893	int16_t result;
AnnaBridge	167:84c0a372a020	894
AnnaBridge	167:84c0a372a020	895	__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge	167:84c0a372a020	896	return result;
AnnaBridge	167:84c0a372a020	897	#endif
AnnaBridge	167:84c0a372a020	898	}
AnnaBridge	167:84c0a372a020	899
AnnaBridge	167:84c0a372a020	900
AnnaBridge	167:84c0a372a020	901	/**
AnnaBridge	167:84c0a372a020	902	\brief Rotate Right in unsigned value (32 bit)
AnnaBridge	167:84c0a372a020	903	\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
AnnaBridge	167:84c0a372a020	904	\param [in] op1 Value to rotate
AnnaBridge	167:84c0a372a020	905	\param [in] op2 Number of Bits to rotate
AnnaBridge	167:84c0a372a020	906	\return Rotated value
AnnaBridge	167:84c0a372a020	907	*/
AnnaBridge	167:84c0a372a020	908	__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	909	{
AnnaBridge	167:84c0a372a020	910	return (op1 >> op2) \| (op1 << (32U - op2));
AnnaBridge	167:84c0a372a020	911	}
AnnaBridge	167:84c0a372a020	912
AnnaBridge	167:84c0a372a020	913
AnnaBridge	167:84c0a372a020	914	/**
AnnaBridge	167:84c0a372a020	915	\brief Breakpoint
AnnaBridge	167:84c0a372a020	916	\details Causes the processor to enter Debug state.
AnnaBridge	167:84c0a372a020	917	Debug tools can use this to investigate system state when the instruction at a particular address is reached.
AnnaBridge	167:84c0a372a020	918	\param [in] value is ignored by the processor.
AnnaBridge	167:84c0a372a020	919	If required, a debugger can use it to store additional information about the breakpoint.
AnnaBridge	167:84c0a372a020	920	*/
AnnaBridge	167:84c0a372a020	921	#define __BKPT(value) __ASM volatile ("bkpt "#value)
AnnaBridge	167:84c0a372a020	922
AnnaBridge	167:84c0a372a020	923
AnnaBridge	167:84c0a372a020	924	/**
AnnaBridge	167:84c0a372a020	925	\brief Reverse bit order of value
AnnaBridge	167:84c0a372a020	926	\details Reverses the bit order of the given value.
AnnaBridge	167:84c0a372a020	927	\param [in] value Value to reverse
AnnaBridge	167:84c0a372a020	928	\return Reversed value
AnnaBridge	167:84c0a372a020	929	*/
AnnaBridge	167:84c0a372a020	930	__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
AnnaBridge	167:84c0a372a020	931	{
AnnaBridge	167:84c0a372a020	932	uint32_t result;
AnnaBridge	167:84c0a372a020	933
AnnaBridge	167:84c0a372a020	934	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	935	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	936	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	167:84c0a372a020	937	__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
AnnaBridge	167:84c0a372a020	938	#else
AnnaBridge	167:84c0a372a020	939	uint32_t s = (4U /sizeof(v)/ * 8U) - 1U; /* extra shift needed at end */
AnnaBridge	167:84c0a372a020	940
AnnaBridge	167:84c0a372a020	941	result = value; /* r will be reversed bits of v; first get LSB of v */
AnnaBridge	167:84c0a372a020	942	for (value >>= 1U; value != 0U; value >>= 1U)
AnnaBridge	167:84c0a372a020	943	{
AnnaBridge	167:84c0a372a020	944	result <<= 1U;
AnnaBridge	167:84c0a372a020	945	result \|= value & 1U;
AnnaBridge	167:84c0a372a020	946	s--;
AnnaBridge	167:84c0a372a020	947	}
AnnaBridge	167:84c0a372a020	948	result <<= s; /* shift when v's highest bits are zero */
AnnaBridge	167:84c0a372a020	949	#endif
AnnaBridge	167:84c0a372a020	950	return result;
AnnaBridge	167:84c0a372a020	951	}
AnnaBridge	167:84c0a372a020	952
AnnaBridge	167:84c0a372a020	953
AnnaBridge	167:84c0a372a020	954	/**
AnnaBridge	167:84c0a372a020	955	\brief Count leading zeros
AnnaBridge	167:84c0a372a020	956	\details Counts the number of leading zeros of a data value.
AnnaBridge	167:84c0a372a020	957	\param [in] value Value to count the leading zeros
AnnaBridge	167:84c0a372a020	958	\return number of leading zeros in value
AnnaBridge	167:84c0a372a020	959	*/
AnnaBridge	167:84c0a372a020	960	#define __CLZ __builtin_clz
AnnaBridge	167:84c0a372a020	961
AnnaBridge	167:84c0a372a020	962
AnnaBridge	167:84c0a372a020	963	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	964	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	965	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	966	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge	167:84c0a372a020	967	/**
AnnaBridge	167:84c0a372a020	968	\brief LDR Exclusive (8 bit)
AnnaBridge	167:84c0a372a020	969	\details Executes a exclusive LDR instruction for 8 bit value.
AnnaBridge	167:84c0a372a020	970	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	971	\return value of type uint8_t at (*ptr)
AnnaBridge	167:84c0a372a020	972	*/
AnnaBridge	167:84c0a372a020	973	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
AnnaBridge	167:84c0a372a020	974	{
AnnaBridge	167:84c0a372a020	975	uint32_t result;
AnnaBridge	167:84c0a372a020	976
AnnaBridge	167:84c0a372a020	977	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	167:84c0a372a020	978	__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge	167:84c0a372a020	979	#else
AnnaBridge	167:84c0a372a020	980	/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge	167:84c0a372a020	981	accepted by assembler. So has to use following less efficient pattern.
AnnaBridge	167:84c0a372a020	982	*/
AnnaBridge	167:84c0a372a020	983	__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
AnnaBridge	167:84c0a372a020	984	#endif
AnnaBridge	167:84c0a372a020	985	return ((uint8_t) result); /* Add explicit type cast here */
AnnaBridge	167:84c0a372a020	986	}
AnnaBridge	167:84c0a372a020	987
AnnaBridge	167:84c0a372a020	988
AnnaBridge	167:84c0a372a020	989	/**
AnnaBridge	167:84c0a372a020	990	\brief LDR Exclusive (16 bit)
AnnaBridge	167:84c0a372a020	991	\details Executes a exclusive LDR instruction for 16 bit values.
AnnaBridge	167:84c0a372a020	992	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	993	\return value of type uint16_t at (*ptr)
AnnaBridge	167:84c0a372a020	994	*/
AnnaBridge	167:84c0a372a020	995	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
AnnaBridge	167:84c0a372a020	996	{
AnnaBridge	167:84c0a372a020	997	uint32_t result;
AnnaBridge	167:84c0a372a020	998
AnnaBridge	167:84c0a372a020	999	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	167:84c0a372a020	1000	__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge	167:84c0a372a020	1001	#else
AnnaBridge	167:84c0a372a020	1002	/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge	167:84c0a372a020	1003	accepted by assembler. So has to use following less efficient pattern.
AnnaBridge	167:84c0a372a020	1004	*/
AnnaBridge	167:84c0a372a020	1005	__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
AnnaBridge	167:84c0a372a020	1006	#endif
AnnaBridge	167:84c0a372a020	1007	return ((uint16_t) result); /* Add explicit type cast here */
AnnaBridge	167:84c0a372a020	1008	}
AnnaBridge	167:84c0a372a020	1009
AnnaBridge	167:84c0a372a020	1010
AnnaBridge	167:84c0a372a020	1011	/**
AnnaBridge	167:84c0a372a020	1012	\brief LDR Exclusive (32 bit)
AnnaBridge	167:84c0a372a020	1013	\details Executes a exclusive LDR instruction for 32 bit values.
AnnaBridge	167:84c0a372a020	1014	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	1015	\return value of type uint32_t at (*ptr)
AnnaBridge	167:84c0a372a020	1016	*/
AnnaBridge	167:84c0a372a020	1017	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
AnnaBridge	167:84c0a372a020	1018	{
AnnaBridge	167:84c0a372a020	1019	uint32_t result;
AnnaBridge	167:84c0a372a020	1020
AnnaBridge	167:84c0a372a020	1021	__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge	167:84c0a372a020	1022	return(result);
AnnaBridge	167:84c0a372a020	1023	}
AnnaBridge	167:84c0a372a020	1024
AnnaBridge	167:84c0a372a020	1025
AnnaBridge	167:84c0a372a020	1026	/**
AnnaBridge	167:84c0a372a020	1027	\brief STR Exclusive (8 bit)
AnnaBridge	167:84c0a372a020	1028	\details Executes a exclusive STR instruction for 8 bit values.
AnnaBridge	167:84c0a372a020	1029	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	1030	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	1031	\return 0 Function succeeded
AnnaBridge	167:84c0a372a020	1032	\return 1 Function failed
AnnaBridge	167:84c0a372a020	1033	*/
AnnaBridge	167:84c0a372a020	1034	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
AnnaBridge	167:84c0a372a020	1035	{
AnnaBridge	167:84c0a372a020	1036	uint32_t result;
AnnaBridge	167:84c0a372a020	1037
AnnaBridge	167:84c0a372a020	1038	__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
AnnaBridge	167:84c0a372a020	1039	return(result);
AnnaBridge	167:84c0a372a020	1040	}
AnnaBridge	167:84c0a372a020	1041
AnnaBridge	167:84c0a372a020	1042
AnnaBridge	167:84c0a372a020	1043	/**
AnnaBridge	167:84c0a372a020	1044	\brief STR Exclusive (16 bit)
AnnaBridge	167:84c0a372a020	1045	\details Executes a exclusive STR instruction for 16 bit values.
AnnaBridge	167:84c0a372a020	1046	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	1047	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	1048	\return 0 Function succeeded
AnnaBridge	167:84c0a372a020	1049	\return 1 Function failed
AnnaBridge	167:84c0a372a020	1050	*/
AnnaBridge	167:84c0a372a020	1051	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
AnnaBridge	167:84c0a372a020	1052	{
AnnaBridge	167:84c0a372a020	1053	uint32_t result;
AnnaBridge	167:84c0a372a020	1054
AnnaBridge	167:84c0a372a020	1055	__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
AnnaBridge	167:84c0a372a020	1056	return(result);
AnnaBridge	167:84c0a372a020	1057	}
AnnaBridge	167:84c0a372a020	1058
AnnaBridge	167:84c0a372a020	1059
AnnaBridge	167:84c0a372a020	1060	/**
AnnaBridge	167:84c0a372a020	1061	\brief STR Exclusive (32 bit)
AnnaBridge	167:84c0a372a020	1062	\details Executes a exclusive STR instruction for 32 bit values.
AnnaBridge	167:84c0a372a020	1063	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	1064	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	1065	\return 0 Function succeeded
AnnaBridge	167:84c0a372a020	1066	\return 1 Function failed
AnnaBridge	167:84c0a372a020	1067	*/
AnnaBridge	167:84c0a372a020	1068	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
AnnaBridge	167:84c0a372a020	1069	{
AnnaBridge	167:84c0a372a020	1070	uint32_t result;
AnnaBridge	167:84c0a372a020	1071
AnnaBridge	167:84c0a372a020	1072	__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
AnnaBridge	167:84c0a372a020	1073	return(result);
AnnaBridge	167:84c0a372a020	1074	}
AnnaBridge	167:84c0a372a020	1075
AnnaBridge	167:84c0a372a020	1076
AnnaBridge	167:84c0a372a020	1077	/**
AnnaBridge	167:84c0a372a020	1078	\brief Remove the exclusive lock
AnnaBridge	167:84c0a372a020	1079	\details Removes the exclusive lock which is created by LDREX.
AnnaBridge	167:84c0a372a020	1080	*/
AnnaBridge	167:84c0a372a020	1081	__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
AnnaBridge	167:84c0a372a020	1082	{
AnnaBridge	167:84c0a372a020	1083	__ASM volatile ("clrex" ::: "memory");
AnnaBridge	167:84c0a372a020	1084	}
AnnaBridge	167:84c0a372a020	1085
AnnaBridge	167:84c0a372a020	1086	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	1087	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	1088	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	1089	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge	167:84c0a372a020	1090
AnnaBridge	167:84c0a372a020	1091
AnnaBridge	167:84c0a372a020	1092	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	1093	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	1094	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge	167:84c0a372a020	1095	/**
AnnaBridge	167:84c0a372a020	1096	\brief Signed Saturate
AnnaBridge	167:84c0a372a020	1097	\details Saturates a signed value.
AnnaBridge	167:84c0a372a020	1098	\param [in] ARG1 Value to be saturated
AnnaBridge	167:84c0a372a020	1099	\param [in] ARG2 Bit position to saturate to (1..32)
AnnaBridge	167:84c0a372a020	1100	\return Saturated value
AnnaBridge	167:84c0a372a020	1101	*/
AnnaBridge	167:84c0a372a020	1102	#define __SSAT(ARG1,ARG2) \
AnnaBridge	167:84c0a372a020	1103	__extension__ \
AnnaBridge	167:84c0a372a020	1104	({ \
AnnaBridge	167:84c0a372a020	1105	int32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	167:84c0a372a020	1106	__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	167:84c0a372a020	1107	__RES; \
AnnaBridge	167:84c0a372a020	1108	})
AnnaBridge	167:84c0a372a020	1109
AnnaBridge	167:84c0a372a020	1110
AnnaBridge	167:84c0a372a020	1111	/**
AnnaBridge	167:84c0a372a020	1112	\brief Unsigned Saturate
AnnaBridge	167:84c0a372a020	1113	\details Saturates an unsigned value.
AnnaBridge	167:84c0a372a020	1114	\param [in] ARG1 Value to be saturated
AnnaBridge	167:84c0a372a020	1115	\param [in] ARG2 Bit position to saturate to (0..31)
AnnaBridge	167:84c0a372a020	1116	\return Saturated value
AnnaBridge	167:84c0a372a020	1117	*/
AnnaBridge	167:84c0a372a020	1118	#define __USAT(ARG1,ARG2) \
AnnaBridge	167:84c0a372a020	1119	__extension__ \
AnnaBridge	167:84c0a372a020	1120	({ \
AnnaBridge	167:84c0a372a020	1121	uint32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	167:84c0a372a020	1122	__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	167:84c0a372a020	1123	__RES; \
AnnaBridge	167:84c0a372a020	1124	})
AnnaBridge	167:84c0a372a020	1125
AnnaBridge	167:84c0a372a020	1126
AnnaBridge	167:84c0a372a020	1127	/**
AnnaBridge	167:84c0a372a020	1128	\brief Rotate Right with Extend (32 bit)
AnnaBridge	167:84c0a372a020	1129	\details Moves each bit of a bitstring right by one bit.
AnnaBridge	167:84c0a372a020	1130	The carry input is shifted in at the left end of the bitstring.
AnnaBridge	167:84c0a372a020	1131	\param [in] value Value to rotate
AnnaBridge	167:84c0a372a020	1132	\return Rotated value
AnnaBridge	167:84c0a372a020	1133	*/
AnnaBridge	167:84c0a372a020	1134	__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
AnnaBridge	167:84c0a372a020	1135	{
AnnaBridge	167:84c0a372a020	1136	uint32_t result;
AnnaBridge	167:84c0a372a020	1137
AnnaBridge	167:84c0a372a020	1138	__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge	167:84c0a372a020	1139	return(result);
AnnaBridge	167:84c0a372a020	1140	}
AnnaBridge	167:84c0a372a020	1141
AnnaBridge	167:84c0a372a020	1142
AnnaBridge	167:84c0a372a020	1143	/**
AnnaBridge	167:84c0a372a020	1144	\brief LDRT Unprivileged (8 bit)
AnnaBridge	167:84c0a372a020	1145	\details Executes a Unprivileged LDRT instruction for 8 bit value.
AnnaBridge	167:84c0a372a020	1146	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	1147	\return value of type uint8_t at (*ptr)
AnnaBridge	167:84c0a372a020	1148	*/
AnnaBridge	167:84c0a372a020	1149	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
AnnaBridge	167:84c0a372a020	1150	{
AnnaBridge	167:84c0a372a020	1151	uint32_t result;
AnnaBridge	167:84c0a372a020	1152
AnnaBridge	167:84c0a372a020	1153	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	167:84c0a372a020	1154	__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	167:84c0a372a020	1155	#else
AnnaBridge	167:84c0a372a020	1156	/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge	167:84c0a372a020	1157	accepted by assembler. So has to use following less efficient pattern.
AnnaBridge	167:84c0a372a020	1158	*/
AnnaBridge	167:84c0a372a020	1159	__ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
AnnaBridge	167:84c0a372a020	1160	#endif
AnnaBridge	167:84c0a372a020	1161	return ((uint8_t) result); /* Add explicit type cast here */
AnnaBridge	167:84c0a372a020	1162	}
AnnaBridge	167:84c0a372a020	1163
AnnaBridge	167:84c0a372a020	1164
AnnaBridge	167:84c0a372a020	1165	/**
AnnaBridge	167:84c0a372a020	1166	\brief LDRT Unprivileged (16 bit)
AnnaBridge	167:84c0a372a020	1167	\details Executes a Unprivileged LDRT instruction for 16 bit values.
AnnaBridge	167:84c0a372a020	1168	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	1169	\return value of type uint16_t at (*ptr)
AnnaBridge	167:84c0a372a020	1170	*/
AnnaBridge	167:84c0a372a020	1171	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
AnnaBridge	167:84c0a372a020	1172	{
AnnaBridge	167:84c0a372a020	1173	uint32_t result;
AnnaBridge	167:84c0a372a020	1174
AnnaBridge	167:84c0a372a020	1175	#if (__GNUC__ > 4) \|\| (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge	167:84c0a372a020	1176	__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	167:84c0a372a020	1177	#else
AnnaBridge	167:84c0a372a020	1178	/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge	167:84c0a372a020	1179	accepted by assembler. So has to use following less efficient pattern.
AnnaBridge	167:84c0a372a020	1180	*/
AnnaBridge	167:84c0a372a020	1181	__ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
AnnaBridge	167:84c0a372a020	1182	#endif
AnnaBridge	167:84c0a372a020	1183	return ((uint16_t) result); /* Add explicit type cast here */
AnnaBridge	167:84c0a372a020	1184	}
AnnaBridge	167:84c0a372a020	1185
AnnaBridge	167:84c0a372a020	1186
AnnaBridge	167:84c0a372a020	1187	/**
AnnaBridge	167:84c0a372a020	1188	\brief LDRT Unprivileged (32 bit)
AnnaBridge	167:84c0a372a020	1189	\details Executes a Unprivileged LDRT instruction for 32 bit values.
AnnaBridge	167:84c0a372a020	1190	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	1191	\return value of type uint32_t at (*ptr)
AnnaBridge	167:84c0a372a020	1192	*/
AnnaBridge	167:84c0a372a020	1193	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
AnnaBridge	167:84c0a372a020	1194	{
AnnaBridge	167:84c0a372a020	1195	uint32_t result;
AnnaBridge	167:84c0a372a020	1196
AnnaBridge	167:84c0a372a020	1197	__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	167:84c0a372a020	1198	return(result);
AnnaBridge	167:84c0a372a020	1199	}
AnnaBridge	167:84c0a372a020	1200
AnnaBridge	167:84c0a372a020	1201
AnnaBridge	167:84c0a372a020	1202	/**
AnnaBridge	167:84c0a372a020	1203	\brief STRT Unprivileged (8 bit)
AnnaBridge	167:84c0a372a020	1204	\details Executes a Unprivileged STRT instruction for 8 bit values.
AnnaBridge	167:84c0a372a020	1205	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	1206	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	1207	*/
AnnaBridge	167:84c0a372a020	1208	__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
AnnaBridge	167:84c0a372a020	1209	{
AnnaBridge	167:84c0a372a020	1210	__ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	167:84c0a372a020	1211	}
AnnaBridge	167:84c0a372a020	1212
AnnaBridge	167:84c0a372a020	1213
AnnaBridge	167:84c0a372a020	1214	/**
AnnaBridge	167:84c0a372a020	1215	\brief STRT Unprivileged (16 bit)
AnnaBridge	167:84c0a372a020	1216	\details Executes a Unprivileged STRT instruction for 16 bit values.
AnnaBridge	167:84c0a372a020	1217	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	1218	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	1219	*/
AnnaBridge	167:84c0a372a020	1220	__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
AnnaBridge	167:84c0a372a020	1221	{
AnnaBridge	167:84c0a372a020	1222	__ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	167:84c0a372a020	1223	}
AnnaBridge	167:84c0a372a020	1224
AnnaBridge	167:84c0a372a020	1225
AnnaBridge	167:84c0a372a020	1226	/**
AnnaBridge	167:84c0a372a020	1227	\brief STRT Unprivileged (32 bit)
AnnaBridge	167:84c0a372a020	1228	\details Executes a Unprivileged STRT instruction for 32 bit values.
AnnaBridge	167:84c0a372a020	1229	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	1230	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	1231	*/
AnnaBridge	167:84c0a372a020	1232	__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
AnnaBridge	167:84c0a372a020	1233	{
AnnaBridge	167:84c0a372a020	1234	__ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
AnnaBridge	167:84c0a372a020	1235	}
AnnaBridge	167:84c0a372a020	1236
AnnaBridge	167:84c0a372a020	1237	#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	1238	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	1239	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge	167:84c0a372a020	1240
AnnaBridge	167:84c0a372a020	1241	/**
AnnaBridge	167:84c0a372a020	1242	\brief Signed Saturate
AnnaBridge	167:84c0a372a020	1243	\details Saturates a signed value.
AnnaBridge	167:84c0a372a020	1244	\param [in] value Value to be saturated
AnnaBridge	167:84c0a372a020	1245	\param [in] sat Bit position to saturate to (1..32)
AnnaBridge	167:84c0a372a020	1246	\return Saturated value
AnnaBridge	167:84c0a372a020	1247	*/
AnnaBridge	167:84c0a372a020	1248	__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
AnnaBridge	167:84c0a372a020	1249	{
AnnaBridge	167:84c0a372a020	1250	if ((sat >= 1U) && (sat <= 32U)) {
AnnaBridge	167:84c0a372a020	1251	const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
AnnaBridge	167:84c0a372a020	1252	const int32_t min = -1 - max ;
AnnaBridge	167:84c0a372a020	1253	if (val > max) {
AnnaBridge	167:84c0a372a020	1254	return max;
AnnaBridge	167:84c0a372a020	1255	} else if (val < min) {
AnnaBridge	167:84c0a372a020	1256	return min;
AnnaBridge	167:84c0a372a020	1257	}
AnnaBridge	167:84c0a372a020	1258	}
AnnaBridge	167:84c0a372a020	1259	return val;
AnnaBridge	167:84c0a372a020	1260	}
AnnaBridge	167:84c0a372a020	1261
AnnaBridge	167:84c0a372a020	1262	/**
AnnaBridge	167:84c0a372a020	1263	\brief Unsigned Saturate
AnnaBridge	167:84c0a372a020	1264	\details Saturates an unsigned value.
AnnaBridge	167:84c0a372a020	1265	\param [in] value Value to be saturated
AnnaBridge	167:84c0a372a020	1266	\param [in] sat Bit position to saturate to (0..31)
AnnaBridge	167:84c0a372a020	1267	\return Saturated value
AnnaBridge	167:84c0a372a020	1268	*/
AnnaBridge	167:84c0a372a020	1269	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
AnnaBridge	167:84c0a372a020	1270	{
AnnaBridge	167:84c0a372a020	1271	if (sat <= 31U) {
AnnaBridge	167:84c0a372a020	1272	const uint32_t max = ((1U << sat) - 1U);
AnnaBridge	167:84c0a372a020	1273	if (val > (int32_t)max) {
AnnaBridge	167:84c0a372a020	1274	return max;
AnnaBridge	167:84c0a372a020	1275	} else if (val < 0) {
AnnaBridge	167:84c0a372a020	1276	return 0U;
AnnaBridge	167:84c0a372a020	1277	}
AnnaBridge	167:84c0a372a020	1278	}
AnnaBridge	167:84c0a372a020	1279	return (uint32_t)val;
AnnaBridge	167:84c0a372a020	1280	}
AnnaBridge	167:84c0a372a020	1281
AnnaBridge	167:84c0a372a020	1282	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	1283	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	1284	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge	167:84c0a372a020	1285
AnnaBridge	167:84c0a372a020	1286
AnnaBridge	167:84c0a372a020	1287	#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	1288	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge	167:84c0a372a020	1289	/**
AnnaBridge	167:84c0a372a020	1290	\brief Load-Acquire (8 bit)
AnnaBridge	167:84c0a372a020	1291	\details Executes a LDAB instruction for 8 bit value.
AnnaBridge	167:84c0a372a020	1292	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	1293	\return value of type uint8_t at (*ptr)
AnnaBridge	167:84c0a372a020	1294	*/
AnnaBridge	167:84c0a372a020	1295	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
AnnaBridge	167:84c0a372a020	1296	{
AnnaBridge	167:84c0a372a020	1297	uint32_t result;
AnnaBridge	167:84c0a372a020	1298
AnnaBridge	167:84c0a372a020	1299	__ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	167:84c0a372a020	1300	return ((uint8_t) result);
AnnaBridge	167:84c0a372a020	1301	}
AnnaBridge	167:84c0a372a020	1302
AnnaBridge	167:84c0a372a020	1303
AnnaBridge	167:84c0a372a020	1304	/**
AnnaBridge	167:84c0a372a020	1305	\brief Load-Acquire (16 bit)
AnnaBridge	167:84c0a372a020	1306	\details Executes a LDAH instruction for 16 bit values.
AnnaBridge	167:84c0a372a020	1307	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	1308	\return value of type uint16_t at (*ptr)
AnnaBridge	167:84c0a372a020	1309	*/
AnnaBridge	167:84c0a372a020	1310	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
AnnaBridge	167:84c0a372a020	1311	{
AnnaBridge	167:84c0a372a020	1312	uint32_t result;
AnnaBridge	167:84c0a372a020	1313
AnnaBridge	167:84c0a372a020	1314	__ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	167:84c0a372a020	1315	return ((uint16_t) result);
AnnaBridge	167:84c0a372a020	1316	}
AnnaBridge	167:84c0a372a020	1317
AnnaBridge	167:84c0a372a020	1318
AnnaBridge	167:84c0a372a020	1319	/**
AnnaBridge	167:84c0a372a020	1320	\brief Load-Acquire (32 bit)
AnnaBridge	167:84c0a372a020	1321	\details Executes a LDA instruction for 32 bit values.
AnnaBridge	167:84c0a372a020	1322	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	1323	\return value of type uint32_t at (*ptr)
AnnaBridge	167:84c0a372a020	1324	*/
AnnaBridge	167:84c0a372a020	1325	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
AnnaBridge	167:84c0a372a020	1326	{
AnnaBridge	167:84c0a372a020	1327	uint32_t result;
AnnaBridge	167:84c0a372a020	1328
AnnaBridge	167:84c0a372a020	1329	__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	167:84c0a372a020	1330	return(result);
AnnaBridge	167:84c0a372a020	1331	}
AnnaBridge	167:84c0a372a020	1332
AnnaBridge	167:84c0a372a020	1333
AnnaBridge	167:84c0a372a020	1334	/**
AnnaBridge	167:84c0a372a020	1335	\brief Store-Release (8 bit)
AnnaBridge	167:84c0a372a020	1336	\details Executes a STLB instruction for 8 bit values.
AnnaBridge	167:84c0a372a020	1337	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	1338	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	1339	*/
AnnaBridge	167:84c0a372a020	1340	__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
AnnaBridge	167:84c0a372a020	1341	{
AnnaBridge	167:84c0a372a020	1342	__ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	167:84c0a372a020	1343	}
AnnaBridge	167:84c0a372a020	1344
AnnaBridge	167:84c0a372a020	1345
AnnaBridge	167:84c0a372a020	1346	/**
AnnaBridge	167:84c0a372a020	1347	\brief Store-Release (16 bit)
AnnaBridge	167:84c0a372a020	1348	\details Executes a STLH instruction for 16 bit values.
AnnaBridge	167:84c0a372a020	1349	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	1350	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	1351	*/
AnnaBridge	167:84c0a372a020	1352	__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
AnnaBridge	167:84c0a372a020	1353	{
AnnaBridge	167:84c0a372a020	1354	__ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	167:84c0a372a020	1355	}
AnnaBridge	167:84c0a372a020	1356
AnnaBridge	167:84c0a372a020	1357
AnnaBridge	167:84c0a372a020	1358	/**
AnnaBridge	167:84c0a372a020	1359	\brief Store-Release (32 bit)
AnnaBridge	167:84c0a372a020	1360	\details Executes a STL instruction for 32 bit values.
AnnaBridge	167:84c0a372a020	1361	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	1362	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	1363	*/
AnnaBridge	167:84c0a372a020	1364	__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
AnnaBridge	167:84c0a372a020	1365	{
AnnaBridge	167:84c0a372a020	1366	__ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	167:84c0a372a020	1367	}
AnnaBridge	167:84c0a372a020	1368
AnnaBridge	167:84c0a372a020	1369
AnnaBridge	167:84c0a372a020	1370	/**
AnnaBridge	167:84c0a372a020	1371	\brief Load-Acquire Exclusive (8 bit)
AnnaBridge	167:84c0a372a020	1372	\details Executes a LDAB exclusive instruction for 8 bit value.
AnnaBridge	167:84c0a372a020	1373	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	1374	\return value of type uint8_t at (*ptr)
AnnaBridge	167:84c0a372a020	1375	*/
AnnaBridge	167:84c0a372a020	1376	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
AnnaBridge	167:84c0a372a020	1377	{
AnnaBridge	167:84c0a372a020	1378	uint32_t result;
AnnaBridge	167:84c0a372a020	1379
AnnaBridge	167:84c0a372a020	1380	__ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	167:84c0a372a020	1381	return ((uint8_t) result);
AnnaBridge	167:84c0a372a020	1382	}
AnnaBridge	167:84c0a372a020	1383
AnnaBridge	167:84c0a372a020	1384
AnnaBridge	167:84c0a372a020	1385	/**
AnnaBridge	167:84c0a372a020	1386	\brief Load-Acquire Exclusive (16 bit)
AnnaBridge	167:84c0a372a020	1387	\details Executes a LDAH exclusive instruction for 16 bit values.
AnnaBridge	167:84c0a372a020	1388	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	1389	\return value of type uint16_t at (*ptr)
AnnaBridge	167:84c0a372a020	1390	*/
AnnaBridge	167:84c0a372a020	1391	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
AnnaBridge	167:84c0a372a020	1392	{
AnnaBridge	167:84c0a372a020	1393	uint32_t result;
AnnaBridge	167:84c0a372a020	1394
AnnaBridge	167:84c0a372a020	1395	__ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	167:84c0a372a020	1396	return ((uint16_t) result);
AnnaBridge	167:84c0a372a020	1397	}
AnnaBridge	167:84c0a372a020	1398
AnnaBridge	167:84c0a372a020	1399
AnnaBridge	167:84c0a372a020	1400	/**
AnnaBridge	167:84c0a372a020	1401	\brief Load-Acquire Exclusive (32 bit)
AnnaBridge	167:84c0a372a020	1402	\details Executes a LDA exclusive instruction for 32 bit values.
AnnaBridge	167:84c0a372a020	1403	\param [in] ptr Pointer to data
AnnaBridge	167:84c0a372a020	1404	\return value of type uint32_t at (*ptr)
AnnaBridge	167:84c0a372a020	1405	*/
AnnaBridge	167:84c0a372a020	1406	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr)
AnnaBridge	167:84c0a372a020	1407	{
AnnaBridge	167:84c0a372a020	1408	uint32_t result;
AnnaBridge	167:84c0a372a020	1409
AnnaBridge	167:84c0a372a020	1410	__ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge	167:84c0a372a020	1411	return(result);
AnnaBridge	167:84c0a372a020	1412	}
AnnaBridge	167:84c0a372a020	1413
AnnaBridge	167:84c0a372a020	1414
AnnaBridge	167:84c0a372a020	1415	/**
AnnaBridge	167:84c0a372a020	1416	\brief Store-Release Exclusive (8 bit)
AnnaBridge	167:84c0a372a020	1417	\details Executes a STLB exclusive instruction for 8 bit values.
AnnaBridge	167:84c0a372a020	1418	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	1419	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	1420	\return 0 Function succeeded
AnnaBridge	167:84c0a372a020	1421	\return 1 Function failed
AnnaBridge	167:84c0a372a020	1422	*/
AnnaBridge	167:84c0a372a020	1423	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
AnnaBridge	167:84c0a372a020	1424	{
AnnaBridge	167:84c0a372a020	1425	uint32_t result;
AnnaBridge	167:84c0a372a020	1426
AnnaBridge	167:84c0a372a020	1427	__ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	167:84c0a372a020	1428	return(result);
AnnaBridge	167:84c0a372a020	1429	}
AnnaBridge	167:84c0a372a020	1430
AnnaBridge	167:84c0a372a020	1431
AnnaBridge	167:84c0a372a020	1432	/**
AnnaBridge	167:84c0a372a020	1433	\brief Store-Release Exclusive (16 bit)
AnnaBridge	167:84c0a372a020	1434	\details Executes a STLH exclusive instruction for 16 bit values.
AnnaBridge	167:84c0a372a020	1435	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	1436	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	1437	\return 0 Function succeeded
AnnaBridge	167:84c0a372a020	1438	\return 1 Function failed
AnnaBridge	167:84c0a372a020	1439	*/
AnnaBridge	167:84c0a372a020	1440	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
AnnaBridge	167:84c0a372a020	1441	{
AnnaBridge	167:84c0a372a020	1442	uint32_t result;
AnnaBridge	167:84c0a372a020	1443
AnnaBridge	167:84c0a372a020	1444	__ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	167:84c0a372a020	1445	return(result);
AnnaBridge	167:84c0a372a020	1446	}
AnnaBridge	167:84c0a372a020	1447
AnnaBridge	167:84c0a372a020	1448
AnnaBridge	167:84c0a372a020	1449	/**
AnnaBridge	167:84c0a372a020	1450	\brief Store-Release Exclusive (32 bit)
AnnaBridge	167:84c0a372a020	1451	\details Executes a STL exclusive instruction for 32 bit values.
AnnaBridge	167:84c0a372a020	1452	\param [in] value Value to store
AnnaBridge	167:84c0a372a020	1453	\param [in] ptr Pointer to location
AnnaBridge	167:84c0a372a020	1454	\return 0 Function succeeded
AnnaBridge	167:84c0a372a020	1455	\return 1 Function failed
AnnaBridge	167:84c0a372a020	1456	*/
AnnaBridge	167:84c0a372a020	1457	__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
AnnaBridge	167:84c0a372a020	1458	{
AnnaBridge	167:84c0a372a020	1459	uint32_t result;
AnnaBridge	167:84c0a372a020	1460
AnnaBridge	167:84c0a372a020	1461	__ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge	167:84c0a372a020	1462	return(result);
AnnaBridge	167:84c0a372a020	1463	}
AnnaBridge	167:84c0a372a020	1464
AnnaBridge	167:84c0a372a020	1465	#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
AnnaBridge	167:84c0a372a020	1466	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge	167:84c0a372a020	1467
AnnaBridge	167:84c0a372a020	1468	/@}/ /* end of group CMSIS_Core_InstructionInterface */
AnnaBridge	167:84c0a372a020	1469
AnnaBridge	167:84c0a372a020	1470
AnnaBridge	167:84c0a372a020	1471	/* ################### Compiler specific Intrinsics ########################### */
AnnaBridge	167:84c0a372a020	1472	/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
AnnaBridge	167:84c0a372a020	1473	Access to dedicated SIMD instructions
AnnaBridge	167:84c0a372a020	1474	@{
AnnaBridge	167:84c0a372a020	1475	*/
AnnaBridge	167:84c0a372a020	1476
AnnaBridge	167:84c0a372a020	1477	#if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
AnnaBridge	167:84c0a372a020	1478
AnnaBridge	167:84c0a372a020	1479	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1480	{
AnnaBridge	167:84c0a372a020	1481	uint32_t result;
AnnaBridge	167:84c0a372a020	1482
AnnaBridge	167:84c0a372a020	1483	__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1484	return(result);
AnnaBridge	167:84c0a372a020	1485	}
AnnaBridge	167:84c0a372a020	1486
AnnaBridge	167:84c0a372a020	1487	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1488	{
AnnaBridge	167:84c0a372a020	1489	uint32_t result;
AnnaBridge	167:84c0a372a020	1490
AnnaBridge	167:84c0a372a020	1491	__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1492	return(result);
AnnaBridge	167:84c0a372a020	1493	}
AnnaBridge	167:84c0a372a020	1494
AnnaBridge	167:84c0a372a020	1495	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1496	{
AnnaBridge	167:84c0a372a020	1497	uint32_t result;
AnnaBridge	167:84c0a372a020	1498
AnnaBridge	167:84c0a372a020	1499	__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1500	return(result);
AnnaBridge	167:84c0a372a020	1501	}
AnnaBridge	167:84c0a372a020	1502
AnnaBridge	167:84c0a372a020	1503	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1504	{
AnnaBridge	167:84c0a372a020	1505	uint32_t result;
AnnaBridge	167:84c0a372a020	1506
AnnaBridge	167:84c0a372a020	1507	__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1508	return(result);
AnnaBridge	167:84c0a372a020	1509	}
AnnaBridge	167:84c0a372a020	1510
AnnaBridge	167:84c0a372a020	1511	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1512	{
AnnaBridge	167:84c0a372a020	1513	uint32_t result;
AnnaBridge	167:84c0a372a020	1514
AnnaBridge	167:84c0a372a020	1515	__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1516	return(result);
AnnaBridge	167:84c0a372a020	1517	}
AnnaBridge	167:84c0a372a020	1518
AnnaBridge	167:84c0a372a020	1519	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1520	{
AnnaBridge	167:84c0a372a020	1521	uint32_t result;
AnnaBridge	167:84c0a372a020	1522
AnnaBridge	167:84c0a372a020	1523	__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1524	return(result);
AnnaBridge	167:84c0a372a020	1525	}
AnnaBridge	167:84c0a372a020	1526
AnnaBridge	167:84c0a372a020	1527
AnnaBridge	167:84c0a372a020	1528	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1529	{
AnnaBridge	167:84c0a372a020	1530	uint32_t result;
AnnaBridge	167:84c0a372a020	1531
AnnaBridge	167:84c0a372a020	1532	__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1533	return(result);
AnnaBridge	167:84c0a372a020	1534	}
AnnaBridge	167:84c0a372a020	1535
AnnaBridge	167:84c0a372a020	1536	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1537	{
AnnaBridge	167:84c0a372a020	1538	uint32_t result;
AnnaBridge	167:84c0a372a020	1539
AnnaBridge	167:84c0a372a020	1540	__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1541	return(result);
AnnaBridge	167:84c0a372a020	1542	}
AnnaBridge	167:84c0a372a020	1543
AnnaBridge	167:84c0a372a020	1544	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1545	{
AnnaBridge	167:84c0a372a020	1546	uint32_t result;
AnnaBridge	167:84c0a372a020	1547
AnnaBridge	167:84c0a372a020	1548	__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1549	return(result);
AnnaBridge	167:84c0a372a020	1550	}
AnnaBridge	167:84c0a372a020	1551
AnnaBridge	167:84c0a372a020	1552	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1553	{
AnnaBridge	167:84c0a372a020	1554	uint32_t result;
AnnaBridge	167:84c0a372a020	1555
AnnaBridge	167:84c0a372a020	1556	__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1557	return(result);
AnnaBridge	167:84c0a372a020	1558	}
AnnaBridge	167:84c0a372a020	1559
AnnaBridge	167:84c0a372a020	1560	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1561	{
AnnaBridge	167:84c0a372a020	1562	uint32_t result;
AnnaBridge	167:84c0a372a020	1563
AnnaBridge	167:84c0a372a020	1564	__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1565	return(result);
AnnaBridge	167:84c0a372a020	1566	}
AnnaBridge	167:84c0a372a020	1567
AnnaBridge	167:84c0a372a020	1568	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1569	{
AnnaBridge	167:84c0a372a020	1570	uint32_t result;
AnnaBridge	167:84c0a372a020	1571
AnnaBridge	167:84c0a372a020	1572	__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1573	return(result);
AnnaBridge	167:84c0a372a020	1574	}
AnnaBridge	167:84c0a372a020	1575
AnnaBridge	167:84c0a372a020	1576
AnnaBridge	167:84c0a372a020	1577	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1578	{
AnnaBridge	167:84c0a372a020	1579	uint32_t result;
AnnaBridge	167:84c0a372a020	1580
AnnaBridge	167:84c0a372a020	1581	__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1582	return(result);
AnnaBridge	167:84c0a372a020	1583	}
AnnaBridge	167:84c0a372a020	1584
AnnaBridge	167:84c0a372a020	1585	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1586	{
AnnaBridge	167:84c0a372a020	1587	uint32_t result;
AnnaBridge	167:84c0a372a020	1588
AnnaBridge	167:84c0a372a020	1589	__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1590	return(result);
AnnaBridge	167:84c0a372a020	1591	}
AnnaBridge	167:84c0a372a020	1592
AnnaBridge	167:84c0a372a020	1593	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1594	{
AnnaBridge	167:84c0a372a020	1595	uint32_t result;
AnnaBridge	167:84c0a372a020	1596
AnnaBridge	167:84c0a372a020	1597	__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1598	return(result);
AnnaBridge	167:84c0a372a020	1599	}
AnnaBridge	167:84c0a372a020	1600
AnnaBridge	167:84c0a372a020	1601	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1602	{
AnnaBridge	167:84c0a372a020	1603	uint32_t result;
AnnaBridge	167:84c0a372a020	1604
AnnaBridge	167:84c0a372a020	1605	__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1606	return(result);
AnnaBridge	167:84c0a372a020	1607	}
AnnaBridge	167:84c0a372a020	1608
AnnaBridge	167:84c0a372a020	1609	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1610	{
AnnaBridge	167:84c0a372a020	1611	uint32_t result;
AnnaBridge	167:84c0a372a020	1612
AnnaBridge	167:84c0a372a020	1613	__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1614	return(result);
AnnaBridge	167:84c0a372a020	1615	}
AnnaBridge	167:84c0a372a020	1616
AnnaBridge	167:84c0a372a020	1617	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1618	{
AnnaBridge	167:84c0a372a020	1619	uint32_t result;
AnnaBridge	167:84c0a372a020	1620
AnnaBridge	167:84c0a372a020	1621	__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1622	return(result);
AnnaBridge	167:84c0a372a020	1623	}
AnnaBridge	167:84c0a372a020	1624
AnnaBridge	167:84c0a372a020	1625	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1626	{
AnnaBridge	167:84c0a372a020	1627	uint32_t result;
AnnaBridge	167:84c0a372a020	1628
AnnaBridge	167:84c0a372a020	1629	__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1630	return(result);
AnnaBridge	167:84c0a372a020	1631	}
AnnaBridge	167:84c0a372a020	1632
AnnaBridge	167:84c0a372a020	1633	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1634	{
AnnaBridge	167:84c0a372a020	1635	uint32_t result;
AnnaBridge	167:84c0a372a020	1636
AnnaBridge	167:84c0a372a020	1637	__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1638	return(result);
AnnaBridge	167:84c0a372a020	1639	}
AnnaBridge	167:84c0a372a020	1640
AnnaBridge	167:84c0a372a020	1641	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1642	{
AnnaBridge	167:84c0a372a020	1643	uint32_t result;
AnnaBridge	167:84c0a372a020	1644
AnnaBridge	167:84c0a372a020	1645	__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1646	return(result);
AnnaBridge	167:84c0a372a020	1647	}
AnnaBridge	167:84c0a372a020	1648
AnnaBridge	167:84c0a372a020	1649	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1650	{
AnnaBridge	167:84c0a372a020	1651	uint32_t result;
AnnaBridge	167:84c0a372a020	1652
AnnaBridge	167:84c0a372a020	1653	__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1654	return(result);
AnnaBridge	167:84c0a372a020	1655	}
AnnaBridge	167:84c0a372a020	1656
AnnaBridge	167:84c0a372a020	1657	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1658	{
AnnaBridge	167:84c0a372a020	1659	uint32_t result;
AnnaBridge	167:84c0a372a020	1660
AnnaBridge	167:84c0a372a020	1661	__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1662	return(result);
AnnaBridge	167:84c0a372a020	1663	}
AnnaBridge	167:84c0a372a020	1664
AnnaBridge	167:84c0a372a020	1665	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1666	{
AnnaBridge	167:84c0a372a020	1667	uint32_t result;
AnnaBridge	167:84c0a372a020	1668
AnnaBridge	167:84c0a372a020	1669	__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1670	return(result);
AnnaBridge	167:84c0a372a020	1671	}
AnnaBridge	167:84c0a372a020	1672
AnnaBridge	167:84c0a372a020	1673	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1674	{
AnnaBridge	167:84c0a372a020	1675	uint32_t result;
AnnaBridge	167:84c0a372a020	1676
AnnaBridge	167:84c0a372a020	1677	__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1678	return(result);
AnnaBridge	167:84c0a372a020	1679	}
AnnaBridge	167:84c0a372a020	1680
AnnaBridge	167:84c0a372a020	1681	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1682	{
AnnaBridge	167:84c0a372a020	1683	uint32_t result;
AnnaBridge	167:84c0a372a020	1684
AnnaBridge	167:84c0a372a020	1685	__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1686	return(result);
AnnaBridge	167:84c0a372a020	1687	}
AnnaBridge	167:84c0a372a020	1688
AnnaBridge	167:84c0a372a020	1689	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1690	{
AnnaBridge	167:84c0a372a020	1691	uint32_t result;
AnnaBridge	167:84c0a372a020	1692
AnnaBridge	167:84c0a372a020	1693	__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1694	return(result);
AnnaBridge	167:84c0a372a020	1695	}
AnnaBridge	167:84c0a372a020	1696
AnnaBridge	167:84c0a372a020	1697	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1698	{
AnnaBridge	167:84c0a372a020	1699	uint32_t result;
AnnaBridge	167:84c0a372a020	1700
AnnaBridge	167:84c0a372a020	1701	__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1702	return(result);
AnnaBridge	167:84c0a372a020	1703	}
AnnaBridge	167:84c0a372a020	1704
AnnaBridge	167:84c0a372a020	1705	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1706	{
AnnaBridge	167:84c0a372a020	1707	uint32_t result;
AnnaBridge	167:84c0a372a020	1708
AnnaBridge	167:84c0a372a020	1709	__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1710	return(result);
AnnaBridge	167:84c0a372a020	1711	}
AnnaBridge	167:84c0a372a020	1712
AnnaBridge	167:84c0a372a020	1713	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1714	{
AnnaBridge	167:84c0a372a020	1715	uint32_t result;
AnnaBridge	167:84c0a372a020	1716
AnnaBridge	167:84c0a372a020	1717	__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1718	return(result);
AnnaBridge	167:84c0a372a020	1719	}
AnnaBridge	167:84c0a372a020	1720
AnnaBridge	167:84c0a372a020	1721	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1722	{
AnnaBridge	167:84c0a372a020	1723	uint32_t result;
AnnaBridge	167:84c0a372a020	1724
AnnaBridge	167:84c0a372a020	1725	__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1726	return(result);
AnnaBridge	167:84c0a372a020	1727	}
AnnaBridge	167:84c0a372a020	1728
AnnaBridge	167:84c0a372a020	1729	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1730	{
AnnaBridge	167:84c0a372a020	1731	uint32_t result;
AnnaBridge	167:84c0a372a020	1732
AnnaBridge	167:84c0a372a020	1733	__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1734	return(result);
AnnaBridge	167:84c0a372a020	1735	}
AnnaBridge	167:84c0a372a020	1736
AnnaBridge	167:84c0a372a020	1737	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1738	{
AnnaBridge	167:84c0a372a020	1739	uint32_t result;
AnnaBridge	167:84c0a372a020	1740
AnnaBridge	167:84c0a372a020	1741	__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1742	return(result);
AnnaBridge	167:84c0a372a020	1743	}
AnnaBridge	167:84c0a372a020	1744
AnnaBridge	167:84c0a372a020	1745	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1746	{
AnnaBridge	167:84c0a372a020	1747	uint32_t result;
AnnaBridge	167:84c0a372a020	1748
AnnaBridge	167:84c0a372a020	1749	__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1750	return(result);
AnnaBridge	167:84c0a372a020	1751	}
AnnaBridge	167:84c0a372a020	1752
AnnaBridge	167:84c0a372a020	1753	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1754	{
AnnaBridge	167:84c0a372a020	1755	uint32_t result;
AnnaBridge	167:84c0a372a020	1756
AnnaBridge	167:84c0a372a020	1757	__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1758	return(result);
AnnaBridge	167:84c0a372a020	1759	}
AnnaBridge	167:84c0a372a020	1760
AnnaBridge	167:84c0a372a020	1761	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1762	{
AnnaBridge	167:84c0a372a020	1763	uint32_t result;
AnnaBridge	167:84c0a372a020	1764
AnnaBridge	167:84c0a372a020	1765	__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1766	return(result);
AnnaBridge	167:84c0a372a020	1767	}
AnnaBridge	167:84c0a372a020	1768
AnnaBridge	167:84c0a372a020	1769	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1770	{
AnnaBridge	167:84c0a372a020	1771	uint32_t result;
AnnaBridge	167:84c0a372a020	1772
AnnaBridge	167:84c0a372a020	1773	__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1774	return(result);
AnnaBridge	167:84c0a372a020	1775	}
AnnaBridge	167:84c0a372a020	1776
AnnaBridge	167:84c0a372a020	1777	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	167:84c0a372a020	1778	{
AnnaBridge	167:84c0a372a020	1779	uint32_t result;
AnnaBridge	167:84c0a372a020	1780
AnnaBridge	167:84c0a372a020	1781	__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	167:84c0a372a020	1782	return(result);
AnnaBridge	167:84c0a372a020	1783	}
AnnaBridge	167:84c0a372a020	1784
AnnaBridge	167:84c0a372a020	1785	#define __SSAT16(ARG1,ARG2) \
AnnaBridge	167:84c0a372a020	1786	({ \
AnnaBridge	167:84c0a372a020	1787	int32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	167:84c0a372a020	1788	__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	167:84c0a372a020	1789	__RES; \
AnnaBridge	167:84c0a372a020	1790	})
AnnaBridge	167:84c0a372a020	1791
AnnaBridge	167:84c0a372a020	1792	#define __USAT16(ARG1,ARG2) \
AnnaBridge	167:84c0a372a020	1793	({ \
AnnaBridge	167:84c0a372a020	1794	uint32_t __RES, __ARG1 = (ARG1); \
AnnaBridge	167:84c0a372a020	1795	__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge	167:84c0a372a020	1796	__RES; \
AnnaBridge	167:84c0a372a020	1797	})
AnnaBridge	167:84c0a372a020	1798
AnnaBridge	167:84c0a372a020	1799	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
AnnaBridge	167:84c0a372a020	1800	{
AnnaBridge	167:84c0a372a020	1801	uint32_t result;
AnnaBridge	167:84c0a372a020	1802
AnnaBridge	167:84c0a372a020	1803	__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge	167:84c0a372a020	1804	return(result);
AnnaBridge	167:84c0a372a020	1805	}
AnnaBridge	167:84c0a372a020	1806
AnnaBridge	167:84c0a372a020	1807	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1808	{
AnnaBridge	167:84c0a372a020	1809	uint32_t result;
AnnaBridge	167:84c0a372a020	1810
AnnaBridge	167:84c0a372a020	1811	__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1812	return(result);
AnnaBridge	167:84c0a372a020	1813	}
AnnaBridge	167:84c0a372a020	1814
AnnaBridge	167:84c0a372a020	1815	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
AnnaBridge	167:84c0a372a020	1816	{
AnnaBridge	167:84c0a372a020	1817	uint32_t result;
AnnaBridge	167:84c0a372a020	1818
AnnaBridge	167:84c0a372a020	1819	__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge	167:84c0a372a020	1820	return(result);
AnnaBridge	167:84c0a372a020	1821	}
AnnaBridge	167:84c0a372a020	1822
AnnaBridge	167:84c0a372a020	1823	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1824	{
AnnaBridge	167:84c0a372a020	1825	uint32_t result;
AnnaBridge	167:84c0a372a020	1826
AnnaBridge	167:84c0a372a020	1827	__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1828	return(result);
AnnaBridge	167:84c0a372a020	1829	}
AnnaBridge	167:84c0a372a020	1830
AnnaBridge	167:84c0a372a020	1831	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1832	{
AnnaBridge	167:84c0a372a020	1833	uint32_t result;
AnnaBridge	167:84c0a372a020	1834
AnnaBridge	167:84c0a372a020	1835	__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1836	return(result);
AnnaBridge	167:84c0a372a020	1837	}
AnnaBridge	167:84c0a372a020	1838
AnnaBridge	167:84c0a372a020	1839	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1840	{
AnnaBridge	167:84c0a372a020	1841	uint32_t result;
AnnaBridge	167:84c0a372a020	1842
AnnaBridge	167:84c0a372a020	1843	__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1844	return(result);
AnnaBridge	167:84c0a372a020	1845	}
AnnaBridge	167:84c0a372a020	1846
AnnaBridge	167:84c0a372a020	1847	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	167:84c0a372a020	1848	{
AnnaBridge	167:84c0a372a020	1849	uint32_t result;
AnnaBridge	167:84c0a372a020	1850
AnnaBridge	167:84c0a372a020	1851	__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	167:84c0a372a020	1852	return(result);
AnnaBridge	167:84c0a372a020	1853	}
AnnaBridge	167:84c0a372a020	1854
AnnaBridge	167:84c0a372a020	1855	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	167:84c0a372a020	1856	{
AnnaBridge	167:84c0a372a020	1857	uint32_t result;
AnnaBridge	167:84c0a372a020	1858
AnnaBridge	167:84c0a372a020	1859	__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	167:84c0a372a020	1860	return(result);
AnnaBridge	167:84c0a372a020	1861	}
AnnaBridge	167:84c0a372a020	1862
AnnaBridge	167:84c0a372a020	1863	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	167:84c0a372a020	1864	{
AnnaBridge	167:84c0a372a020	1865	union llreg_u{
AnnaBridge	167:84c0a372a020	1866	uint32_t w32[2];
AnnaBridge	167:84c0a372a020	1867	uint64_t w64;
AnnaBridge	167:84c0a372a020	1868	} llr;
AnnaBridge	167:84c0a372a020	1869	llr.w64 = acc;
AnnaBridge	167:84c0a372a020	1870
AnnaBridge	167:84c0a372a020	1871	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	167:84c0a372a020	1872	__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	167:84c0a372a020	1873	#else /* Big endian */
AnnaBridge	167:84c0a372a020	1874	__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	167:84c0a372a020	1875	#endif
AnnaBridge	167:84c0a372a020	1876
AnnaBridge	167:84c0a372a020	1877	return(llr.w64);
AnnaBridge	167:84c0a372a020	1878	}
AnnaBridge	167:84c0a372a020	1879
AnnaBridge	167:84c0a372a020	1880	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	167:84c0a372a020	1881	{
AnnaBridge	167:84c0a372a020	1882	union llreg_u{
AnnaBridge	167:84c0a372a020	1883	uint32_t w32[2];
AnnaBridge	167:84c0a372a020	1884	uint64_t w64;
AnnaBridge	167:84c0a372a020	1885	} llr;
AnnaBridge	167:84c0a372a020	1886	llr.w64 = acc;
AnnaBridge	167:84c0a372a020	1887
AnnaBridge	167:84c0a372a020	1888	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	167:84c0a372a020	1889	__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	167:84c0a372a020	1890	#else /* Big endian */
AnnaBridge	167:84c0a372a020	1891	__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	167:84c0a372a020	1892	#endif
AnnaBridge	167:84c0a372a020	1893
AnnaBridge	167:84c0a372a020	1894	return(llr.w64);
AnnaBridge	167:84c0a372a020	1895	}
AnnaBridge	167:84c0a372a020	1896
AnnaBridge	167:84c0a372a020	1897	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1898	{
AnnaBridge	167:84c0a372a020	1899	uint32_t result;
AnnaBridge	167:84c0a372a020	1900
AnnaBridge	167:84c0a372a020	1901	__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1902	return(result);
AnnaBridge	167:84c0a372a020	1903	}
AnnaBridge	167:84c0a372a020	1904
AnnaBridge	167:84c0a372a020	1905	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1906	{
AnnaBridge	167:84c0a372a020	1907	uint32_t result;
AnnaBridge	167:84c0a372a020	1908
AnnaBridge	167:84c0a372a020	1909	__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1910	return(result);
AnnaBridge	167:84c0a372a020	1911	}
AnnaBridge	167:84c0a372a020	1912
AnnaBridge	167:84c0a372a020	1913	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	167:84c0a372a020	1914	{
AnnaBridge	167:84c0a372a020	1915	uint32_t result;
AnnaBridge	167:84c0a372a020	1916
AnnaBridge	167:84c0a372a020	1917	__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	167:84c0a372a020	1918	return(result);
AnnaBridge	167:84c0a372a020	1919	}
AnnaBridge	167:84c0a372a020	1920
AnnaBridge	167:84c0a372a020	1921	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge	167:84c0a372a020	1922	{
AnnaBridge	167:84c0a372a020	1923	uint32_t result;
AnnaBridge	167:84c0a372a020	1924
AnnaBridge	167:84c0a372a020	1925	__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	167:84c0a372a020	1926	return(result);
AnnaBridge	167:84c0a372a020	1927	}
AnnaBridge	167:84c0a372a020	1928
AnnaBridge	167:84c0a372a020	1929	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	167:84c0a372a020	1930	{
AnnaBridge	167:84c0a372a020	1931	union llreg_u{
AnnaBridge	167:84c0a372a020	1932	uint32_t w32[2];
AnnaBridge	167:84c0a372a020	1933	uint64_t w64;
AnnaBridge	167:84c0a372a020	1934	} llr;
AnnaBridge	167:84c0a372a020	1935	llr.w64 = acc;
AnnaBridge	167:84c0a372a020	1936
AnnaBridge	167:84c0a372a020	1937	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	167:84c0a372a020	1938	__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	167:84c0a372a020	1939	#else /* Big endian */
AnnaBridge	167:84c0a372a020	1940	__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	167:84c0a372a020	1941	#endif
AnnaBridge	167:84c0a372a020	1942
AnnaBridge	167:84c0a372a020	1943	return(llr.w64);
AnnaBridge	167:84c0a372a020	1944	}
AnnaBridge	167:84c0a372a020	1945
AnnaBridge	167:84c0a372a020	1946	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge	167:84c0a372a020	1947	{
AnnaBridge	167:84c0a372a020	1948	union llreg_u{
AnnaBridge	167:84c0a372a020	1949	uint32_t w32[2];
AnnaBridge	167:84c0a372a020	1950	uint64_t w64;
AnnaBridge	167:84c0a372a020	1951	} llr;
AnnaBridge	167:84c0a372a020	1952	llr.w64 = acc;
AnnaBridge	167:84c0a372a020	1953
AnnaBridge	167:84c0a372a020	1954	#ifndef __ARMEB__ /* Little endian */
AnnaBridge	167:84c0a372a020	1955	__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge	167:84c0a372a020	1956	#else /* Big endian */
AnnaBridge	167:84c0a372a020	1957	__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge	167:84c0a372a020	1958	#endif
AnnaBridge	167:84c0a372a020	1959
AnnaBridge	167:84c0a372a020	1960	return(llr.w64);
AnnaBridge	167:84c0a372a020	1961	}
AnnaBridge	167:84c0a372a020	1962
AnnaBridge	167:84c0a372a020	1963	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
AnnaBridge	167:84c0a372a020	1964	{
AnnaBridge	167:84c0a372a020	1965	uint32_t result;
AnnaBridge	167:84c0a372a020	1966
AnnaBridge	167:84c0a372a020	1967	__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1968	return(result);
AnnaBridge	167:84c0a372a020	1969	}
AnnaBridge	167:84c0a372a020	1970
AnnaBridge	167:84c0a372a020	1971	__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
AnnaBridge	167:84c0a372a020	1972	{
AnnaBridge	167:84c0a372a020	1973	int32_t result;
AnnaBridge	167:84c0a372a020	1974
AnnaBridge	167:84c0a372a020	1975	__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1976	return(result);
AnnaBridge	167:84c0a372a020	1977	}
AnnaBridge	167:84c0a372a020	1978
AnnaBridge	167:84c0a372a020	1979	__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
AnnaBridge	167:84c0a372a020	1980	{
AnnaBridge	167:84c0a372a020	1981	int32_t result;
AnnaBridge	167:84c0a372a020	1982
AnnaBridge	167:84c0a372a020	1983	__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge	167:84c0a372a020	1984	return(result);
AnnaBridge	167:84c0a372a020	1985	}
AnnaBridge	167:84c0a372a020	1986
AnnaBridge	167:84c0a372a020	1987	#if 0
AnnaBridge	167:84c0a372a020	1988	#define __PKHBT(ARG1,ARG2,ARG3) \
AnnaBridge	167:84c0a372a020	1989	({ \
AnnaBridge	167:84c0a372a020	1990	uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge	167:84c0a372a020	1991	__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge	167:84c0a372a020	1992	__RES; \
AnnaBridge	167:84c0a372a020	1993	})
AnnaBridge	167:84c0a372a020	1994
AnnaBridge	167:84c0a372a020	1995	#define __PKHTB(ARG1,ARG2,ARG3) \
AnnaBridge	167:84c0a372a020	1996	({ \
AnnaBridge	167:84c0a372a020	1997	uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge	167:84c0a372a020	1998	if (ARG3 == 0) \
AnnaBridge	167:84c0a372a020	1999	__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
AnnaBridge	167:84c0a372a020	2000	else \
AnnaBridge	167:84c0a372a020	2001	__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge	167:84c0a372a020	2002	__RES; \
AnnaBridge	167:84c0a372a020	2003	})
AnnaBridge	167:84c0a372a020	2004	#endif
AnnaBridge	167:84c0a372a020	2005
AnnaBridge	167:84c0a372a020	2006	#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) \| \
AnnaBridge	167:84c0a372a020	2007	((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
AnnaBridge	167:84c0a372a020	2008
AnnaBridge	167:84c0a372a020	2009	#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) \| \
AnnaBridge	167:84c0a372a020	2010	((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
AnnaBridge	167:84c0a372a020	2011
AnnaBridge	167:84c0a372a020	2012	__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
AnnaBridge	167:84c0a372a020	2013	{
AnnaBridge	167:84c0a372a020	2014	int32_t result;
AnnaBridge	167:84c0a372a020	2015
AnnaBridge	167:84c0a372a020	2016	__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge	167:84c0a372a020	2017	return(result);
AnnaBridge	167:84c0a372a020	2018	}
AnnaBridge	167:84c0a372a020	2019
AnnaBridge	167:84c0a372a020	2020	#endif /* (__ARM_FEATURE_DSP == 1) */
AnnaBridge	167:84c0a372a020	2021	/@} end of group CMSIS_SIMD_intrinsics /
AnnaBridge	167:84c0a372a020	2022
AnnaBridge	167:84c0a372a020	2023
AnnaBridge	167:84c0a372a020	2024	#pragma GCC diagnostic pop
AnnaBridge	167:84c0a372a020	2025
AnnaBridge	167:84c0a372a020	2026	#endif /* __CMSIS_GCC_H */