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TARGET_SAKURAIO_EVB_01/core_cm4.h@159:7130f322cb7e, 2017-12-21 (annotated)

Committer:: mbed_official
Date:: Thu Dec 21 18:20:02 2017 +0000
Revision:: 159:7130f322cb7e

mbed library version 157

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	159:7130f322cb7e	1	/************************************************************************//
mbed_official	159:7130f322cb7e	2	* @file core_cm4.h
mbed_official	159:7130f322cb7e	3	* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
mbed_official	159:7130f322cb7e	4	* @version V5.0.2
mbed_official	159:7130f322cb7e	5	* @date 13. February 2017
mbed_official	159:7130f322cb7e	6	******************************************************************************/
mbed_official	159:7130f322cb7e	7	/*
mbed_official	159:7130f322cb7e	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
mbed_official	159:7130f322cb7e	9	*
mbed_official	159:7130f322cb7e	10	* SPDX-License-Identifier: Apache-2.0
mbed_official	159:7130f322cb7e	11	*
mbed_official	159:7130f322cb7e	12	* Licensed under the Apache License, Version 2.0 (the License); you may
mbed_official	159:7130f322cb7e	13	* not use this file except in compliance with the License.
mbed_official	159:7130f322cb7e	14	* You may obtain a copy of the License at
mbed_official	159:7130f322cb7e	15	*
mbed_official	159:7130f322cb7e	16	* www.apache.org/licenses/LICENSE-2.0
mbed_official	159:7130f322cb7e	17	*
mbed_official	159:7130f322cb7e	18	* Unless required by applicable law or agreed to in writing, software
mbed_official	159:7130f322cb7e	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
mbed_official	159:7130f322cb7e	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official	159:7130f322cb7e	21	* See the License for the specific language governing permissions and
mbed_official	159:7130f322cb7e	22	* limitations under the License.
mbed_official	159:7130f322cb7e	23	*/
mbed_official	159:7130f322cb7e	24
mbed_official	159:7130f322cb7e	25	#if defined ( __ICCARM__ )
mbed_official	159:7130f322cb7e	26	#pragma system_include /* treat file as system include file for MISRA check */
mbed_official	159:7130f322cb7e	27	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
mbed_official	159:7130f322cb7e	28	#pragma clang system_header /* treat file as system include file */
mbed_official	159:7130f322cb7e	29	#endif
mbed_official	159:7130f322cb7e	30
mbed_official	159:7130f322cb7e	31	#ifndef __CORE_CM4_H_GENERIC
mbed_official	159:7130f322cb7e	32	#define __CORE_CM4_H_GENERIC
mbed_official	159:7130f322cb7e	33
mbed_official	159:7130f322cb7e	34	#include <stdint.h>
mbed_official	159:7130f322cb7e	35
mbed_official	159:7130f322cb7e	36	#ifdef __cplusplus
mbed_official	159:7130f322cb7e	37	extern "C" {
mbed_official	159:7130f322cb7e	38	#endif
mbed_official	159:7130f322cb7e	39
mbed_official	159:7130f322cb7e	40	/**
mbed_official	159:7130f322cb7e	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mbed_official	159:7130f322cb7e	42	CMSIS violates the following MISRA-C:2004 rules:
mbed_official	159:7130f322cb7e	43
mbed_official	159:7130f322cb7e	44	\li Required Rule 8.5, object/function definition in header file.<br>
mbed_official	159:7130f322cb7e	45	Function definitions in header files are used to allow 'inlining'.
mbed_official	159:7130f322cb7e	46
mbed_official	159:7130f322cb7e	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mbed_official	159:7130f322cb7e	48	Unions are used for effective representation of core registers.
mbed_official	159:7130f322cb7e	49
mbed_official	159:7130f322cb7e	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
mbed_official	159:7130f322cb7e	51	Function-like macros are used to allow more efficient code.
mbed_official	159:7130f322cb7e	52	*/
mbed_official	159:7130f322cb7e	53
mbed_official	159:7130f322cb7e	54
mbed_official	159:7130f322cb7e	55	/*******************************************************************************
mbed_official	159:7130f322cb7e	56	* CMSIS definitions
mbed_official	159:7130f322cb7e	57	******************************************************************************/
mbed_official	159:7130f322cb7e	58	/**
mbed_official	159:7130f322cb7e	59	\ingroup Cortex_M4
mbed_official	159:7130f322cb7e	60	@{
mbed_official	159:7130f322cb7e	61	*/
mbed_official	159:7130f322cb7e	62
mbed_official	159:7130f322cb7e	63	/* CMSIS CM4 definitions */
mbed_official	159:7130f322cb7e	64	#define __CM4_CMSIS_VERSION_MAIN ( 5U) /!< [31:16] CMSIS HAL main version /
mbed_official	159:7130f322cb7e	65	#define __CM4_CMSIS_VERSION_SUB ( 0U) /!< [15:0] CMSIS HAL sub version /
mbed_official	159:7130f322cb7e	66	#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) \| \
mbed_official	159:7130f322cb7e	67	__CM4_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
mbed_official	159:7130f322cb7e	68
mbed_official	159:7130f322cb7e	69	#define __CORTEX_M (4U) /!< Cortex-M Core /
mbed_official	159:7130f322cb7e	70
mbed_official	159:7130f322cb7e	71	/** __FPU_USED indicates whether an FPU is used or not.
mbed_official	159:7130f322cb7e	72	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
mbed_official	159:7130f322cb7e	73	*/
mbed_official	159:7130f322cb7e	74	#if defined ( __CC_ARM )
mbed_official	159:7130f322cb7e	75	#if defined __TARGET_FPU_VFP
mbed_official	159:7130f322cb7e	76	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
mbed_official	159:7130f322cb7e	77	#define __FPU_USED 1U
mbed_official	159:7130f322cb7e	78	#else
mbed_official	159:7130f322cb7e	79	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official	159:7130f322cb7e	80	#define __FPU_USED 0U
mbed_official	159:7130f322cb7e	81	#endif
mbed_official	159:7130f322cb7e	82	#else
mbed_official	159:7130f322cb7e	83	#define __FPU_USED 0U
mbed_official	159:7130f322cb7e	84	#endif
mbed_official	159:7130f322cb7e	85
mbed_official	159:7130f322cb7e	86	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
mbed_official	159:7130f322cb7e	87	#if defined __ARM_PCS_VFP
mbed_official	159:7130f322cb7e	88	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
mbed_official	159:7130f322cb7e	89	#define __FPU_USED 1U
mbed_official	159:7130f322cb7e	90	#else
mbed_official	159:7130f322cb7e	91	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official	159:7130f322cb7e	92	#define __FPU_USED 0U
mbed_official	159:7130f322cb7e	93	#endif
mbed_official	159:7130f322cb7e	94	#else
mbed_official	159:7130f322cb7e	95	#define __FPU_USED 0U
mbed_official	159:7130f322cb7e	96	#endif
mbed_official	159:7130f322cb7e	97
mbed_official	159:7130f322cb7e	98	#elif defined ( __GNUC__ )
mbed_official	159:7130f322cb7e	99	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
mbed_official	159:7130f322cb7e	100	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
mbed_official	159:7130f322cb7e	101	#define __FPU_USED 1U
mbed_official	159:7130f322cb7e	102	#else
mbed_official	159:7130f322cb7e	103	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official	159:7130f322cb7e	104	#define __FPU_USED 0U
mbed_official	159:7130f322cb7e	105	#endif
mbed_official	159:7130f322cb7e	106	#else
mbed_official	159:7130f322cb7e	107	#define __FPU_USED 0U
mbed_official	159:7130f322cb7e	108	#endif
mbed_official	159:7130f322cb7e	109
mbed_official	159:7130f322cb7e	110	#elif defined ( __ICCARM__ )
mbed_official	159:7130f322cb7e	111	#if defined __ARMVFP__
mbed_official	159:7130f322cb7e	112	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
mbed_official	159:7130f322cb7e	113	#define __FPU_USED 1U
mbed_official	159:7130f322cb7e	114	#else
mbed_official	159:7130f322cb7e	115	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official	159:7130f322cb7e	116	#define __FPU_USED 0U
mbed_official	159:7130f322cb7e	117	#endif
mbed_official	159:7130f322cb7e	118	#else
mbed_official	159:7130f322cb7e	119	#define __FPU_USED 0U
mbed_official	159:7130f322cb7e	120	#endif
mbed_official	159:7130f322cb7e	121
mbed_official	159:7130f322cb7e	122	#elif defined ( __TI_ARM__ )
mbed_official	159:7130f322cb7e	123	#if defined __TI_VFP_SUPPORT__
mbed_official	159:7130f322cb7e	124	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
mbed_official	159:7130f322cb7e	125	#define __FPU_USED 1U
mbed_official	159:7130f322cb7e	126	#else
mbed_official	159:7130f322cb7e	127	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official	159:7130f322cb7e	128	#define __FPU_USED 0U
mbed_official	159:7130f322cb7e	129	#endif
mbed_official	159:7130f322cb7e	130	#else
mbed_official	159:7130f322cb7e	131	#define __FPU_USED 0U
mbed_official	159:7130f322cb7e	132	#endif
mbed_official	159:7130f322cb7e	133
mbed_official	159:7130f322cb7e	134	#elif defined ( __TASKING__ )
mbed_official	159:7130f322cb7e	135	#if defined __FPU_VFP__
mbed_official	159:7130f322cb7e	136	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
mbed_official	159:7130f322cb7e	137	#define __FPU_USED 1U
mbed_official	159:7130f322cb7e	138	#else
mbed_official	159:7130f322cb7e	139	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official	159:7130f322cb7e	140	#define __FPU_USED 0U
mbed_official	159:7130f322cb7e	141	#endif
mbed_official	159:7130f322cb7e	142	#else
mbed_official	159:7130f322cb7e	143	#define __FPU_USED 0U
mbed_official	159:7130f322cb7e	144	#endif
mbed_official	159:7130f322cb7e	145
mbed_official	159:7130f322cb7e	146	#elif defined ( __CSMC__ )
mbed_official	159:7130f322cb7e	147	#if ( __CSMC__ & 0x400U)
mbed_official	159:7130f322cb7e	148	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
mbed_official	159:7130f322cb7e	149	#define __FPU_USED 1U
mbed_official	159:7130f322cb7e	150	#else
mbed_official	159:7130f322cb7e	151	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official	159:7130f322cb7e	152	#define __FPU_USED 0U
mbed_official	159:7130f322cb7e	153	#endif
mbed_official	159:7130f322cb7e	154	#else
mbed_official	159:7130f322cb7e	155	#define __FPU_USED 0U
mbed_official	159:7130f322cb7e	156	#endif
mbed_official	159:7130f322cb7e	157
mbed_official	159:7130f322cb7e	158	#endif
mbed_official	159:7130f322cb7e	159
mbed_official	159:7130f322cb7e	160	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
mbed_official	159:7130f322cb7e	161
mbed_official	159:7130f322cb7e	162
mbed_official	159:7130f322cb7e	163	#ifdef __cplusplus
mbed_official	159:7130f322cb7e	164	}
mbed_official	159:7130f322cb7e	165	#endif
mbed_official	159:7130f322cb7e	166
mbed_official	159:7130f322cb7e	167	#endif /* __CORE_CM4_H_GENERIC */
mbed_official	159:7130f322cb7e	168
mbed_official	159:7130f322cb7e	169	#ifndef __CMSIS_GENERIC
mbed_official	159:7130f322cb7e	170
mbed_official	159:7130f322cb7e	171	#ifndef __CORE_CM4_H_DEPENDANT
mbed_official	159:7130f322cb7e	172	#define __CORE_CM4_H_DEPENDANT
mbed_official	159:7130f322cb7e	173
mbed_official	159:7130f322cb7e	174	#ifdef __cplusplus
mbed_official	159:7130f322cb7e	175	extern "C" {
mbed_official	159:7130f322cb7e	176	#endif
mbed_official	159:7130f322cb7e	177
mbed_official	159:7130f322cb7e	178	/* check device defines and use defaults */
mbed_official	159:7130f322cb7e	179	#if defined __CHECK_DEVICE_DEFINES
mbed_official	159:7130f322cb7e	180	#ifndef __CM4_REV
mbed_official	159:7130f322cb7e	181	#define __CM4_REV 0x0000U
mbed_official	159:7130f322cb7e	182	#warning "__CM4_REV not defined in device header file; using default!"
mbed_official	159:7130f322cb7e	183	#endif
mbed_official	159:7130f322cb7e	184
mbed_official	159:7130f322cb7e	185	#ifndef __FPU_PRESENT
mbed_official	159:7130f322cb7e	186	#define __FPU_PRESENT 0U
mbed_official	159:7130f322cb7e	187	#warning "__FPU_PRESENT not defined in device header file; using default!"
mbed_official	159:7130f322cb7e	188	#endif
mbed_official	159:7130f322cb7e	189
mbed_official	159:7130f322cb7e	190	#ifndef __MPU_PRESENT
mbed_official	159:7130f322cb7e	191	#define __MPU_PRESENT 0U
mbed_official	159:7130f322cb7e	192	#warning "__MPU_PRESENT not defined in device header file; using default!"
mbed_official	159:7130f322cb7e	193	#endif
mbed_official	159:7130f322cb7e	194
mbed_official	159:7130f322cb7e	195	#ifndef __NVIC_PRIO_BITS
mbed_official	159:7130f322cb7e	196	#define __NVIC_PRIO_BITS 3U
mbed_official	159:7130f322cb7e	197	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mbed_official	159:7130f322cb7e	198	#endif
mbed_official	159:7130f322cb7e	199
mbed_official	159:7130f322cb7e	200	#ifndef __Vendor_SysTickConfig
mbed_official	159:7130f322cb7e	201	#define __Vendor_SysTickConfig 0U
mbed_official	159:7130f322cb7e	202	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mbed_official	159:7130f322cb7e	203	#endif
mbed_official	159:7130f322cb7e	204	#endif
mbed_official	159:7130f322cb7e	205
mbed_official	159:7130f322cb7e	206	/* IO definitions (access restrictions to peripheral registers) */
mbed_official	159:7130f322cb7e	207	/**
mbed_official	159:7130f322cb7e	208	\defgroup CMSIS_glob_defs CMSIS Global Defines
mbed_official	159:7130f322cb7e	209
mbed_official	159:7130f322cb7e	210	<strong>IO Type Qualifiers</strong> are used
mbed_official	159:7130f322cb7e	211	\li to specify the access to peripheral variables.
mbed_official	159:7130f322cb7e	212	\li for automatic generation of peripheral register debug information.
mbed_official	159:7130f322cb7e	213	*/
mbed_official	159:7130f322cb7e	214	#ifdef __cplusplus
mbed_official	159:7130f322cb7e	215	#define __I volatile /!< Defines 'read only' permissions /
mbed_official	159:7130f322cb7e	216	#else
mbed_official	159:7130f322cb7e	217	#define __I volatile const /!< Defines 'read only' permissions /
mbed_official	159:7130f322cb7e	218	#endif
mbed_official	159:7130f322cb7e	219	#define __O volatile /!< Defines 'write only' permissions /
mbed_official	159:7130f322cb7e	220	#define __IO volatile /!< Defines 'read / write' permissions /
mbed_official	159:7130f322cb7e	221
mbed_official	159:7130f322cb7e	222	/* following defines should be used for structure members */
mbed_official	159:7130f322cb7e	223	#define __IM volatile const /! Defines 'read only' structure member permissions /
mbed_official	159:7130f322cb7e	224	#define __OM volatile /! Defines 'write only' structure member permissions /
mbed_official	159:7130f322cb7e	225	#define __IOM volatile /! Defines 'read / write' structure member permissions /
mbed_official	159:7130f322cb7e	226
mbed_official	159:7130f322cb7e	227	/@} end of group Cortex_M4 /
mbed_official	159:7130f322cb7e	228
mbed_official	159:7130f322cb7e	229
mbed_official	159:7130f322cb7e	230
mbed_official	159:7130f322cb7e	231	/*******************************************************************************
mbed_official	159:7130f322cb7e	232	* Register Abstraction
mbed_official	159:7130f322cb7e	233	Core Register contain:
mbed_official	159:7130f322cb7e	234	- Core Register
mbed_official	159:7130f322cb7e	235	- Core NVIC Register
mbed_official	159:7130f322cb7e	236	- Core SCB Register
mbed_official	159:7130f322cb7e	237	- Core SysTick Register
mbed_official	159:7130f322cb7e	238	- Core Debug Register
mbed_official	159:7130f322cb7e	239	- Core MPU Register
mbed_official	159:7130f322cb7e	240	- Core FPU Register
mbed_official	159:7130f322cb7e	241	******************************************************************************/
mbed_official	159:7130f322cb7e	242	/**
mbed_official	159:7130f322cb7e	243	\defgroup CMSIS_core_register Defines and Type Definitions
mbed_official	159:7130f322cb7e	244	\brief Type definitions and defines for Cortex-M processor based devices.
mbed_official	159:7130f322cb7e	245	*/
mbed_official	159:7130f322cb7e	246
mbed_official	159:7130f322cb7e	247	/**
mbed_official	159:7130f322cb7e	248	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	249	\defgroup CMSIS_CORE Status and Control Registers
mbed_official	159:7130f322cb7e	250	\brief Core Register type definitions.
mbed_official	159:7130f322cb7e	251	@{
mbed_official	159:7130f322cb7e	252	*/
mbed_official	159:7130f322cb7e	253
mbed_official	159:7130f322cb7e	254	/**
mbed_official	159:7130f322cb7e	255	\brief Union type to access the Application Program Status Register (APSR).
mbed_official	159:7130f322cb7e	256	*/
mbed_official	159:7130f322cb7e	257	typedef union
mbed_official	159:7130f322cb7e	258	{
mbed_official	159:7130f322cb7e	259	struct
mbed_official	159:7130f322cb7e	260	{
mbed_official	159:7130f322cb7e	261	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
mbed_official	159:7130f322cb7e	262	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
mbed_official	159:7130f322cb7e	263	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
mbed_official	159:7130f322cb7e	264	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
mbed_official	159:7130f322cb7e	265	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
mbed_official	159:7130f322cb7e	266	uint32_t C:1; /!< bit: 29 Carry condition code flag /
mbed_official	159:7130f322cb7e	267	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
mbed_official	159:7130f322cb7e	268	uint32_t N:1; /!< bit: 31 Negative condition code flag /
mbed_official	159:7130f322cb7e	269	} b; /!< Structure used for bit access /
mbed_official	159:7130f322cb7e	270	uint32_t w; /!< Type used for word access /
mbed_official	159:7130f322cb7e	271	} APSR_Type;
mbed_official	159:7130f322cb7e	272
mbed_official	159:7130f322cb7e	273	/* APSR Register Definitions */
mbed_official	159:7130f322cb7e	274	#define APSR_N_Pos 31U /!< APSR: N Position /
mbed_official	159:7130f322cb7e	275	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
mbed_official	159:7130f322cb7e	276
mbed_official	159:7130f322cb7e	277	#define APSR_Z_Pos 30U /!< APSR: Z Position /
mbed_official	159:7130f322cb7e	278	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
mbed_official	159:7130f322cb7e	279
mbed_official	159:7130f322cb7e	280	#define APSR_C_Pos 29U /!< APSR: C Position /
mbed_official	159:7130f322cb7e	281	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
mbed_official	159:7130f322cb7e	282
mbed_official	159:7130f322cb7e	283	#define APSR_V_Pos 28U /!< APSR: V Position /
mbed_official	159:7130f322cb7e	284	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
mbed_official	159:7130f322cb7e	285
mbed_official	159:7130f322cb7e	286	#define APSR_Q_Pos 27U /!< APSR: Q Position /
mbed_official	159:7130f322cb7e	287	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
mbed_official	159:7130f322cb7e	288
mbed_official	159:7130f322cb7e	289	#define APSR_GE_Pos 16U /!< APSR: GE Position /
mbed_official	159:7130f322cb7e	290	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
mbed_official	159:7130f322cb7e	291
mbed_official	159:7130f322cb7e	292
mbed_official	159:7130f322cb7e	293	/**
mbed_official	159:7130f322cb7e	294	\brief Union type to access the Interrupt Program Status Register (IPSR).
mbed_official	159:7130f322cb7e	295	*/
mbed_official	159:7130f322cb7e	296	typedef union
mbed_official	159:7130f322cb7e	297	{
mbed_official	159:7130f322cb7e	298	struct
mbed_official	159:7130f322cb7e	299	{
mbed_official	159:7130f322cb7e	300	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
mbed_official	159:7130f322cb7e	301	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
mbed_official	159:7130f322cb7e	302	} b; /!< Structure used for bit access /
mbed_official	159:7130f322cb7e	303	uint32_t w; /!< Type used for word access /
mbed_official	159:7130f322cb7e	304	} IPSR_Type;
mbed_official	159:7130f322cb7e	305
mbed_official	159:7130f322cb7e	306	/* IPSR Register Definitions */
mbed_official	159:7130f322cb7e	307	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
mbed_official	159:7130f322cb7e	308	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
mbed_official	159:7130f322cb7e	309
mbed_official	159:7130f322cb7e	310
mbed_official	159:7130f322cb7e	311	/**
mbed_official	159:7130f322cb7e	312	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mbed_official	159:7130f322cb7e	313	*/
mbed_official	159:7130f322cb7e	314	typedef union
mbed_official	159:7130f322cb7e	315	{
mbed_official	159:7130f322cb7e	316	struct
mbed_official	159:7130f322cb7e	317	{
mbed_official	159:7130f322cb7e	318	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
mbed_official	159:7130f322cb7e	319	uint32_t _reserved0:1; /!< bit: 9 Reserved /
mbed_official	159:7130f322cb7e	320	uint32_t ICI_IT_1:6; /!< bit: 10..15 ICI/IT part 1 /
mbed_official	159:7130f322cb7e	321	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
mbed_official	159:7130f322cb7e	322	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
mbed_official	159:7130f322cb7e	323	uint32_t T:1; /!< bit: 24 Thumb bit /
mbed_official	159:7130f322cb7e	324	uint32_t ICI_IT_2:2; /!< bit: 25..26 ICI/IT part 2 /
mbed_official	159:7130f322cb7e	325	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
mbed_official	159:7130f322cb7e	326	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
mbed_official	159:7130f322cb7e	327	uint32_t C:1; /!< bit: 29 Carry condition code flag /
mbed_official	159:7130f322cb7e	328	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
mbed_official	159:7130f322cb7e	329	uint32_t N:1; /!< bit: 31 Negative condition code flag /
mbed_official	159:7130f322cb7e	330	} b; /!< Structure used for bit access /
mbed_official	159:7130f322cb7e	331	uint32_t w; /!< Type used for word access /
mbed_official	159:7130f322cb7e	332	} xPSR_Type;
mbed_official	159:7130f322cb7e	333
mbed_official	159:7130f322cb7e	334	/* xPSR Register Definitions */
mbed_official	159:7130f322cb7e	335	#define xPSR_N_Pos 31U /!< xPSR: N Position /
mbed_official	159:7130f322cb7e	336	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
mbed_official	159:7130f322cb7e	337
mbed_official	159:7130f322cb7e	338	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
mbed_official	159:7130f322cb7e	339	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
mbed_official	159:7130f322cb7e	340
mbed_official	159:7130f322cb7e	341	#define xPSR_C_Pos 29U /!< xPSR: C Position /
mbed_official	159:7130f322cb7e	342	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
mbed_official	159:7130f322cb7e	343
mbed_official	159:7130f322cb7e	344	#define xPSR_V_Pos 28U /!< xPSR: V Position /
mbed_official	159:7130f322cb7e	345	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
mbed_official	159:7130f322cb7e	346
mbed_official	159:7130f322cb7e	347	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
mbed_official	159:7130f322cb7e	348	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
mbed_official	159:7130f322cb7e	349
mbed_official	159:7130f322cb7e	350	#define xPSR_ICI_IT_2_Pos 25U /!< xPSR: ICI/IT part 2 Position /
mbed_official	159:7130f322cb7e	351	#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /!< xPSR: ICI/IT part 2 Mask /
mbed_official	159:7130f322cb7e	352
mbed_official	159:7130f322cb7e	353	#define xPSR_T_Pos 24U /!< xPSR: T Position /
mbed_official	159:7130f322cb7e	354	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
mbed_official	159:7130f322cb7e	355
mbed_official	159:7130f322cb7e	356	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
mbed_official	159:7130f322cb7e	357	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
mbed_official	159:7130f322cb7e	358
mbed_official	159:7130f322cb7e	359	#define xPSR_ICI_IT_1_Pos 10U /!< xPSR: ICI/IT part 1 Position /
mbed_official	159:7130f322cb7e	360	#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /!< xPSR: ICI/IT part 1 Mask /
mbed_official	159:7130f322cb7e	361
mbed_official	159:7130f322cb7e	362	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
mbed_official	159:7130f322cb7e	363	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
mbed_official	159:7130f322cb7e	364
mbed_official	159:7130f322cb7e	365
mbed_official	159:7130f322cb7e	366	/**
mbed_official	159:7130f322cb7e	367	\brief Union type to access the Control Registers (CONTROL).
mbed_official	159:7130f322cb7e	368	*/
mbed_official	159:7130f322cb7e	369	typedef union
mbed_official	159:7130f322cb7e	370	{
mbed_official	159:7130f322cb7e	371	struct
mbed_official	159:7130f322cb7e	372	{
mbed_official	159:7130f322cb7e	373	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
mbed_official	159:7130f322cb7e	374	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
mbed_official	159:7130f322cb7e	375	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
mbed_official	159:7130f322cb7e	376	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
mbed_official	159:7130f322cb7e	377	} b; /!< Structure used for bit access /
mbed_official	159:7130f322cb7e	378	uint32_t w; /!< Type used for word access /
mbed_official	159:7130f322cb7e	379	} CONTROL_Type;
mbed_official	159:7130f322cb7e	380
mbed_official	159:7130f322cb7e	381	/* CONTROL Register Definitions */
mbed_official	159:7130f322cb7e	382	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
mbed_official	159:7130f322cb7e	383	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
mbed_official	159:7130f322cb7e	384
mbed_official	159:7130f322cb7e	385	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
mbed_official	159:7130f322cb7e	386	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
mbed_official	159:7130f322cb7e	387
mbed_official	159:7130f322cb7e	388	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
mbed_official	159:7130f322cb7e	389	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
mbed_official	159:7130f322cb7e	390
mbed_official	159:7130f322cb7e	391	/@} end of group CMSIS_CORE /
mbed_official	159:7130f322cb7e	392
mbed_official	159:7130f322cb7e	393
mbed_official	159:7130f322cb7e	394	/**
mbed_official	159:7130f322cb7e	395	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	396	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mbed_official	159:7130f322cb7e	397	\brief Type definitions for the NVIC Registers
mbed_official	159:7130f322cb7e	398	@{
mbed_official	159:7130f322cb7e	399	*/
mbed_official	159:7130f322cb7e	400
mbed_official	159:7130f322cb7e	401	/**
mbed_official	159:7130f322cb7e	402	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mbed_official	159:7130f322cb7e	403	*/
mbed_official	159:7130f322cb7e	404	typedef struct
mbed_official	159:7130f322cb7e	405	{
mbed_official	159:7130f322cb7e	406	__IOM uint32_t ISER[8U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
mbed_official	159:7130f322cb7e	407	uint32_t RESERVED0[24U];
mbed_official	159:7130f322cb7e	408	__IOM uint32_t ICER[8U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
mbed_official	159:7130f322cb7e	409	uint32_t RSERVED1[24U];
mbed_official	159:7130f322cb7e	410	__IOM uint32_t ISPR[8U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
mbed_official	159:7130f322cb7e	411	uint32_t RESERVED2[24U];
mbed_official	159:7130f322cb7e	412	__IOM uint32_t ICPR[8U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
mbed_official	159:7130f322cb7e	413	uint32_t RESERVED3[24U];
mbed_official	159:7130f322cb7e	414	__IOM uint32_t IABR[8U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
mbed_official	159:7130f322cb7e	415	uint32_t RESERVED4[56U];
mbed_official	159:7130f322cb7e	416	__IOM uint8_t IP[240U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
mbed_official	159:7130f322cb7e	417	uint32_t RESERVED5[644U];
mbed_official	159:7130f322cb7e	418	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
mbed_official	159:7130f322cb7e	419	} NVIC_Type;
mbed_official	159:7130f322cb7e	420
mbed_official	159:7130f322cb7e	421	/* Software Triggered Interrupt Register Definitions */
mbed_official	159:7130f322cb7e	422	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
mbed_official	159:7130f322cb7e	423	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
mbed_official	159:7130f322cb7e	424
mbed_official	159:7130f322cb7e	425	/@} end of group CMSIS_NVIC /
mbed_official	159:7130f322cb7e	426
mbed_official	159:7130f322cb7e	427
mbed_official	159:7130f322cb7e	428	/**
mbed_official	159:7130f322cb7e	429	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	430	\defgroup CMSIS_SCB System Control Block (SCB)
mbed_official	159:7130f322cb7e	431	\brief Type definitions for the System Control Block Registers
mbed_official	159:7130f322cb7e	432	@{
mbed_official	159:7130f322cb7e	433	*/
mbed_official	159:7130f322cb7e	434
mbed_official	159:7130f322cb7e	435	/**
mbed_official	159:7130f322cb7e	436	\brief Structure type to access the System Control Block (SCB).
mbed_official	159:7130f322cb7e	437	*/
mbed_official	159:7130f322cb7e	438	typedef struct
mbed_official	159:7130f322cb7e	439	{
mbed_official	159:7130f322cb7e	440	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
mbed_official	159:7130f322cb7e	441	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
mbed_official	159:7130f322cb7e	442	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
mbed_official	159:7130f322cb7e	443	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
mbed_official	159:7130f322cb7e	444	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
mbed_official	159:7130f322cb7e	445	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
mbed_official	159:7130f322cb7e	446	__IOM uint8_t SHP[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
mbed_official	159:7130f322cb7e	447	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
mbed_official	159:7130f322cb7e	448	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
mbed_official	159:7130f322cb7e	449	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
mbed_official	159:7130f322cb7e	450	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
mbed_official	159:7130f322cb7e	451	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
mbed_official	159:7130f322cb7e	452	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
mbed_official	159:7130f322cb7e	453	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
mbed_official	159:7130f322cb7e	454	__IM uint32_t PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
mbed_official	159:7130f322cb7e	455	__IM uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
mbed_official	159:7130f322cb7e	456	__IM uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
mbed_official	159:7130f322cb7e	457	__IM uint32_t MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
mbed_official	159:7130f322cb7e	458	__IM uint32_t ISAR[5U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
mbed_official	159:7130f322cb7e	459	uint32_t RESERVED0[5U];
mbed_official	159:7130f322cb7e	460	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
mbed_official	159:7130f322cb7e	461	} SCB_Type;
mbed_official	159:7130f322cb7e	462
mbed_official	159:7130f322cb7e	463	/* SCB CPUID Register Definitions */
mbed_official	159:7130f322cb7e	464	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
mbed_official	159:7130f322cb7e	465	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
mbed_official	159:7130f322cb7e	466
mbed_official	159:7130f322cb7e	467	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
mbed_official	159:7130f322cb7e	468	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
mbed_official	159:7130f322cb7e	469
mbed_official	159:7130f322cb7e	470	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
mbed_official	159:7130f322cb7e	471	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
mbed_official	159:7130f322cb7e	472
mbed_official	159:7130f322cb7e	473	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
mbed_official	159:7130f322cb7e	474	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
mbed_official	159:7130f322cb7e	475
mbed_official	159:7130f322cb7e	476	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
mbed_official	159:7130f322cb7e	477	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
mbed_official	159:7130f322cb7e	478
mbed_official	159:7130f322cb7e	479	/* SCB Interrupt Control State Register Definitions */
mbed_official	159:7130f322cb7e	480	#define SCB_ICSR_NMIPENDSET_Pos 31U /!< SCB ICSR: NMIPENDSET Position /
mbed_official	159:7130f322cb7e	481	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
mbed_official	159:7130f322cb7e	482
mbed_official	159:7130f322cb7e	483	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
mbed_official	159:7130f322cb7e	484	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
mbed_official	159:7130f322cb7e	485
mbed_official	159:7130f322cb7e	486	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
mbed_official	159:7130f322cb7e	487	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
mbed_official	159:7130f322cb7e	488
mbed_official	159:7130f322cb7e	489	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
mbed_official	159:7130f322cb7e	490	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
mbed_official	159:7130f322cb7e	491
mbed_official	159:7130f322cb7e	492	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
mbed_official	159:7130f322cb7e	493	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
mbed_official	159:7130f322cb7e	494
mbed_official	159:7130f322cb7e	495	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
mbed_official	159:7130f322cb7e	496	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
mbed_official	159:7130f322cb7e	497
mbed_official	159:7130f322cb7e	498	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
mbed_official	159:7130f322cb7e	499	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
mbed_official	159:7130f322cb7e	500
mbed_official	159:7130f322cb7e	501	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
mbed_official	159:7130f322cb7e	502	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
mbed_official	159:7130f322cb7e	503
mbed_official	159:7130f322cb7e	504	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
mbed_official	159:7130f322cb7e	505	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
mbed_official	159:7130f322cb7e	506
mbed_official	159:7130f322cb7e	507	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
mbed_official	159:7130f322cb7e	508	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
mbed_official	159:7130f322cb7e	509
mbed_official	159:7130f322cb7e	510	/* SCB Vector Table Offset Register Definitions */
mbed_official	159:7130f322cb7e	511	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
mbed_official	159:7130f322cb7e	512	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
mbed_official	159:7130f322cb7e	513
mbed_official	159:7130f322cb7e	514	/* SCB Application Interrupt and Reset Control Register Definitions */
mbed_official	159:7130f322cb7e	515	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
mbed_official	159:7130f322cb7e	516	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
mbed_official	159:7130f322cb7e	517
mbed_official	159:7130f322cb7e	518	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
mbed_official	159:7130f322cb7e	519	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
mbed_official	159:7130f322cb7e	520
mbed_official	159:7130f322cb7e	521	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
mbed_official	159:7130f322cb7e	522	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
mbed_official	159:7130f322cb7e	523
mbed_official	159:7130f322cb7e	524	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
mbed_official	159:7130f322cb7e	525	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
mbed_official	159:7130f322cb7e	526
mbed_official	159:7130f322cb7e	527	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
mbed_official	159:7130f322cb7e	528	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
mbed_official	159:7130f322cb7e	529
mbed_official	159:7130f322cb7e	530	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
mbed_official	159:7130f322cb7e	531	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
mbed_official	159:7130f322cb7e	532
mbed_official	159:7130f322cb7e	533	#define SCB_AIRCR_VECTRESET_Pos 0U /!< SCB AIRCR: VECTRESET Position /
mbed_official	159:7130f322cb7e	534	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
mbed_official	159:7130f322cb7e	535
mbed_official	159:7130f322cb7e	536	/* SCB System Control Register Definitions */
mbed_official	159:7130f322cb7e	537	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
mbed_official	159:7130f322cb7e	538	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
mbed_official	159:7130f322cb7e	539
mbed_official	159:7130f322cb7e	540	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
mbed_official	159:7130f322cb7e	541	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
mbed_official	159:7130f322cb7e	542
mbed_official	159:7130f322cb7e	543	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
mbed_official	159:7130f322cb7e	544	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
mbed_official	159:7130f322cb7e	545
mbed_official	159:7130f322cb7e	546	/* SCB Configuration Control Register Definitions */
mbed_official	159:7130f322cb7e	547	#define SCB_CCR_STKALIGN_Pos 9U /!< SCB CCR: STKALIGN Position /
mbed_official	159:7130f322cb7e	548	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
mbed_official	159:7130f322cb7e	549
mbed_official	159:7130f322cb7e	550	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
mbed_official	159:7130f322cb7e	551	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
mbed_official	159:7130f322cb7e	552
mbed_official	159:7130f322cb7e	553	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
mbed_official	159:7130f322cb7e	554	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
mbed_official	159:7130f322cb7e	555
mbed_official	159:7130f322cb7e	556	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
mbed_official	159:7130f322cb7e	557	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
mbed_official	159:7130f322cb7e	558
mbed_official	159:7130f322cb7e	559	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
mbed_official	159:7130f322cb7e	560	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
mbed_official	159:7130f322cb7e	561
mbed_official	159:7130f322cb7e	562	#define SCB_CCR_NONBASETHRDENA_Pos 0U /!< SCB CCR: NONBASETHRDENA Position /
mbed_official	159:7130f322cb7e	563	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
mbed_official	159:7130f322cb7e	564
mbed_official	159:7130f322cb7e	565	/* SCB System Handler Control and State Register Definitions */
mbed_official	159:7130f322cb7e	566	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
mbed_official	159:7130f322cb7e	567	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
mbed_official	159:7130f322cb7e	568
mbed_official	159:7130f322cb7e	569	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
mbed_official	159:7130f322cb7e	570	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
mbed_official	159:7130f322cb7e	571
mbed_official	159:7130f322cb7e	572	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
mbed_official	159:7130f322cb7e	573	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
mbed_official	159:7130f322cb7e	574
mbed_official	159:7130f322cb7e	575	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
mbed_official	159:7130f322cb7e	576	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
mbed_official	159:7130f322cb7e	577
mbed_official	159:7130f322cb7e	578	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
mbed_official	159:7130f322cb7e	579	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
mbed_official	159:7130f322cb7e	580
mbed_official	159:7130f322cb7e	581	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
mbed_official	159:7130f322cb7e	582	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
mbed_official	159:7130f322cb7e	583
mbed_official	159:7130f322cb7e	584	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
mbed_official	159:7130f322cb7e	585	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
mbed_official	159:7130f322cb7e	586
mbed_official	159:7130f322cb7e	587	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
mbed_official	159:7130f322cb7e	588	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
mbed_official	159:7130f322cb7e	589
mbed_official	159:7130f322cb7e	590	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
mbed_official	159:7130f322cb7e	591	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
mbed_official	159:7130f322cb7e	592
mbed_official	159:7130f322cb7e	593	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
mbed_official	159:7130f322cb7e	594	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
mbed_official	159:7130f322cb7e	595
mbed_official	159:7130f322cb7e	596	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
mbed_official	159:7130f322cb7e	597	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
mbed_official	159:7130f322cb7e	598
mbed_official	159:7130f322cb7e	599	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
mbed_official	159:7130f322cb7e	600	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
mbed_official	159:7130f322cb7e	601
mbed_official	159:7130f322cb7e	602	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
mbed_official	159:7130f322cb7e	603	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
mbed_official	159:7130f322cb7e	604
mbed_official	159:7130f322cb7e	605	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
mbed_official	159:7130f322cb7e	606	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
mbed_official	159:7130f322cb7e	607
mbed_official	159:7130f322cb7e	608	/* SCB Configurable Fault Status Register Definitions */
mbed_official	159:7130f322cb7e	609	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
mbed_official	159:7130f322cb7e	610	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
mbed_official	159:7130f322cb7e	611
mbed_official	159:7130f322cb7e	612	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
mbed_official	159:7130f322cb7e	613	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
mbed_official	159:7130f322cb7e	614
mbed_official	159:7130f322cb7e	615	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
mbed_official	159:7130f322cb7e	616	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
mbed_official	159:7130f322cb7e	617
mbed_official	159:7130f322cb7e	618	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
mbed_official	159:7130f322cb7e	619	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
mbed_official	159:7130f322cb7e	620	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
mbed_official	159:7130f322cb7e	621
mbed_official	159:7130f322cb7e	622	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
mbed_official	159:7130f322cb7e	623	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
mbed_official	159:7130f322cb7e	624
mbed_official	159:7130f322cb7e	625	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
mbed_official	159:7130f322cb7e	626	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
mbed_official	159:7130f322cb7e	627
mbed_official	159:7130f322cb7e	628	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
mbed_official	159:7130f322cb7e	629	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
mbed_official	159:7130f322cb7e	630
mbed_official	159:7130f322cb7e	631	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
mbed_official	159:7130f322cb7e	632	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
mbed_official	159:7130f322cb7e	633
mbed_official	159:7130f322cb7e	634	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
mbed_official	159:7130f322cb7e	635	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
mbed_official	159:7130f322cb7e	636
mbed_official	159:7130f322cb7e	637	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
mbed_official	159:7130f322cb7e	638	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
mbed_official	159:7130f322cb7e	639	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
mbed_official	159:7130f322cb7e	640
mbed_official	159:7130f322cb7e	641	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
mbed_official	159:7130f322cb7e	642	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
mbed_official	159:7130f322cb7e	643
mbed_official	159:7130f322cb7e	644	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
mbed_official	159:7130f322cb7e	645	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
mbed_official	159:7130f322cb7e	646
mbed_official	159:7130f322cb7e	647	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
mbed_official	159:7130f322cb7e	648	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
mbed_official	159:7130f322cb7e	649
mbed_official	159:7130f322cb7e	650	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
mbed_official	159:7130f322cb7e	651	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
mbed_official	159:7130f322cb7e	652
mbed_official	159:7130f322cb7e	653	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
mbed_official	159:7130f322cb7e	654	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
mbed_official	159:7130f322cb7e	655
mbed_official	159:7130f322cb7e	656	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
mbed_official	159:7130f322cb7e	657	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
mbed_official	159:7130f322cb7e	658
mbed_official	159:7130f322cb7e	659	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
mbed_official	159:7130f322cb7e	660	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
mbed_official	159:7130f322cb7e	661	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
mbed_official	159:7130f322cb7e	662
mbed_official	159:7130f322cb7e	663	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
mbed_official	159:7130f322cb7e	664	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
mbed_official	159:7130f322cb7e	665
mbed_official	159:7130f322cb7e	666	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
mbed_official	159:7130f322cb7e	667	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
mbed_official	159:7130f322cb7e	668
mbed_official	159:7130f322cb7e	669	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
mbed_official	159:7130f322cb7e	670	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
mbed_official	159:7130f322cb7e	671
mbed_official	159:7130f322cb7e	672	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
mbed_official	159:7130f322cb7e	673	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
mbed_official	159:7130f322cb7e	674
mbed_official	159:7130f322cb7e	675	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
mbed_official	159:7130f322cb7e	676	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
mbed_official	159:7130f322cb7e	677
mbed_official	159:7130f322cb7e	678	/* SCB Hard Fault Status Register Definitions */
mbed_official	159:7130f322cb7e	679	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
mbed_official	159:7130f322cb7e	680	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
mbed_official	159:7130f322cb7e	681
mbed_official	159:7130f322cb7e	682	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
mbed_official	159:7130f322cb7e	683	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
mbed_official	159:7130f322cb7e	684
mbed_official	159:7130f322cb7e	685	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
mbed_official	159:7130f322cb7e	686	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
mbed_official	159:7130f322cb7e	687
mbed_official	159:7130f322cb7e	688	/* SCB Debug Fault Status Register Definitions */
mbed_official	159:7130f322cb7e	689	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
mbed_official	159:7130f322cb7e	690	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
mbed_official	159:7130f322cb7e	691
mbed_official	159:7130f322cb7e	692	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
mbed_official	159:7130f322cb7e	693	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
mbed_official	159:7130f322cb7e	694
mbed_official	159:7130f322cb7e	695	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
mbed_official	159:7130f322cb7e	696	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
mbed_official	159:7130f322cb7e	697
mbed_official	159:7130f322cb7e	698	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
mbed_official	159:7130f322cb7e	699	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
mbed_official	159:7130f322cb7e	700
mbed_official	159:7130f322cb7e	701	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
mbed_official	159:7130f322cb7e	702	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
mbed_official	159:7130f322cb7e	703
mbed_official	159:7130f322cb7e	704	/@} end of group CMSIS_SCB /
mbed_official	159:7130f322cb7e	705
mbed_official	159:7130f322cb7e	706
mbed_official	159:7130f322cb7e	707	/**
mbed_official	159:7130f322cb7e	708	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	709	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
mbed_official	159:7130f322cb7e	710	\brief Type definitions for the System Control and ID Register not in the SCB
mbed_official	159:7130f322cb7e	711	@{
mbed_official	159:7130f322cb7e	712	*/
mbed_official	159:7130f322cb7e	713
mbed_official	159:7130f322cb7e	714	/**
mbed_official	159:7130f322cb7e	715	\brief Structure type to access the System Control and ID Register not in the SCB.
mbed_official	159:7130f322cb7e	716	*/
mbed_official	159:7130f322cb7e	717	typedef struct
mbed_official	159:7130f322cb7e	718	{
mbed_official	159:7130f322cb7e	719	uint32_t RESERVED0[1U];
mbed_official	159:7130f322cb7e	720	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
mbed_official	159:7130f322cb7e	721	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
mbed_official	159:7130f322cb7e	722	} SCnSCB_Type;
mbed_official	159:7130f322cb7e	723
mbed_official	159:7130f322cb7e	724	/* Interrupt Controller Type Register Definitions */
mbed_official	159:7130f322cb7e	725	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
mbed_official	159:7130f322cb7e	726	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
mbed_official	159:7130f322cb7e	727
mbed_official	159:7130f322cb7e	728	/* Auxiliary Control Register Definitions */
mbed_official	159:7130f322cb7e	729	#define SCnSCB_ACTLR_DISOOFP_Pos 9U /!< ACTLR: DISOOFP Position /
mbed_official	159:7130f322cb7e	730	#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /!< ACTLR: DISOOFP Mask /
mbed_official	159:7130f322cb7e	731
mbed_official	159:7130f322cb7e	732	#define SCnSCB_ACTLR_DISFPCA_Pos 8U /!< ACTLR: DISFPCA Position /
mbed_official	159:7130f322cb7e	733	#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /!< ACTLR: DISFPCA Mask /
mbed_official	159:7130f322cb7e	734
mbed_official	159:7130f322cb7e	735	#define SCnSCB_ACTLR_DISFOLD_Pos 2U /!< ACTLR: DISFOLD Position /
mbed_official	159:7130f322cb7e	736	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
mbed_official	159:7130f322cb7e	737
mbed_official	159:7130f322cb7e	738	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /!< ACTLR: DISDEFWBUF Position /
mbed_official	159:7130f322cb7e	739	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
mbed_official	159:7130f322cb7e	740
mbed_official	159:7130f322cb7e	741	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /!< ACTLR: DISMCYCINT Position /
mbed_official	159:7130f322cb7e	742	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
mbed_official	159:7130f322cb7e	743
mbed_official	159:7130f322cb7e	744	/@} end of group CMSIS_SCnotSCB /
mbed_official	159:7130f322cb7e	745
mbed_official	159:7130f322cb7e	746
mbed_official	159:7130f322cb7e	747	/**
mbed_official	159:7130f322cb7e	748	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	749	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
mbed_official	159:7130f322cb7e	750	\brief Type definitions for the System Timer Registers.
mbed_official	159:7130f322cb7e	751	@{
mbed_official	159:7130f322cb7e	752	*/
mbed_official	159:7130f322cb7e	753
mbed_official	159:7130f322cb7e	754	/**
mbed_official	159:7130f322cb7e	755	\brief Structure type to access the System Timer (SysTick).
mbed_official	159:7130f322cb7e	756	*/
mbed_official	159:7130f322cb7e	757	typedef struct
mbed_official	159:7130f322cb7e	758	{
mbed_official	159:7130f322cb7e	759	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
mbed_official	159:7130f322cb7e	760	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
mbed_official	159:7130f322cb7e	761	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
mbed_official	159:7130f322cb7e	762	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
mbed_official	159:7130f322cb7e	763	} SysTick_Type;
mbed_official	159:7130f322cb7e	764
mbed_official	159:7130f322cb7e	765	/* SysTick Control / Status Register Definitions */
mbed_official	159:7130f322cb7e	766	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
mbed_official	159:7130f322cb7e	767	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
mbed_official	159:7130f322cb7e	768
mbed_official	159:7130f322cb7e	769	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
mbed_official	159:7130f322cb7e	770	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
mbed_official	159:7130f322cb7e	771
mbed_official	159:7130f322cb7e	772	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
mbed_official	159:7130f322cb7e	773	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
mbed_official	159:7130f322cb7e	774
mbed_official	159:7130f322cb7e	775	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
mbed_official	159:7130f322cb7e	776	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
mbed_official	159:7130f322cb7e	777
mbed_official	159:7130f322cb7e	778	/* SysTick Reload Register Definitions */
mbed_official	159:7130f322cb7e	779	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
mbed_official	159:7130f322cb7e	780	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
mbed_official	159:7130f322cb7e	781
mbed_official	159:7130f322cb7e	782	/* SysTick Current Register Definitions */
mbed_official	159:7130f322cb7e	783	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
mbed_official	159:7130f322cb7e	784	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
mbed_official	159:7130f322cb7e	785
mbed_official	159:7130f322cb7e	786	/* SysTick Calibration Register Definitions */
mbed_official	159:7130f322cb7e	787	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
mbed_official	159:7130f322cb7e	788	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
mbed_official	159:7130f322cb7e	789
mbed_official	159:7130f322cb7e	790	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
mbed_official	159:7130f322cb7e	791	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
mbed_official	159:7130f322cb7e	792
mbed_official	159:7130f322cb7e	793	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
mbed_official	159:7130f322cb7e	794	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
mbed_official	159:7130f322cb7e	795
mbed_official	159:7130f322cb7e	796	/@} end of group CMSIS_SysTick /
mbed_official	159:7130f322cb7e	797
mbed_official	159:7130f322cb7e	798
mbed_official	159:7130f322cb7e	799	/**
mbed_official	159:7130f322cb7e	800	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	801	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
mbed_official	159:7130f322cb7e	802	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
mbed_official	159:7130f322cb7e	803	@{
mbed_official	159:7130f322cb7e	804	*/
mbed_official	159:7130f322cb7e	805
mbed_official	159:7130f322cb7e	806	/**
mbed_official	159:7130f322cb7e	807	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
mbed_official	159:7130f322cb7e	808	*/
mbed_official	159:7130f322cb7e	809	typedef struct
mbed_official	159:7130f322cb7e	810	{
mbed_official	159:7130f322cb7e	811	__OM union
mbed_official	159:7130f322cb7e	812	{
mbed_official	159:7130f322cb7e	813	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
mbed_official	159:7130f322cb7e	814	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
mbed_official	159:7130f322cb7e	815	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
mbed_official	159:7130f322cb7e	816	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
mbed_official	159:7130f322cb7e	817	uint32_t RESERVED0[864U];
mbed_official	159:7130f322cb7e	818	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
mbed_official	159:7130f322cb7e	819	uint32_t RESERVED1[15U];
mbed_official	159:7130f322cb7e	820	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
mbed_official	159:7130f322cb7e	821	uint32_t RESERVED2[15U];
mbed_official	159:7130f322cb7e	822	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
mbed_official	159:7130f322cb7e	823	uint32_t RESERVED3[29U];
mbed_official	159:7130f322cb7e	824	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
mbed_official	159:7130f322cb7e	825	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
mbed_official	159:7130f322cb7e	826	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
mbed_official	159:7130f322cb7e	827	uint32_t RESERVED4[43U];
mbed_official	159:7130f322cb7e	828	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
mbed_official	159:7130f322cb7e	829	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
mbed_official	159:7130f322cb7e	830	uint32_t RESERVED5[6U];
mbed_official	159:7130f322cb7e	831	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
mbed_official	159:7130f322cb7e	832	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
mbed_official	159:7130f322cb7e	833	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
mbed_official	159:7130f322cb7e	834	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
mbed_official	159:7130f322cb7e	835	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
mbed_official	159:7130f322cb7e	836	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
mbed_official	159:7130f322cb7e	837	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
mbed_official	159:7130f322cb7e	838	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
mbed_official	159:7130f322cb7e	839	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
mbed_official	159:7130f322cb7e	840	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
mbed_official	159:7130f322cb7e	841	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
mbed_official	159:7130f322cb7e	842	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
mbed_official	159:7130f322cb7e	843	} ITM_Type;
mbed_official	159:7130f322cb7e	844
mbed_official	159:7130f322cb7e	845	/* ITM Trace Privilege Register Definitions */
mbed_official	159:7130f322cb7e	846	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
mbed_official	159:7130f322cb7e	847	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
mbed_official	159:7130f322cb7e	848
mbed_official	159:7130f322cb7e	849	/* ITM Trace Control Register Definitions */
mbed_official	159:7130f322cb7e	850	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
mbed_official	159:7130f322cb7e	851	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
mbed_official	159:7130f322cb7e	852
mbed_official	159:7130f322cb7e	853	#define ITM_TCR_TraceBusID_Pos 16U /!< ITM TCR: ATBID Position /
mbed_official	159:7130f322cb7e	854	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
mbed_official	159:7130f322cb7e	855
mbed_official	159:7130f322cb7e	856	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
mbed_official	159:7130f322cb7e	857	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
mbed_official	159:7130f322cb7e	858
mbed_official	159:7130f322cb7e	859	#define ITM_TCR_TSPrescale_Pos 8U /!< ITM TCR: TSPrescale Position /
mbed_official	159:7130f322cb7e	860	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
mbed_official	159:7130f322cb7e	861
mbed_official	159:7130f322cb7e	862	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
mbed_official	159:7130f322cb7e	863	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
mbed_official	159:7130f322cb7e	864
mbed_official	159:7130f322cb7e	865	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
mbed_official	159:7130f322cb7e	866	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
mbed_official	159:7130f322cb7e	867
mbed_official	159:7130f322cb7e	868	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
mbed_official	159:7130f322cb7e	869	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
mbed_official	159:7130f322cb7e	870
mbed_official	159:7130f322cb7e	871	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
mbed_official	159:7130f322cb7e	872	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
mbed_official	159:7130f322cb7e	873
mbed_official	159:7130f322cb7e	874	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
mbed_official	159:7130f322cb7e	875	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
mbed_official	159:7130f322cb7e	876
mbed_official	159:7130f322cb7e	877	/* ITM Integration Write Register Definitions */
mbed_official	159:7130f322cb7e	878	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
mbed_official	159:7130f322cb7e	879	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
mbed_official	159:7130f322cb7e	880
mbed_official	159:7130f322cb7e	881	/* ITM Integration Read Register Definitions */
mbed_official	159:7130f322cb7e	882	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
mbed_official	159:7130f322cb7e	883	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
mbed_official	159:7130f322cb7e	884
mbed_official	159:7130f322cb7e	885	/* ITM Integration Mode Control Register Definitions */
mbed_official	159:7130f322cb7e	886	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
mbed_official	159:7130f322cb7e	887	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
mbed_official	159:7130f322cb7e	888
mbed_official	159:7130f322cb7e	889	/* ITM Lock Status Register Definitions */
mbed_official	159:7130f322cb7e	890	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
mbed_official	159:7130f322cb7e	891	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
mbed_official	159:7130f322cb7e	892
mbed_official	159:7130f322cb7e	893	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
mbed_official	159:7130f322cb7e	894	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
mbed_official	159:7130f322cb7e	895
mbed_official	159:7130f322cb7e	896	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
mbed_official	159:7130f322cb7e	897	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
mbed_official	159:7130f322cb7e	898
mbed_official	159:7130f322cb7e	899	/@}/ /* end of group CMSIS_ITM */
mbed_official	159:7130f322cb7e	900
mbed_official	159:7130f322cb7e	901
mbed_official	159:7130f322cb7e	902	/**
mbed_official	159:7130f322cb7e	903	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	904	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
mbed_official	159:7130f322cb7e	905	\brief Type definitions for the Data Watchpoint and Trace (DWT)
mbed_official	159:7130f322cb7e	906	@{
mbed_official	159:7130f322cb7e	907	*/
mbed_official	159:7130f322cb7e	908
mbed_official	159:7130f322cb7e	909	/**
mbed_official	159:7130f322cb7e	910	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
mbed_official	159:7130f322cb7e	911	*/
mbed_official	159:7130f322cb7e	912	typedef struct
mbed_official	159:7130f322cb7e	913	{
mbed_official	159:7130f322cb7e	914	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
mbed_official	159:7130f322cb7e	915	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
mbed_official	159:7130f322cb7e	916	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
mbed_official	159:7130f322cb7e	917	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
mbed_official	159:7130f322cb7e	918	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
mbed_official	159:7130f322cb7e	919	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
mbed_official	159:7130f322cb7e	920	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
mbed_official	159:7130f322cb7e	921	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
mbed_official	159:7130f322cb7e	922	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
mbed_official	159:7130f322cb7e	923	__IOM uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
mbed_official	159:7130f322cb7e	924	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
mbed_official	159:7130f322cb7e	925	uint32_t RESERVED0[1U];
mbed_official	159:7130f322cb7e	926	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
mbed_official	159:7130f322cb7e	927	__IOM uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
mbed_official	159:7130f322cb7e	928	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
mbed_official	159:7130f322cb7e	929	uint32_t RESERVED1[1U];
mbed_official	159:7130f322cb7e	930	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
mbed_official	159:7130f322cb7e	931	__IOM uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
mbed_official	159:7130f322cb7e	932	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
mbed_official	159:7130f322cb7e	933	uint32_t RESERVED2[1U];
mbed_official	159:7130f322cb7e	934	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
mbed_official	159:7130f322cb7e	935	__IOM uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
mbed_official	159:7130f322cb7e	936	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
mbed_official	159:7130f322cb7e	937	} DWT_Type;
mbed_official	159:7130f322cb7e	938
mbed_official	159:7130f322cb7e	939	/* DWT Control Register Definitions */
mbed_official	159:7130f322cb7e	940	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
mbed_official	159:7130f322cb7e	941	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
mbed_official	159:7130f322cb7e	942
mbed_official	159:7130f322cb7e	943	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
mbed_official	159:7130f322cb7e	944	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
mbed_official	159:7130f322cb7e	945
mbed_official	159:7130f322cb7e	946	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
mbed_official	159:7130f322cb7e	947	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
mbed_official	159:7130f322cb7e	948
mbed_official	159:7130f322cb7e	949	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
mbed_official	159:7130f322cb7e	950	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
mbed_official	159:7130f322cb7e	951
mbed_official	159:7130f322cb7e	952	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
mbed_official	159:7130f322cb7e	953	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
mbed_official	159:7130f322cb7e	954
mbed_official	159:7130f322cb7e	955	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
mbed_official	159:7130f322cb7e	956	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
mbed_official	159:7130f322cb7e	957
mbed_official	159:7130f322cb7e	958	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
mbed_official	159:7130f322cb7e	959	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
mbed_official	159:7130f322cb7e	960
mbed_official	159:7130f322cb7e	961	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
mbed_official	159:7130f322cb7e	962	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
mbed_official	159:7130f322cb7e	963
mbed_official	159:7130f322cb7e	964	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
mbed_official	159:7130f322cb7e	965	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
mbed_official	159:7130f322cb7e	966
mbed_official	159:7130f322cb7e	967	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
mbed_official	159:7130f322cb7e	968	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
mbed_official	159:7130f322cb7e	969
mbed_official	159:7130f322cb7e	970	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
mbed_official	159:7130f322cb7e	971	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
mbed_official	159:7130f322cb7e	972
mbed_official	159:7130f322cb7e	973	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
mbed_official	159:7130f322cb7e	974	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
mbed_official	159:7130f322cb7e	975
mbed_official	159:7130f322cb7e	976	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
mbed_official	159:7130f322cb7e	977	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
mbed_official	159:7130f322cb7e	978
mbed_official	159:7130f322cb7e	979	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
mbed_official	159:7130f322cb7e	980	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
mbed_official	159:7130f322cb7e	981
mbed_official	159:7130f322cb7e	982	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
mbed_official	159:7130f322cb7e	983	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
mbed_official	159:7130f322cb7e	984
mbed_official	159:7130f322cb7e	985	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
mbed_official	159:7130f322cb7e	986	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
mbed_official	159:7130f322cb7e	987
mbed_official	159:7130f322cb7e	988	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
mbed_official	159:7130f322cb7e	989	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
mbed_official	159:7130f322cb7e	990
mbed_official	159:7130f322cb7e	991	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
mbed_official	159:7130f322cb7e	992	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
mbed_official	159:7130f322cb7e	993
mbed_official	159:7130f322cb7e	994	/* DWT CPI Count Register Definitions */
mbed_official	159:7130f322cb7e	995	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
mbed_official	159:7130f322cb7e	996	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
mbed_official	159:7130f322cb7e	997
mbed_official	159:7130f322cb7e	998	/* DWT Exception Overhead Count Register Definitions */
mbed_official	159:7130f322cb7e	999	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
mbed_official	159:7130f322cb7e	1000	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
mbed_official	159:7130f322cb7e	1001
mbed_official	159:7130f322cb7e	1002	/* DWT Sleep Count Register Definitions */
mbed_official	159:7130f322cb7e	1003	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
mbed_official	159:7130f322cb7e	1004	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
mbed_official	159:7130f322cb7e	1005
mbed_official	159:7130f322cb7e	1006	/* DWT LSU Count Register Definitions */
mbed_official	159:7130f322cb7e	1007	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
mbed_official	159:7130f322cb7e	1008	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
mbed_official	159:7130f322cb7e	1009
mbed_official	159:7130f322cb7e	1010	/* DWT Folded-instruction Count Register Definitions */
mbed_official	159:7130f322cb7e	1011	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
mbed_official	159:7130f322cb7e	1012	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
mbed_official	159:7130f322cb7e	1013
mbed_official	159:7130f322cb7e	1014	/* DWT Comparator Mask Register Definitions */
mbed_official	159:7130f322cb7e	1015	#define DWT_MASK_MASK_Pos 0U /!< DWT MASK: MASK Position /
mbed_official	159:7130f322cb7e	1016	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
mbed_official	159:7130f322cb7e	1017
mbed_official	159:7130f322cb7e	1018	/* DWT Comparator Function Register Definitions */
mbed_official	159:7130f322cb7e	1019	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
mbed_official	159:7130f322cb7e	1020	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
mbed_official	159:7130f322cb7e	1021
mbed_official	159:7130f322cb7e	1022	#define DWT_FUNCTION_DATAVADDR1_Pos 16U /!< DWT FUNCTION: DATAVADDR1 Position /
mbed_official	159:7130f322cb7e	1023	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
mbed_official	159:7130f322cb7e	1024
mbed_official	159:7130f322cb7e	1025	#define DWT_FUNCTION_DATAVADDR0_Pos 12U /!< DWT FUNCTION: DATAVADDR0 Position /
mbed_official	159:7130f322cb7e	1026	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
mbed_official	159:7130f322cb7e	1027
mbed_official	159:7130f322cb7e	1028	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
mbed_official	159:7130f322cb7e	1029	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
mbed_official	159:7130f322cb7e	1030
mbed_official	159:7130f322cb7e	1031	#define DWT_FUNCTION_LNK1ENA_Pos 9U /!< DWT FUNCTION: LNK1ENA Position /
mbed_official	159:7130f322cb7e	1032	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
mbed_official	159:7130f322cb7e	1033
mbed_official	159:7130f322cb7e	1034	#define DWT_FUNCTION_DATAVMATCH_Pos 8U /!< DWT FUNCTION: DATAVMATCH Position /
mbed_official	159:7130f322cb7e	1035	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
mbed_official	159:7130f322cb7e	1036
mbed_official	159:7130f322cb7e	1037	#define DWT_FUNCTION_CYCMATCH_Pos 7U /!< DWT FUNCTION: CYCMATCH Position /
mbed_official	159:7130f322cb7e	1038	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
mbed_official	159:7130f322cb7e	1039
mbed_official	159:7130f322cb7e	1040	#define DWT_FUNCTION_EMITRANGE_Pos 5U /!< DWT FUNCTION: EMITRANGE Position /
mbed_official	159:7130f322cb7e	1041	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
mbed_official	159:7130f322cb7e	1042
mbed_official	159:7130f322cb7e	1043	#define DWT_FUNCTION_FUNCTION_Pos 0U /!< DWT FUNCTION: FUNCTION Position /
mbed_official	159:7130f322cb7e	1044	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
mbed_official	159:7130f322cb7e	1045
mbed_official	159:7130f322cb7e	1046	/@}/ /* end of group CMSIS_DWT */
mbed_official	159:7130f322cb7e	1047
mbed_official	159:7130f322cb7e	1048
mbed_official	159:7130f322cb7e	1049	/**
mbed_official	159:7130f322cb7e	1050	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	1051	\defgroup CMSIS_TPI Trace Port Interface (TPI)
mbed_official	159:7130f322cb7e	1052	\brief Type definitions for the Trace Port Interface (TPI)
mbed_official	159:7130f322cb7e	1053	@{
mbed_official	159:7130f322cb7e	1054	*/
mbed_official	159:7130f322cb7e	1055
mbed_official	159:7130f322cb7e	1056	/**
mbed_official	159:7130f322cb7e	1057	\brief Structure type to access the Trace Port Interface Register (TPI).
mbed_official	159:7130f322cb7e	1058	*/
mbed_official	159:7130f322cb7e	1059	typedef struct
mbed_official	159:7130f322cb7e	1060	{
mbed_official	159:7130f322cb7e	1061	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
mbed_official	159:7130f322cb7e	1062	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
mbed_official	159:7130f322cb7e	1063	uint32_t RESERVED0[2U];
mbed_official	159:7130f322cb7e	1064	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
mbed_official	159:7130f322cb7e	1065	uint32_t RESERVED1[55U];
mbed_official	159:7130f322cb7e	1066	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
mbed_official	159:7130f322cb7e	1067	uint32_t RESERVED2[131U];
mbed_official	159:7130f322cb7e	1068	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
mbed_official	159:7130f322cb7e	1069	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
mbed_official	159:7130f322cb7e	1070	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
mbed_official	159:7130f322cb7e	1071	uint32_t RESERVED3[759U];
mbed_official	159:7130f322cb7e	1072	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
mbed_official	159:7130f322cb7e	1073	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
mbed_official	159:7130f322cb7e	1074	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
mbed_official	159:7130f322cb7e	1075	uint32_t RESERVED4[1U];
mbed_official	159:7130f322cb7e	1076	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
mbed_official	159:7130f322cb7e	1077	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
mbed_official	159:7130f322cb7e	1078	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
mbed_official	159:7130f322cb7e	1079	uint32_t RESERVED5[39U];
mbed_official	159:7130f322cb7e	1080	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
mbed_official	159:7130f322cb7e	1081	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
mbed_official	159:7130f322cb7e	1082	uint32_t RESERVED7[8U];
mbed_official	159:7130f322cb7e	1083	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
mbed_official	159:7130f322cb7e	1084	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
mbed_official	159:7130f322cb7e	1085	} TPI_Type;
mbed_official	159:7130f322cb7e	1086
mbed_official	159:7130f322cb7e	1087	/* TPI Asynchronous Clock Prescaler Register Definitions */
mbed_official	159:7130f322cb7e	1088	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
mbed_official	159:7130f322cb7e	1089	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
mbed_official	159:7130f322cb7e	1090
mbed_official	159:7130f322cb7e	1091	/* TPI Selected Pin Protocol Register Definitions */
mbed_official	159:7130f322cb7e	1092	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
mbed_official	159:7130f322cb7e	1093	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
mbed_official	159:7130f322cb7e	1094
mbed_official	159:7130f322cb7e	1095	/* TPI Formatter and Flush Status Register Definitions */
mbed_official	159:7130f322cb7e	1096	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
mbed_official	159:7130f322cb7e	1097	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
mbed_official	159:7130f322cb7e	1098
mbed_official	159:7130f322cb7e	1099	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
mbed_official	159:7130f322cb7e	1100	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
mbed_official	159:7130f322cb7e	1101
mbed_official	159:7130f322cb7e	1102	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
mbed_official	159:7130f322cb7e	1103	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
mbed_official	159:7130f322cb7e	1104
mbed_official	159:7130f322cb7e	1105	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
mbed_official	159:7130f322cb7e	1106	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
mbed_official	159:7130f322cb7e	1107
mbed_official	159:7130f322cb7e	1108	/* TPI Formatter and Flush Control Register Definitions */
mbed_official	159:7130f322cb7e	1109	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
mbed_official	159:7130f322cb7e	1110	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
mbed_official	159:7130f322cb7e	1111
mbed_official	159:7130f322cb7e	1112	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
mbed_official	159:7130f322cb7e	1113	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
mbed_official	159:7130f322cb7e	1114
mbed_official	159:7130f322cb7e	1115	/* TPI TRIGGER Register Definitions */
mbed_official	159:7130f322cb7e	1116	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
mbed_official	159:7130f322cb7e	1117	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
mbed_official	159:7130f322cb7e	1118
mbed_official	159:7130f322cb7e	1119	/* TPI Integration ETM Data Register Definitions (FIFO0) */
mbed_official	159:7130f322cb7e	1120	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
mbed_official	159:7130f322cb7e	1121	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
mbed_official	159:7130f322cb7e	1122
mbed_official	159:7130f322cb7e	1123	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
mbed_official	159:7130f322cb7e	1124	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
mbed_official	159:7130f322cb7e	1125
mbed_official	159:7130f322cb7e	1126	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
mbed_official	159:7130f322cb7e	1127	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
mbed_official	159:7130f322cb7e	1128
mbed_official	159:7130f322cb7e	1129	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
mbed_official	159:7130f322cb7e	1130	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
mbed_official	159:7130f322cb7e	1131
mbed_official	159:7130f322cb7e	1132	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
mbed_official	159:7130f322cb7e	1133	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
mbed_official	159:7130f322cb7e	1134
mbed_official	159:7130f322cb7e	1135	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
mbed_official	159:7130f322cb7e	1136	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
mbed_official	159:7130f322cb7e	1137
mbed_official	159:7130f322cb7e	1138	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
mbed_official	159:7130f322cb7e	1139	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
mbed_official	159:7130f322cb7e	1140
mbed_official	159:7130f322cb7e	1141	/* TPI ITATBCTR2 Register Definitions */
mbed_official	159:7130f322cb7e	1142	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
mbed_official	159:7130f322cb7e	1143	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
mbed_official	159:7130f322cb7e	1144
mbed_official	159:7130f322cb7e	1145	/* TPI Integration ITM Data Register Definitions (FIFO1) */
mbed_official	159:7130f322cb7e	1146	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
mbed_official	159:7130f322cb7e	1147	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
mbed_official	159:7130f322cb7e	1148
mbed_official	159:7130f322cb7e	1149	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
mbed_official	159:7130f322cb7e	1150	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
mbed_official	159:7130f322cb7e	1151
mbed_official	159:7130f322cb7e	1152	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
mbed_official	159:7130f322cb7e	1153	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
mbed_official	159:7130f322cb7e	1154
mbed_official	159:7130f322cb7e	1155	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
mbed_official	159:7130f322cb7e	1156	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
mbed_official	159:7130f322cb7e	1157
mbed_official	159:7130f322cb7e	1158	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
mbed_official	159:7130f322cb7e	1159	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
mbed_official	159:7130f322cb7e	1160
mbed_official	159:7130f322cb7e	1161	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
mbed_official	159:7130f322cb7e	1162	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
mbed_official	159:7130f322cb7e	1163
mbed_official	159:7130f322cb7e	1164	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
mbed_official	159:7130f322cb7e	1165	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
mbed_official	159:7130f322cb7e	1166
mbed_official	159:7130f322cb7e	1167	/* TPI ITATBCTR0 Register Definitions */
mbed_official	159:7130f322cb7e	1168	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
mbed_official	159:7130f322cb7e	1169	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
mbed_official	159:7130f322cb7e	1170
mbed_official	159:7130f322cb7e	1171	/* TPI Integration Mode Control Register Definitions */
mbed_official	159:7130f322cb7e	1172	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
mbed_official	159:7130f322cb7e	1173	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
mbed_official	159:7130f322cb7e	1174
mbed_official	159:7130f322cb7e	1175	/* TPI DEVID Register Definitions */
mbed_official	159:7130f322cb7e	1176	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
mbed_official	159:7130f322cb7e	1177	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
mbed_official	159:7130f322cb7e	1178
mbed_official	159:7130f322cb7e	1179	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
mbed_official	159:7130f322cb7e	1180	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
mbed_official	159:7130f322cb7e	1181
mbed_official	159:7130f322cb7e	1182	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
mbed_official	159:7130f322cb7e	1183	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
mbed_official	159:7130f322cb7e	1184
mbed_official	159:7130f322cb7e	1185	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
mbed_official	159:7130f322cb7e	1186	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
mbed_official	159:7130f322cb7e	1187
mbed_official	159:7130f322cb7e	1188	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
mbed_official	159:7130f322cb7e	1189	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
mbed_official	159:7130f322cb7e	1190
mbed_official	159:7130f322cb7e	1191	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
mbed_official	159:7130f322cb7e	1192	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
mbed_official	159:7130f322cb7e	1193
mbed_official	159:7130f322cb7e	1194	/* TPI DEVTYPE Register Definitions */
mbed_official	159:7130f322cb7e	1195	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
mbed_official	159:7130f322cb7e	1196	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
mbed_official	159:7130f322cb7e	1197
mbed_official	159:7130f322cb7e	1198	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
mbed_official	159:7130f322cb7e	1199	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
mbed_official	159:7130f322cb7e	1200
mbed_official	159:7130f322cb7e	1201	/@}/ /* end of group CMSIS_TPI */
mbed_official	159:7130f322cb7e	1202
mbed_official	159:7130f322cb7e	1203
mbed_official	159:7130f322cb7e	1204	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
mbed_official	159:7130f322cb7e	1205	/**
mbed_official	159:7130f322cb7e	1206	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	1207	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
mbed_official	159:7130f322cb7e	1208	\brief Type definitions for the Memory Protection Unit (MPU)
mbed_official	159:7130f322cb7e	1209	@{
mbed_official	159:7130f322cb7e	1210	*/
mbed_official	159:7130f322cb7e	1211
mbed_official	159:7130f322cb7e	1212	/**
mbed_official	159:7130f322cb7e	1213	\brief Structure type to access the Memory Protection Unit (MPU).
mbed_official	159:7130f322cb7e	1214	*/
mbed_official	159:7130f322cb7e	1215	typedef struct
mbed_official	159:7130f322cb7e	1216	{
mbed_official	159:7130f322cb7e	1217	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
mbed_official	159:7130f322cb7e	1218	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
mbed_official	159:7130f322cb7e	1219	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
mbed_official	159:7130f322cb7e	1220	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
mbed_official	159:7130f322cb7e	1221	__IOM uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
mbed_official	159:7130f322cb7e	1222	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
mbed_official	159:7130f322cb7e	1223	__IOM uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
mbed_official	159:7130f322cb7e	1224	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
mbed_official	159:7130f322cb7e	1225	__IOM uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
mbed_official	159:7130f322cb7e	1226	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
mbed_official	159:7130f322cb7e	1227	__IOM uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
mbed_official	159:7130f322cb7e	1228	} MPU_Type;
mbed_official	159:7130f322cb7e	1229
mbed_official	159:7130f322cb7e	1230	/* MPU Type Register Definitions */
mbed_official	159:7130f322cb7e	1231	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
mbed_official	159:7130f322cb7e	1232	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
mbed_official	159:7130f322cb7e	1233
mbed_official	159:7130f322cb7e	1234	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
mbed_official	159:7130f322cb7e	1235	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
mbed_official	159:7130f322cb7e	1236
mbed_official	159:7130f322cb7e	1237	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
mbed_official	159:7130f322cb7e	1238	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
mbed_official	159:7130f322cb7e	1239
mbed_official	159:7130f322cb7e	1240	/* MPU Control Register Definitions */
mbed_official	159:7130f322cb7e	1241	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
mbed_official	159:7130f322cb7e	1242	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
mbed_official	159:7130f322cb7e	1243
mbed_official	159:7130f322cb7e	1244	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
mbed_official	159:7130f322cb7e	1245	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
mbed_official	159:7130f322cb7e	1246
mbed_official	159:7130f322cb7e	1247	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
mbed_official	159:7130f322cb7e	1248	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
mbed_official	159:7130f322cb7e	1249
mbed_official	159:7130f322cb7e	1250	/* MPU Region Number Register Definitions */
mbed_official	159:7130f322cb7e	1251	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
mbed_official	159:7130f322cb7e	1252	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
mbed_official	159:7130f322cb7e	1253
mbed_official	159:7130f322cb7e	1254	/* MPU Region Base Address Register Definitions */
mbed_official	159:7130f322cb7e	1255	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
mbed_official	159:7130f322cb7e	1256	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
mbed_official	159:7130f322cb7e	1257
mbed_official	159:7130f322cb7e	1258	#define MPU_RBAR_VALID_Pos 4U /!< MPU RBAR: VALID Position /
mbed_official	159:7130f322cb7e	1259	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
mbed_official	159:7130f322cb7e	1260
mbed_official	159:7130f322cb7e	1261	#define MPU_RBAR_REGION_Pos 0U /!< MPU RBAR: REGION Position /
mbed_official	159:7130f322cb7e	1262	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
mbed_official	159:7130f322cb7e	1263
mbed_official	159:7130f322cb7e	1264	/* MPU Region Attribute and Size Register Definitions */
mbed_official	159:7130f322cb7e	1265	#define MPU_RASR_ATTRS_Pos 16U /!< MPU RASR: MPU Region Attribute field Position /
mbed_official	159:7130f322cb7e	1266	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
mbed_official	159:7130f322cb7e	1267
mbed_official	159:7130f322cb7e	1268	#define MPU_RASR_XN_Pos 28U /!< MPU RASR: ATTRS.XN Position /
mbed_official	159:7130f322cb7e	1269	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
mbed_official	159:7130f322cb7e	1270
mbed_official	159:7130f322cb7e	1271	#define MPU_RASR_AP_Pos 24U /!< MPU RASR: ATTRS.AP Position /
mbed_official	159:7130f322cb7e	1272	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
mbed_official	159:7130f322cb7e	1273
mbed_official	159:7130f322cb7e	1274	#define MPU_RASR_TEX_Pos 19U /!< MPU RASR: ATTRS.TEX Position /
mbed_official	159:7130f322cb7e	1275	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
mbed_official	159:7130f322cb7e	1276
mbed_official	159:7130f322cb7e	1277	#define MPU_RASR_S_Pos 18U /!< MPU RASR: ATTRS.S Position /
mbed_official	159:7130f322cb7e	1278	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
mbed_official	159:7130f322cb7e	1279
mbed_official	159:7130f322cb7e	1280	#define MPU_RASR_C_Pos 17U /!< MPU RASR: ATTRS.C Position /
mbed_official	159:7130f322cb7e	1281	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
mbed_official	159:7130f322cb7e	1282
mbed_official	159:7130f322cb7e	1283	#define MPU_RASR_B_Pos 16U /!< MPU RASR: ATTRS.B Position /
mbed_official	159:7130f322cb7e	1284	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
mbed_official	159:7130f322cb7e	1285
mbed_official	159:7130f322cb7e	1286	#define MPU_RASR_SRD_Pos 8U /!< MPU RASR: Sub-Region Disable Position /
mbed_official	159:7130f322cb7e	1287	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
mbed_official	159:7130f322cb7e	1288
mbed_official	159:7130f322cb7e	1289	#define MPU_RASR_SIZE_Pos 1U /!< MPU RASR: Region Size Field Position /
mbed_official	159:7130f322cb7e	1290	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
mbed_official	159:7130f322cb7e	1291
mbed_official	159:7130f322cb7e	1292	#define MPU_RASR_ENABLE_Pos 0U /!< MPU RASR: Region enable bit Position /
mbed_official	159:7130f322cb7e	1293	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
mbed_official	159:7130f322cb7e	1294
mbed_official	159:7130f322cb7e	1295	/@} end of group CMSIS_MPU /
mbed_official	159:7130f322cb7e	1296	#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
mbed_official	159:7130f322cb7e	1297
mbed_official	159:7130f322cb7e	1298
mbed_official	159:7130f322cb7e	1299	/**
mbed_official	159:7130f322cb7e	1300	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	1301	\defgroup CMSIS_FPU Floating Point Unit (FPU)
mbed_official	159:7130f322cb7e	1302	\brief Type definitions for the Floating Point Unit (FPU)
mbed_official	159:7130f322cb7e	1303	@{
mbed_official	159:7130f322cb7e	1304	*/
mbed_official	159:7130f322cb7e	1305
mbed_official	159:7130f322cb7e	1306	/**
mbed_official	159:7130f322cb7e	1307	\brief Structure type to access the Floating Point Unit (FPU).
mbed_official	159:7130f322cb7e	1308	*/
mbed_official	159:7130f322cb7e	1309	typedef struct
mbed_official	159:7130f322cb7e	1310	{
mbed_official	159:7130f322cb7e	1311	uint32_t RESERVED0[1U];
mbed_official	159:7130f322cb7e	1312	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
mbed_official	159:7130f322cb7e	1313	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
mbed_official	159:7130f322cb7e	1314	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
mbed_official	159:7130f322cb7e	1315	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
mbed_official	159:7130f322cb7e	1316	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
mbed_official	159:7130f322cb7e	1317	} FPU_Type;
mbed_official	159:7130f322cb7e	1318
mbed_official	159:7130f322cb7e	1319	/* Floating-Point Context Control Register Definitions */
mbed_official	159:7130f322cb7e	1320	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
mbed_official	159:7130f322cb7e	1321	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
mbed_official	159:7130f322cb7e	1322
mbed_official	159:7130f322cb7e	1323	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
mbed_official	159:7130f322cb7e	1324	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
mbed_official	159:7130f322cb7e	1325
mbed_official	159:7130f322cb7e	1326	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
mbed_official	159:7130f322cb7e	1327	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
mbed_official	159:7130f322cb7e	1328
mbed_official	159:7130f322cb7e	1329	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
mbed_official	159:7130f322cb7e	1330	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
mbed_official	159:7130f322cb7e	1331
mbed_official	159:7130f322cb7e	1332	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
mbed_official	159:7130f322cb7e	1333	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
mbed_official	159:7130f322cb7e	1334
mbed_official	159:7130f322cb7e	1335	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
mbed_official	159:7130f322cb7e	1336	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
mbed_official	159:7130f322cb7e	1337
mbed_official	159:7130f322cb7e	1338	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
mbed_official	159:7130f322cb7e	1339	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
mbed_official	159:7130f322cb7e	1340
mbed_official	159:7130f322cb7e	1341	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
mbed_official	159:7130f322cb7e	1342	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
mbed_official	159:7130f322cb7e	1343
mbed_official	159:7130f322cb7e	1344	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
mbed_official	159:7130f322cb7e	1345	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
mbed_official	159:7130f322cb7e	1346
mbed_official	159:7130f322cb7e	1347	/* Floating-Point Context Address Register Definitions */
mbed_official	159:7130f322cb7e	1348	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
mbed_official	159:7130f322cb7e	1349	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
mbed_official	159:7130f322cb7e	1350
mbed_official	159:7130f322cb7e	1351	/* Floating-Point Default Status Control Register Definitions */
mbed_official	159:7130f322cb7e	1352	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
mbed_official	159:7130f322cb7e	1353	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
mbed_official	159:7130f322cb7e	1354
mbed_official	159:7130f322cb7e	1355	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
mbed_official	159:7130f322cb7e	1356	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
mbed_official	159:7130f322cb7e	1357
mbed_official	159:7130f322cb7e	1358	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
mbed_official	159:7130f322cb7e	1359	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
mbed_official	159:7130f322cb7e	1360
mbed_official	159:7130f322cb7e	1361	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
mbed_official	159:7130f322cb7e	1362	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
mbed_official	159:7130f322cb7e	1363
mbed_official	159:7130f322cb7e	1364	/* Media and FP Feature Register 0 Definitions */
mbed_official	159:7130f322cb7e	1365	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
mbed_official	159:7130f322cb7e	1366	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
mbed_official	159:7130f322cb7e	1367
mbed_official	159:7130f322cb7e	1368	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
mbed_official	159:7130f322cb7e	1369	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
mbed_official	159:7130f322cb7e	1370
mbed_official	159:7130f322cb7e	1371	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
mbed_official	159:7130f322cb7e	1372	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
mbed_official	159:7130f322cb7e	1373
mbed_official	159:7130f322cb7e	1374	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
mbed_official	159:7130f322cb7e	1375	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
mbed_official	159:7130f322cb7e	1376
mbed_official	159:7130f322cb7e	1377	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
mbed_official	159:7130f322cb7e	1378	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
mbed_official	159:7130f322cb7e	1379
mbed_official	159:7130f322cb7e	1380	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
mbed_official	159:7130f322cb7e	1381	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
mbed_official	159:7130f322cb7e	1382
mbed_official	159:7130f322cb7e	1383	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
mbed_official	159:7130f322cb7e	1384	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
mbed_official	159:7130f322cb7e	1385
mbed_official	159:7130f322cb7e	1386	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
mbed_official	159:7130f322cb7e	1387	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
mbed_official	159:7130f322cb7e	1388
mbed_official	159:7130f322cb7e	1389	/* Media and FP Feature Register 1 Definitions */
mbed_official	159:7130f322cb7e	1390	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
mbed_official	159:7130f322cb7e	1391	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
mbed_official	159:7130f322cb7e	1392
mbed_official	159:7130f322cb7e	1393	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
mbed_official	159:7130f322cb7e	1394	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
mbed_official	159:7130f322cb7e	1395
mbed_official	159:7130f322cb7e	1396	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
mbed_official	159:7130f322cb7e	1397	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
mbed_official	159:7130f322cb7e	1398
mbed_official	159:7130f322cb7e	1399	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
mbed_official	159:7130f322cb7e	1400	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
mbed_official	159:7130f322cb7e	1401
mbed_official	159:7130f322cb7e	1402	/@} end of group CMSIS_FPU /
mbed_official	159:7130f322cb7e	1403
mbed_official	159:7130f322cb7e	1404
mbed_official	159:7130f322cb7e	1405	/**
mbed_official	159:7130f322cb7e	1406	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	1407	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mbed_official	159:7130f322cb7e	1408	\brief Type definitions for the Core Debug Registers
mbed_official	159:7130f322cb7e	1409	@{
mbed_official	159:7130f322cb7e	1410	*/
mbed_official	159:7130f322cb7e	1411
mbed_official	159:7130f322cb7e	1412	/**
mbed_official	159:7130f322cb7e	1413	\brief Structure type to access the Core Debug Register (CoreDebug).
mbed_official	159:7130f322cb7e	1414	*/
mbed_official	159:7130f322cb7e	1415	typedef struct
mbed_official	159:7130f322cb7e	1416	{
mbed_official	159:7130f322cb7e	1417	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
mbed_official	159:7130f322cb7e	1418	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
mbed_official	159:7130f322cb7e	1419	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
mbed_official	159:7130f322cb7e	1420	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
mbed_official	159:7130f322cb7e	1421	} CoreDebug_Type;
mbed_official	159:7130f322cb7e	1422
mbed_official	159:7130f322cb7e	1423	/* Debug Halting Control and Status Register Definitions */
mbed_official	159:7130f322cb7e	1424	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
mbed_official	159:7130f322cb7e	1425	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
mbed_official	159:7130f322cb7e	1426
mbed_official	159:7130f322cb7e	1427	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
mbed_official	159:7130f322cb7e	1428	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
mbed_official	159:7130f322cb7e	1429
mbed_official	159:7130f322cb7e	1430	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
mbed_official	159:7130f322cb7e	1431	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
mbed_official	159:7130f322cb7e	1432
mbed_official	159:7130f322cb7e	1433	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
mbed_official	159:7130f322cb7e	1434	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
mbed_official	159:7130f322cb7e	1435
mbed_official	159:7130f322cb7e	1436	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
mbed_official	159:7130f322cb7e	1437	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
mbed_official	159:7130f322cb7e	1438
mbed_official	159:7130f322cb7e	1439	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
mbed_official	159:7130f322cb7e	1440	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
mbed_official	159:7130f322cb7e	1441
mbed_official	159:7130f322cb7e	1442	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
mbed_official	159:7130f322cb7e	1443	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
mbed_official	159:7130f322cb7e	1444
mbed_official	159:7130f322cb7e	1445	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
mbed_official	159:7130f322cb7e	1446	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
mbed_official	159:7130f322cb7e	1447
mbed_official	159:7130f322cb7e	1448	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
mbed_official	159:7130f322cb7e	1449	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
mbed_official	159:7130f322cb7e	1450
mbed_official	159:7130f322cb7e	1451	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
mbed_official	159:7130f322cb7e	1452	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
mbed_official	159:7130f322cb7e	1453
mbed_official	159:7130f322cb7e	1454	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
mbed_official	159:7130f322cb7e	1455	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
mbed_official	159:7130f322cb7e	1456
mbed_official	159:7130f322cb7e	1457	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
mbed_official	159:7130f322cb7e	1458	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
mbed_official	159:7130f322cb7e	1459
mbed_official	159:7130f322cb7e	1460	/* Debug Core Register Selector Register Definitions */
mbed_official	159:7130f322cb7e	1461	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
mbed_official	159:7130f322cb7e	1462	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
mbed_official	159:7130f322cb7e	1463
mbed_official	159:7130f322cb7e	1464	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
mbed_official	159:7130f322cb7e	1465	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
mbed_official	159:7130f322cb7e	1466
mbed_official	159:7130f322cb7e	1467	/* Debug Exception and Monitor Control Register Definitions */
mbed_official	159:7130f322cb7e	1468	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
mbed_official	159:7130f322cb7e	1469	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
mbed_official	159:7130f322cb7e	1470
mbed_official	159:7130f322cb7e	1471	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
mbed_official	159:7130f322cb7e	1472	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
mbed_official	159:7130f322cb7e	1473
mbed_official	159:7130f322cb7e	1474	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
mbed_official	159:7130f322cb7e	1475	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
mbed_official	159:7130f322cb7e	1476
mbed_official	159:7130f322cb7e	1477	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
mbed_official	159:7130f322cb7e	1478	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
mbed_official	159:7130f322cb7e	1479
mbed_official	159:7130f322cb7e	1480	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
mbed_official	159:7130f322cb7e	1481	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
mbed_official	159:7130f322cb7e	1482
mbed_official	159:7130f322cb7e	1483	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
mbed_official	159:7130f322cb7e	1484	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
mbed_official	159:7130f322cb7e	1485
mbed_official	159:7130f322cb7e	1486	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
mbed_official	159:7130f322cb7e	1487	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
mbed_official	159:7130f322cb7e	1488
mbed_official	159:7130f322cb7e	1489	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
mbed_official	159:7130f322cb7e	1490	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
mbed_official	159:7130f322cb7e	1491
mbed_official	159:7130f322cb7e	1492	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
mbed_official	159:7130f322cb7e	1493	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
mbed_official	159:7130f322cb7e	1494
mbed_official	159:7130f322cb7e	1495	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
mbed_official	159:7130f322cb7e	1496	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
mbed_official	159:7130f322cb7e	1497
mbed_official	159:7130f322cb7e	1498	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
mbed_official	159:7130f322cb7e	1499	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
mbed_official	159:7130f322cb7e	1500
mbed_official	159:7130f322cb7e	1501	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
mbed_official	159:7130f322cb7e	1502	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
mbed_official	159:7130f322cb7e	1503
mbed_official	159:7130f322cb7e	1504	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
mbed_official	159:7130f322cb7e	1505	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
mbed_official	159:7130f322cb7e	1506
mbed_official	159:7130f322cb7e	1507	/@} end of group CMSIS_CoreDebug /
mbed_official	159:7130f322cb7e	1508
mbed_official	159:7130f322cb7e	1509
mbed_official	159:7130f322cb7e	1510	/**
mbed_official	159:7130f322cb7e	1511	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	1512	\defgroup CMSIS_core_bitfield Core register bit field macros
mbed_official	159:7130f322cb7e	1513	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
mbed_official	159:7130f322cb7e	1514	@{
mbed_official	159:7130f322cb7e	1515	*/
mbed_official	159:7130f322cb7e	1516
mbed_official	159:7130f322cb7e	1517	/**
mbed_official	159:7130f322cb7e	1518	\brief Mask and shift a bit field value for use in a register bit range.
mbed_official	159:7130f322cb7e	1519	\param[in] field Name of the register bit field.
mbed_official	159:7130f322cb7e	1520	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
mbed_official	159:7130f322cb7e	1521	\return Masked and shifted value.
mbed_official	159:7130f322cb7e	1522	*/
mbed_official	159:7130f322cb7e	1523	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
mbed_official	159:7130f322cb7e	1524
mbed_official	159:7130f322cb7e	1525	/**
mbed_official	159:7130f322cb7e	1526	\brief Mask and shift a register value to extract a bit filed value.
mbed_official	159:7130f322cb7e	1527	\param[in] field Name of the register bit field.
mbed_official	159:7130f322cb7e	1528	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
mbed_official	159:7130f322cb7e	1529	\return Masked and shifted bit field value.
mbed_official	159:7130f322cb7e	1530	*/
mbed_official	159:7130f322cb7e	1531	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
mbed_official	159:7130f322cb7e	1532
mbed_official	159:7130f322cb7e	1533	/@} end of group CMSIS_core_bitfield /
mbed_official	159:7130f322cb7e	1534
mbed_official	159:7130f322cb7e	1535
mbed_official	159:7130f322cb7e	1536	/**
mbed_official	159:7130f322cb7e	1537	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	1538	\defgroup CMSIS_core_base Core Definitions
mbed_official	159:7130f322cb7e	1539	\brief Definitions for base addresses, unions, and structures.
mbed_official	159:7130f322cb7e	1540	@{
mbed_official	159:7130f322cb7e	1541	*/
mbed_official	159:7130f322cb7e	1542
mbed_official	159:7130f322cb7e	1543	/* Memory mapping of Core Hardware */
mbed_official	159:7130f322cb7e	1544	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
mbed_official	159:7130f322cb7e	1545	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
mbed_official	159:7130f322cb7e	1546	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
mbed_official	159:7130f322cb7e	1547	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
mbed_official	159:7130f322cb7e	1548	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
mbed_official	159:7130f322cb7e	1549	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
mbed_official	159:7130f322cb7e	1550	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
mbed_official	159:7130f322cb7e	1551	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
mbed_official	159:7130f322cb7e	1552
mbed_official	159:7130f322cb7e	1553	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
mbed_official	159:7130f322cb7e	1554	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
mbed_official	159:7130f322cb7e	1555	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
mbed_official	159:7130f322cb7e	1556	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
mbed_official	159:7130f322cb7e	1557	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
mbed_official	159:7130f322cb7e	1558	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
mbed_official	159:7130f322cb7e	1559	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
mbed_official	159:7130f322cb7e	1560	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
mbed_official	159:7130f322cb7e	1561
mbed_official	159:7130f322cb7e	1562	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
mbed_official	159:7130f322cb7e	1563	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
mbed_official	159:7130f322cb7e	1564	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
mbed_official	159:7130f322cb7e	1565	#endif
mbed_official	159:7130f322cb7e	1566
mbed_official	159:7130f322cb7e	1567	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
mbed_official	159:7130f322cb7e	1568	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
mbed_official	159:7130f322cb7e	1569
mbed_official	159:7130f322cb7e	1570	/@} /
mbed_official	159:7130f322cb7e	1571
mbed_official	159:7130f322cb7e	1572
mbed_official	159:7130f322cb7e	1573
mbed_official	159:7130f322cb7e	1574	/*******************************************************************************
mbed_official	159:7130f322cb7e	1575	* Hardware Abstraction Layer
mbed_official	159:7130f322cb7e	1576	Core Function Interface contains:
mbed_official	159:7130f322cb7e	1577	- Core NVIC Functions
mbed_official	159:7130f322cb7e	1578	- Core SysTick Functions
mbed_official	159:7130f322cb7e	1579	- Core Debug Functions
mbed_official	159:7130f322cb7e	1580	- Core Register Access Functions
mbed_official	159:7130f322cb7e	1581	******************************************************************************/
mbed_official	159:7130f322cb7e	1582	/**
mbed_official	159:7130f322cb7e	1583	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mbed_official	159:7130f322cb7e	1584	*/
mbed_official	159:7130f322cb7e	1585
mbed_official	159:7130f322cb7e	1586
mbed_official	159:7130f322cb7e	1587
mbed_official	159:7130f322cb7e	1588	/* ########################## NVIC functions #################################### */
mbed_official	159:7130f322cb7e	1589	/**
mbed_official	159:7130f322cb7e	1590	\ingroup CMSIS_Core_FunctionInterface
mbed_official	159:7130f322cb7e	1591	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
mbed_official	159:7130f322cb7e	1592	\brief Functions that manage interrupts and exceptions via the NVIC.
mbed_official	159:7130f322cb7e	1593	@{
mbed_official	159:7130f322cb7e	1594	*/
mbed_official	159:7130f322cb7e	1595
mbed_official	159:7130f322cb7e	1596	#ifdef CMSIS_NVIC_VIRTUAL
mbed_official	159:7130f322cb7e	1597	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
mbed_official	159:7130f322cb7e	1598	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
mbed_official	159:7130f322cb7e	1599	#endif
mbed_official	159:7130f322cb7e	1600	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
mbed_official	159:7130f322cb7e	1601	#else
mbed_official	159:7130f322cb7e	1602	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
mbed_official	159:7130f322cb7e	1603	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
mbed_official	159:7130f322cb7e	1604	#define NVIC_EnableIRQ __NVIC_EnableIRQ
mbed_official	159:7130f322cb7e	1605	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
mbed_official	159:7130f322cb7e	1606	#define NVIC_DisableIRQ __NVIC_DisableIRQ
mbed_official	159:7130f322cb7e	1607	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
mbed_official	159:7130f322cb7e	1608	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
mbed_official	159:7130f322cb7e	1609	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
mbed_official	159:7130f322cb7e	1610	#define NVIC_GetActive __NVIC_GetActive
mbed_official	159:7130f322cb7e	1611	#define NVIC_SetPriority __NVIC_SetPriority
mbed_official	159:7130f322cb7e	1612	#define NVIC_GetPriority __NVIC_GetPriority
mbed_official	159:7130f322cb7e	1613	#define NVIC_SystemReset __NVIC_SystemReset
mbed_official	159:7130f322cb7e	1614	#endif /* CMSIS_NVIC_VIRTUAL */
mbed_official	159:7130f322cb7e	1615
mbed_official	159:7130f322cb7e	1616	#ifdef CMSIS_VECTAB_VIRTUAL
mbed_official	159:7130f322cb7e	1617	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
mbed_official	159:7130f322cb7e	1618	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
mbed_official	159:7130f322cb7e	1619	#endif
mbed_official	159:7130f322cb7e	1620	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
mbed_official	159:7130f322cb7e	1621	#else
mbed_official	159:7130f322cb7e	1622	#define NVIC_SetVector __NVIC_SetVector
mbed_official	159:7130f322cb7e	1623	#define NVIC_GetVector __NVIC_GetVector
mbed_official	159:7130f322cb7e	1624	#endif /* (CMSIS_VECTAB_VIRTUAL) */
mbed_official	159:7130f322cb7e	1625
mbed_official	159:7130f322cb7e	1626	#define NVIC_USER_IRQ_OFFSET 16
mbed_official	159:7130f322cb7e	1627
mbed_official	159:7130f322cb7e	1628
mbed_official	159:7130f322cb7e	1629
mbed_official	159:7130f322cb7e	1630	/**
mbed_official	159:7130f322cb7e	1631	\brief Set Priority Grouping
mbed_official	159:7130f322cb7e	1632	\details Sets the priority grouping field using the required unlock sequence.
mbed_official	159:7130f322cb7e	1633	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
mbed_official	159:7130f322cb7e	1634	Only values from 0..7 are used.
mbed_official	159:7130f322cb7e	1635	In case of a conflict between priority grouping and available
mbed_official	159:7130f322cb7e	1636	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
mbed_official	159:7130f322cb7e	1637	\param [in] PriorityGroup Priority grouping field.
mbed_official	159:7130f322cb7e	1638	*/
mbed_official	159:7130f322cb7e	1639	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
mbed_official	159:7130f322cb7e	1640	{
mbed_official	159:7130f322cb7e	1641	uint32_t reg_value;
mbed_official	159:7130f322cb7e	1642	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mbed_official	159:7130f322cb7e	1643
mbed_official	159:7130f322cb7e	1644	reg_value = SCB->AIRCR; /* read old register configuration */
mbed_official	159:7130f322cb7e	1645	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
mbed_official	159:7130f322cb7e	1646	reg_value = (reg_value \|
mbed_official	159:7130f322cb7e	1647	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
mbed_official	159:7130f322cb7e	1648	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
mbed_official	159:7130f322cb7e	1649	SCB->AIRCR = reg_value;
mbed_official	159:7130f322cb7e	1650	}
mbed_official	159:7130f322cb7e	1651
mbed_official	159:7130f322cb7e	1652
mbed_official	159:7130f322cb7e	1653	/**
mbed_official	159:7130f322cb7e	1654	\brief Get Priority Grouping
mbed_official	159:7130f322cb7e	1655	\details Reads the priority grouping field from the NVIC Interrupt Controller.
mbed_official	159:7130f322cb7e	1656	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
mbed_official	159:7130f322cb7e	1657	*/
mbed_official	159:7130f322cb7e	1658	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
mbed_official	159:7130f322cb7e	1659	{
mbed_official	159:7130f322cb7e	1660	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
mbed_official	159:7130f322cb7e	1661	}
mbed_official	159:7130f322cb7e	1662
mbed_official	159:7130f322cb7e	1663
mbed_official	159:7130f322cb7e	1664	/**
mbed_official	159:7130f322cb7e	1665	\brief Enable Interrupt
mbed_official	159:7130f322cb7e	1666	\details Enables a device specific interrupt in the NVIC interrupt controller.
mbed_official	159:7130f322cb7e	1667	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1668	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1669	*/
mbed_official	159:7130f322cb7e	1670	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1671	{
mbed_official	159:7130f322cb7e	1672	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1673	{
mbed_official	159:7130f322cb7e	1674	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official	159:7130f322cb7e	1675	}
mbed_official	159:7130f322cb7e	1676	}
mbed_official	159:7130f322cb7e	1677
mbed_official	159:7130f322cb7e	1678
mbed_official	159:7130f322cb7e	1679	/**
mbed_official	159:7130f322cb7e	1680	\brief Get Interrupt Enable status
mbed_official	159:7130f322cb7e	1681	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
mbed_official	159:7130f322cb7e	1682	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1683	\return 0 Interrupt is not enabled.
mbed_official	159:7130f322cb7e	1684	\return 1 Interrupt is enabled.
mbed_official	159:7130f322cb7e	1685	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1686	*/
mbed_official	159:7130f322cb7e	1687	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1688	{
mbed_official	159:7130f322cb7e	1689	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1690	{
mbed_official	159:7130f322cb7e	1691	return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official	159:7130f322cb7e	1692	}
mbed_official	159:7130f322cb7e	1693	else
mbed_official	159:7130f322cb7e	1694	{
mbed_official	159:7130f322cb7e	1695	return(0U);
mbed_official	159:7130f322cb7e	1696	}
mbed_official	159:7130f322cb7e	1697	}
mbed_official	159:7130f322cb7e	1698
mbed_official	159:7130f322cb7e	1699
mbed_official	159:7130f322cb7e	1700	/**
mbed_official	159:7130f322cb7e	1701	\brief Disable Interrupt
mbed_official	159:7130f322cb7e	1702	\details Disables a device specific interrupt in the NVIC interrupt controller.
mbed_official	159:7130f322cb7e	1703	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1704	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1705	*/
mbed_official	159:7130f322cb7e	1706	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1707	{
mbed_official	159:7130f322cb7e	1708	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1709	{
mbed_official	159:7130f322cb7e	1710	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official	159:7130f322cb7e	1711	__DSB();
mbed_official	159:7130f322cb7e	1712	__ISB();
mbed_official	159:7130f322cb7e	1713	}
mbed_official	159:7130f322cb7e	1714	}
mbed_official	159:7130f322cb7e	1715
mbed_official	159:7130f322cb7e	1716
mbed_official	159:7130f322cb7e	1717	/**
mbed_official	159:7130f322cb7e	1718	\brief Get Pending Interrupt
mbed_official	159:7130f322cb7e	1719	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
mbed_official	159:7130f322cb7e	1720	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1721	\return 0 Interrupt status is not pending.
mbed_official	159:7130f322cb7e	1722	\return 1 Interrupt status is pending.
mbed_official	159:7130f322cb7e	1723	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1724	*/
mbed_official	159:7130f322cb7e	1725	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1726	{
mbed_official	159:7130f322cb7e	1727	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1728	{
mbed_official	159:7130f322cb7e	1729	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official	159:7130f322cb7e	1730	}
mbed_official	159:7130f322cb7e	1731	else
mbed_official	159:7130f322cb7e	1732	{
mbed_official	159:7130f322cb7e	1733	return(0U);
mbed_official	159:7130f322cb7e	1734	}
mbed_official	159:7130f322cb7e	1735	}
mbed_official	159:7130f322cb7e	1736
mbed_official	159:7130f322cb7e	1737
mbed_official	159:7130f322cb7e	1738	/**
mbed_official	159:7130f322cb7e	1739	\brief Set Pending Interrupt
mbed_official	159:7130f322cb7e	1740	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
mbed_official	159:7130f322cb7e	1741	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1742	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1743	*/
mbed_official	159:7130f322cb7e	1744	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1745	{
mbed_official	159:7130f322cb7e	1746	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1747	{
mbed_official	159:7130f322cb7e	1748	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official	159:7130f322cb7e	1749	}
mbed_official	159:7130f322cb7e	1750	}
mbed_official	159:7130f322cb7e	1751
mbed_official	159:7130f322cb7e	1752
mbed_official	159:7130f322cb7e	1753	/**
mbed_official	159:7130f322cb7e	1754	\brief Clear Pending Interrupt
mbed_official	159:7130f322cb7e	1755	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
mbed_official	159:7130f322cb7e	1756	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1757	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1758	*/
mbed_official	159:7130f322cb7e	1759	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1760	{
mbed_official	159:7130f322cb7e	1761	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1762	{
mbed_official	159:7130f322cb7e	1763	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official	159:7130f322cb7e	1764	}
mbed_official	159:7130f322cb7e	1765	}
mbed_official	159:7130f322cb7e	1766
mbed_official	159:7130f322cb7e	1767
mbed_official	159:7130f322cb7e	1768	/**
mbed_official	159:7130f322cb7e	1769	\brief Get Active Interrupt
mbed_official	159:7130f322cb7e	1770	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
mbed_official	159:7130f322cb7e	1771	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1772	\return 0 Interrupt status is not active.
mbed_official	159:7130f322cb7e	1773	\return 1 Interrupt status is active.
mbed_official	159:7130f322cb7e	1774	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1775	*/
mbed_official	159:7130f322cb7e	1776	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1777	{
mbed_official	159:7130f322cb7e	1778	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1779	{
mbed_official	159:7130f322cb7e	1780	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official	159:7130f322cb7e	1781	}
mbed_official	159:7130f322cb7e	1782	else
mbed_official	159:7130f322cb7e	1783	{
mbed_official	159:7130f322cb7e	1784	return(0U);
mbed_official	159:7130f322cb7e	1785	}
mbed_official	159:7130f322cb7e	1786	}
mbed_official	159:7130f322cb7e	1787
mbed_official	159:7130f322cb7e	1788
mbed_official	159:7130f322cb7e	1789	/**
mbed_official	159:7130f322cb7e	1790	\brief Set Interrupt Priority
mbed_official	159:7130f322cb7e	1791	\details Sets the priority of a device specific interrupt or a processor exception.
mbed_official	159:7130f322cb7e	1792	The interrupt number can be positive to specify a device specific interrupt,
mbed_official	159:7130f322cb7e	1793	or negative to specify a processor exception.
mbed_official	159:7130f322cb7e	1794	\param [in] IRQn Interrupt number.
mbed_official	159:7130f322cb7e	1795	\param [in] priority Priority to set.
mbed_official	159:7130f322cb7e	1796	\note The priority cannot be set for every processor exception.
mbed_official	159:7130f322cb7e	1797	*/
mbed_official	159:7130f322cb7e	1798	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mbed_official	159:7130f322cb7e	1799	{
mbed_official	159:7130f322cb7e	1800	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1801	{
mbed_official	159:7130f322cb7e	1802	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
mbed_official	159:7130f322cb7e	1803	}
mbed_official	159:7130f322cb7e	1804	else
mbed_official	159:7130f322cb7e	1805	{
mbed_official	159:7130f322cb7e	1806	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
mbed_official	159:7130f322cb7e	1807	}
mbed_official	159:7130f322cb7e	1808	}
mbed_official	159:7130f322cb7e	1809
mbed_official	159:7130f322cb7e	1810
mbed_official	159:7130f322cb7e	1811	/**
mbed_official	159:7130f322cb7e	1812	\brief Get Interrupt Priority
mbed_official	159:7130f322cb7e	1813	\details Reads the priority of a device specific interrupt or a processor exception.
mbed_official	159:7130f322cb7e	1814	The interrupt number can be positive to specify a device specific interrupt,
mbed_official	159:7130f322cb7e	1815	or negative to specify a processor exception.
mbed_official	159:7130f322cb7e	1816	\param [in] IRQn Interrupt number.
mbed_official	159:7130f322cb7e	1817	\return Interrupt Priority.
mbed_official	159:7130f322cb7e	1818	Value is aligned automatically to the implemented priority bits of the microcontroller.
mbed_official	159:7130f322cb7e	1819	*/
mbed_official	159:7130f322cb7e	1820	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1821	{
mbed_official	159:7130f322cb7e	1822
mbed_official	159:7130f322cb7e	1823	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1824	{
mbed_official	159:7130f322cb7e	1825	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
mbed_official	159:7130f322cb7e	1826	}
mbed_official	159:7130f322cb7e	1827	else
mbed_official	159:7130f322cb7e	1828	{
mbed_official	159:7130f322cb7e	1829	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
mbed_official	159:7130f322cb7e	1830	}
mbed_official	159:7130f322cb7e	1831	}
mbed_official	159:7130f322cb7e	1832
mbed_official	159:7130f322cb7e	1833
mbed_official	159:7130f322cb7e	1834	/**
mbed_official	159:7130f322cb7e	1835	\brief Encode Priority
mbed_official	159:7130f322cb7e	1836	\details Encodes the priority for an interrupt with the given priority group,
mbed_official	159:7130f322cb7e	1837	preemptive priority value, and subpriority value.
mbed_official	159:7130f322cb7e	1838	In case of a conflict between priority grouping and available
mbed_official	159:7130f322cb7e	1839	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
mbed_official	159:7130f322cb7e	1840	\param [in] PriorityGroup Used priority group.
mbed_official	159:7130f322cb7e	1841	\param [in] PreemptPriority Preemptive priority value (starting from 0).
mbed_official	159:7130f322cb7e	1842	\param [in] SubPriority Subpriority value (starting from 0).
mbed_official	159:7130f322cb7e	1843	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
mbed_official	159:7130f322cb7e	1844	*/
mbed_official	159:7130f322cb7e	1845	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
mbed_official	159:7130f322cb7e	1846	{
mbed_official	159:7130f322cb7e	1847	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mbed_official	159:7130f322cb7e	1848	uint32_t PreemptPriorityBits;
mbed_official	159:7130f322cb7e	1849	uint32_t SubPriorityBits;
mbed_official	159:7130f322cb7e	1850
mbed_official	159:7130f322cb7e	1851	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
mbed_official	159:7130f322cb7e	1852	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
mbed_official	159:7130f322cb7e	1853
mbed_official	159:7130f322cb7e	1854	return (
mbed_official	159:7130f322cb7e	1855	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
mbed_official	159:7130f322cb7e	1856	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
mbed_official	159:7130f322cb7e	1857	);
mbed_official	159:7130f322cb7e	1858	}
mbed_official	159:7130f322cb7e	1859
mbed_official	159:7130f322cb7e	1860
mbed_official	159:7130f322cb7e	1861	/**
mbed_official	159:7130f322cb7e	1862	\brief Decode Priority
mbed_official	159:7130f322cb7e	1863	\details Decodes an interrupt priority value with a given priority group to
mbed_official	159:7130f322cb7e	1864	preemptive priority value and subpriority value.
mbed_official	159:7130f322cb7e	1865	In case of a conflict between priority grouping and available
mbed_official	159:7130f322cb7e	1866	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
mbed_official	159:7130f322cb7e	1867	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
mbed_official	159:7130f322cb7e	1868	\param [in] PriorityGroup Used priority group.
mbed_official	159:7130f322cb7e	1869	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
mbed_official	159:7130f322cb7e	1870	\param [out] pSubPriority Subpriority value (starting from 0).
mbed_official	159:7130f322cb7e	1871	*/
mbed_official	159:7130f322cb7e	1872	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
mbed_official	159:7130f322cb7e	1873	{
mbed_official	159:7130f322cb7e	1874	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mbed_official	159:7130f322cb7e	1875	uint32_t PreemptPriorityBits;
mbed_official	159:7130f322cb7e	1876	uint32_t SubPriorityBits;
mbed_official	159:7130f322cb7e	1877
mbed_official	159:7130f322cb7e	1878	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
mbed_official	159:7130f322cb7e	1879	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
mbed_official	159:7130f322cb7e	1880
mbed_official	159:7130f322cb7e	1881	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
mbed_official	159:7130f322cb7e	1882	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
mbed_official	159:7130f322cb7e	1883	}
mbed_official	159:7130f322cb7e	1884
mbed_official	159:7130f322cb7e	1885
mbed_official	159:7130f322cb7e	1886	/**
mbed_official	159:7130f322cb7e	1887	\brief Set Interrupt Vector
mbed_official	159:7130f322cb7e	1888	\details Sets an interrupt vector in SRAM based interrupt vector table.
mbed_official	159:7130f322cb7e	1889	The interrupt number can be positive to specify a device specific interrupt,
mbed_official	159:7130f322cb7e	1890	or negative to specify a processor exception.
mbed_official	159:7130f322cb7e	1891	VTOR must been relocated to SRAM before.
mbed_official	159:7130f322cb7e	1892	\param [in] IRQn Interrupt number
mbed_official	159:7130f322cb7e	1893	\param [in] vector Address of interrupt handler function
mbed_official	159:7130f322cb7e	1894	*/
mbed_official	159:7130f322cb7e	1895	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
mbed_official	159:7130f322cb7e	1896	{
mbed_official	159:7130f322cb7e	1897	uint32_t vectors = (uint32_t )SCB->VTOR;
mbed_official	159:7130f322cb7e	1898	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
mbed_official	159:7130f322cb7e	1899	}
mbed_official	159:7130f322cb7e	1900
mbed_official	159:7130f322cb7e	1901
mbed_official	159:7130f322cb7e	1902	/**
mbed_official	159:7130f322cb7e	1903	\brief Get Interrupt Vector
mbed_official	159:7130f322cb7e	1904	\details Reads an interrupt vector from interrupt vector table.
mbed_official	159:7130f322cb7e	1905	The interrupt number can be positive to specify a device specific interrupt,
mbed_official	159:7130f322cb7e	1906	or negative to specify a processor exception.
mbed_official	159:7130f322cb7e	1907	\param [in] IRQn Interrupt number.
mbed_official	159:7130f322cb7e	1908	\return Address of interrupt handler function
mbed_official	159:7130f322cb7e	1909	*/
mbed_official	159:7130f322cb7e	1910	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1911	{
mbed_official	159:7130f322cb7e	1912	uint32_t vectors = (uint32_t )SCB->VTOR;
mbed_official	159:7130f322cb7e	1913	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
mbed_official	159:7130f322cb7e	1914	}
mbed_official	159:7130f322cb7e	1915
mbed_official	159:7130f322cb7e	1916
mbed_official	159:7130f322cb7e	1917	/**
mbed_official	159:7130f322cb7e	1918	\brief System Reset
mbed_official	159:7130f322cb7e	1919	\details Initiates a system reset request to reset the MCU.
mbed_official	159:7130f322cb7e	1920	*/
mbed_official	159:7130f322cb7e	1921	__STATIC_INLINE void __NVIC_SystemReset(void)
mbed_official	159:7130f322cb7e	1922	{
mbed_official	159:7130f322cb7e	1923	__DSB(); /* Ensure all outstanding memory accesses included
mbed_official	159:7130f322cb7e	1924	buffered write are completed before reset */
mbed_official	159:7130f322cb7e	1925	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
mbed_official	159:7130f322cb7e	1926	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
mbed_official	159:7130f322cb7e	1927	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
mbed_official	159:7130f322cb7e	1928	__DSB(); /* Ensure completion of memory access */
mbed_official	159:7130f322cb7e	1929
mbed_official	159:7130f322cb7e	1930	for(;;) /* wait until reset */
mbed_official	159:7130f322cb7e	1931	{
mbed_official	159:7130f322cb7e	1932	__NOP();
mbed_official	159:7130f322cb7e	1933	}
mbed_official	159:7130f322cb7e	1934	}
mbed_official	159:7130f322cb7e	1935
mbed_official	159:7130f322cb7e	1936	/@} end of CMSIS_Core_NVICFunctions /
mbed_official	159:7130f322cb7e	1937
mbed_official	159:7130f322cb7e	1938
mbed_official	159:7130f322cb7e	1939	/* ########################## FPU functions #################################### */
mbed_official	159:7130f322cb7e	1940	/**
mbed_official	159:7130f322cb7e	1941	\ingroup CMSIS_Core_FunctionInterface
mbed_official	159:7130f322cb7e	1942	\defgroup CMSIS_Core_FpuFunctions FPU Functions
mbed_official	159:7130f322cb7e	1943	\brief Function that provides FPU type.
mbed_official	159:7130f322cb7e	1944	@{
mbed_official	159:7130f322cb7e	1945	*/
mbed_official	159:7130f322cb7e	1946
mbed_official	159:7130f322cb7e	1947	/**
mbed_official	159:7130f322cb7e	1948	\brief get FPU type
mbed_official	159:7130f322cb7e	1949	\details returns the FPU type
mbed_official	159:7130f322cb7e	1950	\returns
mbed_official	159:7130f322cb7e	1951	- \b 0: No FPU
mbed_official	159:7130f322cb7e	1952	- \b 1: Single precision FPU
mbed_official	159:7130f322cb7e	1953	- \b 2: Double + Single precision FPU
mbed_official	159:7130f322cb7e	1954	*/
mbed_official	159:7130f322cb7e	1955	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
mbed_official	159:7130f322cb7e	1956	{
mbed_official	159:7130f322cb7e	1957	uint32_t mvfr0;
mbed_official	159:7130f322cb7e	1958
mbed_official	159:7130f322cb7e	1959	mvfr0 = FPU->MVFR0;
mbed_official	159:7130f322cb7e	1960	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
mbed_official	159:7130f322cb7e	1961	{
mbed_official	159:7130f322cb7e	1962	return 1U; /* Single precision FPU */
mbed_official	159:7130f322cb7e	1963	}
mbed_official	159:7130f322cb7e	1964	else
mbed_official	159:7130f322cb7e	1965	{
mbed_official	159:7130f322cb7e	1966	return 0U; /* No FPU */
mbed_official	159:7130f322cb7e	1967	}
mbed_official	159:7130f322cb7e	1968	}
mbed_official	159:7130f322cb7e	1969
mbed_official	159:7130f322cb7e	1970
mbed_official	159:7130f322cb7e	1971	/@} end of CMSIS_Core_FpuFunctions /
mbed_official	159:7130f322cb7e	1972
mbed_official	159:7130f322cb7e	1973
mbed_official	159:7130f322cb7e	1974
mbed_official	159:7130f322cb7e	1975	/* ################################## SysTick function ############################################ */
mbed_official	159:7130f322cb7e	1976	/**
mbed_official	159:7130f322cb7e	1977	\ingroup CMSIS_Core_FunctionInterface
mbed_official	159:7130f322cb7e	1978	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mbed_official	159:7130f322cb7e	1979	\brief Functions that configure the System.
mbed_official	159:7130f322cb7e	1980	@{
mbed_official	159:7130f322cb7e	1981	*/
mbed_official	159:7130f322cb7e	1982
mbed_official	159:7130f322cb7e	1983	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
mbed_official	159:7130f322cb7e	1984
mbed_official	159:7130f322cb7e	1985	/**
mbed_official	159:7130f322cb7e	1986	\brief System Tick Configuration
mbed_official	159:7130f322cb7e	1987	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
mbed_official	159:7130f322cb7e	1988	Counter is in free running mode to generate periodic interrupts.
mbed_official	159:7130f322cb7e	1989	\param [in] ticks Number of ticks between two interrupts.
mbed_official	159:7130f322cb7e	1990	\return 0 Function succeeded.
mbed_official	159:7130f322cb7e	1991	\return 1 Function failed.
mbed_official	159:7130f322cb7e	1992	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mbed_official	159:7130f322cb7e	1993	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mbed_official	159:7130f322cb7e	1994	must contain a vendor-specific implementation of this function.
mbed_official	159:7130f322cb7e	1995	*/
mbed_official	159:7130f322cb7e	1996	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mbed_official	159:7130f322cb7e	1997	{
mbed_official	159:7130f322cb7e	1998	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
mbed_official	159:7130f322cb7e	1999	{
mbed_official	159:7130f322cb7e	2000	return (1UL); /* Reload value impossible */
mbed_official	159:7130f322cb7e	2001	}
mbed_official	159:7130f322cb7e	2002
mbed_official	159:7130f322cb7e	2003	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
mbed_official	159:7130f322cb7e	2004	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
mbed_official	159:7130f322cb7e	2005	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
mbed_official	159:7130f322cb7e	2006	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
mbed_official	159:7130f322cb7e	2007	SysTick_CTRL_TICKINT_Msk \|
mbed_official	159:7130f322cb7e	2008	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mbed_official	159:7130f322cb7e	2009	return (0UL); /* Function successful */
mbed_official	159:7130f322cb7e	2010	}
mbed_official	159:7130f322cb7e	2011
mbed_official	159:7130f322cb7e	2012	#endif
mbed_official	159:7130f322cb7e	2013
mbed_official	159:7130f322cb7e	2014	/@} end of CMSIS_Core_SysTickFunctions /
mbed_official	159:7130f322cb7e	2015
mbed_official	159:7130f322cb7e	2016
mbed_official	159:7130f322cb7e	2017
mbed_official	159:7130f322cb7e	2018	/* ##################################### Debug In/Output function ########################################### */
mbed_official	159:7130f322cb7e	2019	/**
mbed_official	159:7130f322cb7e	2020	\ingroup CMSIS_Core_FunctionInterface
mbed_official	159:7130f322cb7e	2021	\defgroup CMSIS_core_DebugFunctions ITM Functions
mbed_official	159:7130f322cb7e	2022	\brief Functions that access the ITM debug interface.
mbed_official	159:7130f322cb7e	2023	@{
mbed_official	159:7130f322cb7e	2024	*/
mbed_official	159:7130f322cb7e	2025
mbed_official	159:7130f322cb7e	2026	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
mbed_official	159:7130f322cb7e	2027	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
mbed_official	159:7130f322cb7e	2028
mbed_official	159:7130f322cb7e	2029
mbed_official	159:7130f322cb7e	2030	/**
mbed_official	159:7130f322cb7e	2031	\brief ITM Send Character
mbed_official	159:7130f322cb7e	2032	\details Transmits a character via the ITM channel 0, and
mbed_official	159:7130f322cb7e	2033	\li Just returns when no debugger is connected that has booked the output.
mbed_official	159:7130f322cb7e	2034	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
mbed_official	159:7130f322cb7e	2035	\param [in] ch Character to transmit.
mbed_official	159:7130f322cb7e	2036	\returns Character to transmit.
mbed_official	159:7130f322cb7e	2037	*/
mbed_official	159:7130f322cb7e	2038	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
mbed_official	159:7130f322cb7e	2039	{
mbed_official	159:7130f322cb7e	2040	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
mbed_official	159:7130f322cb7e	2041	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
mbed_official	159:7130f322cb7e	2042	{
mbed_official	159:7130f322cb7e	2043	while (ITM->PORT[0U].u32 == 0UL)
mbed_official	159:7130f322cb7e	2044	{
mbed_official	159:7130f322cb7e	2045	__NOP();
mbed_official	159:7130f322cb7e	2046	}
mbed_official	159:7130f322cb7e	2047	ITM->PORT[0U].u8 = (uint8_t)ch;
mbed_official	159:7130f322cb7e	2048	}
mbed_official	159:7130f322cb7e	2049	return (ch);
mbed_official	159:7130f322cb7e	2050	}
mbed_official	159:7130f322cb7e	2051
mbed_official	159:7130f322cb7e	2052
mbed_official	159:7130f322cb7e	2053	/**
mbed_official	159:7130f322cb7e	2054	\brief ITM Receive Character
mbed_official	159:7130f322cb7e	2055	\details Inputs a character via the external variable \ref ITM_RxBuffer.
mbed_official	159:7130f322cb7e	2056	\return Received character.
mbed_official	159:7130f322cb7e	2057	\return -1 No character pending.
mbed_official	159:7130f322cb7e	2058	*/
mbed_official	159:7130f322cb7e	2059	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
mbed_official	159:7130f322cb7e	2060	{
mbed_official	159:7130f322cb7e	2061	int32_t ch = -1; /* no character available */
mbed_official	159:7130f322cb7e	2062
mbed_official	159:7130f322cb7e	2063	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
mbed_official	159:7130f322cb7e	2064	{
mbed_official	159:7130f322cb7e	2065	ch = ITM_RxBuffer;
mbed_official	159:7130f322cb7e	2066	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
mbed_official	159:7130f322cb7e	2067	}
mbed_official	159:7130f322cb7e	2068
mbed_official	159:7130f322cb7e	2069	return (ch);
mbed_official	159:7130f322cb7e	2070	}
mbed_official	159:7130f322cb7e	2071
mbed_official	159:7130f322cb7e	2072
mbed_official	159:7130f322cb7e	2073	/**
mbed_official	159:7130f322cb7e	2074	\brief ITM Check Character
mbed_official	159:7130f322cb7e	2075	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
mbed_official	159:7130f322cb7e	2076	\return 0 No character available.
mbed_official	159:7130f322cb7e	2077	\return 1 Character available.
mbed_official	159:7130f322cb7e	2078	*/
mbed_official	159:7130f322cb7e	2079	__STATIC_INLINE int32_t ITM_CheckChar (void)
mbed_official	159:7130f322cb7e	2080	{
mbed_official	159:7130f322cb7e	2081
mbed_official	159:7130f322cb7e	2082	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
mbed_official	159:7130f322cb7e	2083	{
mbed_official	159:7130f322cb7e	2084	return (0); /* no character available */
mbed_official	159:7130f322cb7e	2085	}
mbed_official	159:7130f322cb7e	2086	else
mbed_official	159:7130f322cb7e	2087	{
mbed_official	159:7130f322cb7e	2088	return (1); /* character available */
mbed_official	159:7130f322cb7e	2089	}
mbed_official	159:7130f322cb7e	2090	}
mbed_official	159:7130f322cb7e	2091
mbed_official	159:7130f322cb7e	2092	/@} end of CMSIS_core_DebugFunctions /
mbed_official	159:7130f322cb7e	2093
mbed_official	159:7130f322cb7e	2094
mbed_official	159:7130f322cb7e	2095
mbed_official	159:7130f322cb7e	2096
mbed_official	159:7130f322cb7e	2097	#ifdef __cplusplus
mbed_official	159:7130f322cb7e	2098	}
mbed_official	159:7130f322cb7e	2099	#endif
mbed_official	159:7130f322cb7e	2100
mbed_official	159:7130f322cb7e	2101	#endif /* __CORE_CM4_H_DEPENDANT */
mbed_official	159:7130f322cb7e	2102
mbed_official	159:7130f322cb7e	2103	#endif /* __CMSIS_GENERIC */