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TARGET_SAKURAIO_EVB_01/core_cm33.h@159:7130f322cb7e, 2017-12-21 (annotated)

Committer:
mbed_official
Date:
Thu Dec 21 18:20:02 2017 +0000
Revision:
159:7130f322cb7e
mbed library version 157

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 159:7130f322cb7e 1 /**************************************************************************//**
mbed_official 159:7130f322cb7e 2 * @file core_cm33.h
mbed_official 159:7130f322cb7e 3 * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
mbed_official 159:7130f322cb7e 4 * @version V5.0.2
mbed_official 159:7130f322cb7e 5 * @date 13. February 2017
mbed_official 159:7130f322cb7e 6 ******************************************************************************/
mbed_official 159:7130f322cb7e 7 /*
mbed_official 159:7130f322cb7e 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
mbed_official 159:7130f322cb7e 9 *
mbed_official 159:7130f322cb7e 10 * SPDX-License-Identifier: Apache-2.0
mbed_official 159:7130f322cb7e 11 *
mbed_official 159:7130f322cb7e 12 * Licensed under the Apache License, Version 2.0 (the License); you may
mbed_official 159:7130f322cb7e 13 * not use this file except in compliance with the License.
mbed_official 159:7130f322cb7e 14 * You may obtain a copy of the License at
mbed_official 159:7130f322cb7e 15 *
mbed_official 159:7130f322cb7e 16 * www.apache.org/licenses/LICENSE-2.0
mbed_official 159:7130f322cb7e 17 *
mbed_official 159:7130f322cb7e 18 * Unless required by applicable law or agreed to in writing, software
mbed_official 159:7130f322cb7e 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
mbed_official 159:7130f322cb7e 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 159:7130f322cb7e 21 * See the License for the specific language governing permissions and
mbed_official 159:7130f322cb7e 22 * limitations under the License.
mbed_official 159:7130f322cb7e 23 */
mbed_official 159:7130f322cb7e 24
mbed_official 159:7130f322cb7e 25 #if defined ( __ICCARM__ )
mbed_official 159:7130f322cb7e 26 #pragma system_include /* treat file as system include file for MISRA check */
mbed_official 159:7130f322cb7e 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
mbed_official 159:7130f322cb7e 28 #pragma clang system_header /* treat file as system include file */
mbed_official 159:7130f322cb7e 29 #endif
mbed_official 159:7130f322cb7e 30
mbed_official 159:7130f322cb7e 31 #ifndef __CORE_CM33_H_GENERIC
mbed_official 159:7130f322cb7e 32 #define __CORE_CM33_H_GENERIC
mbed_official 159:7130f322cb7e 33
mbed_official 159:7130f322cb7e 34 #include <stdint.h>
mbed_official 159:7130f322cb7e 35
mbed_official 159:7130f322cb7e 36 #ifdef __cplusplus
mbed_official 159:7130f322cb7e 37 extern "C" {
mbed_official 159:7130f322cb7e 38 #endif
mbed_official 159:7130f322cb7e 39
mbed_official 159:7130f322cb7e 40 /**
mbed_official 159:7130f322cb7e 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mbed_official 159:7130f322cb7e 42 CMSIS violates the following MISRA-C:2004 rules:
mbed_official 159:7130f322cb7e 43
mbed_official 159:7130f322cb7e 44 \li Required Rule 8.5, object/function definition in header file.<br>
mbed_official 159:7130f322cb7e 45 Function definitions in header files are used to allow 'inlining'.
mbed_official 159:7130f322cb7e 46
mbed_official 159:7130f322cb7e 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mbed_official 159:7130f322cb7e 48 Unions are used for effective representation of core registers.
mbed_official 159:7130f322cb7e 49
mbed_official 159:7130f322cb7e 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
mbed_official 159:7130f322cb7e 51 Function-like macros are used to allow more efficient code.
mbed_official 159:7130f322cb7e 52 */
mbed_official 159:7130f322cb7e 53
mbed_official 159:7130f322cb7e 54
mbed_official 159:7130f322cb7e 55 /*******************************************************************************
mbed_official 159:7130f322cb7e 56 * CMSIS definitions
mbed_official 159:7130f322cb7e 57 ******************************************************************************/
mbed_official 159:7130f322cb7e 58 /**
mbed_official 159:7130f322cb7e 59 \ingroup Cortex_M33
mbed_official 159:7130f322cb7e 60 @{
mbed_official 159:7130f322cb7e 61 */
mbed_official 159:7130f322cb7e 62
mbed_official 159:7130f322cb7e 63 /* CMSIS CM33 definitions */
mbed_official 159:7130f322cb7e 64 #define __CM33_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
mbed_official 159:7130f322cb7e 65 #define __CM33_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
mbed_official 159:7130f322cb7e 66 #define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
mbed_official 159:7130f322cb7e 67 __CM33_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
mbed_official 159:7130f322cb7e 68
mbed_official 159:7130f322cb7e 69 #define __CORTEX_M (33U) /*!< Cortex-M Core */
mbed_official 159:7130f322cb7e 70
mbed_official 159:7130f322cb7e 71 /** __FPU_USED indicates whether an FPU is used or not.
mbed_official 159:7130f322cb7e 72 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
mbed_official 159:7130f322cb7e 73 */
mbed_official 159:7130f322cb7e 74 #if defined ( __CC_ARM )
mbed_official 159:7130f322cb7e 75 #if defined __TARGET_FPU_VFP
mbed_official 159:7130f322cb7e 76 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
mbed_official 159:7130f322cb7e 77 #define __FPU_USED 1U
mbed_official 159:7130f322cb7e 78 #else
mbed_official 159:7130f322cb7e 79 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 159:7130f322cb7e 80 #define __FPU_USED 0U
mbed_official 159:7130f322cb7e 81 #endif
mbed_official 159:7130f322cb7e 82 #else
mbed_official 159:7130f322cb7e 83 #define __FPU_USED 0U
mbed_official 159:7130f322cb7e 84 #endif
mbed_official 159:7130f322cb7e 85
mbed_official 159:7130f322cb7e 86 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
mbed_official 159:7130f322cb7e 87 #if defined __ARM_PCS_VFP
mbed_official 159:7130f322cb7e 88 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
mbed_official 159:7130f322cb7e 89 #define __FPU_USED 1U
mbed_official 159:7130f322cb7e 90 #else
mbed_official 159:7130f322cb7e 91 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 159:7130f322cb7e 92 #define __FPU_USED 0U
mbed_official 159:7130f322cb7e 93 #endif
mbed_official 159:7130f322cb7e 94 #else
mbed_official 159:7130f322cb7e 95 #define __FPU_USED 0U
mbed_official 159:7130f322cb7e 96 #endif
mbed_official 159:7130f322cb7e 97
mbed_official 159:7130f322cb7e 98 #elif defined ( __GNUC__ )
mbed_official 159:7130f322cb7e 99 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mbed_official 159:7130f322cb7e 100 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
mbed_official 159:7130f322cb7e 101 #define __FPU_USED 1U
mbed_official 159:7130f322cb7e 102 #else
mbed_official 159:7130f322cb7e 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 159:7130f322cb7e 104 #define __FPU_USED 0U
mbed_official 159:7130f322cb7e 105 #endif
mbed_official 159:7130f322cb7e 106 #else
mbed_official 159:7130f322cb7e 107 #define __FPU_USED 0U
mbed_official 159:7130f322cb7e 108 #endif
mbed_official 159:7130f322cb7e 109
mbed_official 159:7130f322cb7e 110 #elif defined ( __ICCARM__ )
mbed_official 159:7130f322cb7e 111 #if defined __ARMVFP__
mbed_official 159:7130f322cb7e 112 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
mbed_official 159:7130f322cb7e 113 #define __FPU_USED 1U
mbed_official 159:7130f322cb7e 114 #else
mbed_official 159:7130f322cb7e 115 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 159:7130f322cb7e 116 #define __FPU_USED 0U
mbed_official 159:7130f322cb7e 117 #endif
mbed_official 159:7130f322cb7e 118 #else
mbed_official 159:7130f322cb7e 119 #define __FPU_USED 0U
mbed_official 159:7130f322cb7e 120 #endif
mbed_official 159:7130f322cb7e 121
mbed_official 159:7130f322cb7e 122 #elif defined ( __TI_ARM__ )
mbed_official 159:7130f322cb7e 123 #if defined __TI_VFP_SUPPORT__
mbed_official 159:7130f322cb7e 124 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
mbed_official 159:7130f322cb7e 125 #define __FPU_USED 1U
mbed_official 159:7130f322cb7e 126 #else
mbed_official 159:7130f322cb7e 127 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 159:7130f322cb7e 128 #define __FPU_USED 0U
mbed_official 159:7130f322cb7e 129 #endif
mbed_official 159:7130f322cb7e 130 #else
mbed_official 159:7130f322cb7e 131 #define __FPU_USED 0U
mbed_official 159:7130f322cb7e 132 #endif
mbed_official 159:7130f322cb7e 133
mbed_official 159:7130f322cb7e 134 #elif defined ( __TASKING__ )
mbed_official 159:7130f322cb7e 135 #if defined __FPU_VFP__
mbed_official 159:7130f322cb7e 136 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
mbed_official 159:7130f322cb7e 137 #define __FPU_USED 1U
mbed_official 159:7130f322cb7e 138 #else
mbed_official 159:7130f322cb7e 139 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 159:7130f322cb7e 140 #define __FPU_USED 0U
mbed_official 159:7130f322cb7e 141 #endif
mbed_official 159:7130f322cb7e 142 #else
mbed_official 159:7130f322cb7e 143 #define __FPU_USED 0U
mbed_official 159:7130f322cb7e 144 #endif
mbed_official 159:7130f322cb7e 145
mbed_official 159:7130f322cb7e 146 #elif defined ( __CSMC__ )
mbed_official 159:7130f322cb7e 147 #if ( __CSMC__ & 0x400U)
mbed_official 159:7130f322cb7e 148 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
mbed_official 159:7130f322cb7e 149 #define __FPU_USED 1U
mbed_official 159:7130f322cb7e 150 #else
mbed_official 159:7130f322cb7e 151 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 159:7130f322cb7e 152 #define __FPU_USED 0U
mbed_official 159:7130f322cb7e 153 #endif
mbed_official 159:7130f322cb7e 154 #else
mbed_official 159:7130f322cb7e 155 #define __FPU_USED 0U
mbed_official 159:7130f322cb7e 156 #endif
mbed_official 159:7130f322cb7e 157
mbed_official 159:7130f322cb7e 158 #endif
mbed_official 159:7130f322cb7e 159
mbed_official 159:7130f322cb7e 160 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
mbed_official 159:7130f322cb7e 161
mbed_official 159:7130f322cb7e 162
mbed_official 159:7130f322cb7e 163 #ifdef __cplusplus
mbed_official 159:7130f322cb7e 164 }
mbed_official 159:7130f322cb7e 165 #endif
mbed_official 159:7130f322cb7e 166
mbed_official 159:7130f322cb7e 167 #endif /* __CORE_CM33_H_GENERIC */
mbed_official 159:7130f322cb7e 168
mbed_official 159:7130f322cb7e 169 #ifndef __CMSIS_GENERIC
mbed_official 159:7130f322cb7e 170
mbed_official 159:7130f322cb7e 171 #ifndef __CORE_CM33_H_DEPENDANT
mbed_official 159:7130f322cb7e 172 #define __CORE_CM33_H_DEPENDANT
mbed_official 159:7130f322cb7e 173
mbed_official 159:7130f322cb7e 174 #ifdef __cplusplus
mbed_official 159:7130f322cb7e 175 extern "C" {
mbed_official 159:7130f322cb7e 176 #endif
mbed_official 159:7130f322cb7e 177
mbed_official 159:7130f322cb7e 178 /* check device defines and use defaults */
mbed_official 159:7130f322cb7e 179 #if defined __CHECK_DEVICE_DEFINES
mbed_official 159:7130f322cb7e 180 #ifndef __CM33_REV
mbed_official 159:7130f322cb7e 181 #define __CM33_REV 0x0000U
mbed_official 159:7130f322cb7e 182 #warning "__CM33_REV not defined in device header file; using default!"
mbed_official 159:7130f322cb7e 183 #endif
mbed_official 159:7130f322cb7e 184
mbed_official 159:7130f322cb7e 185 #ifndef __FPU_PRESENT
mbed_official 159:7130f322cb7e 186 #define __FPU_PRESENT 0U
mbed_official 159:7130f322cb7e 187 #warning "__FPU_PRESENT not defined in device header file; using default!"
mbed_official 159:7130f322cb7e 188 #endif
mbed_official 159:7130f322cb7e 189
mbed_official 159:7130f322cb7e 190 #ifndef __MPU_PRESENT
mbed_official 159:7130f322cb7e 191 #define __MPU_PRESENT 0U
mbed_official 159:7130f322cb7e 192 #warning "__MPU_PRESENT not defined in device header file; using default!"
mbed_official 159:7130f322cb7e 193 #endif
mbed_official 159:7130f322cb7e 194
mbed_official 159:7130f322cb7e 195 #ifndef __SAUREGION_PRESENT
mbed_official 159:7130f322cb7e 196 #define __SAUREGION_PRESENT 0U
mbed_official 159:7130f322cb7e 197 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
mbed_official 159:7130f322cb7e 198 #endif
mbed_official 159:7130f322cb7e 199
mbed_official 159:7130f322cb7e 200 #ifndef __DSP_PRESENT
mbed_official 159:7130f322cb7e 201 #define __DSP_PRESENT 0U
mbed_official 159:7130f322cb7e 202 #warning "__DSP_PRESENT not defined in device header file; using default!"
mbed_official 159:7130f322cb7e 203 #endif
mbed_official 159:7130f322cb7e 204
mbed_official 159:7130f322cb7e 205 #ifndef __NVIC_PRIO_BITS
mbed_official 159:7130f322cb7e 206 #define __NVIC_PRIO_BITS 3U
mbed_official 159:7130f322cb7e 207 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mbed_official 159:7130f322cb7e 208 #endif
mbed_official 159:7130f322cb7e 209
mbed_official 159:7130f322cb7e 210 #ifndef __Vendor_SysTickConfig
mbed_official 159:7130f322cb7e 211 #define __Vendor_SysTickConfig 0U
mbed_official 159:7130f322cb7e 212 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mbed_official 159:7130f322cb7e 213 #endif
mbed_official 159:7130f322cb7e 214 #endif
mbed_official 159:7130f322cb7e 215
mbed_official 159:7130f322cb7e 216 /* IO definitions (access restrictions to peripheral registers) */
mbed_official 159:7130f322cb7e 217 /**
mbed_official 159:7130f322cb7e 218 \defgroup CMSIS_glob_defs CMSIS Global Defines
mbed_official 159:7130f322cb7e 219
mbed_official 159:7130f322cb7e 220 <strong>IO Type Qualifiers</strong> are used
mbed_official 159:7130f322cb7e 221 \li to specify the access to peripheral variables.
mbed_official 159:7130f322cb7e 222 \li for automatic generation of peripheral register debug information.
mbed_official 159:7130f322cb7e 223 */
mbed_official 159:7130f322cb7e 224 #ifdef __cplusplus
mbed_official 159:7130f322cb7e 225 #define __I volatile /*!< Defines 'read only' permissions */
mbed_official 159:7130f322cb7e 226 #else
mbed_official 159:7130f322cb7e 227 #define __I volatile const /*!< Defines 'read only' permissions */
mbed_official 159:7130f322cb7e 228 #endif
mbed_official 159:7130f322cb7e 229 #define __O volatile /*!< Defines 'write only' permissions */
mbed_official 159:7130f322cb7e 230 #define __IO volatile /*!< Defines 'read / write' permissions */
mbed_official 159:7130f322cb7e 231
mbed_official 159:7130f322cb7e 232 /* following defines should be used for structure members */
mbed_official 159:7130f322cb7e 233 #define __IM volatile const /*! Defines 'read only' structure member permissions */
mbed_official 159:7130f322cb7e 234 #define __OM volatile /*! Defines 'write only' structure member permissions */
mbed_official 159:7130f322cb7e 235 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
mbed_official 159:7130f322cb7e 236
mbed_official 159:7130f322cb7e 237 /*@} end of group Cortex_M33 */
mbed_official 159:7130f322cb7e 238
mbed_official 159:7130f322cb7e 239
mbed_official 159:7130f322cb7e 240
mbed_official 159:7130f322cb7e 241 /*******************************************************************************
mbed_official 159:7130f322cb7e 242 * Register Abstraction
mbed_official 159:7130f322cb7e 243 Core Register contain:
mbed_official 159:7130f322cb7e 244 - Core Register
mbed_official 159:7130f322cb7e 245 - Core NVIC Register
mbed_official 159:7130f322cb7e 246 - Core SCB Register
mbed_official 159:7130f322cb7e 247 - Core SysTick Register
mbed_official 159:7130f322cb7e 248 - Core Debug Register
mbed_official 159:7130f322cb7e 249 - Core MPU Register
mbed_official 159:7130f322cb7e 250 - Core SAU Register
mbed_official 159:7130f322cb7e 251 - Core FPU Register
mbed_official 159:7130f322cb7e 252 ******************************************************************************/
mbed_official 159:7130f322cb7e 253 /**
mbed_official 159:7130f322cb7e 254 \defgroup CMSIS_core_register Defines and Type Definitions
mbed_official 159:7130f322cb7e 255 \brief Type definitions and defines for Cortex-M processor based devices.
mbed_official 159:7130f322cb7e 256 */
mbed_official 159:7130f322cb7e 257
mbed_official 159:7130f322cb7e 258 /**
mbed_official 159:7130f322cb7e 259 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 260 \defgroup CMSIS_CORE Status and Control Registers
mbed_official 159:7130f322cb7e 261 \brief Core Register type definitions.
mbed_official 159:7130f322cb7e 262 @{
mbed_official 159:7130f322cb7e 263 */
mbed_official 159:7130f322cb7e 264
mbed_official 159:7130f322cb7e 265 /**
mbed_official 159:7130f322cb7e 266 \brief Union type to access the Application Program Status Register (APSR).
mbed_official 159:7130f322cb7e 267 */
mbed_official 159:7130f322cb7e 268 typedef union
mbed_official 159:7130f322cb7e 269 {
mbed_official 159:7130f322cb7e 270 struct
mbed_official 159:7130f322cb7e 271 {
mbed_official 159:7130f322cb7e 272 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
mbed_official 159:7130f322cb7e 273 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mbed_official 159:7130f322cb7e 274 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
mbed_official 159:7130f322cb7e 275 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mbed_official 159:7130f322cb7e 276 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mbed_official 159:7130f322cb7e 277 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mbed_official 159:7130f322cb7e 278 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mbed_official 159:7130f322cb7e 279 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mbed_official 159:7130f322cb7e 280 } b; /*!< Structure used for bit access */
mbed_official 159:7130f322cb7e 281 uint32_t w; /*!< Type used for word access */
mbed_official 159:7130f322cb7e 282 } APSR_Type;
mbed_official 159:7130f322cb7e 283
mbed_official 159:7130f322cb7e 284 /* APSR Register Definitions */
mbed_official 159:7130f322cb7e 285 #define APSR_N_Pos 31U /*!< APSR: N Position */
mbed_official 159:7130f322cb7e 286 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
mbed_official 159:7130f322cb7e 287
mbed_official 159:7130f322cb7e 288 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
mbed_official 159:7130f322cb7e 289 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
mbed_official 159:7130f322cb7e 290
mbed_official 159:7130f322cb7e 291 #define APSR_C_Pos 29U /*!< APSR: C Position */
mbed_official 159:7130f322cb7e 292 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
mbed_official 159:7130f322cb7e 293
mbed_official 159:7130f322cb7e 294 #define APSR_V_Pos 28U /*!< APSR: V Position */
mbed_official 159:7130f322cb7e 295 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
mbed_official 159:7130f322cb7e 296
mbed_official 159:7130f322cb7e 297 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
mbed_official 159:7130f322cb7e 298 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
mbed_official 159:7130f322cb7e 299
mbed_official 159:7130f322cb7e 300 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
mbed_official 159:7130f322cb7e 301 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
mbed_official 159:7130f322cb7e 302
mbed_official 159:7130f322cb7e 303
mbed_official 159:7130f322cb7e 304 /**
mbed_official 159:7130f322cb7e 305 \brief Union type to access the Interrupt Program Status Register (IPSR).
mbed_official 159:7130f322cb7e 306 */
mbed_official 159:7130f322cb7e 307 typedef union
mbed_official 159:7130f322cb7e 308 {
mbed_official 159:7130f322cb7e 309 struct
mbed_official 159:7130f322cb7e 310 {
mbed_official 159:7130f322cb7e 311 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mbed_official 159:7130f322cb7e 312 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
mbed_official 159:7130f322cb7e 313 } b; /*!< Structure used for bit access */
mbed_official 159:7130f322cb7e 314 uint32_t w; /*!< Type used for word access */
mbed_official 159:7130f322cb7e 315 } IPSR_Type;
mbed_official 159:7130f322cb7e 316
mbed_official 159:7130f322cb7e 317 /* IPSR Register Definitions */
mbed_official 159:7130f322cb7e 318 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
mbed_official 159:7130f322cb7e 319 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
mbed_official 159:7130f322cb7e 320
mbed_official 159:7130f322cb7e 321
mbed_official 159:7130f322cb7e 322 /**
mbed_official 159:7130f322cb7e 323 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mbed_official 159:7130f322cb7e 324 */
mbed_official 159:7130f322cb7e 325 typedef union
mbed_official 159:7130f322cb7e 326 {
mbed_official 159:7130f322cb7e 327 struct
mbed_official 159:7130f322cb7e 328 {
mbed_official 159:7130f322cb7e 329 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mbed_official 159:7130f322cb7e 330 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
mbed_official 159:7130f322cb7e 331 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mbed_official 159:7130f322cb7e 332 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
mbed_official 159:7130f322cb7e 333 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
mbed_official 159:7130f322cb7e 334 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
mbed_official 159:7130f322cb7e 335 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mbed_official 159:7130f322cb7e 336 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mbed_official 159:7130f322cb7e 337 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mbed_official 159:7130f322cb7e 338 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mbed_official 159:7130f322cb7e 339 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mbed_official 159:7130f322cb7e 340 } b; /*!< Structure used for bit access */
mbed_official 159:7130f322cb7e 341 uint32_t w; /*!< Type used for word access */
mbed_official 159:7130f322cb7e 342 } xPSR_Type;
mbed_official 159:7130f322cb7e 343
mbed_official 159:7130f322cb7e 344 /* xPSR Register Definitions */
mbed_official 159:7130f322cb7e 345 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
mbed_official 159:7130f322cb7e 346 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
mbed_official 159:7130f322cb7e 347
mbed_official 159:7130f322cb7e 348 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
mbed_official 159:7130f322cb7e 349 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
mbed_official 159:7130f322cb7e 350
mbed_official 159:7130f322cb7e 351 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
mbed_official 159:7130f322cb7e 352 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
mbed_official 159:7130f322cb7e 353
mbed_official 159:7130f322cb7e 354 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
mbed_official 159:7130f322cb7e 355 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
mbed_official 159:7130f322cb7e 356
mbed_official 159:7130f322cb7e 357 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
mbed_official 159:7130f322cb7e 358 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
mbed_official 159:7130f322cb7e 359
mbed_official 159:7130f322cb7e 360 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
mbed_official 159:7130f322cb7e 361 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
mbed_official 159:7130f322cb7e 362
mbed_official 159:7130f322cb7e 363 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
mbed_official 159:7130f322cb7e 364 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
mbed_official 159:7130f322cb7e 365
mbed_official 159:7130f322cb7e 366 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
mbed_official 159:7130f322cb7e 367 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
mbed_official 159:7130f322cb7e 368
mbed_official 159:7130f322cb7e 369 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
mbed_official 159:7130f322cb7e 370 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
mbed_official 159:7130f322cb7e 371
mbed_official 159:7130f322cb7e 372
mbed_official 159:7130f322cb7e 373 /**
mbed_official 159:7130f322cb7e 374 \brief Union type to access the Control Registers (CONTROL).
mbed_official 159:7130f322cb7e 375 */
mbed_official 159:7130f322cb7e 376 typedef union
mbed_official 159:7130f322cb7e 377 {
mbed_official 159:7130f322cb7e 378 struct
mbed_official 159:7130f322cb7e 379 {
mbed_official 159:7130f322cb7e 380 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
mbed_official 159:7130f322cb7e 381 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
mbed_official 159:7130f322cb7e 382 uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
mbed_official 159:7130f322cb7e 383 uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
mbed_official 159:7130f322cb7e 384 uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
mbed_official 159:7130f322cb7e 385 } b; /*!< Structure used for bit access */
mbed_official 159:7130f322cb7e 386 uint32_t w; /*!< Type used for word access */
mbed_official 159:7130f322cb7e 387 } CONTROL_Type;
mbed_official 159:7130f322cb7e 388
mbed_official 159:7130f322cb7e 389 /* CONTROL Register Definitions */
mbed_official 159:7130f322cb7e 390 #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
mbed_official 159:7130f322cb7e 391 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
mbed_official 159:7130f322cb7e 392
mbed_official 159:7130f322cb7e 393 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
mbed_official 159:7130f322cb7e 394 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
mbed_official 159:7130f322cb7e 395
mbed_official 159:7130f322cb7e 396 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
mbed_official 159:7130f322cb7e 397 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
mbed_official 159:7130f322cb7e 398
mbed_official 159:7130f322cb7e 399 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
mbed_official 159:7130f322cb7e 400 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
mbed_official 159:7130f322cb7e 401
mbed_official 159:7130f322cb7e 402 /*@} end of group CMSIS_CORE */
mbed_official 159:7130f322cb7e 403
mbed_official 159:7130f322cb7e 404
mbed_official 159:7130f322cb7e 405 /**
mbed_official 159:7130f322cb7e 406 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 407 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mbed_official 159:7130f322cb7e 408 \brief Type definitions for the NVIC Registers
mbed_official 159:7130f322cb7e 409 @{
mbed_official 159:7130f322cb7e 410 */
mbed_official 159:7130f322cb7e 411
mbed_official 159:7130f322cb7e 412 /**
mbed_official 159:7130f322cb7e 413 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mbed_official 159:7130f322cb7e 414 */
mbed_official 159:7130f322cb7e 415 typedef struct
mbed_official 159:7130f322cb7e 416 {
mbed_official 159:7130f322cb7e 417 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
mbed_official 159:7130f322cb7e 418 uint32_t RESERVED0[16U];
mbed_official 159:7130f322cb7e 419 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
mbed_official 159:7130f322cb7e 420 uint32_t RSERVED1[16U];
mbed_official 159:7130f322cb7e 421 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
mbed_official 159:7130f322cb7e 422 uint32_t RESERVED2[16U];
mbed_official 159:7130f322cb7e 423 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
mbed_official 159:7130f322cb7e 424 uint32_t RESERVED3[16U];
mbed_official 159:7130f322cb7e 425 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
mbed_official 159:7130f322cb7e 426 uint32_t RESERVED4[16U];
mbed_official 159:7130f322cb7e 427 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
mbed_official 159:7130f322cb7e 428 uint32_t RESERVED5[16U];
mbed_official 159:7130f322cb7e 429 __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
mbed_official 159:7130f322cb7e 430 uint32_t RESERVED6[580U];
mbed_official 159:7130f322cb7e 431 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
mbed_official 159:7130f322cb7e 432 } NVIC_Type;
mbed_official 159:7130f322cb7e 433
mbed_official 159:7130f322cb7e 434 /* Software Triggered Interrupt Register Definitions */
mbed_official 159:7130f322cb7e 435 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
mbed_official 159:7130f322cb7e 436 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
mbed_official 159:7130f322cb7e 437
mbed_official 159:7130f322cb7e 438 /*@} end of group CMSIS_NVIC */
mbed_official 159:7130f322cb7e 439
mbed_official 159:7130f322cb7e 440
mbed_official 159:7130f322cb7e 441 /**
mbed_official 159:7130f322cb7e 442 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 443 \defgroup CMSIS_SCB System Control Block (SCB)
mbed_official 159:7130f322cb7e 444 \brief Type definitions for the System Control Block Registers
mbed_official 159:7130f322cb7e 445 @{
mbed_official 159:7130f322cb7e 446 */
mbed_official 159:7130f322cb7e 447
mbed_official 159:7130f322cb7e 448 /**
mbed_official 159:7130f322cb7e 449 \brief Structure type to access the System Control Block (SCB).
mbed_official 159:7130f322cb7e 450 */
mbed_official 159:7130f322cb7e 451 typedef struct
mbed_official 159:7130f322cb7e 452 {
mbed_official 159:7130f322cb7e 453 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
mbed_official 159:7130f322cb7e 454 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
mbed_official 159:7130f322cb7e 455 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
mbed_official 159:7130f322cb7e 456 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
mbed_official 159:7130f322cb7e 457 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
mbed_official 159:7130f322cb7e 458 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
mbed_official 159:7130f322cb7e 459 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
mbed_official 159:7130f322cb7e 460 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
mbed_official 159:7130f322cb7e 461 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
mbed_official 159:7130f322cb7e 462 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
mbed_official 159:7130f322cb7e 463 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
mbed_official 159:7130f322cb7e 464 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
mbed_official 159:7130f322cb7e 465 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
mbed_official 159:7130f322cb7e 466 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
mbed_official 159:7130f322cb7e 467 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
mbed_official 159:7130f322cb7e 468 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
mbed_official 159:7130f322cb7e 469 __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
mbed_official 159:7130f322cb7e 470 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
mbed_official 159:7130f322cb7e 471 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
mbed_official 159:7130f322cb7e 472 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
mbed_official 159:7130f322cb7e 473 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
mbed_official 159:7130f322cb7e 474 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
mbed_official 159:7130f322cb7e 475 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
mbed_official 159:7130f322cb7e 476 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
mbed_official 159:7130f322cb7e 477 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
mbed_official 159:7130f322cb7e 478 uint32_t RESERVED3[92U];
mbed_official 159:7130f322cb7e 479 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
mbed_official 159:7130f322cb7e 480 uint32_t RESERVED4[15U];
mbed_official 159:7130f322cb7e 481 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
mbed_official 159:7130f322cb7e 482 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
mbed_official 159:7130f322cb7e 483 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
mbed_official 159:7130f322cb7e 484 uint32_t RESERVED5[1U];
mbed_official 159:7130f322cb7e 485 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
mbed_official 159:7130f322cb7e 486 uint32_t RESERVED6[1U];
mbed_official 159:7130f322cb7e 487 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
mbed_official 159:7130f322cb7e 488 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
mbed_official 159:7130f322cb7e 489 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
mbed_official 159:7130f322cb7e 490 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
mbed_official 159:7130f322cb7e 491 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
mbed_official 159:7130f322cb7e 492 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
mbed_official 159:7130f322cb7e 493 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
mbed_official 159:7130f322cb7e 494 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
mbed_official 159:7130f322cb7e 495 uint32_t RESERVED7[6U];
mbed_official 159:7130f322cb7e 496 __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
mbed_official 159:7130f322cb7e 497 __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
mbed_official 159:7130f322cb7e 498 __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
mbed_official 159:7130f322cb7e 499 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
mbed_official 159:7130f322cb7e 500 __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
mbed_official 159:7130f322cb7e 501 uint32_t RESERVED8[1U];
mbed_official 159:7130f322cb7e 502 __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
mbed_official 159:7130f322cb7e 503 } SCB_Type;
mbed_official 159:7130f322cb7e 504
mbed_official 159:7130f322cb7e 505 /* SCB CPUID Register Definitions */
mbed_official 159:7130f322cb7e 506 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
mbed_official 159:7130f322cb7e 507 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
mbed_official 159:7130f322cb7e 508
mbed_official 159:7130f322cb7e 509 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
mbed_official 159:7130f322cb7e 510 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
mbed_official 159:7130f322cb7e 511
mbed_official 159:7130f322cb7e 512 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
mbed_official 159:7130f322cb7e 513 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
mbed_official 159:7130f322cb7e 514
mbed_official 159:7130f322cb7e 515 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
mbed_official 159:7130f322cb7e 516 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
mbed_official 159:7130f322cb7e 517
mbed_official 159:7130f322cb7e 518 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
mbed_official 159:7130f322cb7e 519 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
mbed_official 159:7130f322cb7e 520
mbed_official 159:7130f322cb7e 521 /* SCB Interrupt Control State Register Definitions */
mbed_official 159:7130f322cb7e 522 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
mbed_official 159:7130f322cb7e 523 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
mbed_official 159:7130f322cb7e 524
mbed_official 159:7130f322cb7e 525 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
mbed_official 159:7130f322cb7e 526 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
mbed_official 159:7130f322cb7e 527
mbed_official 159:7130f322cb7e 528 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
mbed_official 159:7130f322cb7e 529 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
mbed_official 159:7130f322cb7e 530
mbed_official 159:7130f322cb7e 531 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
mbed_official 159:7130f322cb7e 532 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
mbed_official 159:7130f322cb7e 533
mbed_official 159:7130f322cb7e 534 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
mbed_official 159:7130f322cb7e 535 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
mbed_official 159:7130f322cb7e 536
mbed_official 159:7130f322cb7e 537 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
mbed_official 159:7130f322cb7e 538 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
mbed_official 159:7130f322cb7e 539
mbed_official 159:7130f322cb7e 540 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
mbed_official 159:7130f322cb7e 541 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
mbed_official 159:7130f322cb7e 542
mbed_official 159:7130f322cb7e 543 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
mbed_official 159:7130f322cb7e 544 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
mbed_official 159:7130f322cb7e 545
mbed_official 159:7130f322cb7e 546 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
mbed_official 159:7130f322cb7e 547 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
mbed_official 159:7130f322cb7e 548
mbed_official 159:7130f322cb7e 549 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
mbed_official 159:7130f322cb7e 550 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
mbed_official 159:7130f322cb7e 551
mbed_official 159:7130f322cb7e 552 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
mbed_official 159:7130f322cb7e 553 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
mbed_official 159:7130f322cb7e 554
mbed_official 159:7130f322cb7e 555 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
mbed_official 159:7130f322cb7e 556 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
mbed_official 159:7130f322cb7e 557
mbed_official 159:7130f322cb7e 558 /* SCB Vector Table Offset Register Definitions */
mbed_official 159:7130f322cb7e 559 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
mbed_official 159:7130f322cb7e 560 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
mbed_official 159:7130f322cb7e 561
mbed_official 159:7130f322cb7e 562 /* SCB Application Interrupt and Reset Control Register Definitions */
mbed_official 159:7130f322cb7e 563 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
mbed_official 159:7130f322cb7e 564 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
mbed_official 159:7130f322cb7e 565
mbed_official 159:7130f322cb7e 566 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
mbed_official 159:7130f322cb7e 567 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
mbed_official 159:7130f322cb7e 568
mbed_official 159:7130f322cb7e 569 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
mbed_official 159:7130f322cb7e 570 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
mbed_official 159:7130f322cb7e 571
mbed_official 159:7130f322cb7e 572 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
mbed_official 159:7130f322cb7e 573 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
mbed_official 159:7130f322cb7e 574
mbed_official 159:7130f322cb7e 575 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
mbed_official 159:7130f322cb7e 576 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
mbed_official 159:7130f322cb7e 577
mbed_official 159:7130f322cb7e 578 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
mbed_official 159:7130f322cb7e 579 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
mbed_official 159:7130f322cb7e 580
mbed_official 159:7130f322cb7e 581 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
mbed_official 159:7130f322cb7e 582 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
mbed_official 159:7130f322cb7e 583
mbed_official 159:7130f322cb7e 584 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
mbed_official 159:7130f322cb7e 585 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
mbed_official 159:7130f322cb7e 586
mbed_official 159:7130f322cb7e 587 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
mbed_official 159:7130f322cb7e 588 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
mbed_official 159:7130f322cb7e 589
mbed_official 159:7130f322cb7e 590 /* SCB System Control Register Definitions */
mbed_official 159:7130f322cb7e 591 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
mbed_official 159:7130f322cb7e 592 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
mbed_official 159:7130f322cb7e 593
mbed_official 159:7130f322cb7e 594 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
mbed_official 159:7130f322cb7e 595 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
mbed_official 159:7130f322cb7e 596
mbed_official 159:7130f322cb7e 597 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
mbed_official 159:7130f322cb7e 598 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
mbed_official 159:7130f322cb7e 599
mbed_official 159:7130f322cb7e 600 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
mbed_official 159:7130f322cb7e 601 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
mbed_official 159:7130f322cb7e 602
mbed_official 159:7130f322cb7e 603 /* SCB Configuration Control Register Definitions */
mbed_official 159:7130f322cb7e 604 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
mbed_official 159:7130f322cb7e 605 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
mbed_official 159:7130f322cb7e 606
mbed_official 159:7130f322cb7e 607 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
mbed_official 159:7130f322cb7e 608 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
mbed_official 159:7130f322cb7e 609
mbed_official 159:7130f322cb7e 610 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
mbed_official 159:7130f322cb7e 611 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
mbed_official 159:7130f322cb7e 612
mbed_official 159:7130f322cb7e 613 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
mbed_official 159:7130f322cb7e 614 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
mbed_official 159:7130f322cb7e 615
mbed_official 159:7130f322cb7e 616 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
mbed_official 159:7130f322cb7e 617 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
mbed_official 159:7130f322cb7e 618
mbed_official 159:7130f322cb7e 619 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
mbed_official 159:7130f322cb7e 620 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
mbed_official 159:7130f322cb7e 621
mbed_official 159:7130f322cb7e 622 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
mbed_official 159:7130f322cb7e 623 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
mbed_official 159:7130f322cb7e 624
mbed_official 159:7130f322cb7e 625 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
mbed_official 159:7130f322cb7e 626 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
mbed_official 159:7130f322cb7e 627
mbed_official 159:7130f322cb7e 628 /* SCB System Handler Control and State Register Definitions */
mbed_official 159:7130f322cb7e 629 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
mbed_official 159:7130f322cb7e 630 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
mbed_official 159:7130f322cb7e 631
mbed_official 159:7130f322cb7e 632 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
mbed_official 159:7130f322cb7e 633 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
mbed_official 159:7130f322cb7e 634
mbed_official 159:7130f322cb7e 635 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
mbed_official 159:7130f322cb7e 636 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
mbed_official 159:7130f322cb7e 637
mbed_official 159:7130f322cb7e 638 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
mbed_official 159:7130f322cb7e 639 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
mbed_official 159:7130f322cb7e 640
mbed_official 159:7130f322cb7e 641 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
mbed_official 159:7130f322cb7e 642 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
mbed_official 159:7130f322cb7e 643
mbed_official 159:7130f322cb7e 644 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
mbed_official 159:7130f322cb7e 645 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
mbed_official 159:7130f322cb7e 646
mbed_official 159:7130f322cb7e 647 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
mbed_official 159:7130f322cb7e 648 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
mbed_official 159:7130f322cb7e 649
mbed_official 159:7130f322cb7e 650 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
mbed_official 159:7130f322cb7e 651 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
mbed_official 159:7130f322cb7e 652
mbed_official 159:7130f322cb7e 653 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
mbed_official 159:7130f322cb7e 654 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
mbed_official 159:7130f322cb7e 655
mbed_official 159:7130f322cb7e 656 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
mbed_official 159:7130f322cb7e 657 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
mbed_official 159:7130f322cb7e 658
mbed_official 159:7130f322cb7e 659 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
mbed_official 159:7130f322cb7e 660 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
mbed_official 159:7130f322cb7e 661
mbed_official 159:7130f322cb7e 662 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
mbed_official 159:7130f322cb7e 663 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
mbed_official 159:7130f322cb7e 664
mbed_official 159:7130f322cb7e 665 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
mbed_official 159:7130f322cb7e 666 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
mbed_official 159:7130f322cb7e 667
mbed_official 159:7130f322cb7e 668 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
mbed_official 159:7130f322cb7e 669 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
mbed_official 159:7130f322cb7e 670
mbed_official 159:7130f322cb7e 671 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
mbed_official 159:7130f322cb7e 672 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
mbed_official 159:7130f322cb7e 673
mbed_official 159:7130f322cb7e 674 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
mbed_official 159:7130f322cb7e 675 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
mbed_official 159:7130f322cb7e 676
mbed_official 159:7130f322cb7e 677 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
mbed_official 159:7130f322cb7e 678 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
mbed_official 159:7130f322cb7e 679
mbed_official 159:7130f322cb7e 680 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
mbed_official 159:7130f322cb7e 681 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
mbed_official 159:7130f322cb7e 682
mbed_official 159:7130f322cb7e 683 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
mbed_official 159:7130f322cb7e 684 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
mbed_official 159:7130f322cb7e 685
mbed_official 159:7130f322cb7e 686 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
mbed_official 159:7130f322cb7e 687 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
mbed_official 159:7130f322cb7e 688
mbed_official 159:7130f322cb7e 689 /* SCB Configurable Fault Status Register Definitions */
mbed_official 159:7130f322cb7e 690 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
mbed_official 159:7130f322cb7e 691 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
mbed_official 159:7130f322cb7e 692
mbed_official 159:7130f322cb7e 693 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
mbed_official 159:7130f322cb7e 694 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
mbed_official 159:7130f322cb7e 695
mbed_official 159:7130f322cb7e 696 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
mbed_official 159:7130f322cb7e 697 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
mbed_official 159:7130f322cb7e 698
mbed_official 159:7130f322cb7e 699 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
mbed_official 159:7130f322cb7e 700 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
mbed_official 159:7130f322cb7e 701 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
mbed_official 159:7130f322cb7e 702
mbed_official 159:7130f322cb7e 703 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
mbed_official 159:7130f322cb7e 704 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
mbed_official 159:7130f322cb7e 705
mbed_official 159:7130f322cb7e 706 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
mbed_official 159:7130f322cb7e 707 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
mbed_official 159:7130f322cb7e 708
mbed_official 159:7130f322cb7e 709 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
mbed_official 159:7130f322cb7e 710 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
mbed_official 159:7130f322cb7e 711
mbed_official 159:7130f322cb7e 712 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
mbed_official 159:7130f322cb7e 713 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
mbed_official 159:7130f322cb7e 714
mbed_official 159:7130f322cb7e 715 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
mbed_official 159:7130f322cb7e 716 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
mbed_official 159:7130f322cb7e 717
mbed_official 159:7130f322cb7e 718 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
mbed_official 159:7130f322cb7e 719 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
mbed_official 159:7130f322cb7e 720 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
mbed_official 159:7130f322cb7e 721
mbed_official 159:7130f322cb7e 722 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
mbed_official 159:7130f322cb7e 723 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
mbed_official 159:7130f322cb7e 724
mbed_official 159:7130f322cb7e 725 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
mbed_official 159:7130f322cb7e 726 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
mbed_official 159:7130f322cb7e 727
mbed_official 159:7130f322cb7e 728 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
mbed_official 159:7130f322cb7e 729 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
mbed_official 159:7130f322cb7e 730
mbed_official 159:7130f322cb7e 731 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
mbed_official 159:7130f322cb7e 732 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
mbed_official 159:7130f322cb7e 733
mbed_official 159:7130f322cb7e 734 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
mbed_official 159:7130f322cb7e 735 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
mbed_official 159:7130f322cb7e 736
mbed_official 159:7130f322cb7e 737 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
mbed_official 159:7130f322cb7e 738 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
mbed_official 159:7130f322cb7e 739
mbed_official 159:7130f322cb7e 740 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
mbed_official 159:7130f322cb7e 741 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
mbed_official 159:7130f322cb7e 742 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
mbed_official 159:7130f322cb7e 743
mbed_official 159:7130f322cb7e 744 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
mbed_official 159:7130f322cb7e 745 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
mbed_official 159:7130f322cb7e 746
mbed_official 159:7130f322cb7e 747 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
mbed_official 159:7130f322cb7e 748 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
mbed_official 159:7130f322cb7e 749
mbed_official 159:7130f322cb7e 750 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
mbed_official 159:7130f322cb7e 751 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
mbed_official 159:7130f322cb7e 752
mbed_official 159:7130f322cb7e 753 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
mbed_official 159:7130f322cb7e 754 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
mbed_official 159:7130f322cb7e 755
mbed_official 159:7130f322cb7e 756 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
mbed_official 159:7130f322cb7e 757 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
mbed_official 159:7130f322cb7e 758
mbed_official 159:7130f322cb7e 759 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
mbed_official 159:7130f322cb7e 760 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
mbed_official 159:7130f322cb7e 761
mbed_official 159:7130f322cb7e 762 /* SCB Hard Fault Status Register Definitions */
mbed_official 159:7130f322cb7e 763 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
mbed_official 159:7130f322cb7e 764 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
mbed_official 159:7130f322cb7e 765
mbed_official 159:7130f322cb7e 766 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
mbed_official 159:7130f322cb7e 767 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
mbed_official 159:7130f322cb7e 768
mbed_official 159:7130f322cb7e 769 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
mbed_official 159:7130f322cb7e 770 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
mbed_official 159:7130f322cb7e 771
mbed_official 159:7130f322cb7e 772 /* SCB Debug Fault Status Register Definitions */
mbed_official 159:7130f322cb7e 773 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
mbed_official 159:7130f322cb7e 774 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
mbed_official 159:7130f322cb7e 775
mbed_official 159:7130f322cb7e 776 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
mbed_official 159:7130f322cb7e 777 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
mbed_official 159:7130f322cb7e 778
mbed_official 159:7130f322cb7e 779 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
mbed_official 159:7130f322cb7e 780 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
mbed_official 159:7130f322cb7e 781
mbed_official 159:7130f322cb7e 782 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
mbed_official 159:7130f322cb7e 783 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
mbed_official 159:7130f322cb7e 784
mbed_official 159:7130f322cb7e 785 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
mbed_official 159:7130f322cb7e 786 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
mbed_official 159:7130f322cb7e 787
mbed_official 159:7130f322cb7e 788 /* SCB Non-Secure Access Control Register Definitions */
mbed_official 159:7130f322cb7e 789 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
mbed_official 159:7130f322cb7e 790 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
mbed_official 159:7130f322cb7e 791
mbed_official 159:7130f322cb7e 792 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
mbed_official 159:7130f322cb7e 793 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
mbed_official 159:7130f322cb7e 794
mbed_official 159:7130f322cb7e 795 #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
mbed_official 159:7130f322cb7e 796 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
mbed_official 159:7130f322cb7e 797
mbed_official 159:7130f322cb7e 798 /* SCB Cache Level ID Register Definitions */
mbed_official 159:7130f322cb7e 799 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
mbed_official 159:7130f322cb7e 800 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
mbed_official 159:7130f322cb7e 801
mbed_official 159:7130f322cb7e 802 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
mbed_official 159:7130f322cb7e 803 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
mbed_official 159:7130f322cb7e 804
mbed_official 159:7130f322cb7e 805 /* SCB Cache Type Register Definitions */
mbed_official 159:7130f322cb7e 806 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
mbed_official 159:7130f322cb7e 807 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
mbed_official 159:7130f322cb7e 808
mbed_official 159:7130f322cb7e 809 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
mbed_official 159:7130f322cb7e 810 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
mbed_official 159:7130f322cb7e 811
mbed_official 159:7130f322cb7e 812 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
mbed_official 159:7130f322cb7e 813 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
mbed_official 159:7130f322cb7e 814
mbed_official 159:7130f322cb7e 815 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
mbed_official 159:7130f322cb7e 816 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
mbed_official 159:7130f322cb7e 817
mbed_official 159:7130f322cb7e 818 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
mbed_official 159:7130f322cb7e 819 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
mbed_official 159:7130f322cb7e 820
mbed_official 159:7130f322cb7e 821 /* SCB Cache Size ID Register Definitions */
mbed_official 159:7130f322cb7e 822 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
mbed_official 159:7130f322cb7e 823 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
mbed_official 159:7130f322cb7e 824
mbed_official 159:7130f322cb7e 825 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
mbed_official 159:7130f322cb7e 826 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
mbed_official 159:7130f322cb7e 827
mbed_official 159:7130f322cb7e 828 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
mbed_official 159:7130f322cb7e 829 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
mbed_official 159:7130f322cb7e 830
mbed_official 159:7130f322cb7e 831 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
mbed_official 159:7130f322cb7e 832 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
mbed_official 159:7130f322cb7e 833
mbed_official 159:7130f322cb7e 834 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
mbed_official 159:7130f322cb7e 835 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
mbed_official 159:7130f322cb7e 836
mbed_official 159:7130f322cb7e 837 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
mbed_official 159:7130f322cb7e 838 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
mbed_official 159:7130f322cb7e 839
mbed_official 159:7130f322cb7e 840 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
mbed_official 159:7130f322cb7e 841 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
mbed_official 159:7130f322cb7e 842
mbed_official 159:7130f322cb7e 843 /* SCB Cache Size Selection Register Definitions */
mbed_official 159:7130f322cb7e 844 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
mbed_official 159:7130f322cb7e 845 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
mbed_official 159:7130f322cb7e 846
mbed_official 159:7130f322cb7e 847 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
mbed_official 159:7130f322cb7e 848 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
mbed_official 159:7130f322cb7e 849
mbed_official 159:7130f322cb7e 850 /* SCB Software Triggered Interrupt Register Definitions */
mbed_official 159:7130f322cb7e 851 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
mbed_official 159:7130f322cb7e 852 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
mbed_official 159:7130f322cb7e 853
mbed_official 159:7130f322cb7e 854 /* SCB D-Cache Invalidate by Set-way Register Definitions */
mbed_official 159:7130f322cb7e 855 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
mbed_official 159:7130f322cb7e 856 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
mbed_official 159:7130f322cb7e 857
mbed_official 159:7130f322cb7e 858 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
mbed_official 159:7130f322cb7e 859 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
mbed_official 159:7130f322cb7e 860
mbed_official 159:7130f322cb7e 861 /* SCB D-Cache Clean by Set-way Register Definitions */
mbed_official 159:7130f322cb7e 862 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
mbed_official 159:7130f322cb7e 863 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
mbed_official 159:7130f322cb7e 864
mbed_official 159:7130f322cb7e 865 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
mbed_official 159:7130f322cb7e 866 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
mbed_official 159:7130f322cb7e 867
mbed_official 159:7130f322cb7e 868 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
mbed_official 159:7130f322cb7e 869 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
mbed_official 159:7130f322cb7e 870 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
mbed_official 159:7130f322cb7e 871
mbed_official 159:7130f322cb7e 872 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
mbed_official 159:7130f322cb7e 873 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
mbed_official 159:7130f322cb7e 874
mbed_official 159:7130f322cb7e 875 /* Instruction Tightly-Coupled Memory Control Register Definitions */
mbed_official 159:7130f322cb7e 876 #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
mbed_official 159:7130f322cb7e 877 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
mbed_official 159:7130f322cb7e 878
mbed_official 159:7130f322cb7e 879 #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
mbed_official 159:7130f322cb7e 880 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
mbed_official 159:7130f322cb7e 881
mbed_official 159:7130f322cb7e 882 #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
mbed_official 159:7130f322cb7e 883 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
mbed_official 159:7130f322cb7e 884
mbed_official 159:7130f322cb7e 885 #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
mbed_official 159:7130f322cb7e 886 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
mbed_official 159:7130f322cb7e 887
mbed_official 159:7130f322cb7e 888 /* Data Tightly-Coupled Memory Control Register Definitions */
mbed_official 159:7130f322cb7e 889 #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
mbed_official 159:7130f322cb7e 890 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
mbed_official 159:7130f322cb7e 891
mbed_official 159:7130f322cb7e 892 #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
mbed_official 159:7130f322cb7e 893 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
mbed_official 159:7130f322cb7e 894
mbed_official 159:7130f322cb7e 895 #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
mbed_official 159:7130f322cb7e 896 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
mbed_official 159:7130f322cb7e 897
mbed_official 159:7130f322cb7e 898 #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
mbed_official 159:7130f322cb7e 899 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
mbed_official 159:7130f322cb7e 900
mbed_official 159:7130f322cb7e 901 /* AHBP Control Register Definitions */
mbed_official 159:7130f322cb7e 902 #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
mbed_official 159:7130f322cb7e 903 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
mbed_official 159:7130f322cb7e 904
mbed_official 159:7130f322cb7e 905 #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
mbed_official 159:7130f322cb7e 906 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
mbed_official 159:7130f322cb7e 907
mbed_official 159:7130f322cb7e 908 /* L1 Cache Control Register Definitions */
mbed_official 159:7130f322cb7e 909 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
mbed_official 159:7130f322cb7e 910 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
mbed_official 159:7130f322cb7e 911
mbed_official 159:7130f322cb7e 912 #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
mbed_official 159:7130f322cb7e 913 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
mbed_official 159:7130f322cb7e 914
mbed_official 159:7130f322cb7e 915 #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
mbed_official 159:7130f322cb7e 916 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
mbed_official 159:7130f322cb7e 917
mbed_official 159:7130f322cb7e 918 /* AHBS Control Register Definitions */
mbed_official 159:7130f322cb7e 919 #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
mbed_official 159:7130f322cb7e 920 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
mbed_official 159:7130f322cb7e 921
mbed_official 159:7130f322cb7e 922 #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
mbed_official 159:7130f322cb7e 923 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
mbed_official 159:7130f322cb7e 924
mbed_official 159:7130f322cb7e 925 #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
mbed_official 159:7130f322cb7e 926 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
mbed_official 159:7130f322cb7e 927
mbed_official 159:7130f322cb7e 928 /* Auxiliary Bus Fault Status Register Definitions */
mbed_official 159:7130f322cb7e 929 #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
mbed_official 159:7130f322cb7e 930 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
mbed_official 159:7130f322cb7e 931
mbed_official 159:7130f322cb7e 932 #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
mbed_official 159:7130f322cb7e 933 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
mbed_official 159:7130f322cb7e 934
mbed_official 159:7130f322cb7e 935 #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
mbed_official 159:7130f322cb7e 936 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
mbed_official 159:7130f322cb7e 937
mbed_official 159:7130f322cb7e 938 #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
mbed_official 159:7130f322cb7e 939 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
mbed_official 159:7130f322cb7e 940
mbed_official 159:7130f322cb7e 941 #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
mbed_official 159:7130f322cb7e 942 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
mbed_official 159:7130f322cb7e 943
mbed_official 159:7130f322cb7e 944 #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
mbed_official 159:7130f322cb7e 945 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
mbed_official 159:7130f322cb7e 946
mbed_official 159:7130f322cb7e 947 /*@} end of group CMSIS_SCB */
mbed_official 159:7130f322cb7e 948
mbed_official 159:7130f322cb7e 949
mbed_official 159:7130f322cb7e 950 /**
mbed_official 159:7130f322cb7e 951 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 952 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
mbed_official 159:7130f322cb7e 953 \brief Type definitions for the System Control and ID Register not in the SCB
mbed_official 159:7130f322cb7e 954 @{
mbed_official 159:7130f322cb7e 955 */
mbed_official 159:7130f322cb7e 956
mbed_official 159:7130f322cb7e 957 /**
mbed_official 159:7130f322cb7e 958 \brief Structure type to access the System Control and ID Register not in the SCB.
mbed_official 159:7130f322cb7e 959 */
mbed_official 159:7130f322cb7e 960 typedef struct
mbed_official 159:7130f322cb7e 961 {
mbed_official 159:7130f322cb7e 962 uint32_t RESERVED0[1U];
mbed_official 159:7130f322cb7e 963 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
mbed_official 159:7130f322cb7e 964 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
mbed_official 159:7130f322cb7e 965 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
mbed_official 159:7130f322cb7e 966 } SCnSCB_Type;
mbed_official 159:7130f322cb7e 967
mbed_official 159:7130f322cb7e 968 /* Interrupt Controller Type Register Definitions */
mbed_official 159:7130f322cb7e 969 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
mbed_official 159:7130f322cb7e 970 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
mbed_official 159:7130f322cb7e 971
mbed_official 159:7130f322cb7e 972 /*@} end of group CMSIS_SCnotSCB */
mbed_official 159:7130f322cb7e 973
mbed_official 159:7130f322cb7e 974
mbed_official 159:7130f322cb7e 975 /**
mbed_official 159:7130f322cb7e 976 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 977 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
mbed_official 159:7130f322cb7e 978 \brief Type definitions for the System Timer Registers.
mbed_official 159:7130f322cb7e 979 @{
mbed_official 159:7130f322cb7e 980 */
mbed_official 159:7130f322cb7e 981
mbed_official 159:7130f322cb7e 982 /**
mbed_official 159:7130f322cb7e 983 \brief Structure type to access the System Timer (SysTick).
mbed_official 159:7130f322cb7e 984 */
mbed_official 159:7130f322cb7e 985 typedef struct
mbed_official 159:7130f322cb7e 986 {
mbed_official 159:7130f322cb7e 987 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
mbed_official 159:7130f322cb7e 988 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
mbed_official 159:7130f322cb7e 989 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
mbed_official 159:7130f322cb7e 990 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
mbed_official 159:7130f322cb7e 991 } SysTick_Type;
mbed_official 159:7130f322cb7e 992
mbed_official 159:7130f322cb7e 993 /* SysTick Control / Status Register Definitions */
mbed_official 159:7130f322cb7e 994 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
mbed_official 159:7130f322cb7e 995 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
mbed_official 159:7130f322cb7e 996
mbed_official 159:7130f322cb7e 997 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
mbed_official 159:7130f322cb7e 998 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
mbed_official 159:7130f322cb7e 999
mbed_official 159:7130f322cb7e 1000 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
mbed_official 159:7130f322cb7e 1001 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
mbed_official 159:7130f322cb7e 1002
mbed_official 159:7130f322cb7e 1003 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
mbed_official 159:7130f322cb7e 1004 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
mbed_official 159:7130f322cb7e 1005
mbed_official 159:7130f322cb7e 1006 /* SysTick Reload Register Definitions */
mbed_official 159:7130f322cb7e 1007 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
mbed_official 159:7130f322cb7e 1008 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
mbed_official 159:7130f322cb7e 1009
mbed_official 159:7130f322cb7e 1010 /* SysTick Current Register Definitions */
mbed_official 159:7130f322cb7e 1011 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
mbed_official 159:7130f322cb7e 1012 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
mbed_official 159:7130f322cb7e 1013
mbed_official 159:7130f322cb7e 1014 /* SysTick Calibration Register Definitions */
mbed_official 159:7130f322cb7e 1015 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
mbed_official 159:7130f322cb7e 1016 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
mbed_official 159:7130f322cb7e 1017
mbed_official 159:7130f322cb7e 1018 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
mbed_official 159:7130f322cb7e 1019 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
mbed_official 159:7130f322cb7e 1020
mbed_official 159:7130f322cb7e 1021 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
mbed_official 159:7130f322cb7e 1022 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
mbed_official 159:7130f322cb7e 1023
mbed_official 159:7130f322cb7e 1024 /*@} end of group CMSIS_SysTick */
mbed_official 159:7130f322cb7e 1025
mbed_official 159:7130f322cb7e 1026
mbed_official 159:7130f322cb7e 1027 /**
mbed_official 159:7130f322cb7e 1028 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 1029 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
mbed_official 159:7130f322cb7e 1030 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
mbed_official 159:7130f322cb7e 1031 @{
mbed_official 159:7130f322cb7e 1032 */
mbed_official 159:7130f322cb7e 1033
mbed_official 159:7130f322cb7e 1034 /**
mbed_official 159:7130f322cb7e 1035 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
mbed_official 159:7130f322cb7e 1036 */
mbed_official 159:7130f322cb7e 1037 typedef struct
mbed_official 159:7130f322cb7e 1038 {
mbed_official 159:7130f322cb7e 1039 __OM union
mbed_official 159:7130f322cb7e 1040 {
mbed_official 159:7130f322cb7e 1041 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
mbed_official 159:7130f322cb7e 1042 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
mbed_official 159:7130f322cb7e 1043 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
mbed_official 159:7130f322cb7e 1044 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
mbed_official 159:7130f322cb7e 1045 uint32_t RESERVED0[864U];
mbed_official 159:7130f322cb7e 1046 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
mbed_official 159:7130f322cb7e 1047 uint32_t RESERVED1[15U];
mbed_official 159:7130f322cb7e 1048 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
mbed_official 159:7130f322cb7e 1049 uint32_t RESERVED2[15U];
mbed_official 159:7130f322cb7e 1050 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
mbed_official 159:7130f322cb7e 1051 uint32_t RESERVED3[29U];
mbed_official 159:7130f322cb7e 1052 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
mbed_official 159:7130f322cb7e 1053 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
mbed_official 159:7130f322cb7e 1054 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
mbed_official 159:7130f322cb7e 1055 uint32_t RESERVED4[43U];
mbed_official 159:7130f322cb7e 1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
mbed_official 159:7130f322cb7e 1057 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
mbed_official 159:7130f322cb7e 1058 uint32_t RESERVED5[1U];
mbed_official 159:7130f322cb7e 1059 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
mbed_official 159:7130f322cb7e 1060 uint32_t RESERVED6[4U];
mbed_official 159:7130f322cb7e 1061 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
mbed_official 159:7130f322cb7e 1062 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
mbed_official 159:7130f322cb7e 1063 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
mbed_official 159:7130f322cb7e 1064 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
mbed_official 159:7130f322cb7e 1065 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
mbed_official 159:7130f322cb7e 1066 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
mbed_official 159:7130f322cb7e 1067 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
mbed_official 159:7130f322cb7e 1068 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
mbed_official 159:7130f322cb7e 1069 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
mbed_official 159:7130f322cb7e 1070 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
mbed_official 159:7130f322cb7e 1071 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
mbed_official 159:7130f322cb7e 1072 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
mbed_official 159:7130f322cb7e 1073 } ITM_Type;
mbed_official 159:7130f322cb7e 1074
mbed_official 159:7130f322cb7e 1075 /* ITM Stimulus Port Register Definitions */
mbed_official 159:7130f322cb7e 1076 #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
mbed_official 159:7130f322cb7e 1077 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
mbed_official 159:7130f322cb7e 1078
mbed_official 159:7130f322cb7e 1079 #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
mbed_official 159:7130f322cb7e 1080 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
mbed_official 159:7130f322cb7e 1081
mbed_official 159:7130f322cb7e 1082 /* ITM Trace Privilege Register Definitions */
mbed_official 159:7130f322cb7e 1083 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
mbed_official 159:7130f322cb7e 1084 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
mbed_official 159:7130f322cb7e 1085
mbed_official 159:7130f322cb7e 1086 /* ITM Trace Control Register Definitions */
mbed_official 159:7130f322cb7e 1087 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
mbed_official 159:7130f322cb7e 1088 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
mbed_official 159:7130f322cb7e 1089
mbed_official 159:7130f322cb7e 1090 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
mbed_official 159:7130f322cb7e 1091 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
mbed_official 159:7130f322cb7e 1092
mbed_official 159:7130f322cb7e 1093 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
mbed_official 159:7130f322cb7e 1094 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
mbed_official 159:7130f322cb7e 1095
mbed_official 159:7130f322cb7e 1096 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
mbed_official 159:7130f322cb7e 1097 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
mbed_official 159:7130f322cb7e 1098
mbed_official 159:7130f322cb7e 1099 #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
mbed_official 159:7130f322cb7e 1100 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
mbed_official 159:7130f322cb7e 1101
mbed_official 159:7130f322cb7e 1102 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
mbed_official 159:7130f322cb7e 1103 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
mbed_official 159:7130f322cb7e 1104
mbed_official 159:7130f322cb7e 1105 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
mbed_official 159:7130f322cb7e 1106 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
mbed_official 159:7130f322cb7e 1107
mbed_official 159:7130f322cb7e 1108 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
mbed_official 159:7130f322cb7e 1109 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
mbed_official 159:7130f322cb7e 1110
mbed_official 159:7130f322cb7e 1111 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
mbed_official 159:7130f322cb7e 1112 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
mbed_official 159:7130f322cb7e 1113
mbed_official 159:7130f322cb7e 1114 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
mbed_official 159:7130f322cb7e 1115 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
mbed_official 159:7130f322cb7e 1116
mbed_official 159:7130f322cb7e 1117 /* ITM Integration Write Register Definitions */
mbed_official 159:7130f322cb7e 1118 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
mbed_official 159:7130f322cb7e 1119 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
mbed_official 159:7130f322cb7e 1120
mbed_official 159:7130f322cb7e 1121 /* ITM Integration Read Register Definitions */
mbed_official 159:7130f322cb7e 1122 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
mbed_official 159:7130f322cb7e 1123 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
mbed_official 159:7130f322cb7e 1124
mbed_official 159:7130f322cb7e 1125 /* ITM Integration Mode Control Register Definitions */
mbed_official 159:7130f322cb7e 1126 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
mbed_official 159:7130f322cb7e 1127 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
mbed_official 159:7130f322cb7e 1128
mbed_official 159:7130f322cb7e 1129 /* ITM Lock Status Register Definitions */
mbed_official 159:7130f322cb7e 1130 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
mbed_official 159:7130f322cb7e 1131 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
mbed_official 159:7130f322cb7e 1132
mbed_official 159:7130f322cb7e 1133 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
mbed_official 159:7130f322cb7e 1134 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
mbed_official 159:7130f322cb7e 1135
mbed_official 159:7130f322cb7e 1136 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
mbed_official 159:7130f322cb7e 1137 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
mbed_official 159:7130f322cb7e 1138
mbed_official 159:7130f322cb7e 1139 /*@}*/ /* end of group CMSIS_ITM */
mbed_official 159:7130f322cb7e 1140
mbed_official 159:7130f322cb7e 1141
mbed_official 159:7130f322cb7e 1142 /**
mbed_official 159:7130f322cb7e 1143 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 1144 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
mbed_official 159:7130f322cb7e 1145 \brief Type definitions for the Data Watchpoint and Trace (DWT)
mbed_official 159:7130f322cb7e 1146 @{
mbed_official 159:7130f322cb7e 1147 */
mbed_official 159:7130f322cb7e 1148
mbed_official 159:7130f322cb7e 1149 /**
mbed_official 159:7130f322cb7e 1150 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
mbed_official 159:7130f322cb7e 1151 */
mbed_official 159:7130f322cb7e 1152 typedef struct
mbed_official 159:7130f322cb7e 1153 {
mbed_official 159:7130f322cb7e 1154 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
mbed_official 159:7130f322cb7e 1155 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
mbed_official 159:7130f322cb7e 1156 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
mbed_official 159:7130f322cb7e 1157 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
mbed_official 159:7130f322cb7e 1158 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
mbed_official 159:7130f322cb7e 1159 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
mbed_official 159:7130f322cb7e 1160 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
mbed_official 159:7130f322cb7e 1161 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
mbed_official 159:7130f322cb7e 1162 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
mbed_official 159:7130f322cb7e 1163 uint32_t RESERVED1[1U];
mbed_official 159:7130f322cb7e 1164 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
mbed_official 159:7130f322cb7e 1165 uint32_t RESERVED2[1U];
mbed_official 159:7130f322cb7e 1166 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
mbed_official 159:7130f322cb7e 1167 uint32_t RESERVED3[1U];
mbed_official 159:7130f322cb7e 1168 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
mbed_official 159:7130f322cb7e 1169 uint32_t RESERVED4[1U];
mbed_official 159:7130f322cb7e 1170 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
mbed_official 159:7130f322cb7e 1171 uint32_t RESERVED5[1U];
mbed_official 159:7130f322cb7e 1172 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
mbed_official 159:7130f322cb7e 1173 uint32_t RESERVED6[1U];
mbed_official 159:7130f322cb7e 1174 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
mbed_official 159:7130f322cb7e 1175 uint32_t RESERVED7[1U];
mbed_official 159:7130f322cb7e 1176 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
mbed_official 159:7130f322cb7e 1177 uint32_t RESERVED8[1U];
mbed_official 159:7130f322cb7e 1178 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
mbed_official 159:7130f322cb7e 1179 uint32_t RESERVED9[1U];
mbed_official 159:7130f322cb7e 1180 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
mbed_official 159:7130f322cb7e 1181 uint32_t RESERVED10[1U];
mbed_official 159:7130f322cb7e 1182 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
mbed_official 159:7130f322cb7e 1183 uint32_t RESERVED11[1U];
mbed_official 159:7130f322cb7e 1184 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
mbed_official 159:7130f322cb7e 1185 uint32_t RESERVED12[1U];
mbed_official 159:7130f322cb7e 1186 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
mbed_official 159:7130f322cb7e 1187 uint32_t RESERVED13[1U];
mbed_official 159:7130f322cb7e 1188 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
mbed_official 159:7130f322cb7e 1189 uint32_t RESERVED14[1U];
mbed_official 159:7130f322cb7e 1190 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
mbed_official 159:7130f322cb7e 1191 uint32_t RESERVED15[1U];
mbed_official 159:7130f322cb7e 1192 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
mbed_official 159:7130f322cb7e 1193 uint32_t RESERVED16[1U];
mbed_official 159:7130f322cb7e 1194 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
mbed_official 159:7130f322cb7e 1195 uint32_t RESERVED17[1U];
mbed_official 159:7130f322cb7e 1196 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
mbed_official 159:7130f322cb7e 1197 uint32_t RESERVED18[1U];
mbed_official 159:7130f322cb7e 1198 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
mbed_official 159:7130f322cb7e 1199 uint32_t RESERVED19[1U];
mbed_official 159:7130f322cb7e 1200 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
mbed_official 159:7130f322cb7e 1201 uint32_t RESERVED20[1U];
mbed_official 159:7130f322cb7e 1202 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
mbed_official 159:7130f322cb7e 1203 uint32_t RESERVED21[1U];
mbed_official 159:7130f322cb7e 1204 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
mbed_official 159:7130f322cb7e 1205 uint32_t RESERVED22[1U];
mbed_official 159:7130f322cb7e 1206 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
mbed_official 159:7130f322cb7e 1207 uint32_t RESERVED23[1U];
mbed_official 159:7130f322cb7e 1208 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
mbed_official 159:7130f322cb7e 1209 uint32_t RESERVED24[1U];
mbed_official 159:7130f322cb7e 1210 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
mbed_official 159:7130f322cb7e 1211 uint32_t RESERVED25[1U];
mbed_official 159:7130f322cb7e 1212 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
mbed_official 159:7130f322cb7e 1213 uint32_t RESERVED26[1U];
mbed_official 159:7130f322cb7e 1214 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
mbed_official 159:7130f322cb7e 1215 uint32_t RESERVED27[1U];
mbed_official 159:7130f322cb7e 1216 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
mbed_official 159:7130f322cb7e 1217 uint32_t RESERVED28[1U];
mbed_official 159:7130f322cb7e 1218 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
mbed_official 159:7130f322cb7e 1219 uint32_t RESERVED29[1U];
mbed_official 159:7130f322cb7e 1220 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
mbed_official 159:7130f322cb7e 1221 uint32_t RESERVED30[1U];
mbed_official 159:7130f322cb7e 1222 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
mbed_official 159:7130f322cb7e 1223 uint32_t RESERVED31[1U];
mbed_official 159:7130f322cb7e 1224 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
mbed_official 159:7130f322cb7e 1225 uint32_t RESERVED32[934U];
mbed_official 159:7130f322cb7e 1226 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
mbed_official 159:7130f322cb7e 1227 uint32_t RESERVED33[1U];
mbed_official 159:7130f322cb7e 1228 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
mbed_official 159:7130f322cb7e 1229 } DWT_Type;
mbed_official 159:7130f322cb7e 1230
mbed_official 159:7130f322cb7e 1231 /* DWT Control Register Definitions */
mbed_official 159:7130f322cb7e 1232 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
mbed_official 159:7130f322cb7e 1233 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
mbed_official 159:7130f322cb7e 1234
mbed_official 159:7130f322cb7e 1235 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
mbed_official 159:7130f322cb7e 1236 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
mbed_official 159:7130f322cb7e 1237
mbed_official 159:7130f322cb7e 1238 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
mbed_official 159:7130f322cb7e 1239 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
mbed_official 159:7130f322cb7e 1240
mbed_official 159:7130f322cb7e 1241 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
mbed_official 159:7130f322cb7e 1242 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
mbed_official 159:7130f322cb7e 1243
mbed_official 159:7130f322cb7e 1244 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
mbed_official 159:7130f322cb7e 1245 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
mbed_official 159:7130f322cb7e 1246
mbed_official 159:7130f322cb7e 1247 #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
mbed_official 159:7130f322cb7e 1248 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
mbed_official 159:7130f322cb7e 1249
mbed_official 159:7130f322cb7e 1250 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
mbed_official 159:7130f322cb7e 1251 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
mbed_official 159:7130f322cb7e 1252
mbed_official 159:7130f322cb7e 1253 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
mbed_official 159:7130f322cb7e 1254 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
mbed_official 159:7130f322cb7e 1255
mbed_official 159:7130f322cb7e 1256 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
mbed_official 159:7130f322cb7e 1257 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
mbed_official 159:7130f322cb7e 1258
mbed_official 159:7130f322cb7e 1259 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
mbed_official 159:7130f322cb7e 1260 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
mbed_official 159:7130f322cb7e 1261
mbed_official 159:7130f322cb7e 1262 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
mbed_official 159:7130f322cb7e 1263 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
mbed_official 159:7130f322cb7e 1264
mbed_official 159:7130f322cb7e 1265 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
mbed_official 159:7130f322cb7e 1266 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
mbed_official 159:7130f322cb7e 1267
mbed_official 159:7130f322cb7e 1268 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
mbed_official 159:7130f322cb7e 1269 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
mbed_official 159:7130f322cb7e 1270
mbed_official 159:7130f322cb7e 1271 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
mbed_official 159:7130f322cb7e 1272 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
mbed_official 159:7130f322cb7e 1273
mbed_official 159:7130f322cb7e 1274 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
mbed_official 159:7130f322cb7e 1275 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
mbed_official 159:7130f322cb7e 1276
mbed_official 159:7130f322cb7e 1277 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
mbed_official 159:7130f322cb7e 1278 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
mbed_official 159:7130f322cb7e 1279
mbed_official 159:7130f322cb7e 1280 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
mbed_official 159:7130f322cb7e 1281 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
mbed_official 159:7130f322cb7e 1282
mbed_official 159:7130f322cb7e 1283 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
mbed_official 159:7130f322cb7e 1284 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
mbed_official 159:7130f322cb7e 1285
mbed_official 159:7130f322cb7e 1286 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
mbed_official 159:7130f322cb7e 1287 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
mbed_official 159:7130f322cb7e 1288
mbed_official 159:7130f322cb7e 1289 /* DWT CPI Count Register Definitions */
mbed_official 159:7130f322cb7e 1290 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
mbed_official 159:7130f322cb7e 1291 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
mbed_official 159:7130f322cb7e 1292
mbed_official 159:7130f322cb7e 1293 /* DWT Exception Overhead Count Register Definitions */
mbed_official 159:7130f322cb7e 1294 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
mbed_official 159:7130f322cb7e 1295 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
mbed_official 159:7130f322cb7e 1296
mbed_official 159:7130f322cb7e 1297 /* DWT Sleep Count Register Definitions */
mbed_official 159:7130f322cb7e 1298 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
mbed_official 159:7130f322cb7e 1299 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
mbed_official 159:7130f322cb7e 1300
mbed_official 159:7130f322cb7e 1301 /* DWT LSU Count Register Definitions */
mbed_official 159:7130f322cb7e 1302 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
mbed_official 159:7130f322cb7e 1303 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
mbed_official 159:7130f322cb7e 1304
mbed_official 159:7130f322cb7e 1305 /* DWT Folded-instruction Count Register Definitions */
mbed_official 159:7130f322cb7e 1306 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
mbed_official 159:7130f322cb7e 1307 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
mbed_official 159:7130f322cb7e 1308
mbed_official 159:7130f322cb7e 1309 /* DWT Comparator Function Register Definitions */
mbed_official 159:7130f322cb7e 1310 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
mbed_official 159:7130f322cb7e 1311 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
mbed_official 159:7130f322cb7e 1312
mbed_official 159:7130f322cb7e 1313 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
mbed_official 159:7130f322cb7e 1314 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
mbed_official 159:7130f322cb7e 1315
mbed_official 159:7130f322cb7e 1316 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
mbed_official 159:7130f322cb7e 1317 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
mbed_official 159:7130f322cb7e 1318
mbed_official 159:7130f322cb7e 1319 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
mbed_official 159:7130f322cb7e 1320 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
mbed_official 159:7130f322cb7e 1321
mbed_official 159:7130f322cb7e 1322 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
mbed_official 159:7130f322cb7e 1323 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
mbed_official 159:7130f322cb7e 1324
mbed_official 159:7130f322cb7e 1325 /*@}*/ /* end of group CMSIS_DWT */
mbed_official 159:7130f322cb7e 1326
mbed_official 159:7130f322cb7e 1327
mbed_official 159:7130f322cb7e 1328 /**
mbed_official 159:7130f322cb7e 1329 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 1330 \defgroup CMSIS_TPI Trace Port Interface (TPI)
mbed_official 159:7130f322cb7e 1331 \brief Type definitions for the Trace Port Interface (TPI)
mbed_official 159:7130f322cb7e 1332 @{
mbed_official 159:7130f322cb7e 1333 */
mbed_official 159:7130f322cb7e 1334
mbed_official 159:7130f322cb7e 1335 /**
mbed_official 159:7130f322cb7e 1336 \brief Structure type to access the Trace Port Interface Register (TPI).
mbed_official 159:7130f322cb7e 1337 */
mbed_official 159:7130f322cb7e 1338 typedef struct
mbed_official 159:7130f322cb7e 1339 {
mbed_official 159:7130f322cb7e 1340 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
mbed_official 159:7130f322cb7e 1341 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
mbed_official 159:7130f322cb7e 1342 uint32_t RESERVED0[2U];
mbed_official 159:7130f322cb7e 1343 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
mbed_official 159:7130f322cb7e 1344 uint32_t RESERVED1[55U];
mbed_official 159:7130f322cb7e 1345 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
mbed_official 159:7130f322cb7e 1346 uint32_t RESERVED2[131U];
mbed_official 159:7130f322cb7e 1347 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
mbed_official 159:7130f322cb7e 1348 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
mbed_official 159:7130f322cb7e 1349 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
mbed_official 159:7130f322cb7e 1350 uint32_t RESERVED3[759U];
mbed_official 159:7130f322cb7e 1351 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
mbed_official 159:7130f322cb7e 1352 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
mbed_official 159:7130f322cb7e 1353 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
mbed_official 159:7130f322cb7e 1354 uint32_t RESERVED4[1U];
mbed_official 159:7130f322cb7e 1355 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
mbed_official 159:7130f322cb7e 1356 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
mbed_official 159:7130f322cb7e 1357 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
mbed_official 159:7130f322cb7e 1358 uint32_t RESERVED5[39U];
mbed_official 159:7130f322cb7e 1359 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
mbed_official 159:7130f322cb7e 1360 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
mbed_official 159:7130f322cb7e 1361 uint32_t RESERVED7[8U];
mbed_official 159:7130f322cb7e 1362 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
mbed_official 159:7130f322cb7e 1363 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
mbed_official 159:7130f322cb7e 1364 } TPI_Type;
mbed_official 159:7130f322cb7e 1365
mbed_official 159:7130f322cb7e 1366 /* TPI Asynchronous Clock Prescaler Register Definitions */
mbed_official 159:7130f322cb7e 1367 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
mbed_official 159:7130f322cb7e 1368 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
mbed_official 159:7130f322cb7e 1369
mbed_official 159:7130f322cb7e 1370 /* TPI Selected Pin Protocol Register Definitions */
mbed_official 159:7130f322cb7e 1371 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
mbed_official 159:7130f322cb7e 1372 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
mbed_official 159:7130f322cb7e 1373
mbed_official 159:7130f322cb7e 1374 /* TPI Formatter and Flush Status Register Definitions */
mbed_official 159:7130f322cb7e 1375 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
mbed_official 159:7130f322cb7e 1376 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
mbed_official 159:7130f322cb7e 1377
mbed_official 159:7130f322cb7e 1378 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
mbed_official 159:7130f322cb7e 1379 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
mbed_official 159:7130f322cb7e 1380
mbed_official 159:7130f322cb7e 1381 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
mbed_official 159:7130f322cb7e 1382 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
mbed_official 159:7130f322cb7e 1383
mbed_official 159:7130f322cb7e 1384 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
mbed_official 159:7130f322cb7e 1385 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
mbed_official 159:7130f322cb7e 1386
mbed_official 159:7130f322cb7e 1387 /* TPI Formatter and Flush Control Register Definitions */
mbed_official 159:7130f322cb7e 1388 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
mbed_official 159:7130f322cb7e 1389 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
mbed_official 159:7130f322cb7e 1390
mbed_official 159:7130f322cb7e 1391 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
mbed_official 159:7130f322cb7e 1392 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
mbed_official 159:7130f322cb7e 1393
mbed_official 159:7130f322cb7e 1394 /* TPI TRIGGER Register Definitions */
mbed_official 159:7130f322cb7e 1395 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
mbed_official 159:7130f322cb7e 1396 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
mbed_official 159:7130f322cb7e 1397
mbed_official 159:7130f322cb7e 1398 /* TPI Integration ETM Data Register Definitions (FIFO0) */
mbed_official 159:7130f322cb7e 1399 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
mbed_official 159:7130f322cb7e 1400 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
mbed_official 159:7130f322cb7e 1401
mbed_official 159:7130f322cb7e 1402 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
mbed_official 159:7130f322cb7e 1403 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
mbed_official 159:7130f322cb7e 1404
mbed_official 159:7130f322cb7e 1405 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
mbed_official 159:7130f322cb7e 1406 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
mbed_official 159:7130f322cb7e 1407
mbed_official 159:7130f322cb7e 1408 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
mbed_official 159:7130f322cb7e 1409 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
mbed_official 159:7130f322cb7e 1410
mbed_official 159:7130f322cb7e 1411 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
mbed_official 159:7130f322cb7e 1412 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
mbed_official 159:7130f322cb7e 1413
mbed_official 159:7130f322cb7e 1414 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
mbed_official 159:7130f322cb7e 1415 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
mbed_official 159:7130f322cb7e 1416
mbed_official 159:7130f322cb7e 1417 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
mbed_official 159:7130f322cb7e 1418 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
mbed_official 159:7130f322cb7e 1419
mbed_official 159:7130f322cb7e 1420 /* TPI ITATBCTR2 Register Definitions */
mbed_official 159:7130f322cb7e 1421 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
mbed_official 159:7130f322cb7e 1422 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
mbed_official 159:7130f322cb7e 1423
mbed_official 159:7130f322cb7e 1424 /* TPI Integration ITM Data Register Definitions (FIFO1) */
mbed_official 159:7130f322cb7e 1425 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
mbed_official 159:7130f322cb7e 1426 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
mbed_official 159:7130f322cb7e 1427
mbed_official 159:7130f322cb7e 1428 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
mbed_official 159:7130f322cb7e 1429 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
mbed_official 159:7130f322cb7e 1430
mbed_official 159:7130f322cb7e 1431 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
mbed_official 159:7130f322cb7e 1432 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
mbed_official 159:7130f322cb7e 1433
mbed_official 159:7130f322cb7e 1434 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
mbed_official 159:7130f322cb7e 1435 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
mbed_official 159:7130f322cb7e 1436
mbed_official 159:7130f322cb7e 1437 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
mbed_official 159:7130f322cb7e 1438 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
mbed_official 159:7130f322cb7e 1439
mbed_official 159:7130f322cb7e 1440 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
mbed_official 159:7130f322cb7e 1441 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
mbed_official 159:7130f322cb7e 1442
mbed_official 159:7130f322cb7e 1443 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
mbed_official 159:7130f322cb7e 1444 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
mbed_official 159:7130f322cb7e 1445
mbed_official 159:7130f322cb7e 1446 /* TPI ITATBCTR0 Register Definitions */
mbed_official 159:7130f322cb7e 1447 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
mbed_official 159:7130f322cb7e 1448 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
mbed_official 159:7130f322cb7e 1449
mbed_official 159:7130f322cb7e 1450 /* TPI Integration Mode Control Register Definitions */
mbed_official 159:7130f322cb7e 1451 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
mbed_official 159:7130f322cb7e 1452 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
mbed_official 159:7130f322cb7e 1453
mbed_official 159:7130f322cb7e 1454 /* TPI DEVID Register Definitions */
mbed_official 159:7130f322cb7e 1455 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
mbed_official 159:7130f322cb7e 1456 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
mbed_official 159:7130f322cb7e 1457
mbed_official 159:7130f322cb7e 1458 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
mbed_official 159:7130f322cb7e 1459 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
mbed_official 159:7130f322cb7e 1460
mbed_official 159:7130f322cb7e 1461 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
mbed_official 159:7130f322cb7e 1462 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
mbed_official 159:7130f322cb7e 1463
mbed_official 159:7130f322cb7e 1464 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
mbed_official 159:7130f322cb7e 1465 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
mbed_official 159:7130f322cb7e 1466
mbed_official 159:7130f322cb7e 1467 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
mbed_official 159:7130f322cb7e 1468 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
mbed_official 159:7130f322cb7e 1469
mbed_official 159:7130f322cb7e 1470 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
mbed_official 159:7130f322cb7e 1471 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
mbed_official 159:7130f322cb7e 1472
mbed_official 159:7130f322cb7e 1473 /* TPI DEVTYPE Register Definitions */
mbed_official 159:7130f322cb7e 1474 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
mbed_official 159:7130f322cb7e 1475 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
mbed_official 159:7130f322cb7e 1476
mbed_official 159:7130f322cb7e 1477 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
mbed_official 159:7130f322cb7e 1478 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
mbed_official 159:7130f322cb7e 1479
mbed_official 159:7130f322cb7e 1480 /*@}*/ /* end of group CMSIS_TPI */
mbed_official 159:7130f322cb7e 1481
mbed_official 159:7130f322cb7e 1482
mbed_official 159:7130f322cb7e 1483 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
mbed_official 159:7130f322cb7e 1484 /**
mbed_official 159:7130f322cb7e 1485 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 1486 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
mbed_official 159:7130f322cb7e 1487 \brief Type definitions for the Memory Protection Unit (MPU)
mbed_official 159:7130f322cb7e 1488 @{
mbed_official 159:7130f322cb7e 1489 */
mbed_official 159:7130f322cb7e 1490
mbed_official 159:7130f322cb7e 1491 /**
mbed_official 159:7130f322cb7e 1492 \brief Structure type to access the Memory Protection Unit (MPU).
mbed_official 159:7130f322cb7e 1493 */
mbed_official 159:7130f322cb7e 1494 typedef struct
mbed_official 159:7130f322cb7e 1495 {
mbed_official 159:7130f322cb7e 1496 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
mbed_official 159:7130f322cb7e 1497 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
mbed_official 159:7130f322cb7e 1498 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
mbed_official 159:7130f322cb7e 1499 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
mbed_official 159:7130f322cb7e 1500 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
mbed_official 159:7130f322cb7e 1501 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
mbed_official 159:7130f322cb7e 1502 __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
mbed_official 159:7130f322cb7e 1503 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
mbed_official 159:7130f322cb7e 1504 __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
mbed_official 159:7130f322cb7e 1505 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
mbed_official 159:7130f322cb7e 1506 __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
mbed_official 159:7130f322cb7e 1507 uint32_t RESERVED0[1];
mbed_official 159:7130f322cb7e 1508 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
mbed_official 159:7130f322cb7e 1509 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
mbed_official 159:7130f322cb7e 1510 } MPU_Type;
mbed_official 159:7130f322cb7e 1511
mbed_official 159:7130f322cb7e 1512 /* MPU Type Register Definitions */
mbed_official 159:7130f322cb7e 1513 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
mbed_official 159:7130f322cb7e 1514 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
mbed_official 159:7130f322cb7e 1515
mbed_official 159:7130f322cb7e 1516 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
mbed_official 159:7130f322cb7e 1517 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
mbed_official 159:7130f322cb7e 1518
mbed_official 159:7130f322cb7e 1519 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
mbed_official 159:7130f322cb7e 1520 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
mbed_official 159:7130f322cb7e 1521
mbed_official 159:7130f322cb7e 1522 /* MPU Control Register Definitions */
mbed_official 159:7130f322cb7e 1523 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
mbed_official 159:7130f322cb7e 1524 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
mbed_official 159:7130f322cb7e 1525
mbed_official 159:7130f322cb7e 1526 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
mbed_official 159:7130f322cb7e 1527 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
mbed_official 159:7130f322cb7e 1528
mbed_official 159:7130f322cb7e 1529 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
mbed_official 159:7130f322cb7e 1530 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
mbed_official 159:7130f322cb7e 1531
mbed_official 159:7130f322cb7e 1532 /* MPU Region Number Register Definitions */
mbed_official 159:7130f322cb7e 1533 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
mbed_official 159:7130f322cb7e 1534 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
mbed_official 159:7130f322cb7e 1535
mbed_official 159:7130f322cb7e 1536 /* MPU Region Base Address Register Definitions */
mbed_official 159:7130f322cb7e 1537 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
mbed_official 159:7130f322cb7e 1538 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
mbed_official 159:7130f322cb7e 1539
mbed_official 159:7130f322cb7e 1540 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
mbed_official 159:7130f322cb7e 1541 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
mbed_official 159:7130f322cb7e 1542
mbed_official 159:7130f322cb7e 1543 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
mbed_official 159:7130f322cb7e 1544 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
mbed_official 159:7130f322cb7e 1545
mbed_official 159:7130f322cb7e 1546 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
mbed_official 159:7130f322cb7e 1547 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
mbed_official 159:7130f322cb7e 1548
mbed_official 159:7130f322cb7e 1549 /* MPU Region Limit Address Register Definitions */
mbed_official 159:7130f322cb7e 1550 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
mbed_official 159:7130f322cb7e 1551 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
mbed_official 159:7130f322cb7e 1552
mbed_official 159:7130f322cb7e 1553 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
mbed_official 159:7130f322cb7e 1554 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
mbed_official 159:7130f322cb7e 1555
mbed_official 159:7130f322cb7e 1556 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
mbed_official 159:7130f322cb7e 1557 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
mbed_official 159:7130f322cb7e 1558
mbed_official 159:7130f322cb7e 1559 /* MPU Memory Attribute Indirection Register 0 Definitions */
mbed_official 159:7130f322cb7e 1560 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
mbed_official 159:7130f322cb7e 1561 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
mbed_official 159:7130f322cb7e 1562
mbed_official 159:7130f322cb7e 1563 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
mbed_official 159:7130f322cb7e 1564 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
mbed_official 159:7130f322cb7e 1565
mbed_official 159:7130f322cb7e 1566 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
mbed_official 159:7130f322cb7e 1567 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
mbed_official 159:7130f322cb7e 1568
mbed_official 159:7130f322cb7e 1569 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
mbed_official 159:7130f322cb7e 1570 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
mbed_official 159:7130f322cb7e 1571
mbed_official 159:7130f322cb7e 1572 /* MPU Memory Attribute Indirection Register 1 Definitions */
mbed_official 159:7130f322cb7e 1573 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
mbed_official 159:7130f322cb7e 1574 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
mbed_official 159:7130f322cb7e 1575
mbed_official 159:7130f322cb7e 1576 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
mbed_official 159:7130f322cb7e 1577 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
mbed_official 159:7130f322cb7e 1578
mbed_official 159:7130f322cb7e 1579 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
mbed_official 159:7130f322cb7e 1580 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
mbed_official 159:7130f322cb7e 1581
mbed_official 159:7130f322cb7e 1582 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
mbed_official 159:7130f322cb7e 1583 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
mbed_official 159:7130f322cb7e 1584
mbed_official 159:7130f322cb7e 1585 /*@} end of group CMSIS_MPU */
mbed_official 159:7130f322cb7e 1586 #endif
mbed_official 159:7130f322cb7e 1587
mbed_official 159:7130f322cb7e 1588
mbed_official 159:7130f322cb7e 1589 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
mbed_official 159:7130f322cb7e 1590 /**
mbed_official 159:7130f322cb7e 1591 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 1592 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
mbed_official 159:7130f322cb7e 1593 \brief Type definitions for the Security Attribution Unit (SAU)
mbed_official 159:7130f322cb7e 1594 @{
mbed_official 159:7130f322cb7e 1595 */
mbed_official 159:7130f322cb7e 1596
mbed_official 159:7130f322cb7e 1597 /**
mbed_official 159:7130f322cb7e 1598 \brief Structure type to access the Security Attribution Unit (SAU).
mbed_official 159:7130f322cb7e 1599 */
mbed_official 159:7130f322cb7e 1600 typedef struct
mbed_official 159:7130f322cb7e 1601 {
mbed_official 159:7130f322cb7e 1602 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
mbed_official 159:7130f322cb7e 1603 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
mbed_official 159:7130f322cb7e 1604 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
mbed_official 159:7130f322cb7e 1605 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
mbed_official 159:7130f322cb7e 1606 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
mbed_official 159:7130f322cb7e 1607 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
mbed_official 159:7130f322cb7e 1608 #else
mbed_official 159:7130f322cb7e 1609 uint32_t RESERVED0[3];
mbed_official 159:7130f322cb7e 1610 #endif
mbed_official 159:7130f322cb7e 1611 __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
mbed_official 159:7130f322cb7e 1612 __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
mbed_official 159:7130f322cb7e 1613 } SAU_Type;
mbed_official 159:7130f322cb7e 1614
mbed_official 159:7130f322cb7e 1615 /* SAU Control Register Definitions */
mbed_official 159:7130f322cb7e 1616 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
mbed_official 159:7130f322cb7e 1617 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
mbed_official 159:7130f322cb7e 1618
mbed_official 159:7130f322cb7e 1619 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
mbed_official 159:7130f322cb7e 1620 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
mbed_official 159:7130f322cb7e 1621
mbed_official 159:7130f322cb7e 1622 /* SAU Type Register Definitions */
mbed_official 159:7130f322cb7e 1623 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
mbed_official 159:7130f322cb7e 1624 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
mbed_official 159:7130f322cb7e 1625
mbed_official 159:7130f322cb7e 1626 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
mbed_official 159:7130f322cb7e 1627 /* SAU Region Number Register Definitions */
mbed_official 159:7130f322cb7e 1628 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
mbed_official 159:7130f322cb7e 1629 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
mbed_official 159:7130f322cb7e 1630
mbed_official 159:7130f322cb7e 1631 /* SAU Region Base Address Register Definitions */
mbed_official 159:7130f322cb7e 1632 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
mbed_official 159:7130f322cb7e 1633 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
mbed_official 159:7130f322cb7e 1634
mbed_official 159:7130f322cb7e 1635 /* SAU Region Limit Address Register Definitions */
mbed_official 159:7130f322cb7e 1636 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
mbed_official 159:7130f322cb7e 1637 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
mbed_official 159:7130f322cb7e 1638
mbed_official 159:7130f322cb7e 1639 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
mbed_official 159:7130f322cb7e 1640 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
mbed_official 159:7130f322cb7e 1641
mbed_official 159:7130f322cb7e 1642 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
mbed_official 159:7130f322cb7e 1643 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
mbed_official 159:7130f322cb7e 1644
mbed_official 159:7130f322cb7e 1645 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
mbed_official 159:7130f322cb7e 1646
mbed_official 159:7130f322cb7e 1647 /* Secure Fault Status Register Definitions */
mbed_official 159:7130f322cb7e 1648 #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
mbed_official 159:7130f322cb7e 1649 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
mbed_official 159:7130f322cb7e 1650
mbed_official 159:7130f322cb7e 1651 #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
mbed_official 159:7130f322cb7e 1652 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
mbed_official 159:7130f322cb7e 1653
mbed_official 159:7130f322cb7e 1654 #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
mbed_official 159:7130f322cb7e 1655 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
mbed_official 159:7130f322cb7e 1656
mbed_official 159:7130f322cb7e 1657 #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
mbed_official 159:7130f322cb7e 1658 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
mbed_official 159:7130f322cb7e 1659
mbed_official 159:7130f322cb7e 1660 #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
mbed_official 159:7130f322cb7e 1661 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
mbed_official 159:7130f322cb7e 1662
mbed_official 159:7130f322cb7e 1663 #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
mbed_official 159:7130f322cb7e 1664 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
mbed_official 159:7130f322cb7e 1665
mbed_official 159:7130f322cb7e 1666 #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
mbed_official 159:7130f322cb7e 1667 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
mbed_official 159:7130f322cb7e 1668
mbed_official 159:7130f322cb7e 1669 #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
mbed_official 159:7130f322cb7e 1670 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
mbed_official 159:7130f322cb7e 1671
mbed_official 159:7130f322cb7e 1672 /*@} end of group CMSIS_SAU */
mbed_official 159:7130f322cb7e 1673 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
mbed_official 159:7130f322cb7e 1674
mbed_official 159:7130f322cb7e 1675
mbed_official 159:7130f322cb7e 1676 /**
mbed_official 159:7130f322cb7e 1677 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 1678 \defgroup CMSIS_FPU Floating Point Unit (FPU)
mbed_official 159:7130f322cb7e 1679 \brief Type definitions for the Floating Point Unit (FPU)
mbed_official 159:7130f322cb7e 1680 @{
mbed_official 159:7130f322cb7e 1681 */
mbed_official 159:7130f322cb7e 1682
mbed_official 159:7130f322cb7e 1683 /**
mbed_official 159:7130f322cb7e 1684 \brief Structure type to access the Floating Point Unit (FPU).
mbed_official 159:7130f322cb7e 1685 */
mbed_official 159:7130f322cb7e 1686 typedef struct
mbed_official 159:7130f322cb7e 1687 {
mbed_official 159:7130f322cb7e 1688 uint32_t RESERVED0[1U];
mbed_official 159:7130f322cb7e 1689 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
mbed_official 159:7130f322cb7e 1690 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
mbed_official 159:7130f322cb7e 1691 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
mbed_official 159:7130f322cb7e 1692 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
mbed_official 159:7130f322cb7e 1693 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
mbed_official 159:7130f322cb7e 1694 } FPU_Type;
mbed_official 159:7130f322cb7e 1695
mbed_official 159:7130f322cb7e 1696 /* Floating-Point Context Control Register Definitions */
mbed_official 159:7130f322cb7e 1697 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
mbed_official 159:7130f322cb7e 1698 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
mbed_official 159:7130f322cb7e 1699
mbed_official 159:7130f322cb7e 1700 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
mbed_official 159:7130f322cb7e 1701 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
mbed_official 159:7130f322cb7e 1702
mbed_official 159:7130f322cb7e 1703 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
mbed_official 159:7130f322cb7e 1704 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
mbed_official 159:7130f322cb7e 1705
mbed_official 159:7130f322cb7e 1706 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
mbed_official 159:7130f322cb7e 1707 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
mbed_official 159:7130f322cb7e 1708
mbed_official 159:7130f322cb7e 1709 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
mbed_official 159:7130f322cb7e 1710 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
mbed_official 159:7130f322cb7e 1711
mbed_official 159:7130f322cb7e 1712 #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
mbed_official 159:7130f322cb7e 1713 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
mbed_official 159:7130f322cb7e 1714
mbed_official 159:7130f322cb7e 1715 #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
mbed_official 159:7130f322cb7e 1716 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
mbed_official 159:7130f322cb7e 1717
mbed_official 159:7130f322cb7e 1718 #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
mbed_official 159:7130f322cb7e 1719 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
mbed_official 159:7130f322cb7e 1720
mbed_official 159:7130f322cb7e 1721 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
mbed_official 159:7130f322cb7e 1722 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
mbed_official 159:7130f322cb7e 1723
mbed_official 159:7130f322cb7e 1724 #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
mbed_official 159:7130f322cb7e 1725 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
mbed_official 159:7130f322cb7e 1726
mbed_official 159:7130f322cb7e 1727 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
mbed_official 159:7130f322cb7e 1728 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
mbed_official 159:7130f322cb7e 1729
mbed_official 159:7130f322cb7e 1730 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
mbed_official 159:7130f322cb7e 1731 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
mbed_official 159:7130f322cb7e 1732
mbed_official 159:7130f322cb7e 1733 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
mbed_official 159:7130f322cb7e 1734 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
mbed_official 159:7130f322cb7e 1735
mbed_official 159:7130f322cb7e 1736 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
mbed_official 159:7130f322cb7e 1737 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
mbed_official 159:7130f322cb7e 1738
mbed_official 159:7130f322cb7e 1739 #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
mbed_official 159:7130f322cb7e 1740 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
mbed_official 159:7130f322cb7e 1741
mbed_official 159:7130f322cb7e 1742 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
mbed_official 159:7130f322cb7e 1743 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
mbed_official 159:7130f322cb7e 1744
mbed_official 159:7130f322cb7e 1745 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
mbed_official 159:7130f322cb7e 1746 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
mbed_official 159:7130f322cb7e 1747
mbed_official 159:7130f322cb7e 1748 /* Floating-Point Context Address Register Definitions */
mbed_official 159:7130f322cb7e 1749 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
mbed_official 159:7130f322cb7e 1750 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
mbed_official 159:7130f322cb7e 1751
mbed_official 159:7130f322cb7e 1752 /* Floating-Point Default Status Control Register Definitions */
mbed_official 159:7130f322cb7e 1753 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
mbed_official 159:7130f322cb7e 1754 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
mbed_official 159:7130f322cb7e 1755
mbed_official 159:7130f322cb7e 1756 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
mbed_official 159:7130f322cb7e 1757 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
mbed_official 159:7130f322cb7e 1758
mbed_official 159:7130f322cb7e 1759 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
mbed_official 159:7130f322cb7e 1760 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
mbed_official 159:7130f322cb7e 1761
mbed_official 159:7130f322cb7e 1762 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
mbed_official 159:7130f322cb7e 1763 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
mbed_official 159:7130f322cb7e 1764
mbed_official 159:7130f322cb7e 1765 /* Media and FP Feature Register 0 Definitions */
mbed_official 159:7130f322cb7e 1766 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
mbed_official 159:7130f322cb7e 1767 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
mbed_official 159:7130f322cb7e 1768
mbed_official 159:7130f322cb7e 1769 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
mbed_official 159:7130f322cb7e 1770 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
mbed_official 159:7130f322cb7e 1771
mbed_official 159:7130f322cb7e 1772 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
mbed_official 159:7130f322cb7e 1773 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
mbed_official 159:7130f322cb7e 1774
mbed_official 159:7130f322cb7e 1775 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
mbed_official 159:7130f322cb7e 1776 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
mbed_official 159:7130f322cb7e 1777
mbed_official 159:7130f322cb7e 1778 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
mbed_official 159:7130f322cb7e 1779 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
mbed_official 159:7130f322cb7e 1780
mbed_official 159:7130f322cb7e 1781 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
mbed_official 159:7130f322cb7e 1782 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
mbed_official 159:7130f322cb7e 1783
mbed_official 159:7130f322cb7e 1784 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
mbed_official 159:7130f322cb7e 1785 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
mbed_official 159:7130f322cb7e 1786
mbed_official 159:7130f322cb7e 1787 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
mbed_official 159:7130f322cb7e 1788 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
mbed_official 159:7130f322cb7e 1789
mbed_official 159:7130f322cb7e 1790 /* Media and FP Feature Register 1 Definitions */
mbed_official 159:7130f322cb7e 1791 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
mbed_official 159:7130f322cb7e 1792 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
mbed_official 159:7130f322cb7e 1793
mbed_official 159:7130f322cb7e 1794 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
mbed_official 159:7130f322cb7e 1795 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
mbed_official 159:7130f322cb7e 1796
mbed_official 159:7130f322cb7e 1797 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
mbed_official 159:7130f322cb7e 1798 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
mbed_official 159:7130f322cb7e 1799
mbed_official 159:7130f322cb7e 1800 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
mbed_official 159:7130f322cb7e 1801 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
mbed_official 159:7130f322cb7e 1802
mbed_official 159:7130f322cb7e 1803 /*@} end of group CMSIS_FPU */
mbed_official 159:7130f322cb7e 1804
mbed_official 159:7130f322cb7e 1805
mbed_official 159:7130f322cb7e 1806 /**
mbed_official 159:7130f322cb7e 1807 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 1808 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mbed_official 159:7130f322cb7e 1809 \brief Type definitions for the Core Debug Registers
mbed_official 159:7130f322cb7e 1810 @{
mbed_official 159:7130f322cb7e 1811 */
mbed_official 159:7130f322cb7e 1812
mbed_official 159:7130f322cb7e 1813 /**
mbed_official 159:7130f322cb7e 1814 \brief Structure type to access the Core Debug Register (CoreDebug).
mbed_official 159:7130f322cb7e 1815 */
mbed_official 159:7130f322cb7e 1816 typedef struct
mbed_official 159:7130f322cb7e 1817 {
mbed_official 159:7130f322cb7e 1818 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
mbed_official 159:7130f322cb7e 1819 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
mbed_official 159:7130f322cb7e 1820 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
mbed_official 159:7130f322cb7e 1821 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
mbed_official 159:7130f322cb7e 1822 uint32_t RESERVED4[1U];
mbed_official 159:7130f322cb7e 1823 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
mbed_official 159:7130f322cb7e 1824 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
mbed_official 159:7130f322cb7e 1825 } CoreDebug_Type;
mbed_official 159:7130f322cb7e 1826
mbed_official 159:7130f322cb7e 1827 /* Debug Halting Control and Status Register Definitions */
mbed_official 159:7130f322cb7e 1828 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
mbed_official 159:7130f322cb7e 1829 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
mbed_official 159:7130f322cb7e 1830
mbed_official 159:7130f322cb7e 1831 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
mbed_official 159:7130f322cb7e 1832 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
mbed_official 159:7130f322cb7e 1833
mbed_official 159:7130f322cb7e 1834 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
mbed_official 159:7130f322cb7e 1835 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
mbed_official 159:7130f322cb7e 1836
mbed_official 159:7130f322cb7e 1837 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
mbed_official 159:7130f322cb7e 1838 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
mbed_official 159:7130f322cb7e 1839
mbed_official 159:7130f322cb7e 1840 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
mbed_official 159:7130f322cb7e 1841 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
mbed_official 159:7130f322cb7e 1842
mbed_official 159:7130f322cb7e 1843 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
mbed_official 159:7130f322cb7e 1844 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
mbed_official 159:7130f322cb7e 1845
mbed_official 159:7130f322cb7e 1846 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
mbed_official 159:7130f322cb7e 1847 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
mbed_official 159:7130f322cb7e 1848
mbed_official 159:7130f322cb7e 1849 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
mbed_official 159:7130f322cb7e 1850 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
mbed_official 159:7130f322cb7e 1851
mbed_official 159:7130f322cb7e 1852 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
mbed_official 159:7130f322cb7e 1853 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
mbed_official 159:7130f322cb7e 1854
mbed_official 159:7130f322cb7e 1855 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
mbed_official 159:7130f322cb7e 1856 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
mbed_official 159:7130f322cb7e 1857
mbed_official 159:7130f322cb7e 1858 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
mbed_official 159:7130f322cb7e 1859 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
mbed_official 159:7130f322cb7e 1860
mbed_official 159:7130f322cb7e 1861 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
mbed_official 159:7130f322cb7e 1862 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
mbed_official 159:7130f322cb7e 1863
mbed_official 159:7130f322cb7e 1864 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
mbed_official 159:7130f322cb7e 1865 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
mbed_official 159:7130f322cb7e 1866
mbed_official 159:7130f322cb7e 1867 /* Debug Core Register Selector Register Definitions */
mbed_official 159:7130f322cb7e 1868 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
mbed_official 159:7130f322cb7e 1869 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
mbed_official 159:7130f322cb7e 1870
mbed_official 159:7130f322cb7e 1871 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
mbed_official 159:7130f322cb7e 1872 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
mbed_official 159:7130f322cb7e 1873
mbed_official 159:7130f322cb7e 1874 /* Debug Exception and Monitor Control Register Definitions */
mbed_official 159:7130f322cb7e 1875 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
mbed_official 159:7130f322cb7e 1876 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
mbed_official 159:7130f322cb7e 1877
mbed_official 159:7130f322cb7e 1878 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
mbed_official 159:7130f322cb7e 1879 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
mbed_official 159:7130f322cb7e 1880
mbed_official 159:7130f322cb7e 1881 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
mbed_official 159:7130f322cb7e 1882 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
mbed_official 159:7130f322cb7e 1883
mbed_official 159:7130f322cb7e 1884 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
mbed_official 159:7130f322cb7e 1885 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
mbed_official 159:7130f322cb7e 1886
mbed_official 159:7130f322cb7e 1887 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
mbed_official 159:7130f322cb7e 1888 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
mbed_official 159:7130f322cb7e 1889
mbed_official 159:7130f322cb7e 1890 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
mbed_official 159:7130f322cb7e 1891 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
mbed_official 159:7130f322cb7e 1892
mbed_official 159:7130f322cb7e 1893 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
mbed_official 159:7130f322cb7e 1894 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
mbed_official 159:7130f322cb7e 1895
mbed_official 159:7130f322cb7e 1896 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
mbed_official 159:7130f322cb7e 1897 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
mbed_official 159:7130f322cb7e 1898
mbed_official 159:7130f322cb7e 1899 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
mbed_official 159:7130f322cb7e 1900 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
mbed_official 159:7130f322cb7e 1901
mbed_official 159:7130f322cb7e 1902 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
mbed_official 159:7130f322cb7e 1903 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
mbed_official 159:7130f322cb7e 1904
mbed_official 159:7130f322cb7e 1905 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
mbed_official 159:7130f322cb7e 1906 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
mbed_official 159:7130f322cb7e 1907
mbed_official 159:7130f322cb7e 1908 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
mbed_official 159:7130f322cb7e 1909 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
mbed_official 159:7130f322cb7e 1910
mbed_official 159:7130f322cb7e 1911 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
mbed_official 159:7130f322cb7e 1912 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
mbed_official 159:7130f322cb7e 1913
mbed_official 159:7130f322cb7e 1914 /* Debug Authentication Control Register Definitions */
mbed_official 159:7130f322cb7e 1915 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
mbed_official 159:7130f322cb7e 1916 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
mbed_official 159:7130f322cb7e 1917
mbed_official 159:7130f322cb7e 1918 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
mbed_official 159:7130f322cb7e 1919 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
mbed_official 159:7130f322cb7e 1920
mbed_official 159:7130f322cb7e 1921 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
mbed_official 159:7130f322cb7e 1922 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
mbed_official 159:7130f322cb7e 1923
mbed_official 159:7130f322cb7e 1924 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
mbed_official 159:7130f322cb7e 1925 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
mbed_official 159:7130f322cb7e 1926
mbed_official 159:7130f322cb7e 1927 /* Debug Security Control and Status Register Definitions */
mbed_official 159:7130f322cb7e 1928 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
mbed_official 159:7130f322cb7e 1929 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
mbed_official 159:7130f322cb7e 1930
mbed_official 159:7130f322cb7e 1931 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
mbed_official 159:7130f322cb7e 1932 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
mbed_official 159:7130f322cb7e 1933
mbed_official 159:7130f322cb7e 1934 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
mbed_official 159:7130f322cb7e 1935 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
mbed_official 159:7130f322cb7e 1936
mbed_official 159:7130f322cb7e 1937 /*@} end of group CMSIS_CoreDebug */
mbed_official 159:7130f322cb7e 1938
mbed_official 159:7130f322cb7e 1939
mbed_official 159:7130f322cb7e 1940 /**
mbed_official 159:7130f322cb7e 1941 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 1942 \defgroup CMSIS_core_bitfield Core register bit field macros
mbed_official 159:7130f322cb7e 1943 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
mbed_official 159:7130f322cb7e 1944 @{
mbed_official 159:7130f322cb7e 1945 */
mbed_official 159:7130f322cb7e 1946
mbed_official 159:7130f322cb7e 1947 /**
mbed_official 159:7130f322cb7e 1948 \brief Mask and shift a bit field value for use in a register bit range.
mbed_official 159:7130f322cb7e 1949 \param[in] field Name of the register bit field.
mbed_official 159:7130f322cb7e 1950 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
mbed_official 159:7130f322cb7e 1951 \return Masked and shifted value.
mbed_official 159:7130f322cb7e 1952 */
mbed_official 159:7130f322cb7e 1953 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
mbed_official 159:7130f322cb7e 1954
mbed_official 159:7130f322cb7e 1955 /**
mbed_official 159:7130f322cb7e 1956 \brief Mask and shift a register value to extract a bit filed value.
mbed_official 159:7130f322cb7e 1957 \param[in] field Name of the register bit field.
mbed_official 159:7130f322cb7e 1958 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
mbed_official 159:7130f322cb7e 1959 \return Masked and shifted bit field value.
mbed_official 159:7130f322cb7e 1960 */
mbed_official 159:7130f322cb7e 1961 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
mbed_official 159:7130f322cb7e 1962
mbed_official 159:7130f322cb7e 1963 /*@} end of group CMSIS_core_bitfield */
mbed_official 159:7130f322cb7e 1964
mbed_official 159:7130f322cb7e 1965
mbed_official 159:7130f322cb7e 1966 /**
mbed_official 159:7130f322cb7e 1967 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 1968 \defgroup CMSIS_core_base Core Definitions
mbed_official 159:7130f322cb7e 1969 \brief Definitions for base addresses, unions, and structures.
mbed_official 159:7130f322cb7e 1970 @{
mbed_official 159:7130f322cb7e 1971 */
mbed_official 159:7130f322cb7e 1972
mbed_official 159:7130f322cb7e 1973 /* Memory mapping of Core Hardware */
mbed_official 159:7130f322cb7e 1974 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
mbed_official 159:7130f322cb7e 1975 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
mbed_official 159:7130f322cb7e 1976 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
mbed_official 159:7130f322cb7e 1977 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
mbed_official 159:7130f322cb7e 1978 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
mbed_official 159:7130f322cb7e 1979 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
mbed_official 159:7130f322cb7e 1980 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
mbed_official 159:7130f322cb7e 1981 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
mbed_official 159:7130f322cb7e 1982
mbed_official 159:7130f322cb7e 1983 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
mbed_official 159:7130f322cb7e 1984 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
mbed_official 159:7130f322cb7e 1985 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
mbed_official 159:7130f322cb7e 1986 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
mbed_official 159:7130f322cb7e 1987 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
mbed_official 159:7130f322cb7e 1988 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
mbed_official 159:7130f322cb7e 1989 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
mbed_official 159:7130f322cb7e 1990 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
mbed_official 159:7130f322cb7e 1991
mbed_official 159:7130f322cb7e 1992 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
mbed_official 159:7130f322cb7e 1993 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
mbed_official 159:7130f322cb7e 1994 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
mbed_official 159:7130f322cb7e 1995 #endif
mbed_official 159:7130f322cb7e 1996
mbed_official 159:7130f322cb7e 1997 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
mbed_official 159:7130f322cb7e 1998 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
mbed_official 159:7130f322cb7e 1999 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
mbed_official 159:7130f322cb7e 2000 #endif
mbed_official 159:7130f322cb7e 2001
mbed_official 159:7130f322cb7e 2002 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
mbed_official 159:7130f322cb7e 2003 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
mbed_official 159:7130f322cb7e 2004
mbed_official 159:7130f322cb7e 2005 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
mbed_official 159:7130f322cb7e 2006 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
mbed_official 159:7130f322cb7e 2007 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
mbed_official 159:7130f322cb7e 2008 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
mbed_official 159:7130f322cb7e 2009 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
mbed_official 159:7130f322cb7e 2010 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
mbed_official 159:7130f322cb7e 2011
mbed_official 159:7130f322cb7e 2012 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
mbed_official 159:7130f322cb7e 2013 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
mbed_official 159:7130f322cb7e 2014 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
mbed_official 159:7130f322cb7e 2015 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
mbed_official 159:7130f322cb7e 2016 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
mbed_official 159:7130f322cb7e 2017
mbed_official 159:7130f322cb7e 2018 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
mbed_official 159:7130f322cb7e 2019 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
mbed_official 159:7130f322cb7e 2020 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
mbed_official 159:7130f322cb7e 2021 #endif
mbed_official 159:7130f322cb7e 2022
mbed_official 159:7130f322cb7e 2023 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
mbed_official 159:7130f322cb7e 2024 #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
mbed_official 159:7130f322cb7e 2025
mbed_official 159:7130f322cb7e 2026 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
mbed_official 159:7130f322cb7e 2027 /*@} */
mbed_official 159:7130f322cb7e 2028
mbed_official 159:7130f322cb7e 2029
mbed_official 159:7130f322cb7e 2030
mbed_official 159:7130f322cb7e 2031 /*******************************************************************************
mbed_official 159:7130f322cb7e 2032 * Hardware Abstraction Layer
mbed_official 159:7130f322cb7e 2033 Core Function Interface contains:
mbed_official 159:7130f322cb7e 2034 - Core NVIC Functions
mbed_official 159:7130f322cb7e 2035 - Core SysTick Functions
mbed_official 159:7130f322cb7e 2036 - Core Debug Functions
mbed_official 159:7130f322cb7e 2037 - Core Register Access Functions
mbed_official 159:7130f322cb7e 2038 ******************************************************************************/
mbed_official 159:7130f322cb7e 2039 /**
mbed_official 159:7130f322cb7e 2040 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mbed_official 159:7130f322cb7e 2041 */
mbed_official 159:7130f322cb7e 2042
mbed_official 159:7130f322cb7e 2043
mbed_official 159:7130f322cb7e 2044
mbed_official 159:7130f322cb7e 2045 /* ########################## NVIC functions #################################### */
mbed_official 159:7130f322cb7e 2046 /**
mbed_official 159:7130f322cb7e 2047 \ingroup CMSIS_Core_FunctionInterface
mbed_official 159:7130f322cb7e 2048 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
mbed_official 159:7130f322cb7e 2049 \brief Functions that manage interrupts and exceptions via the NVIC.
mbed_official 159:7130f322cb7e 2050 @{
mbed_official 159:7130f322cb7e 2051 */
mbed_official 159:7130f322cb7e 2052
mbed_official 159:7130f322cb7e 2053 #ifdef CMSIS_NVIC_VIRTUAL
mbed_official 159:7130f322cb7e 2054 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
mbed_official 159:7130f322cb7e 2055 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
mbed_official 159:7130f322cb7e 2056 #endif
mbed_official 159:7130f322cb7e 2057 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
mbed_official 159:7130f322cb7e 2058 #else
mbed_official 159:7130f322cb7e 2059 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
mbed_official 159:7130f322cb7e 2060 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
mbed_official 159:7130f322cb7e 2061 #define NVIC_EnableIRQ __NVIC_EnableIRQ
mbed_official 159:7130f322cb7e 2062 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
mbed_official 159:7130f322cb7e 2063 #define NVIC_DisableIRQ __NVIC_DisableIRQ
mbed_official 159:7130f322cb7e 2064 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
mbed_official 159:7130f322cb7e 2065 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
mbed_official 159:7130f322cb7e 2066 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
mbed_official 159:7130f322cb7e 2067 #define NVIC_GetActive __NVIC_GetActive
mbed_official 159:7130f322cb7e 2068 #define NVIC_SetPriority __NVIC_SetPriority
mbed_official 159:7130f322cb7e 2069 #define NVIC_GetPriority __NVIC_GetPriority
mbed_official 159:7130f322cb7e 2070 #define NVIC_SystemReset __NVIC_SystemReset
mbed_official 159:7130f322cb7e 2071 #endif /* CMSIS_NVIC_VIRTUAL */
mbed_official 159:7130f322cb7e 2072
mbed_official 159:7130f322cb7e 2073 #ifdef CMSIS_VECTAB_VIRTUAL
mbed_official 159:7130f322cb7e 2074 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
mbed_official 159:7130f322cb7e 2075 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
mbed_official 159:7130f322cb7e 2076 #endif
mbed_official 159:7130f322cb7e 2077 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
mbed_official 159:7130f322cb7e 2078 #else
mbed_official 159:7130f322cb7e 2079 #define NVIC_SetVector __NVIC_SetVector
mbed_official 159:7130f322cb7e 2080 #define NVIC_GetVector __NVIC_GetVector
mbed_official 159:7130f322cb7e 2081 #endif /* (CMSIS_VECTAB_VIRTUAL) */
mbed_official 159:7130f322cb7e 2082
mbed_official 159:7130f322cb7e 2083 #define NVIC_USER_IRQ_OFFSET 16
mbed_official 159:7130f322cb7e 2084
mbed_official 159:7130f322cb7e 2085
mbed_official 159:7130f322cb7e 2086
mbed_official 159:7130f322cb7e 2087 /**
mbed_official 159:7130f322cb7e 2088 \brief Set Priority Grouping
mbed_official 159:7130f322cb7e 2089 \details Sets the priority grouping field using the required unlock sequence.
mbed_official 159:7130f322cb7e 2090 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
mbed_official 159:7130f322cb7e 2091 Only values from 0..7 are used.
mbed_official 159:7130f322cb7e 2092 In case of a conflict between priority grouping and available
mbed_official 159:7130f322cb7e 2093 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
mbed_official 159:7130f322cb7e 2094 \param [in] PriorityGroup Priority grouping field.
mbed_official 159:7130f322cb7e 2095 */
mbed_official 159:7130f322cb7e 2096 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
mbed_official 159:7130f322cb7e 2097 {
mbed_official 159:7130f322cb7e 2098 uint32_t reg_value;
mbed_official 159:7130f322cb7e 2099 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mbed_official 159:7130f322cb7e 2100
mbed_official 159:7130f322cb7e 2101 reg_value = SCB->AIRCR; /* read old register configuration */
mbed_official 159:7130f322cb7e 2102 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
mbed_official 159:7130f322cb7e 2103 reg_value = (reg_value |
mbed_official 159:7130f322cb7e 2104 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
mbed_official 159:7130f322cb7e 2105 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
mbed_official 159:7130f322cb7e 2106 SCB->AIRCR = reg_value;
mbed_official 159:7130f322cb7e 2107 }
mbed_official 159:7130f322cb7e 2108
mbed_official 159:7130f322cb7e 2109
mbed_official 159:7130f322cb7e 2110 /**
mbed_official 159:7130f322cb7e 2111 \brief Get Priority Grouping
mbed_official 159:7130f322cb7e 2112 \details Reads the priority grouping field from the NVIC Interrupt Controller.
mbed_official 159:7130f322cb7e 2113 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
mbed_official 159:7130f322cb7e 2114 */
mbed_official 159:7130f322cb7e 2115 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
mbed_official 159:7130f322cb7e 2116 {
mbed_official 159:7130f322cb7e 2117 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
mbed_official 159:7130f322cb7e 2118 }
mbed_official 159:7130f322cb7e 2119
mbed_official 159:7130f322cb7e 2120
mbed_official 159:7130f322cb7e 2121 /**
mbed_official 159:7130f322cb7e 2122 \brief Enable Interrupt
mbed_official 159:7130f322cb7e 2123 \details Enables a device specific interrupt in the NVIC interrupt controller.
mbed_official 159:7130f322cb7e 2124 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 2125 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 2126 */
mbed_official 159:7130f322cb7e 2127 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 2128 {
mbed_official 159:7130f322cb7e 2129 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 2130 {
mbed_official 159:7130f322cb7e 2131 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 159:7130f322cb7e 2132 }
mbed_official 159:7130f322cb7e 2133 }
mbed_official 159:7130f322cb7e 2134
mbed_official 159:7130f322cb7e 2135
mbed_official 159:7130f322cb7e 2136 /**
mbed_official 159:7130f322cb7e 2137 \brief Get Interrupt Enable status
mbed_official 159:7130f322cb7e 2138 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
mbed_official 159:7130f322cb7e 2139 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 2140 \return 0 Interrupt is not enabled.
mbed_official 159:7130f322cb7e 2141 \return 1 Interrupt is enabled.
mbed_official 159:7130f322cb7e 2142 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 2143 */
mbed_official 159:7130f322cb7e 2144 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 2145 {
mbed_official 159:7130f322cb7e 2146 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 2147 {
mbed_official 159:7130f322cb7e 2148 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official 159:7130f322cb7e 2149 }
mbed_official 159:7130f322cb7e 2150 else
mbed_official 159:7130f322cb7e 2151 {
mbed_official 159:7130f322cb7e 2152 return(0U);
mbed_official 159:7130f322cb7e 2153 }
mbed_official 159:7130f322cb7e 2154 }
mbed_official 159:7130f322cb7e 2155
mbed_official 159:7130f322cb7e 2156
mbed_official 159:7130f322cb7e 2157 /**
mbed_official 159:7130f322cb7e 2158 \brief Disable Interrupt
mbed_official 159:7130f322cb7e 2159 \details Disables a device specific interrupt in the NVIC interrupt controller.
mbed_official 159:7130f322cb7e 2160 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 2161 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 2162 */
mbed_official 159:7130f322cb7e 2163 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 2164 {
mbed_official 159:7130f322cb7e 2165 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 2166 {
mbed_official 159:7130f322cb7e 2167 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 159:7130f322cb7e 2168 __DSB();
mbed_official 159:7130f322cb7e 2169 __ISB();
mbed_official 159:7130f322cb7e 2170 }
mbed_official 159:7130f322cb7e 2171 }
mbed_official 159:7130f322cb7e 2172
mbed_official 159:7130f322cb7e 2173
mbed_official 159:7130f322cb7e 2174 /**
mbed_official 159:7130f322cb7e 2175 \brief Get Pending Interrupt
mbed_official 159:7130f322cb7e 2176 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
mbed_official 159:7130f322cb7e 2177 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 2178 \return 0 Interrupt status is not pending.
mbed_official 159:7130f322cb7e 2179 \return 1 Interrupt status is pending.
mbed_official 159:7130f322cb7e 2180 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 2181 */
mbed_official 159:7130f322cb7e 2182 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 2183 {
mbed_official 159:7130f322cb7e 2184 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 2185 {
mbed_official 159:7130f322cb7e 2186 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official 159:7130f322cb7e 2187 }
mbed_official 159:7130f322cb7e 2188 else
mbed_official 159:7130f322cb7e 2189 {
mbed_official 159:7130f322cb7e 2190 return(0U);
mbed_official 159:7130f322cb7e 2191 }
mbed_official 159:7130f322cb7e 2192 }
mbed_official 159:7130f322cb7e 2193
mbed_official 159:7130f322cb7e 2194
mbed_official 159:7130f322cb7e 2195 /**
mbed_official 159:7130f322cb7e 2196 \brief Set Pending Interrupt
mbed_official 159:7130f322cb7e 2197 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
mbed_official 159:7130f322cb7e 2198 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 2199 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 2200 */
mbed_official 159:7130f322cb7e 2201 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 2202 {
mbed_official 159:7130f322cb7e 2203 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 2204 {
mbed_official 159:7130f322cb7e 2205 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 159:7130f322cb7e 2206 }
mbed_official 159:7130f322cb7e 2207 }
mbed_official 159:7130f322cb7e 2208
mbed_official 159:7130f322cb7e 2209
mbed_official 159:7130f322cb7e 2210 /**
mbed_official 159:7130f322cb7e 2211 \brief Clear Pending Interrupt
mbed_official 159:7130f322cb7e 2212 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
mbed_official 159:7130f322cb7e 2213 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 2214 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 2215 */
mbed_official 159:7130f322cb7e 2216 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 2217 {
mbed_official 159:7130f322cb7e 2218 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 2219 {
mbed_official 159:7130f322cb7e 2220 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 159:7130f322cb7e 2221 }
mbed_official 159:7130f322cb7e 2222 }
mbed_official 159:7130f322cb7e 2223
mbed_official 159:7130f322cb7e 2224
mbed_official 159:7130f322cb7e 2225 /**
mbed_official 159:7130f322cb7e 2226 \brief Get Active Interrupt
mbed_official 159:7130f322cb7e 2227 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
mbed_official 159:7130f322cb7e 2228 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 2229 \return 0 Interrupt status is not active.
mbed_official 159:7130f322cb7e 2230 \return 1 Interrupt status is active.
mbed_official 159:7130f322cb7e 2231 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 2232 */
mbed_official 159:7130f322cb7e 2233 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 2234 {
mbed_official 159:7130f322cb7e 2235 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 2236 {
mbed_official 159:7130f322cb7e 2237 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official 159:7130f322cb7e 2238 }
mbed_official 159:7130f322cb7e 2239 else
mbed_official 159:7130f322cb7e 2240 {
mbed_official 159:7130f322cb7e 2241 return(0U);
mbed_official 159:7130f322cb7e 2242 }
mbed_official 159:7130f322cb7e 2243 }
mbed_official 159:7130f322cb7e 2244
mbed_official 159:7130f322cb7e 2245
mbed_official 159:7130f322cb7e 2246 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
mbed_official 159:7130f322cb7e 2247 /**
mbed_official 159:7130f322cb7e 2248 \brief Get Interrupt Target State
mbed_official 159:7130f322cb7e 2249 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
mbed_official 159:7130f322cb7e 2250 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 2251 \return 0 if interrupt is assigned to Secure
mbed_official 159:7130f322cb7e 2252 \return 1 if interrupt is assigned to Non Secure
mbed_official 159:7130f322cb7e 2253 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 2254 */
mbed_official 159:7130f322cb7e 2255 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 2256 {
mbed_official 159:7130f322cb7e 2257 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 2258 {
mbed_official 159:7130f322cb7e 2259 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official 159:7130f322cb7e 2260 }
mbed_official 159:7130f322cb7e 2261 else
mbed_official 159:7130f322cb7e 2262 {
mbed_official 159:7130f322cb7e 2263 return(0U);
mbed_official 159:7130f322cb7e 2264 }
mbed_official 159:7130f322cb7e 2265 }
mbed_official 159:7130f322cb7e 2266
mbed_official 159:7130f322cb7e 2267
mbed_official 159:7130f322cb7e 2268 /**
mbed_official 159:7130f322cb7e 2269 \brief Set Interrupt Target State
mbed_official 159:7130f322cb7e 2270 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
mbed_official 159:7130f322cb7e 2271 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 2272 \return 0 if interrupt is assigned to Secure
mbed_official 159:7130f322cb7e 2273 1 if interrupt is assigned to Non Secure
mbed_official 159:7130f322cb7e 2274 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 2275 */
mbed_official 159:7130f322cb7e 2276 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 2277 {
mbed_official 159:7130f322cb7e 2278 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 2279 {
mbed_official 159:7130f322cb7e 2280 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
mbed_official 159:7130f322cb7e 2281 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official 159:7130f322cb7e 2282 }
mbed_official 159:7130f322cb7e 2283 else
mbed_official 159:7130f322cb7e 2284 {
mbed_official 159:7130f322cb7e 2285 return(0U);
mbed_official 159:7130f322cb7e 2286 }
mbed_official 159:7130f322cb7e 2287 }
mbed_official 159:7130f322cb7e 2288
mbed_official 159:7130f322cb7e 2289
mbed_official 159:7130f322cb7e 2290 /**
mbed_official 159:7130f322cb7e 2291 \brief Clear Interrupt Target State
mbed_official 159:7130f322cb7e 2292 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
mbed_official 159:7130f322cb7e 2293 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 2294 \return 0 if interrupt is assigned to Secure
mbed_official 159:7130f322cb7e 2295 1 if interrupt is assigned to Non Secure
mbed_official 159:7130f322cb7e 2296 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 2297 */
mbed_official 159:7130f322cb7e 2298 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 2299 {
mbed_official 159:7130f322cb7e 2300 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 2301 {
mbed_official 159:7130f322cb7e 2302 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
mbed_official 159:7130f322cb7e 2303 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official 159:7130f322cb7e 2304 }
mbed_official 159:7130f322cb7e 2305 else
mbed_official 159:7130f322cb7e 2306 {
mbed_official 159:7130f322cb7e 2307 return(0U);
mbed_official 159:7130f322cb7e 2308 }
mbed_official 159:7130f322cb7e 2309 }
mbed_official 159:7130f322cb7e 2310 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
mbed_official 159:7130f322cb7e 2311
mbed_official 159:7130f322cb7e 2312
mbed_official 159:7130f322cb7e 2313 /**
mbed_official 159:7130f322cb7e 2314 \brief Set Interrupt Priority
mbed_official 159:7130f322cb7e 2315 \details Sets the priority of a device specific interrupt or a processor exception.
mbed_official 159:7130f322cb7e 2316 The interrupt number can be positive to specify a device specific interrupt,
mbed_official 159:7130f322cb7e 2317 or negative to specify a processor exception.
mbed_official 159:7130f322cb7e 2318 \param [in] IRQn Interrupt number.
mbed_official 159:7130f322cb7e 2319 \param [in] priority Priority to set.
mbed_official 159:7130f322cb7e 2320 \note The priority cannot be set for every processor exception.
mbed_official 159:7130f322cb7e 2321 */
mbed_official 159:7130f322cb7e 2322 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mbed_official 159:7130f322cb7e 2323 {
mbed_official 159:7130f322cb7e 2324 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 2325 {
mbed_official 159:7130f322cb7e 2326 NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
mbed_official 159:7130f322cb7e 2327 }
mbed_official 159:7130f322cb7e 2328 else
mbed_official 159:7130f322cb7e 2329 {
mbed_official 159:7130f322cb7e 2330 SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
mbed_official 159:7130f322cb7e 2331 }
mbed_official 159:7130f322cb7e 2332 }
mbed_official 159:7130f322cb7e 2333
mbed_official 159:7130f322cb7e 2334
mbed_official 159:7130f322cb7e 2335 /**
mbed_official 159:7130f322cb7e 2336 \brief Get Interrupt Priority
mbed_official 159:7130f322cb7e 2337 \details Reads the priority of a device specific interrupt or a processor exception.
mbed_official 159:7130f322cb7e 2338 The interrupt number can be positive to specify a device specific interrupt,
mbed_official 159:7130f322cb7e 2339 or negative to specify a processor exception.
mbed_official 159:7130f322cb7e 2340 \param [in] IRQn Interrupt number.
mbed_official 159:7130f322cb7e 2341 \return Interrupt Priority.
mbed_official 159:7130f322cb7e 2342 Value is aligned automatically to the implemented priority bits of the microcontroller.
mbed_official 159:7130f322cb7e 2343 */
mbed_official 159:7130f322cb7e 2344 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 2345 {
mbed_official 159:7130f322cb7e 2346
mbed_official 159:7130f322cb7e 2347 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 2348 {
mbed_official 159:7130f322cb7e 2349 return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
mbed_official 159:7130f322cb7e 2350 }
mbed_official 159:7130f322cb7e 2351 else
mbed_official 159:7130f322cb7e 2352 {
mbed_official 159:7130f322cb7e 2353 return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
mbed_official 159:7130f322cb7e 2354 }
mbed_official 159:7130f322cb7e 2355 }
mbed_official 159:7130f322cb7e 2356
mbed_official 159:7130f322cb7e 2357
mbed_official 159:7130f322cb7e 2358 /**
mbed_official 159:7130f322cb7e 2359 \brief Encode Priority
mbed_official 159:7130f322cb7e 2360 \details Encodes the priority for an interrupt with the given priority group,
mbed_official 159:7130f322cb7e 2361 preemptive priority value, and subpriority value.
mbed_official 159:7130f322cb7e 2362 In case of a conflict between priority grouping and available
mbed_official 159:7130f322cb7e 2363 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
mbed_official 159:7130f322cb7e 2364 \param [in] PriorityGroup Used priority group.
mbed_official 159:7130f322cb7e 2365 \param [in] PreemptPriority Preemptive priority value (starting from 0).
mbed_official 159:7130f322cb7e 2366 \param [in] SubPriority Subpriority value (starting from 0).
mbed_official 159:7130f322cb7e 2367 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
mbed_official 159:7130f322cb7e 2368 */
mbed_official 159:7130f322cb7e 2369 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
mbed_official 159:7130f322cb7e 2370 {
mbed_official 159:7130f322cb7e 2371 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mbed_official 159:7130f322cb7e 2372 uint32_t PreemptPriorityBits;
mbed_official 159:7130f322cb7e 2373 uint32_t SubPriorityBits;
mbed_official 159:7130f322cb7e 2374
mbed_official 159:7130f322cb7e 2375 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
mbed_official 159:7130f322cb7e 2376 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
mbed_official 159:7130f322cb7e 2377
mbed_official 159:7130f322cb7e 2378 return (
mbed_official 159:7130f322cb7e 2379 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
mbed_official 159:7130f322cb7e 2380 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
mbed_official 159:7130f322cb7e 2381 );
mbed_official 159:7130f322cb7e 2382 }
mbed_official 159:7130f322cb7e 2383
mbed_official 159:7130f322cb7e 2384
mbed_official 159:7130f322cb7e 2385 /**
mbed_official 159:7130f322cb7e 2386 \brief Decode Priority
mbed_official 159:7130f322cb7e 2387 \details Decodes an interrupt priority value with a given priority group to
mbed_official 159:7130f322cb7e 2388 preemptive priority value and subpriority value.
mbed_official 159:7130f322cb7e 2389 In case of a conflict between priority grouping and available
mbed_official 159:7130f322cb7e 2390 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
mbed_official 159:7130f322cb7e 2391 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
mbed_official 159:7130f322cb7e 2392 \param [in] PriorityGroup Used priority group.
mbed_official 159:7130f322cb7e 2393 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
mbed_official 159:7130f322cb7e 2394 \param [out] pSubPriority Subpriority value (starting from 0).
mbed_official 159:7130f322cb7e 2395 */
mbed_official 159:7130f322cb7e 2396 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
mbed_official 159:7130f322cb7e 2397 {
mbed_official 159:7130f322cb7e 2398 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mbed_official 159:7130f322cb7e 2399 uint32_t PreemptPriorityBits;
mbed_official 159:7130f322cb7e 2400 uint32_t SubPriorityBits;
mbed_official 159:7130f322cb7e 2401
mbed_official 159:7130f322cb7e 2402 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
mbed_official 159:7130f322cb7e 2403 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
mbed_official 159:7130f322cb7e 2404
mbed_official 159:7130f322cb7e 2405 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
mbed_official 159:7130f322cb7e 2406 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
mbed_official 159:7130f322cb7e 2407 }
mbed_official 159:7130f322cb7e 2408
mbed_official 159:7130f322cb7e 2409
mbed_official 159:7130f322cb7e 2410 /**
mbed_official 159:7130f322cb7e 2411 \brief Set Interrupt Vector
mbed_official 159:7130f322cb7e 2412 \details Sets an interrupt vector in SRAM based interrupt vector table.
mbed_official 159:7130f322cb7e 2413 The interrupt number can be positive to specify a device specific interrupt,
mbed_official 159:7130f322cb7e 2414 or negative to specify a processor exception.
mbed_official 159:7130f322cb7e 2415 VTOR must been relocated to SRAM before.
mbed_official 159:7130f322cb7e 2416 \param [in] IRQn Interrupt number
mbed_official 159:7130f322cb7e 2417 \param [in] vector Address of interrupt handler function
mbed_official 159:7130f322cb7e 2418 */
mbed_official 159:7130f322cb7e 2419 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
mbed_official 159:7130f322cb7e 2420 {
mbed_official 159:7130f322cb7e 2421 uint32_t *vectors = (uint32_t *)SCB->VTOR;
mbed_official 159:7130f322cb7e 2422 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
mbed_official 159:7130f322cb7e 2423 }
mbed_official 159:7130f322cb7e 2424
mbed_official 159:7130f322cb7e 2425
mbed_official 159:7130f322cb7e 2426 /**
mbed_official 159:7130f322cb7e 2427 \brief Get Interrupt Vector
mbed_official 159:7130f322cb7e 2428 \details Reads an interrupt vector from interrupt vector table.
mbed_official 159:7130f322cb7e 2429 The interrupt number can be positive to specify a device specific interrupt,
mbed_official 159:7130f322cb7e 2430 or negative to specify a processor exception.
mbed_official 159:7130f322cb7e 2431 \param [in] IRQn Interrupt number.
mbed_official 159:7130f322cb7e 2432 \return Address of interrupt handler function
mbed_official 159:7130f322cb7e 2433 */
mbed_official 159:7130f322cb7e 2434 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 2435 {
mbed_official 159:7130f322cb7e 2436 uint32_t *vectors = (uint32_t *)SCB->VTOR;
mbed_official 159:7130f322cb7e 2437 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
mbed_official 159:7130f322cb7e 2438 }
mbed_official 159:7130f322cb7e 2439
mbed_official 159:7130f322cb7e 2440
mbed_official 159:7130f322cb7e 2441 /**
mbed_official 159:7130f322cb7e 2442 \brief System Reset
mbed_official 159:7130f322cb7e 2443 \details Initiates a system reset request to reset the MCU.
mbed_official 159:7130f322cb7e 2444 */
mbed_official 159:7130f322cb7e 2445 __STATIC_INLINE void __NVIC_SystemReset(void)
mbed_official 159:7130f322cb7e 2446 {
mbed_official 159:7130f322cb7e 2447 __DSB(); /* Ensure all outstanding memory accesses included
mbed_official 159:7130f322cb7e 2448 buffered write are completed before reset */
mbed_official 159:7130f322cb7e 2449 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
mbed_official 159:7130f322cb7e 2450 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
mbed_official 159:7130f322cb7e 2451 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
mbed_official 159:7130f322cb7e 2452 __DSB(); /* Ensure completion of memory access */
mbed_official 159:7130f322cb7e 2453
mbed_official 159:7130f322cb7e 2454 for(;;) /* wait until reset */
mbed_official 159:7130f322cb7e 2455 {
mbed_official 159:7130f322cb7e 2456 __NOP();
mbed_official 159:7130f322cb7e 2457 }
mbed_official 159:7130f322cb7e 2458 }
mbed_official 159:7130f322cb7e 2459
mbed_official 159:7130f322cb7e 2460 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
mbed_official 159:7130f322cb7e 2461 /**
mbed_official 159:7130f322cb7e 2462 \brief Set Priority Grouping (non-secure)
mbed_official 159:7130f322cb7e 2463 \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
mbed_official 159:7130f322cb7e 2464 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
mbed_official 159:7130f322cb7e 2465 Only values from 0..7 are used.
mbed_official 159:7130f322cb7e 2466 In case of a conflict between priority grouping and available
mbed_official 159:7130f322cb7e 2467 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
mbed_official 159:7130f322cb7e 2468 \param [in] PriorityGroup Priority grouping field.
mbed_official 159:7130f322cb7e 2469 */
mbed_official 159:7130f322cb7e 2470 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
mbed_official 159:7130f322cb7e 2471 {
mbed_official 159:7130f322cb7e 2472 uint32_t reg_value;
mbed_official 159:7130f322cb7e 2473 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mbed_official 159:7130f322cb7e 2474
mbed_official 159:7130f322cb7e 2475 reg_value = SCB_NS->AIRCR; /* read old register configuration */
mbed_official 159:7130f322cb7e 2476 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
mbed_official 159:7130f322cb7e 2477 reg_value = (reg_value |
mbed_official 159:7130f322cb7e 2478 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
mbed_official 159:7130f322cb7e 2479 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
mbed_official 159:7130f322cb7e 2480 SCB_NS->AIRCR = reg_value;
mbed_official 159:7130f322cb7e 2481 }
mbed_official 159:7130f322cb7e 2482
mbed_official 159:7130f322cb7e 2483
mbed_official 159:7130f322cb7e 2484 /**
mbed_official 159:7130f322cb7e 2485 \brief Get Priority Grouping (non-secure)
mbed_official 159:7130f322cb7e 2486 \details Reads the priority grouping field from the non-secure NVIC when in secure state.
mbed_official 159:7130f322cb7e 2487 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
mbed_official 159:7130f322cb7e 2488 */
mbed_official 159:7130f322cb7e 2489 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
mbed_official 159:7130f322cb7e 2490 {
mbed_official 159:7130f322cb7e 2491 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
mbed_official 159:7130f322cb7e 2492 }
mbed_official 159:7130f322cb7e 2493
mbed_official 159:7130f322cb7e 2494
mbed_official 159:7130f322cb7e 2495 /**
mbed_official 159:7130f322cb7e 2496 \brief Enable Interrupt (non-secure)
mbed_official 159:7130f322cb7e 2497 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
mbed_official 159:7130f322cb7e 2498 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 2499 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 2500 */
mbed_official 159:7130f322cb7e 2501 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 2502 {
mbed_official 159:7130f322cb7e 2503 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 2504 {
mbed_official 159:7130f322cb7e 2505 NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 159:7130f322cb7e 2506 }
mbed_official 159:7130f322cb7e 2507 }
mbed_official 159:7130f322cb7e 2508
mbed_official 159:7130f322cb7e 2509
mbed_official 159:7130f322cb7e 2510 /**
mbed_official 159:7130f322cb7e 2511 \brief Get Interrupt Enable status (non-secure)
mbed_official 159:7130f322cb7e 2512 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
mbed_official 159:7130f322cb7e 2513 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 2514 \return 0 Interrupt is not enabled.
mbed_official 159:7130f322cb7e 2515 \return 1 Interrupt is enabled.
mbed_official 159:7130f322cb7e 2516 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 2517 */
mbed_official 159:7130f322cb7e 2518 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 2519 {
mbed_official 159:7130f322cb7e 2520 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 2521 {
mbed_official 159:7130f322cb7e 2522 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official 159:7130f322cb7e 2523 }
mbed_official 159:7130f322cb7e 2524 else
mbed_official 159:7130f322cb7e 2525 {
mbed_official 159:7130f322cb7e 2526 return(0U);
mbed_official 159:7130f322cb7e 2527 }
mbed_official 159:7130f322cb7e 2528 }
mbed_official 159:7130f322cb7e 2529
mbed_official 159:7130f322cb7e 2530
mbed_official 159:7130f322cb7e 2531 /**
mbed_official 159:7130f322cb7e 2532 \brief Disable Interrupt (non-secure)
mbed_official 159:7130f322cb7e 2533 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
mbed_official 159:7130f322cb7e 2534 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 2535 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 2536 */
mbed_official 159:7130f322cb7e 2537 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 2538 {
mbed_official 159:7130f322cb7e 2539 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 2540 {
mbed_official 159:7130f322cb7e 2541 NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 159:7130f322cb7e 2542 }
mbed_official 159:7130f322cb7e 2543 }
mbed_official 159:7130f322cb7e 2544
mbed_official 159:7130f322cb7e 2545
mbed_official 159:7130f322cb7e 2546 /**
mbed_official 159:7130f322cb7e 2547 \brief Get Pending Interrupt (non-secure)
mbed_official 159:7130f322cb7e 2548 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
mbed_official 159:7130f322cb7e 2549 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 2550 \return 0 Interrupt status is not pending.
mbed_official 159:7130f322cb7e 2551 \return 1 Interrupt status is pending.
mbed_official 159:7130f322cb7e 2552 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 2553 */
mbed_official 159:7130f322cb7e 2554 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 2555 {
mbed_official 159:7130f322cb7e 2556 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 2557 {
mbed_official 159:7130f322cb7e 2558 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official 159:7130f322cb7e 2559 }
mbed_official 159:7130f322cb7e 2560 }
mbed_official 159:7130f322cb7e 2561
mbed_official 159:7130f322cb7e 2562
mbed_official 159:7130f322cb7e 2563 /**
mbed_official 159:7130f322cb7e 2564 \brief Set Pending Interrupt (non-secure)
mbed_official 159:7130f322cb7e 2565 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
mbed_official 159:7130f322cb7e 2566 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 2567 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 2568 */
mbed_official 159:7130f322cb7e 2569 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 2570 {
mbed_official 159:7130f322cb7e 2571 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 2572 {
mbed_official 159:7130f322cb7e 2573 NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 159:7130f322cb7e 2574 }
mbed_official 159:7130f322cb7e 2575 }
mbed_official 159:7130f322cb7e 2576
mbed_official 159:7130f322cb7e 2577
mbed_official 159:7130f322cb7e 2578 /**
mbed_official 159:7130f322cb7e 2579 \brief Clear Pending Interrupt (non-secure)
mbed_official 159:7130f322cb7e 2580 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
mbed_official 159:7130f322cb7e 2581 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 2582 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 2583 */
mbed_official 159:7130f322cb7e 2584 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 2585 {
mbed_official 159:7130f322cb7e 2586 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 2587 {
mbed_official 159:7130f322cb7e 2588 NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 159:7130f322cb7e 2589 }
mbed_official 159:7130f322cb7e 2590 }
mbed_official 159:7130f322cb7e 2591
mbed_official 159:7130f322cb7e 2592
mbed_official 159:7130f322cb7e 2593 /**
mbed_official 159:7130f322cb7e 2594 \brief Get Active Interrupt (non-secure)
mbed_official 159:7130f322cb7e 2595 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
mbed_official 159:7130f322cb7e 2596 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 2597 \return 0 Interrupt status is not active.
mbed_official 159:7130f322cb7e 2598 \return 1 Interrupt status is active.
mbed_official 159:7130f322cb7e 2599 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 2600 */
mbed_official 159:7130f322cb7e 2601 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 2602 {
mbed_official 159:7130f322cb7e 2603 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 2604 {
mbed_official 159:7130f322cb7e 2605 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official 159:7130f322cb7e 2606 }
mbed_official 159:7130f322cb7e 2607 else
mbed_official 159:7130f322cb7e 2608 {
mbed_official 159:7130f322cb7e 2609 return(0U);
mbed_official 159:7130f322cb7e 2610 }
mbed_official 159:7130f322cb7e 2611 }
mbed_official 159:7130f322cb7e 2612
mbed_official 159:7130f322cb7e 2613
mbed_official 159:7130f322cb7e 2614 /**
mbed_official 159:7130f322cb7e 2615 \brief Set Interrupt Priority (non-secure)
mbed_official 159:7130f322cb7e 2616 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
mbed_official 159:7130f322cb7e 2617 The interrupt number can be positive to specify a device specific interrupt,
mbed_official 159:7130f322cb7e 2618 or negative to specify a processor exception.
mbed_official 159:7130f322cb7e 2619 \param [in] IRQn Interrupt number.
mbed_official 159:7130f322cb7e 2620 \param [in] priority Priority to set.
mbed_official 159:7130f322cb7e 2621 \note The priority cannot be set for every non-secure processor exception.
mbed_official 159:7130f322cb7e 2622 */
mbed_official 159:7130f322cb7e 2623 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
mbed_official 159:7130f322cb7e 2624 {
mbed_official 159:7130f322cb7e 2625 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 2626 {
mbed_official 159:7130f322cb7e 2627 NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
mbed_official 159:7130f322cb7e 2628 }
mbed_official 159:7130f322cb7e 2629 else
mbed_official 159:7130f322cb7e 2630 {
mbed_official 159:7130f322cb7e 2631 SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
mbed_official 159:7130f322cb7e 2632 }
mbed_official 159:7130f322cb7e 2633 }
mbed_official 159:7130f322cb7e 2634
mbed_official 159:7130f322cb7e 2635
mbed_official 159:7130f322cb7e 2636 /**
mbed_official 159:7130f322cb7e 2637 \brief Get Interrupt Priority (non-secure)
mbed_official 159:7130f322cb7e 2638 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
mbed_official 159:7130f322cb7e 2639 The interrupt number can be positive to specify a device specific interrupt,
mbed_official 159:7130f322cb7e 2640 or negative to specify a processor exception.
mbed_official 159:7130f322cb7e 2641 \param [in] IRQn Interrupt number.
mbed_official 159:7130f322cb7e 2642 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
mbed_official 159:7130f322cb7e 2643 */
mbed_official 159:7130f322cb7e 2644 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 2645 {
mbed_official 159:7130f322cb7e 2646
mbed_official 159:7130f322cb7e 2647 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 2648 {
mbed_official 159:7130f322cb7e 2649 return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
mbed_official 159:7130f322cb7e 2650 }
mbed_official 159:7130f322cb7e 2651 else
mbed_official 159:7130f322cb7e 2652 {
mbed_official 159:7130f322cb7e 2653 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
mbed_official 159:7130f322cb7e 2654 }
mbed_official 159:7130f322cb7e 2655 }
mbed_official 159:7130f322cb7e 2656 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
mbed_official 159:7130f322cb7e 2657
mbed_official 159:7130f322cb7e 2658 /*@} end of CMSIS_Core_NVICFunctions */
mbed_official 159:7130f322cb7e 2659
mbed_official 159:7130f322cb7e 2660
mbed_official 159:7130f322cb7e 2661 /* ########################## FPU functions #################################### */
mbed_official 159:7130f322cb7e 2662 /**
mbed_official 159:7130f322cb7e 2663 \ingroup CMSIS_Core_FunctionInterface
mbed_official 159:7130f322cb7e 2664 \defgroup CMSIS_Core_FpuFunctions FPU Functions
mbed_official 159:7130f322cb7e 2665 \brief Function that provides FPU type.
mbed_official 159:7130f322cb7e 2666 @{
mbed_official 159:7130f322cb7e 2667 */
mbed_official 159:7130f322cb7e 2668
mbed_official 159:7130f322cb7e 2669 /**
mbed_official 159:7130f322cb7e 2670 \brief get FPU type
mbed_official 159:7130f322cb7e 2671 \details returns the FPU type
mbed_official 159:7130f322cb7e 2672 \returns
mbed_official 159:7130f322cb7e 2673 - \b 0: No FPU
mbed_official 159:7130f322cb7e 2674 - \b 1: Single precision FPU
mbed_official 159:7130f322cb7e 2675 - \b 2: Double + Single precision FPU
mbed_official 159:7130f322cb7e 2676 */
mbed_official 159:7130f322cb7e 2677 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
mbed_official 159:7130f322cb7e 2678 {
mbed_official 159:7130f322cb7e 2679 uint32_t mvfr0;
mbed_official 159:7130f322cb7e 2680
mbed_official 159:7130f322cb7e 2681 mvfr0 = FPU->MVFR0;
mbed_official 159:7130f322cb7e 2682 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
mbed_official 159:7130f322cb7e 2683 {
mbed_official 159:7130f322cb7e 2684 return 2U; /* Double + Single precision FPU */
mbed_official 159:7130f322cb7e 2685 }
mbed_official 159:7130f322cb7e 2686 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
mbed_official 159:7130f322cb7e 2687 {
mbed_official 159:7130f322cb7e 2688 return 1U; /* Single precision FPU */
mbed_official 159:7130f322cb7e 2689 }
mbed_official 159:7130f322cb7e 2690 else
mbed_official 159:7130f322cb7e 2691 {
mbed_official 159:7130f322cb7e 2692 return 0U; /* No FPU */
mbed_official 159:7130f322cb7e 2693 }
mbed_official 159:7130f322cb7e 2694 }
mbed_official 159:7130f322cb7e 2695
mbed_official 159:7130f322cb7e 2696
mbed_official 159:7130f322cb7e 2697 /*@} end of CMSIS_Core_FpuFunctions */
mbed_official 159:7130f322cb7e 2698
mbed_official 159:7130f322cb7e 2699
mbed_official 159:7130f322cb7e 2700
mbed_official 159:7130f322cb7e 2701 /* ########################## SAU functions #################################### */
mbed_official 159:7130f322cb7e 2702 /**
mbed_official 159:7130f322cb7e 2703 \ingroup CMSIS_Core_FunctionInterface
mbed_official 159:7130f322cb7e 2704 \defgroup CMSIS_Core_SAUFunctions SAU Functions
mbed_official 159:7130f322cb7e 2705 \brief Functions that configure the SAU.
mbed_official 159:7130f322cb7e 2706 @{
mbed_official 159:7130f322cb7e 2707 */
mbed_official 159:7130f322cb7e 2708
mbed_official 159:7130f322cb7e 2709 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
mbed_official 159:7130f322cb7e 2710
mbed_official 159:7130f322cb7e 2711 /**
mbed_official 159:7130f322cb7e 2712 \brief Enable SAU
mbed_official 159:7130f322cb7e 2713 \details Enables the Security Attribution Unit (SAU).
mbed_official 159:7130f322cb7e 2714 */
mbed_official 159:7130f322cb7e 2715 __STATIC_INLINE void TZ_SAU_Enable(void)
mbed_official 159:7130f322cb7e 2716 {
mbed_official 159:7130f322cb7e 2717 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
mbed_official 159:7130f322cb7e 2718 }
mbed_official 159:7130f322cb7e 2719
mbed_official 159:7130f322cb7e 2720
mbed_official 159:7130f322cb7e 2721
mbed_official 159:7130f322cb7e 2722 /**
mbed_official 159:7130f322cb7e 2723 \brief Disable SAU
mbed_official 159:7130f322cb7e 2724 \details Disables the Security Attribution Unit (SAU).
mbed_official 159:7130f322cb7e 2725 */
mbed_official 159:7130f322cb7e 2726 __STATIC_INLINE void TZ_SAU_Disable(void)
mbed_official 159:7130f322cb7e 2727 {
mbed_official 159:7130f322cb7e 2728 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
mbed_official 159:7130f322cb7e 2729 }
mbed_official 159:7130f322cb7e 2730
mbed_official 159:7130f322cb7e 2731 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
mbed_official 159:7130f322cb7e 2732
mbed_official 159:7130f322cb7e 2733 /*@} end of CMSIS_Core_SAUFunctions */
mbed_official 159:7130f322cb7e 2734
mbed_official 159:7130f322cb7e 2735
mbed_official 159:7130f322cb7e 2736
mbed_official 159:7130f322cb7e 2737
mbed_official 159:7130f322cb7e 2738 /* ################################## SysTick function ############################################ */
mbed_official 159:7130f322cb7e 2739 /**
mbed_official 159:7130f322cb7e 2740 \ingroup CMSIS_Core_FunctionInterface
mbed_official 159:7130f322cb7e 2741 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mbed_official 159:7130f322cb7e 2742 \brief Functions that configure the System.
mbed_official 159:7130f322cb7e 2743 @{
mbed_official 159:7130f322cb7e 2744 */
mbed_official 159:7130f322cb7e 2745
mbed_official 159:7130f322cb7e 2746 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
mbed_official 159:7130f322cb7e 2747
mbed_official 159:7130f322cb7e 2748 /**
mbed_official 159:7130f322cb7e 2749 \brief System Tick Configuration
mbed_official 159:7130f322cb7e 2750 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
mbed_official 159:7130f322cb7e 2751 Counter is in free running mode to generate periodic interrupts.
mbed_official 159:7130f322cb7e 2752 \param [in] ticks Number of ticks between two interrupts.
mbed_official 159:7130f322cb7e 2753 \return 0 Function succeeded.
mbed_official 159:7130f322cb7e 2754 \return 1 Function failed.
mbed_official 159:7130f322cb7e 2755 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mbed_official 159:7130f322cb7e 2756 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mbed_official 159:7130f322cb7e 2757 must contain a vendor-specific implementation of this function.
mbed_official 159:7130f322cb7e 2758 */
mbed_official 159:7130f322cb7e 2759 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mbed_official 159:7130f322cb7e 2760 {
mbed_official 159:7130f322cb7e 2761 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
mbed_official 159:7130f322cb7e 2762 {
mbed_official 159:7130f322cb7e 2763 return (1UL); /* Reload value impossible */
mbed_official 159:7130f322cb7e 2764 }
mbed_official 159:7130f322cb7e 2765
mbed_official 159:7130f322cb7e 2766 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
mbed_official 159:7130f322cb7e 2767 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
mbed_official 159:7130f322cb7e 2768 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
mbed_official 159:7130f322cb7e 2769 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
mbed_official 159:7130f322cb7e 2770 SysTick_CTRL_TICKINT_Msk |
mbed_official 159:7130f322cb7e 2771 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mbed_official 159:7130f322cb7e 2772 return (0UL); /* Function successful */
mbed_official 159:7130f322cb7e 2773 }
mbed_official 159:7130f322cb7e 2774
mbed_official 159:7130f322cb7e 2775 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
mbed_official 159:7130f322cb7e 2776 /**
mbed_official 159:7130f322cb7e 2777 \brief System Tick Configuration (non-secure)
mbed_official 159:7130f322cb7e 2778 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
mbed_official 159:7130f322cb7e 2779 Counter is in free running mode to generate periodic interrupts.
mbed_official 159:7130f322cb7e 2780 \param [in] ticks Number of ticks between two interrupts.
mbed_official 159:7130f322cb7e 2781 \return 0 Function succeeded.
mbed_official 159:7130f322cb7e 2782 \return 1 Function failed.
mbed_official 159:7130f322cb7e 2783 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mbed_official 159:7130f322cb7e 2784 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
mbed_official 159:7130f322cb7e 2785 must contain a vendor-specific implementation of this function.
mbed_official 159:7130f322cb7e 2786
mbed_official 159:7130f322cb7e 2787 */
mbed_official 159:7130f322cb7e 2788 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
mbed_official 159:7130f322cb7e 2789 {
mbed_official 159:7130f322cb7e 2790 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
mbed_official 159:7130f322cb7e 2791 {
mbed_official 159:7130f322cb7e 2792 return (1UL); /* Reload value impossible */
mbed_official 159:7130f322cb7e 2793 }
mbed_official 159:7130f322cb7e 2794
mbed_official 159:7130f322cb7e 2795 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
mbed_official 159:7130f322cb7e 2796 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
mbed_official 159:7130f322cb7e 2797 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
mbed_official 159:7130f322cb7e 2798 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
mbed_official 159:7130f322cb7e 2799 SysTick_CTRL_TICKINT_Msk |
mbed_official 159:7130f322cb7e 2800 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mbed_official 159:7130f322cb7e 2801 return (0UL); /* Function successful */
mbed_official 159:7130f322cb7e 2802 }
mbed_official 159:7130f322cb7e 2803 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
mbed_official 159:7130f322cb7e 2804
mbed_official 159:7130f322cb7e 2805 #endif
mbed_official 159:7130f322cb7e 2806
mbed_official 159:7130f322cb7e 2807 /*@} end of CMSIS_Core_SysTickFunctions */
mbed_official 159:7130f322cb7e 2808
mbed_official 159:7130f322cb7e 2809
mbed_official 159:7130f322cb7e 2810
mbed_official 159:7130f322cb7e 2811 /* ##################################### Debug In/Output function ########################################### */
mbed_official 159:7130f322cb7e 2812 /**
mbed_official 159:7130f322cb7e 2813 \ingroup CMSIS_Core_FunctionInterface
mbed_official 159:7130f322cb7e 2814 \defgroup CMSIS_core_DebugFunctions ITM Functions
mbed_official 159:7130f322cb7e 2815 \brief Functions that access the ITM debug interface.
mbed_official 159:7130f322cb7e 2816 @{
mbed_official 159:7130f322cb7e 2817 */
mbed_official 159:7130f322cb7e 2818
mbed_official 159:7130f322cb7e 2819 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
mbed_official 159:7130f322cb7e 2820 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
mbed_official 159:7130f322cb7e 2821
mbed_official 159:7130f322cb7e 2822
mbed_official 159:7130f322cb7e 2823 /**
mbed_official 159:7130f322cb7e 2824 \brief ITM Send Character
mbed_official 159:7130f322cb7e 2825 \details Transmits a character via the ITM channel 0, and
mbed_official 159:7130f322cb7e 2826 \li Just returns when no debugger is connected that has booked the output.
mbed_official 159:7130f322cb7e 2827 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
mbed_official 159:7130f322cb7e 2828 \param [in] ch Character to transmit.
mbed_official 159:7130f322cb7e 2829 \returns Character to transmit.
mbed_official 159:7130f322cb7e 2830 */
mbed_official 159:7130f322cb7e 2831 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
mbed_official 159:7130f322cb7e 2832 {
mbed_official 159:7130f322cb7e 2833 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
mbed_official 159:7130f322cb7e 2834 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
mbed_official 159:7130f322cb7e 2835 {
mbed_official 159:7130f322cb7e 2836 while (ITM->PORT[0U].u32 == 0UL)
mbed_official 159:7130f322cb7e 2837 {
mbed_official 159:7130f322cb7e 2838 __NOP();
mbed_official 159:7130f322cb7e 2839 }
mbed_official 159:7130f322cb7e 2840 ITM->PORT[0U].u8 = (uint8_t)ch;
mbed_official 159:7130f322cb7e 2841 }
mbed_official 159:7130f322cb7e 2842 return (ch);
mbed_official 159:7130f322cb7e 2843 }
mbed_official 159:7130f322cb7e 2844
mbed_official 159:7130f322cb7e 2845
mbed_official 159:7130f322cb7e 2846 /**
mbed_official 159:7130f322cb7e 2847 \brief ITM Receive Character
mbed_official 159:7130f322cb7e 2848 \details Inputs a character via the external variable \ref ITM_RxBuffer.
mbed_official 159:7130f322cb7e 2849 \return Received character.
mbed_official 159:7130f322cb7e 2850 \return -1 No character pending.
mbed_official 159:7130f322cb7e 2851 */
mbed_official 159:7130f322cb7e 2852 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
mbed_official 159:7130f322cb7e 2853 {
mbed_official 159:7130f322cb7e 2854 int32_t ch = -1; /* no character available */
mbed_official 159:7130f322cb7e 2855
mbed_official 159:7130f322cb7e 2856 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
mbed_official 159:7130f322cb7e 2857 {
mbed_official 159:7130f322cb7e 2858 ch = ITM_RxBuffer;
mbed_official 159:7130f322cb7e 2859 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
mbed_official 159:7130f322cb7e 2860 }
mbed_official 159:7130f322cb7e 2861
mbed_official 159:7130f322cb7e 2862 return (ch);
mbed_official 159:7130f322cb7e 2863 }
mbed_official 159:7130f322cb7e 2864
mbed_official 159:7130f322cb7e 2865
mbed_official 159:7130f322cb7e 2866 /**
mbed_official 159:7130f322cb7e 2867 \brief ITM Check Character
mbed_official 159:7130f322cb7e 2868 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
mbed_official 159:7130f322cb7e 2869 \return 0 No character available.
mbed_official 159:7130f322cb7e 2870 \return 1 Character available.
mbed_official 159:7130f322cb7e 2871 */
mbed_official 159:7130f322cb7e 2872 __STATIC_INLINE int32_t ITM_CheckChar (void)
mbed_official 159:7130f322cb7e 2873 {
mbed_official 159:7130f322cb7e 2874
mbed_official 159:7130f322cb7e 2875 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
mbed_official 159:7130f322cb7e 2876 {
mbed_official 159:7130f322cb7e 2877 return (0); /* no character available */
mbed_official 159:7130f322cb7e 2878 }
mbed_official 159:7130f322cb7e 2879 else
mbed_official 159:7130f322cb7e 2880 {
mbed_official 159:7130f322cb7e 2881 return (1); /* character available */
mbed_official 159:7130f322cb7e 2882 }
mbed_official 159:7130f322cb7e 2883 }
mbed_official 159:7130f322cb7e 2884
mbed_official 159:7130f322cb7e 2885 /*@} end of CMSIS_core_DebugFunctions */
mbed_official 159:7130f322cb7e 2886
mbed_official 159:7130f322cb7e 2887
mbed_official 159:7130f322cb7e 2888
mbed_official 159:7130f322cb7e 2889
mbed_official 159:7130f322cb7e 2890 #ifdef __cplusplus
mbed_official 159:7130f322cb7e 2891 }
mbed_official 159:7130f322cb7e 2892 #endif
mbed_official 159:7130f322cb7e 2893
mbed_official 159:7130f322cb7e 2894 #endif /* __CORE_CM33_H_DEPENDANT */
mbed_official 159:7130f322cb7e 2895
mbed_official 159:7130f322cb7e 2896 #endif /* __CMSIS_GENERIC */