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TARGET_SAKURAIO_EVB_01/core_cm23.h@159:7130f322cb7e, 2017-12-21 (annotated)

Committer:: mbed_official
Date:: Thu Dec 21 18:20:02 2017 +0000
Revision:: 159:7130f322cb7e

mbed library version 157

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	159:7130f322cb7e	1	/************************************************************************//
mbed_official	159:7130f322cb7e	2	* @file core_cm23.h
mbed_official	159:7130f322cb7e	3	* @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
mbed_official	159:7130f322cb7e	4	* @version V5.0.2
mbed_official	159:7130f322cb7e	5	* @date 13. February 2017
mbed_official	159:7130f322cb7e	6	******************************************************************************/
mbed_official	159:7130f322cb7e	7	/*
mbed_official	159:7130f322cb7e	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
mbed_official	159:7130f322cb7e	9	*
mbed_official	159:7130f322cb7e	10	* SPDX-License-Identifier: Apache-2.0
mbed_official	159:7130f322cb7e	11	*
mbed_official	159:7130f322cb7e	12	* Licensed under the Apache License, Version 2.0 (the License); you may
mbed_official	159:7130f322cb7e	13	* not use this file except in compliance with the License.
mbed_official	159:7130f322cb7e	14	* You may obtain a copy of the License at
mbed_official	159:7130f322cb7e	15	*
mbed_official	159:7130f322cb7e	16	* www.apache.org/licenses/LICENSE-2.0
mbed_official	159:7130f322cb7e	17	*
mbed_official	159:7130f322cb7e	18	* Unless required by applicable law or agreed to in writing, software
mbed_official	159:7130f322cb7e	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
mbed_official	159:7130f322cb7e	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official	159:7130f322cb7e	21	* See the License for the specific language governing permissions and
mbed_official	159:7130f322cb7e	22	* limitations under the License.
mbed_official	159:7130f322cb7e	23	*/
mbed_official	159:7130f322cb7e	24
mbed_official	159:7130f322cb7e	25	#if defined ( __ICCARM__ )
mbed_official	159:7130f322cb7e	26	#pragma system_include /* treat file as system include file for MISRA check */
mbed_official	159:7130f322cb7e	27	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
mbed_official	159:7130f322cb7e	28	#pragma clang system_header /* treat file as system include file */
mbed_official	159:7130f322cb7e	29	#endif
mbed_official	159:7130f322cb7e	30
mbed_official	159:7130f322cb7e	31	#ifndef __CORE_CM23_H_GENERIC
mbed_official	159:7130f322cb7e	32	#define __CORE_CM23_H_GENERIC
mbed_official	159:7130f322cb7e	33
mbed_official	159:7130f322cb7e	34	#include <stdint.h>
mbed_official	159:7130f322cb7e	35
mbed_official	159:7130f322cb7e	36	#ifdef __cplusplus
mbed_official	159:7130f322cb7e	37	extern "C" {
mbed_official	159:7130f322cb7e	38	#endif
mbed_official	159:7130f322cb7e	39
mbed_official	159:7130f322cb7e	40	/**
mbed_official	159:7130f322cb7e	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mbed_official	159:7130f322cb7e	42	CMSIS violates the following MISRA-C:2004 rules:
mbed_official	159:7130f322cb7e	43
mbed_official	159:7130f322cb7e	44	\li Required Rule 8.5, object/function definition in header file.<br>
mbed_official	159:7130f322cb7e	45	Function definitions in header files are used to allow 'inlining'.
mbed_official	159:7130f322cb7e	46
mbed_official	159:7130f322cb7e	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mbed_official	159:7130f322cb7e	48	Unions are used for effective representation of core registers.
mbed_official	159:7130f322cb7e	49
mbed_official	159:7130f322cb7e	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
mbed_official	159:7130f322cb7e	51	Function-like macros are used to allow more efficient code.
mbed_official	159:7130f322cb7e	52	*/
mbed_official	159:7130f322cb7e	53
mbed_official	159:7130f322cb7e	54
mbed_official	159:7130f322cb7e	55	/*******************************************************************************
mbed_official	159:7130f322cb7e	56	* CMSIS definitions
mbed_official	159:7130f322cb7e	57	******************************************************************************/
mbed_official	159:7130f322cb7e	58	/**
mbed_official	159:7130f322cb7e	59	\ingroup Cortex_M23
mbed_official	159:7130f322cb7e	60	@{
mbed_official	159:7130f322cb7e	61	*/
mbed_official	159:7130f322cb7e	62
mbed_official	159:7130f322cb7e	63	/* CMSIS cmGrebe definitions */
mbed_official	159:7130f322cb7e	64	#define __CM23_CMSIS_VERSION_MAIN ( 5U) /!< [31:16] CMSIS HAL main version /
mbed_official	159:7130f322cb7e	65	#define __CM23_CMSIS_VERSION_SUB ( 0U) /!< [15:0] CMSIS HAL sub version /
mbed_official	159:7130f322cb7e	66	#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) \| \
mbed_official	159:7130f322cb7e	67	__CM23_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
mbed_official	159:7130f322cb7e	68
mbed_official	159:7130f322cb7e	69	#define __CORTEX_M (23U) /!< Cortex-M Core /
mbed_official	159:7130f322cb7e	70
mbed_official	159:7130f322cb7e	71	/** __FPU_USED indicates whether an FPU is used or not.
mbed_official	159:7130f322cb7e	72	This core does not support an FPU at all
mbed_official	159:7130f322cb7e	73	*/
mbed_official	159:7130f322cb7e	74	#define __FPU_USED 0U
mbed_official	159:7130f322cb7e	75
mbed_official	159:7130f322cb7e	76	#if defined ( __CC_ARM )
mbed_official	159:7130f322cb7e	77	#if defined __TARGET_FPU_VFP
mbed_official	159:7130f322cb7e	78	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official	159:7130f322cb7e	79	#endif
mbed_official	159:7130f322cb7e	80
mbed_official	159:7130f322cb7e	81	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
mbed_official	159:7130f322cb7e	82	#if defined __ARM_PCS_VFP
mbed_official	159:7130f322cb7e	83	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official	159:7130f322cb7e	84	#endif
mbed_official	159:7130f322cb7e	85
mbed_official	159:7130f322cb7e	86	#elif defined ( __GNUC__ )
mbed_official	159:7130f322cb7e	87	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
mbed_official	159:7130f322cb7e	88	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official	159:7130f322cb7e	89	#endif
mbed_official	159:7130f322cb7e	90
mbed_official	159:7130f322cb7e	91	#elif defined ( __ICCARM__ )
mbed_official	159:7130f322cb7e	92	#if defined __ARMVFP__
mbed_official	159:7130f322cb7e	93	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official	159:7130f322cb7e	94	#endif
mbed_official	159:7130f322cb7e	95
mbed_official	159:7130f322cb7e	96	#elif defined ( __TI_ARM__ )
mbed_official	159:7130f322cb7e	97	#if defined __TI_VFP_SUPPORT__
mbed_official	159:7130f322cb7e	98	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official	159:7130f322cb7e	99	#endif
mbed_official	159:7130f322cb7e	100
mbed_official	159:7130f322cb7e	101	#elif defined ( __TASKING__ )
mbed_official	159:7130f322cb7e	102	#if defined __FPU_VFP__
mbed_official	159:7130f322cb7e	103	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official	159:7130f322cb7e	104	#endif
mbed_official	159:7130f322cb7e	105
mbed_official	159:7130f322cb7e	106	#elif defined ( __CSMC__ )
mbed_official	159:7130f322cb7e	107	#if ( __CSMC__ & 0x400U)
mbed_official	159:7130f322cb7e	108	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official	159:7130f322cb7e	109	#endif
mbed_official	159:7130f322cb7e	110
mbed_official	159:7130f322cb7e	111	#endif
mbed_official	159:7130f322cb7e	112
mbed_official	159:7130f322cb7e	113	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
mbed_official	159:7130f322cb7e	114
mbed_official	159:7130f322cb7e	115
mbed_official	159:7130f322cb7e	116	#ifdef __cplusplus
mbed_official	159:7130f322cb7e	117	}
mbed_official	159:7130f322cb7e	118	#endif
mbed_official	159:7130f322cb7e	119
mbed_official	159:7130f322cb7e	120	#endif /* __CORE_CM23_H_GENERIC */
mbed_official	159:7130f322cb7e	121
mbed_official	159:7130f322cb7e	122	#ifndef __CMSIS_GENERIC
mbed_official	159:7130f322cb7e	123
mbed_official	159:7130f322cb7e	124	#ifndef __CORE_CM23_H_DEPENDANT
mbed_official	159:7130f322cb7e	125	#define __CORE_CM23_H_DEPENDANT
mbed_official	159:7130f322cb7e	126
mbed_official	159:7130f322cb7e	127	#ifdef __cplusplus
mbed_official	159:7130f322cb7e	128	extern "C" {
mbed_official	159:7130f322cb7e	129	#endif
mbed_official	159:7130f322cb7e	130
mbed_official	159:7130f322cb7e	131	/* check device defines and use defaults */
mbed_official	159:7130f322cb7e	132	#if defined __CHECK_DEVICE_DEFINES
mbed_official	159:7130f322cb7e	133	#ifndef __CM23_REV
mbed_official	159:7130f322cb7e	134	#define __CM23_REV 0x0000U
mbed_official	159:7130f322cb7e	135	#warning "__CM23_REV not defined in device header file; using default!"
mbed_official	159:7130f322cb7e	136	#endif
mbed_official	159:7130f322cb7e	137
mbed_official	159:7130f322cb7e	138	#ifndef __FPU_PRESENT
mbed_official	159:7130f322cb7e	139	#define __FPU_PRESENT 0U
mbed_official	159:7130f322cb7e	140	#warning "__FPU_PRESENT not defined in device header file; using default!"
mbed_official	159:7130f322cb7e	141	#endif
mbed_official	159:7130f322cb7e	142
mbed_official	159:7130f322cb7e	143	#ifndef __MPU_PRESENT
mbed_official	159:7130f322cb7e	144	#define __MPU_PRESENT 0U
mbed_official	159:7130f322cb7e	145	#warning "__MPU_PRESENT not defined in device header file; using default!"
mbed_official	159:7130f322cb7e	146	#endif
mbed_official	159:7130f322cb7e	147
mbed_official	159:7130f322cb7e	148	#ifndef __SAUREGION_PRESENT
mbed_official	159:7130f322cb7e	149	#define __SAUREGION_PRESENT 0U
mbed_official	159:7130f322cb7e	150	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
mbed_official	159:7130f322cb7e	151	#endif
mbed_official	159:7130f322cb7e	152
mbed_official	159:7130f322cb7e	153	#ifndef __VTOR_PRESENT
mbed_official	159:7130f322cb7e	154	#define __VTOR_PRESENT 0U
mbed_official	159:7130f322cb7e	155	#warning "__VTOR_PRESENT not defined in device header file; using default!"
mbed_official	159:7130f322cb7e	156	#endif
mbed_official	159:7130f322cb7e	157
mbed_official	159:7130f322cb7e	158	#ifndef __NVIC_PRIO_BITS
mbed_official	159:7130f322cb7e	159	#define __NVIC_PRIO_BITS 2U
mbed_official	159:7130f322cb7e	160	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mbed_official	159:7130f322cb7e	161	#endif
mbed_official	159:7130f322cb7e	162
mbed_official	159:7130f322cb7e	163	#ifndef __Vendor_SysTickConfig
mbed_official	159:7130f322cb7e	164	#define __Vendor_SysTickConfig 0U
mbed_official	159:7130f322cb7e	165	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mbed_official	159:7130f322cb7e	166	#endif
mbed_official	159:7130f322cb7e	167
mbed_official	159:7130f322cb7e	168	#ifndef __ETM_PRESENT
mbed_official	159:7130f322cb7e	169	#define __ETM_PRESENT 0U
mbed_official	159:7130f322cb7e	170	#warning "__ETM_PRESENT not defined in device header file; using default!"
mbed_official	159:7130f322cb7e	171	#endif
mbed_official	159:7130f322cb7e	172
mbed_official	159:7130f322cb7e	173	#ifndef __MTB_PRESENT
mbed_official	159:7130f322cb7e	174	#define __MTB_PRESENT 0U
mbed_official	159:7130f322cb7e	175	#warning "__MTB_PRESENT not defined in device header file; using default!"
mbed_official	159:7130f322cb7e	176	#endif
mbed_official	159:7130f322cb7e	177
mbed_official	159:7130f322cb7e	178	#endif
mbed_official	159:7130f322cb7e	179
mbed_official	159:7130f322cb7e	180	/* IO definitions (access restrictions to peripheral registers) */
mbed_official	159:7130f322cb7e	181	/**
mbed_official	159:7130f322cb7e	182	\defgroup CMSIS_glob_defs CMSIS Global Defines
mbed_official	159:7130f322cb7e	183
mbed_official	159:7130f322cb7e	184	<strong>IO Type Qualifiers</strong> are used
mbed_official	159:7130f322cb7e	185	\li to specify the access to peripheral variables.
mbed_official	159:7130f322cb7e	186	\li for automatic generation of peripheral register debug information.
mbed_official	159:7130f322cb7e	187	*/
mbed_official	159:7130f322cb7e	188	#ifdef __cplusplus
mbed_official	159:7130f322cb7e	189	#define __I volatile /!< Defines 'read only' permissions /
mbed_official	159:7130f322cb7e	190	#else
mbed_official	159:7130f322cb7e	191	#define __I volatile const /!< Defines 'read only' permissions /
mbed_official	159:7130f322cb7e	192	#endif
mbed_official	159:7130f322cb7e	193	#define __O volatile /!< Defines 'write only' permissions /
mbed_official	159:7130f322cb7e	194	#define __IO volatile /!< Defines 'read / write' permissions /
mbed_official	159:7130f322cb7e	195
mbed_official	159:7130f322cb7e	196	/* following defines should be used for structure members */
mbed_official	159:7130f322cb7e	197	#define __IM volatile const /! Defines 'read only' structure member permissions /
mbed_official	159:7130f322cb7e	198	#define __OM volatile /! Defines 'write only' structure member permissions /
mbed_official	159:7130f322cb7e	199	#define __IOM volatile /! Defines 'read / write' structure member permissions /
mbed_official	159:7130f322cb7e	200
mbed_official	159:7130f322cb7e	201	/@} end of group Cortex_M23 /
mbed_official	159:7130f322cb7e	202
mbed_official	159:7130f322cb7e	203
mbed_official	159:7130f322cb7e	204
mbed_official	159:7130f322cb7e	205	/*******************************************************************************
mbed_official	159:7130f322cb7e	206	* Register Abstraction
mbed_official	159:7130f322cb7e	207	Core Register contain:
mbed_official	159:7130f322cb7e	208	- Core Register
mbed_official	159:7130f322cb7e	209	- Core NVIC Register
mbed_official	159:7130f322cb7e	210	- Core SCB Register
mbed_official	159:7130f322cb7e	211	- Core SysTick Register
mbed_official	159:7130f322cb7e	212	- Core Debug Register
mbed_official	159:7130f322cb7e	213	- Core MPU Register
mbed_official	159:7130f322cb7e	214	- Core SAU Register
mbed_official	159:7130f322cb7e	215	******************************************************************************/
mbed_official	159:7130f322cb7e	216	/**
mbed_official	159:7130f322cb7e	217	\defgroup CMSIS_core_register Defines and Type Definitions
mbed_official	159:7130f322cb7e	218	\brief Type definitions and defines for Cortex-M processor based devices.
mbed_official	159:7130f322cb7e	219	*/
mbed_official	159:7130f322cb7e	220
mbed_official	159:7130f322cb7e	221	/**
mbed_official	159:7130f322cb7e	222	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	223	\defgroup CMSIS_CORE Status and Control Registers
mbed_official	159:7130f322cb7e	224	\brief Core Register type definitions.
mbed_official	159:7130f322cb7e	225	@{
mbed_official	159:7130f322cb7e	226	*/
mbed_official	159:7130f322cb7e	227
mbed_official	159:7130f322cb7e	228	/**
mbed_official	159:7130f322cb7e	229	\brief Union type to access the Application Program Status Register (APSR).
mbed_official	159:7130f322cb7e	230	*/
mbed_official	159:7130f322cb7e	231	typedef union
mbed_official	159:7130f322cb7e	232	{
mbed_official	159:7130f322cb7e	233	struct
mbed_official	159:7130f322cb7e	234	{
mbed_official	159:7130f322cb7e	235	uint32_t _reserved0:28; /!< bit: 0..27 Reserved /
mbed_official	159:7130f322cb7e	236	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
mbed_official	159:7130f322cb7e	237	uint32_t C:1; /!< bit: 29 Carry condition code flag /
mbed_official	159:7130f322cb7e	238	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
mbed_official	159:7130f322cb7e	239	uint32_t N:1; /!< bit: 31 Negative condition code flag /
mbed_official	159:7130f322cb7e	240	} b; /!< Structure used for bit access /
mbed_official	159:7130f322cb7e	241	uint32_t w; /!< Type used for word access /
mbed_official	159:7130f322cb7e	242	} APSR_Type;
mbed_official	159:7130f322cb7e	243
mbed_official	159:7130f322cb7e	244	/* APSR Register Definitions */
mbed_official	159:7130f322cb7e	245	#define APSR_N_Pos 31U /!< APSR: N Position /
mbed_official	159:7130f322cb7e	246	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
mbed_official	159:7130f322cb7e	247
mbed_official	159:7130f322cb7e	248	#define APSR_Z_Pos 30U /!< APSR: Z Position /
mbed_official	159:7130f322cb7e	249	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
mbed_official	159:7130f322cb7e	250
mbed_official	159:7130f322cb7e	251	#define APSR_C_Pos 29U /!< APSR: C Position /
mbed_official	159:7130f322cb7e	252	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
mbed_official	159:7130f322cb7e	253
mbed_official	159:7130f322cb7e	254	#define APSR_V_Pos 28U /!< APSR: V Position /
mbed_official	159:7130f322cb7e	255	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
mbed_official	159:7130f322cb7e	256
mbed_official	159:7130f322cb7e	257
mbed_official	159:7130f322cb7e	258	/**
mbed_official	159:7130f322cb7e	259	\brief Union type to access the Interrupt Program Status Register (IPSR).
mbed_official	159:7130f322cb7e	260	*/
mbed_official	159:7130f322cb7e	261	typedef union
mbed_official	159:7130f322cb7e	262	{
mbed_official	159:7130f322cb7e	263	struct
mbed_official	159:7130f322cb7e	264	{
mbed_official	159:7130f322cb7e	265	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
mbed_official	159:7130f322cb7e	266	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
mbed_official	159:7130f322cb7e	267	} b; /!< Structure used for bit access /
mbed_official	159:7130f322cb7e	268	uint32_t w; /!< Type used for word access /
mbed_official	159:7130f322cb7e	269	} IPSR_Type;
mbed_official	159:7130f322cb7e	270
mbed_official	159:7130f322cb7e	271	/* IPSR Register Definitions */
mbed_official	159:7130f322cb7e	272	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
mbed_official	159:7130f322cb7e	273	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
mbed_official	159:7130f322cb7e	274
mbed_official	159:7130f322cb7e	275
mbed_official	159:7130f322cb7e	276	/**
mbed_official	159:7130f322cb7e	277	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mbed_official	159:7130f322cb7e	278	*/
mbed_official	159:7130f322cb7e	279	typedef union
mbed_official	159:7130f322cb7e	280	{
mbed_official	159:7130f322cb7e	281	struct
mbed_official	159:7130f322cb7e	282	{
mbed_official	159:7130f322cb7e	283	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
mbed_official	159:7130f322cb7e	284	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
mbed_official	159:7130f322cb7e	285	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
mbed_official	159:7130f322cb7e	286	uint32_t _reserved1:3; /!< bit: 25..27 Reserved /
mbed_official	159:7130f322cb7e	287	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
mbed_official	159:7130f322cb7e	288	uint32_t C:1; /!< bit: 29 Carry condition code flag /
mbed_official	159:7130f322cb7e	289	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
mbed_official	159:7130f322cb7e	290	uint32_t N:1; /!< bit: 31 Negative condition code flag /
mbed_official	159:7130f322cb7e	291	} b; /!< Structure used for bit access /
mbed_official	159:7130f322cb7e	292	uint32_t w; /!< Type used for word access /
mbed_official	159:7130f322cb7e	293	} xPSR_Type;
mbed_official	159:7130f322cb7e	294
mbed_official	159:7130f322cb7e	295	/* xPSR Register Definitions */
mbed_official	159:7130f322cb7e	296	#define xPSR_N_Pos 31U /!< xPSR: N Position /
mbed_official	159:7130f322cb7e	297	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
mbed_official	159:7130f322cb7e	298
mbed_official	159:7130f322cb7e	299	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
mbed_official	159:7130f322cb7e	300	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
mbed_official	159:7130f322cb7e	301
mbed_official	159:7130f322cb7e	302	#define xPSR_C_Pos 29U /!< xPSR: C Position /
mbed_official	159:7130f322cb7e	303	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
mbed_official	159:7130f322cb7e	304
mbed_official	159:7130f322cb7e	305	#define xPSR_V_Pos 28U /!< xPSR: V Position /
mbed_official	159:7130f322cb7e	306	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
mbed_official	159:7130f322cb7e	307
mbed_official	159:7130f322cb7e	308	#define xPSR_T_Pos 24U /!< xPSR: T Position /
mbed_official	159:7130f322cb7e	309	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
mbed_official	159:7130f322cb7e	310
mbed_official	159:7130f322cb7e	311	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
mbed_official	159:7130f322cb7e	312	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
mbed_official	159:7130f322cb7e	313
mbed_official	159:7130f322cb7e	314
mbed_official	159:7130f322cb7e	315	/**
mbed_official	159:7130f322cb7e	316	\brief Union type to access the Control Registers (CONTROL).
mbed_official	159:7130f322cb7e	317	*/
mbed_official	159:7130f322cb7e	318	typedef union
mbed_official	159:7130f322cb7e	319	{
mbed_official	159:7130f322cb7e	320	struct
mbed_official	159:7130f322cb7e	321	{
mbed_official	159:7130f322cb7e	322	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
mbed_official	159:7130f322cb7e	323	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
mbed_official	159:7130f322cb7e	324	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
mbed_official	159:7130f322cb7e	325	} b; /!< Structure used for bit access /
mbed_official	159:7130f322cb7e	326	uint32_t w; /!< Type used for word access /
mbed_official	159:7130f322cb7e	327	} CONTROL_Type;
mbed_official	159:7130f322cb7e	328
mbed_official	159:7130f322cb7e	329	/* CONTROL Register Definitions */
mbed_official	159:7130f322cb7e	330	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
mbed_official	159:7130f322cb7e	331	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
mbed_official	159:7130f322cb7e	332
mbed_official	159:7130f322cb7e	333	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
mbed_official	159:7130f322cb7e	334	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
mbed_official	159:7130f322cb7e	335
mbed_official	159:7130f322cb7e	336	/@} end of group CMSIS_CORE /
mbed_official	159:7130f322cb7e	337
mbed_official	159:7130f322cb7e	338
mbed_official	159:7130f322cb7e	339	/**
mbed_official	159:7130f322cb7e	340	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	341	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mbed_official	159:7130f322cb7e	342	\brief Type definitions for the NVIC Registers
mbed_official	159:7130f322cb7e	343	@{
mbed_official	159:7130f322cb7e	344	*/
mbed_official	159:7130f322cb7e	345
mbed_official	159:7130f322cb7e	346	/**
mbed_official	159:7130f322cb7e	347	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mbed_official	159:7130f322cb7e	348	*/
mbed_official	159:7130f322cb7e	349	typedef struct
mbed_official	159:7130f322cb7e	350	{
mbed_official	159:7130f322cb7e	351	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
mbed_official	159:7130f322cb7e	352	uint32_t RESERVED0[16U];
mbed_official	159:7130f322cb7e	353	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
mbed_official	159:7130f322cb7e	354	uint32_t RSERVED1[16U];
mbed_official	159:7130f322cb7e	355	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
mbed_official	159:7130f322cb7e	356	uint32_t RESERVED2[16U];
mbed_official	159:7130f322cb7e	357	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
mbed_official	159:7130f322cb7e	358	uint32_t RESERVED3[16U];
mbed_official	159:7130f322cb7e	359	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
mbed_official	159:7130f322cb7e	360	uint32_t RESERVED4[16U];
mbed_official	159:7130f322cb7e	361	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
mbed_official	159:7130f322cb7e	362	uint32_t RESERVED5[16U];
mbed_official	159:7130f322cb7e	363	__IOM uint32_t IPR[124U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register /
mbed_official	159:7130f322cb7e	364	} NVIC_Type;
mbed_official	159:7130f322cb7e	365
mbed_official	159:7130f322cb7e	366	/@} end of group CMSIS_NVIC /
mbed_official	159:7130f322cb7e	367
mbed_official	159:7130f322cb7e	368
mbed_official	159:7130f322cb7e	369	/**
mbed_official	159:7130f322cb7e	370	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	371	\defgroup CMSIS_SCB System Control Block (SCB)
mbed_official	159:7130f322cb7e	372	\brief Type definitions for the System Control Block Registers
mbed_official	159:7130f322cb7e	373	@{
mbed_official	159:7130f322cb7e	374	*/
mbed_official	159:7130f322cb7e	375
mbed_official	159:7130f322cb7e	376	/**
mbed_official	159:7130f322cb7e	377	\brief Structure type to access the System Control Block (SCB).
mbed_official	159:7130f322cb7e	378	*/
mbed_official	159:7130f322cb7e	379	typedef struct
mbed_official	159:7130f322cb7e	380	{
mbed_official	159:7130f322cb7e	381	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
mbed_official	159:7130f322cb7e	382	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
mbed_official	159:7130f322cb7e	383	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
mbed_official	159:7130f322cb7e	384	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
mbed_official	159:7130f322cb7e	385	#else
mbed_official	159:7130f322cb7e	386	uint32_t RESERVED0;
mbed_official	159:7130f322cb7e	387	#endif
mbed_official	159:7130f322cb7e	388	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
mbed_official	159:7130f322cb7e	389	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
mbed_official	159:7130f322cb7e	390	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
mbed_official	159:7130f322cb7e	391	uint32_t RESERVED1;
mbed_official	159:7130f322cb7e	392	__IOM uint32_t SHPR[2U]; /!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED /
mbed_official	159:7130f322cb7e	393	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
mbed_official	159:7130f322cb7e	394	} SCB_Type;
mbed_official	159:7130f322cb7e	395
mbed_official	159:7130f322cb7e	396	/* SCB CPUID Register Definitions */
mbed_official	159:7130f322cb7e	397	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
mbed_official	159:7130f322cb7e	398	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
mbed_official	159:7130f322cb7e	399
mbed_official	159:7130f322cb7e	400	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
mbed_official	159:7130f322cb7e	401	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
mbed_official	159:7130f322cb7e	402
mbed_official	159:7130f322cb7e	403	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
mbed_official	159:7130f322cb7e	404	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
mbed_official	159:7130f322cb7e	405
mbed_official	159:7130f322cb7e	406	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
mbed_official	159:7130f322cb7e	407	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
mbed_official	159:7130f322cb7e	408
mbed_official	159:7130f322cb7e	409	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
mbed_official	159:7130f322cb7e	410	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
mbed_official	159:7130f322cb7e	411
mbed_official	159:7130f322cb7e	412	/* SCB Interrupt Control State Register Definitions */
mbed_official	159:7130f322cb7e	413	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
mbed_official	159:7130f322cb7e	414	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
mbed_official	159:7130f322cb7e	415
mbed_official	159:7130f322cb7e	416	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
mbed_official	159:7130f322cb7e	417	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
mbed_official	159:7130f322cb7e	418
mbed_official	159:7130f322cb7e	419	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
mbed_official	159:7130f322cb7e	420	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
mbed_official	159:7130f322cb7e	421
mbed_official	159:7130f322cb7e	422	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
mbed_official	159:7130f322cb7e	423	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
mbed_official	159:7130f322cb7e	424
mbed_official	159:7130f322cb7e	425	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
mbed_official	159:7130f322cb7e	426	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
mbed_official	159:7130f322cb7e	427
mbed_official	159:7130f322cb7e	428	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
mbed_official	159:7130f322cb7e	429	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
mbed_official	159:7130f322cb7e	430
mbed_official	159:7130f322cb7e	431	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
mbed_official	159:7130f322cb7e	432	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
mbed_official	159:7130f322cb7e	433
mbed_official	159:7130f322cb7e	434	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
mbed_official	159:7130f322cb7e	435	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
mbed_official	159:7130f322cb7e	436
mbed_official	159:7130f322cb7e	437	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
mbed_official	159:7130f322cb7e	438	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
mbed_official	159:7130f322cb7e	439
mbed_official	159:7130f322cb7e	440	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
mbed_official	159:7130f322cb7e	441	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
mbed_official	159:7130f322cb7e	442
mbed_official	159:7130f322cb7e	443	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
mbed_official	159:7130f322cb7e	444	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
mbed_official	159:7130f322cb7e	445
mbed_official	159:7130f322cb7e	446	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
mbed_official	159:7130f322cb7e	447	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
mbed_official	159:7130f322cb7e	448
mbed_official	159:7130f322cb7e	449	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
mbed_official	159:7130f322cb7e	450	/* SCB Vector Table Offset Register Definitions */
mbed_official	159:7130f322cb7e	451	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
mbed_official	159:7130f322cb7e	452	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
mbed_official	159:7130f322cb7e	453	#endif
mbed_official	159:7130f322cb7e	454
mbed_official	159:7130f322cb7e	455	/* SCB Application Interrupt and Reset Control Register Definitions */
mbed_official	159:7130f322cb7e	456	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
mbed_official	159:7130f322cb7e	457	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
mbed_official	159:7130f322cb7e	458
mbed_official	159:7130f322cb7e	459	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
mbed_official	159:7130f322cb7e	460	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
mbed_official	159:7130f322cb7e	461
mbed_official	159:7130f322cb7e	462	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
mbed_official	159:7130f322cb7e	463	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
mbed_official	159:7130f322cb7e	464
mbed_official	159:7130f322cb7e	465	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
mbed_official	159:7130f322cb7e	466	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
mbed_official	159:7130f322cb7e	467
mbed_official	159:7130f322cb7e	468	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
mbed_official	159:7130f322cb7e	469	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
mbed_official	159:7130f322cb7e	470
mbed_official	159:7130f322cb7e	471	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
mbed_official	159:7130f322cb7e	472	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
mbed_official	159:7130f322cb7e	473
mbed_official	159:7130f322cb7e	474	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
mbed_official	159:7130f322cb7e	475	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
mbed_official	159:7130f322cb7e	476
mbed_official	159:7130f322cb7e	477	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
mbed_official	159:7130f322cb7e	478	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
mbed_official	159:7130f322cb7e	479
mbed_official	159:7130f322cb7e	480	/* SCB System Control Register Definitions */
mbed_official	159:7130f322cb7e	481	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
mbed_official	159:7130f322cb7e	482	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
mbed_official	159:7130f322cb7e	483
mbed_official	159:7130f322cb7e	484	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
mbed_official	159:7130f322cb7e	485	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
mbed_official	159:7130f322cb7e	486
mbed_official	159:7130f322cb7e	487	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
mbed_official	159:7130f322cb7e	488	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
mbed_official	159:7130f322cb7e	489
mbed_official	159:7130f322cb7e	490	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
mbed_official	159:7130f322cb7e	491	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
mbed_official	159:7130f322cb7e	492
mbed_official	159:7130f322cb7e	493	/* SCB Configuration Control Register Definitions */
mbed_official	159:7130f322cb7e	494	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
mbed_official	159:7130f322cb7e	495	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
mbed_official	159:7130f322cb7e	496
mbed_official	159:7130f322cb7e	497	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
mbed_official	159:7130f322cb7e	498	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
mbed_official	159:7130f322cb7e	499
mbed_official	159:7130f322cb7e	500	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
mbed_official	159:7130f322cb7e	501	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
mbed_official	159:7130f322cb7e	502
mbed_official	159:7130f322cb7e	503	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
mbed_official	159:7130f322cb7e	504	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
mbed_official	159:7130f322cb7e	505
mbed_official	159:7130f322cb7e	506	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
mbed_official	159:7130f322cb7e	507	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
mbed_official	159:7130f322cb7e	508
mbed_official	159:7130f322cb7e	509	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
mbed_official	159:7130f322cb7e	510	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
mbed_official	159:7130f322cb7e	511
mbed_official	159:7130f322cb7e	512	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
mbed_official	159:7130f322cb7e	513	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
mbed_official	159:7130f322cb7e	514
mbed_official	159:7130f322cb7e	515	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
mbed_official	159:7130f322cb7e	516	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
mbed_official	159:7130f322cb7e	517
mbed_official	159:7130f322cb7e	518	/* SCB System Handler Control and State Register Definitions */
mbed_official	159:7130f322cb7e	519	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
mbed_official	159:7130f322cb7e	520	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
mbed_official	159:7130f322cb7e	521
mbed_official	159:7130f322cb7e	522	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
mbed_official	159:7130f322cb7e	523	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
mbed_official	159:7130f322cb7e	524
mbed_official	159:7130f322cb7e	525	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
mbed_official	159:7130f322cb7e	526	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
mbed_official	159:7130f322cb7e	527
mbed_official	159:7130f322cb7e	528	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
mbed_official	159:7130f322cb7e	529	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
mbed_official	159:7130f322cb7e	530
mbed_official	159:7130f322cb7e	531	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
mbed_official	159:7130f322cb7e	532	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
mbed_official	159:7130f322cb7e	533
mbed_official	159:7130f322cb7e	534	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
mbed_official	159:7130f322cb7e	535	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
mbed_official	159:7130f322cb7e	536
mbed_official	159:7130f322cb7e	537	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
mbed_official	159:7130f322cb7e	538	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
mbed_official	159:7130f322cb7e	539
mbed_official	159:7130f322cb7e	540	/@} end of group CMSIS_SCB /
mbed_official	159:7130f322cb7e	541
mbed_official	159:7130f322cb7e	542
mbed_official	159:7130f322cb7e	543	/**
mbed_official	159:7130f322cb7e	544	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	545	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
mbed_official	159:7130f322cb7e	546	\brief Type definitions for the System Timer Registers.
mbed_official	159:7130f322cb7e	547	@{
mbed_official	159:7130f322cb7e	548	*/
mbed_official	159:7130f322cb7e	549
mbed_official	159:7130f322cb7e	550	/**
mbed_official	159:7130f322cb7e	551	\brief Structure type to access the System Timer (SysTick).
mbed_official	159:7130f322cb7e	552	*/
mbed_official	159:7130f322cb7e	553	typedef struct
mbed_official	159:7130f322cb7e	554	{
mbed_official	159:7130f322cb7e	555	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
mbed_official	159:7130f322cb7e	556	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
mbed_official	159:7130f322cb7e	557	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
mbed_official	159:7130f322cb7e	558	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
mbed_official	159:7130f322cb7e	559	} SysTick_Type;
mbed_official	159:7130f322cb7e	560
mbed_official	159:7130f322cb7e	561	/* SysTick Control / Status Register Definitions */
mbed_official	159:7130f322cb7e	562	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
mbed_official	159:7130f322cb7e	563	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
mbed_official	159:7130f322cb7e	564
mbed_official	159:7130f322cb7e	565	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
mbed_official	159:7130f322cb7e	566	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
mbed_official	159:7130f322cb7e	567
mbed_official	159:7130f322cb7e	568	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
mbed_official	159:7130f322cb7e	569	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
mbed_official	159:7130f322cb7e	570
mbed_official	159:7130f322cb7e	571	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
mbed_official	159:7130f322cb7e	572	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
mbed_official	159:7130f322cb7e	573
mbed_official	159:7130f322cb7e	574	/* SysTick Reload Register Definitions */
mbed_official	159:7130f322cb7e	575	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
mbed_official	159:7130f322cb7e	576	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
mbed_official	159:7130f322cb7e	577
mbed_official	159:7130f322cb7e	578	/* SysTick Current Register Definitions */
mbed_official	159:7130f322cb7e	579	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
mbed_official	159:7130f322cb7e	580	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
mbed_official	159:7130f322cb7e	581
mbed_official	159:7130f322cb7e	582	/* SysTick Calibration Register Definitions */
mbed_official	159:7130f322cb7e	583	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
mbed_official	159:7130f322cb7e	584	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
mbed_official	159:7130f322cb7e	585
mbed_official	159:7130f322cb7e	586	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
mbed_official	159:7130f322cb7e	587	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
mbed_official	159:7130f322cb7e	588
mbed_official	159:7130f322cb7e	589	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
mbed_official	159:7130f322cb7e	590	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
mbed_official	159:7130f322cb7e	591
mbed_official	159:7130f322cb7e	592	/@} end of group CMSIS_SysTick /
mbed_official	159:7130f322cb7e	593
mbed_official	159:7130f322cb7e	594
mbed_official	159:7130f322cb7e	595	/**
mbed_official	159:7130f322cb7e	596	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	597	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
mbed_official	159:7130f322cb7e	598	\brief Type definitions for the Data Watchpoint and Trace (DWT)
mbed_official	159:7130f322cb7e	599	@{
mbed_official	159:7130f322cb7e	600	*/
mbed_official	159:7130f322cb7e	601
mbed_official	159:7130f322cb7e	602	/**
mbed_official	159:7130f322cb7e	603	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
mbed_official	159:7130f322cb7e	604	*/
mbed_official	159:7130f322cb7e	605	typedef struct
mbed_official	159:7130f322cb7e	606	{
mbed_official	159:7130f322cb7e	607	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
mbed_official	159:7130f322cb7e	608	uint32_t RESERVED0[6U];
mbed_official	159:7130f322cb7e	609	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
mbed_official	159:7130f322cb7e	610	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
mbed_official	159:7130f322cb7e	611	uint32_t RESERVED1[1U];
mbed_official	159:7130f322cb7e	612	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
mbed_official	159:7130f322cb7e	613	uint32_t RESERVED2[1U];
mbed_official	159:7130f322cb7e	614	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
mbed_official	159:7130f322cb7e	615	uint32_t RESERVED3[1U];
mbed_official	159:7130f322cb7e	616	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
mbed_official	159:7130f322cb7e	617	uint32_t RESERVED4[1U];
mbed_official	159:7130f322cb7e	618	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
mbed_official	159:7130f322cb7e	619	uint32_t RESERVED5[1U];
mbed_official	159:7130f322cb7e	620	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
mbed_official	159:7130f322cb7e	621	uint32_t RESERVED6[1U];
mbed_official	159:7130f322cb7e	622	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
mbed_official	159:7130f322cb7e	623	uint32_t RESERVED7[1U];
mbed_official	159:7130f322cb7e	624	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
mbed_official	159:7130f322cb7e	625	uint32_t RESERVED8[1U];
mbed_official	159:7130f322cb7e	626	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
mbed_official	159:7130f322cb7e	627	uint32_t RESERVED9[1U];
mbed_official	159:7130f322cb7e	628	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
mbed_official	159:7130f322cb7e	629	uint32_t RESERVED10[1U];
mbed_official	159:7130f322cb7e	630	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
mbed_official	159:7130f322cb7e	631	uint32_t RESERVED11[1U];
mbed_official	159:7130f322cb7e	632	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
mbed_official	159:7130f322cb7e	633	uint32_t RESERVED12[1U];
mbed_official	159:7130f322cb7e	634	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
mbed_official	159:7130f322cb7e	635	uint32_t RESERVED13[1U];
mbed_official	159:7130f322cb7e	636	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
mbed_official	159:7130f322cb7e	637	uint32_t RESERVED14[1U];
mbed_official	159:7130f322cb7e	638	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
mbed_official	159:7130f322cb7e	639	uint32_t RESERVED15[1U];
mbed_official	159:7130f322cb7e	640	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
mbed_official	159:7130f322cb7e	641	uint32_t RESERVED16[1U];
mbed_official	159:7130f322cb7e	642	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
mbed_official	159:7130f322cb7e	643	uint32_t RESERVED17[1U];
mbed_official	159:7130f322cb7e	644	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
mbed_official	159:7130f322cb7e	645	uint32_t RESERVED18[1U];
mbed_official	159:7130f322cb7e	646	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
mbed_official	159:7130f322cb7e	647	uint32_t RESERVED19[1U];
mbed_official	159:7130f322cb7e	648	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
mbed_official	159:7130f322cb7e	649	uint32_t RESERVED20[1U];
mbed_official	159:7130f322cb7e	650	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
mbed_official	159:7130f322cb7e	651	uint32_t RESERVED21[1U];
mbed_official	159:7130f322cb7e	652	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
mbed_official	159:7130f322cb7e	653	uint32_t RESERVED22[1U];
mbed_official	159:7130f322cb7e	654	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
mbed_official	159:7130f322cb7e	655	uint32_t RESERVED23[1U];
mbed_official	159:7130f322cb7e	656	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
mbed_official	159:7130f322cb7e	657	uint32_t RESERVED24[1U];
mbed_official	159:7130f322cb7e	658	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
mbed_official	159:7130f322cb7e	659	uint32_t RESERVED25[1U];
mbed_official	159:7130f322cb7e	660	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
mbed_official	159:7130f322cb7e	661	uint32_t RESERVED26[1U];
mbed_official	159:7130f322cb7e	662	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
mbed_official	159:7130f322cb7e	663	uint32_t RESERVED27[1U];
mbed_official	159:7130f322cb7e	664	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
mbed_official	159:7130f322cb7e	665	uint32_t RESERVED28[1U];
mbed_official	159:7130f322cb7e	666	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
mbed_official	159:7130f322cb7e	667	uint32_t RESERVED29[1U];
mbed_official	159:7130f322cb7e	668	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
mbed_official	159:7130f322cb7e	669	uint32_t RESERVED30[1U];
mbed_official	159:7130f322cb7e	670	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
mbed_official	159:7130f322cb7e	671	uint32_t RESERVED31[1U];
mbed_official	159:7130f322cb7e	672	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
mbed_official	159:7130f322cb7e	673	} DWT_Type;
mbed_official	159:7130f322cb7e	674
mbed_official	159:7130f322cb7e	675	/* DWT Control Register Definitions */
mbed_official	159:7130f322cb7e	676	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
mbed_official	159:7130f322cb7e	677	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
mbed_official	159:7130f322cb7e	678
mbed_official	159:7130f322cb7e	679	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
mbed_official	159:7130f322cb7e	680	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
mbed_official	159:7130f322cb7e	681
mbed_official	159:7130f322cb7e	682	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
mbed_official	159:7130f322cb7e	683	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
mbed_official	159:7130f322cb7e	684
mbed_official	159:7130f322cb7e	685	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
mbed_official	159:7130f322cb7e	686	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
mbed_official	159:7130f322cb7e	687
mbed_official	159:7130f322cb7e	688	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
mbed_official	159:7130f322cb7e	689	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
mbed_official	159:7130f322cb7e	690
mbed_official	159:7130f322cb7e	691	/* DWT Comparator Function Register Definitions */
mbed_official	159:7130f322cb7e	692	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
mbed_official	159:7130f322cb7e	693	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
mbed_official	159:7130f322cb7e	694
mbed_official	159:7130f322cb7e	695	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
mbed_official	159:7130f322cb7e	696	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
mbed_official	159:7130f322cb7e	697
mbed_official	159:7130f322cb7e	698	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
mbed_official	159:7130f322cb7e	699	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
mbed_official	159:7130f322cb7e	700
mbed_official	159:7130f322cb7e	701	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
mbed_official	159:7130f322cb7e	702	#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
mbed_official	159:7130f322cb7e	703
mbed_official	159:7130f322cb7e	704	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
mbed_official	159:7130f322cb7e	705	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
mbed_official	159:7130f322cb7e	706
mbed_official	159:7130f322cb7e	707	/@}/ /* end of group CMSIS_DWT */
mbed_official	159:7130f322cb7e	708
mbed_official	159:7130f322cb7e	709
mbed_official	159:7130f322cb7e	710	/**
mbed_official	159:7130f322cb7e	711	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	712	\defgroup CMSIS_TPI Trace Port Interface (TPI)
mbed_official	159:7130f322cb7e	713	\brief Type definitions for the Trace Port Interface (TPI)
mbed_official	159:7130f322cb7e	714	@{
mbed_official	159:7130f322cb7e	715	*/
mbed_official	159:7130f322cb7e	716
mbed_official	159:7130f322cb7e	717	/**
mbed_official	159:7130f322cb7e	718	\brief Structure type to access the Trace Port Interface Register (TPI).
mbed_official	159:7130f322cb7e	719	*/
mbed_official	159:7130f322cb7e	720	typedef struct
mbed_official	159:7130f322cb7e	721	{
mbed_official	159:7130f322cb7e	722	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
mbed_official	159:7130f322cb7e	723	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
mbed_official	159:7130f322cb7e	724	uint32_t RESERVED0[2U];
mbed_official	159:7130f322cb7e	725	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
mbed_official	159:7130f322cb7e	726	uint32_t RESERVED1[55U];
mbed_official	159:7130f322cb7e	727	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
mbed_official	159:7130f322cb7e	728	uint32_t RESERVED2[131U];
mbed_official	159:7130f322cb7e	729	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
mbed_official	159:7130f322cb7e	730	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
mbed_official	159:7130f322cb7e	731	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
mbed_official	159:7130f322cb7e	732	uint32_t RESERVED3[759U];
mbed_official	159:7130f322cb7e	733	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
mbed_official	159:7130f322cb7e	734	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
mbed_official	159:7130f322cb7e	735	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
mbed_official	159:7130f322cb7e	736	uint32_t RESERVED4[1U];
mbed_official	159:7130f322cb7e	737	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
mbed_official	159:7130f322cb7e	738	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
mbed_official	159:7130f322cb7e	739	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
mbed_official	159:7130f322cb7e	740	uint32_t RESERVED5[39U];
mbed_official	159:7130f322cb7e	741	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
mbed_official	159:7130f322cb7e	742	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
mbed_official	159:7130f322cb7e	743	uint32_t RESERVED7[8U];
mbed_official	159:7130f322cb7e	744	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
mbed_official	159:7130f322cb7e	745	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
mbed_official	159:7130f322cb7e	746	} TPI_Type;
mbed_official	159:7130f322cb7e	747
mbed_official	159:7130f322cb7e	748	/* TPI Asynchronous Clock Prescaler Register Definitions */
mbed_official	159:7130f322cb7e	749	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
mbed_official	159:7130f322cb7e	750	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
mbed_official	159:7130f322cb7e	751
mbed_official	159:7130f322cb7e	752	/* TPI Selected Pin Protocol Register Definitions */
mbed_official	159:7130f322cb7e	753	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
mbed_official	159:7130f322cb7e	754	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
mbed_official	159:7130f322cb7e	755
mbed_official	159:7130f322cb7e	756	/* TPI Formatter and Flush Status Register Definitions */
mbed_official	159:7130f322cb7e	757	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
mbed_official	159:7130f322cb7e	758	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
mbed_official	159:7130f322cb7e	759
mbed_official	159:7130f322cb7e	760	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
mbed_official	159:7130f322cb7e	761	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
mbed_official	159:7130f322cb7e	762
mbed_official	159:7130f322cb7e	763	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
mbed_official	159:7130f322cb7e	764	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
mbed_official	159:7130f322cb7e	765
mbed_official	159:7130f322cb7e	766	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
mbed_official	159:7130f322cb7e	767	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
mbed_official	159:7130f322cb7e	768
mbed_official	159:7130f322cb7e	769	/* TPI Formatter and Flush Control Register Definitions */
mbed_official	159:7130f322cb7e	770	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
mbed_official	159:7130f322cb7e	771	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
mbed_official	159:7130f322cb7e	772
mbed_official	159:7130f322cb7e	773	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
mbed_official	159:7130f322cb7e	774	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
mbed_official	159:7130f322cb7e	775
mbed_official	159:7130f322cb7e	776	/* TPI TRIGGER Register Definitions */
mbed_official	159:7130f322cb7e	777	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
mbed_official	159:7130f322cb7e	778	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
mbed_official	159:7130f322cb7e	779
mbed_official	159:7130f322cb7e	780	/* TPI Integration ETM Data Register Definitions (FIFO0) */
mbed_official	159:7130f322cb7e	781	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
mbed_official	159:7130f322cb7e	782	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
mbed_official	159:7130f322cb7e	783
mbed_official	159:7130f322cb7e	784	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
mbed_official	159:7130f322cb7e	785	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
mbed_official	159:7130f322cb7e	786
mbed_official	159:7130f322cb7e	787	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
mbed_official	159:7130f322cb7e	788	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
mbed_official	159:7130f322cb7e	789
mbed_official	159:7130f322cb7e	790	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
mbed_official	159:7130f322cb7e	791	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
mbed_official	159:7130f322cb7e	792
mbed_official	159:7130f322cb7e	793	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
mbed_official	159:7130f322cb7e	794	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
mbed_official	159:7130f322cb7e	795
mbed_official	159:7130f322cb7e	796	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
mbed_official	159:7130f322cb7e	797	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
mbed_official	159:7130f322cb7e	798
mbed_official	159:7130f322cb7e	799	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
mbed_official	159:7130f322cb7e	800	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
mbed_official	159:7130f322cb7e	801
mbed_official	159:7130f322cb7e	802	/* TPI ITATBCTR2 Register Definitions */
mbed_official	159:7130f322cb7e	803	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
mbed_official	159:7130f322cb7e	804	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
mbed_official	159:7130f322cb7e	805
mbed_official	159:7130f322cb7e	806	/* TPI Integration ITM Data Register Definitions (FIFO1) */
mbed_official	159:7130f322cb7e	807	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
mbed_official	159:7130f322cb7e	808	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
mbed_official	159:7130f322cb7e	809
mbed_official	159:7130f322cb7e	810	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
mbed_official	159:7130f322cb7e	811	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
mbed_official	159:7130f322cb7e	812
mbed_official	159:7130f322cb7e	813	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
mbed_official	159:7130f322cb7e	814	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
mbed_official	159:7130f322cb7e	815
mbed_official	159:7130f322cb7e	816	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
mbed_official	159:7130f322cb7e	817	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
mbed_official	159:7130f322cb7e	818
mbed_official	159:7130f322cb7e	819	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
mbed_official	159:7130f322cb7e	820	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
mbed_official	159:7130f322cb7e	821
mbed_official	159:7130f322cb7e	822	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
mbed_official	159:7130f322cb7e	823	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
mbed_official	159:7130f322cb7e	824
mbed_official	159:7130f322cb7e	825	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
mbed_official	159:7130f322cb7e	826	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
mbed_official	159:7130f322cb7e	827
mbed_official	159:7130f322cb7e	828	/* TPI ITATBCTR0 Register Definitions */
mbed_official	159:7130f322cb7e	829	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
mbed_official	159:7130f322cb7e	830	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
mbed_official	159:7130f322cb7e	831
mbed_official	159:7130f322cb7e	832	/* TPI Integration Mode Control Register Definitions */
mbed_official	159:7130f322cb7e	833	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
mbed_official	159:7130f322cb7e	834	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
mbed_official	159:7130f322cb7e	835
mbed_official	159:7130f322cb7e	836	/* TPI DEVID Register Definitions */
mbed_official	159:7130f322cb7e	837	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
mbed_official	159:7130f322cb7e	838	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
mbed_official	159:7130f322cb7e	839
mbed_official	159:7130f322cb7e	840	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
mbed_official	159:7130f322cb7e	841	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
mbed_official	159:7130f322cb7e	842
mbed_official	159:7130f322cb7e	843	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
mbed_official	159:7130f322cb7e	844	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
mbed_official	159:7130f322cb7e	845
mbed_official	159:7130f322cb7e	846	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
mbed_official	159:7130f322cb7e	847	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
mbed_official	159:7130f322cb7e	848
mbed_official	159:7130f322cb7e	849	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
mbed_official	159:7130f322cb7e	850	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
mbed_official	159:7130f322cb7e	851
mbed_official	159:7130f322cb7e	852	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
mbed_official	159:7130f322cb7e	853	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
mbed_official	159:7130f322cb7e	854
mbed_official	159:7130f322cb7e	855	/* TPI DEVTYPE Register Definitions */
mbed_official	159:7130f322cb7e	856	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
mbed_official	159:7130f322cb7e	857	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
mbed_official	159:7130f322cb7e	858
mbed_official	159:7130f322cb7e	859	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
mbed_official	159:7130f322cb7e	860	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
mbed_official	159:7130f322cb7e	861
mbed_official	159:7130f322cb7e	862	/@}/ /* end of group CMSIS_TPI */
mbed_official	159:7130f322cb7e	863
mbed_official	159:7130f322cb7e	864
mbed_official	159:7130f322cb7e	865	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
mbed_official	159:7130f322cb7e	866	/**
mbed_official	159:7130f322cb7e	867	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	868	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
mbed_official	159:7130f322cb7e	869	\brief Type definitions for the Memory Protection Unit (MPU)
mbed_official	159:7130f322cb7e	870	@{
mbed_official	159:7130f322cb7e	871	*/
mbed_official	159:7130f322cb7e	872
mbed_official	159:7130f322cb7e	873	/**
mbed_official	159:7130f322cb7e	874	\brief Structure type to access the Memory Protection Unit (MPU).
mbed_official	159:7130f322cb7e	875	*/
mbed_official	159:7130f322cb7e	876	typedef struct
mbed_official	159:7130f322cb7e	877	{
mbed_official	159:7130f322cb7e	878	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
mbed_official	159:7130f322cb7e	879	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
mbed_official	159:7130f322cb7e	880	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
mbed_official	159:7130f322cb7e	881	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
mbed_official	159:7130f322cb7e	882	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
mbed_official	159:7130f322cb7e	883	uint32_t RESERVED0[7U];
mbed_official	159:7130f322cb7e	884	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
mbed_official	159:7130f322cb7e	885	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
mbed_official	159:7130f322cb7e	886	} MPU_Type;
mbed_official	159:7130f322cb7e	887
mbed_official	159:7130f322cb7e	888	/* MPU Type Register Definitions */
mbed_official	159:7130f322cb7e	889	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
mbed_official	159:7130f322cb7e	890	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
mbed_official	159:7130f322cb7e	891
mbed_official	159:7130f322cb7e	892	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
mbed_official	159:7130f322cb7e	893	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
mbed_official	159:7130f322cb7e	894
mbed_official	159:7130f322cb7e	895	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
mbed_official	159:7130f322cb7e	896	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
mbed_official	159:7130f322cb7e	897
mbed_official	159:7130f322cb7e	898	/* MPU Control Register Definitions */
mbed_official	159:7130f322cb7e	899	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
mbed_official	159:7130f322cb7e	900	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
mbed_official	159:7130f322cb7e	901
mbed_official	159:7130f322cb7e	902	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
mbed_official	159:7130f322cb7e	903	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
mbed_official	159:7130f322cb7e	904
mbed_official	159:7130f322cb7e	905	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
mbed_official	159:7130f322cb7e	906	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
mbed_official	159:7130f322cb7e	907
mbed_official	159:7130f322cb7e	908	/* MPU Region Number Register Definitions */
mbed_official	159:7130f322cb7e	909	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
mbed_official	159:7130f322cb7e	910	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
mbed_official	159:7130f322cb7e	911
mbed_official	159:7130f322cb7e	912	/* MPU Region Base Address Register Definitions */
mbed_official	159:7130f322cb7e	913	#define MPU_RBAR_BASE_Pos 5U /!< MPU RBAR: BASE Position /
mbed_official	159:7130f322cb7e	914	#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /!< MPU RBAR: BASE Mask /
mbed_official	159:7130f322cb7e	915
mbed_official	159:7130f322cb7e	916	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
mbed_official	159:7130f322cb7e	917	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
mbed_official	159:7130f322cb7e	918
mbed_official	159:7130f322cb7e	919	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
mbed_official	159:7130f322cb7e	920	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
mbed_official	159:7130f322cb7e	921
mbed_official	159:7130f322cb7e	922	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
mbed_official	159:7130f322cb7e	923	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
mbed_official	159:7130f322cb7e	924
mbed_official	159:7130f322cb7e	925	/* MPU Region Limit Address Register Definitions */
mbed_official	159:7130f322cb7e	926	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
mbed_official	159:7130f322cb7e	927	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
mbed_official	159:7130f322cb7e	928
mbed_official	159:7130f322cb7e	929	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
mbed_official	159:7130f322cb7e	930	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
mbed_official	159:7130f322cb7e	931
mbed_official	159:7130f322cb7e	932	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: EN Position /
mbed_official	159:7130f322cb7e	933	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: EN Mask /
mbed_official	159:7130f322cb7e	934
mbed_official	159:7130f322cb7e	935	/* MPU Memory Attribute Indirection Register 0 Definitions */
mbed_official	159:7130f322cb7e	936	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
mbed_official	159:7130f322cb7e	937	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
mbed_official	159:7130f322cb7e	938
mbed_official	159:7130f322cb7e	939	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
mbed_official	159:7130f322cb7e	940	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
mbed_official	159:7130f322cb7e	941
mbed_official	159:7130f322cb7e	942	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
mbed_official	159:7130f322cb7e	943	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
mbed_official	159:7130f322cb7e	944
mbed_official	159:7130f322cb7e	945	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
mbed_official	159:7130f322cb7e	946	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
mbed_official	159:7130f322cb7e	947
mbed_official	159:7130f322cb7e	948	/* MPU Memory Attribute Indirection Register 1 Definitions */
mbed_official	159:7130f322cb7e	949	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
mbed_official	159:7130f322cb7e	950	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
mbed_official	159:7130f322cb7e	951
mbed_official	159:7130f322cb7e	952	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
mbed_official	159:7130f322cb7e	953	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
mbed_official	159:7130f322cb7e	954
mbed_official	159:7130f322cb7e	955	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
mbed_official	159:7130f322cb7e	956	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
mbed_official	159:7130f322cb7e	957
mbed_official	159:7130f322cb7e	958	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
mbed_official	159:7130f322cb7e	959	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
mbed_official	159:7130f322cb7e	960
mbed_official	159:7130f322cb7e	961	/@} end of group CMSIS_MPU /
mbed_official	159:7130f322cb7e	962	#endif
mbed_official	159:7130f322cb7e	963
mbed_official	159:7130f322cb7e	964
mbed_official	159:7130f322cb7e	965	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
mbed_official	159:7130f322cb7e	966	/**
mbed_official	159:7130f322cb7e	967	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	968	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
mbed_official	159:7130f322cb7e	969	\brief Type definitions for the Security Attribution Unit (SAU)
mbed_official	159:7130f322cb7e	970	@{
mbed_official	159:7130f322cb7e	971	*/
mbed_official	159:7130f322cb7e	972
mbed_official	159:7130f322cb7e	973	/**
mbed_official	159:7130f322cb7e	974	\brief Structure type to access the Security Attribution Unit (SAU).
mbed_official	159:7130f322cb7e	975	*/
mbed_official	159:7130f322cb7e	976	typedef struct
mbed_official	159:7130f322cb7e	977	{
mbed_official	159:7130f322cb7e	978	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
mbed_official	159:7130f322cb7e	979	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
mbed_official	159:7130f322cb7e	980	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
mbed_official	159:7130f322cb7e	981	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
mbed_official	159:7130f322cb7e	982	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
mbed_official	159:7130f322cb7e	983	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
mbed_official	159:7130f322cb7e	984	#endif
mbed_official	159:7130f322cb7e	985	} SAU_Type;
mbed_official	159:7130f322cb7e	986
mbed_official	159:7130f322cb7e	987	/* SAU Control Register Definitions */
mbed_official	159:7130f322cb7e	988	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
mbed_official	159:7130f322cb7e	989	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
mbed_official	159:7130f322cb7e	990
mbed_official	159:7130f322cb7e	991	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
mbed_official	159:7130f322cb7e	992	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
mbed_official	159:7130f322cb7e	993
mbed_official	159:7130f322cb7e	994	/* SAU Type Register Definitions */
mbed_official	159:7130f322cb7e	995	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
mbed_official	159:7130f322cb7e	996	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
mbed_official	159:7130f322cb7e	997
mbed_official	159:7130f322cb7e	998	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
mbed_official	159:7130f322cb7e	999	/* SAU Region Number Register Definitions */
mbed_official	159:7130f322cb7e	1000	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
mbed_official	159:7130f322cb7e	1001	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
mbed_official	159:7130f322cb7e	1002
mbed_official	159:7130f322cb7e	1003	/* SAU Region Base Address Register Definitions */
mbed_official	159:7130f322cb7e	1004	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
mbed_official	159:7130f322cb7e	1005	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
mbed_official	159:7130f322cb7e	1006
mbed_official	159:7130f322cb7e	1007	/* SAU Region Limit Address Register Definitions */
mbed_official	159:7130f322cb7e	1008	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
mbed_official	159:7130f322cb7e	1009	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
mbed_official	159:7130f322cb7e	1010
mbed_official	159:7130f322cb7e	1011	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
mbed_official	159:7130f322cb7e	1012	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
mbed_official	159:7130f322cb7e	1013
mbed_official	159:7130f322cb7e	1014	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
mbed_official	159:7130f322cb7e	1015	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
mbed_official	159:7130f322cb7e	1016
mbed_official	159:7130f322cb7e	1017	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
mbed_official	159:7130f322cb7e	1018
mbed_official	159:7130f322cb7e	1019	/@} end of group CMSIS_SAU /
mbed_official	159:7130f322cb7e	1020	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
mbed_official	159:7130f322cb7e	1021
mbed_official	159:7130f322cb7e	1022
mbed_official	159:7130f322cb7e	1023	/**
mbed_official	159:7130f322cb7e	1024	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	1025	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mbed_official	159:7130f322cb7e	1026	\brief Type definitions for the Core Debug Registers
mbed_official	159:7130f322cb7e	1027	@{
mbed_official	159:7130f322cb7e	1028	*/
mbed_official	159:7130f322cb7e	1029
mbed_official	159:7130f322cb7e	1030	/**
mbed_official	159:7130f322cb7e	1031	\brief Structure type to access the Core Debug Register (CoreDebug).
mbed_official	159:7130f322cb7e	1032	*/
mbed_official	159:7130f322cb7e	1033	typedef struct
mbed_official	159:7130f322cb7e	1034	{
mbed_official	159:7130f322cb7e	1035	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
mbed_official	159:7130f322cb7e	1036	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
mbed_official	159:7130f322cb7e	1037	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
mbed_official	159:7130f322cb7e	1038	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
mbed_official	159:7130f322cb7e	1039	uint32_t RESERVED4[1U];
mbed_official	159:7130f322cb7e	1040	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
mbed_official	159:7130f322cb7e	1041	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
mbed_official	159:7130f322cb7e	1042	} CoreDebug_Type;
mbed_official	159:7130f322cb7e	1043
mbed_official	159:7130f322cb7e	1044	/* Debug Halting Control and Status Register Definitions */
mbed_official	159:7130f322cb7e	1045	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
mbed_official	159:7130f322cb7e	1046	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
mbed_official	159:7130f322cb7e	1047
mbed_official	159:7130f322cb7e	1048	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
mbed_official	159:7130f322cb7e	1049	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
mbed_official	159:7130f322cb7e	1050
mbed_official	159:7130f322cb7e	1051	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
mbed_official	159:7130f322cb7e	1052	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
mbed_official	159:7130f322cb7e	1053
mbed_official	159:7130f322cb7e	1054	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
mbed_official	159:7130f322cb7e	1055	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
mbed_official	159:7130f322cb7e	1056
mbed_official	159:7130f322cb7e	1057	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
mbed_official	159:7130f322cb7e	1058	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
mbed_official	159:7130f322cb7e	1059
mbed_official	159:7130f322cb7e	1060	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
mbed_official	159:7130f322cb7e	1061	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
mbed_official	159:7130f322cb7e	1062
mbed_official	159:7130f322cb7e	1063	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
mbed_official	159:7130f322cb7e	1064	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
mbed_official	159:7130f322cb7e	1065
mbed_official	159:7130f322cb7e	1066	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
mbed_official	159:7130f322cb7e	1067	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
mbed_official	159:7130f322cb7e	1068
mbed_official	159:7130f322cb7e	1069	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
mbed_official	159:7130f322cb7e	1070	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
mbed_official	159:7130f322cb7e	1071
mbed_official	159:7130f322cb7e	1072	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
mbed_official	159:7130f322cb7e	1073	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
mbed_official	159:7130f322cb7e	1074
mbed_official	159:7130f322cb7e	1075	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
mbed_official	159:7130f322cb7e	1076	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
mbed_official	159:7130f322cb7e	1077
mbed_official	159:7130f322cb7e	1078	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
mbed_official	159:7130f322cb7e	1079	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
mbed_official	159:7130f322cb7e	1080
mbed_official	159:7130f322cb7e	1081	/* Debug Core Register Selector Register Definitions */
mbed_official	159:7130f322cb7e	1082	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
mbed_official	159:7130f322cb7e	1083	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
mbed_official	159:7130f322cb7e	1084
mbed_official	159:7130f322cb7e	1085	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
mbed_official	159:7130f322cb7e	1086	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
mbed_official	159:7130f322cb7e	1087
mbed_official	159:7130f322cb7e	1088	/* Debug Exception and Monitor Control Register */
mbed_official	159:7130f322cb7e	1089	#define CoreDebug_DEMCR_DWTENA_Pos 24U /!< CoreDebug DEMCR: DWTENA Position /
mbed_official	159:7130f322cb7e	1090	#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /!< CoreDebug DEMCR: DWTENA Mask /
mbed_official	159:7130f322cb7e	1091
mbed_official	159:7130f322cb7e	1092	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
mbed_official	159:7130f322cb7e	1093	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
mbed_official	159:7130f322cb7e	1094
mbed_official	159:7130f322cb7e	1095	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
mbed_official	159:7130f322cb7e	1096	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
mbed_official	159:7130f322cb7e	1097
mbed_official	159:7130f322cb7e	1098	/* Debug Authentication Control Register Definitions */
mbed_official	159:7130f322cb7e	1099	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
mbed_official	159:7130f322cb7e	1100	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
mbed_official	159:7130f322cb7e	1101
mbed_official	159:7130f322cb7e	1102	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
mbed_official	159:7130f322cb7e	1103	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
mbed_official	159:7130f322cb7e	1104
mbed_official	159:7130f322cb7e	1105	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
mbed_official	159:7130f322cb7e	1106	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
mbed_official	159:7130f322cb7e	1107
mbed_official	159:7130f322cb7e	1108	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
mbed_official	159:7130f322cb7e	1109	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
mbed_official	159:7130f322cb7e	1110
mbed_official	159:7130f322cb7e	1111	/* Debug Security Control and Status Register Definitions */
mbed_official	159:7130f322cb7e	1112	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
mbed_official	159:7130f322cb7e	1113	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
mbed_official	159:7130f322cb7e	1114
mbed_official	159:7130f322cb7e	1115	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
mbed_official	159:7130f322cb7e	1116	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
mbed_official	159:7130f322cb7e	1117
mbed_official	159:7130f322cb7e	1118	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
mbed_official	159:7130f322cb7e	1119	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
mbed_official	159:7130f322cb7e	1120
mbed_official	159:7130f322cb7e	1121	/@} end of group CMSIS_CoreDebug /
mbed_official	159:7130f322cb7e	1122
mbed_official	159:7130f322cb7e	1123
mbed_official	159:7130f322cb7e	1124	/**
mbed_official	159:7130f322cb7e	1125	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	1126	\defgroup CMSIS_core_bitfield Core register bit field macros
mbed_official	159:7130f322cb7e	1127	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
mbed_official	159:7130f322cb7e	1128	@{
mbed_official	159:7130f322cb7e	1129	*/
mbed_official	159:7130f322cb7e	1130
mbed_official	159:7130f322cb7e	1131	/**
mbed_official	159:7130f322cb7e	1132	\brief Mask and shift a bit field value for use in a register bit range.
mbed_official	159:7130f322cb7e	1133	\param[in] field Name of the register bit field.
mbed_official	159:7130f322cb7e	1134	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
mbed_official	159:7130f322cb7e	1135	\return Masked and shifted value.
mbed_official	159:7130f322cb7e	1136	*/
mbed_official	159:7130f322cb7e	1137	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
mbed_official	159:7130f322cb7e	1138
mbed_official	159:7130f322cb7e	1139	/**
mbed_official	159:7130f322cb7e	1140	\brief Mask and shift a register value to extract a bit filed value.
mbed_official	159:7130f322cb7e	1141	\param[in] field Name of the register bit field.
mbed_official	159:7130f322cb7e	1142	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
mbed_official	159:7130f322cb7e	1143	\return Masked and shifted bit field value.
mbed_official	159:7130f322cb7e	1144	*/
mbed_official	159:7130f322cb7e	1145	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
mbed_official	159:7130f322cb7e	1146
mbed_official	159:7130f322cb7e	1147	/@} end of group CMSIS_core_bitfield /
mbed_official	159:7130f322cb7e	1148
mbed_official	159:7130f322cb7e	1149
mbed_official	159:7130f322cb7e	1150	/**
mbed_official	159:7130f322cb7e	1151	\ingroup CMSIS_core_register
mbed_official	159:7130f322cb7e	1152	\defgroup CMSIS_core_base Core Definitions
mbed_official	159:7130f322cb7e	1153	\brief Definitions for base addresses, unions, and structures.
mbed_official	159:7130f322cb7e	1154	@{
mbed_official	159:7130f322cb7e	1155	*/
mbed_official	159:7130f322cb7e	1156
mbed_official	159:7130f322cb7e	1157	/* Memory mapping of Core Hardware */
mbed_official	159:7130f322cb7e	1158	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
mbed_official	159:7130f322cb7e	1159	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
mbed_official	159:7130f322cb7e	1160	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
mbed_official	159:7130f322cb7e	1161	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
mbed_official	159:7130f322cb7e	1162	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
mbed_official	159:7130f322cb7e	1163	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
mbed_official	159:7130f322cb7e	1164	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
mbed_official	159:7130f322cb7e	1165
mbed_official	159:7130f322cb7e	1166
mbed_official	159:7130f322cb7e	1167	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
mbed_official	159:7130f322cb7e	1168	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
mbed_official	159:7130f322cb7e	1169	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
mbed_official	159:7130f322cb7e	1170	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
mbed_official	159:7130f322cb7e	1171	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
mbed_official	159:7130f322cb7e	1172	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
mbed_official	159:7130f322cb7e	1173
mbed_official	159:7130f322cb7e	1174	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
mbed_official	159:7130f322cb7e	1175	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
mbed_official	159:7130f322cb7e	1176	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
mbed_official	159:7130f322cb7e	1177	#endif
mbed_official	159:7130f322cb7e	1178
mbed_official	159:7130f322cb7e	1179	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
mbed_official	159:7130f322cb7e	1180	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
mbed_official	159:7130f322cb7e	1181	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
mbed_official	159:7130f322cb7e	1182	#endif
mbed_official	159:7130f322cb7e	1183
mbed_official	159:7130f322cb7e	1184	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
mbed_official	159:7130f322cb7e	1185	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
mbed_official	159:7130f322cb7e	1186	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
mbed_official	159:7130f322cb7e	1187	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
mbed_official	159:7130f322cb7e	1188	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
mbed_official	159:7130f322cb7e	1189	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
mbed_official	159:7130f322cb7e	1190
mbed_official	159:7130f322cb7e	1191	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
mbed_official	159:7130f322cb7e	1192	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
mbed_official	159:7130f322cb7e	1193	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
mbed_official	159:7130f322cb7e	1194	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
mbed_official	159:7130f322cb7e	1195
mbed_official	159:7130f322cb7e	1196	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
mbed_official	159:7130f322cb7e	1197	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
mbed_official	159:7130f322cb7e	1198	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
mbed_official	159:7130f322cb7e	1199	#endif
mbed_official	159:7130f322cb7e	1200
mbed_official	159:7130f322cb7e	1201	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
mbed_official	159:7130f322cb7e	1202	/@} /
mbed_official	159:7130f322cb7e	1203
mbed_official	159:7130f322cb7e	1204
mbed_official	159:7130f322cb7e	1205
mbed_official	159:7130f322cb7e	1206	/*******************************************************************************
mbed_official	159:7130f322cb7e	1207	* Hardware Abstraction Layer
mbed_official	159:7130f322cb7e	1208	Core Function Interface contains:
mbed_official	159:7130f322cb7e	1209	- Core NVIC Functions
mbed_official	159:7130f322cb7e	1210	- Core SysTick Functions
mbed_official	159:7130f322cb7e	1211	- Core Register Access Functions
mbed_official	159:7130f322cb7e	1212	******************************************************************************/
mbed_official	159:7130f322cb7e	1213	/**
mbed_official	159:7130f322cb7e	1214	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mbed_official	159:7130f322cb7e	1215	*/
mbed_official	159:7130f322cb7e	1216
mbed_official	159:7130f322cb7e	1217
mbed_official	159:7130f322cb7e	1218
mbed_official	159:7130f322cb7e	1219	/* ########################## NVIC functions #################################### */
mbed_official	159:7130f322cb7e	1220	/**
mbed_official	159:7130f322cb7e	1221	\ingroup CMSIS_Core_FunctionInterface
mbed_official	159:7130f322cb7e	1222	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
mbed_official	159:7130f322cb7e	1223	\brief Functions that manage interrupts and exceptions via the NVIC.
mbed_official	159:7130f322cb7e	1224	@{
mbed_official	159:7130f322cb7e	1225	*/
mbed_official	159:7130f322cb7e	1226
mbed_official	159:7130f322cb7e	1227	#ifdef CMSIS_NVIC_VIRTUAL
mbed_official	159:7130f322cb7e	1228	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
mbed_official	159:7130f322cb7e	1229	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
mbed_official	159:7130f322cb7e	1230	#endif
mbed_official	159:7130f322cb7e	1231	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
mbed_official	159:7130f322cb7e	1232	#else
mbed_official	159:7130f322cb7e	1233	/#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 /
mbed_official	159:7130f322cb7e	1234	/#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 /
mbed_official	159:7130f322cb7e	1235	#define NVIC_EnableIRQ __NVIC_EnableIRQ
mbed_official	159:7130f322cb7e	1236	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
mbed_official	159:7130f322cb7e	1237	#define NVIC_DisableIRQ __NVIC_DisableIRQ
mbed_official	159:7130f322cb7e	1238	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
mbed_official	159:7130f322cb7e	1239	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
mbed_official	159:7130f322cb7e	1240	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
mbed_official	159:7130f322cb7e	1241	#define NVIC_GetActive __NVIC_GetActive
mbed_official	159:7130f322cb7e	1242	#define NVIC_SetPriority __NVIC_SetPriority
mbed_official	159:7130f322cb7e	1243	#define NVIC_GetPriority __NVIC_GetPriority
mbed_official	159:7130f322cb7e	1244	#define NVIC_SystemReset __NVIC_SystemReset
mbed_official	159:7130f322cb7e	1245	#endif /* CMSIS_NVIC_VIRTUAL */
mbed_official	159:7130f322cb7e	1246
mbed_official	159:7130f322cb7e	1247	#ifdef CMSIS_VECTAB_VIRTUAL
mbed_official	159:7130f322cb7e	1248	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
mbed_official	159:7130f322cb7e	1249	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
mbed_official	159:7130f322cb7e	1250	#endif
mbed_official	159:7130f322cb7e	1251	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
mbed_official	159:7130f322cb7e	1252	#else
mbed_official	159:7130f322cb7e	1253	#define NVIC_SetVector __NVIC_SetVector
mbed_official	159:7130f322cb7e	1254	#define NVIC_GetVector __NVIC_GetVector
mbed_official	159:7130f322cb7e	1255	#endif /* (CMSIS_VECTAB_VIRTUAL) */
mbed_official	159:7130f322cb7e	1256
mbed_official	159:7130f322cb7e	1257	#define NVIC_USER_IRQ_OFFSET 16
mbed_official	159:7130f322cb7e	1258
mbed_official	159:7130f322cb7e	1259
mbed_official	159:7130f322cb7e	1260	/* Interrupt Priorities are WORD accessible only under ARMv6M */
mbed_official	159:7130f322cb7e	1261	/* The following MACROS handle generation of the register offset and byte masks */
mbed_official	159:7130f322cb7e	1262	#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
mbed_official	159:7130f322cb7e	1263	#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
mbed_official	159:7130f322cb7e	1264	#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
mbed_official	159:7130f322cb7e	1265
mbed_official	159:7130f322cb7e	1266
mbed_official	159:7130f322cb7e	1267	/**
mbed_official	159:7130f322cb7e	1268	\brief Enable Interrupt
mbed_official	159:7130f322cb7e	1269	\details Enables a device specific interrupt in the NVIC interrupt controller.
mbed_official	159:7130f322cb7e	1270	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1271	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1272	*/
mbed_official	159:7130f322cb7e	1273	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1274	{
mbed_official	159:7130f322cb7e	1275	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1276	{
mbed_official	159:7130f322cb7e	1277	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official	159:7130f322cb7e	1278	}
mbed_official	159:7130f322cb7e	1279	}
mbed_official	159:7130f322cb7e	1280
mbed_official	159:7130f322cb7e	1281
mbed_official	159:7130f322cb7e	1282	/**
mbed_official	159:7130f322cb7e	1283	\brief Get Interrupt Enable status
mbed_official	159:7130f322cb7e	1284	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
mbed_official	159:7130f322cb7e	1285	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1286	\return 0 Interrupt is not enabled.
mbed_official	159:7130f322cb7e	1287	\return 1 Interrupt is enabled.
mbed_official	159:7130f322cb7e	1288	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1289	*/
mbed_official	159:7130f322cb7e	1290	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1291	{
mbed_official	159:7130f322cb7e	1292	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1293	{
mbed_official	159:7130f322cb7e	1294	return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official	159:7130f322cb7e	1295	}
mbed_official	159:7130f322cb7e	1296	else
mbed_official	159:7130f322cb7e	1297	{
mbed_official	159:7130f322cb7e	1298	return(0U);
mbed_official	159:7130f322cb7e	1299	}
mbed_official	159:7130f322cb7e	1300	}
mbed_official	159:7130f322cb7e	1301
mbed_official	159:7130f322cb7e	1302
mbed_official	159:7130f322cb7e	1303	/**
mbed_official	159:7130f322cb7e	1304	\brief Disable Interrupt
mbed_official	159:7130f322cb7e	1305	\details Disables a device specific interrupt in the NVIC interrupt controller.
mbed_official	159:7130f322cb7e	1306	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1307	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1308	*/
mbed_official	159:7130f322cb7e	1309	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1310	{
mbed_official	159:7130f322cb7e	1311	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1312	{
mbed_official	159:7130f322cb7e	1313	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official	159:7130f322cb7e	1314	__DSB();
mbed_official	159:7130f322cb7e	1315	__ISB();
mbed_official	159:7130f322cb7e	1316	}
mbed_official	159:7130f322cb7e	1317	}
mbed_official	159:7130f322cb7e	1318
mbed_official	159:7130f322cb7e	1319
mbed_official	159:7130f322cb7e	1320	/**
mbed_official	159:7130f322cb7e	1321	\brief Get Pending Interrupt
mbed_official	159:7130f322cb7e	1322	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
mbed_official	159:7130f322cb7e	1323	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1324	\return 0 Interrupt status is not pending.
mbed_official	159:7130f322cb7e	1325	\return 1 Interrupt status is pending.
mbed_official	159:7130f322cb7e	1326	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1327	*/
mbed_official	159:7130f322cb7e	1328	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1329	{
mbed_official	159:7130f322cb7e	1330	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1331	{
mbed_official	159:7130f322cb7e	1332	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official	159:7130f322cb7e	1333	}
mbed_official	159:7130f322cb7e	1334	else
mbed_official	159:7130f322cb7e	1335	{
mbed_official	159:7130f322cb7e	1336	return(0U);
mbed_official	159:7130f322cb7e	1337	}
mbed_official	159:7130f322cb7e	1338	}
mbed_official	159:7130f322cb7e	1339
mbed_official	159:7130f322cb7e	1340
mbed_official	159:7130f322cb7e	1341	/**
mbed_official	159:7130f322cb7e	1342	\brief Set Pending Interrupt
mbed_official	159:7130f322cb7e	1343	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
mbed_official	159:7130f322cb7e	1344	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1345	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1346	*/
mbed_official	159:7130f322cb7e	1347	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1348	{
mbed_official	159:7130f322cb7e	1349	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1350	{
mbed_official	159:7130f322cb7e	1351	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official	159:7130f322cb7e	1352	}
mbed_official	159:7130f322cb7e	1353	}
mbed_official	159:7130f322cb7e	1354
mbed_official	159:7130f322cb7e	1355
mbed_official	159:7130f322cb7e	1356	/**
mbed_official	159:7130f322cb7e	1357	\brief Clear Pending Interrupt
mbed_official	159:7130f322cb7e	1358	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
mbed_official	159:7130f322cb7e	1359	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1360	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1361	*/
mbed_official	159:7130f322cb7e	1362	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1363	{
mbed_official	159:7130f322cb7e	1364	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1365	{
mbed_official	159:7130f322cb7e	1366	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official	159:7130f322cb7e	1367	}
mbed_official	159:7130f322cb7e	1368	}
mbed_official	159:7130f322cb7e	1369
mbed_official	159:7130f322cb7e	1370
mbed_official	159:7130f322cb7e	1371	/**
mbed_official	159:7130f322cb7e	1372	\brief Get Active Interrupt
mbed_official	159:7130f322cb7e	1373	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
mbed_official	159:7130f322cb7e	1374	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1375	\return 0 Interrupt status is not active.
mbed_official	159:7130f322cb7e	1376	\return 1 Interrupt status is active.
mbed_official	159:7130f322cb7e	1377	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1378	*/
mbed_official	159:7130f322cb7e	1379	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1380	{
mbed_official	159:7130f322cb7e	1381	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1382	{
mbed_official	159:7130f322cb7e	1383	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official	159:7130f322cb7e	1384	}
mbed_official	159:7130f322cb7e	1385	else
mbed_official	159:7130f322cb7e	1386	{
mbed_official	159:7130f322cb7e	1387	return(0U);
mbed_official	159:7130f322cb7e	1388	}
mbed_official	159:7130f322cb7e	1389	}
mbed_official	159:7130f322cb7e	1390
mbed_official	159:7130f322cb7e	1391
mbed_official	159:7130f322cb7e	1392	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
mbed_official	159:7130f322cb7e	1393	/**
mbed_official	159:7130f322cb7e	1394	\brief Get Interrupt Target State
mbed_official	159:7130f322cb7e	1395	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
mbed_official	159:7130f322cb7e	1396	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1397	\return 0 if interrupt is assigned to Secure
mbed_official	159:7130f322cb7e	1398	\return 1 if interrupt is assigned to Non Secure
mbed_official	159:7130f322cb7e	1399	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1400	*/
mbed_official	159:7130f322cb7e	1401	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1402	{
mbed_official	159:7130f322cb7e	1403	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1404	{
mbed_official	159:7130f322cb7e	1405	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official	159:7130f322cb7e	1406	}
mbed_official	159:7130f322cb7e	1407	else
mbed_official	159:7130f322cb7e	1408	{
mbed_official	159:7130f322cb7e	1409	return(0U);
mbed_official	159:7130f322cb7e	1410	}
mbed_official	159:7130f322cb7e	1411	}
mbed_official	159:7130f322cb7e	1412
mbed_official	159:7130f322cb7e	1413
mbed_official	159:7130f322cb7e	1414	/**
mbed_official	159:7130f322cb7e	1415	\brief Set Interrupt Target State
mbed_official	159:7130f322cb7e	1416	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
mbed_official	159:7130f322cb7e	1417	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1418	\return 0 if interrupt is assigned to Secure
mbed_official	159:7130f322cb7e	1419	1 if interrupt is assigned to Non Secure
mbed_official	159:7130f322cb7e	1420	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1421	*/
mbed_official	159:7130f322cb7e	1422	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1423	{
mbed_official	159:7130f322cb7e	1424	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1425	{
mbed_official	159:7130f322cb7e	1426	NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
mbed_official	159:7130f322cb7e	1427	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official	159:7130f322cb7e	1428	}
mbed_official	159:7130f322cb7e	1429	else
mbed_official	159:7130f322cb7e	1430	{
mbed_official	159:7130f322cb7e	1431	return(0U);
mbed_official	159:7130f322cb7e	1432	}
mbed_official	159:7130f322cb7e	1433	}
mbed_official	159:7130f322cb7e	1434
mbed_official	159:7130f322cb7e	1435
mbed_official	159:7130f322cb7e	1436	/**
mbed_official	159:7130f322cb7e	1437	\brief Clear Interrupt Target State
mbed_official	159:7130f322cb7e	1438	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
mbed_official	159:7130f322cb7e	1439	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1440	\return 0 if interrupt is assigned to Secure
mbed_official	159:7130f322cb7e	1441	1 if interrupt is assigned to Non Secure
mbed_official	159:7130f322cb7e	1442	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1443	*/
mbed_official	159:7130f322cb7e	1444	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1445	{
mbed_official	159:7130f322cb7e	1446	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1447	{
mbed_official	159:7130f322cb7e	1448	NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
mbed_official	159:7130f322cb7e	1449	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official	159:7130f322cb7e	1450	}
mbed_official	159:7130f322cb7e	1451	else
mbed_official	159:7130f322cb7e	1452	{
mbed_official	159:7130f322cb7e	1453	return(0U);
mbed_official	159:7130f322cb7e	1454	}
mbed_official	159:7130f322cb7e	1455	}
mbed_official	159:7130f322cb7e	1456	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
mbed_official	159:7130f322cb7e	1457
mbed_official	159:7130f322cb7e	1458
mbed_official	159:7130f322cb7e	1459	/**
mbed_official	159:7130f322cb7e	1460	\brief Set Interrupt Priority
mbed_official	159:7130f322cb7e	1461	\details Sets the priority of a device specific interrupt or a processor exception.
mbed_official	159:7130f322cb7e	1462	The interrupt number can be positive to specify a device specific interrupt,
mbed_official	159:7130f322cb7e	1463	or negative to specify a processor exception.
mbed_official	159:7130f322cb7e	1464	\param [in] IRQn Interrupt number.
mbed_official	159:7130f322cb7e	1465	\param [in] priority Priority to set.
mbed_official	159:7130f322cb7e	1466	\note The priority cannot be set for every processor exception.
mbed_official	159:7130f322cb7e	1467	*/
mbed_official	159:7130f322cb7e	1468	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mbed_official	159:7130f322cb7e	1469	{
mbed_official	159:7130f322cb7e	1470	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1471	{
mbed_official	159:7130f322cb7e	1472	NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
mbed_official	159:7130f322cb7e	1473	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
mbed_official	159:7130f322cb7e	1474	}
mbed_official	159:7130f322cb7e	1475	else
mbed_official	159:7130f322cb7e	1476	{
mbed_official	159:7130f322cb7e	1477	SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
mbed_official	159:7130f322cb7e	1478	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
mbed_official	159:7130f322cb7e	1479	}
mbed_official	159:7130f322cb7e	1480	}
mbed_official	159:7130f322cb7e	1481
mbed_official	159:7130f322cb7e	1482
mbed_official	159:7130f322cb7e	1483	/**
mbed_official	159:7130f322cb7e	1484	\brief Get Interrupt Priority
mbed_official	159:7130f322cb7e	1485	\details Reads the priority of a device specific interrupt or a processor exception.
mbed_official	159:7130f322cb7e	1486	The interrupt number can be positive to specify a device specific interrupt,
mbed_official	159:7130f322cb7e	1487	or negative to specify a processor exception.
mbed_official	159:7130f322cb7e	1488	\param [in] IRQn Interrupt number.
mbed_official	159:7130f322cb7e	1489	\return Interrupt Priority.
mbed_official	159:7130f322cb7e	1490	Value is aligned automatically to the implemented priority bits of the microcontroller.
mbed_official	159:7130f322cb7e	1491	*/
mbed_official	159:7130f322cb7e	1492	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1493	{
mbed_official	159:7130f322cb7e	1494
mbed_official	159:7130f322cb7e	1495	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1496	{
mbed_official	159:7130f322cb7e	1497	return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
mbed_official	159:7130f322cb7e	1498	}
mbed_official	159:7130f322cb7e	1499	else
mbed_official	159:7130f322cb7e	1500	{
mbed_official	159:7130f322cb7e	1501	return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
mbed_official	159:7130f322cb7e	1502	}
mbed_official	159:7130f322cb7e	1503	}
mbed_official	159:7130f322cb7e	1504
mbed_official	159:7130f322cb7e	1505
mbed_official	159:7130f322cb7e	1506	/**
mbed_official	159:7130f322cb7e	1507	\brief Set Interrupt Vector
mbed_official	159:7130f322cb7e	1508	\details Sets an interrupt vector in SRAM based interrupt vector table.
mbed_official	159:7130f322cb7e	1509	The interrupt number can be positive to specify a device specific interrupt,
mbed_official	159:7130f322cb7e	1510	or negative to specify a processor exception.
mbed_official	159:7130f322cb7e	1511	VTOR must been relocated to SRAM before.
mbed_official	159:7130f322cb7e	1512	If VTOR is not present address 0 must be mapped to SRAM.
mbed_official	159:7130f322cb7e	1513	\param [in] IRQn Interrupt number
mbed_official	159:7130f322cb7e	1514	\param [in] vector Address of interrupt handler function
mbed_official	159:7130f322cb7e	1515	*/
mbed_official	159:7130f322cb7e	1516	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
mbed_official	159:7130f322cb7e	1517	{
mbed_official	159:7130f322cb7e	1518	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
mbed_official	159:7130f322cb7e	1519	uint32_t vectors = (uint32_t )SCB->VTOR;
mbed_official	159:7130f322cb7e	1520	#else
mbed_official	159:7130f322cb7e	1521	uint32_t vectors = (uint32_t )0x0U;
mbed_official	159:7130f322cb7e	1522	#endif
mbed_official	159:7130f322cb7e	1523	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
mbed_official	159:7130f322cb7e	1524	}
mbed_official	159:7130f322cb7e	1525
mbed_official	159:7130f322cb7e	1526
mbed_official	159:7130f322cb7e	1527	/**
mbed_official	159:7130f322cb7e	1528	\brief Get Interrupt Vector
mbed_official	159:7130f322cb7e	1529	\details Reads an interrupt vector from interrupt vector table.
mbed_official	159:7130f322cb7e	1530	The interrupt number can be positive to specify a device specific interrupt,
mbed_official	159:7130f322cb7e	1531	or negative to specify a processor exception.
mbed_official	159:7130f322cb7e	1532	\param [in] IRQn Interrupt number.
mbed_official	159:7130f322cb7e	1533	\return Address of interrupt handler function
mbed_official	159:7130f322cb7e	1534	*/
mbed_official	159:7130f322cb7e	1535	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1536	{
mbed_official	159:7130f322cb7e	1537	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
mbed_official	159:7130f322cb7e	1538	uint32_t vectors = (uint32_t )SCB->VTOR;
mbed_official	159:7130f322cb7e	1539	#else
mbed_official	159:7130f322cb7e	1540	uint32_t vectors = (uint32_t )0x0U;
mbed_official	159:7130f322cb7e	1541	#endif
mbed_official	159:7130f322cb7e	1542	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
mbed_official	159:7130f322cb7e	1543	}
mbed_official	159:7130f322cb7e	1544
mbed_official	159:7130f322cb7e	1545
mbed_official	159:7130f322cb7e	1546	/**
mbed_official	159:7130f322cb7e	1547	\brief System Reset
mbed_official	159:7130f322cb7e	1548	\details Initiates a system reset request to reset the MCU.
mbed_official	159:7130f322cb7e	1549	*/
mbed_official	159:7130f322cb7e	1550	__STATIC_INLINE void __NVIC_SystemReset(void)
mbed_official	159:7130f322cb7e	1551	{
mbed_official	159:7130f322cb7e	1552	__DSB(); /* Ensure all outstanding memory accesses included
mbed_official	159:7130f322cb7e	1553	buffered write are completed before reset */
mbed_official	159:7130f322cb7e	1554	SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
mbed_official	159:7130f322cb7e	1555	SCB_AIRCR_SYSRESETREQ_Msk);
mbed_official	159:7130f322cb7e	1556	__DSB(); /* Ensure completion of memory access */
mbed_official	159:7130f322cb7e	1557
mbed_official	159:7130f322cb7e	1558	for(;;) /* wait until reset */
mbed_official	159:7130f322cb7e	1559	{
mbed_official	159:7130f322cb7e	1560	__NOP();
mbed_official	159:7130f322cb7e	1561	}
mbed_official	159:7130f322cb7e	1562	}
mbed_official	159:7130f322cb7e	1563
mbed_official	159:7130f322cb7e	1564	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
mbed_official	159:7130f322cb7e	1565	/**
mbed_official	159:7130f322cb7e	1566	\brief Enable Interrupt (non-secure)
mbed_official	159:7130f322cb7e	1567	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
mbed_official	159:7130f322cb7e	1568	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1569	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1570	*/
mbed_official	159:7130f322cb7e	1571	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1572	{
mbed_official	159:7130f322cb7e	1573	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1574	{
mbed_official	159:7130f322cb7e	1575	NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official	159:7130f322cb7e	1576	}
mbed_official	159:7130f322cb7e	1577	}
mbed_official	159:7130f322cb7e	1578
mbed_official	159:7130f322cb7e	1579
mbed_official	159:7130f322cb7e	1580	/**
mbed_official	159:7130f322cb7e	1581	\brief Get Interrupt Enable status (non-secure)
mbed_official	159:7130f322cb7e	1582	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
mbed_official	159:7130f322cb7e	1583	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1584	\return 0 Interrupt is not enabled.
mbed_official	159:7130f322cb7e	1585	\return 1 Interrupt is enabled.
mbed_official	159:7130f322cb7e	1586	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1587	*/
mbed_official	159:7130f322cb7e	1588	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1589	{
mbed_official	159:7130f322cb7e	1590	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1591	{
mbed_official	159:7130f322cb7e	1592	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official	159:7130f322cb7e	1593	}
mbed_official	159:7130f322cb7e	1594	else
mbed_official	159:7130f322cb7e	1595	{
mbed_official	159:7130f322cb7e	1596	return(0U);
mbed_official	159:7130f322cb7e	1597	}
mbed_official	159:7130f322cb7e	1598	}
mbed_official	159:7130f322cb7e	1599
mbed_official	159:7130f322cb7e	1600
mbed_official	159:7130f322cb7e	1601	/**
mbed_official	159:7130f322cb7e	1602	\brief Disable Interrupt (non-secure)
mbed_official	159:7130f322cb7e	1603	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
mbed_official	159:7130f322cb7e	1604	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1605	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1606	*/
mbed_official	159:7130f322cb7e	1607	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1608	{
mbed_official	159:7130f322cb7e	1609	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1610	{
mbed_official	159:7130f322cb7e	1611	NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official	159:7130f322cb7e	1612	}
mbed_official	159:7130f322cb7e	1613	}
mbed_official	159:7130f322cb7e	1614
mbed_official	159:7130f322cb7e	1615
mbed_official	159:7130f322cb7e	1616	/**
mbed_official	159:7130f322cb7e	1617	\brief Get Pending Interrupt (non-secure)
mbed_official	159:7130f322cb7e	1618	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
mbed_official	159:7130f322cb7e	1619	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1620	\return 0 Interrupt status is not pending.
mbed_official	159:7130f322cb7e	1621	\return 1 Interrupt status is pending.
mbed_official	159:7130f322cb7e	1622	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1623	*/
mbed_official	159:7130f322cb7e	1624	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1625	{
mbed_official	159:7130f322cb7e	1626	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1627	{
mbed_official	159:7130f322cb7e	1628	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official	159:7130f322cb7e	1629	}
mbed_official	159:7130f322cb7e	1630	}
mbed_official	159:7130f322cb7e	1631
mbed_official	159:7130f322cb7e	1632
mbed_official	159:7130f322cb7e	1633	/**
mbed_official	159:7130f322cb7e	1634	\brief Set Pending Interrupt (non-secure)
mbed_official	159:7130f322cb7e	1635	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
mbed_official	159:7130f322cb7e	1636	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1637	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1638	*/
mbed_official	159:7130f322cb7e	1639	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1640	{
mbed_official	159:7130f322cb7e	1641	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1642	{
mbed_official	159:7130f322cb7e	1643	NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official	159:7130f322cb7e	1644	}
mbed_official	159:7130f322cb7e	1645	}
mbed_official	159:7130f322cb7e	1646
mbed_official	159:7130f322cb7e	1647
mbed_official	159:7130f322cb7e	1648	/**
mbed_official	159:7130f322cb7e	1649	\brief Clear Pending Interrupt (non-secure)
mbed_official	159:7130f322cb7e	1650	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
mbed_official	159:7130f322cb7e	1651	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1652	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1653	*/
mbed_official	159:7130f322cb7e	1654	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1655	{
mbed_official	159:7130f322cb7e	1656	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1657	{
mbed_official	159:7130f322cb7e	1658	NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official	159:7130f322cb7e	1659	}
mbed_official	159:7130f322cb7e	1660	}
mbed_official	159:7130f322cb7e	1661
mbed_official	159:7130f322cb7e	1662
mbed_official	159:7130f322cb7e	1663	/**
mbed_official	159:7130f322cb7e	1664	\brief Get Active Interrupt (non-secure)
mbed_official	159:7130f322cb7e	1665	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
mbed_official	159:7130f322cb7e	1666	\param [in] IRQn Device specific interrupt number.
mbed_official	159:7130f322cb7e	1667	\return 0 Interrupt status is not active.
mbed_official	159:7130f322cb7e	1668	\return 1 Interrupt status is active.
mbed_official	159:7130f322cb7e	1669	\note IRQn must not be negative.
mbed_official	159:7130f322cb7e	1670	*/
mbed_official	159:7130f322cb7e	1671	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1672	{
mbed_official	159:7130f322cb7e	1673	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1674	{
mbed_official	159:7130f322cb7e	1675	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official	159:7130f322cb7e	1676	}
mbed_official	159:7130f322cb7e	1677	else
mbed_official	159:7130f322cb7e	1678	{
mbed_official	159:7130f322cb7e	1679	return(0U);
mbed_official	159:7130f322cb7e	1680	}
mbed_official	159:7130f322cb7e	1681	}
mbed_official	159:7130f322cb7e	1682
mbed_official	159:7130f322cb7e	1683
mbed_official	159:7130f322cb7e	1684	/**
mbed_official	159:7130f322cb7e	1685	\brief Set Interrupt Priority (non-secure)
mbed_official	159:7130f322cb7e	1686	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
mbed_official	159:7130f322cb7e	1687	The interrupt number can be positive to specify a device specific interrupt,
mbed_official	159:7130f322cb7e	1688	or negative to specify a processor exception.
mbed_official	159:7130f322cb7e	1689	\param [in] IRQn Interrupt number.
mbed_official	159:7130f322cb7e	1690	\param [in] priority Priority to set.
mbed_official	159:7130f322cb7e	1691	\note The priority cannot be set for every non-secure processor exception.
mbed_official	159:7130f322cb7e	1692	*/
mbed_official	159:7130f322cb7e	1693	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
mbed_official	159:7130f322cb7e	1694	{
mbed_official	159:7130f322cb7e	1695	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1696	{
mbed_official	159:7130f322cb7e	1697	NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
mbed_official	159:7130f322cb7e	1698	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
mbed_official	159:7130f322cb7e	1699	}
mbed_official	159:7130f322cb7e	1700	else
mbed_official	159:7130f322cb7e	1701	{
mbed_official	159:7130f322cb7e	1702	SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
mbed_official	159:7130f322cb7e	1703	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
mbed_official	159:7130f322cb7e	1704	}
mbed_official	159:7130f322cb7e	1705	}
mbed_official	159:7130f322cb7e	1706
mbed_official	159:7130f322cb7e	1707
mbed_official	159:7130f322cb7e	1708	/**
mbed_official	159:7130f322cb7e	1709	\brief Get Interrupt Priority (non-secure)
mbed_official	159:7130f322cb7e	1710	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
mbed_official	159:7130f322cb7e	1711	The interrupt number can be positive to specify a device specific interrupt,
mbed_official	159:7130f322cb7e	1712	or negative to specify a processor exception.
mbed_official	159:7130f322cb7e	1713	\param [in] IRQn Interrupt number.
mbed_official	159:7130f322cb7e	1714	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
mbed_official	159:7130f322cb7e	1715	*/
mbed_official	159:7130f322cb7e	1716	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
mbed_official	159:7130f322cb7e	1717	{
mbed_official	159:7130f322cb7e	1718
mbed_official	159:7130f322cb7e	1719	if ((int32_t)(IRQn) >= 0)
mbed_official	159:7130f322cb7e	1720	{
mbed_official	159:7130f322cb7e	1721	return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
mbed_official	159:7130f322cb7e	1722	}
mbed_official	159:7130f322cb7e	1723	else
mbed_official	159:7130f322cb7e	1724	{
mbed_official	159:7130f322cb7e	1725	return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
mbed_official	159:7130f322cb7e	1726	}
mbed_official	159:7130f322cb7e	1727	}
mbed_official	159:7130f322cb7e	1728	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
mbed_official	159:7130f322cb7e	1729
mbed_official	159:7130f322cb7e	1730	/@} end of CMSIS_Core_NVICFunctions /
mbed_official	159:7130f322cb7e	1731
mbed_official	159:7130f322cb7e	1732
mbed_official	159:7130f322cb7e	1733	/* ########################## FPU functions #################################### */
mbed_official	159:7130f322cb7e	1734	/**
mbed_official	159:7130f322cb7e	1735	\ingroup CMSIS_Core_FunctionInterface
mbed_official	159:7130f322cb7e	1736	\defgroup CMSIS_Core_FpuFunctions FPU Functions
mbed_official	159:7130f322cb7e	1737	\brief Function that provides FPU type.
mbed_official	159:7130f322cb7e	1738	@{
mbed_official	159:7130f322cb7e	1739	*/
mbed_official	159:7130f322cb7e	1740
mbed_official	159:7130f322cb7e	1741	/**
mbed_official	159:7130f322cb7e	1742	\brief get FPU type
mbed_official	159:7130f322cb7e	1743	\details returns the FPU type
mbed_official	159:7130f322cb7e	1744	\returns
mbed_official	159:7130f322cb7e	1745	- \b 0: No FPU
mbed_official	159:7130f322cb7e	1746	- \b 1: Single precision FPU
mbed_official	159:7130f322cb7e	1747	- \b 2: Double + Single precision FPU
mbed_official	159:7130f322cb7e	1748	*/
mbed_official	159:7130f322cb7e	1749	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
mbed_official	159:7130f322cb7e	1750	{
mbed_official	159:7130f322cb7e	1751	return 0U; /* No FPU */
mbed_official	159:7130f322cb7e	1752	}
mbed_official	159:7130f322cb7e	1753
mbed_official	159:7130f322cb7e	1754
mbed_official	159:7130f322cb7e	1755	/@} end of CMSIS_Core_FpuFunctions /
mbed_official	159:7130f322cb7e	1756
mbed_official	159:7130f322cb7e	1757
mbed_official	159:7130f322cb7e	1758
mbed_official	159:7130f322cb7e	1759	/* ########################## SAU functions #################################### */
mbed_official	159:7130f322cb7e	1760	/**
mbed_official	159:7130f322cb7e	1761	\ingroup CMSIS_Core_FunctionInterface
mbed_official	159:7130f322cb7e	1762	\defgroup CMSIS_Core_SAUFunctions SAU Functions
mbed_official	159:7130f322cb7e	1763	\brief Functions that configure the SAU.
mbed_official	159:7130f322cb7e	1764	@{
mbed_official	159:7130f322cb7e	1765	*/
mbed_official	159:7130f322cb7e	1766
mbed_official	159:7130f322cb7e	1767	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
mbed_official	159:7130f322cb7e	1768
mbed_official	159:7130f322cb7e	1769	/**
mbed_official	159:7130f322cb7e	1770	\brief Enable SAU
mbed_official	159:7130f322cb7e	1771	\details Enables the Security Attribution Unit (SAU).
mbed_official	159:7130f322cb7e	1772	*/
mbed_official	159:7130f322cb7e	1773	__STATIC_INLINE void TZ_SAU_Enable(void)
mbed_official	159:7130f322cb7e	1774	{
mbed_official	159:7130f322cb7e	1775	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
mbed_official	159:7130f322cb7e	1776	}
mbed_official	159:7130f322cb7e	1777
mbed_official	159:7130f322cb7e	1778
mbed_official	159:7130f322cb7e	1779
mbed_official	159:7130f322cb7e	1780	/**
mbed_official	159:7130f322cb7e	1781	\brief Disable SAU
mbed_official	159:7130f322cb7e	1782	\details Disables the Security Attribution Unit (SAU).
mbed_official	159:7130f322cb7e	1783	*/
mbed_official	159:7130f322cb7e	1784	__STATIC_INLINE void TZ_SAU_Disable(void)
mbed_official	159:7130f322cb7e	1785	{
mbed_official	159:7130f322cb7e	1786	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
mbed_official	159:7130f322cb7e	1787	}
mbed_official	159:7130f322cb7e	1788
mbed_official	159:7130f322cb7e	1789	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
mbed_official	159:7130f322cb7e	1790
mbed_official	159:7130f322cb7e	1791	/@} end of CMSIS_Core_SAUFunctions /
mbed_official	159:7130f322cb7e	1792
mbed_official	159:7130f322cb7e	1793
mbed_official	159:7130f322cb7e	1794
mbed_official	159:7130f322cb7e	1795
mbed_official	159:7130f322cb7e	1796	/* ################################## SysTick function ############################################ */
mbed_official	159:7130f322cb7e	1797	/**
mbed_official	159:7130f322cb7e	1798	\ingroup CMSIS_Core_FunctionInterface
mbed_official	159:7130f322cb7e	1799	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mbed_official	159:7130f322cb7e	1800	\brief Functions that configure the System.
mbed_official	159:7130f322cb7e	1801	@{
mbed_official	159:7130f322cb7e	1802	*/
mbed_official	159:7130f322cb7e	1803
mbed_official	159:7130f322cb7e	1804	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
mbed_official	159:7130f322cb7e	1805
mbed_official	159:7130f322cb7e	1806	/**
mbed_official	159:7130f322cb7e	1807	\brief System Tick Configuration
mbed_official	159:7130f322cb7e	1808	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
mbed_official	159:7130f322cb7e	1809	Counter is in free running mode to generate periodic interrupts.
mbed_official	159:7130f322cb7e	1810	\param [in] ticks Number of ticks between two interrupts.
mbed_official	159:7130f322cb7e	1811	\return 0 Function succeeded.
mbed_official	159:7130f322cb7e	1812	\return 1 Function failed.
mbed_official	159:7130f322cb7e	1813	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mbed_official	159:7130f322cb7e	1814	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mbed_official	159:7130f322cb7e	1815	must contain a vendor-specific implementation of this function.
mbed_official	159:7130f322cb7e	1816	*/
mbed_official	159:7130f322cb7e	1817	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mbed_official	159:7130f322cb7e	1818	{
mbed_official	159:7130f322cb7e	1819	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
mbed_official	159:7130f322cb7e	1820	{
mbed_official	159:7130f322cb7e	1821	return (1UL); /* Reload value impossible */
mbed_official	159:7130f322cb7e	1822	}
mbed_official	159:7130f322cb7e	1823
mbed_official	159:7130f322cb7e	1824	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
mbed_official	159:7130f322cb7e	1825	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
mbed_official	159:7130f322cb7e	1826	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
mbed_official	159:7130f322cb7e	1827	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
mbed_official	159:7130f322cb7e	1828	SysTick_CTRL_TICKINT_Msk \|
mbed_official	159:7130f322cb7e	1829	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mbed_official	159:7130f322cb7e	1830	return (0UL); /* Function successful */
mbed_official	159:7130f322cb7e	1831	}
mbed_official	159:7130f322cb7e	1832
mbed_official	159:7130f322cb7e	1833	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
mbed_official	159:7130f322cb7e	1834	/**
mbed_official	159:7130f322cb7e	1835	\brief System Tick Configuration (non-secure)
mbed_official	159:7130f322cb7e	1836	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
mbed_official	159:7130f322cb7e	1837	Counter is in free running mode to generate periodic interrupts.
mbed_official	159:7130f322cb7e	1838	\param [in] ticks Number of ticks between two interrupts.
mbed_official	159:7130f322cb7e	1839	\return 0 Function succeeded.
mbed_official	159:7130f322cb7e	1840	\return 1 Function failed.
mbed_official	159:7130f322cb7e	1841	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mbed_official	159:7130f322cb7e	1842	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
mbed_official	159:7130f322cb7e	1843	must contain a vendor-specific implementation of this function.
mbed_official	159:7130f322cb7e	1844
mbed_official	159:7130f322cb7e	1845	*/
mbed_official	159:7130f322cb7e	1846	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
mbed_official	159:7130f322cb7e	1847	{
mbed_official	159:7130f322cb7e	1848	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
mbed_official	159:7130f322cb7e	1849	{
mbed_official	159:7130f322cb7e	1850	return (1UL); /* Reload value impossible */
mbed_official	159:7130f322cb7e	1851	}
mbed_official	159:7130f322cb7e	1852
mbed_official	159:7130f322cb7e	1853	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
mbed_official	159:7130f322cb7e	1854	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
mbed_official	159:7130f322cb7e	1855	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
mbed_official	159:7130f322cb7e	1856	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
mbed_official	159:7130f322cb7e	1857	SysTick_CTRL_TICKINT_Msk \|
mbed_official	159:7130f322cb7e	1858	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mbed_official	159:7130f322cb7e	1859	return (0UL); /* Function successful */
mbed_official	159:7130f322cb7e	1860	}
mbed_official	159:7130f322cb7e	1861	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
mbed_official	159:7130f322cb7e	1862
mbed_official	159:7130f322cb7e	1863	#endif
mbed_official	159:7130f322cb7e	1864
mbed_official	159:7130f322cb7e	1865	/@} end of CMSIS_Core_SysTickFunctions /
mbed_official	159:7130f322cb7e	1866
mbed_official	159:7130f322cb7e	1867
mbed_official	159:7130f322cb7e	1868
mbed_official	159:7130f322cb7e	1869
mbed_official	159:7130f322cb7e	1870	#ifdef __cplusplus
mbed_official	159:7130f322cb7e	1871	}
mbed_official	159:7130f322cb7e	1872	#endif
mbed_official	159:7130f322cb7e	1873
mbed_official	159:7130f322cb7e	1874	#endif /* __CORE_CM23_H_DEPENDANT */
mbed_official	159:7130f322cb7e	1875
mbed_official	159:7130f322cb7e	1876	#endif /* __CMSIS_GENERIC */